/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5585 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 5586 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f051x8.h | 5616 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 5617 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f071xb.h | 6169 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6170 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f042x6.h | 9391 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9392 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f048xx.h | 9355 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9356 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f072xb.h | 9966 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9967 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f091xc.h | 10623 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 10624 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f098xx.h | 10590 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 10591 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f078xx.h | 9936 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9937 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6142 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6143 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l062xx.h | 6279 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6280 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l053xx.h | 6301 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6302 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l072xx.h | 6438 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6439 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l073xx.h | 6597 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6598 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l083xx.h | 6734 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6735 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l063xx.h | 6436 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6437 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32l082xx.h | 6575 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 6576 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7403 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 7404 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32f318xx.h | 7390 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 7391 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9286 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9287 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8625 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 8626 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32u083xx.h | 9562 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 9563 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8056 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 8057 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7884 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 7885 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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D | stm32wb15xx.h | 8056 #define TSC_IOASCR_G2_IO1_Pos (4U) macro 8057 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
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