/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5579 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 5580 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f051x8.h | 5610 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 5611 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f071xb.h | 6163 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6164 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f042x6.h | 9385 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9386 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f048xx.h | 9349 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9350 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f072xb.h | 9960 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9961 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f091xc.h | 10617 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 10618 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f098xx.h | 10584 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 10585 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f078xx.h | 9930 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9931 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6136 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6137 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l062xx.h | 6273 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6274 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l053xx.h | 6295 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6296 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l072xx.h | 6432 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6433 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l073xx.h | 6591 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6592 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l083xx.h | 6728 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6729 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l063xx.h | 6430 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6431 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32l082xx.h | 6569 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 6570 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7397 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 7398 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32f318xx.h | 7384 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 7385 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9280 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9281 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8619 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 8620 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32u083xx.h | 9556 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 9557 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8050 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 8051 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7878 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 7879 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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D | stm32wb15xx.h | 8050 #define TSC_IOASCR_G1_IO3_Pos (2U) macro 8051 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
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