/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5576 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 5577 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f051x8.h | 5607 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 5608 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f071xb.h | 6160 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6161 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f042x6.h | 9382 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9383 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f048xx.h | 9346 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9347 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f072xb.h | 9957 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9958 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f091xc.h | 10614 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 10615 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f098xx.h | 10581 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 10582 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f078xx.h | 9927 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9928 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6133 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6134 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l062xx.h | 6270 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6271 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l053xx.h | 6292 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6293 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l072xx.h | 6429 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6430 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l073xx.h | 6588 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6589 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l083xx.h | 6725 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6726 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l063xx.h | 6427 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6428 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32l082xx.h | 6566 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 6567 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7394 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 7395 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32f318xx.h | 7381 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 7382 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9277 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9278 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32u0xx/soc/ |
D | stm32u031xx.h | 8616 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 8617 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32u083xx.h | 9553 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 9554 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8047 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 8048 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7875 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 7876 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|
D | stm32wb15xx.h | 8047 #define TSC_IOASCR_G1_IO2_Pos (1U) macro 8048 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
|