TIM_DCR_DBA_4 (reference) in projects: hal_stm32-latest

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Searched refs:TIM_DCR_DBA_4 (Results 1 – 25 of 300) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_ll_tim.h	1227 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1228 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1229 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1230 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1231 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1232 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1233 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1234 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1235 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1236 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … [all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
D	stm32u0xx_ll_tim.h	1165 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1166 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1167 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1168 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1169 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1170 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1171 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1172 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … 1173 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) …
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_ll_tim.h	1359 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1360 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1361 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1362 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1363 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1364 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1365 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1366 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1367 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1368 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … [all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_ll_tim.h	1374 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1375 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1376 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1377 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1378 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1379 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1380 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1381 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1382 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1383 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … [all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
D	stm32g4xx_ll_tim.h	1389 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1390 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1391 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1392 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1393 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1394 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1395 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1396 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1397 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1398 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … [all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
D	stm32n6xx_ll_tim.h	1299 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1300 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1301 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1302 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1303 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1304 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1305 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1306 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1307 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1308 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
D	stm32h7rsxx_ll_tim.h	1267 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1268 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1269 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) … 1270 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) … 1271 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1272 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1273 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1274 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1275 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1276 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
D	stm32g0xx_ll_tim.h	1175 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1176 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1177 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1178 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1179 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1180 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1181 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1182 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … 1183 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) …
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
D	stm32wb0x_ll_tim.h	1069 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1070 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1071 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1072 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1073 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1074 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1075 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1076 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
D	stm32wbxx_ll_tim.h	1172 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1173 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1174 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1175 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1176 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1177 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1178 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1179 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
D	stm32f7xx_ll_tim.h	1091 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1092 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1093 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1094 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1095 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1096 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1098 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1099 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
D	stm32c0xx_ll_tim.h	1153 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1154 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1155 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1156 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1157 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1158 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1159 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … 1160 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) …
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
D	stm32wlxx_ll_tim.h	1142 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1143 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1144 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1145 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1146 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1147 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1148 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1149 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_ll_tim.h	1123 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1124 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1125 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1126 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1127 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1128 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1129 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1130 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_ll_tim.h	1198 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1199 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1200 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1201 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1202 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1204 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1205 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … 1207 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) …
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_ll_tim.h	1112 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1113 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1114 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1115 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1116 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1117 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1118 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) … 1119 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) …
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_ll_tim.h	1163 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1164 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1165 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1166 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1167 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1168 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM… 1169 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3) … 1170 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) …
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
D	stm32f3xx_ll_tim.h	1119 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 1120 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) … 1121 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) … 1123 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) … 1124 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) … 1125 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM…
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
D	stm32l0xx_ll_tim.h	`637 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 638 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) …`
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
D	stm32l1xx_ll_tim.h	`633 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 634 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) …`
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
D	stm32f0xx_ll_tim.h	`888 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 889 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) …`
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
D	stm32f2xx_ll_tim.h	`891 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 892 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) …`
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
D	stm32f1xx_ll_tim.h	`884 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 885 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) …`
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
D	stm32f4xx_ll_tim.h	`891 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 … 892 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) …`
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
D	stm32f101x6.h	`4103 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /!< 0x00000010 / macro`

12 3 4 5 6 7 8 9 10 >>...12

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