1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32U0xx_LL_TIM_H
21 #define __STM32U0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u0xx.h"
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM6) \
38 || defined (TIM7) \
39 || defined (TIM15) \
40 || defined (TIM16)
41
42 /** @defgroup TIM_LL TIM
43 * @{
44 */
45
46 /* Private types -------------------------------------------------------------*/
47 /* Private variables ---------------------------------------------------------*/
48 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
49 * @{
50 */
51 static const uint8_t OFFSET_TAB_CCMRx[] =
52 {
53 0x00U, /* 0: TIMx_CH1 */
54 0x00U, /* 1: TIMx_CH1N */
55 0x00U, /* 2: TIMx_CH2 */
56 0x00U, /* 3: TIMx_CH2N */
57 0x04U, /* 4: TIMx_CH3 */
58 0x04U, /* 5: TIMx_CH3N */
59 0x04U, /* 6: TIMx_CH4 */
60 0x3CU, /* 7: TIMx_CH5 */
61 0x3CU /* 8: TIMx_CH6 */
62 };
63
64 static const uint8_t SHIFT_TAB_OCxx[] =
65 {
66 0U, /* 0: OC1M, OC1FE, OC1PE */
67 0U, /* 1: - NA */
68 8U, /* 2: OC2M, OC2FE, OC2PE */
69 0U, /* 3: - NA */
70 0U, /* 4: OC3M, OC3FE, OC3PE */
71 0U, /* 5: - NA */
72 8U, /* 6: OC4M, OC4FE, OC4PE */
73 0U, /* 7: OC5M, OC5FE, OC5PE */
74 8U /* 8: OC6M, OC6FE, OC6PE */
75 };
76
77 static const uint8_t SHIFT_TAB_ICxx[] =
78 {
79 0U, /* 0: CC1S, IC1PSC, IC1F */
80 0U, /* 1: - NA */
81 8U, /* 2: CC2S, IC2PSC, IC2F */
82 0U, /* 3: - NA */
83 0U, /* 4: CC3S, IC3PSC, IC3F */
84 0U, /* 5: - NA */
85 8U, /* 6: CC4S, IC4PSC, IC4F */
86 0U, /* 7: - NA */
87 0U /* 8: - NA */
88 };
89
90 static const uint8_t SHIFT_TAB_CCxP[] =
91 {
92 0U, /* 0: CC1P */
93 2U, /* 1: CC1NP */
94 4U, /* 2: CC2P */
95 6U, /* 3: CC2NP */
96 8U, /* 4: CC3P */
97 10U, /* 5: CC3NP */
98 12U, /* 6: CC4P */
99 16U, /* 7: CC5P */
100 20U /* 8: CC6P */
101 };
102
103 static const uint8_t SHIFT_TAB_OISx[] =
104 {
105 0U, /* 0: OIS1 */
106 1U, /* 1: OIS1N */
107 2U, /* 2: OIS2 */
108 3U, /* 3: OIS2N */
109 4U, /* 4: OIS3 */
110 5U, /* 5: OIS3N */
111 6U, /* 6: OIS4 */
112 8U, /* 7: OIS5 */
113 10U /* 8: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 #define OCREF_CLEAR_SELECT_Pos (16U)
152 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
153 /**
154 * @}
155 */
156
157 /* Private macros ------------------------------------------------------------*/
158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
159 * @{
160 */
161 /** @brief Convert channel id into channel index.
162 * @param __CHANNEL__ This parameter can be one of the following values:
163 * @arg @ref LL_TIM_CHANNEL_CH1
164 * @arg @ref LL_TIM_CHANNEL_CH1N
165 * @arg @ref LL_TIM_CHANNEL_CH2
166 * @arg @ref LL_TIM_CHANNEL_CH2N
167 * @arg @ref LL_TIM_CHANNEL_CH3
168 * @arg @ref LL_TIM_CHANNEL_CH3N
169 * @arg @ref LL_TIM_CHANNEL_CH4
170 * @arg @ref LL_TIM_CHANNEL_CH5
171 * @arg @ref LL_TIM_CHANNEL_CH6
172 * @retval none
173 */
174 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
175 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
183
184 /** @brief Calculate the deadtime sampling period(in ps).
185 * @param __TIMCLK__ timer input clock frequency (in Hz).
186 * @param __CKD__ This parameter can be one of the following values:
187 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
190 * @retval none
191 */
192 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
193 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
194 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
195 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
196 /**
197 * @}
198 */
199
200
201 /* Exported types ------------------------------------------------------------*/
202 #if defined(USE_FULL_LL_DRIVER)
203 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
204 * @{
205 */
206
207 /**
208 * @brief TIM Time Base configuration structure definition.
209 */
210 typedef struct
211 {
212 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
213 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
214
215 This feature can be modified afterwards using unitary function
216 @ref LL_TIM_SetPrescaler().*/
217
218 uint32_t CounterMode; /*!< Specifies the counter mode.
219 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
220
221 This feature can be modified afterwards using unitary function
222 @ref LL_TIM_SetCounterMode().*/
223
224 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
225 Auto-Reload Register at the next update event.
226 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
227 Some timer instances may support 32 bits counters. In that case this parameter must
228 be a number between 0x0000 and 0xFFFFFFFF.
229
230 This feature can be modified afterwards using unitary function
231 @ref LL_TIM_SetAutoReload().*/
232
233 uint32_t ClockDivision; /*!< Specifies the clock division.
234 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
235
236 This feature can be modified afterwards using unitary function
237 @ref LL_TIM_SetClockDivision().*/
238
239 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
240 reaches zero, an update event is generated and counting restarts
241 from the RCR value (N).
242 This means in PWM mode that (N+1) corresponds to:
243 - the number of PWM periods in edge-aligned mode
244 - the number of half PWM period in center-aligned mode
245 GP timers: this parameter must be a number between Min_Data = 0x00 and
246 Max_Data = 0xFF.
247 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
248 Max_Data = 0xFFFF.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_SetRepetitionCounter().*/
252 } LL_TIM_InitTypeDef;
253
254 /**
255 * @brief TIM Output Compare configuration structure definition.
256 */
257 typedef struct
258 {
259 uint32_t OCMode; /*!< Specifies the output mode.
260 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
261
262 This feature can be modified afterwards using unitary function
263 @ref LL_TIM_OC_SetMode().*/
264
265 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
266 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
267
268 This feature can be modified afterwards using unitary functions
269 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
270
271 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
272 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
273
274 This feature can be modified afterwards using unitary functions
275 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
276
277 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
278 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
279
280 This feature can be modified afterwards using unitary function
281 LL_TIM_OC_SetCompareCHx (x=1..6).*/
282
283 uint32_t OCPolarity; /*!< Specifies the output polarity.
284 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
285
286 This feature can be modified afterwards using unitary function
287 @ref LL_TIM_OC_SetPolarity().*/
288
289 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
290 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_OC_SetPolarity().*/
294
295
296 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
297 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetIdleState().*/
301
302 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
303 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetIdleState().*/
307 } LL_TIM_OC_InitTypeDef;
308
309 /**
310 * @brief TIM Input Capture configuration structure definition.
311 */
312
313 typedef struct
314 {
315
316 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
317 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_IC_SetPolarity().*/
321
322 uint32_t ICActiveInput; /*!< Specifies the input.
323 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetActiveInput().*/
327
328 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
329 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetPrescaler().*/
333
334 uint32_t ICFilter; /*!< Specifies the input capture filter.
335 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
336
337 This feature can be modified afterwards using unitary function
338 @ref LL_TIM_IC_SetFilter().*/
339 } LL_TIM_IC_InitTypeDef;
340
341
342 /**
343 * @brief TIM Encoder interface configuration structure definition.
344 */
345 typedef struct
346 {
347 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
348 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_SetEncoderMode().*/
352
353 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
354 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_IC_SetPolarity().*/
358
359 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
360 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetActiveInput().*/
364
365 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
366 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetPrescaler().*/
370
371 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
372 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetFilter().*/
376
377 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
378 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetPolarity().*/
382
383 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
384 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetActiveInput().*/
388
389 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
390 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetPrescaler().*/
394
395 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
396 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
397
398 This feature can be modified afterwards using unitary function
399 @ref LL_TIM_IC_SetFilter().*/
400
401 } LL_TIM_ENCODER_InitTypeDef;
402
403 /**
404 * @brief TIM Hall sensor interface configuration structure definition.
405 */
406 typedef struct
407 {
408
409 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
410 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
411
412 This feature can be modified afterwards using unitary function
413 @ref LL_TIM_IC_SetPolarity().*/
414
415 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
416 Prescaler must be set to get a maximum counter period longer than the
417 time interval between 2 consecutive changes on the Hall inputs.
418 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetPrescaler().*/
422
423 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
424 This parameter can be a value of
425 @ref TIM_LL_EC_IC_FILTER.
426
427 This feature can be modified afterwards using unitary function
428 @ref LL_TIM_IC_SetFilter().*/
429
430 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
431 A positive pulse (TRGO event) is generated with a programmable delay every time
432 a change occurs on the Hall inputs.
433 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_OC_SetCompareCH2().*/
437 } LL_TIM_HALLSENSOR_InitTypeDef;
438
439 /**
440 * @brief BDTR (Break and Dead Time) structure definition
441 */
442 typedef struct
443 {
444 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
445 This parameter can be a value of @ref TIM_LL_EC_OSSR
446
447 This feature can be modified afterwards using unitary function
448 @ref LL_TIM_SetOffStates()
449
450 @note This bit-field cannot be modified as long as LOCK level 2 has been
451 programmed. */
452
453 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
454 This parameter can be a value of @ref TIM_LL_EC_OSSI
455
456 This feature can be modified afterwards using unitary function
457 @ref LL_TIM_SetOffStates()
458
459 @note This bit-field cannot be modified as long as LOCK level 2 has been
460 programmed. */
461
462 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
463 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
464
465 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
466 register has been written, their content is frozen until the next reset.*/
467
468 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
469 switching-on of the outputs.
470 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
471
472 This feature can be modified afterwards using unitary function
473 @ref LL_TIM_OC_SetDeadTime()
474
475 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
476 programmed. */
477
478 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
479 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
480
481 This feature can be modified afterwards using unitary functions
482 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
483
484 @note This bit-field can not be modified as long as LOCK level 1 has been
485 programmed. */
486
487 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
488 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
489
490 This feature can be modified afterwards using unitary function
491 @ref LL_TIM_ConfigBRK()
492
493 @note This bit-field can not be modified as long as LOCK level 1 has been
494 programmed. */
495
496 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
497 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
498
499 This feature can be modified afterwards using unitary function
500 @ref LL_TIM_ConfigBRK()
501
502 @note This bit-field can not be modified as long as LOCK level 1 has been
503 programmed. */
504
505 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
506 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
507
508 This feature can be modified afterwards using unitary functions
509 @ref LL_TIM_ConfigBRK()
510
511 @note Bidirectional break input is only supported by advanced timers instances.
512
513 @note This bit-field can not be modified as long as LOCK level 1 has been
514 programmed. */
515
516 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
518
519 This feature can be modified afterwards using unitary functions
520 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
526 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
527
528 This feature can be modified afterwards using unitary function
529 @ref LL_TIM_ConfigBRK2()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533
534 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
536
537 This feature can be modified afterwards using unitary function
538 @ref LL_TIM_ConfigBRK2()
539
540 @note This bit-field can not be modified as long as LOCK level 1 has been
541 programmed. */
542
543 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
544 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
545
546 This feature can be modified afterwards using unitary functions
547 @ref LL_TIM_ConfigBRK2()
548
549 @note Bidirectional break input is only supported by advanced timers instances.
550
551 @note This bit-field can not be modified as long as LOCK level 1 has been
552 programmed. */
553
554 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
555 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
556
557 This feature can be modified afterwards using unitary functions
558 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
559
560 @note This bit-field can not be modified as long as LOCK level 1 has been
561 programmed. */
562 } LL_TIM_BDTR_InitTypeDef;
563
564 /**
565 * @}
566 */
567 #endif /* USE_FULL_LL_DRIVER */
568
569 /* Exported constants --------------------------------------------------------*/
570 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
571 * @{
572 */
573
574 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
575 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
576 * @{
577 */
578 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
579 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
580 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
581 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
582 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
583 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
584 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
585 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
586 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
587 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
588 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
589 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
590 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
591 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
592 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
593 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
594 /**
595 * @}
596 */
597
598 #if defined(USE_FULL_LL_DRIVER)
599 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
600 * @{
601 */
602 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
603 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
604 /**
605 * @}
606 */
607
608 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
609 * @{
610 */
611 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
612 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
613 /**
614 * @}
615 */
616
617 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
618 * @{
619 */
620 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
621 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
622 /**
623 * @}
624 */
625 #endif /* USE_FULL_LL_DRIVER */
626
627 /** @defgroup TIM_LL_EC_IT IT Defines
628 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
629 * @{
630 */
631 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
632 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
633 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
634 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
635 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
636 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
637 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
638 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
644 * @{
645 */
646 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
647 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
648 /**
649 * @}
650 */
651
652 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
653 * @{
654 */
655 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
656 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
657 /**
658 * @}
659 */
660
661 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
662 * @{
663 */
664 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
665 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
666 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
667 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
668 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
674 * @{
675 */
676 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
677 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
678 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
684 * @{
685 */
686 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
687 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
693 * @{
694 */
695 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
696 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
697 /**
698 * @}
699 */
700
701 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
702 * @{
703 */
704 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
705 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
706 /**
707 * @}
708 */
709
710 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
711 * @{
712 */
713 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
714 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
715 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
716 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_LL_EC_CHANNEL Channel
722 * @{
723 */
724 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
725 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
726 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
727 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
728 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
729 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
730 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
731 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
732 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
733 /**
734 * @}
735 */
736
737 #if defined(USE_FULL_LL_DRIVER)
738 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
739 * @{
740 */
741 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
742 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
743 /**
744 * @}
745 */
746 #endif /* USE_FULL_LL_DRIVER */
747
748 /** Legacy definitions for compatibility purpose
749 @cond 0
750 */
751 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
752 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
753 /**
754 @endcond
755 */
756
757 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
758 * @{
759 */
760 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
761 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
762 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
763 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
764 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
765 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
766 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
767 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
768 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
769 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
770 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
771 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
772 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
773 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
774 /**
775 * @}
776 */
777
778 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
779 * @{
780 */
781 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
782 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
783 /**
784 * @}
785 */
786
787 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
788 * @{
789 */
790 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
791 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
792 /**
793 * @}
794 */
795
796 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
797 * @{
798 */
799 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
800 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
801 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
802 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
803 /**
804 * @}
805 */
806
807 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
808 * @{
809 */
810 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
811 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
812 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
813 /**
814 * @}
815 */
816
817 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
818 * @{
819 */
820 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
821 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
822 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
823 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
824 /**
825 * @}
826 */
827
828 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
829 * @{
830 */
831 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
832 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
833 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
834 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
835 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
836 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
837 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
838 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
839 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
842 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
843 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
844 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
845 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
846 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
847 /**
848 * @}
849 */
850
851 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
852 * @{
853 */
854 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
855 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
856 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
857 /**
858 * @}
859 */
860
861 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
862 * @{
863 */
864 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
865 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
866 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
867 /**
868 * @}
869 */
870
871 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
872 * @{
873 */
874 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
875 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
876 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
877 /**
878 * @}
879 */
880
881 /** @defgroup TIM_LL_EC_TRGO Trigger Output
882 * @{
883 */
884 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
885 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
886 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
887 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
888 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
889 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
890 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
891 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
892 /**
893 * @}
894 */
895
896 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
897 * @{
898 */
899 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
900 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
901 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
902 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
912 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
913 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
915 /**
916 * @}
917 */
918
919 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
920 * @{
921 */
922 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
923 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
924 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
925 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
926 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
927 /**
928 * @}
929 */
930
931 /** @defgroup TIM_LL_EC_TS Trigger Selection
932 * @{
933 */
934 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
935 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
936 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
937 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
938 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
939 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
940 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
941 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
942 /**
943 * @}
944 */
945
946 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
947 * @{
948 */
949 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
950 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
951 /**
952 * @}
953 */
954
955 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
956 * @{
957 */
958 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
959 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
960 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
961 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
962 /**
963 * @}
964 */
965
966 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
967 * @{
968 */
969 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
970 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
971 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
972 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
973 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
974 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
975 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
976 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
977 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
979 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
980 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
981 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
982 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
983 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
984 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
985 /**
986 * @}
987 */
988
989 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
990 * @{
991 */
992 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
993 #define LL_TIM_ETRSOURCE_COMP1 TIM_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
994 #if defined(COMP2)
995 #define LL_TIM_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
996 #endif /* COMP2 */
997 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
998 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
999 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
1000 #define LL_TIM_ETRSOURCE_LSE (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1001 #define LL_TIM_ETRSOURCE_MCO TIM_AF1_ETRSEL_2 /*!< ETR input is connected to MCO */
1002 #define LL_TIM_ETRSOURCE_MCO2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1008 * @{
1009 */
1010 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1011 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1017 * @{
1018 */
1019 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1020 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1021 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1022 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1023 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1024 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1025 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1026 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1027 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1028 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1029 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1030 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1031 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1032 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1033 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1034 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1040 * @{
1041 */
1042 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1043 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1049 * @{
1050 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1052 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1065 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1066 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup TIM_LL_EC_OSSI OSSI
1072 * @{
1073 */
1074 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1075 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1076 /**
1077 * @}
1078 */
1079
1080 /** @defgroup TIM_LL_EC_OSSR OSSR
1081 * @{
1082 */
1083 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1084 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1090 * @{
1091 */
1092 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1093 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1094 /**
1095 * @}
1096 */
1097
1098 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1099 * @{
1100 */
1101 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1102 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1103 #if defined(COMP2)
1104 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1105 #endif /* COMP2 */
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1111 * @{
1112 */
1113 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1114 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1120 * @{
1121 */
1122 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1123 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1124 /**
1125 * @}
1126 */
1127
1128 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1129 * @{
1130 */
1131 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1132 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1133 /**
1134 * @}
1135 */
1136
1137 /** Legacy definitions for compatibility purpose
1138 @cond 0
1139 */
1140 #define LL_TIM_ReArmBRK(_PARAM_)
1141 #define LL_TIM_ReArmBRK2(_PARAM_)
1142 /**
1143 @endcond
1144 */
1145
1146 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1147 * @{
1148 */
1149 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1155 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1156 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1162 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1163 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1164 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1165 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1166 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1167 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1168 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1169 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1170 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1171 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1172 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1173 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1174 /**
1175 * @}
1176 */
1177
1178 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1179 * @{
1180 */
1181 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1182 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1183 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1184 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1185 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1186 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1187 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1188 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1189 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1190 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1191 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1192 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1193 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1194 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1195 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1196 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1197 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1198 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1199 /**
1200 * @}
1201 */
1202
1203 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1204 * @{
1205 */
1206 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1207 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1208 /**
1209 * @}
1210 */
1211
1212 /** @defgroup TIM_LL_EC_TIM1_TI2_RMP TIM1 Timer Input Ch2 Remap
1213 * @{
1214 */
1215 #define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /*!< TIM1 input 2 is connected to GPIO */
1216 #if defined(COMP2)
1217 #define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM1 input 2 is connected to COMP2_OUT */
1218 #endif /* COMP2 */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1224 * @{
1225 */
1226 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1227 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1233 * @{
1234 */
1235 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1236 #if defined(COMP2)
1237 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP2_OUT */
1238 #endif /* COMP2 */
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1244 * @{
1245 */
1246 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1247 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1253 * @{
1254 */
1255 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1256 #if defined(COMP2)
1257 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP2_OUT */
1258 #endif /* COMP2 */
1259 /**
1260 * @}
1261 */
1262
1263 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1264 * @{
1265 */
1266 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1267 #define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 input 1 */
1268 #define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 input 1 */
1269 /**
1270 * @}
1271 */
1272
1273 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1274 * @{
1275 */
1276 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1277 #define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to TIM2 input 2 */
1278 #define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3 input 2 */
1279 /**
1280 * @}
1281 */
1282
1283 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1284 * @{
1285 */
1286 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1287 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to LSI */
1288 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to LSE */
1289 #define LL_TIM_TIM16_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1290 #define LL_TIM_TIM16_TI1_RMP_MCO2 TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to MCO2 */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1296 * @{
1297 */
1298 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1299 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1300 #if defined(COMP2)
1301 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM_OR1_OCREF_CLR /*!< OCREF clear input is connected to COMP2_OUT */
1302 #endif /* COMP2 */
1303 /**
1304 * @}
1305 */
1306
1307 /** Legacy definitions for compatibility purpose
1308 @cond 0
1309 */
1310 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1311 /**
1312 @endcond
1313 */
1314
1315 /**
1316 * @}
1317 */
1318
1319 /* Exported macro ------------------------------------------------------------*/
1320 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1321 * @{
1322 */
1323
1324 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1325 * @{
1326 */
1327 /**
1328 * @brief Write a value in TIM register.
1329 * @param __INSTANCE__ TIM Instance
1330 * @param __REG__ Register to be written
1331 * @param __VALUE__ Value to be written in the register
1332 * @retval None
1333 */
1334 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1335
1336 /**
1337 * @brief Read a value in TIM register.
1338 * @param __INSTANCE__ TIM Instance
1339 * @param __REG__ Register to be read
1340 * @retval Register value
1341 */
1342 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1343 /**
1344 * @}
1345 */
1346
1347 /**
1348 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1349 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1350 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1351 * to TIMx_CNT register bit 31)
1352 * @param __CNT__ Counter value
1353 * @retval UIF status bit
1354 */
1355 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1356 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1357
1358 /**
1359 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1360 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1361 * @param __TIMCLK__ timer input clock frequency (in Hz)
1362 * @param __CKD__ This parameter can be one of the following values:
1363 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1364 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1365 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1366 * @param __DT__ deadtime duration (in ns)
1367 * @retval DTG[0:7]
1368 */
1369 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1370 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1371 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1372 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1373 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1374 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1375 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1376 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1377 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1378 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1379 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1380 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1381 0U)
1382
1383 /**
1384 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1385 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1386 * @param __TIMCLK__ timer input clock frequency (in Hz)
1387 * @param __CNTCLK__ counter clock frequency (in Hz)
1388 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1389 */
1390 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1391 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1392
1393 /**
1394 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1395 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1396 * @param __TIMCLK__ timer input clock frequency (in Hz)
1397 * @param __PSC__ prescaler
1398 * @param __FREQ__ output signal frequency (in Hz)
1399 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1400 */
1401 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1402 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1403
1404 /**
1405 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1406 * active/inactive delay.
1407 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1408 * @param __TIMCLK__ timer input clock frequency (in Hz)
1409 * @param __PSC__ prescaler
1410 * @param __DELAY__ timer output compare active/inactive delay (in us)
1411 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1412 */
1413 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1414 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1415 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1416
1417 /**
1418 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1419 * (when the timer operates in one pulse mode).
1420 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1421 * @param __TIMCLK__ timer input clock frequency (in Hz)
1422 * @param __PSC__ prescaler
1423 * @param __DELAY__ timer output compare active/inactive delay (in us)
1424 * @param __PULSE__ pulse duration (in us)
1425 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1426 */
1427 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1428 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1429 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1430
1431 /**
1432 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1433 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1434 * @param __ICPSC__ This parameter can be one of the following values:
1435 * @arg @ref LL_TIM_ICPSC_DIV1
1436 * @arg @ref LL_TIM_ICPSC_DIV2
1437 * @arg @ref LL_TIM_ICPSC_DIV4
1438 * @arg @ref LL_TIM_ICPSC_DIV8
1439 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1440 */
1441 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1442 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1443
1444
1445 /**
1446 * @}
1447 */
1448
1449 /* Exported functions --------------------------------------------------------*/
1450 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1451 * @{
1452 */
1453
1454 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1455 * @{
1456 */
1457 /**
1458 * @brief Enable timer counter.
1459 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1460 * @param TIMx Timer instance
1461 * @retval None
1462 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1463 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1464 {
1465 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1466 }
1467
1468 /**
1469 * @brief Disable timer counter.
1470 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1471 * @param TIMx Timer instance
1472 * @retval None
1473 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1474 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1475 {
1476 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1477 }
1478
1479 /**
1480 * @brief Indicates whether the timer counter is enabled.
1481 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1482 * @param TIMx Timer instance
1483 * @retval State of bit (1 or 0).
1484 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1485 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1486 {
1487 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1488 }
1489
1490 /**
1491 * @brief Enable update event generation.
1492 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1493 * @param TIMx Timer instance
1494 * @retval None
1495 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1496 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1497 {
1498 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1499 }
1500
1501 /**
1502 * @brief Disable update event generation.
1503 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1504 * @param TIMx Timer instance
1505 * @retval None
1506 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1507 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1508 {
1509 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1510 }
1511
1512 /**
1513 * @brief Indicates whether update event generation is enabled.
1514 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1515 * @param TIMx Timer instance
1516 * @retval Inverted state of bit (0 or 1).
1517 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1519 {
1520 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1521 }
1522
1523 /**
1524 * @brief Set update event source
1525 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1526 * generate an update interrupt or DMA request if enabled:
1527 * - Counter overflow/underflow
1528 * - Setting the UG bit
1529 * - Update generation through the slave mode controller
1530 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1531 * overflow/underflow generates an update interrupt or DMA request if enabled.
1532 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1533 * @param TIMx Timer instance
1534 * @param UpdateSource This parameter can be one of the following values:
1535 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1536 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1537 * @retval None
1538 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1539 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1540 {
1541 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1542 }
1543
1544 /**
1545 * @brief Get actual event update source
1546 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1547 * @param TIMx Timer instance
1548 * @retval Returned value can be one of the following values:
1549 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1550 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1551 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1552 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1553 {
1554 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1555 }
1556
1557 /**
1558 * @brief Set one pulse mode (one shot v.s. repetitive).
1559 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1560 * @param TIMx Timer instance
1561 * @param OnePulseMode This parameter can be one of the following values:
1562 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1563 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1564 * @retval None
1565 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1566 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1567 {
1568 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1569 }
1570
1571 /**
1572 * @brief Get actual one pulse mode.
1573 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1574 * @param TIMx Timer instance
1575 * @retval Returned value can be one of the following values:
1576 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1577 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1578 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1579 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1580 {
1581 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1582 }
1583
1584 /**
1585 * @brief Set the timer counter counting mode.
1586 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1587 * check whether or not the counter mode selection feature is supported
1588 * by a timer instance.
1589 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1590 * requires a timer reset to avoid unexpected direction
1591 * due to DIR bit readonly in center aligned mode.
1592 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1593 * CR1 CMS LL_TIM_SetCounterMode
1594 * @param TIMx Timer instance
1595 * @param CounterMode This parameter can be one of the following values:
1596 * @arg @ref LL_TIM_COUNTERMODE_UP
1597 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1598 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1599 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1600 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1601 * @retval None
1602 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1603 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1604 {
1605 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1606 }
1607
1608 /**
1609 * @brief Get actual counter mode.
1610 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1611 * check whether or not the counter mode selection feature is supported
1612 * by a timer instance.
1613 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1614 * CR1 CMS LL_TIM_GetCounterMode
1615 * @param TIMx Timer instance
1616 * @retval Returned value can be one of the following values:
1617 * @arg @ref LL_TIM_COUNTERMODE_UP
1618 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1619 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1620 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1621 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1622 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1623 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1624 {
1625 uint32_t counter_mode;
1626
1627 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1628
1629 if (counter_mode == 0U)
1630 {
1631 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1632 }
1633
1634 return counter_mode;
1635 }
1636
1637 /**
1638 * @brief Enable auto-reload (ARR) preload.
1639 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1640 * @param TIMx Timer instance
1641 * @retval None
1642 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1643 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1644 {
1645 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1646 }
1647
1648 /**
1649 * @brief Disable auto-reload (ARR) preload.
1650 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1651 * @param TIMx Timer instance
1652 * @retval None
1653 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1654 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1655 {
1656 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1657 }
1658
1659 /**
1660 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1661 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1662 * @param TIMx Timer instance
1663 * @retval State of bit (1 or 0).
1664 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1665 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1666 {
1667 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1668 }
1669
1670 /**
1671 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1672 * (when supported) and the digital filters.
1673 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1674 * whether or not the clock division feature is supported by the timer
1675 * instance.
1676 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1677 * @param TIMx Timer instance
1678 * @param ClockDivision This parameter can be one of the following values:
1679 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1680 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1681 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1682 * @retval None
1683 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1684 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1685 {
1686 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1687 }
1688
1689 /**
1690 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1691 * generators (when supported) and the digital filters.
1692 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1693 * whether or not the clock division feature is supported by the timer
1694 * instance.
1695 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1696 * @param TIMx Timer instance
1697 * @retval Returned value can be one of the following values:
1698 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1699 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1700 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1701 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1702 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1703 {
1704 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1705 }
1706
1707 /**
1708 * @brief Set the counter value.
1709 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1710 * whether or not a timer instance supports a 32 bits counter.
1711 * @rmtoll CNT CNT LL_TIM_SetCounter
1712 * @param TIMx Timer instance
1713 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1714 * @retval None
1715 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1716 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1717 {
1718 WRITE_REG(TIMx->CNT, Counter);
1719 }
1720
1721 /**
1722 * @brief Get the counter value.
1723 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1724 * whether or not a timer instance supports a 32 bits counter.
1725 * @rmtoll CNT CNT LL_TIM_GetCounter
1726 * @param TIMx Timer instance
1727 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1728 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1729 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1730 {
1731 return (uint32_t)(READ_REG(TIMx->CNT));
1732 }
1733
1734 /**
1735 * @brief Get the current direction of the counter
1736 * @rmtoll CR1 DIR LL_TIM_GetDirection
1737 * @param TIMx Timer instance
1738 * @retval Returned value can be one of the following values:
1739 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1740 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1741 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1742 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1743 {
1744 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1745 }
1746
1747 /**
1748 * @brief Set the prescaler value.
1749 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1750 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1751 * prescaler ratio is taken into account at the next update event.
1752 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1753 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1754 * @param TIMx Timer instance
1755 * @param Prescaler between Min_Data=0 and Max_Data=65535
1756 * @retval None
1757 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1758 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1759 {
1760 WRITE_REG(TIMx->PSC, Prescaler);
1761 }
1762
1763 /**
1764 * @brief Get the prescaler value.
1765 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1766 * @param TIMx Timer instance
1767 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1768 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1769 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1770 {
1771 return (uint32_t)(READ_REG(TIMx->PSC));
1772 }
1773
1774 /**
1775 * @brief Set the auto-reload value.
1776 * @note The counter is blocked while the auto-reload value is null.
1777 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1778 * whether or not a timer instance supports a 32 bits counter.
1779 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1780 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1781 * @param TIMx Timer instance
1782 * @param AutoReload between Min_Data=0 and Max_Data=65535
1783 * @retval None
1784 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1785 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1786 {
1787 WRITE_REG(TIMx->ARR, AutoReload);
1788 }
1789
1790 /**
1791 * @brief Get the auto-reload value.
1792 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1793 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1794 * whether or not a timer instance supports a 32 bits counter.
1795 * @param TIMx Timer instance
1796 * @retval Auto-reload value
1797 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1798 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1799 {
1800 return (uint32_t)(READ_REG(TIMx->ARR));
1801 }
1802
1803 /**
1804 * @brief Set the repetition counter value.
1805 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1806 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1807 * whether or not a timer instance supports a repetition counter.
1808 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1809 * @param TIMx Timer instance
1810 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1811 * @retval None
1812 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1813 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1814 {
1815 WRITE_REG(TIMx->RCR, RepetitionCounter);
1816 }
1817
1818 /**
1819 * @brief Get the repetition counter value.
1820 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1821 * whether or not a timer instance supports a repetition counter.
1822 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1823 * @param TIMx Timer instance
1824 * @retval Repetition counter value
1825 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1826 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1827 {
1828 return (uint32_t)(READ_REG(TIMx->RCR));
1829 }
1830
1831 /**
1832 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1833 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1834 * in an atomic way.
1835 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1836 * @param TIMx Timer instance
1837 * @retval None
1838 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1839 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1840 {
1841 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1842 }
1843
1844 /**
1845 * @brief Disable update interrupt flag (UIF) remapping.
1846 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1847 * @param TIMx Timer instance
1848 * @retval None
1849 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1850 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1851 {
1852 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1853 }
1854
1855 /**
1856 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1857 * @param Counter Counter value
1858 * @retval State of bit (1 or 0).
1859 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1860 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1861 {
1862 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1863 }
1864
1865 /**
1866 * @}
1867 */
1868
1869 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1870 * @{
1871 */
1872 /**
1873 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1874 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1875 * they are updated only when a commutation event (COM) occurs.
1876 * @note Only on channels that have a complementary output.
1877 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1878 * whether or not a timer instance is able to generate a commutation event.
1879 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1880 * @param TIMx Timer instance
1881 * @retval None
1882 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1883 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1884 {
1885 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1886 }
1887
1888 /**
1889 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1890 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1891 * whether or not a timer instance is able to generate a commutation event.
1892 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1893 * @param TIMx Timer instance
1894 * @retval None
1895 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1896 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1897 {
1898 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1899 }
1900
1901 /**
1902 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1903 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1904 * @param TIMx Timer instance
1905 * @retval State of bit (1 or 0).
1906 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1907 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1908 {
1909 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1914 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1915 * whether or not a timer instance is able to generate a commutation event.
1916 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1917 * @param TIMx Timer instance
1918 * @param CCUpdateSource This parameter can be one of the following values:
1919 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1920 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1921 * @retval None
1922 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1923 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1924 {
1925 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1926 }
1927
1928 /**
1929 * @brief Set the trigger of the capture/compare DMA request.
1930 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1931 * @param TIMx Timer instance
1932 * @param DMAReqTrigger This parameter can be one of the following values:
1933 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1934 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1935 * @retval None
1936 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1937 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1938 {
1939 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1940 }
1941
1942 /**
1943 * @brief Get actual trigger of the capture/compare DMA request.
1944 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1945 * @param TIMx Timer instance
1946 * @retval Returned value can be one of the following values:
1947 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1948 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1949 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1950 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1951 {
1952 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1953 }
1954
1955 /**
1956 * @brief Set the lock level to freeze the
1957 * configuration of several capture/compare parameters.
1958 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1959 * the lock mechanism is supported by a timer instance.
1960 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1961 * @param TIMx Timer instance
1962 * @param LockLevel This parameter can be one of the following values:
1963 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1964 * @arg @ref LL_TIM_LOCKLEVEL_1
1965 * @arg @ref LL_TIM_LOCKLEVEL_2
1966 * @arg @ref LL_TIM_LOCKLEVEL_3
1967 * @retval None
1968 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1969 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1970 {
1971 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1972 }
1973
1974 /**
1975 * @brief Enable capture/compare channels.
1976 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1977 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1978 * CCER CC2E LL_TIM_CC_EnableChannel\n
1979 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1980 * CCER CC3E LL_TIM_CC_EnableChannel\n
1981 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1982 * CCER CC4E LL_TIM_CC_EnableChannel\n
1983 * CCER CC5E LL_TIM_CC_EnableChannel\n
1984 * CCER CC6E LL_TIM_CC_EnableChannel
1985 * @param TIMx Timer instance
1986 * @param Channels This parameter can be a combination of the following values:
1987 * @arg @ref LL_TIM_CHANNEL_CH1
1988 * @arg @ref LL_TIM_CHANNEL_CH1N
1989 * @arg @ref LL_TIM_CHANNEL_CH2
1990 * @arg @ref LL_TIM_CHANNEL_CH2N
1991 * @arg @ref LL_TIM_CHANNEL_CH3
1992 * @arg @ref LL_TIM_CHANNEL_CH3N
1993 * @arg @ref LL_TIM_CHANNEL_CH4
1994 * @arg @ref LL_TIM_CHANNEL_CH5
1995 * @arg @ref LL_TIM_CHANNEL_CH6
1996 * @retval None
1997 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1998 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1999 {
2000 SET_BIT(TIMx->CCER, Channels);
2001 }
2002
2003 /**
2004 * @brief Disable capture/compare channels.
2005 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2006 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2007 * CCER CC2E LL_TIM_CC_DisableChannel\n
2008 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2009 * CCER CC3E LL_TIM_CC_DisableChannel\n
2010 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2011 * CCER CC4E LL_TIM_CC_DisableChannel\n
2012 * CCER CC5E LL_TIM_CC_DisableChannel\n
2013 * CCER CC6E LL_TIM_CC_DisableChannel
2014 * @param TIMx Timer instance
2015 * @param Channels This parameter can be a combination of the following values:
2016 * @arg @ref LL_TIM_CHANNEL_CH1
2017 * @arg @ref LL_TIM_CHANNEL_CH1N
2018 * @arg @ref LL_TIM_CHANNEL_CH2
2019 * @arg @ref LL_TIM_CHANNEL_CH2N
2020 * @arg @ref LL_TIM_CHANNEL_CH3
2021 * @arg @ref LL_TIM_CHANNEL_CH3N
2022 * @arg @ref LL_TIM_CHANNEL_CH4
2023 * @arg @ref LL_TIM_CHANNEL_CH5
2024 * @arg @ref LL_TIM_CHANNEL_CH6
2025 * @retval None
2026 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2027 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2028 {
2029 CLEAR_BIT(TIMx->CCER, Channels);
2030 }
2031
2032 /**
2033 * @brief Indicate whether channel(s) is(are) enabled.
2034 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2035 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2036 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2037 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2038 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2039 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2040 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2041 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2042 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2043 * @param TIMx Timer instance
2044 * @param Channels This parameter can be a combination of the following values:
2045 * @arg @ref LL_TIM_CHANNEL_CH1
2046 * @arg @ref LL_TIM_CHANNEL_CH1N
2047 * @arg @ref LL_TIM_CHANNEL_CH2
2048 * @arg @ref LL_TIM_CHANNEL_CH2N
2049 * @arg @ref LL_TIM_CHANNEL_CH3
2050 * @arg @ref LL_TIM_CHANNEL_CH3N
2051 * @arg @ref LL_TIM_CHANNEL_CH4
2052 * @arg @ref LL_TIM_CHANNEL_CH5
2053 * @arg @ref LL_TIM_CHANNEL_CH6
2054 * @retval State of bit (1 or 0).
2055 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2056 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2057 {
2058 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2059 }
2060
2061 /**
2062 * @}
2063 */
2064
2065 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2066 * @{
2067 */
2068 /**
2069 * @brief Configure an output channel.
2070 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2071 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2072 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2073 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2074 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2075 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2076 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2077 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2078 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2079 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2080 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2081 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2082 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2083 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2084 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2085 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2086 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2087 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2088 * @param TIMx Timer instance
2089 * @param Channel This parameter can be one of the following values:
2090 * @arg @ref LL_TIM_CHANNEL_CH1
2091 * @arg @ref LL_TIM_CHANNEL_CH2
2092 * @arg @ref LL_TIM_CHANNEL_CH3
2093 * @arg @ref LL_TIM_CHANNEL_CH4
2094 * @arg @ref LL_TIM_CHANNEL_CH5
2095 * @arg @ref LL_TIM_CHANNEL_CH6
2096 * @param Configuration This parameter must be a combination of all the following values:
2097 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2098 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2099 * @retval None
2100 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2101 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2102 {
2103 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2104 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2105 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2106 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2107 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2108 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2109 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2110 }
2111
2112 /**
2113 * @brief Define the behavior of the output reference signal OCxREF from which
2114 * OCx and OCxN (when relevant) are derived.
2115 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2116 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2117 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2118 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2119 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2120 * CCMR3 OC6M LL_TIM_OC_SetMode
2121 * @param TIMx Timer instance
2122 * @param Channel This parameter can be one of the following values:
2123 * @arg @ref LL_TIM_CHANNEL_CH1
2124 * @arg @ref LL_TIM_CHANNEL_CH2
2125 * @arg @ref LL_TIM_CHANNEL_CH3
2126 * @arg @ref LL_TIM_CHANNEL_CH4
2127 * @arg @ref LL_TIM_CHANNEL_CH5
2128 * @arg @ref LL_TIM_CHANNEL_CH6
2129 * @param Mode This parameter can be one of the following values:
2130 * @arg @ref LL_TIM_OCMODE_FROZEN
2131 * @arg @ref LL_TIM_OCMODE_ACTIVE
2132 * @arg @ref LL_TIM_OCMODE_INACTIVE
2133 * @arg @ref LL_TIM_OCMODE_TOGGLE
2134 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2135 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2136 * @arg @ref LL_TIM_OCMODE_PWM1
2137 * @arg @ref LL_TIM_OCMODE_PWM2
2138 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2139 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2140 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2141 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2142 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2143 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2144 * @retval None
2145 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2146 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2147 {
2148 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2149 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2150 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2151 }
2152
2153 /**
2154 * @brief Get the output compare mode of an output channel.
2155 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2156 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2157 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2158 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2159 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2160 * CCMR3 OC6M LL_TIM_OC_GetMode
2161 * @param TIMx Timer instance
2162 * @param Channel This parameter can be one of the following values:
2163 * @arg @ref LL_TIM_CHANNEL_CH1
2164 * @arg @ref LL_TIM_CHANNEL_CH2
2165 * @arg @ref LL_TIM_CHANNEL_CH3
2166 * @arg @ref LL_TIM_CHANNEL_CH4
2167 * @arg @ref LL_TIM_CHANNEL_CH5
2168 * @arg @ref LL_TIM_CHANNEL_CH6
2169 * @retval Returned value can be one of the following values:
2170 * @arg @ref LL_TIM_OCMODE_FROZEN
2171 * @arg @ref LL_TIM_OCMODE_ACTIVE
2172 * @arg @ref LL_TIM_OCMODE_INACTIVE
2173 * @arg @ref LL_TIM_OCMODE_TOGGLE
2174 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2175 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2176 * @arg @ref LL_TIM_OCMODE_PWM1
2177 * @arg @ref LL_TIM_OCMODE_PWM2
2178 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2179 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2180 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2181 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2182 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2183 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2184 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2185 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2186 {
2187 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2188 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2189 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2190 }
2191
2192 /**
2193 * @brief Set the polarity of an output channel.
2194 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2195 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2196 * CCER CC2P LL_TIM_OC_SetPolarity\n
2197 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2198 * CCER CC3P LL_TIM_OC_SetPolarity\n
2199 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2200 * CCER CC4P LL_TIM_OC_SetPolarity\n
2201 * CCER CC5P LL_TIM_OC_SetPolarity\n
2202 * CCER CC6P LL_TIM_OC_SetPolarity
2203 * @param TIMx Timer instance
2204 * @param Channel This parameter can be one of the following values:
2205 * @arg @ref LL_TIM_CHANNEL_CH1
2206 * @arg @ref LL_TIM_CHANNEL_CH1N
2207 * @arg @ref LL_TIM_CHANNEL_CH2
2208 * @arg @ref LL_TIM_CHANNEL_CH2N
2209 * @arg @ref LL_TIM_CHANNEL_CH3
2210 * @arg @ref LL_TIM_CHANNEL_CH3N
2211 * @arg @ref LL_TIM_CHANNEL_CH4
2212 * @arg @ref LL_TIM_CHANNEL_CH5
2213 * @arg @ref LL_TIM_CHANNEL_CH6
2214 * @param Polarity This parameter can be one of the following values:
2215 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2216 * @arg @ref LL_TIM_OCPOLARITY_LOW
2217 * @retval None
2218 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2219 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2220 {
2221 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2222 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2223 }
2224
2225 /**
2226 * @brief Get the polarity of an output channel.
2227 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2228 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2229 * CCER CC2P LL_TIM_OC_GetPolarity\n
2230 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2231 * CCER CC3P LL_TIM_OC_GetPolarity\n
2232 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2233 * CCER CC4P LL_TIM_OC_GetPolarity\n
2234 * CCER CC5P LL_TIM_OC_GetPolarity\n
2235 * CCER CC6P LL_TIM_OC_GetPolarity
2236 * @param TIMx Timer instance
2237 * @param Channel This parameter can be one of the following values:
2238 * @arg @ref LL_TIM_CHANNEL_CH1
2239 * @arg @ref LL_TIM_CHANNEL_CH1N
2240 * @arg @ref LL_TIM_CHANNEL_CH2
2241 * @arg @ref LL_TIM_CHANNEL_CH2N
2242 * @arg @ref LL_TIM_CHANNEL_CH3
2243 * @arg @ref LL_TIM_CHANNEL_CH3N
2244 * @arg @ref LL_TIM_CHANNEL_CH4
2245 * @arg @ref LL_TIM_CHANNEL_CH5
2246 * @arg @ref LL_TIM_CHANNEL_CH6
2247 * @retval Returned value can be one of the following values:
2248 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2249 * @arg @ref LL_TIM_OCPOLARITY_LOW
2250 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2251 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2252 {
2253 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2254 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2255 }
2256
2257 /**
2258 * @brief Set the IDLE state of an output channel
2259 * @note This function is significant only for the timer instances
2260 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2261 * can be used to check whether or not a timer instance provides
2262 * a break input.
2263 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2264 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2265 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2266 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2267 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2268 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2269 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2270 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2271 * CR2 OIS6 LL_TIM_OC_SetIdleState
2272 * @param TIMx Timer instance
2273 * @param Channel This parameter can be one of the following values:
2274 * @arg @ref LL_TIM_CHANNEL_CH1
2275 * @arg @ref LL_TIM_CHANNEL_CH1N
2276 * @arg @ref LL_TIM_CHANNEL_CH2
2277 * @arg @ref LL_TIM_CHANNEL_CH2N
2278 * @arg @ref LL_TIM_CHANNEL_CH3
2279 * @arg @ref LL_TIM_CHANNEL_CH3N
2280 * @arg @ref LL_TIM_CHANNEL_CH4
2281 * @arg @ref LL_TIM_CHANNEL_CH5
2282 * @arg @ref LL_TIM_CHANNEL_CH6
2283 * @param IdleState This parameter can be one of the following values:
2284 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2285 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2286 * @retval None
2287 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2288 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2289 {
2290 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2291 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2292 }
2293
2294 /**
2295 * @brief Get the IDLE state of an output channel
2296 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2297 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2298 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2299 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2300 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2301 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2302 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2303 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2304 * CR2 OIS6 LL_TIM_OC_GetIdleState
2305 * @param TIMx Timer instance
2306 * @param Channel This parameter can be one of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH1N
2309 * @arg @ref LL_TIM_CHANNEL_CH2
2310 * @arg @ref LL_TIM_CHANNEL_CH2N
2311 * @arg @ref LL_TIM_CHANNEL_CH3
2312 * @arg @ref LL_TIM_CHANNEL_CH3N
2313 * @arg @ref LL_TIM_CHANNEL_CH4
2314 * @arg @ref LL_TIM_CHANNEL_CH5
2315 * @arg @ref LL_TIM_CHANNEL_CH6
2316 * @retval Returned value can be one of the following values:
2317 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2318 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2319 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2320 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2321 {
2322 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2323 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2324 }
2325
2326 /**
2327 * @brief Enable fast mode for the output channel.
2328 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2329 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2330 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2331 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2332 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2333 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2334 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2335 * @param TIMx Timer instance
2336 * @param Channel This parameter can be one of the following values:
2337 * @arg @ref LL_TIM_CHANNEL_CH1
2338 * @arg @ref LL_TIM_CHANNEL_CH2
2339 * @arg @ref LL_TIM_CHANNEL_CH3
2340 * @arg @ref LL_TIM_CHANNEL_CH4
2341 * @arg @ref LL_TIM_CHANNEL_CH5
2342 * @arg @ref LL_TIM_CHANNEL_CH6
2343 * @retval None
2344 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2345 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2346 {
2347 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2348 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2349 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2350
2351 }
2352
2353 /**
2354 * @brief Disable fast mode for the output channel.
2355 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2356 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2357 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2358 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2359 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2360 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2361 * @param TIMx Timer instance
2362 * @param Channel This parameter can be one of the following values:
2363 * @arg @ref LL_TIM_CHANNEL_CH1
2364 * @arg @ref LL_TIM_CHANNEL_CH2
2365 * @arg @ref LL_TIM_CHANNEL_CH3
2366 * @arg @ref LL_TIM_CHANNEL_CH4
2367 * @arg @ref LL_TIM_CHANNEL_CH5
2368 * @arg @ref LL_TIM_CHANNEL_CH6
2369 * @retval None
2370 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2371 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2372 {
2373 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2374 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2375 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2376
2377 }
2378
2379 /**
2380 * @brief Indicates whether fast mode is enabled for the output channel.
2381 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2382 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2383 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2384 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2385 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2386 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2387 * @param TIMx Timer instance
2388 * @param Channel This parameter can be one of the following values:
2389 * @arg @ref LL_TIM_CHANNEL_CH1
2390 * @arg @ref LL_TIM_CHANNEL_CH2
2391 * @arg @ref LL_TIM_CHANNEL_CH3
2392 * @arg @ref LL_TIM_CHANNEL_CH4
2393 * @arg @ref LL_TIM_CHANNEL_CH5
2394 * @arg @ref LL_TIM_CHANNEL_CH6
2395 * @retval State of bit (1 or 0).
2396 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2397 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2398 {
2399 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2400 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2401 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2402 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2403 }
2404
2405 /**
2406 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2407 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2408 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2409 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2410 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2411 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2412 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2413 * @param TIMx Timer instance
2414 * @param Channel This parameter can be one of the following values:
2415 * @arg @ref LL_TIM_CHANNEL_CH1
2416 * @arg @ref LL_TIM_CHANNEL_CH2
2417 * @arg @ref LL_TIM_CHANNEL_CH3
2418 * @arg @ref LL_TIM_CHANNEL_CH4
2419 * @arg @ref LL_TIM_CHANNEL_CH5
2420 * @arg @ref LL_TIM_CHANNEL_CH6
2421 * @retval None
2422 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2423 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2424 {
2425 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2426 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2427 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2428 }
2429
2430 /**
2431 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2432 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2433 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2434 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2435 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2436 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2437 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2438 * @param TIMx Timer instance
2439 * @param Channel This parameter can be one of the following values:
2440 * @arg @ref LL_TIM_CHANNEL_CH1
2441 * @arg @ref LL_TIM_CHANNEL_CH2
2442 * @arg @ref LL_TIM_CHANNEL_CH3
2443 * @arg @ref LL_TIM_CHANNEL_CH4
2444 * @arg @ref LL_TIM_CHANNEL_CH5
2445 * @arg @ref LL_TIM_CHANNEL_CH6
2446 * @retval None
2447 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2448 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2449 {
2450 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2451 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2452 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2453 }
2454
2455 /**
2456 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2457 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2458 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2459 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2460 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2461 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2462 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2463 * @param TIMx Timer instance
2464 * @param Channel This parameter can be one of the following values:
2465 * @arg @ref LL_TIM_CHANNEL_CH1
2466 * @arg @ref LL_TIM_CHANNEL_CH2
2467 * @arg @ref LL_TIM_CHANNEL_CH3
2468 * @arg @ref LL_TIM_CHANNEL_CH4
2469 * @arg @ref LL_TIM_CHANNEL_CH5
2470 * @arg @ref LL_TIM_CHANNEL_CH6
2471 * @retval State of bit (1 or 0).
2472 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2473 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2474 {
2475 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2476 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2477 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2478 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2479 }
2480
2481 /**
2482 * @brief Enable clearing the output channel on an external event.
2483 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2484 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2485 * or not a timer instance can clear the OCxREF signal on an external event.
2486 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2487 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2488 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2489 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2490 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2491 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2492 * @param TIMx Timer instance
2493 * @param Channel This parameter can be one of the following values:
2494 * @arg @ref LL_TIM_CHANNEL_CH1
2495 * @arg @ref LL_TIM_CHANNEL_CH2
2496 * @arg @ref LL_TIM_CHANNEL_CH3
2497 * @arg @ref LL_TIM_CHANNEL_CH4
2498 * @arg @ref LL_TIM_CHANNEL_CH5
2499 * @arg @ref LL_TIM_CHANNEL_CH6
2500 * @retval None
2501 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2502 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2503 {
2504 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2506 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2507 }
2508
2509 /**
2510 * @brief Disable clearing the output channel on an external event.
2511 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2512 * or not a timer instance can clear the OCxREF signal on an external event.
2513 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2514 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2515 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2516 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2517 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2518 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2519 * @param TIMx Timer instance
2520 * @param Channel This parameter can be one of the following values:
2521 * @arg @ref LL_TIM_CHANNEL_CH1
2522 * @arg @ref LL_TIM_CHANNEL_CH2
2523 * @arg @ref LL_TIM_CHANNEL_CH3
2524 * @arg @ref LL_TIM_CHANNEL_CH4
2525 * @arg @ref LL_TIM_CHANNEL_CH5
2526 * @arg @ref LL_TIM_CHANNEL_CH6
2527 * @retval None
2528 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2529 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2530 {
2531 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2532 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2533 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2534 }
2535
2536 /**
2537 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2538 * @note This function enables clearing the output channel on an external event.
2539 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2540 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2541 * or not a timer instance can clear the OCxREF signal on an external event.
2542 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2543 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2544 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2545 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2546 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2547 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2548 * @param TIMx Timer instance
2549 * @param Channel This parameter can be one of the following values:
2550 * @arg @ref LL_TIM_CHANNEL_CH1
2551 * @arg @ref LL_TIM_CHANNEL_CH2
2552 * @arg @ref LL_TIM_CHANNEL_CH3
2553 * @arg @ref LL_TIM_CHANNEL_CH4
2554 * @arg @ref LL_TIM_CHANNEL_CH5
2555 * @arg @ref LL_TIM_CHANNEL_CH6
2556 * @retval State of bit (1 or 0).
2557 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2558 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2559 {
2560 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2561 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2562 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2563 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2564 }
2565
2566 /**
2567 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2568 * the Ocx and OCxN signals).
2569 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2570 * dead-time insertion feature is supported by a timer instance.
2571 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2572 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2573 * @param TIMx Timer instance
2574 * @param DeadTime between Min_Data=0 and Max_Data=255
2575 * @retval None
2576 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2577 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2578 {
2579 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2580 }
2581
2582 /**
2583 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2584 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2585 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2586 * whether or not a timer instance supports a 32 bits counter.
2587 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2588 * output channel 1 is supported by a timer instance.
2589 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2590 * @param TIMx Timer instance
2591 * @param CompareValue between Min_Data=0 and Max_Data=65535
2592 * @retval None
2593 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2594 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2595 {
2596 WRITE_REG(TIMx->CCR1, CompareValue);
2597 }
2598
2599 /**
2600 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2601 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2602 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2603 * whether or not a timer instance supports a 32 bits counter.
2604 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2605 * output channel 2 is supported by a timer instance.
2606 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2607 * @param TIMx Timer instance
2608 * @param CompareValue between Min_Data=0 and Max_Data=65535
2609 * @retval None
2610 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2611 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2612 {
2613 WRITE_REG(TIMx->CCR2, CompareValue);
2614 }
2615
2616 /**
2617 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2618 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2619 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2620 * whether or not a timer instance supports a 32 bits counter.
2621 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2622 * output channel is supported by a timer instance.
2623 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2624 * @param TIMx Timer instance
2625 * @param CompareValue between Min_Data=0 and Max_Data=65535
2626 * @retval None
2627 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2628 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2629 {
2630 WRITE_REG(TIMx->CCR3, CompareValue);
2631 }
2632
2633 /**
2634 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2635 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2636 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2637 * whether or not a timer instance supports a 32 bits counter.
2638 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2639 * output channel 4 is supported by a timer instance.
2640 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2641 * @param TIMx Timer instance
2642 * @param CompareValue between Min_Data=0 and Max_Data=65535
2643 * @retval None
2644 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2645 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2646 {
2647 WRITE_REG(TIMx->CCR4, CompareValue);
2648 }
2649
2650 /**
2651 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2652 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2653 * output channel 5 is supported by a timer instance.
2654 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2655 * @param TIMx Timer instance
2656 * @param CompareValue between Min_Data=0 and Max_Data=65535
2657 * @retval None
2658 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2659 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2660 {
2661 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2662 }
2663
2664 /**
2665 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2666 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2667 * output channel 6 is supported by a timer instance.
2668 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2669 * @param TIMx Timer instance
2670 * @param CompareValue between Min_Data=0 and Max_Data=65535
2671 * @retval None
2672 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2673 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2674 {
2675 WRITE_REG(TIMx->CCR6, CompareValue);
2676 }
2677
2678 /**
2679 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2680 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2681 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2682 * whether or not a timer instance supports a 32 bits counter.
2683 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2684 * output channel 1 is supported by a timer instance.
2685 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2686 * @param TIMx Timer instance
2687 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2688 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2689 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2690 {
2691 return (uint32_t)(READ_REG(TIMx->CCR1));
2692 }
2693
2694 /**
2695 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2696 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2697 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2698 * whether or not a timer instance supports a 32 bits counter.
2699 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2700 * output channel 2 is supported by a timer instance.
2701 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2702 * @param TIMx Timer instance
2703 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2704 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2705 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2706 {
2707 return (uint32_t)(READ_REG(TIMx->CCR2));
2708 }
2709
2710 /**
2711 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2712 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2713 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2714 * whether or not a timer instance supports a 32 bits counter.
2715 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2716 * output channel 3 is supported by a timer instance.
2717 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2718 * @param TIMx Timer instance
2719 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2720 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2721 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2722 {
2723 return (uint32_t)(READ_REG(TIMx->CCR3));
2724 }
2725
2726 /**
2727 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2728 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2729 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2730 * whether or not a timer instance supports a 32 bits counter.
2731 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2732 * output channel 4 is supported by a timer instance.
2733 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2734 * @param TIMx Timer instance
2735 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2736 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2737 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2738 {
2739 return (uint32_t)(READ_REG(TIMx->CCR4));
2740 }
2741
2742 /**
2743 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2744 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2745 * output channel 5 is supported by a timer instance.
2746 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2747 * @param TIMx Timer instance
2748 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2749 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2750 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2751 {
2752 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2753 }
2754
2755 /**
2756 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2757 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2758 * output channel 6 is supported by a timer instance.
2759 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2760 * @param TIMx Timer instance
2761 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2762 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2763 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2764 {
2765 return (uint32_t)(READ_REG(TIMx->CCR6));
2766 }
2767
2768 /**
2769 * @brief Select on which reference signal the OC5REF is combined to.
2770 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2771 * whether or not a timer instance supports the combined 3-phase PWM mode.
2772 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2773 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2774 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2775 * @param TIMx Timer instance
2776 * @param GroupCH5 This parameter can be a combination of the following values:
2777 * @arg @ref LL_TIM_GROUPCH5_NONE
2778 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2779 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2780 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2781 * @retval None
2782 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2783 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2784 {
2785 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2786 }
2787
2788 /**
2789 * @}
2790 */
2791
2792 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2793 * @{
2794 */
2795 /**
2796 * @brief Configure input channel.
2797 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2798 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2799 * CCMR1 IC1F LL_TIM_IC_Config\n
2800 * CCMR1 CC2S LL_TIM_IC_Config\n
2801 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2802 * CCMR1 IC2F LL_TIM_IC_Config\n
2803 * CCMR2 CC3S LL_TIM_IC_Config\n
2804 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2805 * CCMR2 IC3F LL_TIM_IC_Config\n
2806 * CCMR2 CC4S LL_TIM_IC_Config\n
2807 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2808 * CCMR2 IC4F LL_TIM_IC_Config\n
2809 * CCER CC1P LL_TIM_IC_Config\n
2810 * CCER CC1NP LL_TIM_IC_Config\n
2811 * CCER CC2P LL_TIM_IC_Config\n
2812 * CCER CC2NP LL_TIM_IC_Config\n
2813 * CCER CC3P LL_TIM_IC_Config\n
2814 * CCER CC3NP LL_TIM_IC_Config\n
2815 * CCER CC4P LL_TIM_IC_Config\n
2816 * CCER CC4NP LL_TIM_IC_Config
2817 * @param TIMx Timer instance
2818 * @param Channel This parameter can be one of the following values:
2819 * @arg @ref LL_TIM_CHANNEL_CH1
2820 * @arg @ref LL_TIM_CHANNEL_CH2
2821 * @arg @ref LL_TIM_CHANNEL_CH3
2822 * @arg @ref LL_TIM_CHANNEL_CH4
2823 * @param Configuration This parameter must be a combination of all the following values:
2824 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2825 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2826 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2827 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2828 * @retval None
2829 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2830 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2831 {
2832 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2833 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2834 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2835 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2836 << SHIFT_TAB_ICxx[iChannel]);
2837 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2838 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2839 }
2840
2841 /**
2842 * @brief Set the active input.
2843 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2844 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2845 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2846 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2847 * @param TIMx Timer instance
2848 * @param Channel This parameter can be one of the following values:
2849 * @arg @ref LL_TIM_CHANNEL_CH1
2850 * @arg @ref LL_TIM_CHANNEL_CH2
2851 * @arg @ref LL_TIM_CHANNEL_CH3
2852 * @arg @ref LL_TIM_CHANNEL_CH4
2853 * @param ICActiveInput This parameter can be one of the following values:
2854 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2855 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2856 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2857 * @retval None
2858 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2859 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2860 {
2861 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2862 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2863 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2864 }
2865
2866 /**
2867 * @brief Get the current active input.
2868 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2869 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2870 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2871 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2872 * @param TIMx Timer instance
2873 * @param Channel This parameter can be one of the following values:
2874 * @arg @ref LL_TIM_CHANNEL_CH1
2875 * @arg @ref LL_TIM_CHANNEL_CH2
2876 * @arg @ref LL_TIM_CHANNEL_CH3
2877 * @arg @ref LL_TIM_CHANNEL_CH4
2878 * @retval Returned value can be one of the following values:
2879 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2880 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2881 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2882 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2883 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2884 {
2885 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2886 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2887 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2888 }
2889
2890 /**
2891 * @brief Set the prescaler of input channel.
2892 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2893 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2894 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2895 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2896 * @param TIMx Timer instance
2897 * @param Channel This parameter can be one of the following values:
2898 * @arg @ref LL_TIM_CHANNEL_CH1
2899 * @arg @ref LL_TIM_CHANNEL_CH2
2900 * @arg @ref LL_TIM_CHANNEL_CH3
2901 * @arg @ref LL_TIM_CHANNEL_CH4
2902 * @param ICPrescaler This parameter can be one of the following values:
2903 * @arg @ref LL_TIM_ICPSC_DIV1
2904 * @arg @ref LL_TIM_ICPSC_DIV2
2905 * @arg @ref LL_TIM_ICPSC_DIV4
2906 * @arg @ref LL_TIM_ICPSC_DIV8
2907 * @retval None
2908 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2909 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2910 {
2911 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2912 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2913 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2914 }
2915
2916 /**
2917 * @brief Get the current prescaler value acting on an input channel.
2918 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2919 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2920 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2921 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2922 * @param TIMx Timer instance
2923 * @param Channel This parameter can be one of the following values:
2924 * @arg @ref LL_TIM_CHANNEL_CH1
2925 * @arg @ref LL_TIM_CHANNEL_CH2
2926 * @arg @ref LL_TIM_CHANNEL_CH3
2927 * @arg @ref LL_TIM_CHANNEL_CH4
2928 * @retval Returned value can be one of the following values:
2929 * @arg @ref LL_TIM_ICPSC_DIV1
2930 * @arg @ref LL_TIM_ICPSC_DIV2
2931 * @arg @ref LL_TIM_ICPSC_DIV4
2932 * @arg @ref LL_TIM_ICPSC_DIV8
2933 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2934 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2935 {
2936 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2937 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2938 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2939 }
2940
2941 /**
2942 * @brief Set the input filter duration.
2943 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2944 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2945 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2946 * CCMR2 IC4F LL_TIM_IC_SetFilter
2947 * @param TIMx Timer instance
2948 * @param Channel This parameter can be one of the following values:
2949 * @arg @ref LL_TIM_CHANNEL_CH1
2950 * @arg @ref LL_TIM_CHANNEL_CH2
2951 * @arg @ref LL_TIM_CHANNEL_CH3
2952 * @arg @ref LL_TIM_CHANNEL_CH4
2953 * @param ICFilter This parameter can be one of the following values:
2954 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2955 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2956 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2957 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2958 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2959 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2960 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2961 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2962 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2963 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2964 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2965 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2967 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2968 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2969 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2970 * @retval None
2971 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2972 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2973 {
2974 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2975 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2976 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2977 }
2978
2979 /**
2980 * @brief Get the input filter duration.
2981 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2982 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2983 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2984 * CCMR2 IC4F LL_TIM_IC_GetFilter
2985 * @param TIMx Timer instance
2986 * @param Channel This parameter can be one of the following values:
2987 * @arg @ref LL_TIM_CHANNEL_CH1
2988 * @arg @ref LL_TIM_CHANNEL_CH2
2989 * @arg @ref LL_TIM_CHANNEL_CH3
2990 * @arg @ref LL_TIM_CHANNEL_CH4
2991 * @retval Returned value can be one of the following values:
2992 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2993 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2994 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2995 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2996 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2997 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2998 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2999 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3000 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3001 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3002 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3003 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3004 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3005 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3006 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3007 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3008 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3009 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3010 {
3011 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3012 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3013 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3014 }
3015
3016 /**
3017 * @brief Set the input channel polarity.
3018 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3019 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3020 * CCER CC2P LL_TIM_IC_SetPolarity\n
3021 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3022 * CCER CC3P LL_TIM_IC_SetPolarity\n
3023 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3024 * CCER CC4P LL_TIM_IC_SetPolarity\n
3025 * CCER CC4NP LL_TIM_IC_SetPolarity
3026 * @param TIMx Timer instance
3027 * @param Channel This parameter can be one of the following values:
3028 * @arg @ref LL_TIM_CHANNEL_CH1
3029 * @arg @ref LL_TIM_CHANNEL_CH2
3030 * @arg @ref LL_TIM_CHANNEL_CH3
3031 * @arg @ref LL_TIM_CHANNEL_CH4
3032 * @param ICPolarity This parameter can be one of the following values:
3033 * @arg @ref LL_TIM_IC_POLARITY_RISING
3034 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3035 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3036 * @retval None
3037 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3038 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3039 {
3040 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3041 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3042 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3043 }
3044
3045 /**
3046 * @brief Get the current input channel polarity.
3047 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3048 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3049 * CCER CC2P LL_TIM_IC_GetPolarity\n
3050 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3051 * CCER CC3P LL_TIM_IC_GetPolarity\n
3052 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3053 * CCER CC4P LL_TIM_IC_GetPolarity\n
3054 * CCER CC4NP LL_TIM_IC_GetPolarity
3055 * @param TIMx Timer instance
3056 * @param Channel This parameter can be one of the following values:
3057 * @arg @ref LL_TIM_CHANNEL_CH1
3058 * @arg @ref LL_TIM_CHANNEL_CH2
3059 * @arg @ref LL_TIM_CHANNEL_CH3
3060 * @arg @ref LL_TIM_CHANNEL_CH4
3061 * @retval Returned value can be one of the following values:
3062 * @arg @ref LL_TIM_IC_POLARITY_RISING
3063 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3064 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3065 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3066 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3067 {
3068 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3069 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3070 SHIFT_TAB_CCxP[iChannel]);
3071 }
3072
3073 /**
3074 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3075 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3076 * a timer instance provides an XOR input.
3077 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3078 * @param TIMx Timer instance
3079 * @retval None
3080 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3081 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3082 {
3083 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3084 }
3085
3086 /**
3087 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3088 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3089 * a timer instance provides an XOR input.
3090 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3091 * @param TIMx Timer instance
3092 * @retval None
3093 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3094 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3095 {
3096 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3097 }
3098
3099 /**
3100 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3101 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3102 * a timer instance provides an XOR input.
3103 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3104 * @param TIMx Timer instance
3105 * @retval State of bit (1 or 0).
3106 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3107 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3108 {
3109 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3110 }
3111
3112 /**
3113 * @brief Get captured value for input channel 1.
3114 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3115 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3116 * whether or not a timer instance supports a 32 bits counter.
3117 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3118 * input channel 1 is supported by a timer instance.
3119 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3120 * @param TIMx Timer instance
3121 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3122 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3123 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3124 {
3125 return (uint32_t)(READ_REG(TIMx->CCR1));
3126 }
3127
3128 /**
3129 * @brief Get captured value for input channel 2.
3130 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3131 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3132 * whether or not a timer instance supports a 32 bits counter.
3133 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3134 * input channel 2 is supported by a timer instance.
3135 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3136 * @param TIMx Timer instance
3137 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3138 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3139 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3140 {
3141 return (uint32_t)(READ_REG(TIMx->CCR2));
3142 }
3143
3144 /**
3145 * @brief Get captured value for input channel 3.
3146 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3147 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3148 * whether or not a timer instance supports a 32 bits counter.
3149 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3150 * input channel 3 is supported by a timer instance.
3151 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3152 * @param TIMx Timer instance
3153 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3154 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3155 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3156 {
3157 return (uint32_t)(READ_REG(TIMx->CCR3));
3158 }
3159
3160 /**
3161 * @brief Get captured value for input channel 4.
3162 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3163 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3164 * whether or not a timer instance supports a 32 bits counter.
3165 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3166 * input channel 4 is supported by a timer instance.
3167 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3168 * @param TIMx Timer instance
3169 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3170 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3171 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3172 {
3173 return (uint32_t)(READ_REG(TIMx->CCR4));
3174 }
3175
3176 /**
3177 * @}
3178 */
3179
3180 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3181 * @{
3182 */
3183 /**
3184 * @brief Enable external clock mode 2.
3185 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3186 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3187 * whether or not a timer instance supports external clock mode2.
3188 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3189 * @param TIMx Timer instance
3190 * @retval None
3191 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3192 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3193 {
3194 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3195 }
3196
3197 /**
3198 * @brief Disable external clock mode 2.
3199 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3200 * whether or not a timer instance supports external clock mode2.
3201 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3202 * @param TIMx Timer instance
3203 * @retval None
3204 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3205 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3206 {
3207 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3208 }
3209
3210 /**
3211 * @brief Indicate whether external clock mode 2 is enabled.
3212 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3213 * whether or not a timer instance supports external clock mode2.
3214 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3215 * @param TIMx Timer instance
3216 * @retval State of bit (1 or 0).
3217 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3218 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3219 {
3220 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3221 }
3222
3223 /**
3224 * @brief Set the clock source of the counter clock.
3225 * @note when selected clock source is external clock mode 1, the timer input
3226 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3227 * function. This timer input must be configured by calling
3228 * the @ref LL_TIM_IC_Config() function.
3229 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3230 * whether or not a timer instance supports external clock mode1.
3231 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3232 * whether or not a timer instance supports external clock mode2.
3233 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3234 * SMCR ECE LL_TIM_SetClockSource
3235 * @param TIMx Timer instance
3236 * @param ClockSource This parameter can be one of the following values:
3237 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3238 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3239 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3240 * @retval None
3241 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3242 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3243 {
3244 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3245 }
3246
3247 /**
3248 * @brief Set the encoder interface mode.
3249 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3250 * whether or not a timer instance supports the encoder mode.
3251 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3252 * @param TIMx Timer instance
3253 * @param EncoderMode This parameter can be one of the following values:
3254 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3255 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3256 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3257 * @retval None
3258 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3259 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3260 {
3261 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3262 }
3263
3264 /**
3265 * @}
3266 */
3267
3268 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3269 * @{
3270 */
3271 /**
3272 * @brief Set the trigger output (TRGO) used for timer synchronization .
3273 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3274 * whether or not a timer instance can operate as a master timer.
3275 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3276 * @param TIMx Timer instance
3277 * @param TimerSynchronization This parameter can be one of the following values:
3278 * @arg @ref LL_TIM_TRGO_RESET
3279 * @arg @ref LL_TIM_TRGO_ENABLE
3280 * @arg @ref LL_TIM_TRGO_UPDATE
3281 * @arg @ref LL_TIM_TRGO_CC1IF
3282 * @arg @ref LL_TIM_TRGO_OC1REF
3283 * @arg @ref LL_TIM_TRGO_OC2REF
3284 * @arg @ref LL_TIM_TRGO_OC3REF
3285 * @arg @ref LL_TIM_TRGO_OC4REF
3286 * @retval None
3287 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3288 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3289 {
3290 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3291 }
3292
3293 /**
3294 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3295 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3296 * whether or not a timer instance can be used for ADC synchronization.
3297 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3298 * @param TIMx Timer Instance
3299 * @param ADCSynchronization This parameter can be one of the following values:
3300 * @arg @ref LL_TIM_TRGO2_RESET
3301 * @arg @ref LL_TIM_TRGO2_ENABLE
3302 * @arg @ref LL_TIM_TRGO2_UPDATE
3303 * @arg @ref LL_TIM_TRGO2_CC1F
3304 * @arg @ref LL_TIM_TRGO2_OC1
3305 * @arg @ref LL_TIM_TRGO2_OC2
3306 * @arg @ref LL_TIM_TRGO2_OC3
3307 * @arg @ref LL_TIM_TRGO2_OC4
3308 * @arg @ref LL_TIM_TRGO2_OC5
3309 * @arg @ref LL_TIM_TRGO2_OC6
3310 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3311 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3312 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3313 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3314 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3315 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3316 * @retval None
3317 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3318 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3319 {
3320 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3321 }
3322
3323 /**
3324 * @brief Set the synchronization mode of a slave timer.
3325 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3326 * a timer instance can operate as a slave timer.
3327 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3328 * @param TIMx Timer instance
3329 * @param SlaveMode This parameter can be one of the following values:
3330 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3331 * @arg @ref LL_TIM_SLAVEMODE_RESET
3332 * @arg @ref LL_TIM_SLAVEMODE_GATED
3333 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3334 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3335 * @retval None
3336 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3337 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3338 {
3339 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3340 }
3341
3342 /**
3343 * @brief Set the selects the trigger input to be used to synchronize the counter.
3344 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3345 * a timer instance can operate as a slave timer.
3346 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3347 * @param TIMx Timer instance
3348 * @param TriggerInput This parameter can be one of the following values:
3349 * @arg @ref LL_TIM_TS_ITR0
3350 * @arg @ref LL_TIM_TS_ITR1
3351 * @arg @ref LL_TIM_TS_ITR2
3352 * @arg @ref LL_TIM_TS_ITR7
3353 * @arg @ref LL_TIM_TS_TI1F_ED
3354 * @arg @ref LL_TIM_TS_TI1FP1
3355 * @arg @ref LL_TIM_TS_TI2FP2
3356 * @arg @ref LL_TIM_TS_ETRF
3357 * @retval None
3358 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3359 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3360 {
3361 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3362 }
3363
3364 /**
3365 * @brief Enable the Master/Slave mode.
3366 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3367 * a timer instance can operate as a slave timer.
3368 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3369 * @param TIMx Timer instance
3370 * @retval None
3371 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3372 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3373 {
3374 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3375 }
3376
3377 /**
3378 * @brief Disable the Master/Slave mode.
3379 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3380 * a timer instance can operate as a slave timer.
3381 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3382 * @param TIMx Timer instance
3383 * @retval None
3384 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3385 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3386 {
3387 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3388 }
3389
3390 /**
3391 * @brief Indicates whether the Master/Slave mode is enabled.
3392 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3393 * a timer instance can operate as a slave timer.
3394 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3395 * @param TIMx Timer instance
3396 * @retval State of bit (1 or 0).
3397 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3398 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3399 {
3400 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3401 }
3402
3403 /**
3404 * @brief Configure the external trigger (ETR) input.
3405 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3406 * a timer instance provides an external trigger input.
3407 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3408 * SMCR ETPS LL_TIM_ConfigETR\n
3409 * SMCR ETF LL_TIM_ConfigETR
3410 * @param TIMx Timer instance
3411 * @param ETRPolarity This parameter can be one of the following values:
3412 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3413 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3414 * @param ETRPrescaler This parameter can be one of the following values:
3415 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3416 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3417 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3418 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3419 * @param ETRFilter This parameter can be one of the following values:
3420 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3421 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3422 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3423 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3424 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3425 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3426 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3427 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3428 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3429 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3430 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3431 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3432 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3433 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3434 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3435 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3436 * @retval None
3437 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3438 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3439 uint32_t ETRFilter)
3440 {
3441 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3442 }
3443
3444 /**
3445 * @brief Select the external trigger (ETR) input source.
3446 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3447 * not a timer instance supports ETR source selection.
3448 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3449 * @param TIMx Timer instance
3450 * @param ETRSource This parameter can be one of the following values:
3451 *
3452 * TIM1
3453 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3454 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3455 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*)
3456 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3457 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3458 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3459 *
3460 * TIM2
3461 *
3462 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3463 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3464 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*)
3465 * @arg @ref LL_TIM_ETRSOURCE_LSE
3466 * @arg @ref LL_TIM_ETRSOURCE_MCO2
3467 *
3468 * TIM3
3469 *
3470 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3471 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3472 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*)
3473 *
3474 * (*) Value not defined in all devices. \n
3475 *
3476 * @retval None
3477 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3478 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3479 {
3480 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3481 }
3482
3483 /**
3484 * @}
3485 */
3486
3487 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3488 * @{
3489 */
3490 /**
3491 * @brief Enable the break function.
3492 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3493 * a timer instance provides a break input.
3494 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3495 * @param TIMx Timer instance
3496 * @retval None
3497 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3498 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3499 {
3500 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3501 }
3502
3503 /**
3504 * @brief Disable the break function.
3505 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3506 * @param TIMx Timer instance
3507 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3508 * a timer instance provides a break input.
3509 * @retval None
3510 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3511 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3512 {
3513 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3514 }
3515
3516 /**
3517 * @brief Configure the break input.
3518 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3519 * a timer instance provides a break input.
3520 * @note Bidirectional mode is only supported by advanced timer instances.
3521 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3522 * a timer instance is an advanced-control timer.
3523 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3524 * in input mode and in open drain output mode. Any active Break event will
3525 * assert a low logic level on the Break input to indicate an internal break
3526 * event to external devices.
3527 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3528 * LL_TIM_BREAK_AFMODE_INPUT.
3529 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3530 * BDTR BKF LL_TIM_ConfigBRK\n
3531 * BDTR BKBID LL_TIM_ConfigBRK
3532 * @param TIMx Timer instance
3533 * @param BreakPolarity This parameter can be one of the following values:
3534 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3535 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3536 * @param BreakFilter This parameter can be one of the following values:
3537 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3538 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3539 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3540 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3541 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3542 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3543 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3544 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3545 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3546 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3547 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3548 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3549 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3550 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3551 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3552 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3553 * @param BreakAFMode This parameter can be one of the following values:
3554 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3555 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3556 * @retval None
3557 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3558 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3559 uint32_t BreakAFMode)
3560 {
3561 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3562 }
3563
3564 /**
3565 * @brief Disarm the break input (when it operates in bidirectional mode).
3566 * @note The break input can be disarmed only when it is configured in
3567 * bidirectional mode and when when MOE is reset.
3568 * @note Purpose is to be able to have the input voltage back to high-state,
3569 * whatever the time constant on the output .
3570 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3571 * @param TIMx Timer instance
3572 * @retval None
3573 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3574 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3575 {
3576 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3577 }
3578
3579 /**
3580 * @brief Enable the break 2 function.
3581 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3582 * a timer instance provides a second break input.
3583 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3584 * @param TIMx Timer instance
3585 * @retval None
3586 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3587 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3588 {
3589 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3590 }
3591
3592 /**
3593 * @brief Disable the break 2 function.
3594 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3595 * a timer instance provides a second break input.
3596 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3597 * @param TIMx Timer instance
3598 * @retval None
3599 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3600 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3601 {
3602 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3603 }
3604
3605 /**
3606 * @brief Configure the break 2 input.
3607 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3608 * a timer instance provides a second break input.
3609 * @note Bidirectional mode is only supported by advanced timer instances.
3610 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3611 * a timer instance is an advanced-control timer.
3612 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3613 * in input mode and in open drain output mode. Any active Break event will
3614 * assert a low logic level on the Break 2 input to indicate an internal break
3615 * event to external devices.
3616 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3617 * LL_TIM_BREAK2_AFMODE_INPUT.
3618 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3619 * BDTR BK2F LL_TIM_ConfigBRK2\n
3620 * BDTR BK2BID LL_TIM_ConfigBRK2
3621 * @param TIMx Timer instance
3622 * @param Break2Polarity This parameter can be one of the following values:
3623 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3624 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3625 * @param Break2Filter This parameter can be one of the following values:
3626 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3627 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3628 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3629 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3630 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3631 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3632 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3633 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3634 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3635 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3636 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3637 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3638 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3639 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3640 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3641 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3642 * @param Break2AFMode This parameter can be one of the following values:
3643 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3644 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3645 * @retval None
3646 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3647 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3648 uint32_t Break2AFMode)
3649 {
3650 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3651 }
3652
3653 /**
3654 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3655 * @note The break 2 input can be disarmed only when it is configured in
3656 * bidirectional mode and when when MOE is reset.
3657 * @note Purpose is to be able to have the input voltage back to high-state,
3658 * whatever the time constant on the output.
3659 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3660 * @param TIMx Timer instance
3661 * @retval None
3662 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3663 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3664 {
3665 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3666 }
3667
3668 /**
3669 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3670 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3671 * a timer instance provides a break input.
3672 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3673 * BDTR OSSR LL_TIM_SetOffStates
3674 * @param TIMx Timer instance
3675 * @param OffStateIdle This parameter can be one of the following values:
3676 * @arg @ref LL_TIM_OSSI_DISABLE
3677 * @arg @ref LL_TIM_OSSI_ENABLE
3678 * @param OffStateRun This parameter can be one of the following values:
3679 * @arg @ref LL_TIM_OSSR_DISABLE
3680 * @arg @ref LL_TIM_OSSR_ENABLE
3681 * @retval None
3682 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3683 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3684 {
3685 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3686 }
3687
3688 /**
3689 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3690 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3691 * a timer instance provides a break input.
3692 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3693 * @param TIMx Timer instance
3694 * @retval None
3695 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3696 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3697 {
3698 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3699 }
3700
3701 /**
3702 * @brief Disable automatic output (MOE can be set only by software).
3703 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3704 * a timer instance provides a break input.
3705 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3706 * @param TIMx Timer instance
3707 * @retval None
3708 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3709 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3710 {
3711 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3712 }
3713
3714 /**
3715 * @brief Indicate whether automatic output is enabled.
3716 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3717 * a timer instance provides a break input.
3718 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3719 * @param TIMx Timer instance
3720 * @retval State of bit (1 or 0).
3721 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3722 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3723 {
3724 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3725 }
3726
3727 /**
3728 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3729 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3730 * software and is reset in case of break or break2 event
3731 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3732 * a timer instance provides a break input.
3733 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3734 * @param TIMx Timer instance
3735 * @retval None
3736 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3737 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3738 {
3739 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3740 }
3741
3742 /**
3743 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3744 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3745 * software and is reset in case of break or break2 event.
3746 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3747 * a timer instance provides a break input.
3748 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3749 * @param TIMx Timer instance
3750 * @retval None
3751 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3752 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3753 {
3754 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3755 }
3756
3757 /**
3758 * @brief Indicates whether outputs are enabled.
3759 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3760 * a timer instance provides a break input.
3761 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3762 * @param TIMx Timer instance
3763 * @retval State of bit (1 or 0).
3764 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3765 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3766 {
3767 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3768 }
3769
3770 /**
3771 * @brief Enable the signals connected to the designated timer break input.
3772 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3773 * or not a timer instance allows for break input selection.
3774 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3775 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3776 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3777 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3778 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3779 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3780 * @param TIMx Timer instance
3781 * @param BreakInput This parameter can be one of the following values:
3782 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3783 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3784 * @param Source This parameter can be one of the following values:
3785 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3786 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3787 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3788 *
3789 * (*) Value not defined in all devices.
3790 * @retval None
3791 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3792 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3793 {
3794 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3795 SET_BIT(*pReg, Source);
3796 }
3797
3798 /**
3799 * @brief Disable the signals connected to the designated timer break input.
3800 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3801 * or not a timer instance allows for break input selection.
3802 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3803 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3804 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3805 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3806 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3807 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3808 * @param TIMx Timer instance
3809 * @param BreakInput This parameter can be one of the following values:
3810 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3811 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3812 * @param Source This parameter can be one of the following values:
3813 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3814 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3815 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3816 *
3817 * (*) Value not defined in all devices.
3818 * @retval None
3819 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3820 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3821 {
3822 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3823 CLEAR_BIT(*pReg, Source);
3824 }
3825
3826 /**
3827 * @brief Set the polarity of the break signal for the timer break input.
3828 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3829 * or not a timer instance allows for break input selection.
3830 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3831 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3832 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3833 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3834 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3835 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3836 * @param TIMx Timer instance
3837 * @param BreakInput This parameter can be one of the following values:
3838 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3839 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3840 * @param Source This parameter can be one of the following values:
3841 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3842 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3843 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3844 * @param Polarity This parameter can be one of the following values:
3845 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3846 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3847 *
3848 * (*) Value not defined in all devices.
3849 * @retval None
3850 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3851 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3852 uint32_t Polarity)
3853 {
3854 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3855 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3856 }
3857 /**
3858 * @}
3859 */
3860
3861 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3862 * @{
3863 */
3864 /**
3865 * @brief Configures the timer DMA burst feature.
3866 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3867 * not a timer instance supports the DMA burst mode.
3868 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3869 * DCR DBA LL_TIM_ConfigDMABurst
3870 * @param TIMx Timer instance
3871 * @param DMABurstBaseAddress This parameter can be one of the following values:
3872 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3873 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3874 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3875 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3876 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3877 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3878 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3879 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3880 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3881 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3882 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3883 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3884 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3885 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3886 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3887 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3888 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3889 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3890 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3891 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3892 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3893 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3894 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3895 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3896 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3897 * @param DMABurstLength This parameter can be one of the following values:
3898 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3899 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3900 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3901 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3902 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3903 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3904 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3905 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3906 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3907 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3908 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3909 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3910 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3911 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3912 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3913 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3914 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3915 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3916 * @retval None
3917 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3918 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3919 {
3920 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3921 }
3922
3923 /**
3924 * @}
3925 */
3926
3927 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3928 * @{
3929 */
3930 /**
3931 * @brief Remap TIM inputs (input channel, internal/external triggers).
3932 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3933 * a some timer inputs can be remapped.
3934 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
3935 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
3936 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
3937 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
3938 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
3939 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
3940 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
3941 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
3942 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
3943 * @param TIMx Timer instance
3944 * @param Remap Remap param depends on the TIMx. Description available only
3945 * in CHM version of the User Manual (not in .pdf).
3946 * Otherwise see Reference Manual description of TISEL registers.
3947 *
3948 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3949 *
3950 * TIM1: any combination of TI1_RMP and TI2_RMP where
3951 *
3952 * . . TI1_RMP can be one of the following values
3953 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3954 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3955 *
3956 * . . TI2_RMP can be one of the following values
3957 * @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
3958 * @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2 (*)
3959 *
3960 * TIM2: any combination of TI1_RMP and TI2_RMP where
3961 *
3962 * . . TI1_RMP can be one of the following values
3963 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
3964 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
3965 *
3966 * . . TI2_RMP can be one of the following values
3967 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
3968 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 (*)
3969 *
3970 * TIM3: any combination of TI1_RMP and TI2_RMP where
3971 *
3972 * . . TI1_RMP can be one of the following values
3973 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3974 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3975 *
3976 * . . TI2_RMP can be one of the following values
3977 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
3978 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 (*)
3979 *
3980 * TIM15: any combination of TI1_RMP and TI2_RMP where
3981 *
3982 * . . TI1_RMP can be one of the following values
3983 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3984 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
3985 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
3986 *
3987 * . . TI2_RMP can be one of the following values
3988 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
3989 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
3990 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
3991 *
3992 * TIM16: one of the following values
3993 *
3994 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3995 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3996 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3997 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
3998 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2
3999 *
4000 * (*) Value not defined in all devices. \n
4001 * @retval None
4002 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4003 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4004 {
4005 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4006 }
4007
4008 /**
4009 * @}
4010 */
4011
4012 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4013 * @{
4014 */
4015 /**
4016 * @brief Set the OCREF clear input source
4017 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4018 * @note This function can only be used in Output compare and PWM modes.
4019 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4020 * @rmtoll OR1 OCREF_CLR LL_TIM_SetOCRefClearInputSource
4021 * @param TIMx Timer instance
4022 * @param OCRefClearInputSource This parameter can be one of the following values:
4023 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4024 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
4025 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
4026 *
4027 * (*) Value not defined in all devices. \n
4028 *
4029 * @retval None
4030 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4031 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4032 {
4033 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
4034 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
4035 MODIFY_REG(TIMx->OR1, TIM_OR1_OCREF_CLR, OCRefClearInputSource);
4036 }
4037 /**
4038 * @}
4039 */
4040
4041 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4042 * @{
4043 */
4044 /**
4045 * @brief Clear the update interrupt flag (UIF).
4046 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4047 * @param TIMx Timer instance
4048 * @retval None
4049 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4050 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4051 {
4052 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4053 }
4054
4055 /**
4056 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4057 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4058 * @param TIMx Timer instance
4059 * @retval State of bit (1 or 0).
4060 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4061 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4062 {
4063 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4064 }
4065
4066 /**
4067 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4068 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4069 * @param TIMx Timer instance
4070 * @retval None
4071 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4072 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4073 {
4074 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4075 }
4076
4077 /**
4078 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4079 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4080 * @param TIMx Timer instance
4081 * @retval State of bit (1 or 0).
4082 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4083 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4084 {
4085 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4086 }
4087
4088 /**
4089 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4090 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4091 * @param TIMx Timer instance
4092 * @retval None
4093 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4094 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4095 {
4096 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4097 }
4098
4099 /**
4100 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4101 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4102 * @param TIMx Timer instance
4103 * @retval State of bit (1 or 0).
4104 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4105 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4106 {
4107 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4108 }
4109
4110 /**
4111 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4112 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4113 * @param TIMx Timer instance
4114 * @retval None
4115 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4116 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4117 {
4118 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4119 }
4120
4121 /**
4122 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4123 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4124 * @param TIMx Timer instance
4125 * @retval State of bit (1 or 0).
4126 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4127 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4128 {
4129 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4130 }
4131
4132 /**
4133 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4134 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4135 * @param TIMx Timer instance
4136 * @retval None
4137 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4138 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4139 {
4140 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4141 }
4142
4143 /**
4144 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4145 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4146 * @param TIMx Timer instance
4147 * @retval State of bit (1 or 0).
4148 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4149 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4150 {
4151 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4152 }
4153
4154 /**
4155 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4156 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4157 * @param TIMx Timer instance
4158 * @retval None
4159 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4160 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4161 {
4162 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4163 }
4164
4165 /**
4166 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4167 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4168 * @param TIMx Timer instance
4169 * @retval State of bit (1 or 0).
4170 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4171 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4172 {
4173 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4174 }
4175
4176 /**
4177 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4178 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4179 * @param TIMx Timer instance
4180 * @retval None
4181 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4182 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4183 {
4184 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4185 }
4186
4187 /**
4188 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4189 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4190 * @param TIMx Timer instance
4191 * @retval State of bit (1 or 0).
4192 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4193 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4194 {
4195 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4196 }
4197
4198 /**
4199 * @brief Clear the commutation interrupt flag (COMIF).
4200 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4201 * @param TIMx Timer instance
4202 * @retval None
4203 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4204 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4205 {
4206 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4207 }
4208
4209 /**
4210 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4211 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4212 * @param TIMx Timer instance
4213 * @retval State of bit (1 or 0).
4214 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4215 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4216 {
4217 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4218 }
4219
4220 /**
4221 * @brief Clear the trigger interrupt flag (TIF).
4222 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4223 * @param TIMx Timer instance
4224 * @retval None
4225 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4226 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4227 {
4228 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4229 }
4230
4231 /**
4232 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4233 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4234 * @param TIMx Timer instance
4235 * @retval State of bit (1 or 0).
4236 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4238 {
4239 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4240 }
4241
4242 /**
4243 * @brief Clear the break interrupt flag (BIF).
4244 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4245 * @param TIMx Timer instance
4246 * @retval None
4247 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4248 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4249 {
4250 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4251 }
4252
4253 /**
4254 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4255 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4256 * @param TIMx Timer instance
4257 * @retval State of bit (1 or 0).
4258 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4260 {
4261 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4262 }
4263
4264 /**
4265 * @brief Clear the break 2 interrupt flag (B2IF).
4266 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4267 * @param TIMx Timer instance
4268 * @retval None
4269 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4270 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4271 {
4272 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4273 }
4274
4275 /**
4276 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4277 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4278 * @param TIMx Timer instance
4279 * @retval State of bit (1 or 0).
4280 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4281 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4282 {
4283 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4284 }
4285
4286 /**
4287 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4288 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4289 * @param TIMx Timer instance
4290 * @retval None
4291 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4292 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4293 {
4294 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4295 }
4296
4297 /**
4298 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4299 * (Capture/Compare 1 interrupt is pending).
4300 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4301 * @param TIMx Timer instance
4302 * @retval State of bit (1 or 0).
4303 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4304 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4305 {
4306 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4307 }
4308
4309 /**
4310 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4311 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4312 * @param TIMx Timer instance
4313 * @retval None
4314 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4315 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4316 {
4317 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4318 }
4319
4320 /**
4321 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4322 * (Capture/Compare 2 over-capture interrupt is pending).
4323 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4324 * @param TIMx Timer instance
4325 * @retval State of bit (1 or 0).
4326 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4327 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4328 {
4329 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4330 }
4331
4332 /**
4333 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4334 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4335 * @param TIMx Timer instance
4336 * @retval None
4337 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4338 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4339 {
4340 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4341 }
4342
4343 /**
4344 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4345 * (Capture/Compare 3 over-capture interrupt is pending).
4346 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4347 * @param TIMx Timer instance
4348 * @retval State of bit (1 or 0).
4349 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4350 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4351 {
4352 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4353 }
4354
4355 /**
4356 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4357 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4358 * @param TIMx Timer instance
4359 * @retval None
4360 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4361 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4362 {
4363 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4364 }
4365
4366 /**
4367 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4368 * (Capture/Compare 4 over-capture interrupt is pending).
4369 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4370 * @param TIMx Timer instance
4371 * @retval State of bit (1 or 0).
4372 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4373 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4374 {
4375 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4376 }
4377
4378 /**
4379 * @brief Clear the system break interrupt flag (SBIF).
4380 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4381 * @param TIMx Timer instance
4382 * @retval None
4383 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4384 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4385 {
4386 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4387 }
4388
4389 /**
4390 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4391 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4392 * @param TIMx Timer instance
4393 * @retval State of bit (1 or 0).
4394 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4395 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4396 {
4397 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4398 }
4399
4400 /**
4401 * @}
4402 */
4403
4404 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4405 * @{
4406 */
4407 /**
4408 * @brief Enable update interrupt (UIE).
4409 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4410 * @param TIMx Timer instance
4411 * @retval None
4412 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4413 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4414 {
4415 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4416 }
4417
4418 /**
4419 * @brief Disable update interrupt (UIE).
4420 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4421 * @param TIMx Timer instance
4422 * @retval None
4423 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4424 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4425 {
4426 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4427 }
4428
4429 /**
4430 * @brief Indicates whether the update interrupt (UIE) is enabled.
4431 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4432 * @param TIMx Timer instance
4433 * @retval State of bit (1 or 0).
4434 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4435 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4436 {
4437 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4438 }
4439
4440 /**
4441 * @brief Enable capture/compare 1 interrupt (CC1IE).
4442 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4443 * @param TIMx Timer instance
4444 * @retval None
4445 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4446 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4447 {
4448 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4449 }
4450
4451 /**
4452 * @brief Disable capture/compare 1 interrupt (CC1IE).
4453 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4454 * @param TIMx Timer instance
4455 * @retval None
4456 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4457 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4458 {
4459 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4460 }
4461
4462 /**
4463 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4464 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4465 * @param TIMx Timer instance
4466 * @retval State of bit (1 or 0).
4467 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4468 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4469 {
4470 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4471 }
4472
4473 /**
4474 * @brief Enable capture/compare 2 interrupt (CC2IE).
4475 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4476 * @param TIMx Timer instance
4477 * @retval None
4478 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4479 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4480 {
4481 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4482 }
4483
4484 /**
4485 * @brief Disable capture/compare 2 interrupt (CC2IE).
4486 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4487 * @param TIMx Timer instance
4488 * @retval None
4489 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4490 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4491 {
4492 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4493 }
4494
4495 /**
4496 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4497 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4498 * @param TIMx Timer instance
4499 * @retval State of bit (1 or 0).
4500 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4501 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4502 {
4503 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4504 }
4505
4506 /**
4507 * @brief Enable capture/compare 3 interrupt (CC3IE).
4508 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4509 * @param TIMx Timer instance
4510 * @retval None
4511 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4512 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4513 {
4514 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4515 }
4516
4517 /**
4518 * @brief Disable capture/compare 3 interrupt (CC3IE).
4519 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4520 * @param TIMx Timer instance
4521 * @retval None
4522 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4523 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4524 {
4525 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4526 }
4527
4528 /**
4529 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4530 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4531 * @param TIMx Timer instance
4532 * @retval State of bit (1 or 0).
4533 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4534 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4535 {
4536 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4537 }
4538
4539 /**
4540 * @brief Enable capture/compare 4 interrupt (CC4IE).
4541 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4542 * @param TIMx Timer instance
4543 * @retval None
4544 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4545 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4546 {
4547 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4548 }
4549
4550 /**
4551 * @brief Disable capture/compare 4 interrupt (CC4IE).
4552 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4553 * @param TIMx Timer instance
4554 * @retval None
4555 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4556 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4557 {
4558 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4559 }
4560
4561 /**
4562 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4563 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4564 * @param TIMx Timer instance
4565 * @retval State of bit (1 or 0).
4566 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4567 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4568 {
4569 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4570 }
4571
4572 /**
4573 * @brief Enable commutation interrupt (COMIE).
4574 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4575 * @param TIMx Timer instance
4576 * @retval None
4577 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4578 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4579 {
4580 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4581 }
4582
4583 /**
4584 * @brief Disable commutation interrupt (COMIE).
4585 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4586 * @param TIMx Timer instance
4587 * @retval None
4588 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4589 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4590 {
4591 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4592 }
4593
4594 /**
4595 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4596 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4597 * @param TIMx Timer instance
4598 * @retval State of bit (1 or 0).
4599 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4600 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4601 {
4602 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4603 }
4604
4605 /**
4606 * @brief Enable trigger interrupt (TIE).
4607 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4608 * @param TIMx Timer instance
4609 * @retval None
4610 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4611 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4612 {
4613 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4614 }
4615
4616 /**
4617 * @brief Disable trigger interrupt (TIE).
4618 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4619 * @param TIMx Timer instance
4620 * @retval None
4621 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4622 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4623 {
4624 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4625 }
4626
4627 /**
4628 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4629 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4630 * @param TIMx Timer instance
4631 * @retval State of bit (1 or 0).
4632 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4633 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4634 {
4635 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4636 }
4637
4638 /**
4639 * @brief Enable break interrupt (BIE).
4640 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4641 * @param TIMx Timer instance
4642 * @retval None
4643 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4644 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4645 {
4646 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4647 }
4648
4649 /**
4650 * @brief Disable break interrupt (BIE).
4651 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4652 * @param TIMx Timer instance
4653 * @retval None
4654 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4655 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4656 {
4657 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4658 }
4659
4660 /**
4661 * @brief Indicates whether the break interrupt (BIE) is enabled.
4662 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4663 * @param TIMx Timer instance
4664 * @retval State of bit (1 or 0).
4665 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4666 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4667 {
4668 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4669 }
4670
4671 /**
4672 * @}
4673 */
4674
4675 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4676 * @{
4677 */
4678 /**
4679 * @brief Enable update DMA request (UDE).
4680 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4681 * @param TIMx Timer instance
4682 * @retval None
4683 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4684 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4685 {
4686 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4687 }
4688
4689 /**
4690 * @brief Disable update DMA request (UDE).
4691 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4692 * @param TIMx Timer instance
4693 * @retval None
4694 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4695 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4696 {
4697 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4698 }
4699
4700 /**
4701 * @brief Indicates whether the update DMA request (UDE) is enabled.
4702 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4703 * @param TIMx Timer instance
4704 * @retval State of bit (1 or 0).
4705 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4706 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4707 {
4708 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4709 }
4710
4711 /**
4712 * @brief Enable capture/compare 1 DMA request (CC1DE).
4713 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4714 * @param TIMx Timer instance
4715 * @retval None
4716 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4717 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4718 {
4719 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4720 }
4721
4722 /**
4723 * @brief Disable capture/compare 1 DMA request (CC1DE).
4724 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4725 * @param TIMx Timer instance
4726 * @retval None
4727 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4728 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4729 {
4730 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4731 }
4732
4733 /**
4734 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4735 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4736 * @param TIMx Timer instance
4737 * @retval State of bit (1 or 0).
4738 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4739 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4740 {
4741 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4742 }
4743
4744 /**
4745 * @brief Enable capture/compare 2 DMA request (CC2DE).
4746 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4747 * @param TIMx Timer instance
4748 * @retval None
4749 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4750 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4751 {
4752 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4753 }
4754
4755 /**
4756 * @brief Disable capture/compare 2 DMA request (CC2DE).
4757 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4758 * @param TIMx Timer instance
4759 * @retval None
4760 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4761 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4762 {
4763 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4764 }
4765
4766 /**
4767 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4768 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4769 * @param TIMx Timer instance
4770 * @retval State of bit (1 or 0).
4771 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4772 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4773 {
4774 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4775 }
4776
4777 /**
4778 * @brief Enable capture/compare 3 DMA request (CC3DE).
4779 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4780 * @param TIMx Timer instance
4781 * @retval None
4782 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4783 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4784 {
4785 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4786 }
4787
4788 /**
4789 * @brief Disable capture/compare 3 DMA request (CC3DE).
4790 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4791 * @param TIMx Timer instance
4792 * @retval None
4793 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4794 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4795 {
4796 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4797 }
4798
4799 /**
4800 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4801 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4802 * @param TIMx Timer instance
4803 * @retval State of bit (1 or 0).
4804 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4805 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4806 {
4807 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4808 }
4809
4810 /**
4811 * @brief Enable capture/compare 4 DMA request (CC4DE).
4812 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4813 * @param TIMx Timer instance
4814 * @retval None
4815 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4816 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4817 {
4818 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4819 }
4820
4821 /**
4822 * @brief Disable capture/compare 4 DMA request (CC4DE).
4823 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4824 * @param TIMx Timer instance
4825 * @retval None
4826 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4827 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4828 {
4829 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4830 }
4831
4832 /**
4833 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4834 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4835 * @param TIMx Timer instance
4836 * @retval State of bit (1 or 0).
4837 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4838 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4839 {
4840 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4841 }
4842
4843 /**
4844 * @brief Enable commutation DMA request (COMDE).
4845 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4846 * @param TIMx Timer instance
4847 * @retval None
4848 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4849 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4850 {
4851 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4852 }
4853
4854 /**
4855 * @brief Disable commutation DMA request (COMDE).
4856 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4857 * @param TIMx Timer instance
4858 * @retval None
4859 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4860 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4861 {
4862 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4863 }
4864
4865 /**
4866 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4867 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4868 * @param TIMx Timer instance
4869 * @retval State of bit (1 or 0).
4870 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4871 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4872 {
4873 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4874 }
4875
4876 /**
4877 * @brief Enable trigger interrupt (TDE).
4878 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4879 * @param TIMx Timer instance
4880 * @retval None
4881 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4882 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4883 {
4884 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4885 }
4886
4887 /**
4888 * @brief Disable trigger interrupt (TDE).
4889 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4890 * @param TIMx Timer instance
4891 * @retval None
4892 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4893 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4894 {
4895 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4896 }
4897
4898 /**
4899 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4900 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4901 * @param TIMx Timer instance
4902 * @retval State of bit (1 or 0).
4903 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4904 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4905 {
4906 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4907 }
4908
4909 /**
4910 * @}
4911 */
4912
4913 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4914 * @{
4915 */
4916 /**
4917 * @brief Generate an update event.
4918 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4919 * @param TIMx Timer instance
4920 * @retval None
4921 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4922 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4923 {
4924 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4925 }
4926
4927 /**
4928 * @brief Generate Capture/Compare 1 event.
4929 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4930 * @param TIMx Timer instance
4931 * @retval None
4932 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4933 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4934 {
4935 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4936 }
4937
4938 /**
4939 * @brief Generate Capture/Compare 2 event.
4940 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4941 * @param TIMx Timer instance
4942 * @retval None
4943 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4944 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4945 {
4946 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4947 }
4948
4949 /**
4950 * @brief Generate Capture/Compare 3 event.
4951 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4952 * @param TIMx Timer instance
4953 * @retval None
4954 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4955 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4956 {
4957 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4958 }
4959
4960 /**
4961 * @brief Generate Capture/Compare 4 event.
4962 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4963 * @param TIMx Timer instance
4964 * @retval None
4965 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4966 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4967 {
4968 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4969 }
4970
4971 /**
4972 * @brief Generate commutation event.
4973 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4974 * @param TIMx Timer instance
4975 * @retval None
4976 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4977 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4978 {
4979 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4980 }
4981
4982 /**
4983 * @brief Generate trigger event.
4984 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4985 * @param TIMx Timer instance
4986 * @retval None
4987 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4988 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4989 {
4990 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4991 }
4992
4993 /**
4994 * @brief Generate break event.
4995 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4996 * @param TIMx Timer instance
4997 * @retval None
4998 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4999 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5000 {
5001 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5002 }
5003
5004 /**
5005 * @brief Generate break 2 event.
5006 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5007 * @param TIMx Timer instance
5008 * @retval None
5009 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5010 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5011 {
5012 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5013 }
5014
5015 /**
5016 * @}
5017 */
5018
5019 #if defined(USE_FULL_LL_DRIVER)
5020 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5021 * @{
5022 */
5023
5024 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5025 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5026 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5027 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5028 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5029 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5030 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5031 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5032 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5033 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5034 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5035 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5036 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5037 /**
5038 * @}
5039 */
5040 #endif /* USE_FULL_LL_DRIVER */
5041
5042 /**
5043 * @}
5044 */
5045
5046 /**
5047 * @}
5048 */
5049
5050 #endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 || TIM15 || TIM16 */
5051
5052 /**
5053 * @}
5054 */
5055
5056 #ifdef __cplusplus
5057 }
5058 #endif
5059
5060 #endif /* __STM32U0xx_LL_TIM_H */
5061
