1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F1xx_LL_TIM_H
21 #define __STM32F1xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f1xx.h"
29
30 /** @addtogroup STM32F1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 2U, /* 1: CC1NP */
82 4U, /* 2: CC2P */
83 6U, /* 3: CC2NP */
84 8U, /* 4: CC3P */
85 10U, /* 5: CC3NP */
86 12U /* 6: CC4P */
87 };
88
89 static const uint8_t SHIFT_TAB_OISx[] =
90 {
91 0U, /* 0: OIS1 */
92 1U, /* 1: OIS1N */
93 2U, /* 2: OIS2 */
94 3U, /* 3: OIS2N */
95 4U, /* 4: OIS3 */
96 5U, /* 5: OIS3N */
97 6U /* 6: OIS4 */
98 };
99 /**
100 * @}
101 */
102
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
105 * @{
106 */
107
108
109
110 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
111 #define DT_DELAY_1 ((uint8_t)0x7F)
112 #define DT_DELAY_2 ((uint8_t)0x3F)
113 #define DT_DELAY_3 ((uint8_t)0x1F)
114 #define DT_DELAY_4 ((uint8_t)0x1F)
115
116 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
117 #define DT_RANGE_1 ((uint8_t)0x00)
118 #define DT_RANGE_2 ((uint8_t)0x80)
119 #define DT_RANGE_3 ((uint8_t)0xC0)
120 #define DT_RANGE_4 ((uint8_t)0xE0)
121
122
123 /**
124 * @}
125 */
126
127 /* Private macros ------------------------------------------------------------*/
128 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
129 * @{
130 */
131 /** @brief Convert channel id into channel index.
132 * @param __CHANNEL__ This parameter can be one of the following values:
133 * @arg @ref LL_TIM_CHANNEL_CH1
134 * @arg @ref LL_TIM_CHANNEL_CH1N
135 * @arg @ref LL_TIM_CHANNEL_CH2
136 * @arg @ref LL_TIM_CHANNEL_CH2N
137 * @arg @ref LL_TIM_CHANNEL_CH3
138 * @arg @ref LL_TIM_CHANNEL_CH3N
139 * @arg @ref LL_TIM_CHANNEL_CH4
140 * @retval none
141 */
142 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
143 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
144 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
145 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
146 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
147 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
148 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
149
150 /** @brief Calculate the deadtime sampling period(in ps).
151 * @param __TIMCLK__ timer input clock frequency (in Hz).
152 * @param __CKD__ This parameter can be one of the following values:
153 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
154 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
155 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
156 * @retval none
157 */
158 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
159 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
160 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
161 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
162 /**
163 * @}
164 */
165
166
167 /* Exported types ------------------------------------------------------------*/
168 #if defined(USE_FULL_LL_DRIVER)
169 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
170 * @{
171 */
172
173 /**
174 * @brief TIM Time Base configuration structure definition.
175 */
176 typedef struct
177 {
178 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
179 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
180
181 This feature can be modified afterwards using unitary function
182 @ref LL_TIM_SetPrescaler().*/
183
184 uint32_t CounterMode; /*!< Specifies the counter mode.
185 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
186
187 This feature can be modified afterwards using unitary function
188 @ref LL_TIM_SetCounterMode().*/
189
190 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
191 Auto-Reload Register at the next update event.
192 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
193 Some timer instances may support 32 bits counters. In that case this parameter must
194 be a number between 0x0000 and 0xFFFFFFFF.
195
196 This feature can be modified afterwards using unitary function
197 @ref LL_TIM_SetAutoReload().*/
198
199 uint32_t ClockDivision; /*!< Specifies the clock division.
200 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
201
202 This feature can be modified afterwards using unitary function
203 @ref LL_TIM_SetClockDivision().*/
204
205 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
206 reaches zero, an update event is generated and counting restarts
207 from the RCR value (N).
208 This means in PWM mode that (N+1) corresponds to:
209 - the number of PWM periods in edge-aligned mode
210 - the number of half PWM period in center-aligned mode
211 GP timers: this parameter must be a number between Min_Data = 0x00 and
212 Max_Data = 0xFF.
213 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
214 Max_Data = 0xFFFF.
215
216 This feature can be modified afterwards using unitary function
217 @ref LL_TIM_SetRepetitionCounter().*/
218 } LL_TIM_InitTypeDef;
219
220 /**
221 * @brief TIM Output Compare configuration structure definition.
222 */
223 typedef struct
224 {
225 uint32_t OCMode; /*!< Specifies the output mode.
226 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
227
228 This feature can be modified afterwards using unitary function
229 @ref LL_TIM_OC_SetMode().*/
230
231 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
232 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
233
234 This feature can be modified afterwards using unitary functions
235 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
236
237 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
238 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
239
240 This feature can be modified afterwards using unitary functions
241 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
242
243 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
244 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
245
246 This feature can be modified afterwards using unitary function
247 LL_TIM_OC_SetCompareCHx (x=1..6).*/
248
249 uint32_t OCPolarity; /*!< Specifies the output polarity.
250 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
251
252 This feature can be modified afterwards using unitary function
253 @ref LL_TIM_OC_SetPolarity().*/
254
255 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
256 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_OC_SetPolarity().*/
260
261
262 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
263 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_OC_SetIdleState().*/
267
268 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
269 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
270
271 This feature can be modified afterwards using unitary function
272 @ref LL_TIM_OC_SetIdleState().*/
273 } LL_TIM_OC_InitTypeDef;
274
275 /**
276 * @brief TIM Input Capture configuration structure definition.
277 */
278
279 typedef struct
280 {
281
282 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
283 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
284
285 This feature can be modified afterwards using unitary function
286 @ref LL_TIM_IC_SetPolarity().*/
287
288 uint32_t ICActiveInput; /*!< Specifies the input.
289 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
290
291 This feature can be modified afterwards using unitary function
292 @ref LL_TIM_IC_SetActiveInput().*/
293
294 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
295 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
296
297 This feature can be modified afterwards using unitary function
298 @ref LL_TIM_IC_SetPrescaler().*/
299
300 uint32_t ICFilter; /*!< Specifies the input capture filter.
301 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_IC_SetFilter().*/
305 } LL_TIM_IC_InitTypeDef;
306
307
308 /**
309 * @brief TIM Encoder interface configuration structure definition.
310 */
311 typedef struct
312 {
313 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
314 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
315
316 This feature can be modified afterwards using unitary function
317 @ref LL_TIM_SetEncoderMode().*/
318
319 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
320 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_IC_SetPolarity().*/
324
325 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
326 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetPrescaler().*/
336
337 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
338 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetFilter().*/
342
343 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
344 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
345
346 This feature can be modified afterwards using unitary function
347 @ref LL_TIM_IC_SetPolarity().*/
348
349 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
350 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_IC_SetActiveInput().*/
354
355 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
356 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetPrescaler().*/
360
361 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
362 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetFilter().*/
366
367 } LL_TIM_ENCODER_InitTypeDef;
368
369 /**
370 * @brief TIM Hall sensor interface configuration structure definition.
371 */
372 typedef struct
373 {
374
375 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
376 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
377
378 This feature can be modified afterwards using unitary function
379 @ref LL_TIM_IC_SetPolarity().*/
380
381 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
382 Prescaler must be set to get a maximum counter period longer than the
383 time interval between 2 consecutive changes on the Hall inputs.
384 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetPrescaler().*/
388
389 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
390 This parameter can be a value of
391 @ref TIM_LL_EC_IC_FILTER.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetFilter().*/
395
396 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
397 A positive pulse (TRGO event) is generated with a programmable delay every time
398 a change occurs on the Hall inputs.
399 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
400
401 This feature can be modified afterwards using unitary function
402 @ref LL_TIM_OC_SetCompareCH2().*/
403 } LL_TIM_HALLSENSOR_InitTypeDef;
404
405 /**
406 * @brief BDTR (Break and Dead Time) structure definition
407 */
408 typedef struct
409 {
410 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
411 This parameter can be a value of @ref TIM_LL_EC_OSSR
412
413 This feature can be modified afterwards using unitary function
414 @ref LL_TIM_SetOffStates()
415
416 @note This bit-field cannot be modified as long as LOCK level 2 has been
417 programmed. */
418
419 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
420 This parameter can be a value of @ref TIM_LL_EC_OSSI
421
422 This feature can be modified afterwards using unitary function
423 @ref LL_TIM_SetOffStates()
424
425 @note This bit-field cannot be modified as long as LOCK level 2 has been
426 programmed. */
427
428 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
429 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
430
431 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
432 register has been written, their content is frozen until the next reset.*/
433
434 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
435 switching-on of the outputs.
436 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
437
438 This feature can be modified afterwards using unitary function
439 @ref LL_TIM_OC_SetDeadTime()
440
441 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
442 programmed. */
443
444 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
445 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
446
447 This feature can be modified afterwards using unitary functions
448 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
449
450 @note This bit-field can not be modified as long as LOCK level 1 has been
451 programmed. */
452
453 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
454 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
455
456 This feature can be modified afterwards using unitary function
457 @ref LL_TIM_ConfigBRK()
458
459 @note This bit-field can not be modified as long as LOCK level 1 has been
460 programmed. */
461
462 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
463 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
464
465 This feature can be modified afterwards using unitary functions
466 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
467
468 @note This bit-field can not be modified as long as LOCK level 1 has been
469 programmed. */
470 } LL_TIM_BDTR_InitTypeDef;
471
472 /**
473 * @}
474 */
475 #endif /* USE_FULL_LL_DRIVER */
476
477 /* Exported constants --------------------------------------------------------*/
478 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
479 * @{
480 */
481
482 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
483 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
484 * @{
485 */
486 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
487 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
488 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
489 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
490 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
491 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
492 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
493 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
494 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
495 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
496 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
497 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
498 /**
499 * @}
500 */
501
502 #if defined(USE_FULL_LL_DRIVER)
503 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
504 * @{
505 */
506 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
507 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
508 /**
509 * @}
510 */
511
512 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
513 * @{
514 */
515 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
516 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
517 /**
518 * @}
519 */
520 #endif /* USE_FULL_LL_DRIVER */
521
522 /** @defgroup TIM_LL_EC_IT IT Defines
523 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
524 * @{
525 */
526 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
527 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
528 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
529 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
530 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
531 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
532 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
533 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
534 /**
535 * @}
536 */
537
538 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
539 * @{
540 */
541 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
542 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
543 /**
544 * @}
545 */
546
547 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
548 * @{
549 */
550 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
551 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
552 /**
553 * @}
554 */
555
556 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
557 * @{
558 */
559 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
560 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
561 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
562 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
563 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
564 /**
565 * @}
566 */
567
568 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
569 * @{
570 */
571 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
572 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
573 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
574 /**
575 * @}
576 */
577
578 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
579 * @{
580 */
581 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
582 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
583 /**
584 * @}
585 */
586
587 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
588 * @{
589 */
590 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
591 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
592 /**
593 * @}
594 */
595
596 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
597 * @{
598 */
599 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
600 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
606 * @{
607 */
608 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
609 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
610 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
611 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
612 /**
613 * @}
614 */
615
616 /** @defgroup TIM_LL_EC_CHANNEL Channel
617 * @{
618 */
619 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
620 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
621 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
622 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
623 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
624 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
625 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
626 /**
627 * @}
628 */
629
630 #if defined(USE_FULL_LL_DRIVER)
631 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
632 * @{
633 */
634 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
635 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
636 /**
637 * @}
638 */
639 #endif /* USE_FULL_LL_DRIVER */
640
641 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
642 * @{
643 */
644 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
645 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
646 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
647 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
648 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
649 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
650 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
651 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
657 * @{
658 */
659 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
660 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
661 /**
662 * @}
663 */
664
665 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
666 * @{
667 */
668 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
669 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
670 /**
671 * @}
672 */
673
674
675 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
676 * @{
677 */
678 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
679 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
680 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
681 /**
682 * @}
683 */
684
685 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
686 * @{
687 */
688 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
689 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
690 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
691 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
697 * @{
698 */
699 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
700 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
701 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
702 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
703 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
704 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
705 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
706 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
707 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
708 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
709 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
710 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
711 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
712 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
713 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
714 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
715 /**
716 * @}
717 */
718
719 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
720 * @{
721 */
722 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
723 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
724 /**
725 * @}
726 */
727
728 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
729 * @{
730 */
731 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
732 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
733 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
734 /**
735 * @}
736 */
737
738 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
739 * @{
740 */
741 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
742 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
743 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
744 /**
745 * @}
746 */
747
748 /** @defgroup TIM_LL_EC_TRGO Trigger Output
749 * @{
750 */
751 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
752 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
753 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
754 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
755 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
756 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
757 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
758 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
759 /**
760 * @}
761 */
762
763
764 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
765 * @{
766 */
767 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
768 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
769 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
770 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
771 /**
772 * @}
773 */
774
775 /** @defgroup TIM_LL_EC_TS Trigger Selection
776 * @{
777 */
778 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
779 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
780 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
781 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
782 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
783 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
784 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
785 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
791 * @{
792 */
793 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
794 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
800 * @{
801 */
802 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
803 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
804 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
805 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
806 /**
807 * @}
808 */
809
810 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
811 * @{
812 */
813 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
814 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
815 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
816 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
817 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
818 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
819 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
820 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
821 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
822 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
823 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
824 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
825 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
826 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
827 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
828 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
829 /**
830 * @}
831 */
832
833
834 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
835 * @{
836 */
837 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
838 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
839 /**
840 * @}
841 */
842
843
844
845
846 /** @defgroup TIM_LL_EC_OSSI OSSI
847 * @{
848 */
849 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
850 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_OSSR OSSR
856 * @{
857 */
858 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
859 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
860 /**
861 * @}
862 */
863
864
865 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
866 * @{
867 */
868 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
869 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
870 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
871 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
872 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
873 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
874 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
875 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
876 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
891 * @{
892 */
893 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
894 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
895 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
896 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
897 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
898 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
899 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
900 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
901 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
911 /**
912 * @}
913 */
914
915
916
917 /**
918 * @}
919 */
920
921 /* Exported macro ------------------------------------------------------------*/
922 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
923 * @{
924 */
925
926 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
927 * @{
928 */
929 /**
930 * @brief Write a value in TIM register.
931 * @param __INSTANCE__ TIM Instance
932 * @param __REG__ Register to be written
933 * @param __VALUE__ Value to be written in the register
934 * @retval None
935 */
936 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
937
938 /**
939 * @brief Read a value in TIM register.
940 * @param __INSTANCE__ TIM Instance
941 * @param __REG__ Register to be read
942 * @retval Register value
943 */
944 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
945 /**
946 * @}
947 */
948
949 /**
950 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
951 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
952 * @param __TIMCLK__ timer input clock frequency (in Hz)
953 * @param __CKD__ This parameter can be one of the following values:
954 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
955 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
956 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
957 * @param __DT__ deadtime duration (in ns)
958 * @retval DTG[0:7]
959 */
960 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
961 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
962 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
963 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
964 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
965 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
966 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
967 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
968 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
969 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
970 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
971 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
972 0U)
973
974 /**
975 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
976 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
977 * @param __TIMCLK__ timer input clock frequency (in Hz)
978 * @param __CNTCLK__ counter clock frequency (in Hz)
979 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
980 */
981 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
982 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
983
984 /**
985 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
986 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
987 * @param __TIMCLK__ timer input clock frequency (in Hz)
988 * @param __PSC__ prescaler
989 * @param __FREQ__ output signal frequency (in Hz)
990 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
991 */
992 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
993 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
994
995 /**
996 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
997 * active/inactive delay.
998 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
999 * @param __TIMCLK__ timer input clock frequency (in Hz)
1000 * @param __PSC__ prescaler
1001 * @param __DELAY__ timer output compare active/inactive delay (in us)
1002 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1003 */
1004 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1005 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1006 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1007
1008 /**
1009 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1010 * (when the timer operates in one pulse mode).
1011 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1012 * @param __TIMCLK__ timer input clock frequency (in Hz)
1013 * @param __PSC__ prescaler
1014 * @param __DELAY__ timer output compare active/inactive delay (in us)
1015 * @param __PULSE__ pulse duration (in us)
1016 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1017 */
1018 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1019 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1020 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1021
1022 /**
1023 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1024 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1025 * @param __ICPSC__ This parameter can be one of the following values:
1026 * @arg @ref LL_TIM_ICPSC_DIV1
1027 * @arg @ref LL_TIM_ICPSC_DIV2
1028 * @arg @ref LL_TIM_ICPSC_DIV4
1029 * @arg @ref LL_TIM_ICPSC_DIV8
1030 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1031 */
1032 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1033 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1034
1035
1036 /**
1037 * @}
1038 */
1039
1040 /* Exported functions --------------------------------------------------------*/
1041 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1042 * @{
1043 */
1044
1045 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1046 * @{
1047 */
1048 /**
1049 * @brief Enable timer counter.
1050 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1051 * @param TIMx Timer instance
1052 * @retval None
1053 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1054 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1055 {
1056 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1057 }
1058
1059 /**
1060 * @brief Disable timer counter.
1061 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1062 * @param TIMx Timer instance
1063 * @retval None
1064 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1065 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1066 {
1067 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1068 }
1069
1070 /**
1071 * @brief Indicates whether the timer counter is enabled.
1072 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1073 * @param TIMx Timer instance
1074 * @retval State of bit (1 or 0).
1075 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1076 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1077 {
1078 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1079 }
1080
1081 /**
1082 * @brief Enable update event generation.
1083 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1084 * @param TIMx Timer instance
1085 * @retval None
1086 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1087 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1088 {
1089 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1090 }
1091
1092 /**
1093 * @brief Disable update event generation.
1094 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1095 * @param TIMx Timer instance
1096 * @retval None
1097 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1098 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1099 {
1100 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1101 }
1102
1103 /**
1104 * @brief Indicates whether update event generation is enabled.
1105 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1106 * @param TIMx Timer instance
1107 * @retval Inverted state of bit (0 or 1).
1108 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1109 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1110 {
1111 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1112 }
1113
1114 /**
1115 * @brief Set update event source
1116 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1117 * generate an update interrupt or DMA request if enabled:
1118 * - Counter overflow/underflow
1119 * - Setting the UG bit
1120 * - Update generation through the slave mode controller
1121 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1122 * overflow/underflow generates an update interrupt or DMA request if enabled.
1123 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1124 * @param TIMx Timer instance
1125 * @param UpdateSource This parameter can be one of the following values:
1126 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1127 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1128 * @retval None
1129 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1130 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1131 {
1132 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1133 }
1134
1135 /**
1136 * @brief Get actual event update source
1137 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1138 * @param TIMx Timer instance
1139 * @retval Returned value can be one of the following values:
1140 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1141 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1142 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1143 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1144 {
1145 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1146 }
1147
1148 /**
1149 * @brief Set one pulse mode (one shot v.s. repetitive).
1150 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1151 * @param TIMx Timer instance
1152 * @param OnePulseMode This parameter can be one of the following values:
1153 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1154 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1155 * @retval None
1156 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1157 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1158 {
1159 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1160 }
1161
1162 /**
1163 * @brief Get actual one pulse mode.
1164 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1165 * @param TIMx Timer instance
1166 * @retval Returned value can be one of the following values:
1167 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1168 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1169 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1170 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1171 {
1172 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1173 }
1174
1175 /**
1176 * @brief Set the timer counter counting mode.
1177 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1178 * check whether or not the counter mode selection feature is supported
1179 * by a timer instance.
1180 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1181 * requires a timer reset to avoid unexpected direction
1182 * due to DIR bit readonly in center aligned mode.
1183 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1184 * CR1 CMS LL_TIM_SetCounterMode
1185 * @param TIMx Timer instance
1186 * @param CounterMode This parameter can be one of the following values:
1187 * @arg @ref LL_TIM_COUNTERMODE_UP
1188 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1189 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1190 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1191 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1192 * @retval None
1193 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1194 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1195 {
1196 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1197 }
1198
1199 /**
1200 * @brief Get actual counter mode.
1201 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1202 * check whether or not the counter mode selection feature is supported
1203 * by a timer instance.
1204 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1205 * CR1 CMS LL_TIM_GetCounterMode
1206 * @param TIMx Timer instance
1207 * @retval Returned value can be one of the following values:
1208 * @arg @ref LL_TIM_COUNTERMODE_UP
1209 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1210 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1211 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1212 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1213 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1214 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1215 {
1216 uint32_t counter_mode;
1217
1218 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1219
1220 if (counter_mode == 0U)
1221 {
1222 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1223 }
1224
1225 return counter_mode;
1226 }
1227
1228 /**
1229 * @brief Enable auto-reload (ARR) preload.
1230 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1231 * @param TIMx Timer instance
1232 * @retval None
1233 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1234 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1235 {
1236 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1237 }
1238
1239 /**
1240 * @brief Disable auto-reload (ARR) preload.
1241 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1242 * @param TIMx Timer instance
1243 * @retval None
1244 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1245 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1246 {
1247 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1248 }
1249
1250 /**
1251 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1252 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1253 * @param TIMx Timer instance
1254 * @retval State of bit (1 or 0).
1255 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1256 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1257 {
1258 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1259 }
1260
1261 /**
1262 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1263 * (when supported) and the digital filters.
1264 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1265 * whether or not the clock division feature is supported by the timer
1266 * instance.
1267 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1268 * @param TIMx Timer instance
1269 * @param ClockDivision This parameter can be one of the following values:
1270 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1271 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1272 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1273 * @retval None
1274 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1275 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1276 {
1277 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1278 }
1279
1280 /**
1281 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1282 * generators (when supported) and the digital filters.
1283 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1284 * whether or not the clock division feature is supported by the timer
1285 * instance.
1286 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1287 * @param TIMx Timer instance
1288 * @retval Returned value can be one of the following values:
1289 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1290 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1291 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1292 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1293 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1294 {
1295 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1296 }
1297
1298 /**
1299 * @brief Set the counter value.
1300 * @rmtoll CNT CNT LL_TIM_SetCounter
1301 * @param TIMx Timer instance
1302 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1303 * @retval None
1304 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1305 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1306 {
1307 WRITE_REG(TIMx->CNT, Counter);
1308 }
1309
1310 /**
1311 * @brief Get the counter value.
1312 * @rmtoll CNT CNT LL_TIM_GetCounter
1313 * @param TIMx Timer instance
1314 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
1315 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1316 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1317 {
1318 return (uint32_t)(READ_REG(TIMx->CNT));
1319 }
1320
1321 /**
1322 * @brief Get the current direction of the counter
1323 * @rmtoll CR1 DIR LL_TIM_GetDirection
1324 * @param TIMx Timer instance
1325 * @retval Returned value can be one of the following values:
1326 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1327 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1328 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1329 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1330 {
1331 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1332 }
1333
1334 /**
1335 * @brief Set the prescaler value.
1336 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1337 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1338 * prescaler ratio is taken into account at the next update event.
1339 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1340 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1341 * @param TIMx Timer instance
1342 * @param Prescaler between Min_Data=0 and Max_Data=65535
1343 * @retval None
1344 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1345 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1346 {
1347 WRITE_REG(TIMx->PSC, Prescaler);
1348 }
1349
1350 /**
1351 * @brief Get the prescaler value.
1352 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1353 * @param TIMx Timer instance
1354 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1355 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1356 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1357 {
1358 return (uint32_t)(READ_REG(TIMx->PSC));
1359 }
1360
1361 /**
1362 * @brief Set the auto-reload value.
1363 * @note The counter is blocked while the auto-reload value is null.
1364 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1365 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1366 * @param TIMx Timer instance
1367 * @param AutoReload between Min_Data=0 and Max_Data=65535
1368 * @retval None
1369 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1370 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1371 {
1372 WRITE_REG(TIMx->ARR, AutoReload);
1373 }
1374
1375 /**
1376 * @brief Get the auto-reload value.
1377 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1378 * @param TIMx Timer instance
1379 * @retval Auto-reload value
1380 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1381 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1382 {
1383 return (uint32_t)(READ_REG(TIMx->ARR));
1384 }
1385
1386 /**
1387 * @brief Set the repetition counter value.
1388 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1389 * whether or not a timer instance supports a repetition counter.
1390 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1391 * @param TIMx Timer instance
1392 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1393 * @retval None
1394 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1395 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1396 {
1397 WRITE_REG(TIMx->RCR, RepetitionCounter);
1398 }
1399
1400 /**
1401 * @brief Get the repetition counter value.
1402 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1403 * whether or not a timer instance supports a repetition counter.
1404 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1405 * @param TIMx Timer instance
1406 * @retval Repetition counter value
1407 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1408 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1409 {
1410 return (uint32_t)(READ_REG(TIMx->RCR));
1411 }
1412
1413 /**
1414 * @}
1415 */
1416
1417 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1418 * @{
1419 */
1420 /**
1421 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1422 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1423 * they are updated only when a commutation event (COM) occurs.
1424 * @note Only on channels that have a complementary output.
1425 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1426 * whether or not a timer instance is able to generate a commutation event.
1427 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1428 * @param TIMx Timer instance
1429 * @retval None
1430 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1431 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1432 {
1433 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1434 }
1435
1436 /**
1437 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1438 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1439 * whether or not a timer instance is able to generate a commutation event.
1440 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1441 * @param TIMx Timer instance
1442 * @retval None
1443 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1444 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1445 {
1446 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1447 }
1448
1449 /**
1450 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1451 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1452 * @param TIMx Timer instance
1453 * @retval State of bit (1 or 0).
1454 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1455 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1456 {
1457 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1462 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1463 * whether or not a timer instance is able to generate a commutation event.
1464 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1465 * @param TIMx Timer instance
1466 * @param CCUpdateSource This parameter can be one of the following values:
1467 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1468 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1469 * @retval None
1470 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1471 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1472 {
1473 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1474 }
1475
1476 /**
1477 * @brief Set the trigger of the capture/compare DMA request.
1478 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1479 * @param TIMx Timer instance
1480 * @param DMAReqTrigger This parameter can be one of the following values:
1481 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1482 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1483 * @retval None
1484 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1485 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1486 {
1487 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1488 }
1489
1490 /**
1491 * @brief Get actual trigger of the capture/compare DMA request.
1492 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1493 * @param TIMx Timer instance
1494 * @retval Returned value can be one of the following values:
1495 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1496 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1497 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1498 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1499 {
1500 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1501 }
1502
1503 /**
1504 * @brief Set the lock level to freeze the
1505 * configuration of several capture/compare parameters.
1506 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1507 * the lock mechanism is supported by a timer instance.
1508 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1509 * @param TIMx Timer instance
1510 * @param LockLevel This parameter can be one of the following values:
1511 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1512 * @arg @ref LL_TIM_LOCKLEVEL_1
1513 * @arg @ref LL_TIM_LOCKLEVEL_2
1514 * @arg @ref LL_TIM_LOCKLEVEL_3
1515 * @retval None
1516 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1517 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1518 {
1519 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1520 }
1521
1522 /**
1523 * @brief Enable capture/compare channels.
1524 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1525 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1526 * CCER CC2E LL_TIM_CC_EnableChannel\n
1527 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1528 * CCER CC3E LL_TIM_CC_EnableChannel\n
1529 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1530 * CCER CC4E LL_TIM_CC_EnableChannel
1531 * @param TIMx Timer instance
1532 * @param Channels This parameter can be a combination of the following values:
1533 * @arg @ref LL_TIM_CHANNEL_CH1
1534 * @arg @ref LL_TIM_CHANNEL_CH1N
1535 * @arg @ref LL_TIM_CHANNEL_CH2
1536 * @arg @ref LL_TIM_CHANNEL_CH2N
1537 * @arg @ref LL_TIM_CHANNEL_CH3
1538 * @arg @ref LL_TIM_CHANNEL_CH3N
1539 * @arg @ref LL_TIM_CHANNEL_CH4
1540 * @retval None
1541 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1542 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1543 {
1544 SET_BIT(TIMx->CCER, Channels);
1545 }
1546
1547 /**
1548 * @brief Disable capture/compare channels.
1549 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1550 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1551 * CCER CC2E LL_TIM_CC_DisableChannel\n
1552 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1553 * CCER CC3E LL_TIM_CC_DisableChannel\n
1554 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1555 * CCER CC4E LL_TIM_CC_DisableChannel
1556 * @param TIMx Timer instance
1557 * @param Channels This parameter can be a combination of the following values:
1558 * @arg @ref LL_TIM_CHANNEL_CH1
1559 * @arg @ref LL_TIM_CHANNEL_CH1N
1560 * @arg @ref LL_TIM_CHANNEL_CH2
1561 * @arg @ref LL_TIM_CHANNEL_CH2N
1562 * @arg @ref LL_TIM_CHANNEL_CH3
1563 * @arg @ref LL_TIM_CHANNEL_CH3N
1564 * @arg @ref LL_TIM_CHANNEL_CH4
1565 * @retval None
1566 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1567 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1568 {
1569 CLEAR_BIT(TIMx->CCER, Channels);
1570 }
1571
1572 /**
1573 * @brief Indicate whether channel(s) is(are) enabled.
1574 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1575 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1576 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1577 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1578 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1579 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1580 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1581 * @param TIMx Timer instance
1582 * @param Channels This parameter can be a combination of the following values:
1583 * @arg @ref LL_TIM_CHANNEL_CH1
1584 * @arg @ref LL_TIM_CHANNEL_CH1N
1585 * @arg @ref LL_TIM_CHANNEL_CH2
1586 * @arg @ref LL_TIM_CHANNEL_CH2N
1587 * @arg @ref LL_TIM_CHANNEL_CH3
1588 * @arg @ref LL_TIM_CHANNEL_CH3N
1589 * @arg @ref LL_TIM_CHANNEL_CH4
1590 * @retval State of bit (1 or 0).
1591 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1592 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1593 {
1594 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1595 }
1596
1597 /**
1598 * @}
1599 */
1600
1601 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1602 * @{
1603 */
1604 /**
1605 * @brief Configure an output channel.
1606 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1607 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1608 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1609 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1610 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1611 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1612 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1613 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1614 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1615 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1616 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1617 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1618 * @param TIMx Timer instance
1619 * @param Channel This parameter can be one of the following values:
1620 * @arg @ref LL_TIM_CHANNEL_CH1
1621 * @arg @ref LL_TIM_CHANNEL_CH2
1622 * @arg @ref LL_TIM_CHANNEL_CH3
1623 * @arg @ref LL_TIM_CHANNEL_CH4
1624 * @param Configuration This parameter must be a combination of all the following values:
1625 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1626 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1627 * @retval None
1628 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1629 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1630 {
1631 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1632 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1633 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1634 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1635 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1636 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1637 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1638 }
1639
1640 /**
1641 * @brief Define the behavior of the output reference signal OCxREF from which
1642 * OCx and OCxN (when relevant) are derived.
1643 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1644 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1645 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1646 * CCMR2 OC4M LL_TIM_OC_SetMode
1647 * @param TIMx Timer instance
1648 * @param Channel This parameter can be one of the following values:
1649 * @arg @ref LL_TIM_CHANNEL_CH1
1650 * @arg @ref LL_TIM_CHANNEL_CH2
1651 * @arg @ref LL_TIM_CHANNEL_CH3
1652 * @arg @ref LL_TIM_CHANNEL_CH4
1653 * @param Mode This parameter can be one of the following values:
1654 * @arg @ref LL_TIM_OCMODE_FROZEN
1655 * @arg @ref LL_TIM_OCMODE_ACTIVE
1656 * @arg @ref LL_TIM_OCMODE_INACTIVE
1657 * @arg @ref LL_TIM_OCMODE_TOGGLE
1658 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1659 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1660 * @arg @ref LL_TIM_OCMODE_PWM1
1661 * @arg @ref LL_TIM_OCMODE_PWM2
1662 * @retval None
1663 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1664 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1665 {
1666 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1667 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1668 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1669 }
1670
1671 /**
1672 * @brief Get the output compare mode of an output channel.
1673 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1674 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1675 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1676 * CCMR2 OC4M LL_TIM_OC_GetMode
1677 * @param TIMx Timer instance
1678 * @param Channel This parameter can be one of the following values:
1679 * @arg @ref LL_TIM_CHANNEL_CH1
1680 * @arg @ref LL_TIM_CHANNEL_CH2
1681 * @arg @ref LL_TIM_CHANNEL_CH3
1682 * @arg @ref LL_TIM_CHANNEL_CH4
1683 * @retval Returned value can be one of the following values:
1684 * @arg @ref LL_TIM_OCMODE_FROZEN
1685 * @arg @ref LL_TIM_OCMODE_ACTIVE
1686 * @arg @ref LL_TIM_OCMODE_INACTIVE
1687 * @arg @ref LL_TIM_OCMODE_TOGGLE
1688 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1689 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1690 * @arg @ref LL_TIM_OCMODE_PWM1
1691 * @arg @ref LL_TIM_OCMODE_PWM2
1692 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1693 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1694 {
1695 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1696 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1697 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1698 }
1699
1700 /**
1701 * @brief Set the polarity of an output channel.
1702 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1703 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1704 * CCER CC2P LL_TIM_OC_SetPolarity\n
1705 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1706 * CCER CC3P LL_TIM_OC_SetPolarity\n
1707 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1708 * CCER CC4P LL_TIM_OC_SetPolarity
1709 * @param TIMx Timer instance
1710 * @param Channel This parameter can be one of the following values:
1711 * @arg @ref LL_TIM_CHANNEL_CH1
1712 * @arg @ref LL_TIM_CHANNEL_CH1N
1713 * @arg @ref LL_TIM_CHANNEL_CH2
1714 * @arg @ref LL_TIM_CHANNEL_CH2N
1715 * @arg @ref LL_TIM_CHANNEL_CH3
1716 * @arg @ref LL_TIM_CHANNEL_CH3N
1717 * @arg @ref LL_TIM_CHANNEL_CH4
1718 * @param Polarity This parameter can be one of the following values:
1719 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1720 * @arg @ref LL_TIM_OCPOLARITY_LOW
1721 * @retval None
1722 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1723 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1724 {
1725 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1726 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1727 }
1728
1729 /**
1730 * @brief Get the polarity of an output channel.
1731 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1732 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1733 * CCER CC2P LL_TIM_OC_GetPolarity\n
1734 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1735 * CCER CC3P LL_TIM_OC_GetPolarity\n
1736 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1737 * CCER CC4P LL_TIM_OC_GetPolarity
1738 * @param TIMx Timer instance
1739 * @param Channel This parameter can be one of the following values:
1740 * @arg @ref LL_TIM_CHANNEL_CH1
1741 * @arg @ref LL_TIM_CHANNEL_CH1N
1742 * @arg @ref LL_TIM_CHANNEL_CH2
1743 * @arg @ref LL_TIM_CHANNEL_CH2N
1744 * @arg @ref LL_TIM_CHANNEL_CH3
1745 * @arg @ref LL_TIM_CHANNEL_CH3N
1746 * @arg @ref LL_TIM_CHANNEL_CH4
1747 * @retval Returned value can be one of the following values:
1748 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1749 * @arg @ref LL_TIM_OCPOLARITY_LOW
1750 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)1751 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
1752 {
1753 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1754 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1755 }
1756
1757 /**
1758 * @brief Set the IDLE state of an output channel
1759 * @note This function is significant only for the timer instances
1760 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1761 * can be used to check whether or not a timer instance provides
1762 * a break input.
1763 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1764 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1765 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1766 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1767 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1768 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1769 * CR2 OIS4 LL_TIM_OC_SetIdleState
1770 * @param TIMx Timer instance
1771 * @param Channel This parameter can be one of the following values:
1772 * @arg @ref LL_TIM_CHANNEL_CH1
1773 * @arg @ref LL_TIM_CHANNEL_CH1N
1774 * @arg @ref LL_TIM_CHANNEL_CH2
1775 * @arg @ref LL_TIM_CHANNEL_CH2N
1776 * @arg @ref LL_TIM_CHANNEL_CH3
1777 * @arg @ref LL_TIM_CHANNEL_CH3N
1778 * @arg @ref LL_TIM_CHANNEL_CH4
1779 * @param IdleState This parameter can be one of the following values:
1780 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1781 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1782 * @retval None
1783 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1784 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1785 {
1786 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1787 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1788 }
1789
1790 /**
1791 * @brief Get the IDLE state of an output channel
1792 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1793 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1794 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1795 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1796 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1797 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1798 * CR2 OIS4 LL_TIM_OC_GetIdleState
1799 * @param TIMx Timer instance
1800 * @param Channel This parameter can be one of the following values:
1801 * @arg @ref LL_TIM_CHANNEL_CH1
1802 * @arg @ref LL_TIM_CHANNEL_CH1N
1803 * @arg @ref LL_TIM_CHANNEL_CH2
1804 * @arg @ref LL_TIM_CHANNEL_CH2N
1805 * @arg @ref LL_TIM_CHANNEL_CH3
1806 * @arg @ref LL_TIM_CHANNEL_CH3N
1807 * @arg @ref LL_TIM_CHANNEL_CH4
1808 * @retval Returned value can be one of the following values:
1809 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1810 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1811 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)1812 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
1813 {
1814 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1815 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1816 }
1817
1818 /**
1819 * @brief Enable fast mode for the output channel.
1820 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1821 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1822 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1823 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1824 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1825 * @param TIMx Timer instance
1826 * @param Channel This parameter can be one of the following values:
1827 * @arg @ref LL_TIM_CHANNEL_CH1
1828 * @arg @ref LL_TIM_CHANNEL_CH2
1829 * @arg @ref LL_TIM_CHANNEL_CH3
1830 * @arg @ref LL_TIM_CHANNEL_CH4
1831 * @retval None
1832 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1833 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1834 {
1835 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1836 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1837 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1838
1839 }
1840
1841 /**
1842 * @brief Disable fast mode for the output channel.
1843 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1844 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1845 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1846 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1847 * @param TIMx Timer instance
1848 * @param Channel This parameter can be one of the following values:
1849 * @arg @ref LL_TIM_CHANNEL_CH1
1850 * @arg @ref LL_TIM_CHANNEL_CH2
1851 * @arg @ref LL_TIM_CHANNEL_CH3
1852 * @arg @ref LL_TIM_CHANNEL_CH4
1853 * @retval None
1854 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1855 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1856 {
1857 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1858 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1859 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1860
1861 }
1862
1863 /**
1864 * @brief Indicates whether fast mode is enabled for the output channel.
1865 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1866 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1867 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1868 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1869 * @param TIMx Timer instance
1870 * @param Channel This parameter can be one of the following values:
1871 * @arg @ref LL_TIM_CHANNEL_CH1
1872 * @arg @ref LL_TIM_CHANNEL_CH2
1873 * @arg @ref LL_TIM_CHANNEL_CH3
1874 * @arg @ref LL_TIM_CHANNEL_CH4
1875 * @retval State of bit (1 or 0).
1876 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)1877 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
1878 {
1879 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1880 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1881 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1882 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1883 }
1884
1885 /**
1886 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1887 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1888 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1889 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1890 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1891 * @param TIMx Timer instance
1892 * @param Channel This parameter can be one of the following values:
1893 * @arg @ref LL_TIM_CHANNEL_CH1
1894 * @arg @ref LL_TIM_CHANNEL_CH2
1895 * @arg @ref LL_TIM_CHANNEL_CH3
1896 * @arg @ref LL_TIM_CHANNEL_CH4
1897 * @retval None
1898 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1899 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1900 {
1901 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1902 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1903 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1904 }
1905
1906 /**
1907 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1908 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1909 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1910 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1911 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1912 * @param TIMx Timer instance
1913 * @param Channel This parameter can be one of the following values:
1914 * @arg @ref LL_TIM_CHANNEL_CH1
1915 * @arg @ref LL_TIM_CHANNEL_CH2
1916 * @arg @ref LL_TIM_CHANNEL_CH3
1917 * @arg @ref LL_TIM_CHANNEL_CH4
1918 * @retval None
1919 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1920 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1921 {
1922 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1923 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1924 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1925 }
1926
1927 /**
1928 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1929 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1930 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1931 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1932 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1933 * @param TIMx Timer instance
1934 * @param Channel This parameter can be one of the following values:
1935 * @arg @ref LL_TIM_CHANNEL_CH1
1936 * @arg @ref LL_TIM_CHANNEL_CH2
1937 * @arg @ref LL_TIM_CHANNEL_CH3
1938 * @arg @ref LL_TIM_CHANNEL_CH4
1939 * @retval State of bit (1 or 0).
1940 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)1941 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
1942 {
1943 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1944 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1945 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1946 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1947 }
1948
1949 /**
1950 * @brief Enable clearing the output channel on an external event.
1951 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1952 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1953 * or not a timer instance can clear the OCxREF signal on an external event.
1954 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1955 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1956 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1957 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1958 * @param TIMx Timer instance
1959 * @param Channel This parameter can be one of the following values:
1960 * @arg @ref LL_TIM_CHANNEL_CH1
1961 * @arg @ref LL_TIM_CHANNEL_CH2
1962 * @arg @ref LL_TIM_CHANNEL_CH3
1963 * @arg @ref LL_TIM_CHANNEL_CH4
1964 * @retval None
1965 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1966 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1967 {
1968 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1969 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1970 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1971 }
1972
1973 /**
1974 * @brief Disable clearing the output channel on an external event.
1975 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1976 * or not a timer instance can clear the OCxREF signal on an external event.
1977 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1978 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1979 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1980 * CCMR2 OC4CE LL_TIM_OC_DisableClear
1981 * @param TIMx Timer instance
1982 * @param Channel This parameter can be one of the following values:
1983 * @arg @ref LL_TIM_CHANNEL_CH1
1984 * @arg @ref LL_TIM_CHANNEL_CH2
1985 * @arg @ref LL_TIM_CHANNEL_CH3
1986 * @arg @ref LL_TIM_CHANNEL_CH4
1987 * @retval None
1988 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)1989 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1990 {
1991 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1992 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1993 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1994 }
1995
1996 /**
1997 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
1998 * @note This function enables clearing the output channel on an external event.
1999 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2000 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2001 * or not a timer instance can clear the OCxREF signal on an external event.
2002 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2003 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2004 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2005 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2006 * @param TIMx Timer instance
2007 * @param Channel This parameter can be one of the following values:
2008 * @arg @ref LL_TIM_CHANNEL_CH1
2009 * @arg @ref LL_TIM_CHANNEL_CH2
2010 * @arg @ref LL_TIM_CHANNEL_CH3
2011 * @arg @ref LL_TIM_CHANNEL_CH4
2012 * @retval State of bit (1 or 0).
2013 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2014 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2015 {
2016 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2017 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2018 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2019 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2020 }
2021
2022 /**
2023 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2024 * the Ocx and OCxN signals).
2025 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2026 * dead-time insertion feature is supported by a timer instance.
2027 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2028 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2029 * @param TIMx Timer instance
2030 * @param DeadTime between Min_Data=0 and Max_Data=255
2031 * @retval None
2032 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2033 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2034 {
2035 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2036 }
2037
2038 /**
2039 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2040 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2041 * output channel 1 is supported by a timer instance.
2042 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2043 * @param TIMx Timer instance
2044 * @param CompareValue between Min_Data=0 and Max_Data=65535
2045 * @retval None
2046 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2047 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2048 {
2049 WRITE_REG(TIMx->CCR1, CompareValue);
2050 }
2051
2052 /**
2053 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2054 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2055 * output channel 2 is supported by a timer instance.
2056 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2057 * @param TIMx Timer instance
2058 * @param CompareValue between Min_Data=0 and Max_Data=65535
2059 * @retval None
2060 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2061 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2062 {
2063 WRITE_REG(TIMx->CCR2, CompareValue);
2064 }
2065
2066 /**
2067 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2068 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2069 * output channel is supported by a timer instance.
2070 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2071 * @param TIMx Timer instance
2072 * @param CompareValue between Min_Data=0 and Max_Data=65535
2073 * @retval None
2074 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2075 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2076 {
2077 WRITE_REG(TIMx->CCR3, CompareValue);
2078 }
2079
2080 /**
2081 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2082 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2083 * output channel 4 is supported by a timer instance.
2084 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2085 * @param TIMx Timer instance
2086 * @param CompareValue between Min_Data=0 and Max_Data=65535
2087 * @retval None
2088 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2089 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2090 {
2091 WRITE_REG(TIMx->CCR4, CompareValue);
2092 }
2093
2094 /**
2095 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2096 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2097 * output channel 1 is supported by a timer instance.
2098 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2099 * @param TIMx Timer instance
2100 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2101 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2102 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2103 {
2104 return (uint32_t)(READ_REG(TIMx->CCR1));
2105 }
2106
2107 /**
2108 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2109 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2110 * output channel 2 is supported by a timer instance.
2111 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2112 * @param TIMx Timer instance
2113 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2114 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2115 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2116 {
2117 return (uint32_t)(READ_REG(TIMx->CCR2));
2118 }
2119
2120 /**
2121 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2122 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2123 * output channel 3 is supported by a timer instance.
2124 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2125 * @param TIMx Timer instance
2126 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2127 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2128 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2129 {
2130 return (uint32_t)(READ_REG(TIMx->CCR3));
2131 }
2132
2133 /**
2134 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2135 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2136 * output channel 4 is supported by a timer instance.
2137 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2138 * @param TIMx Timer instance
2139 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2140 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2141 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2142 {
2143 return (uint32_t)(READ_REG(TIMx->CCR4));
2144 }
2145
2146 /**
2147 * @}
2148 */
2149
2150 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2151 * @{
2152 */
2153 /**
2154 * @brief Configure input channel.
2155 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2156 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2157 * CCMR1 IC1F LL_TIM_IC_Config\n
2158 * CCMR1 CC2S LL_TIM_IC_Config\n
2159 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2160 * CCMR1 IC2F LL_TIM_IC_Config\n
2161 * CCMR2 CC3S LL_TIM_IC_Config\n
2162 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2163 * CCMR2 IC3F LL_TIM_IC_Config\n
2164 * CCMR2 CC4S LL_TIM_IC_Config\n
2165 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2166 * CCMR2 IC4F LL_TIM_IC_Config\n
2167 * CCER CC1P LL_TIM_IC_Config\n
2168 * CCER CC1NP LL_TIM_IC_Config\n
2169 * CCER CC2P LL_TIM_IC_Config\n
2170 * CCER CC2NP LL_TIM_IC_Config\n
2171 * CCER CC3P LL_TIM_IC_Config\n
2172 * CCER CC3NP LL_TIM_IC_Config\n
2173 * CCER CC4P LL_TIM_IC_Config\n
2174 * @param TIMx Timer instance
2175 * @param Channel This parameter can be one of the following values:
2176 * @arg @ref LL_TIM_CHANNEL_CH1
2177 * @arg @ref LL_TIM_CHANNEL_CH2
2178 * @arg @ref LL_TIM_CHANNEL_CH3
2179 * @arg @ref LL_TIM_CHANNEL_CH4
2180 * @param Configuration This parameter must be a combination of all the following values:
2181 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2182 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2183 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2184 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
2185 * @retval None
2186 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2187 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2188 {
2189 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2190 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2191 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2192 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2193 << SHIFT_TAB_ICxx[iChannel]);
2194 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2195 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2196 }
2197
2198 /**
2199 * @brief Set the active input.
2200 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2201 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2202 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2203 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2204 * @param TIMx Timer instance
2205 * @param Channel This parameter can be one of the following values:
2206 * @arg @ref LL_TIM_CHANNEL_CH1
2207 * @arg @ref LL_TIM_CHANNEL_CH2
2208 * @arg @ref LL_TIM_CHANNEL_CH3
2209 * @arg @ref LL_TIM_CHANNEL_CH4
2210 * @param ICActiveInput This parameter can be one of the following values:
2211 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2212 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2213 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2214 * @retval None
2215 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2216 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2217 {
2218 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2219 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2220 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2221 }
2222
2223 /**
2224 * @brief Get the current active input.
2225 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2226 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2227 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2228 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2229 * @param TIMx Timer instance
2230 * @param Channel This parameter can be one of the following values:
2231 * @arg @ref LL_TIM_CHANNEL_CH1
2232 * @arg @ref LL_TIM_CHANNEL_CH2
2233 * @arg @ref LL_TIM_CHANNEL_CH3
2234 * @arg @ref LL_TIM_CHANNEL_CH4
2235 * @retval Returned value can be one of the following values:
2236 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2237 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2238 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2239 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2240 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2241 {
2242 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2243 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2244 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2245 }
2246
2247 /**
2248 * @brief Set the prescaler of input channel.
2249 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2250 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2251 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2252 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2253 * @param TIMx Timer instance
2254 * @param Channel This parameter can be one of the following values:
2255 * @arg @ref LL_TIM_CHANNEL_CH1
2256 * @arg @ref LL_TIM_CHANNEL_CH2
2257 * @arg @ref LL_TIM_CHANNEL_CH3
2258 * @arg @ref LL_TIM_CHANNEL_CH4
2259 * @param ICPrescaler This parameter can be one of the following values:
2260 * @arg @ref LL_TIM_ICPSC_DIV1
2261 * @arg @ref LL_TIM_ICPSC_DIV2
2262 * @arg @ref LL_TIM_ICPSC_DIV4
2263 * @arg @ref LL_TIM_ICPSC_DIV8
2264 * @retval None
2265 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2266 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2267 {
2268 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2269 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2270 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2271 }
2272
2273 /**
2274 * @brief Get the current prescaler value acting on an input channel.
2275 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2276 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2277 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2278 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2279 * @param TIMx Timer instance
2280 * @param Channel This parameter can be one of the following values:
2281 * @arg @ref LL_TIM_CHANNEL_CH1
2282 * @arg @ref LL_TIM_CHANNEL_CH2
2283 * @arg @ref LL_TIM_CHANNEL_CH3
2284 * @arg @ref LL_TIM_CHANNEL_CH4
2285 * @retval Returned value can be one of the following values:
2286 * @arg @ref LL_TIM_ICPSC_DIV1
2287 * @arg @ref LL_TIM_ICPSC_DIV2
2288 * @arg @ref LL_TIM_ICPSC_DIV4
2289 * @arg @ref LL_TIM_ICPSC_DIV8
2290 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2291 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2292 {
2293 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2294 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2295 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2296 }
2297
2298 /**
2299 * @brief Set the input filter duration.
2300 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2301 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2302 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2303 * CCMR2 IC4F LL_TIM_IC_SetFilter
2304 * @param TIMx Timer instance
2305 * @param Channel This parameter can be one of the following values:
2306 * @arg @ref LL_TIM_CHANNEL_CH1
2307 * @arg @ref LL_TIM_CHANNEL_CH2
2308 * @arg @ref LL_TIM_CHANNEL_CH3
2309 * @arg @ref LL_TIM_CHANNEL_CH4
2310 * @param ICFilter This parameter can be one of the following values:
2311 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2312 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2313 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2314 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2315 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2316 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2317 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2318 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2319 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2320 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2321 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2322 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2323 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2324 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2325 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2326 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2327 * @retval None
2328 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2329 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2330 {
2331 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2332 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2333 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2334 }
2335
2336 /**
2337 * @brief Get the input filter duration.
2338 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2339 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2340 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2341 * CCMR2 IC4F LL_TIM_IC_GetFilter
2342 * @param TIMx Timer instance
2343 * @param Channel This parameter can be one of the following values:
2344 * @arg @ref LL_TIM_CHANNEL_CH1
2345 * @arg @ref LL_TIM_CHANNEL_CH2
2346 * @arg @ref LL_TIM_CHANNEL_CH3
2347 * @arg @ref LL_TIM_CHANNEL_CH4
2348 * @retval Returned value can be one of the following values:
2349 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2350 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2351 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2352 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2353 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2354 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2355 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2356 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2357 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2358 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2359 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2360 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2361 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2362 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2363 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2364 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2365 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2366 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2367 {
2368 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2369 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2370 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2371 }
2372
2373 /**
2374 * @brief Set the input channel polarity.
2375 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2376 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2377 * CCER CC2P LL_TIM_IC_SetPolarity\n
2378 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2379 * CCER CC3P LL_TIM_IC_SetPolarity\n
2380 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2381 * CCER CC4P LL_TIM_IC_SetPolarity\n
2382 * @param TIMx Timer instance
2383 * @param Channel This parameter can be one of the following values:
2384 * @arg @ref LL_TIM_CHANNEL_CH1
2385 * @arg @ref LL_TIM_CHANNEL_CH2
2386 * @arg @ref LL_TIM_CHANNEL_CH3
2387 * @arg @ref LL_TIM_CHANNEL_CH4
2388 * @param ICPolarity This parameter can be one of the following values:
2389 * @arg @ref LL_TIM_IC_POLARITY_RISING
2390 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2391 * @retval None
2392 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2393 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2394 {
2395 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2396 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2397 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2398 }
2399
2400 /**
2401 * @brief Get the current input channel polarity.
2402 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2403 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2404 * CCER CC2P LL_TIM_IC_GetPolarity\n
2405 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2406 * CCER CC3P LL_TIM_IC_GetPolarity\n
2407 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2408 * CCER CC4P LL_TIM_IC_GetPolarity\n
2409 * @param TIMx Timer instance
2410 * @param Channel This parameter can be one of the following values:
2411 * @arg @ref LL_TIM_CHANNEL_CH1
2412 * @arg @ref LL_TIM_CHANNEL_CH2
2413 * @arg @ref LL_TIM_CHANNEL_CH3
2414 * @arg @ref LL_TIM_CHANNEL_CH4
2415 * @retval Returned value can be one of the following values:
2416 * @arg @ref LL_TIM_IC_POLARITY_RISING
2417 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2418 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2419 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2420 {
2421 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2422 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2423 SHIFT_TAB_CCxP[iChannel]);
2424 }
2425
2426 /**
2427 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2428 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2429 * a timer instance provides an XOR input.
2430 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2431 * @param TIMx Timer instance
2432 * @retval None
2433 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2434 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2435 {
2436 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2437 }
2438
2439 /**
2440 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2441 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2442 * a timer instance provides an XOR input.
2443 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2444 * @param TIMx Timer instance
2445 * @retval None
2446 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2447 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2448 {
2449 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2450 }
2451
2452 /**
2453 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2454 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2455 * a timer instance provides an XOR input.
2456 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2457 * @param TIMx Timer instance
2458 * @retval State of bit (1 or 0).
2459 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2460 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2461 {
2462 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2463 }
2464
2465 /**
2466 * @brief Get captured value for input channel 1.
2467 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2468 * input channel 1 is supported by a timer instance.
2469 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2470 * @param TIMx Timer instance
2471 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2472 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2473 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2474 {
2475 return (uint32_t)(READ_REG(TIMx->CCR1));
2476 }
2477
2478 /**
2479 * @brief Get captured value for input channel 2.
2480 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2481 * input channel 2 is supported by a timer instance.
2482 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2483 * @param TIMx Timer instance
2484 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2485 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2486 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2487 {
2488 return (uint32_t)(READ_REG(TIMx->CCR2));
2489 }
2490
2491 /**
2492 * @brief Get captured value for input channel 3.
2493 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2494 * input channel 3 is supported by a timer instance.
2495 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2496 * @param TIMx Timer instance
2497 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2498 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2499 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2500 {
2501 return (uint32_t)(READ_REG(TIMx->CCR3));
2502 }
2503
2504 /**
2505 * @brief Get captured value for input channel 4.
2506 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2507 * input channel 4 is supported by a timer instance.
2508 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2509 * @param TIMx Timer instance
2510 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2511 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2512 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2513 {
2514 return (uint32_t)(READ_REG(TIMx->CCR4));
2515 }
2516
2517 /**
2518 * @}
2519 */
2520
2521 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2522 * @{
2523 */
2524 /**
2525 * @brief Enable external clock mode 2.
2526 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2527 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2528 * whether or not a timer instance supports external clock mode2.
2529 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2530 * @param TIMx Timer instance
2531 * @retval None
2532 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2533 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2534 {
2535 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2536 }
2537
2538 /**
2539 * @brief Disable external clock mode 2.
2540 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2541 * whether or not a timer instance supports external clock mode2.
2542 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2543 * @param TIMx Timer instance
2544 * @retval None
2545 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2546 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2547 {
2548 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2549 }
2550
2551 /**
2552 * @brief Indicate whether external clock mode 2 is enabled.
2553 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2554 * whether or not a timer instance supports external clock mode2.
2555 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2556 * @param TIMx Timer instance
2557 * @retval State of bit (1 or 0).
2558 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2559 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2560 {
2561 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2562 }
2563
2564 /**
2565 * @brief Set the clock source of the counter clock.
2566 * @note when selected clock source is external clock mode 1, the timer input
2567 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2568 * function. This timer input must be configured by calling
2569 * the @ref LL_TIM_IC_Config() function.
2570 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2571 * whether or not a timer instance supports external clock mode1.
2572 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2573 * whether or not a timer instance supports external clock mode2.
2574 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2575 * SMCR ECE LL_TIM_SetClockSource
2576 * @param TIMx Timer instance
2577 * @param ClockSource This parameter can be one of the following values:
2578 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2579 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2580 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2581 * @retval None
2582 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2583 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2584 {
2585 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2586 }
2587
2588 /**
2589 * @brief Set the encoder interface mode.
2590 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2591 * whether or not a timer instance supports the encoder mode.
2592 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2593 * @param TIMx Timer instance
2594 * @param EncoderMode This parameter can be one of the following values:
2595 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2596 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2597 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2598 * @retval None
2599 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2600 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2601 {
2602 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2603 }
2604
2605 /**
2606 * @}
2607 */
2608
2609 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2610 * @{
2611 */
2612 /**
2613 * @brief Set the trigger output (TRGO) used for timer synchronization .
2614 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2615 * whether or not a timer instance can operate as a master timer.
2616 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2617 * @param TIMx Timer instance
2618 * @param TimerSynchronization This parameter can be one of the following values:
2619 * @arg @ref LL_TIM_TRGO_RESET
2620 * @arg @ref LL_TIM_TRGO_ENABLE
2621 * @arg @ref LL_TIM_TRGO_UPDATE
2622 * @arg @ref LL_TIM_TRGO_CC1IF
2623 * @arg @ref LL_TIM_TRGO_OC1REF
2624 * @arg @ref LL_TIM_TRGO_OC2REF
2625 * @arg @ref LL_TIM_TRGO_OC3REF
2626 * @arg @ref LL_TIM_TRGO_OC4REF
2627 * @retval None
2628 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2629 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2630 {
2631 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2632 }
2633
2634 /**
2635 * @brief Set the synchronization mode of a slave timer.
2636 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2637 * a timer instance can operate as a slave timer.
2638 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2639 * @param TIMx Timer instance
2640 * @param SlaveMode This parameter can be one of the following values:
2641 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2642 * @arg @ref LL_TIM_SLAVEMODE_RESET
2643 * @arg @ref LL_TIM_SLAVEMODE_GATED
2644 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2645 * @retval None
2646 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2647 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2648 {
2649 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2650 }
2651
2652 /**
2653 * @brief Set the selects the trigger input to be used to synchronize the counter.
2654 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2655 * a timer instance can operate as a slave timer.
2656 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2657 * @param TIMx Timer instance
2658 * @param TriggerInput This parameter can be one of the following values:
2659 * @arg @ref LL_TIM_TS_ITR0
2660 * @arg @ref LL_TIM_TS_ITR1
2661 * @arg @ref LL_TIM_TS_ITR2
2662 * @arg @ref LL_TIM_TS_ITR3
2663 * @arg @ref LL_TIM_TS_TI1F_ED
2664 * @arg @ref LL_TIM_TS_TI1FP1
2665 * @arg @ref LL_TIM_TS_TI2FP2
2666 * @arg @ref LL_TIM_TS_ETRF
2667 * @retval None
2668 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2669 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2670 {
2671 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2672 }
2673
2674 /**
2675 * @brief Enable the Master/Slave mode.
2676 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2677 * a timer instance can operate as a slave timer.
2678 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2679 * @param TIMx Timer instance
2680 * @retval None
2681 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2682 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2683 {
2684 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2685 }
2686
2687 /**
2688 * @brief Disable the Master/Slave mode.
2689 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2690 * a timer instance can operate as a slave timer.
2691 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2692 * @param TIMx Timer instance
2693 * @retval None
2694 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2695 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2696 {
2697 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2698 }
2699
2700 /**
2701 * @brief Indicates whether the Master/Slave mode is enabled.
2702 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2703 * a timer instance can operate as a slave timer.
2704 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2705 * @param TIMx Timer instance
2706 * @retval State of bit (1 or 0).
2707 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)2708 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
2709 {
2710 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2711 }
2712
2713 /**
2714 * @brief Configure the external trigger (ETR) input.
2715 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2716 * a timer instance provides an external trigger input.
2717 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2718 * SMCR ETPS LL_TIM_ConfigETR\n
2719 * SMCR ETF LL_TIM_ConfigETR
2720 * @param TIMx Timer instance
2721 * @param ETRPolarity This parameter can be one of the following values:
2722 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2723 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2724 * @param ETRPrescaler This parameter can be one of the following values:
2725 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2726 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2727 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2728 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2729 * @param ETRFilter This parameter can be one of the following values:
2730 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2731 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2732 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2733 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2734 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2735 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2736 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2737 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2738 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2739 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2740 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2741 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2742 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2743 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2744 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2745 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2746 * @retval None
2747 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2748 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2749 uint32_t ETRFilter)
2750 {
2751 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2752 }
2753
2754 /**
2755 * @}
2756 */
2757
2758 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2759 * @{
2760 */
2761 /**
2762 * @brief Enable the break function.
2763 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2764 * a timer instance provides a break input.
2765 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2766 * @param TIMx Timer instance
2767 * @retval None
2768 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2769 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2770 {
2771 __IO uint32_t tmpreg;
2772 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2773 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2774 tmpreg = READ_REG(TIMx->BDTR);
2775 (void)(tmpreg);
2776 }
2777
2778 /**
2779 * @brief Disable the break function.
2780 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2781 * @param TIMx Timer instance
2782 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2783 * a timer instance provides a break input.
2784 * @retval None
2785 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2786 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2787 {
2788 __IO uint32_t tmpreg;
2789 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2790 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2791 tmpreg = READ_REG(TIMx->BDTR);
2792 (void)(tmpreg);
2793 }
2794
2795 /**
2796 * @brief Configure the break input.
2797 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2798 * a timer instance provides a break input.
2799 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2800 * @param TIMx Timer instance
2801 * @param BreakPolarity This parameter can be one of the following values:
2802 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2803 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2804 * @retval None
2805 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2806 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2807 {
2808 __IO uint32_t tmpreg;
2809 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2810 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2811 tmpreg = READ_REG(TIMx->BDTR);
2812 (void)(tmpreg);
2813 }
2814
2815 /**
2816 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2817 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2818 * a timer instance provides a break input.
2819 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2820 * BDTR OSSR LL_TIM_SetOffStates
2821 * @param TIMx Timer instance
2822 * @param OffStateIdle This parameter can be one of the following values:
2823 * @arg @ref LL_TIM_OSSI_DISABLE
2824 * @arg @ref LL_TIM_OSSI_ENABLE
2825 * @param OffStateRun This parameter can be one of the following values:
2826 * @arg @ref LL_TIM_OSSR_DISABLE
2827 * @arg @ref LL_TIM_OSSR_ENABLE
2828 * @retval None
2829 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2830 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2831 {
2832 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2833 }
2834
2835 /**
2836 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2837 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2838 * a timer instance provides a break input.
2839 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2840 * @param TIMx Timer instance
2841 * @retval None
2842 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2843 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2844 {
2845 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2846 }
2847
2848 /**
2849 * @brief Disable automatic output (MOE can be set only by software).
2850 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2851 * a timer instance provides a break input.
2852 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2853 * @param TIMx Timer instance
2854 * @retval None
2855 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2856 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2857 {
2858 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2859 }
2860
2861 /**
2862 * @brief Indicate whether automatic output is enabled.
2863 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2864 * a timer instance provides a break input.
2865 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2866 * @param TIMx Timer instance
2867 * @retval State of bit (1 or 0).
2868 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)2869 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
2870 {
2871 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2872 }
2873
2874 /**
2875 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2876 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2877 * software and is reset in case of break or break2 event
2878 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2879 * a timer instance provides a break input.
2880 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2881 * @param TIMx Timer instance
2882 * @retval None
2883 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2884 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2885 {
2886 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2887 }
2888
2889 /**
2890 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2891 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2892 * software and is reset in case of break or break2 event.
2893 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2894 * a timer instance provides a break input.
2895 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2896 * @param TIMx Timer instance
2897 * @retval None
2898 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)2899 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2900 {
2901 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2902 }
2903
2904 /**
2905 * @brief Indicates whether outputs are enabled.
2906 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2907 * a timer instance provides a break input.
2908 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2909 * @param TIMx Timer instance
2910 * @retval State of bit (1 or 0).
2911 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)2912 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
2913 {
2914 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
2915 }
2916
2917 /**
2918 * @}
2919 */
2920
2921 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2922 * @{
2923 */
2924 /**
2925 * @brief Configures the timer DMA burst feature.
2926 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2927 * not a timer instance supports the DMA burst mode.
2928 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2929 * DCR DBA LL_TIM_ConfigDMABurst
2930 * @param TIMx Timer instance
2931 * @param DMABurstBaseAddress This parameter can be one of the following values:
2932 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2933 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2934 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2935 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2936 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2937 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2938 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2939 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2940 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2941 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2942 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2943 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2944 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
2945 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2946 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2947 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2948 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2949 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
2950 * @param DMABurstLength This parameter can be one of the following values:
2951 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
2952 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
2953 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
2954 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
2955 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
2956 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
2957 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
2958 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
2959 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
2960 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
2961 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
2962 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
2963 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
2964 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
2965 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
2966 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
2967 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
2968 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
2969 * @retval None
2970 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)2971 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
2972 {
2973 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
2974 }
2975
2976 /**
2977 * @}
2978 */
2979
2980
2981 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
2982 * @{
2983 */
2984 /**
2985 * @brief Clear the update interrupt flag (UIF).
2986 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
2987 * @param TIMx Timer instance
2988 * @retval None
2989 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)2990 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
2991 {
2992 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
2993 }
2994
2995 /**
2996 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
2997 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
2998 * @param TIMx Timer instance
2999 * @retval State of bit (1 or 0).
3000 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3001 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3002 {
3003 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3004 }
3005
3006 /**
3007 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3008 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3009 * @param TIMx Timer instance
3010 * @retval None
3011 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3012 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3013 {
3014 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3015 }
3016
3017 /**
3018 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3019 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3020 * @param TIMx Timer instance
3021 * @retval State of bit (1 or 0).
3022 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3023 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3024 {
3025 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3026 }
3027
3028 /**
3029 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3030 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3031 * @param TIMx Timer instance
3032 * @retval None
3033 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3034 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3035 {
3036 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3037 }
3038
3039 /**
3040 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3041 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3042 * @param TIMx Timer instance
3043 * @retval State of bit (1 or 0).
3044 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3045 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3046 {
3047 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3048 }
3049
3050 /**
3051 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3052 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3053 * @param TIMx Timer instance
3054 * @retval None
3055 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3056 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3057 {
3058 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3059 }
3060
3061 /**
3062 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3063 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3064 * @param TIMx Timer instance
3065 * @retval State of bit (1 or 0).
3066 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3067 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3068 {
3069 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3070 }
3071
3072 /**
3073 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3074 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3075 * @param TIMx Timer instance
3076 * @retval None
3077 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3078 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3079 {
3080 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3081 }
3082
3083 /**
3084 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3085 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3086 * @param TIMx Timer instance
3087 * @retval State of bit (1 or 0).
3088 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3089 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3090 {
3091 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3092 }
3093
3094 /**
3095 * @brief Clear the commutation interrupt flag (COMIF).
3096 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3097 * @param TIMx Timer instance
3098 * @retval None
3099 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3100 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3101 {
3102 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3103 }
3104
3105 /**
3106 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3107 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3108 * @param TIMx Timer instance
3109 * @retval State of bit (1 or 0).
3110 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3111 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3112 {
3113 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3114 }
3115
3116 /**
3117 * @brief Clear the trigger interrupt flag (TIF).
3118 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3119 * @param TIMx Timer instance
3120 * @retval None
3121 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3122 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3123 {
3124 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3125 }
3126
3127 /**
3128 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3129 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3130 * @param TIMx Timer instance
3131 * @retval State of bit (1 or 0).
3132 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3133 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3134 {
3135 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3136 }
3137
3138 /**
3139 * @brief Clear the break interrupt flag (BIF).
3140 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3141 * @param TIMx Timer instance
3142 * @retval None
3143 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3144 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3145 {
3146 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3147 }
3148
3149 /**
3150 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3151 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3152 * @param TIMx Timer instance
3153 * @retval State of bit (1 or 0).
3154 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3155 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3156 {
3157 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3158 }
3159
3160 /**
3161 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3162 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3163 * @param TIMx Timer instance
3164 * @retval None
3165 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3166 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3167 {
3168 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3169 }
3170
3171 /**
3172 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3173 * (Capture/Compare 1 interrupt is pending).
3174 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3175 * @param TIMx Timer instance
3176 * @retval State of bit (1 or 0).
3177 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3178 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3179 {
3180 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3181 }
3182
3183 /**
3184 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3185 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3186 * @param TIMx Timer instance
3187 * @retval None
3188 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3189 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3190 {
3191 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3192 }
3193
3194 /**
3195 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3196 * (Capture/Compare 2 over-capture interrupt is pending).
3197 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3198 * @param TIMx Timer instance
3199 * @retval State of bit (1 or 0).
3200 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3201 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3202 {
3203 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3204 }
3205
3206 /**
3207 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3208 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3209 * @param TIMx Timer instance
3210 * @retval None
3211 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3212 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3213 {
3214 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3215 }
3216
3217 /**
3218 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3219 * (Capture/Compare 3 over-capture interrupt is pending).
3220 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3221 * @param TIMx Timer instance
3222 * @retval State of bit (1 or 0).
3223 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)3224 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
3225 {
3226 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3227 }
3228
3229 /**
3230 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3231 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3232 * @param TIMx Timer instance
3233 * @retval None
3234 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3235 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3236 {
3237 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3238 }
3239
3240 /**
3241 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3242 * (Capture/Compare 4 over-capture interrupt is pending).
3243 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3244 * @param TIMx Timer instance
3245 * @retval State of bit (1 or 0).
3246 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)3247 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
3248 {
3249 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3250 }
3251
3252 /**
3253 * @}
3254 */
3255
3256 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3257 * @{
3258 */
3259 /**
3260 * @brief Enable update interrupt (UIE).
3261 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3262 * @param TIMx Timer instance
3263 * @retval None
3264 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3265 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3266 {
3267 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3268 }
3269
3270 /**
3271 * @brief Disable update interrupt (UIE).
3272 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3273 * @param TIMx Timer instance
3274 * @retval None
3275 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3276 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3277 {
3278 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3279 }
3280
3281 /**
3282 * @brief Indicates whether the update interrupt (UIE) is enabled.
3283 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3284 * @param TIMx Timer instance
3285 * @retval State of bit (1 or 0).
3286 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)3287 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
3288 {
3289 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3290 }
3291
3292 /**
3293 * @brief Enable capture/compare 1 interrupt (CC1IE).
3294 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3295 * @param TIMx Timer instance
3296 * @retval None
3297 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3298 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3299 {
3300 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3301 }
3302
3303 /**
3304 * @brief Disable capture/compare 1 interrupt (CC1IE).
3305 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3306 * @param TIMx Timer instance
3307 * @retval None
3308 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3309 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3310 {
3311 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3312 }
3313
3314 /**
3315 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3316 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3317 * @param TIMx Timer instance
3318 * @retval State of bit (1 or 0).
3319 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)3320 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
3321 {
3322 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3323 }
3324
3325 /**
3326 * @brief Enable capture/compare 2 interrupt (CC2IE).
3327 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3328 * @param TIMx Timer instance
3329 * @retval None
3330 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3331 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3332 {
3333 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3334 }
3335
3336 /**
3337 * @brief Disable capture/compare 2 interrupt (CC2IE).
3338 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3339 * @param TIMx Timer instance
3340 * @retval None
3341 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3342 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3343 {
3344 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3345 }
3346
3347 /**
3348 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3349 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3350 * @param TIMx Timer instance
3351 * @retval State of bit (1 or 0).
3352 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)3353 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
3354 {
3355 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3356 }
3357
3358 /**
3359 * @brief Enable capture/compare 3 interrupt (CC3IE).
3360 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3361 * @param TIMx Timer instance
3362 * @retval None
3363 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3364 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3365 {
3366 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3367 }
3368
3369 /**
3370 * @brief Disable capture/compare 3 interrupt (CC3IE).
3371 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3372 * @param TIMx Timer instance
3373 * @retval None
3374 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3375 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3376 {
3377 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3378 }
3379
3380 /**
3381 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3382 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3383 * @param TIMx Timer instance
3384 * @retval State of bit (1 or 0).
3385 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)3386 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
3387 {
3388 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3389 }
3390
3391 /**
3392 * @brief Enable capture/compare 4 interrupt (CC4IE).
3393 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3394 * @param TIMx Timer instance
3395 * @retval None
3396 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3397 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3398 {
3399 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3400 }
3401
3402 /**
3403 * @brief Disable capture/compare 4 interrupt (CC4IE).
3404 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3405 * @param TIMx Timer instance
3406 * @retval None
3407 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3408 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3409 {
3410 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3411 }
3412
3413 /**
3414 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3415 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3416 * @param TIMx Timer instance
3417 * @retval State of bit (1 or 0).
3418 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)3419 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
3420 {
3421 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3422 }
3423
3424 /**
3425 * @brief Enable commutation interrupt (COMIE).
3426 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3427 * @param TIMx Timer instance
3428 * @retval None
3429 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3430 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3431 {
3432 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3433 }
3434
3435 /**
3436 * @brief Disable commutation interrupt (COMIE).
3437 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3438 * @param TIMx Timer instance
3439 * @retval None
3440 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3441 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3442 {
3443 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3444 }
3445
3446 /**
3447 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3448 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3449 * @param TIMx Timer instance
3450 * @retval State of bit (1 or 0).
3451 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)3452 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
3453 {
3454 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3455 }
3456
3457 /**
3458 * @brief Enable trigger interrupt (TIE).
3459 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3460 * @param TIMx Timer instance
3461 * @retval None
3462 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3463 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3464 {
3465 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3466 }
3467
3468 /**
3469 * @brief Disable trigger interrupt (TIE).
3470 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3471 * @param TIMx Timer instance
3472 * @retval None
3473 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3474 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3475 {
3476 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3477 }
3478
3479 /**
3480 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3481 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3482 * @param TIMx Timer instance
3483 * @retval State of bit (1 or 0).
3484 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)3485 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
3486 {
3487 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3488 }
3489
3490 /**
3491 * @brief Enable break interrupt (BIE).
3492 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3493 * @param TIMx Timer instance
3494 * @retval None
3495 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3496 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3497 {
3498 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3499 }
3500
3501 /**
3502 * @brief Disable break interrupt (BIE).
3503 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3504 * @param TIMx Timer instance
3505 * @retval None
3506 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3507 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3508 {
3509 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3510 }
3511
3512 /**
3513 * @brief Indicates whether the break interrupt (BIE) is enabled.
3514 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3515 * @param TIMx Timer instance
3516 * @retval State of bit (1 or 0).
3517 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)3518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
3519 {
3520 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3521 }
3522
3523 /**
3524 * @}
3525 */
3526
3527 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3528 * @{
3529 */
3530 /**
3531 * @brief Enable update DMA request (UDE).
3532 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3533 * @param TIMx Timer instance
3534 * @retval None
3535 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3536 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3537 {
3538 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3539 }
3540
3541 /**
3542 * @brief Disable update DMA request (UDE).
3543 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3544 * @param TIMx Timer instance
3545 * @retval None
3546 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3547 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3548 {
3549 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3550 }
3551
3552 /**
3553 * @brief Indicates whether the update DMA request (UDE) is enabled.
3554 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3555 * @param TIMx Timer instance
3556 * @retval State of bit (1 or 0).
3557 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)3558 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
3559 {
3560 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3561 }
3562
3563 /**
3564 * @brief Enable capture/compare 1 DMA request (CC1DE).
3565 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3566 * @param TIMx Timer instance
3567 * @retval None
3568 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3569 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3570 {
3571 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3572 }
3573
3574 /**
3575 * @brief Disable capture/compare 1 DMA request (CC1DE).
3576 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3577 * @param TIMx Timer instance
3578 * @retval None
3579 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3580 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3581 {
3582 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3583 }
3584
3585 /**
3586 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3587 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3588 * @param TIMx Timer instance
3589 * @retval State of bit (1 or 0).
3590 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)3591 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
3592 {
3593 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3594 }
3595
3596 /**
3597 * @brief Enable capture/compare 2 DMA request (CC2DE).
3598 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3599 * @param TIMx Timer instance
3600 * @retval None
3601 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3602 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3603 {
3604 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3605 }
3606
3607 /**
3608 * @brief Disable capture/compare 2 DMA request (CC2DE).
3609 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3610 * @param TIMx Timer instance
3611 * @retval None
3612 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3613 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3614 {
3615 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3616 }
3617
3618 /**
3619 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3620 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3621 * @param TIMx Timer instance
3622 * @retval State of bit (1 or 0).
3623 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)3624 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
3625 {
3626 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3627 }
3628
3629 /**
3630 * @brief Enable capture/compare 3 DMA request (CC3DE).
3631 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3632 * @param TIMx Timer instance
3633 * @retval None
3634 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3635 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3636 {
3637 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3638 }
3639
3640 /**
3641 * @brief Disable capture/compare 3 DMA request (CC3DE).
3642 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3643 * @param TIMx Timer instance
3644 * @retval None
3645 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3646 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3647 {
3648 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3649 }
3650
3651 /**
3652 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3653 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3654 * @param TIMx Timer instance
3655 * @retval State of bit (1 or 0).
3656 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)3657 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
3658 {
3659 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3660 }
3661
3662 /**
3663 * @brief Enable capture/compare 4 DMA request (CC4DE).
3664 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3665 * @param TIMx Timer instance
3666 * @retval None
3667 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3668 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3669 {
3670 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3671 }
3672
3673 /**
3674 * @brief Disable capture/compare 4 DMA request (CC4DE).
3675 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3676 * @param TIMx Timer instance
3677 * @retval None
3678 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3679 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3680 {
3681 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3682 }
3683
3684 /**
3685 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3686 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3687 * @param TIMx Timer instance
3688 * @retval State of bit (1 or 0).
3689 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)3690 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
3691 {
3692 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3693 }
3694
3695 /**
3696 * @brief Enable commutation DMA request (COMDE).
3697 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3698 * @param TIMx Timer instance
3699 * @retval None
3700 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3701 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3702 {
3703 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3704 }
3705
3706 /**
3707 * @brief Disable commutation DMA request (COMDE).
3708 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3709 * @param TIMx Timer instance
3710 * @retval None
3711 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3712 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3713 {
3714 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3715 }
3716
3717 /**
3718 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3719 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3720 * @param TIMx Timer instance
3721 * @retval State of bit (1 or 0).
3722 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)3723 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
3724 {
3725 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3726 }
3727
3728 /**
3729 * @brief Enable trigger interrupt (TDE).
3730 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3731 * @param TIMx Timer instance
3732 * @retval None
3733 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3734 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3735 {
3736 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3737 }
3738
3739 /**
3740 * @brief Disable trigger interrupt (TDE).
3741 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3742 * @param TIMx Timer instance
3743 * @retval None
3744 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3745 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3746 {
3747 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3748 }
3749
3750 /**
3751 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3752 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3753 * @param TIMx Timer instance
3754 * @retval State of bit (1 or 0).
3755 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)3756 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
3757 {
3758 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3759 }
3760
3761 /**
3762 * @}
3763 */
3764
3765 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3766 * @{
3767 */
3768 /**
3769 * @brief Generate an update event.
3770 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3771 * @param TIMx Timer instance
3772 * @retval None
3773 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3774 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3775 {
3776 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3777 }
3778
3779 /**
3780 * @brief Generate Capture/Compare 1 event.
3781 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3782 * @param TIMx Timer instance
3783 * @retval None
3784 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3785 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3786 {
3787 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3788 }
3789
3790 /**
3791 * @brief Generate Capture/Compare 2 event.
3792 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3793 * @param TIMx Timer instance
3794 * @retval None
3795 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3796 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3797 {
3798 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3799 }
3800
3801 /**
3802 * @brief Generate Capture/Compare 3 event.
3803 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3804 * @param TIMx Timer instance
3805 * @retval None
3806 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3807 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3808 {
3809 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3810 }
3811
3812 /**
3813 * @brief Generate Capture/Compare 4 event.
3814 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3815 * @param TIMx Timer instance
3816 * @retval None
3817 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3818 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3819 {
3820 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3821 }
3822
3823 /**
3824 * @brief Generate commutation event.
3825 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3826 * @param TIMx Timer instance
3827 * @retval None
3828 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)3829 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3830 {
3831 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3832 }
3833
3834 /**
3835 * @brief Generate trigger event.
3836 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3837 * @param TIMx Timer instance
3838 * @retval None
3839 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3840 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3841 {
3842 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3843 }
3844
3845 /**
3846 * @brief Generate break event.
3847 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3848 * @param TIMx Timer instance
3849 * @retval None
3850 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)3851 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3852 {
3853 SET_BIT(TIMx->EGR, TIM_EGR_BG);
3854 }
3855
3856 /**
3857 * @}
3858 */
3859
3860 #if defined(USE_FULL_LL_DRIVER)
3861 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3862 * @{
3863 */
3864
3865 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
3866 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3867 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
3868 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3869 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3870 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3871 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3872 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3873 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3874 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3875 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3876 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3877 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3878 /**
3879 * @}
3880 */
3881 #endif /* USE_FULL_LL_DRIVER */
3882
3883 /**
3884 * @}
3885 */
3886
3887 /**
3888 * @}
3889 */
3890
3891 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
3892
3893 /**
3894 * @}
3895 */
3896
3897 #ifdef __cplusplus
3898 }
3899 #endif
3900
3901 #endif /* __STM32F1xx_LL_TIM_H */
3902
