1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F3xx_LL_TIM_H
21 #define __STM32F3xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f3xx.h"
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118
119 #define TIMx_OR_RMP_SHIFT 16U
120 #define TIMx_OR_RMP_MASK 0x0000FFFFU
121 #if defined(TIM1)
122 #define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
123 #endif /* TIM1 */
124 #if defined (TIM8)
125 #define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
126 #endif /* TIM8 */
127 #if defined(TIM14)
128 #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
129 #endif /* TIM14 */
130 #if defined(TIM16)
131 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132 #endif /* TIM16 */
133 #if defined(TIM20)
134 #define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)
135 #endif /* TIM20 */
136
137 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
138 #define DT_DELAY_1 ((uint8_t)0x7F)
139 #define DT_DELAY_2 ((uint8_t)0x3F)
140 #define DT_DELAY_3 ((uint8_t)0x1F)
141 #define DT_DELAY_4 ((uint8_t)0x1F)
142
143 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
144 #define DT_RANGE_1 ((uint8_t)0x00)
145 #define DT_RANGE_2 ((uint8_t)0x80)
146 #define DT_RANGE_3 ((uint8_t)0xC0)
147 #define DT_RANGE_4 ((uint8_t)0xE0)
148
149
150 /**
151 * @}
152 */
153
154 /* Private macros ------------------------------------------------------------*/
155 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
156 * @{
157 */
158 /** @brief Convert channel id into channel index.
159 * @param __CHANNEL__ This parameter can be one of the following values:
160 * @arg @ref LL_TIM_CHANNEL_CH1
161 * @arg @ref LL_TIM_CHANNEL_CH1N
162 * @arg @ref LL_TIM_CHANNEL_CH2
163 * @arg @ref LL_TIM_CHANNEL_CH2N
164 * @arg @ref LL_TIM_CHANNEL_CH3
165 * @arg @ref LL_TIM_CHANNEL_CH3N
166 * @arg @ref LL_TIM_CHANNEL_CH4
167 * @arg @ref LL_TIM_CHANNEL_CH5
168 * @arg @ref LL_TIM_CHANNEL_CH6
169 * @note CH5 and CH6 channels are not available for all F3 devices
170 * @retval none
171 */
172 #if defined(TIM_CCR5_CCR5)
173 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
174 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
182 #else
183 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
184 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
186 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
187 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
189 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
190 #endif
191
192 /** @brief Calculate the deadtime sampling period(in ps).
193 * @param __TIMCLK__ timer input clock frequency (in Hz).
194 * @param __CKD__ This parameter can be one of the following values:
195 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
196 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
197 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
198 * @retval none
199 */
200 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
201 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
202 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
203 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
204 /**
205 * @}
206 */
207
208
209 /* Exported types ------------------------------------------------------------*/
210 #if defined(USE_FULL_LL_DRIVER)
211 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
212 * @{
213 */
214
215 /**
216 * @brief TIM Time Base configuration structure definition.
217 */
218 typedef struct
219 {
220 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
221 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetPrescaler().*/
225
226 uint32_t CounterMode; /*!< Specifies the counter mode.
227 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetCounterMode().*/
231
232 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
233 Auto-Reload Register at the next update event.
234 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
235 Some timer instances may support 32 bits counters. In that case this parameter must
236 be a number between 0x0000 and 0xFFFFFFFF.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetAutoReload().*/
240
241 uint32_t ClockDivision; /*!< Specifies the clock division.
242 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetClockDivision().*/
246
247 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
248 reaches zero, an update event is generated and counting restarts
249 from the RCR value (N).
250 This means in PWM mode that (N+1) corresponds to:
251 - the number of PWM periods in edge-aligned mode
252 - the number of half PWM period in center-aligned mode
253 GP timers: this parameter must be a number between Min_Data = 0x00 and
254 Max_Data = 0xFF.
255 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
256 Max_Data = 0xFFFF.
257
258 This feature can be modified afterwards using unitary function
259 @ref LL_TIM_SetRepetitionCounter().*/
260 } LL_TIM_InitTypeDef;
261
262 /**
263 * @brief TIM Output Compare configuration structure definition.
264 */
265 typedef struct
266 {
267 uint32_t OCMode; /*!< Specifies the output mode.
268 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
269
270 This feature can be modified afterwards using unitary function
271 @ref LL_TIM_OC_SetMode().*/
272
273 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
280 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
281
282 This feature can be modified afterwards using unitary functions
283 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
284
285 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
286 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
287
288 This feature can be modified afterwards using unitary function
289 LL_TIM_OC_SetCompareCHx (x=1..6).*/
290
291 uint32_t OCPolarity; /*!< Specifies the output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
298 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetPolarity().*/
302
303
304 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309
310 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
311 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_OC_SetIdleState().*/
315 } LL_TIM_OC_InitTypeDef;
316
317 /**
318 * @brief TIM Input Capture configuration structure definition.
319 */
320
321 typedef struct
322 {
323
324 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
325 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetPolarity().*/
329
330 uint32_t ICActiveInput; /*!< Specifies the input.
331 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetActiveInput().*/
335
336 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
337 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetPrescaler().*/
341
342 uint32_t ICFilter; /*!< Specifies the input capture filter.
343 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
344
345 This feature can be modified afterwards using unitary function
346 @ref LL_TIM_IC_SetFilter().*/
347 } LL_TIM_IC_InitTypeDef;
348
349
350 /**
351 * @brief TIM Encoder interface configuration structure definition.
352 */
353 typedef struct
354 {
355 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
356 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_SetEncoderMode().*/
360
361 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
362 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetPolarity().*/
366
367 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
368 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetActiveInput().*/
372
373 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
374 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetPrescaler().*/
378
379 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
380 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetFilter().*/
384
385 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
386 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetPolarity().*/
390
391 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
392 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetActiveInput().*/
396
397 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
398 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetPrescaler().*/
402
403 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
404 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetFilter().*/
408
409 } LL_TIM_ENCODER_InitTypeDef;
410
411 /**
412 * @brief TIM Hall sensor interface configuration structure definition.
413 */
414 typedef struct
415 {
416
417 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
418 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetPolarity().*/
422
423 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
424 Prescaler must be set to get a maximum counter period longer than the
425 time interval between 2 consecutive changes on the Hall inputs.
426 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
427
428 This feature can be modified afterwards using unitary function
429 @ref LL_TIM_IC_SetPrescaler().*/
430
431 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
432 This parameter can be a value of
433 @ref TIM_LL_EC_IC_FILTER.
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_IC_SetFilter().*/
437
438 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
439 A positive pulse (TRGO event) is generated with a programmable delay every time
440 a change occurs on the Hall inputs.
441 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
442
443 This feature can be modified afterwards using unitary function
444 @ref LL_TIM_OC_SetCompareCH2().*/
445 } LL_TIM_HALLSENSOR_InitTypeDef;
446
447 /**
448 * @brief BDTR (Break and Dead Time) structure definition
449 */
450 typedef struct
451 {
452 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
453 This parameter can be a value of @ref TIM_LL_EC_OSSR
454
455 This feature can be modified afterwards using unitary function
456 @ref LL_TIM_SetOffStates()
457
458 @note This bit-field cannot be modified as long as LOCK level 2 has been
459 programmed. */
460
461 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
462 This parameter can be a value of @ref TIM_LL_EC_OSSI
463
464 This feature can be modified afterwards using unitary function
465 @ref LL_TIM_SetOffStates()
466
467 @note This bit-field cannot be modified as long as LOCK level 2 has been
468 programmed. */
469
470 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
471 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
472
473 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
474 register has been written, their content is frozen until the next reset.*/
475
476 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
477 switching-on of the outputs.
478 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
479
480 This feature can be modified afterwards using unitary function
481 @ref LL_TIM_OC_SetDeadTime()
482
483 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
484 programmed. */
485
486 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
487 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
488
489 This feature can be modified afterwards using unitary functions
490 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
491
492 @note This bit-field can not be modified as long as LOCK level 1 has been
493 programmed. */
494
495 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
496 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
497
498 This feature can be modified afterwards using unitary function
499 @ref LL_TIM_ConfigBRK()
500
501 @note This bit-field can not be modified as long as LOCK level 1 has been
502 programmed. */
503
504 #if defined(TIM_BDTR_BKF)
505 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
506 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
507
508 This feature can be modified afterwards using unitary function
509 @ref LL_TIM_ConfigBRK()
510
511 @note This bit-field can not be modified as long as LOCK level 1 has been
512 programmed. */
513
514 #endif /* TIM_BDTR_BKF */
515 #if defined(TIM_BDTR_BK2E)
516 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
518
519 This feature can be modified afterwards using unitary functions
520 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
526 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
527
528 This feature can be modified afterwards using unitary function
529 @ref LL_TIM_ConfigBRK2()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533
534 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
536
537 This feature can be modified afterwards using unitary function
538 @ref LL_TIM_ConfigBRK2()
539
540 @note This bit-field can not be modified as long as LOCK level 1 has been
541 programmed. */
542
543 #endif /* TIM_BDTR_BK2E */
544 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
545 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
546
547 This feature can be modified afterwards using unitary functions
548 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
549
550 @note This bit-field can not be modified as long as LOCK level 1 has been
551 programmed. */
552 } LL_TIM_BDTR_InitTypeDef;
553
554 /**
555 * @}
556 */
557 #endif /* USE_FULL_LL_DRIVER */
558
559 /* Exported constants --------------------------------------------------------*/
560 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
561 * @{
562 */
563
564 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
565 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
566 * @{
567 */
568 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
569 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
570 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
571 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
572 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
573 #if defined(TIM_CCMR1_OC1M_3)
574 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
575 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
576 #endif /* TIM_CCMR1_OC1M_3 */
577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
580 #if defined(TIM_SR_B2IF)
581 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
582 #endif /* TIM_SR_B2IF */
583 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
584 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
585 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
586 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
587 /**
588 * @}
589 */
590
591 #if defined(USE_FULL_LL_DRIVER)
592 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
593 * @{
594 */
595 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
596 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
597 /**
598 * @}
599 */
600 #if defined(TIM_BDTR_BK2E)
601
602 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
603 * @{
604 */
605 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
606 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
607 /**
608 * @}
609 */
610 #endif /* TIM_BDTR_BK2E */
611
612 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
613 * @{
614 */
615 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
616 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
617 /**
618 * @}
619 */
620 #endif /* USE_FULL_LL_DRIVER */
621
622 /** @defgroup TIM_LL_EC_IT IT Defines
623 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
624 * @{
625 */
626 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
627 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
628 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
629 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
630 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
631 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
632 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
633 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
634 /**
635 * @}
636 */
637
638 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
639 * @{
640 */
641 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
642 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
643 /**
644 * @}
645 */
646
647 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
648 * @{
649 */
650 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
651 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
657 * @{
658 */
659 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
660 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
661 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
662 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
663 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
664 /**
665 * @}
666 */
667
668 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
669 * @{
670 */
671 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
672 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
673 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
674 /**
675 * @}
676 */
677
678 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
679 * @{
680 */
681 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
682 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
683 /**
684 * @}
685 */
686
687 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
688 * @{
689 */
690 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
691 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
697 * @{
698 */
699 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
700 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
701 /**
702 * @}
703 */
704
705 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
706 * @{
707 */
708 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
709 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
710 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
711 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
712 /**
713 * @}
714 */
715
716 /** @defgroup TIM_LL_EC_CHANNEL Channel
717 * @{
718 */
719 #if defined(TIM_CCMR1_OC1M_3)
720 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
721 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
722 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
723 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
724 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
725 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
726 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
727 #if defined(TIM_CCER_CC5E)
728 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
729 #endif /* TIM_CCER_CC5E */
730 #if defined(TIM_CCER_CC6E)
731 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
732 #endif /* TIM_CCER_CC6E */
733 #else
734 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
735 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
736 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
737 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
738 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
739 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
740 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
741 #endif
742 /**
743 * @}
744 */
745
746 #if defined(USE_FULL_LL_DRIVER)
747 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
748 * @{
749 */
750 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
751 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
752 /**
753 * @}
754 */
755 #endif /* USE_FULL_LL_DRIVER */
756
757 /** Legacy definitions for compatibility purpose
758 @cond 0
759 */
760 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
761 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
762 /**
763 @endcond
764 */
765
766 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
767 * @{
768 */
769 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
770 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
771 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
772 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
773 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
774 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
775 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
776 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
777 #if defined(TIM_CCMR1_OC1M_3)
778 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
779 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
780 #endif
781 #if defined(TIM_CCMR1_OC1M_3)
782 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
783 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
784 #endif
785 #if defined(TIM_CCMR1_OC1M_3)
786 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
787 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
788 #endif
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
794 * @{
795 */
796 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
797 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
803 * @{
804 */
805 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
806 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
807 /**
808 * @}
809 */
810
811 #if defined(TIM_CCR5_CCR5)
812 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
813 * @{
814 */
815 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
816 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
817 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
818 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
819 /**
820 * @}
821 */
822 #endif /* TIM_CCR5_CCR5 */
823
824 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
825 * @{
826 */
827 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
828 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
829 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
830 /**
831 * @}
832 */
833
834 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
835 * @{
836 */
837 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
838 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
839 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
840 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
846 * @{
847 */
848 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
849 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
850 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
851 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
853 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
854 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
855 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
856 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
857 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
858 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
859 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
860 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
861 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
862 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
863 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
864 /**
865 * @}
866 */
867
868 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
869 * @{
870 */
871 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
872 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
873 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
874 /**
875 * @}
876 */
877
878 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
879 * @{
880 */
881 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
882 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
883 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
889 * @{
890 */
891 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
892 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
893 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
894 /**
895 * @}
896 */
897
898 /** @defgroup TIM_LL_EC_TRGO Trigger Output
899 * @{
900 */
901 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
902 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
903 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
904 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
905 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
906 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
907 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
908 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
909 /**
910 * @}
911 */
912
913 #if defined(TIM_CR2_MMS2)
914 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
915 * @{
916 */
917 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
918 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
919 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
920 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
921 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
922 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
933 /**
934 * @}
935 */
936 #endif /* TIM_CR2_MMS2 */
937
938 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
939 * @{
940 */
941 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
942 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
943 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
944 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
945 #if defined (TIM_SMCR_SMS_3)
946 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
947 #endif /* TIM_SMCR_SMS_3 */
948 /**
949 * @}
950 */
951
952 /** @defgroup TIM_LL_EC_TS Trigger Selection
953 * @{
954 */
955 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
956 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
957 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
958 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
959 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
960 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
961 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
962 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
963 /**
964 * @}
965 */
966
967 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
968 * @{
969 */
970 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
971 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
972 /**
973 * @}
974 */
975
976 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
977 * @{
978 */
979 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
980 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
981 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
982 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
983 /**
984 * @}
985 */
986
987 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
988 * @{
989 */
990 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
991 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
992 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
993 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
994 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
995 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
996 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
997 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
998 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
999 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1000 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1001 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1002 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1003 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1004 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1005 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1006 /**
1007 * @}
1008 */
1009
1010
1011 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1012 * @{
1013 */
1014 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1015 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1016 /**
1017 * @}
1018 */
1019
1020 #if defined(TIM_BDTR_BKF)
1021 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1022 * @{
1023 */
1024 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1025 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1026 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1027 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1028 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1029 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1030 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1031 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1032 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1033 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1034 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1035 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1036 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1037 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1038 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1039 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1040 /**
1041 * @}
1042 */
1043 #endif /* TIM_BDTR_BKF */
1044
1045 #if defined(TIM_BDTR_BK2P)
1046 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1047 * @{
1048 */
1049 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1050 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1051 /**
1052 * @}
1053 */
1054 #endif /* TIM_BDTR_BK2P */
1055
1056 #if defined(TIM_BDTR_BK2F)
1057 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1058 * @{
1059 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1061 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1065 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1066 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1067 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1068 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1069 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1070 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1071 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1072 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1073 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1074 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1075 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1076 /**
1077 * @}
1078 */
1079 #endif /* TIM_BDTR_BK2F */
1080
1081 /** @defgroup TIM_LL_EC_OSSI OSSI
1082 * @{
1083 */
1084 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1085 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup TIM_LL_EC_OSSR OSSR
1091 * @{
1092 */
1093 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1094 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1095 /**
1096 * @}
1097 */
1098
1099
1100 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1101 * @{
1102 */
1103 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1104 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1105 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1106 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1107 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1108 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1109 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1110 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1111 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1112 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1113 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1114 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1115 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1116 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1117 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1118 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1119 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1120 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1121 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1122 #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E)
1123 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1124 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1125 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1126 #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1132 * @{
1133 */
1134 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1135 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1136 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1137 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1138 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1139 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1140 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1141 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1142 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1143 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1144 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1145 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1146 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1147 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1148 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1149 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1150 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1151 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1152 /**
1153 * @}
1154 */
1155
1156 #if defined(TIM1)
1157 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1158 * @{
1159 */
1160 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1161 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1162 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1163 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1164 /**
1165 * @}
1166 */
1167 #if defined(ADC4)
1168 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC4_RMP TIM1 External Trigger ADC4 Remap
1169 * @{
1170 */
1171 #define LL_TIM_TIM1_ETR_ADC4_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/
1172 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
1173 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
1174 #define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
1175 /**
1176 * @}
1177 */
1178 #else
1179 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
1180 * @{
1181 */
1182 #define LL_TIM_TIM1_ETR_ADC2_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/
1183 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
1184 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
1185 #define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
1186 /**
1187 * @}
1188 */
1189 #endif /* ADC4 */
1190 #endif /* TIM1 */
1191 #if defined(TIM8)
1192 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1193 * @{
1194 */
1195 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1196 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1197 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1198 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1199 /**
1200 * @}
1201 */
1202
1203 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1204 * @{
1205 */
1206 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1207 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1208 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1209 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1210 /**
1211 * @}
1212 */
1213 #endif /* TIM8 */
1214 #if defined(TIM16)
1215 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1216 * @{
1217 */
1218 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */
1219 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1220 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */
1221 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1222 /**
1223 * @}
1224 */
1225 #endif /* TIM16 */
1226 #if defined(TIM20)
1227 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
1228 * @{
1229 */
1230 #define LL_TIM_TIM20_ETR_ADC3_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
1231 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */
1232 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
1233 #define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
1239 * @{
1240 */
1241 #define LL_TIM_TIM20_ETR_ADC4_RMP_NC TIM20_OR_RMP_MASK /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
1242 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
1243 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
1244 #define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
1245 /**
1246 * @}
1247 */
1248 #endif /* TIM20 */
1249 #if defined(TIM14)
1250 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
1251 * @{
1252 */
1253 #define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to GPIO */
1254 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */
1255 #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */
1256 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
1257 /**
1258 * @}
1259 */
1260 #endif /* TIM14 */
1261
1262 #if defined(TIM_SMCR_OCCS)
1263 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1264 * @{
1265 */
1266 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1267 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1268 /**
1269 * @}
1270 */
1271
1272 #endif /* TIM_SMCR_OCCS*/
1273
1274 /**
1275 * @}
1276 */
1277
1278 /* Exported macro ------------------------------------------------------------*/
1279 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1280 * @{
1281 */
1282
1283 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1284 * @{
1285 */
1286 /**
1287 * @brief Write a value in TIM register.
1288 * @param __INSTANCE__ TIM Instance
1289 * @param __REG__ Register to be written
1290 * @param __VALUE__ Value to be written in the register
1291 * @retval None
1292 */
1293 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1294
1295 /**
1296 * @brief Read a value in TIM register.
1297 * @param __INSTANCE__ TIM Instance
1298 * @param __REG__ Register to be read
1299 * @retval Register value
1300 */
1301 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1302 /**
1303 * @}
1304 */
1305
1306 /**
1307 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1308 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1309 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1310 * to TIMx_CNT register bit 31)
1311 * @param __CNT__ Counter value
1312 * @retval UIF status bit
1313 */
1314 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1315 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1316
1317 /**
1318 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1319 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1320 * @param __TIMCLK__ timer input clock frequency (in Hz)
1321 * @param __CKD__ This parameter can be one of the following values:
1322 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1323 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1324 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1325 * @param __DT__ deadtime duration (in ns)
1326 * @retval DTG[0:7]
1327 */
1328 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1329 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1330 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1331 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1332 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1333 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1334 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1335 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1336 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1337 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1338 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1339 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1340 0U)
1341
1342 /**
1343 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1344 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1345 * @param __TIMCLK__ timer input clock frequency (in Hz)
1346 * @param __CNTCLK__ counter clock frequency (in Hz)
1347 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1348 */
1349 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1350 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1351
1352 /**
1353 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1354 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1355 * @param __TIMCLK__ timer input clock frequency (in Hz)
1356 * @param __PSC__ prescaler
1357 * @param __FREQ__ output signal frequency (in Hz)
1358 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1359 */
1360 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1361 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1362
1363 /**
1364 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1365 * active/inactive delay.
1366 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1367 * @param __TIMCLK__ timer input clock frequency (in Hz)
1368 * @param __PSC__ prescaler
1369 * @param __DELAY__ timer output compare active/inactive delay (in us)
1370 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1371 */
1372 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1373 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1374 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1375
1376 /**
1377 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1378 * (when the timer operates in one pulse mode).
1379 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1380 * @param __TIMCLK__ timer input clock frequency (in Hz)
1381 * @param __PSC__ prescaler
1382 * @param __DELAY__ timer output compare active/inactive delay (in us)
1383 * @param __PULSE__ pulse duration (in us)
1384 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1385 */
1386 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1387 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1388 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1389
1390 /**
1391 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1392 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1393 * @param __ICPSC__ This parameter can be one of the following values:
1394 * @arg @ref LL_TIM_ICPSC_DIV1
1395 * @arg @ref LL_TIM_ICPSC_DIV2
1396 * @arg @ref LL_TIM_ICPSC_DIV4
1397 * @arg @ref LL_TIM_ICPSC_DIV8
1398 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1399 */
1400 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1401 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1402
1403
1404 /**
1405 * @}
1406 */
1407
1408 /* Exported functions --------------------------------------------------------*/
1409 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1410 * @{
1411 */
1412
1413 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1414 * @{
1415 */
1416 /**
1417 * @brief Enable timer counter.
1418 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1419 * @param TIMx Timer instance
1420 * @retval None
1421 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1422 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1423 {
1424 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1425 }
1426
1427 /**
1428 * @brief Disable timer counter.
1429 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1430 * @param TIMx Timer instance
1431 * @retval None
1432 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1433 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1434 {
1435 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1436 }
1437
1438 /**
1439 * @brief Indicates whether the timer counter is enabled.
1440 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1441 * @param TIMx Timer instance
1442 * @retval State of bit (1 or 0).
1443 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1444 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1445 {
1446 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1447 }
1448
1449 /**
1450 * @brief Enable update event generation.
1451 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1452 * @param TIMx Timer instance
1453 * @retval None
1454 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1455 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1456 {
1457 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1458 }
1459
1460 /**
1461 * @brief Disable update event generation.
1462 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1463 * @param TIMx Timer instance
1464 * @retval None
1465 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1466 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1467 {
1468 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1469 }
1470
1471 /**
1472 * @brief Indicates whether update event generation is enabled.
1473 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1474 * @param TIMx Timer instance
1475 * @retval Inverted state of bit (0 or 1).
1476 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1477 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1478 {
1479 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1480 }
1481
1482 /**
1483 * @brief Set update event source
1484 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1485 * generate an update interrupt or DMA request if enabled:
1486 * - Counter overflow/underflow
1487 * - Setting the UG bit
1488 * - Update generation through the slave mode controller
1489 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1490 * overflow/underflow generates an update interrupt or DMA request if enabled.
1491 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1492 * @param TIMx Timer instance
1493 * @param UpdateSource This parameter can be one of the following values:
1494 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1495 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1496 * @retval None
1497 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1498 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1499 {
1500 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1501 }
1502
1503 /**
1504 * @brief Get actual event update source
1505 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1506 * @param TIMx Timer instance
1507 * @retval Returned value can be one of the following values:
1508 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1509 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1510 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1511 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1512 {
1513 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1514 }
1515
1516 /**
1517 * @brief Set one pulse mode (one shot v.s. repetitive).
1518 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1519 * @param TIMx Timer instance
1520 * @param OnePulseMode This parameter can be one of the following values:
1521 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1522 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1523 * @retval None
1524 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1525 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1526 {
1527 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1528 }
1529
1530 /**
1531 * @brief Get actual one pulse mode.
1532 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1533 * @param TIMx Timer instance
1534 * @retval Returned value can be one of the following values:
1535 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1536 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1537 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1538 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1539 {
1540 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1541 }
1542
1543 /**
1544 * @brief Set the timer counter counting mode.
1545 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1546 * check whether or not the counter mode selection feature is supported
1547 * by a timer instance.
1548 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1549 * requires a timer reset to avoid unexpected direction
1550 * due to DIR bit readonly in center aligned mode.
1551 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1552 * CR1 CMS LL_TIM_SetCounterMode
1553 * @param TIMx Timer instance
1554 * @param CounterMode This parameter can be one of the following values:
1555 * @arg @ref LL_TIM_COUNTERMODE_UP
1556 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1557 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1558 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1559 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1560 * @retval None
1561 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1562 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1563 {
1564 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1565 }
1566
1567 /**
1568 * @brief Get actual counter mode.
1569 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1570 * check whether or not the counter mode selection feature is supported
1571 * by a timer instance.
1572 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1573 * CR1 CMS LL_TIM_GetCounterMode
1574 * @param TIMx Timer instance
1575 * @retval Returned value can be one of the following values:
1576 * @arg @ref LL_TIM_COUNTERMODE_UP
1577 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1578 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1579 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1580 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1581 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1582 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1583 {
1584 uint32_t counter_mode;
1585
1586 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1587
1588 if (counter_mode == 0U)
1589 {
1590 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1591 }
1592
1593 return counter_mode;
1594 }
1595
1596 /**
1597 * @brief Enable auto-reload (ARR) preload.
1598 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1599 * @param TIMx Timer instance
1600 * @retval None
1601 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1602 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1603 {
1604 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1605 }
1606
1607 /**
1608 * @brief Disable auto-reload (ARR) preload.
1609 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1610 * @param TIMx Timer instance
1611 * @retval None
1612 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1613 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1614 {
1615 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1616 }
1617
1618 /**
1619 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1620 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1621 * @param TIMx Timer instance
1622 * @retval State of bit (1 or 0).
1623 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1624 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1625 {
1626 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1631 * (when supported) and the digital filters.
1632 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1633 * whether or not the clock division feature is supported by the timer
1634 * instance.
1635 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1636 * @param TIMx Timer instance
1637 * @param ClockDivision This parameter can be one of the following values:
1638 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1639 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1640 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1641 * @retval None
1642 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1643 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1644 {
1645 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1646 }
1647
1648 /**
1649 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1650 * generators (when supported) and the digital filters.
1651 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1652 * whether or not the clock division feature is supported by the timer
1653 * instance.
1654 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1655 * @param TIMx Timer instance
1656 * @retval Returned value can be one of the following values:
1657 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1658 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1659 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1660 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1661 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1662 {
1663 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1664 }
1665
1666 /**
1667 * @brief Set the counter value.
1668 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1669 * whether or not a timer instance supports a 32 bits counter.
1670 * @rmtoll CNT CNT LL_TIM_SetCounter
1671 * @param TIMx Timer instance
1672 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1673 * @retval None
1674 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1675 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1676 {
1677 WRITE_REG(TIMx->CNT, Counter);
1678 }
1679
1680 /**
1681 * @brief Get the counter value.
1682 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1683 * whether or not a timer instance supports a 32 bits counter.
1684 * @rmtoll CNT CNT LL_TIM_GetCounter
1685 * @param TIMx Timer instance
1686 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1687 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1688 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1689 {
1690 return (uint32_t)(READ_REG(TIMx->CNT));
1691 }
1692
1693 /**
1694 * @brief Get the current direction of the counter
1695 * @rmtoll CR1 DIR LL_TIM_GetDirection
1696 * @param TIMx Timer instance
1697 * @retval Returned value can be one of the following values:
1698 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1699 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1700 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1701 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1702 {
1703 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1704 }
1705
1706 /**
1707 * @brief Set the prescaler value.
1708 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1709 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1710 * prescaler ratio is taken into account at the next update event.
1711 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1712 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1713 * @param TIMx Timer instance
1714 * @param Prescaler between Min_Data=0 and Max_Data=65535
1715 * @retval None
1716 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1717 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1718 {
1719 WRITE_REG(TIMx->PSC, Prescaler);
1720 }
1721
1722 /**
1723 * @brief Get the prescaler value.
1724 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1725 * @param TIMx Timer instance
1726 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1727 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1728 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1729 {
1730 return (uint32_t)(READ_REG(TIMx->PSC));
1731 }
1732
1733 /**
1734 * @brief Set the auto-reload value.
1735 * @note The counter is blocked while the auto-reload value is null.
1736 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1737 * whether or not a timer instance supports a 32 bits counter.
1738 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1739 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1740 * @param TIMx Timer instance
1741 * @param AutoReload between Min_Data=0 and Max_Data=65535
1742 * @retval None
1743 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1744 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1745 {
1746 WRITE_REG(TIMx->ARR, AutoReload);
1747 }
1748
1749 /**
1750 * @brief Get the auto-reload value.
1751 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1752 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1753 * whether or not a timer instance supports a 32 bits counter.
1754 * @param TIMx Timer instance
1755 * @retval Auto-reload value
1756 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1757 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1758 {
1759 return (uint32_t)(READ_REG(TIMx->ARR));
1760 }
1761
1762 /**
1763 * @brief Set the repetition counter value.
1764 * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
1765 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1766 * whether or not a timer instance supports a repetition counter.
1767 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1768 * @param TIMx Timer instance
1769 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1770 * @retval None
1771 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1772 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1773 {
1774 WRITE_REG(TIMx->RCR, RepetitionCounter);
1775 }
1776
1777 /**
1778 * @brief Get the repetition counter value.
1779 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1780 * whether or not a timer instance supports a repetition counter.
1781 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1782 * @param TIMx Timer instance
1783 * @retval Repetition counter value
1784 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1785 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1786 {
1787 return (uint32_t)(READ_REG(TIMx->RCR));
1788 }
1789
1790 #if defined(TIM_CR1_UIFREMAP)
1791 /**
1792 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1793 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1794 * in an atomic way.
1795 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1796 * @param TIMx Timer instance
1797 * @retval None
1798 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1799 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1800 {
1801 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1802 }
1803
1804 /**
1805 * @brief Disable update interrupt flag (UIF) remapping.
1806 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1807 * @param TIMx Timer instance
1808 * @retval None
1809 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1810 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1811 {
1812 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1813 }
1814
1815 /**
1816 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1817 * @param Counter Counter value
1818 * @retval State of bit (1 or 0).
1819 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1820 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1821 {
1822 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1823 }
1824
1825 #endif /* TIM_CR1_UIFREMAP */
1826 /**
1827 * @}
1828 */
1829
1830 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1831 * @{
1832 */
1833 /**
1834 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1835 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1836 * they are updated only when a commutation event (COM) occurs.
1837 * @note Only on channels that have a complementary output.
1838 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1839 * whether or not a timer instance is able to generate a commutation event.
1840 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1841 * @param TIMx Timer instance
1842 * @retval None
1843 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1844 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1845 {
1846 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1847 }
1848
1849 /**
1850 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1851 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1852 * whether or not a timer instance is able to generate a commutation event.
1853 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1854 * @param TIMx Timer instance
1855 * @retval None
1856 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1857 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1858 {
1859 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1860 }
1861
1862 /**
1863 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1864 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1865 * @param TIMx Timer instance
1866 * @retval State of bit (1 or 0).
1867 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1868 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1869 {
1870 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1871 }
1872
1873 /**
1874 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1875 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1876 * whether or not a timer instance is able to generate a commutation event.
1877 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1878 * @param TIMx Timer instance
1879 * @param CCUpdateSource This parameter can be one of the following values:
1880 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1881 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1882 * @retval None
1883 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1884 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1885 {
1886 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1887 }
1888
1889 /**
1890 * @brief Set the trigger of the capture/compare DMA request.
1891 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1892 * @param TIMx Timer instance
1893 * @param DMAReqTrigger This parameter can be one of the following values:
1894 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1895 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1896 * @retval None
1897 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1898 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1899 {
1900 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1901 }
1902
1903 /**
1904 * @brief Get actual trigger of the capture/compare DMA request.
1905 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1906 * @param TIMx Timer instance
1907 * @retval Returned value can be one of the following values:
1908 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1909 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1910 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1911 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1912 {
1913 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1914 }
1915
1916 /**
1917 * @brief Set the lock level to freeze the
1918 * configuration of several capture/compare parameters.
1919 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1920 * the lock mechanism is supported by a timer instance.
1921 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1922 * @param TIMx Timer instance
1923 * @param LockLevel This parameter can be one of the following values:
1924 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1925 * @arg @ref LL_TIM_LOCKLEVEL_1
1926 * @arg @ref LL_TIM_LOCKLEVEL_2
1927 * @arg @ref LL_TIM_LOCKLEVEL_3
1928 * @retval None
1929 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1930 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1931 {
1932 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1933 }
1934
1935 /**
1936 * @brief Enable capture/compare channels.
1937 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1938 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1939 * CCER CC2E LL_TIM_CC_EnableChannel\n
1940 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1941 * CCER CC3E LL_TIM_CC_EnableChannel\n
1942 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1943 * CCER CC4E LL_TIM_CC_EnableChannel\n
1944 * CCER CC5E LL_TIM_CC_EnableChannel\n
1945 * CCER CC6E LL_TIM_CC_EnableChannel
1946 * @param TIMx Timer instance
1947 * @param Channels This parameter can be a combination of the following values:
1948 * @arg @ref LL_TIM_CHANNEL_CH1
1949 * @arg @ref LL_TIM_CHANNEL_CH1N
1950 * @arg @ref LL_TIM_CHANNEL_CH2
1951 * @arg @ref LL_TIM_CHANNEL_CH2N
1952 * @arg @ref LL_TIM_CHANNEL_CH3
1953 * @arg @ref LL_TIM_CHANNEL_CH3N
1954 * @arg @ref LL_TIM_CHANNEL_CH4
1955 * @arg @ref LL_TIM_CHANNEL_CH5
1956 * @arg @ref LL_TIM_CHANNEL_CH6
1957 * @note CH5 and CH6 channels are not available for all F3 devices
1958 * @retval None
1959 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1960 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1961 {
1962 SET_BIT(TIMx->CCER, Channels);
1963 }
1964
1965 /**
1966 * @brief Disable capture/compare channels.
1967 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1968 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1969 * CCER CC2E LL_TIM_CC_DisableChannel\n
1970 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1971 * CCER CC3E LL_TIM_CC_DisableChannel\n
1972 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1973 * CCER CC4E LL_TIM_CC_DisableChannel\n
1974 * CCER CC5E LL_TIM_CC_DisableChannel\n
1975 * CCER CC6E LL_TIM_CC_DisableChannel
1976 * @param TIMx Timer instance
1977 * @param Channels This parameter can be a combination of the following values:
1978 * @arg @ref LL_TIM_CHANNEL_CH1
1979 * @arg @ref LL_TIM_CHANNEL_CH1N
1980 * @arg @ref LL_TIM_CHANNEL_CH2
1981 * @arg @ref LL_TIM_CHANNEL_CH2N
1982 * @arg @ref LL_TIM_CHANNEL_CH3
1983 * @arg @ref LL_TIM_CHANNEL_CH3N
1984 * @arg @ref LL_TIM_CHANNEL_CH4
1985 * @arg @ref LL_TIM_CHANNEL_CH5
1986 * @arg @ref LL_TIM_CHANNEL_CH6
1987 * @note CH5 and CH6 channels are not available for all F3 devices
1988 * @retval None
1989 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1990 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1991 {
1992 CLEAR_BIT(TIMx->CCER, Channels);
1993 }
1994
1995 /**
1996 * @brief Indicate whether channel(s) is(are) enabled.
1997 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1998 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1999 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2000 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2001 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2002 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2003 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2004 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2005 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2006 * @param TIMx Timer instance
2007 * @param Channels This parameter can be a combination of the following values:
2008 * @arg @ref LL_TIM_CHANNEL_CH1
2009 * @arg @ref LL_TIM_CHANNEL_CH1N
2010 * @arg @ref LL_TIM_CHANNEL_CH2
2011 * @arg @ref LL_TIM_CHANNEL_CH2N
2012 * @arg @ref LL_TIM_CHANNEL_CH3
2013 * @arg @ref LL_TIM_CHANNEL_CH3N
2014 * @arg @ref LL_TIM_CHANNEL_CH4
2015 * @arg @ref LL_TIM_CHANNEL_CH5
2016 * @arg @ref LL_TIM_CHANNEL_CH6
2017 * @note CH5 and CH6 channels are not available for all F3 devices
2018 * @retval State of bit (1 or 0).
2019 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2020 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2021 {
2022 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2023 }
2024
2025 /**
2026 * @}
2027 */
2028
2029 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2030 * @{
2031 */
2032 /**
2033 * @brief Configure an output channel.
2034 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2035 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2036 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2037 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2038 * @if STM32F334x8
2039 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2040 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2041 * @elseif STM32F303xC
2042 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2043 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2044 * @elseif STM32F302x8
2045 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2046 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2047 * @endif
2048 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2049 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2050 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2051 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2052 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2053 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2054 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2055 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2056 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2057 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2058 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2059 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2060 * @param TIMx Timer instance
2061 * @param Channel This parameter can be one of the following values:
2062 * @arg @ref LL_TIM_CHANNEL_CH1
2063 * @arg @ref LL_TIM_CHANNEL_CH2
2064 * @arg @ref LL_TIM_CHANNEL_CH3
2065 * @arg @ref LL_TIM_CHANNEL_CH4
2066 * @arg @ref LL_TIM_CHANNEL_CH5
2067 * @arg @ref LL_TIM_CHANNEL_CH6
2068 * @param Configuration This parameter must be a combination of all the following values:
2069 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2070 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2071 * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
2072 * @retval None
2073 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2074 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2075 {
2076 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2077 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2078 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2079 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2080 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2081 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2082 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2083 }
2084
2085 /**
2086 * @brief Define the behavior of the output reference signal OCxREF from which
2087 * OCx and OCxN (when relevant) are derived.
2088 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2089 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2090 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2091 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2092 * @if STM32F334x8
2093 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2094 * CCMR3 OC6M LL_TIM_OC_SetMode
2095 * @elseif STM32F303xC
2096 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2097 * CCMR3 OC6M LL_TIM_OC_SetMode
2098 * @elseif STM32F302x8
2099 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2100 * CCMR3 OC6M LL_TIM_OC_SetMode
2101 * @endif
2102 * @param TIMx Timer instance
2103 * @param Channel This parameter can be one of the following values:
2104 * @arg @ref LL_TIM_CHANNEL_CH1
2105 * @arg @ref LL_TIM_CHANNEL_CH2
2106 * @arg @ref LL_TIM_CHANNEL_CH3
2107 * @arg @ref LL_TIM_CHANNEL_CH4
2108 * @arg @ref LL_TIM_CHANNEL_CH5
2109 * @arg @ref LL_TIM_CHANNEL_CH6
2110 * @param Mode This parameter can be one of the following values:
2111 * @arg @ref LL_TIM_OCMODE_FROZEN
2112 * @arg @ref LL_TIM_OCMODE_ACTIVE
2113 * @arg @ref LL_TIM_OCMODE_INACTIVE
2114 * @arg @ref LL_TIM_OCMODE_TOGGLE
2115 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2116 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2117 * @arg @ref LL_TIM_OCMODE_PWM1
2118 * @arg @ref LL_TIM_OCMODE_PWM2
2119 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2120 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2121 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2122 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2123 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2124 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2125 * @note The following OC modes are not available on all F3 devices :
2126 * - LL_TIM_OCMODE_RETRIG_OPM1
2127 * - LL_TIM_OCMODE_RETRIG_OPM2
2128 * - LL_TIM_OCMODE_COMBINED_PWM1
2129 * - LL_TIM_OCMODE_COMBINED_PWM2
2130 * - LL_TIM_OCMODE_ASYMMETRIC_PWM1
2131 * - LL_TIM_OCMODE_ASYMMETRIC_PWM2
2132 * @note CH5 and CH6 channels are not available for all F3 devices
2133 * @retval None
2134 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2135 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2136 {
2137 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2138 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2139 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2140 }
2141
2142 /**
2143 * @brief Get the output compare mode of an output channel.
2144 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2145 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2146 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2147 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2148 * @if STM32F334x8
2149 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2150 * CCMR3 OC6M LL_TIM_OC_GetMode
2151 * @elseif STM32F303xC
2152 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2153 * CCMR3 OC6M LL_TIM_OC_GetMode
2154 * @elseif STM32F302x8
2155 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2156 * CCMR3 OC6M LL_TIM_OC_GetMode
2157 * @endif
2158 * @param TIMx Timer instance
2159 * @param Channel This parameter can be one of the following values:
2160 * @arg @ref LL_TIM_CHANNEL_CH1
2161 * @arg @ref LL_TIM_CHANNEL_CH2
2162 * @arg @ref LL_TIM_CHANNEL_CH3
2163 * @arg @ref LL_TIM_CHANNEL_CH4
2164 * @arg @ref LL_TIM_CHANNEL_CH5
2165 * @arg @ref LL_TIM_CHANNEL_CH6
2166 * @note The following OC modes are not available on all F3 devices :
2167 * - LL_TIM_OCMODE_RETRIG_OPM1
2168 * - LL_TIM_OCMODE_RETRIG_OPM2
2169 * - LL_TIM_OCMODE_COMBINED_PWM1
2170 * - LL_TIM_OCMODE_COMBINED_PWM2
2171 * - LL_TIM_OCMODE_ASYMMETRIC_PWM1
2172 * - LL_TIM_OCMODE_ASYMMETRIC_PWM2
2173 * @note CH5 and CH6 channels are not available for all F3 devices
2174 * @retval Returned value can be one of the following values:
2175 * @arg @ref LL_TIM_OCMODE_FROZEN
2176 * @arg @ref LL_TIM_OCMODE_ACTIVE
2177 * @arg @ref LL_TIM_OCMODE_INACTIVE
2178 * @arg @ref LL_TIM_OCMODE_TOGGLE
2179 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2180 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2181 * @arg @ref LL_TIM_OCMODE_PWM1
2182 * @arg @ref LL_TIM_OCMODE_PWM2
2183 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2184 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2185 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2186 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2187 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2188 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2189 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2190 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2191 {
2192 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2193 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2194 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2195 }
2196
2197 /**
2198 * @brief Set the polarity of an output channel.
2199 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2200 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2201 * CCER CC2P LL_TIM_OC_SetPolarity\n
2202 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2203 * CCER CC3P LL_TIM_OC_SetPolarity\n
2204 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2205 * CCER CC4P LL_TIM_OC_SetPolarity\n
2206 * CCER CC5P LL_TIM_OC_SetPolarity\n
2207 * CCER CC6P LL_TIM_OC_SetPolarity
2208 * @param TIMx Timer instance
2209 * @param Channel This parameter can be one of the following values:
2210 * @arg @ref LL_TIM_CHANNEL_CH1
2211 * @arg @ref LL_TIM_CHANNEL_CH1N
2212 * @arg @ref LL_TIM_CHANNEL_CH2
2213 * @arg @ref LL_TIM_CHANNEL_CH2N
2214 * @arg @ref LL_TIM_CHANNEL_CH3
2215 * @arg @ref LL_TIM_CHANNEL_CH3N
2216 * @arg @ref LL_TIM_CHANNEL_CH4
2217 * @arg @ref LL_TIM_CHANNEL_CH5
2218 * @arg @ref LL_TIM_CHANNEL_CH6
2219 * @param Polarity This parameter can be one of the following values:
2220 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2221 * @arg @ref LL_TIM_OCPOLARITY_LOW
2222 * @note CH5 and CH6 channels are not available for all F3 devices
2223 * @retval None
2224 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2225 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2226 {
2227 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2228 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2229 }
2230
2231 /**
2232 * @brief Get the polarity of an output channel.
2233 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2234 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2235 * CCER CC2P LL_TIM_OC_GetPolarity\n
2236 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2237 * CCER CC3P LL_TIM_OC_GetPolarity\n
2238 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2239 * CCER CC4P LL_TIM_OC_GetPolarity\n
2240 * CCER CC5P LL_TIM_OC_GetPolarity\n
2241 * CCER CC6P LL_TIM_OC_GetPolarity
2242 * @param TIMx Timer instance
2243 * @param Channel This parameter can be one of the following values:
2244 * @arg @ref LL_TIM_CHANNEL_CH1
2245 * @arg @ref LL_TIM_CHANNEL_CH1N
2246 * @arg @ref LL_TIM_CHANNEL_CH2
2247 * @arg @ref LL_TIM_CHANNEL_CH2N
2248 * @arg @ref LL_TIM_CHANNEL_CH3
2249 * @arg @ref LL_TIM_CHANNEL_CH3N
2250 * @arg @ref LL_TIM_CHANNEL_CH4
2251 * @arg @ref LL_TIM_CHANNEL_CH5
2252 * @arg @ref LL_TIM_CHANNEL_CH6
2253 * @note CH5 and CH6 channels are not available for all F3 devices
2254 * @retval Returned value can be one of the following values:
2255 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2256 * @arg @ref LL_TIM_OCPOLARITY_LOW
2257 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2258 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2259 {
2260 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2261 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2262 }
2263
2264 /**
2265 * @brief Set the IDLE state of an output channel
2266 * @note This function is significant only for the timer instances
2267 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2268 * can be used to check whether or not a timer instance provides
2269 * a break input.
2270 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2271 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2272 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2273 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2274 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2275 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2276 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2277 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2278 * CR2 OIS6 LL_TIM_OC_SetIdleState
2279 * @param TIMx Timer instance
2280 * @param Channel This parameter can be one of the following values:
2281 * @arg @ref LL_TIM_CHANNEL_CH1
2282 * @arg @ref LL_TIM_CHANNEL_CH1N
2283 * @arg @ref LL_TIM_CHANNEL_CH2
2284 * @arg @ref LL_TIM_CHANNEL_CH2N
2285 * @arg @ref LL_TIM_CHANNEL_CH3
2286 * @arg @ref LL_TIM_CHANNEL_CH3N
2287 * @arg @ref LL_TIM_CHANNEL_CH4
2288 * @arg @ref LL_TIM_CHANNEL_CH5
2289 * @arg @ref LL_TIM_CHANNEL_CH6
2290 * @param IdleState This parameter can be one of the following values:
2291 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2292 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2293 * @note CH5 and CH6 channels are not available for all F3 devices
2294 * @retval None
2295 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2296 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2297 {
2298 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2299 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2300 }
2301
2302 /**
2303 * @brief Get the IDLE state of an output channel
2304 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2305 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2306 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2307 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2308 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2309 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2310 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2311 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2312 * CR2 OIS6 LL_TIM_OC_GetIdleState
2313 * @param TIMx Timer instance
2314 * @param Channel This parameter can be one of the following values:
2315 * @arg @ref LL_TIM_CHANNEL_CH1
2316 * @arg @ref LL_TIM_CHANNEL_CH1N
2317 * @arg @ref LL_TIM_CHANNEL_CH2
2318 * @arg @ref LL_TIM_CHANNEL_CH2N
2319 * @arg @ref LL_TIM_CHANNEL_CH3
2320 * @arg @ref LL_TIM_CHANNEL_CH3N
2321 * @arg @ref LL_TIM_CHANNEL_CH4
2322 * @arg @ref LL_TIM_CHANNEL_CH5
2323 * @arg @ref LL_TIM_CHANNEL_CH6
2324 * @note CH5 and CH6 channels are not available for all F3 devices
2325 * @retval Returned value can be one of the following values:
2326 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2327 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2328 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2329 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2330 {
2331 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2332 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2333 }
2334
2335 /**
2336 * @brief Enable fast mode for the output channel.
2337 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2338 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2339 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2340 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2341 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2342 * @if STM32F334x8
2343 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2344 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2345 * @elseif STM32F303xC
2346 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2347 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2348 * @elseif STM32F302x8
2349 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2350 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2351 * @endif
2352 * @param TIMx Timer instance
2353 * @param Channel This parameter can be one of the following values:
2354 * @arg @ref LL_TIM_CHANNEL_CH1
2355 * @arg @ref LL_TIM_CHANNEL_CH2
2356 * @arg @ref LL_TIM_CHANNEL_CH3
2357 * @arg @ref LL_TIM_CHANNEL_CH4
2358 * @arg @ref LL_TIM_CHANNEL_CH5
2359 * @arg @ref LL_TIM_CHANNEL_CH6
2360 * @note OC5FE and OC6FE are not available for all F3 devices
2361 * @note CH5 and CH6 channels are not available for all F3 devices
2362 * @retval None
2363 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2364 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2365 {
2366 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2367 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2368 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2369
2370 }
2371
2372 /**
2373 * @brief Disable fast mode for the output channel.
2374 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2375 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2376 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2377 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2378 * @if STM32F334x8
2379 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2380 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2381 * @elseif STM32F303xC
2382 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2383 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2384 * @elseif STM32F302x8
2385 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2386 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2387 * @endif
2388 * @param TIMx Timer instance
2389 * @param Channel This parameter can be one of the following values:
2390 * @arg @ref LL_TIM_CHANNEL_CH1
2391 * @arg @ref LL_TIM_CHANNEL_CH2
2392 * @arg @ref LL_TIM_CHANNEL_CH3
2393 * @arg @ref LL_TIM_CHANNEL_CH4
2394 * @arg @ref LL_TIM_CHANNEL_CH5
2395 * @arg @ref LL_TIM_CHANNEL_CH6
2396 * @note OC5FE and OC6FE are not available for all F3 devices
2397 * @note CH5 and CH6 channels are not available for all F3 devices
2398 * @retval None
2399 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2400 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2401 {
2402 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2403 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2404 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2405
2406 }
2407
2408 /**
2409 * @brief Indicates whether fast mode is enabled for the output channel.
2410 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2411 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2412 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2413 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2414 * @if STM32F334x8
2415 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2416 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2417 * @elseif STM32F303xC
2418 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2419 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2420 * @elseif STM32F302x8
2421 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2422 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2423 * @endif
2424 * @param TIMx Timer instance
2425 * @param Channel This parameter can be one of the following values:
2426 * @arg @ref LL_TIM_CHANNEL_CH1
2427 * @arg @ref LL_TIM_CHANNEL_CH2
2428 * @arg @ref LL_TIM_CHANNEL_CH3
2429 * @arg @ref LL_TIM_CHANNEL_CH4
2430 * @arg @ref LL_TIM_CHANNEL_CH5
2431 * @arg @ref LL_TIM_CHANNEL_CH6
2432 * @note OC5FE and OC6FE are not available for all F3 devices
2433 * @note CH5 and CH6 channels are not available for all F3 devices
2434 * @retval State of bit (1 or 0).
2435 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2436 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2437 {
2438 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2439 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2440 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2441 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2442 }
2443
2444 /**
2445 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2446 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2447 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2448 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2449 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2450 * @if STM32F334x8
2451 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2452 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2453 * @elseif STM32F303xC
2454 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2455 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2456 * @elseif STM32F302x8
2457 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2458 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2459 * @endif
2460 * @param TIMx Timer instance
2461 * @param Channel This parameter can be one of the following values:
2462 * @arg @ref LL_TIM_CHANNEL_CH1
2463 * @arg @ref LL_TIM_CHANNEL_CH2
2464 * @arg @ref LL_TIM_CHANNEL_CH3
2465 * @arg @ref LL_TIM_CHANNEL_CH4
2466 * @arg @ref LL_TIM_CHANNEL_CH5
2467 * @arg @ref LL_TIM_CHANNEL_CH6
2468 * @note OC5PE and OC6PE are not available for all F3 devices
2469 * @note CH5 and CH6 channels are not available for all F3 devices
2470 * @retval None
2471 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2472 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2473 {
2474 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2475 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2476 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2477 }
2478
2479 /**
2480 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2481 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2482 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2483 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2484 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2485 * @if STM32F334x8
2486 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2487 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2488 * @elseif STM32F303xC
2489 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2490 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2491 * @elseif STM32F302x8
2492 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2493 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2494 * @endif
2495 * @param TIMx Timer instance
2496 * @param Channel This parameter can be one of the following values:
2497 * @arg @ref LL_TIM_CHANNEL_CH1
2498 * @arg @ref LL_TIM_CHANNEL_CH2
2499 * @arg @ref LL_TIM_CHANNEL_CH3
2500 * @arg @ref LL_TIM_CHANNEL_CH4
2501 * @arg @ref LL_TIM_CHANNEL_CH5
2502 * @arg @ref LL_TIM_CHANNEL_CH6
2503 * @note OC5PE and OC6PE are not available for all F3 devices
2504 * @note CH5 and CH6 channels are not available for all F3 devices
2505 * @retval None
2506 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2507 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2508 {
2509 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2510 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2511 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2512 }
2513
2514 /**
2515 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2516 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2517 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2518 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2519 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2520 * @if STM32F334x8
2521 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2522 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2523 * @elseif STM32F303xC
2524 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2525 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2526 * @elseif STM32F302x8
2527 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2528 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2529 * @endif
2530 * @param TIMx Timer instance
2531 * @param Channel This parameter can be one of the following values:
2532 * @arg @ref LL_TIM_CHANNEL_CH1
2533 * @arg @ref LL_TIM_CHANNEL_CH2
2534 * @arg @ref LL_TIM_CHANNEL_CH3
2535 * @arg @ref LL_TIM_CHANNEL_CH4
2536 * @arg @ref LL_TIM_CHANNEL_CH5
2537 * @arg @ref LL_TIM_CHANNEL_CH6
2538 * @note OC5PE and OC6PE are not available for all F3 devices
2539 * @note CH5 and CH6 channels are not available for all F3 devices
2540 * @retval State of bit (1 or 0).
2541 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2542 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2543 {
2544 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2545 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2546 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2547 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2548 }
2549
2550 /**
2551 * @brief Enable clearing the output channel on an external event.
2552 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2553 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2554 * or not a timer instance can clear the OCxREF signal on an external event.
2555 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2556 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2557 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2558 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2559 * @if STM32F334x8
2560 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2561 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2562 * @elseif STM32F303xC
2563 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2564 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2565 * @elseif STM32F302x8
2566 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2567 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2568 * @endif
2569 * @param TIMx Timer instance
2570 * @param Channel This parameter can be one of the following values:
2571 * @arg @ref LL_TIM_CHANNEL_CH1
2572 * @arg @ref LL_TIM_CHANNEL_CH2
2573 * @arg @ref LL_TIM_CHANNEL_CH3
2574 * @arg @ref LL_TIM_CHANNEL_CH4
2575 * @arg @ref LL_TIM_CHANNEL_CH5
2576 * @arg @ref LL_TIM_CHANNEL_CH6
2577 * @note OC5CE and OC6CE are not available for all F3 devices
2578 * @note CH5 and CH6 channels are not available for all F3 devices
2579 * @retval None
2580 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2581 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2582 {
2583 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2584 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2585 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2586 }
2587
2588 /**
2589 * @brief Disable clearing the output channel on an external event.
2590 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2591 * or not a timer instance can clear the OCxREF signal on an external event.
2592 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2593 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2594 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2595 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2596 * @if STM32F334x8
2597 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2598 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2599 * @elseif STM32F303xC
2600 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2601 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2602 * @elseif STM32F302x8
2603 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2604 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2605 * @endif
2606 * @param TIMx Timer instance
2607 * @param Channel This parameter can be one of the following values:
2608 * @arg @ref LL_TIM_CHANNEL_CH1
2609 * @arg @ref LL_TIM_CHANNEL_CH2
2610 * @arg @ref LL_TIM_CHANNEL_CH3
2611 * @arg @ref LL_TIM_CHANNEL_CH4
2612 * @arg @ref LL_TIM_CHANNEL_CH5
2613 * @arg @ref LL_TIM_CHANNEL_CH6
2614 * @note OC5CE and OC6CE are not available for all F3 devices
2615 * @note CH5 and CH6 channels are not available for all F3 devices
2616 * @retval None
2617 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2618 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2619 {
2620 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2621 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2622 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2623 }
2624
2625 /**
2626 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2627 * @note This function enables clearing the output channel on an external event.
2628 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2629 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2630 * or not a timer instance can clear the OCxREF signal on an external event.
2631 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2632 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2633 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2634 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2635 * @if STM32F334x8
2636 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2637 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2638 * @elseif STM32F303xC
2639 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2640 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2641 * @elseif STM32F302x8
2642 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2643 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2644 * @endif
2645 * @param TIMx Timer instance
2646 * @param Channel This parameter can be one of the following values:
2647 * @arg @ref LL_TIM_CHANNEL_CH1
2648 * @arg @ref LL_TIM_CHANNEL_CH2
2649 * @arg @ref LL_TIM_CHANNEL_CH3
2650 * @arg @ref LL_TIM_CHANNEL_CH4
2651 * @arg @ref LL_TIM_CHANNEL_CH5
2652 * @arg @ref LL_TIM_CHANNEL_CH6
2653 * @note OC5CE and OC6CE are not available for all F3 devices
2654 * @note CH5 and CH6 channels are not available for all F3 devices
2655 * @retval State of bit (1 or 0).
2656 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2657 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2658 {
2659 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2660 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2661 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2662 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2663 }
2664
2665 /**
2666 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2667 * the Ocx and OCxN signals).
2668 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2669 * dead-time insertion feature is supported by a timer instance.
2670 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2671 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2672 * @param TIMx Timer instance
2673 * @param DeadTime between Min_Data=0 and Max_Data=255
2674 * @retval None
2675 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2676 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2677 {
2678 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2679 }
2680
2681 /**
2682 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2683 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2684 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2685 * whether or not a timer instance supports a 32 bits counter.
2686 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2687 * output channel 1 is supported by a timer instance.
2688 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2689 * @param TIMx Timer instance
2690 * @param CompareValue between Min_Data=0 and Max_Data=65535
2691 * @retval None
2692 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2693 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2694 {
2695 WRITE_REG(TIMx->CCR1, CompareValue);
2696 }
2697
2698 /**
2699 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2700 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2701 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2702 * whether or not a timer instance supports a 32 bits counter.
2703 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2704 * output channel 2 is supported by a timer instance.
2705 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2706 * @param TIMx Timer instance
2707 * @param CompareValue between Min_Data=0 and Max_Data=65535
2708 * @retval None
2709 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2710 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2711 {
2712 WRITE_REG(TIMx->CCR2, CompareValue);
2713 }
2714
2715 /**
2716 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2717 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2718 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2719 * whether or not a timer instance supports a 32 bits counter.
2720 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2721 * output channel is supported by a timer instance.
2722 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2723 * @param TIMx Timer instance
2724 * @param CompareValue between Min_Data=0 and Max_Data=65535
2725 * @retval None
2726 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2727 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2728 {
2729 WRITE_REG(TIMx->CCR3, CompareValue);
2730 }
2731
2732 /**
2733 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2734 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2735 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2736 * whether or not a timer instance supports a 32 bits counter.
2737 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2738 * output channel 4 is supported by a timer instance.
2739 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2740 * @param TIMx Timer instance
2741 * @param CompareValue between Min_Data=0 and Max_Data=65535
2742 * @retval None
2743 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2744 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2745 {
2746 WRITE_REG(TIMx->CCR4, CompareValue);
2747 }
2748
2749 #if defined(TIM_CCR5_CCR5)
2750 /**
2751 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2752 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2753 * output channel 5 is supported by a timer instance.
2754 * @if STM32F334x8
2755 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2756 * @elseif STM32F303xC
2757 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2758 * @elseif STM32F302x8
2759 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2760 * @endif
2761 * @param TIMx Timer instance
2762 * @param CompareValue between Min_Data=0 and Max_Data=65535
2763 * @note CH5 channel is not available for all F3 devices
2764 * @retval None
2765 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2766 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2767 {
2768 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2769 }
2770
2771 #endif /* TIM_CCR5_CCR5 */
2772 #if defined(TIM_CCR6_CCR6)
2773 /**
2774 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2775 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2776 * output channel 6 is supported by a timer instance.
2777 * @if STM32F344x8
2778 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2779 * @elseif STM32F303xC
2780 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2781 * @elseif STM32F302x8
2782 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2783 * @endif
2784 * @param TIMx Timer instance
2785 * @param CompareValue between Min_Data=0 and Max_Data=65535
2786 * @note CH6 channel is not available for all F3 devices
2787 * @retval None
2788 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2789 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2790 {
2791 WRITE_REG(TIMx->CCR6, CompareValue);
2792 }
2793
2794 #endif /* TIM_CCR6_CCR6 */
2795 /**
2796 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2797 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2798 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2799 * whether or not a timer instance supports a 32 bits counter.
2800 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2801 * output channel 1 is supported by a timer instance.
2802 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2803 * @param TIMx Timer instance
2804 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2805 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2806 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2807 {
2808 return (uint32_t)(READ_REG(TIMx->CCR1));
2809 }
2810
2811 /**
2812 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2813 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2814 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2815 * whether or not a timer instance supports a 32 bits counter.
2816 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2817 * output channel 2 is supported by a timer instance.
2818 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2819 * @param TIMx Timer instance
2820 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2821 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2822 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2823 {
2824 return (uint32_t)(READ_REG(TIMx->CCR2));
2825 }
2826
2827 /**
2828 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2829 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2830 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2831 * whether or not a timer instance supports a 32 bits counter.
2832 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2833 * output channel 3 is supported by a timer instance.
2834 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2835 * @param TIMx Timer instance
2836 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2837 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2838 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2839 {
2840 return (uint32_t)(READ_REG(TIMx->CCR3));
2841 }
2842
2843 /**
2844 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2845 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2846 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2847 * whether or not a timer instance supports a 32 bits counter.
2848 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2849 * output channel 4 is supported by a timer instance.
2850 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2851 * @param TIMx Timer instance
2852 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2853 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2854 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2855 {
2856 return (uint32_t)(READ_REG(TIMx->CCR4));
2857 }
2858
2859 #if defined(TIM_CCR5_CCR5)
2860 /**
2861 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2862 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2863 * output channel 5 is supported by a timer instance.
2864 * @if STM32F334x8
2865 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2866 * @elseif STM32F303xC
2867 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2868 * @elseif STM32F302x8
2869 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2870 * @endif
2871 * @param TIMx Timer instance
2872 * @note CH5 channel is not available for all F3 devices
2873 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2874 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2875 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2876 {
2877 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2878 }
2879
2880 #endif /* TIM_CCR5_CCR5 */
2881 #if defined(TIM_CCR6_CCR6)
2882 /**
2883 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2884 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2885 * output channel 6 is supported by a timer instance.
2886 * @if STM32F334x8
2887 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2888 * @elseif STM32F303xC
2889 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2890 * @elseif STM32F302x8
2891 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2892 * @endif
2893 * @param TIMx Timer instance
2894 * @note CH6 channel is not available for all F3 devices
2895 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2896 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2897 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2898 {
2899 return (uint32_t)(READ_REG(TIMx->CCR6));
2900 }
2901
2902 #endif /* TIM_CCR6_CCR6 */
2903 #if defined(TIM_CCR5_CCR5)
2904 /**
2905 * @brief Select on which reference signal the OC5REF is combined to.
2906 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2907 * whether or not a timer instance supports the combined 3-phase PWM mode.
2908 * @if STM32F334x8
2909 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2910 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2911 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2912 * @elseif STM32F303xC
2913 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2914 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2915 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2916 * @elseif STM32F302x8
2917 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2918 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2919 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2920 * @endif
2921 * @param TIMx Timer instance
2922 * @param GroupCH5 This parameter can be a combination of the following values:
2923 * @arg @ref LL_TIM_GROUPCH5_NONE
2924 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2925 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2926 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2927 * @note CH5 channel is not available for all F3 devices
2928 * @retval None
2929 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2930 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2931 {
2932 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2933 }
2934
2935 #endif /* TIM_CCR5_CCR5 */
2936 /**
2937 * @}
2938 */
2939
2940 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2941 * @{
2942 */
2943 /**
2944 * @brief Configure input channel.
2945 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2946 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2947 * CCMR1 IC1F LL_TIM_IC_Config\n
2948 * CCMR1 CC2S LL_TIM_IC_Config\n
2949 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2950 * CCMR1 IC2F LL_TIM_IC_Config\n
2951 * CCMR2 CC3S LL_TIM_IC_Config\n
2952 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2953 * CCMR2 IC3F LL_TIM_IC_Config\n
2954 * CCMR2 CC4S LL_TIM_IC_Config\n
2955 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2956 * CCMR2 IC4F LL_TIM_IC_Config\n
2957 * CCER CC1P LL_TIM_IC_Config\n
2958 * CCER CC1NP LL_TIM_IC_Config\n
2959 * CCER CC2P LL_TIM_IC_Config\n
2960 * CCER CC2NP LL_TIM_IC_Config\n
2961 * CCER CC3P LL_TIM_IC_Config\n
2962 * CCER CC3NP LL_TIM_IC_Config\n
2963 * CCER CC4P LL_TIM_IC_Config\n
2964 * CCER CC4NP LL_TIM_IC_Config
2965 * @param TIMx Timer instance
2966 * @param Channel This parameter can be one of the following values:
2967 * @arg @ref LL_TIM_CHANNEL_CH1
2968 * @arg @ref LL_TIM_CHANNEL_CH2
2969 * @arg @ref LL_TIM_CHANNEL_CH3
2970 * @arg @ref LL_TIM_CHANNEL_CH4
2971 * @param Configuration This parameter must be a combination of all the following values:
2972 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2973 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2974 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2975 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2976 * @retval None
2977 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2978 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2979 {
2980 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2981 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2982 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2983 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2984 << SHIFT_TAB_ICxx[iChannel]);
2985 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2986 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2987 }
2988
2989 /**
2990 * @brief Set the active input.
2991 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2992 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2993 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2994 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2995 * @param TIMx Timer instance
2996 * @param Channel This parameter can be one of the following values:
2997 * @arg @ref LL_TIM_CHANNEL_CH1
2998 * @arg @ref LL_TIM_CHANNEL_CH2
2999 * @arg @ref LL_TIM_CHANNEL_CH3
3000 * @arg @ref LL_TIM_CHANNEL_CH4
3001 * @param ICActiveInput This parameter can be one of the following values:
3002 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3003 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3004 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3005 * @retval None
3006 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3007 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3008 {
3009 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3010 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3011 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3012 }
3013
3014 /**
3015 * @brief Get the current active input.
3016 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3017 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3018 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3019 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3020 * @param TIMx Timer instance
3021 * @param Channel This parameter can be one of the following values:
3022 * @arg @ref LL_TIM_CHANNEL_CH1
3023 * @arg @ref LL_TIM_CHANNEL_CH2
3024 * @arg @ref LL_TIM_CHANNEL_CH3
3025 * @arg @ref LL_TIM_CHANNEL_CH4
3026 * @retval Returned value can be one of the following values:
3027 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3028 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3029 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3030 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3031 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3032 {
3033 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3034 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3035 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3036 }
3037
3038 /**
3039 * @brief Set the prescaler of input channel.
3040 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3041 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3042 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3043 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3044 * @param TIMx Timer instance
3045 * @param Channel This parameter can be one of the following values:
3046 * @arg @ref LL_TIM_CHANNEL_CH1
3047 * @arg @ref LL_TIM_CHANNEL_CH2
3048 * @arg @ref LL_TIM_CHANNEL_CH3
3049 * @arg @ref LL_TIM_CHANNEL_CH4
3050 * @param ICPrescaler This parameter can be one of the following values:
3051 * @arg @ref LL_TIM_ICPSC_DIV1
3052 * @arg @ref LL_TIM_ICPSC_DIV2
3053 * @arg @ref LL_TIM_ICPSC_DIV4
3054 * @arg @ref LL_TIM_ICPSC_DIV8
3055 * @retval None
3056 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3057 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3058 {
3059 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3060 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3061 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3062 }
3063
3064 /**
3065 * @brief Get the current prescaler value acting on an input channel.
3066 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3067 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3068 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3069 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3070 * @param TIMx Timer instance
3071 * @param Channel This parameter can be one of the following values:
3072 * @arg @ref LL_TIM_CHANNEL_CH1
3073 * @arg @ref LL_TIM_CHANNEL_CH2
3074 * @arg @ref LL_TIM_CHANNEL_CH3
3075 * @arg @ref LL_TIM_CHANNEL_CH4
3076 * @retval Returned value can be one of the following values:
3077 * @arg @ref LL_TIM_ICPSC_DIV1
3078 * @arg @ref LL_TIM_ICPSC_DIV2
3079 * @arg @ref LL_TIM_ICPSC_DIV4
3080 * @arg @ref LL_TIM_ICPSC_DIV8
3081 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3082 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3083 {
3084 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3085 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3086 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3087 }
3088
3089 /**
3090 * @brief Set the input filter duration.
3091 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3092 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3093 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3094 * CCMR2 IC4F LL_TIM_IC_SetFilter
3095 * @param TIMx Timer instance
3096 * @param Channel This parameter can be one of the following values:
3097 * @arg @ref LL_TIM_CHANNEL_CH1
3098 * @arg @ref LL_TIM_CHANNEL_CH2
3099 * @arg @ref LL_TIM_CHANNEL_CH3
3100 * @arg @ref LL_TIM_CHANNEL_CH4
3101 * @param ICFilter This parameter can be one of the following values:
3102 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3103 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3104 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3105 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3106 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3107 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3108 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3109 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3110 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3111 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3112 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3113 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3114 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3115 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3116 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3117 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3118 * @retval None
3119 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3120 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3121 {
3122 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3123 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3124 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3125 }
3126
3127 /**
3128 * @brief Get the input filter duration.
3129 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3130 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3131 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3132 * CCMR2 IC4F LL_TIM_IC_GetFilter
3133 * @param TIMx Timer instance
3134 * @param Channel This parameter can be one of the following values:
3135 * @arg @ref LL_TIM_CHANNEL_CH1
3136 * @arg @ref LL_TIM_CHANNEL_CH2
3137 * @arg @ref LL_TIM_CHANNEL_CH3
3138 * @arg @ref LL_TIM_CHANNEL_CH4
3139 * @retval Returned value can be one of the following values:
3140 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3141 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3142 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3143 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3144 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3145 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3146 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3147 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3148 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3149 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3150 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3151 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3152 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3153 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3154 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3155 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3156 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3157 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3158 {
3159 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3160 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3161 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3162 }
3163
3164 /**
3165 * @brief Set the input channel polarity.
3166 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3167 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3168 * CCER CC2P LL_TIM_IC_SetPolarity\n
3169 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3170 * CCER CC3P LL_TIM_IC_SetPolarity\n
3171 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3172 * CCER CC4P LL_TIM_IC_SetPolarity\n
3173 * CCER CC4NP LL_TIM_IC_SetPolarity
3174 * @param TIMx Timer instance
3175 * @param Channel This parameter can be one of the following values:
3176 * @arg @ref LL_TIM_CHANNEL_CH1
3177 * @arg @ref LL_TIM_CHANNEL_CH2
3178 * @arg @ref LL_TIM_CHANNEL_CH3
3179 * @arg @ref LL_TIM_CHANNEL_CH4
3180 * @param ICPolarity This parameter can be one of the following values:
3181 * @arg @ref LL_TIM_IC_POLARITY_RISING
3182 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3183 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3184 * @retval None
3185 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3186 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3187 {
3188 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3189 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3190 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3191 }
3192
3193 /**
3194 * @brief Get the current input channel polarity.
3195 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3196 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3197 * CCER CC2P LL_TIM_IC_GetPolarity\n
3198 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3199 * CCER CC3P LL_TIM_IC_GetPolarity\n
3200 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3201 * CCER CC4P LL_TIM_IC_GetPolarity\n
3202 * CCER CC4NP LL_TIM_IC_GetPolarity
3203 * @param TIMx Timer instance
3204 * @param Channel This parameter can be one of the following values:
3205 * @arg @ref LL_TIM_CHANNEL_CH1
3206 * @arg @ref LL_TIM_CHANNEL_CH2
3207 * @arg @ref LL_TIM_CHANNEL_CH3
3208 * @arg @ref LL_TIM_CHANNEL_CH4
3209 * @retval Returned value can be one of the following values:
3210 * @arg @ref LL_TIM_IC_POLARITY_RISING
3211 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3212 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3213 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3214 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3215 {
3216 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3217 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3218 SHIFT_TAB_CCxP[iChannel]);
3219 }
3220
3221 /**
3222 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3223 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3224 * a timer instance provides an XOR input.
3225 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3226 * @param TIMx Timer instance
3227 * @retval None
3228 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3229 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3230 {
3231 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3232 }
3233
3234 /**
3235 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3236 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3237 * a timer instance provides an XOR input.
3238 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3239 * @param TIMx Timer instance
3240 * @retval None
3241 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3242 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3243 {
3244 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3245 }
3246
3247 /**
3248 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3249 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3250 * a timer instance provides an XOR input.
3251 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3252 * @param TIMx Timer instance
3253 * @retval State of bit (1 or 0).
3254 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3255 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3256 {
3257 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3258 }
3259
3260 /**
3261 * @brief Get captured value for input channel 1.
3262 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3263 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3264 * whether or not a timer instance supports a 32 bits counter.
3265 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3266 * input channel 1 is supported by a timer instance.
3267 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3268 * @param TIMx Timer instance
3269 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3270 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3271 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3272 {
3273 return (uint32_t)(READ_REG(TIMx->CCR1));
3274 }
3275
3276 /**
3277 * @brief Get captured value for input channel 2.
3278 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3279 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3280 * whether or not a timer instance supports a 32 bits counter.
3281 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3282 * input channel 2 is supported by a timer instance.
3283 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3284 * @param TIMx Timer instance
3285 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3286 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3287 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3288 {
3289 return (uint32_t)(READ_REG(TIMx->CCR2));
3290 }
3291
3292 /**
3293 * @brief Get captured value for input channel 3.
3294 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3295 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3296 * whether or not a timer instance supports a 32 bits counter.
3297 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3298 * input channel 3 is supported by a timer instance.
3299 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3300 * @param TIMx Timer instance
3301 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3302 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3303 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3304 {
3305 return (uint32_t)(READ_REG(TIMx->CCR3));
3306 }
3307
3308 /**
3309 * @brief Get captured value for input channel 4.
3310 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3311 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3312 * whether or not a timer instance supports a 32 bits counter.
3313 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3314 * input channel 4 is supported by a timer instance.
3315 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3316 * @param TIMx Timer instance
3317 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3318 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3319 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3320 {
3321 return (uint32_t)(READ_REG(TIMx->CCR4));
3322 }
3323
3324 /**
3325 * @}
3326 */
3327
3328 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3329 * @{
3330 */
3331 /**
3332 * @brief Enable external clock mode 2.
3333 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3334 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3335 * whether or not a timer instance supports external clock mode2.
3336 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3337 * @param TIMx Timer instance
3338 * @retval None
3339 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3340 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3341 {
3342 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3343 }
3344
3345 /**
3346 * @brief Disable external clock mode 2.
3347 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3348 * whether or not a timer instance supports external clock mode2.
3349 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3350 * @param TIMx Timer instance
3351 * @retval None
3352 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3353 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3354 {
3355 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3356 }
3357
3358 /**
3359 * @brief Indicate whether external clock mode 2 is enabled.
3360 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3361 * whether or not a timer instance supports external clock mode2.
3362 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3363 * @param TIMx Timer instance
3364 * @retval State of bit (1 or 0).
3365 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3366 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3367 {
3368 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3369 }
3370
3371 /**
3372 * @brief Set the clock source of the counter clock.
3373 * @note when selected clock source is external clock mode 1, the timer input
3374 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3375 * function. This timer input must be configured by calling
3376 * the @ref LL_TIM_IC_Config() function.
3377 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3378 * whether or not a timer instance supports external clock mode1.
3379 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3380 * whether or not a timer instance supports external clock mode2.
3381 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3382 * SMCR ECE LL_TIM_SetClockSource
3383 * @param TIMx Timer instance
3384 * @param ClockSource This parameter can be one of the following values:
3385 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3386 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3387 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3388 * @retval None
3389 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3390 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3391 {
3392 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3393 }
3394
3395 /**
3396 * @brief Set the encoder interface mode.
3397 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3398 * whether or not a timer instance supports the encoder mode.
3399 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3400 * @param TIMx Timer instance
3401 * @param EncoderMode This parameter can be one of the following values:
3402 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3403 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3404 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3405 * @retval None
3406 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3407 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3408 {
3409 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3410 }
3411
3412 /**
3413 * @}
3414 */
3415
3416 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3417 * @{
3418 */
3419 /**
3420 * @brief Set the trigger output (TRGO) used for timer synchronization .
3421 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3422 * whether or not a timer instance can operate as a master timer.
3423 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3424 * @param TIMx Timer instance
3425 * @param TimerSynchronization This parameter can be one of the following values:
3426 * @arg @ref LL_TIM_TRGO_RESET
3427 * @arg @ref LL_TIM_TRGO_ENABLE
3428 * @arg @ref LL_TIM_TRGO_UPDATE
3429 * @arg @ref LL_TIM_TRGO_CC1IF
3430 * @arg @ref LL_TIM_TRGO_OC1REF
3431 * @arg @ref LL_TIM_TRGO_OC2REF
3432 * @arg @ref LL_TIM_TRGO_OC3REF
3433 * @arg @ref LL_TIM_TRGO_OC4REF
3434 * @retval None
3435 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3436 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3437 {
3438 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3439 }
3440
3441 #if defined(TIM_CR2_MMS2)
3442 /**
3443 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3444 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3445 * whether or not a timer instance can be used for ADC synchronization.
3446 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3447 * @param TIMx Timer Instance
3448 * @param ADCSynchronization This parameter can be one of the following values:
3449 * @arg @ref LL_TIM_TRGO2_RESET
3450 * @arg @ref LL_TIM_TRGO2_ENABLE
3451 * @arg @ref LL_TIM_TRGO2_UPDATE
3452 * @arg @ref LL_TIM_TRGO2_CC1F
3453 * @arg @ref LL_TIM_TRGO2_OC1
3454 * @arg @ref LL_TIM_TRGO2_OC2
3455 * @arg @ref LL_TIM_TRGO2_OC3
3456 * @arg @ref LL_TIM_TRGO2_OC4
3457 * @arg @ref LL_TIM_TRGO2_OC5
3458 * @arg @ref LL_TIM_TRGO2_OC6
3459 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3460 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3461 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3462 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3463 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3464 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3465 * @note OC5 and OC6 are not available for all F3 devices
3466 * @retval None
3467 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3468 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3469 {
3470 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3471 }
3472
3473 #endif /* TIM_CR2_MMS2 */
3474 /**
3475 * @brief Set the synchronization mode of a slave timer.
3476 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3477 * a timer instance can operate as a slave timer.
3478 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3479 * @param TIMx Timer instance
3480 * @param SlaveMode This parameter can be one of the following values:
3481 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3482 * @arg @ref LL_TIM_SLAVEMODE_RESET
3483 * @arg @ref LL_TIM_SLAVEMODE_GATED
3484 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3485 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3486 * @retval None
3487 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3488 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3489 {
3490 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3491 }
3492
3493 /**
3494 * @brief Set the selects the trigger input to be used to synchronize the counter.
3495 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3496 * a timer instance can operate as a slave timer.
3497 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3498 * @param TIMx Timer instance
3499 * @param TriggerInput This parameter can be one of the following values:
3500 * @arg @ref LL_TIM_TS_ITR0
3501 * @arg @ref LL_TIM_TS_ITR1
3502 * @arg @ref LL_TIM_TS_ITR2
3503 * @arg @ref LL_TIM_TS_ITR3
3504 * @arg @ref LL_TIM_TS_TI1F_ED
3505 * @arg @ref LL_TIM_TS_TI1FP1
3506 * @arg @ref LL_TIM_TS_TI2FP2
3507 * @arg @ref LL_TIM_TS_ETRF
3508 * @retval None
3509 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3510 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3511 {
3512 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3513 }
3514
3515 /**
3516 * @brief Enable the Master/Slave mode.
3517 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3518 * a timer instance can operate as a slave timer.
3519 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3520 * @param TIMx Timer instance
3521 * @retval None
3522 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3523 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3524 {
3525 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3526 }
3527
3528 /**
3529 * @brief Disable the Master/Slave mode.
3530 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3531 * a timer instance can operate as a slave timer.
3532 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3533 * @param TIMx Timer instance
3534 * @retval None
3535 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3536 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3537 {
3538 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3539 }
3540
3541 /**
3542 * @brief Indicates whether the Master/Slave mode is enabled.
3543 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3544 * a timer instance can operate as a slave timer.
3545 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3546 * @param TIMx Timer instance
3547 * @retval State of bit (1 or 0).
3548 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3549 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3550 {
3551 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3552 }
3553
3554 /**
3555 * @brief Configure the external trigger (ETR) input.
3556 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3557 * a timer instance provides an external trigger input.
3558 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3559 * SMCR ETPS LL_TIM_ConfigETR\n
3560 * SMCR ETF LL_TIM_ConfigETR
3561 * @param TIMx Timer instance
3562 * @param ETRPolarity This parameter can be one of the following values:
3563 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3564 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3565 * @param ETRPrescaler This parameter can be one of the following values:
3566 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3567 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3568 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3569 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3570 * @param ETRFilter This parameter can be one of the following values:
3571 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3572 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3573 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3574 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3575 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3576 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3577 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3578 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3579 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3580 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3581 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3582 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3583 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3584 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3585 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3586 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3587 * @retval None
3588 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3589 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3590 uint32_t ETRFilter)
3591 {
3592 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3593 }
3594
3595 /**
3596 * @}
3597 */
3598
3599 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3600 * @{
3601 */
3602 /**
3603 * @brief Enable the break function.
3604 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3605 * a timer instance provides a break input.
3606 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3607 * @param TIMx Timer instance
3608 * @retval None
3609 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3610 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3611 {
3612 #if defined(TIM_IP_V2_1)
3613 __IO uint32_t tmpreg;
3614 #endif /* TIM_IP_V2_1 */
3615 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3616 #if defined(TIM_IP_V2_1)
3617 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3618 tmpreg = READ_REG(TIMx->BDTR);
3619 (void)(tmpreg);
3620 #endif /* TIM_IP_V2_1 */
3621 }
3622
3623 /**
3624 * @brief Disable the break function.
3625 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3626 * @param TIMx Timer instance
3627 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3628 * a timer instance provides a break input.
3629 * @retval None
3630 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3631 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3632 {
3633 #if defined(TIM_IP_V2_1)
3634 __IO uint32_t tmpreg;
3635 #endif /* TIM_IP_V2_1 */
3636 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3637 #if defined(TIM_IP_V2_1)
3638 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3639 tmpreg = READ_REG(TIMx->BDTR);
3640 (void)(tmpreg);
3641 #endif /* TIM_IP_V2_1 */
3642 }
3643
3644 #if defined(TIM_BDTR_BKF)
3645 /**
3646 * @brief Configure the break input.
3647 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3648 * a timer instance provides a break input.
3649 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3650 * BDTR BKF LL_TIM_ConfigBRK
3651 * @param TIMx Timer instance
3652 * @param BreakPolarity This parameter can be one of the following values:
3653 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3654 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3655 * @param BreakFilter This parameter can be one of the following values:
3656 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3657 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3658 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3659 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3660 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3661 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3662 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3663 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3664 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3665 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3666 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3667 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3668 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3669 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3670 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3671 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3672 * @retval None
3673 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3674 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3675 uint32_t BreakFilter)
3676 {
3677 #if defined(TIM_IP_V2_1)
3678 __IO uint32_t tmpreg;
3679 #endif /* TIM_IP_V2_1 */
3680 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3681 #if defined(TIM_IP_V2_1)
3682 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
3683 tmpreg = READ_REG(TIMx->BDTR);
3684 (void)(tmpreg);
3685 #endif /* TIM_IP_V2_1 */
3686 }
3687
3688 #else
3689 /**
3690 * @brief Configure the break input.
3691 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3692 * a timer instance provides a break input.
3693 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
3694 * @param TIMx Timer instance
3695 * @param BreakPolarity This parameter can be one of the following values:
3696 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3697 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3698 * @retval None
3699 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)3700 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
3701 {
3702 #if defined(TIM_IP_V2_1)
3703 __IO uint32_t tmpreg;
3704 #endif /* TIM_IP_V2_1 */
3705 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
3706 #if defined(TIM_IP_V2_1)
3707 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
3708 tmpreg = READ_REG(TIMx->BDTR);
3709 (void)(tmpreg);
3710 #endif /* TIM_IP_V2_1 */
3711 }
3712
3713 #endif /* TIM_BDTR_BKF */
3714 #if defined(TIM_BDTR_BK2E)
3715 /**
3716 * @brief Enable the break 2 function.
3717 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3718 * a timer instance provides a second break input.
3719 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3720 * @param TIMx Timer instance
3721 * @retval None
3722 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3723 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3724 {
3725 #if defined(TIM_IP_V2_1)
3726 __IO uint32_t tmpreg;
3727 #endif /* TIM_IP_V2_1 */
3728 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3729 #if defined(TIM_IP_V2_1)
3730 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3731 tmpreg = READ_REG(TIMx->BDTR);
3732 (void)(tmpreg);
3733 #endif /* TIM_IP_V2_1 */
3734 }
3735
3736 /**
3737 * @brief Disable the break 2 function.
3738 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3739 * a timer instance provides a second break input.
3740 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3741 * @param TIMx Timer instance
3742 * @retval None
3743 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3744 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3745 {
3746 #if defined(TIM_IP_V2_1)
3747 __IO uint32_t tmpreg;
3748 #endif /* TIM_IP_V2_1 */
3749 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3750 #if defined(TIM_IP_V2_1)
3751 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3752 tmpreg = READ_REG(TIMx->BDTR);
3753 (void)(tmpreg);
3754 #endif /* TIM_IP_V2_1 */
3755 }
3756
3757 /**
3758 * @brief Configure the break 2 input.
3759 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3760 * a timer instance provides a second break input.
3761 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3762 * BDTR BK2F LL_TIM_ConfigBRK2
3763 * @param TIMx Timer instance
3764 * @param Break2Polarity This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3766 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3767 * @param Break2Filter This parameter can be one of the following values:
3768 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3769 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3770 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3771 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3772 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3773 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3774 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3775 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3776 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3777 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3778 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3779 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3780 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3781 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3782 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3783 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3784 * @retval None
3785 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3786 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3787 {
3788 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3789 }
3790
3791 #endif /* TIM_BDTR_BK2E */
3792 /**
3793 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3794 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3795 * a timer instance provides a break input.
3796 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3797 * BDTR OSSR LL_TIM_SetOffStates
3798 * @param TIMx Timer instance
3799 * @param OffStateIdle This parameter can be one of the following values:
3800 * @arg @ref LL_TIM_OSSI_DISABLE
3801 * @arg @ref LL_TIM_OSSI_ENABLE
3802 * @param OffStateRun This parameter can be one of the following values:
3803 * @arg @ref LL_TIM_OSSR_DISABLE
3804 * @arg @ref LL_TIM_OSSR_ENABLE
3805 * @retval None
3806 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3807 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3808 {
3809 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3810 }
3811
3812 /**
3813 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3814 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3815 * a timer instance provides a break input.
3816 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3817 * @param TIMx Timer instance
3818 * @retval None
3819 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3820 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3821 {
3822 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3823 }
3824
3825 /**
3826 * @brief Disable automatic output (MOE can be set only by software).
3827 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3828 * a timer instance provides a break input.
3829 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3830 * @param TIMx Timer instance
3831 * @retval None
3832 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3833 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3834 {
3835 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3836 }
3837
3838 /**
3839 * @brief Indicate whether automatic output is enabled.
3840 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3841 * a timer instance provides a break input.
3842 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3843 * @param TIMx Timer instance
3844 * @retval State of bit (1 or 0).
3845 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3846 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3847 {
3848 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3849 }
3850
3851 /**
3852 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3853 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3854 * software and is reset in case of break or break2 event
3855 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3856 * a timer instance provides a break input.
3857 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3858 * @param TIMx Timer instance
3859 * @retval None
3860 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3861 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3862 {
3863 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3864 }
3865
3866 /**
3867 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3868 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3869 * software and is reset in case of break or break2 event.
3870 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3871 * a timer instance provides a break input.
3872 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3873 * @param TIMx Timer instance
3874 * @retval None
3875 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3876 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3877 {
3878 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3879 }
3880
3881 /**
3882 * @brief Indicates whether outputs are enabled.
3883 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3884 * a timer instance provides a break input.
3885 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3886 * @param TIMx Timer instance
3887 * @retval State of bit (1 or 0).
3888 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3889 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3890 {
3891 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3892 }
3893
3894 /**
3895 * @}
3896 */
3897
3898 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3899 * @{
3900 */
3901 /**
3902 * @brief Configures the timer DMA burst feature.
3903 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3904 * not a timer instance supports the DMA burst mode.
3905 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3906 * DCR DBA LL_TIM_ConfigDMABurst
3907 * @param TIMx Timer instance
3908 * @param DMABurstBaseAddress This parameter can be one of the following values:
3909 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3910 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3911 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3912 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3913 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3914 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3915 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3916 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3917 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3918 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3919 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3920 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3921 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3922 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3923 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3924 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3925 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3926 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3927 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3928 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
3929 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
3930 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
3931 * (*) value not defined in all devices
3932 * @param DMABurstLength This parameter can be one of the following values:
3933 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3934 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3935 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3936 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3937 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3938 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3939 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3940 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3941 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3942 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3943 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3944 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3945 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3946 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3947 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3948 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3949 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3950 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3951 * @retval None
3952 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3953 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3954 {
3955 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3956 }
3957
3958 /**
3959 * @}
3960 */
3961
3962 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3963 * @{
3964 */
3965 /**
3966 * @brief Remap TIM inputs (input channel, internal/external triggers).
3967 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3968 * a some timer inputs can be remapped.
3969 * @if STM32F334x8
3970 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3971 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3972 * @elseif STM32F302x8
3973 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3974 * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
3975 * @elseif STM32F303xC
3976 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
3977 * TIM8_OR ETR_RMP LL_TIM_SetRemap\n
3978 * TIM20_OR ETR_RMP LL_TIM_SetRemap\n
3979 * @elseif STM32F373xC
3980 * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
3981 * @endif
3982 * @param TIMx Timer instance
3983 * @param Remap Remap params depends on the TIMx. Description available only
3984 * in CHM version of the User Manual (not in .pdf).
3985 * Otherwise see Reference Manual description of OR registers.
3986 *
3987 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3988 *
3989 * TIM1: any combination of ETR_RMP where (**)
3990 *
3991 * . . ETR_RMP can be one of the following values
3992 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3993 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
3994 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
3995 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
3996 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
3997 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
3998 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
3999 * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
4000 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
4001 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
4002 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
4003 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
4004 *
4005 * TIM8: any combination of ETR_RMP where (**)
4006 *
4007 * . . ETR_RMP can be one of the following values
4008 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
4009 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
4010 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
4011 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
4012 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
4013 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
4014 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
4015 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
4016 *
4017 * TIM14: any combination of TI1_RMP where (**)
4018 *
4019 * . . TI1_RMP can be one of the following values
4020 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
4021 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
4022 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
4023 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
4024 *
4025 * TIM16: any combination of TI1_RMP where (**)
4026 *
4027 * . . TI1_RMP can be one of the following values
4028 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
4029 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
4030 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
4031 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
4032 *
4033 * TIM20: any combination of ETR_RMP where (**)
4034 *
4035 * . . ETR_RMP can be one of the following values
4036 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
4037 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
4038 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
4039 * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
4040 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
4041 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
4042 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
4043 * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
4044 *
4045 * (*) Value not defined in all devices. \n
4046 * (**) Register not available in all devices.
4047 * @retval None
4048 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4049 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4050 {
4051 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
4052 }
4053
4054 /**
4055 * @}
4056 */
4057 #if defined(TIM_SMCR_OCCS)
4058
4059 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4060 * @{
4061 */
4062 /**
4063 * @brief Set the OCREF clear input source
4064 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4065 * @note This function can only be used in Output compare and PWM modes.
4066 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4067 * @param TIMx Timer instance
4068 * @param OCRefClearInputSource This parameter can be one of the following values:
4069 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
4070 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4071 * @retval None
4072 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4073 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4074 {
4075 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4076 }
4077 /**
4078 * @}
4079 */
4080 #endif /* TIM_SMCR_OCCS */
4081
4082 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4083 * @{
4084 */
4085 /**
4086 * @brief Clear the update interrupt flag (UIF).
4087 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4088 * @param TIMx Timer instance
4089 * @retval None
4090 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4091 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4092 {
4093 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4094 }
4095
4096 /**
4097 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4098 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4099 * @param TIMx Timer instance
4100 * @retval State of bit (1 or 0).
4101 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4102 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4103 {
4104 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4105 }
4106
4107 /**
4108 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4109 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4110 * @param TIMx Timer instance
4111 * @retval None
4112 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4113 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4114 {
4115 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4116 }
4117
4118 /**
4119 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4120 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4121 * @param TIMx Timer instance
4122 * @retval State of bit (1 or 0).
4123 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4124 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4125 {
4126 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4127 }
4128
4129 /**
4130 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4131 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4132 * @param TIMx Timer instance
4133 * @retval None
4134 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4135 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4136 {
4137 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4138 }
4139
4140 /**
4141 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4142 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4143 * @param TIMx Timer instance
4144 * @retval State of bit (1 or 0).
4145 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4146 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4147 {
4148 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4149 }
4150
4151 /**
4152 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4153 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4154 * @param TIMx Timer instance
4155 * @retval None
4156 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4157 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4158 {
4159 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4160 }
4161
4162 /**
4163 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4164 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4165 * @param TIMx Timer instance
4166 * @retval State of bit (1 or 0).
4167 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4168 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4169 {
4170 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4171 }
4172
4173 /**
4174 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4175 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4176 * @param TIMx Timer instance
4177 * @retval None
4178 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4179 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4180 {
4181 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4182 }
4183
4184 /**
4185 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4186 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4187 * @param TIMx Timer instance
4188 * @retval State of bit (1 or 0).
4189 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4190 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4191 {
4192 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4193 }
4194
4195 #if defined (TIM_SR_CC5IF)
4196 /**
4197 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4198 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4199 * @param TIMx Timer instance
4200 * @retval None
4201 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4202 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4203 {
4204 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4205 }
4206
4207 /**
4208 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4209 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4210 * @param TIMx Timer instance
4211 * @retval State of bit (1 or 0).
4212 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4213 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4214 {
4215 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4216 }
4217
4218 #endif /* TIM_SR_CC5IF */
4219 #if defined (TIM_SR_CC6IF)
4220 /**
4221 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4222 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4223 * @param TIMx Timer instance
4224 * @retval None
4225 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4226 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4227 {
4228 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4229 }
4230
4231 /**
4232 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4233 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4234 * @param TIMx Timer instance
4235 * @retval State of bit (1 or 0).
4236 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4238 {
4239 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4240 }
4241
4242 #endif /* TIM_SR_CC6IF */
4243 /**
4244 * @brief Clear the commutation interrupt flag (COMIF).
4245 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4246 * @param TIMx Timer instance
4247 * @retval None
4248 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4249 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4250 {
4251 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4252 }
4253
4254 /**
4255 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4256 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4257 * @param TIMx Timer instance
4258 * @retval State of bit (1 or 0).
4259 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4260 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4261 {
4262 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4263 }
4264
4265 /**
4266 * @brief Clear the trigger interrupt flag (TIF).
4267 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4268 * @param TIMx Timer instance
4269 * @retval None
4270 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4271 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4272 {
4273 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4274 }
4275
4276 /**
4277 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4278 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4279 * @param TIMx Timer instance
4280 * @retval State of bit (1 or 0).
4281 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4282 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4283 {
4284 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4285 }
4286
4287 /**
4288 * @brief Clear the break interrupt flag (BIF).
4289 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4290 * @param TIMx Timer instance
4291 * @retval None
4292 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4293 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4294 {
4295 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4296 }
4297
4298 /**
4299 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4300 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4301 * @param TIMx Timer instance
4302 * @retval State of bit (1 or 0).
4303 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4304 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4305 {
4306 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4307 }
4308
4309 #if defined(TIM_SR_B2IF)
4310 /**
4311 * @brief Clear the break 2 interrupt flag (B2IF).
4312 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4313 * @param TIMx Timer instance
4314 * @retval None
4315 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4316 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4317 {
4318 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4319 }
4320
4321 /**
4322 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4323 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4324 * @param TIMx Timer instance
4325 * @retval State of bit (1 or 0).
4326 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4327 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4328 {
4329 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4330 }
4331
4332 #endif /* TIM_SR_B2IF */
4333 /**
4334 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4335 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4336 * @param TIMx Timer instance
4337 * @retval None
4338 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4339 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4340 {
4341 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4342 }
4343
4344 /**
4345 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4346 * (Capture/Compare 1 interrupt is pending).
4347 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4348 * @param TIMx Timer instance
4349 * @retval State of bit (1 or 0).
4350 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4351 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4352 {
4353 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4354 }
4355
4356 /**
4357 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4358 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4359 * @param TIMx Timer instance
4360 * @retval None
4361 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4362 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4363 {
4364 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4365 }
4366
4367 /**
4368 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4369 * (Capture/Compare 2 over-capture interrupt is pending).
4370 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4371 * @param TIMx Timer instance
4372 * @retval State of bit (1 or 0).
4373 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4374 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4375 {
4376 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4377 }
4378
4379 /**
4380 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4381 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4382 * @param TIMx Timer instance
4383 * @retval None
4384 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4385 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4386 {
4387 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4388 }
4389
4390 /**
4391 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4392 * (Capture/Compare 3 over-capture interrupt is pending).
4393 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4394 * @param TIMx Timer instance
4395 * @retval State of bit (1 or 0).
4396 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4397 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4398 {
4399 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4400 }
4401
4402 /**
4403 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4404 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4405 * @param TIMx Timer instance
4406 * @retval None
4407 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4408 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4409 {
4410 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4411 }
4412
4413 /**
4414 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4415 * (Capture/Compare 4 over-capture interrupt is pending).
4416 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4417 * @param TIMx Timer instance
4418 * @retval State of bit (1 or 0).
4419 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4420 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4421 {
4422 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4423 }
4424
4425 /**
4426 * @}
4427 */
4428
4429 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4430 * @{
4431 */
4432 /**
4433 * @brief Enable update interrupt (UIE).
4434 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4435 * @param TIMx Timer instance
4436 * @retval None
4437 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4438 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4439 {
4440 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4441 }
4442
4443 /**
4444 * @brief Disable update interrupt (UIE).
4445 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4446 * @param TIMx Timer instance
4447 * @retval None
4448 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4449 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4450 {
4451 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4452 }
4453
4454 /**
4455 * @brief Indicates whether the update interrupt (UIE) is enabled.
4456 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4457 * @param TIMx Timer instance
4458 * @retval State of bit (1 or 0).
4459 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4460 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4461 {
4462 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4463 }
4464
4465 /**
4466 * @brief Enable capture/compare 1 interrupt (CC1IE).
4467 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4468 * @param TIMx Timer instance
4469 * @retval None
4470 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4471 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4472 {
4473 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4474 }
4475
4476 /**
4477 * @brief Disable capture/compare 1 interrupt (CC1IE).
4478 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4479 * @param TIMx Timer instance
4480 * @retval None
4481 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4482 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4483 {
4484 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4485 }
4486
4487 /**
4488 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4489 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4490 * @param TIMx Timer instance
4491 * @retval State of bit (1 or 0).
4492 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4493 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4494 {
4495 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4496 }
4497
4498 /**
4499 * @brief Enable capture/compare 2 interrupt (CC2IE).
4500 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4501 * @param TIMx Timer instance
4502 * @retval None
4503 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4504 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4505 {
4506 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4507 }
4508
4509 /**
4510 * @brief Disable capture/compare 2 interrupt (CC2IE).
4511 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4512 * @param TIMx Timer instance
4513 * @retval None
4514 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4515 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4516 {
4517 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4518 }
4519
4520 /**
4521 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4522 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4523 * @param TIMx Timer instance
4524 * @retval State of bit (1 or 0).
4525 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4526 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4527 {
4528 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4529 }
4530
4531 /**
4532 * @brief Enable capture/compare 3 interrupt (CC3IE).
4533 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4534 * @param TIMx Timer instance
4535 * @retval None
4536 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4537 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4538 {
4539 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4540 }
4541
4542 /**
4543 * @brief Disable capture/compare 3 interrupt (CC3IE).
4544 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4545 * @param TIMx Timer instance
4546 * @retval None
4547 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4548 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4549 {
4550 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4551 }
4552
4553 /**
4554 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4555 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4556 * @param TIMx Timer instance
4557 * @retval State of bit (1 or 0).
4558 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4559 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4560 {
4561 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4562 }
4563
4564 /**
4565 * @brief Enable capture/compare 4 interrupt (CC4IE).
4566 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4567 * @param TIMx Timer instance
4568 * @retval None
4569 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4570 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4571 {
4572 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4573 }
4574
4575 /**
4576 * @brief Disable capture/compare 4 interrupt (CC4IE).
4577 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4578 * @param TIMx Timer instance
4579 * @retval None
4580 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4581 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4582 {
4583 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4584 }
4585
4586 /**
4587 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4588 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4589 * @param TIMx Timer instance
4590 * @retval State of bit (1 or 0).
4591 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4592 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4593 {
4594 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4595 }
4596
4597 /**
4598 * @brief Enable commutation interrupt (COMIE).
4599 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4600 * @param TIMx Timer instance
4601 * @retval None
4602 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4603 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4604 {
4605 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4606 }
4607
4608 /**
4609 * @brief Disable commutation interrupt (COMIE).
4610 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4611 * @param TIMx Timer instance
4612 * @retval None
4613 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4614 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4615 {
4616 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4617 }
4618
4619 /**
4620 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4621 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4622 * @param TIMx Timer instance
4623 * @retval State of bit (1 or 0).
4624 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4625 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4626 {
4627 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4628 }
4629
4630 /**
4631 * @brief Enable trigger interrupt (TIE).
4632 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4633 * @param TIMx Timer instance
4634 * @retval None
4635 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4636 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4637 {
4638 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4639 }
4640
4641 /**
4642 * @brief Disable trigger interrupt (TIE).
4643 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4644 * @param TIMx Timer instance
4645 * @retval None
4646 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4647 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4648 {
4649 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4650 }
4651
4652 /**
4653 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4654 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4655 * @param TIMx Timer instance
4656 * @retval State of bit (1 or 0).
4657 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4659 {
4660 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4661 }
4662
4663 /**
4664 * @brief Enable break interrupt (BIE).
4665 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4666 * @param TIMx Timer instance
4667 * @retval None
4668 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4669 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4670 {
4671 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4672 }
4673
4674 /**
4675 * @brief Disable break interrupt (BIE).
4676 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4677 * @param TIMx Timer instance
4678 * @retval None
4679 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4680 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4681 {
4682 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4683 }
4684
4685 /**
4686 * @brief Indicates whether the break interrupt (BIE) is enabled.
4687 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4688 * @param TIMx Timer instance
4689 * @retval State of bit (1 or 0).
4690 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4692 {
4693 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4694 }
4695
4696 /**
4697 * @}
4698 */
4699
4700 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4701 * @{
4702 */
4703 /**
4704 * @brief Enable update DMA request (UDE).
4705 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4706 * @param TIMx Timer instance
4707 * @retval None
4708 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4709 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4710 {
4711 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4712 }
4713
4714 /**
4715 * @brief Disable update DMA request (UDE).
4716 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4717 * @param TIMx Timer instance
4718 * @retval None
4719 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4720 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4721 {
4722 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4723 }
4724
4725 /**
4726 * @brief Indicates whether the update DMA request (UDE) is enabled.
4727 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4728 * @param TIMx Timer instance
4729 * @retval State of bit (1 or 0).
4730 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4731 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4732 {
4733 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4734 }
4735
4736 /**
4737 * @brief Enable capture/compare 1 DMA request (CC1DE).
4738 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4739 * @param TIMx Timer instance
4740 * @retval None
4741 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4742 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4743 {
4744 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4745 }
4746
4747 /**
4748 * @brief Disable capture/compare 1 DMA request (CC1DE).
4749 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4750 * @param TIMx Timer instance
4751 * @retval None
4752 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4753 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4754 {
4755 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4756 }
4757
4758 /**
4759 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4760 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4761 * @param TIMx Timer instance
4762 * @retval State of bit (1 or 0).
4763 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4764 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4765 {
4766 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4767 }
4768
4769 /**
4770 * @brief Enable capture/compare 2 DMA request (CC2DE).
4771 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4772 * @param TIMx Timer instance
4773 * @retval None
4774 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4775 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4776 {
4777 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4778 }
4779
4780 /**
4781 * @brief Disable capture/compare 2 DMA request (CC2DE).
4782 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4783 * @param TIMx Timer instance
4784 * @retval None
4785 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4786 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4787 {
4788 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4789 }
4790
4791 /**
4792 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4793 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4794 * @param TIMx Timer instance
4795 * @retval State of bit (1 or 0).
4796 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4797 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4798 {
4799 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4800 }
4801
4802 /**
4803 * @brief Enable capture/compare 3 DMA request (CC3DE).
4804 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4805 * @param TIMx Timer instance
4806 * @retval None
4807 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4808 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4809 {
4810 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4811 }
4812
4813 /**
4814 * @brief Disable capture/compare 3 DMA request (CC3DE).
4815 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4816 * @param TIMx Timer instance
4817 * @retval None
4818 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4819 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4820 {
4821 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4822 }
4823
4824 /**
4825 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4826 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4827 * @param TIMx Timer instance
4828 * @retval State of bit (1 or 0).
4829 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4830 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4831 {
4832 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4833 }
4834
4835 /**
4836 * @brief Enable capture/compare 4 DMA request (CC4DE).
4837 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4838 * @param TIMx Timer instance
4839 * @retval None
4840 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4841 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4842 {
4843 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4844 }
4845
4846 /**
4847 * @brief Disable capture/compare 4 DMA request (CC4DE).
4848 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4849 * @param TIMx Timer instance
4850 * @retval None
4851 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4852 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4853 {
4854 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4855 }
4856
4857 /**
4858 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4859 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4860 * @param TIMx Timer instance
4861 * @retval State of bit (1 or 0).
4862 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4863 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4864 {
4865 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4866 }
4867
4868 /**
4869 * @brief Enable commutation DMA request (COMDE).
4870 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4871 * @param TIMx Timer instance
4872 * @retval None
4873 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4874 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4875 {
4876 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4877 }
4878
4879 /**
4880 * @brief Disable commutation DMA request (COMDE).
4881 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4882 * @param TIMx Timer instance
4883 * @retval None
4884 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4885 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4886 {
4887 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4888 }
4889
4890 /**
4891 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4892 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4893 * @param TIMx Timer instance
4894 * @retval State of bit (1 or 0).
4895 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4896 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4897 {
4898 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4899 }
4900
4901 /**
4902 * @brief Enable trigger interrupt (TDE).
4903 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4904 * @param TIMx Timer instance
4905 * @retval None
4906 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4907 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4908 {
4909 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4910 }
4911
4912 /**
4913 * @brief Disable trigger interrupt (TDE).
4914 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4915 * @param TIMx Timer instance
4916 * @retval None
4917 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4918 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4919 {
4920 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4921 }
4922
4923 /**
4924 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4925 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4926 * @param TIMx Timer instance
4927 * @retval State of bit (1 or 0).
4928 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4929 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4930 {
4931 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4932 }
4933
4934 /**
4935 * @}
4936 */
4937
4938 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4939 * @{
4940 */
4941 /**
4942 * @brief Generate an update event.
4943 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4944 * @param TIMx Timer instance
4945 * @retval None
4946 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4947 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4948 {
4949 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4950 }
4951
4952 /**
4953 * @brief Generate Capture/Compare 1 event.
4954 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4955 * @param TIMx Timer instance
4956 * @retval None
4957 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4958 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4959 {
4960 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4961 }
4962
4963 /**
4964 * @brief Generate Capture/Compare 2 event.
4965 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4966 * @param TIMx Timer instance
4967 * @retval None
4968 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4969 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4970 {
4971 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4972 }
4973
4974 /**
4975 * @brief Generate Capture/Compare 3 event.
4976 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4977 * @param TIMx Timer instance
4978 * @retval None
4979 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4980 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4981 {
4982 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4983 }
4984
4985 /**
4986 * @brief Generate Capture/Compare 4 event.
4987 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4988 * @param TIMx Timer instance
4989 * @retval None
4990 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4991 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4992 {
4993 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4994 }
4995
4996 /**
4997 * @brief Generate commutation event.
4998 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4999 * @param TIMx Timer instance
5000 * @retval None
5001 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)5002 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5003 {
5004 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5005 }
5006
5007 /**
5008 * @brief Generate trigger event.
5009 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5010 * @param TIMx Timer instance
5011 * @retval None
5012 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)5013 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5014 {
5015 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5016 }
5017
5018 /**
5019 * @brief Generate break event.
5020 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5021 * @param TIMx Timer instance
5022 * @retval None
5023 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)5024 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5025 {
5026 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5027 }
5028
5029 #if defined(TIM_EGR_B2G)
5030 /**
5031 * @brief Generate break 2 event.
5032 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5033 * @param TIMx Timer instance
5034 * @retval None
5035 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5036 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5037 {
5038 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5039 }
5040
5041 #endif /* TIM_EGR_B2G */
5042 /**
5043 * @}
5044 */
5045
5046 #if defined(USE_FULL_LL_DRIVER)
5047 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5048 * @{
5049 */
5050
5051 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5052 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5053 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5054 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5055 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5056 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5057 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5058 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5059 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5060 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5061 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5062 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5063 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5064 /**
5065 * @}
5066 */
5067 #endif /* USE_FULL_LL_DRIVER */
5068
5069 /**
5070 * @}
5071 */
5072
5073 /**
5074 * @}
5075 */
5076
5077 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
5078
5079 /**
5080 * @}
5081 */
5082
5083 #ifdef __cplusplus
5084 }
5085 #endif
5086
5087 #endif /* __STM32F3xx_LL_TIM_H */
5088
