1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WLxx_LL_TIM_H
21 #define __STM32WLxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #if defined(CORE_CM0PLUS)
120 #define TIM_POSITION_BRK_SOURCE ((Source >> 1U) & 0x1FUL)
121 #else
122 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
123 #endif /* CORE_CM0PLUS */
124
125 /* Generic bit definitions for TIMx_AF1 register */
126 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
127 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
128
129 /* Remap mask definitions */
130 #define TIMx_OR1_RMP_SHIFT 16U
131 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
132 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
133 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR_RMP) << TIMx_OR1_RMP_SHIFT)
134 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
135 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
136
137 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
138 #define DT_DELAY_1 ((uint8_t)0x7F)
139 #define DT_DELAY_2 ((uint8_t)0x3F)
140 #define DT_DELAY_3 ((uint8_t)0x1F)
141 #define DT_DELAY_4 ((uint8_t)0x1F)
142
143 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
144 #define DT_RANGE_1 ((uint8_t)0x00)
145 #define DT_RANGE_2 ((uint8_t)0x80)
146 #define DT_RANGE_3 ((uint8_t)0xC0)
147 #define DT_RANGE_4 ((uint8_t)0xE0)
148
149 /** Legacy definitions for compatibility purpose
150 @cond 0
151 */
152 /**
153 @endcond
154 */
155
156 /**
157 * @}
158 */
159
160 /* Private macros ------------------------------------------------------------*/
161 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
162 * @{
163 */
164 /** @brief Convert channel id into channel index.
165 * @param __CHANNEL__ This parameter can be one of the following values:
166 * @arg @ref LL_TIM_CHANNEL_CH1
167 * @arg @ref LL_TIM_CHANNEL_CH1N
168 * @arg @ref LL_TIM_CHANNEL_CH2
169 * @arg @ref LL_TIM_CHANNEL_CH2N
170 * @arg @ref LL_TIM_CHANNEL_CH3
171 * @arg @ref LL_TIM_CHANNEL_CH3N
172 * @arg @ref LL_TIM_CHANNEL_CH4
173 * @arg @ref LL_TIM_CHANNEL_CH5
174 * @arg @ref LL_TIM_CHANNEL_CH6
175 * @retval none
176 */
177 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
178 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
186
187 /** @brief Calculate the deadtime sampling period(in ps).
188 * @param __TIMCLK__ timer input clock frequency (in Hz).
189 * @param __CKD__ This parameter can be one of the following values:
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
192 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
193 * @retval none
194 */
195 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
196 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
197 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
198 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
199 /**
200 * @}
201 */
202
203
204 /* Exported types ------------------------------------------------------------*/
205 #if defined(USE_FULL_LL_DRIVER)
206 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
207 * @{
208 */
209
210 /**
211 * @brief TIM Time Base configuration structure definition.
212 */
213 typedef struct
214 {
215 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
216 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
217
218 This feature can be modified afterwards using unitary function
219 @ref LL_TIM_SetPrescaler().*/
220
221 uint32_t CounterMode; /*!< Specifies the counter mode.
222 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetCounterMode().*/
226
227 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
228 Auto-Reload Register at the next update event.
229 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
230 Some timer instances may support 32 bits counters. In that case this parameter must
231 be a number between 0x0000 and 0xFFFFFFFF.
232
233 This feature can be modified afterwards using unitary function
234 @ref LL_TIM_SetAutoReload().*/
235
236 uint32_t ClockDivision; /*!< Specifies the clock division.
237 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
238
239 This feature can be modified afterwards using unitary function
240 @ref LL_TIM_SetClockDivision().*/
241
242 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
243 reaches zero, an update event is generated and counting restarts
244 from the RCR value (N).
245 This means in PWM mode that (N+1) corresponds to:
246 - the number of PWM periods in edge-aligned mode
247 - the number of half PWM period in center-aligned mode
248 GP timers: this parameter must be a number between Min_Data = 0x00 and
249 Max_Data = 0xFF.
250 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
251 Max_Data = 0xFFFF.
252
253 This feature can be modified afterwards using unitary function
254 @ref LL_TIM_SetRepetitionCounter().*/
255 } LL_TIM_InitTypeDef;
256
257 /**
258 * @brief TIM Output Compare configuration structure definition.
259 */
260 typedef struct
261 {
262 uint32_t OCMode; /*!< Specifies the output mode.
263 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_OC_SetMode().*/
267
268 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
269 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
270
271 This feature can be modified afterwards using unitary functions
272 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
273
274 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
275 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
276
277 This feature can be modified afterwards using unitary functions
278 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
279
280 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
281 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
282
283 This feature can be modified afterwards using unitary function
284 LL_TIM_OC_SetCompareCHx (x=1..6).*/
285
286 uint32_t OCPolarity; /*!< Specifies the output polarity.
287 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
288
289 This feature can be modified afterwards using unitary function
290 @ref LL_TIM_OC_SetPolarity().*/
291
292 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
293 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
294
295 This feature can be modified afterwards using unitary function
296 @ref LL_TIM_OC_SetPolarity().*/
297
298
299 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
300 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
301
302 This feature can be modified afterwards using unitary function
303 @ref LL_TIM_OC_SetIdleState().*/
304
305 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
306 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
307
308 This feature can be modified afterwards using unitary function
309 @ref LL_TIM_OC_SetIdleState().*/
310 } LL_TIM_OC_InitTypeDef;
311
312 /**
313 * @brief TIM Input Capture configuration structure definition.
314 */
315
316 typedef struct
317 {
318
319 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
320 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_IC_SetPolarity().*/
324
325 uint32_t ICActiveInput; /*!< Specifies the input.
326 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetPrescaler().*/
336
337 uint32_t ICFilter; /*!< Specifies the input capture filter.
338 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetFilter().*/
342 } LL_TIM_IC_InitTypeDef;
343
344
345 /**
346 * @brief TIM Encoder interface configuration structure definition.
347 */
348 typedef struct
349 {
350 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
351 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
352
353 This feature can be modified afterwards using unitary function
354 @ref LL_TIM_SetEncoderMode().*/
355
356 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
357 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
358
359 This feature can be modified afterwards using unitary function
360 @ref LL_TIM_IC_SetPolarity().*/
361
362 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
363 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
364
365 This feature can be modified afterwards using unitary function
366 @ref LL_TIM_IC_SetActiveInput().*/
367
368 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
369 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
370
371 This feature can be modified afterwards using unitary function
372 @ref LL_TIM_IC_SetPrescaler().*/
373
374 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
375 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
376
377 This feature can be modified afterwards using unitary function
378 @ref LL_TIM_IC_SetFilter().*/
379
380 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
381 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
382
383 This feature can be modified afterwards using unitary function
384 @ref LL_TIM_IC_SetPolarity().*/
385
386 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
387 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
388
389 This feature can be modified afterwards using unitary function
390 @ref LL_TIM_IC_SetActiveInput().*/
391
392 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
393 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
394
395 This feature can be modified afterwards using unitary function
396 @ref LL_TIM_IC_SetPrescaler().*/
397
398 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
399 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
400
401 This feature can be modified afterwards using unitary function
402 @ref LL_TIM_IC_SetFilter().*/
403
404 } LL_TIM_ENCODER_InitTypeDef;
405
406 /**
407 * @brief TIM Hall sensor interface configuration structure definition.
408 */
409 typedef struct
410 {
411
412 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
413 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
414
415 This feature can be modified afterwards using unitary function
416 @ref LL_TIM_IC_SetPolarity().*/
417
418 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
419 Prescaler must be set to get a maximum counter period longer than the
420 time interval between 2 consecutive changes on the Hall inputs.
421 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
422
423 This feature can be modified afterwards using unitary function
424 @ref LL_TIM_IC_SetPrescaler().*/
425
426 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
427 This parameter can be a value of
428 @ref TIM_LL_EC_IC_FILTER.
429
430 This feature can be modified afterwards using unitary function
431 @ref LL_TIM_IC_SetFilter().*/
432
433 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
434 A positive pulse (TRGO event) is generated with a programmable delay every time
435 a change occurs on the Hall inputs.
436 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
437
438 This feature can be modified afterwards using unitary function
439 @ref LL_TIM_OC_SetCompareCH2().*/
440 } LL_TIM_HALLSENSOR_InitTypeDef;
441
442 /**
443 * @brief BDTR (Break and Dead Time) structure definition
444 */
445 typedef struct
446 {
447 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
448 This parameter can be a value of @ref TIM_LL_EC_OSSR
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_SetOffStates()
452
453 @note This bit-field cannot be modified as long as LOCK level 2 has been
454 programmed. */
455
456 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
457 This parameter can be a value of @ref TIM_LL_EC_OSSI
458
459 This feature can be modified afterwards using unitary function
460 @ref LL_TIM_SetOffStates()
461
462 @note This bit-field cannot be modified as long as LOCK level 2 has been
463 programmed. */
464
465 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
466 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
467
468 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
469 register has been written, their content is frozen until the next reset.*/
470
471 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
472 switching-on of the outputs.
473 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
474
475 This feature can be modified afterwards using unitary function
476 @ref LL_TIM_OC_SetDeadTime()
477
478 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
479 programmed. */
480
481 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
483
484 This feature can be modified afterwards using unitary functions
485 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
486
487 @note This bit-field can not be modified as long as LOCK level 1 has been
488 programmed. */
489
490 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
491 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
492
493 This feature can be modified afterwards using unitary function
494 @ref LL_TIM_ConfigBRK()
495
496 @note This bit-field can not be modified as long as LOCK level 1 has been
497 programmed. */
498
499 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
500 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
501
502 This feature can be modified afterwards using unitary function
503 @ref LL_TIM_ConfigBRK()
504
505 @note This bit-field can not be modified as long as LOCK level 1 has been
506 programmed. */
507
508 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
509 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
510
511 This feature can be modified afterwards using unitary functions
512 @ref LL_TIM_ConfigBRK()
513
514 @note Bidirectional break input is only supported by advanced timers instances.
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
521
522 This feature can be modified afterwards using unitary functions
523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
539
540 This feature can be modified afterwards using unitary function
541 @ref LL_TIM_ConfigBRK2()
542
543 @note This bit-field can not be modified as long as LOCK level 1 has been
544 programmed. */
545
546 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
547 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_ConfigBRK2()
551
552 @note Bidirectional break input is only supported by advanced timers instances.
553
554 @note This bit-field can not be modified as long as LOCK level 1 has been
555 programmed. */
556
557 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
558 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
559
560 This feature can be modified afterwards using unitary functions
561 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
562
563 @note This bit-field can not be modified as long as LOCK level 1 has been
564 programmed. */
565 } LL_TIM_BDTR_InitTypeDef;
566
567 /**
568 * @}
569 */
570 #endif /* USE_FULL_LL_DRIVER */
571
572 /* Exported constants --------------------------------------------------------*/
573 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
574 * @{
575 */
576
577 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
578 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
579 * @{
580 */
581 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
582 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
583 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
584 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
585 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
586 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
587 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
588 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
589 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
590 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
591 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
592 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
593 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
594 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
595 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
596 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
597 /**
598 * @}
599 */
600
601 #if defined(USE_FULL_LL_DRIVER)
602 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
603 * @{
604 */
605 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
606 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
612 * @{
613 */
614 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
615 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
616 /**
617 * @}
618 */
619
620 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
621 * @{
622 */
623 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
624 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
625 /**
626 * @}
627 */
628 #endif /* USE_FULL_LL_DRIVER */
629
630 /** @defgroup TIM_LL_EC_IT IT Defines
631 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
632 * @{
633 */
634 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
635 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
636 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
637 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
638 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
639 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
640 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
641 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
647 * @{
648 */
649 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
650 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
651 /**
652 * @}
653 */
654
655 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
656 * @{
657 */
658 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
659 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
665 * @{
666 */
667 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
668 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
669 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
670 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
671 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
677 * @{
678 */
679 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
680 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
681 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
687 * @{
688 */
689 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
690 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
696 * @{
697 */
698 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
699 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
705 * @{
706 */
707 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
708 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
714 * @{
715 */
716 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
717 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
718 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
719 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
720 /**
721 * @}
722 */
723
724 /** @defgroup TIM_LL_EC_CHANNEL Channel
725 * @{
726 */
727 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
728 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
729 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
730 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
731 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
732 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
733 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
734 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
735 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
736 /**
737 * @}
738 */
739
740 #if defined(USE_FULL_LL_DRIVER)
741 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
742 * @{
743 */
744 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
745 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
746 /**
747 * @}
748 */
749 #endif /* USE_FULL_LL_DRIVER */
750
751 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
752 * @{
753 */
754 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
755 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
756 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
757 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
758 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
759 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
760 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
761 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
762 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
763 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
764 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
765 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
766 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
767 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
773 * @{
774 */
775 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
776 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
782 * @{
783 */
784 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
785 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
791 * @{
792 */
793 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
794 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
795 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
796 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
797 /**
798 * @}
799 */
800
801 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
802 * @{
803 */
804 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
805 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
806 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
812 * @{
813 */
814 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
815 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
816 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
817 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
823 * @{
824 */
825 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
826 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
827 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
828 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
830 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
831 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
832 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
833 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
834 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
835 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
836 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
837 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
839 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
846 * @{
847 */
848 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
849 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
850 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
856 * @{
857 */
858 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
859 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
860 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
866 * @{
867 */
868 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
869 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
870 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_TRGO Trigger Output
876 * @{
877 */
878 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
879 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
880 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
881 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
882 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
883 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
884 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
885 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
886 /**
887 * @}
888 */
889
890 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
891 * @{
892 */
893 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
894 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
895 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
896 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
909 /**
910 * @}
911 */
912
913 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
914 * @{
915 */
916 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
917 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
918 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
919 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
920 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
921 /**
922 * @}
923 */
924
925 /** @defgroup TIM_LL_EC_TS Trigger Selection
926 * @{
927 */
928 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
929 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
930 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
931 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
932 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
933 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
934 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
935 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
941 * @{
942 */
943 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
944 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
945 /**
946 * @}
947 */
948
949 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
950 * @{
951 */
952 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
953 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
954 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
955 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
956 /**
957 * @}
958 */
959
960 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
961 * @{
962 */
963 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
964 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
965 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
966 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
967 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
968 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
969 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
970 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
971 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
972 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
973 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
974 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
975 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
976 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
977 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
979 /**
980 * @}
981 */
982
983 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
984 * @{
985 */
986 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
987 #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< COMP1 output connected to ETR input */
988 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< COMP2 output connected to ETR input */
989 /**
990 * @}
991 */
992
993 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
994 * @{
995 */
996 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
997 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
998 /**
999 * @}
1000 */
1001
1002 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1003 * @{
1004 */
1005 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1006 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1007 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1008 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1009 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1010 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1011 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1012 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1013 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1014 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1015 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1016 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1017 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1018 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1019 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1020 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1026 * @{
1027 */
1028 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1029 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1035 * @{
1036 */
1037 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1038 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1039 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1040 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1041 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1042 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1043 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1044 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1046 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup TIM_LL_EC_OSSI OSSI
1058 * @{
1059 */
1060 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1061 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup TIM_LL_EC_OSSR OSSR
1067 * @{
1068 */
1069 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1070 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1076 * @{
1077 */
1078 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1079 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1080 /**
1081 * @}
1082 */
1083
1084 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1085 * @{
1086 */
1087 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1088 #if defined(COMP1) && defined(COMP2)
1089 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1090 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1091 #endif /* COMP1 && COMP2 */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1097 * @{
1098 */
1099 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1100 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1101 /**
1102 * @}
1103 */
1104
1105 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1106 * @{
1107 */
1108 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1109 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1110 /**
1111 * @}
1112 */
1113
1114 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1115 * @{
1116 */
1117 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1118 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1119 /**
1120 * @}
1121 */
1122
1123 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1124 * @{
1125 */
1126 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1127 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1128 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1129 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1130 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1131 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1132 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1133 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1134 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1135 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1136 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1137 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1138 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1139 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1140 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1141 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1143 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1144 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1145 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1146 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1147 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1155 * @{
1156 */
1157 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1158 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1159 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1160 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1161 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1162 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1163 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1164 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1165 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1166 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1167 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1168 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1169 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1170 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1171 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1172 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1173 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1174 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1175 /**
1176 * @}
1177 */
1178
1179 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC Remap
1180 * @{
1181 */
1182 #define LL_TIM_TIM1_ETR_ADC_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC analog watchdog x */
1183 #define LL_TIM_TIM1_ETR_ADC_RMP_AWD1 (TIM1_OR1_ETR_ADC_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC analog watchdog 1 */
1184 #define LL_TIM_TIM1_ETR_ADC_RMP_AWD2 (TIM1_OR1_ETR_ADC_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC analog watchdog 2 */
1185 #define LL_TIM_TIM1_ETR_ADC_RMP_AWD3 (TIM1_OR1_ETR_ADC_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC analog watchdog 3 */
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1191 * @{
1192 */
1193 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1194 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1195 /**
1196 * @}
1197 */
1198
1199 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1200 * @{
1201 */
1202 #define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR1_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */
1203 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
1209 * @{
1210 */
1211 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1212 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1213 /**
1214 * @}
1215 */
1216
1217 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1218 * @{
1219 */
1220 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1221 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1222 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1223 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1224 /**
1225 * @}
1226 */
1227 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1228 * @{
1229 */
1230 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1231 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1232 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1233 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1239 * @{
1240 */
1241 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1242 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1243 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1244 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1245 /**
1246 * @}
1247 */
1248
1249 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1250 * @{
1251 */
1252 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1253 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1254 /**
1255 * @}
1256 */
1257
1258 /** Legacy definitions for compatibility purpose
1259 @cond 0
1260 */
1261 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1262 /**
1263 @endcond
1264 */
1265 /**
1266 * @}
1267 */
1268
1269 /* Exported macro ------------------------------------------------------------*/
1270 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1271 * @{
1272 */
1273
1274 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1275 * @{
1276 */
1277 /**
1278 * @brief Write a value in TIM register.
1279 * @param __INSTANCE__ TIM Instance
1280 * @param __REG__ Register to be written
1281 * @param __VALUE__ Value to be written in the register
1282 * @retval None
1283 */
1284 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1285
1286 /**
1287 * @brief Read a value in TIM register.
1288 * @param __INSTANCE__ TIM Instance
1289 * @param __REG__ Register to be read
1290 * @retval Register value
1291 */
1292 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1293 /**
1294 * @}
1295 */
1296
1297 /**
1298 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1299 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1300 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1301 * to TIMx_CNT register bit 31)
1302 * @param __CNT__ Counter value
1303 * @retval UIF status bit
1304 */
1305 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1306 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1307
1308 /**
1309 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1310 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1311 * @param __TIMCLK__ timer input clock frequency (in Hz)
1312 * @param __CKD__ This parameter can be one of the following values:
1313 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1314 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1315 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1316 * @param __DT__ deadtime duration (in ns)
1317 * @retval DTG[0:7]
1318 */
1319 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1320 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1321 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1322 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1323 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1324 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1325 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1326 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1327 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1328 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1329 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1330 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1331 0U)
1332
1333 /**
1334 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1335 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1336 * @param __TIMCLK__ timer input clock frequency (in Hz)
1337 * @param __CNTCLK__ counter clock frequency (in Hz)
1338 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1339 */
1340 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1341 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1342
1343 /**
1344 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1345 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1346 * @param __TIMCLK__ timer input clock frequency (in Hz)
1347 * @param __PSC__ prescaler
1348 * @param __FREQ__ output signal frequency (in Hz)
1349 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1350 */
1351 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1352 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1353
1354 /**
1355 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1356 * active/inactive delay.
1357 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1358 * @param __TIMCLK__ timer input clock frequency (in Hz)
1359 * @param __PSC__ prescaler
1360 * @param __DELAY__ timer output compare active/inactive delay (in us)
1361 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1362 */
1363 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1364 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1365 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1366
1367 /**
1368 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1369 * (when the timer operates in one pulse mode).
1370 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1371 * @param __TIMCLK__ timer input clock frequency (in Hz)
1372 * @param __PSC__ prescaler
1373 * @param __DELAY__ timer output compare active/inactive delay (in us)
1374 * @param __PULSE__ pulse duration (in us)
1375 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1376 */
1377 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1378 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1379 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1380
1381 /**
1382 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1383 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1384 * @param __ICPSC__ This parameter can be one of the following values:
1385 * @arg @ref LL_TIM_ICPSC_DIV1
1386 * @arg @ref LL_TIM_ICPSC_DIV2
1387 * @arg @ref LL_TIM_ICPSC_DIV4
1388 * @arg @ref LL_TIM_ICPSC_DIV8
1389 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1390 */
1391 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1392 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1393
1394
1395 /**
1396 * @}
1397 */
1398
1399
1400 /**
1401 * @}
1402 */
1403
1404 /* Exported functions --------------------------------------------------------*/
1405 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1406 * @{
1407 */
1408
1409 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1410 * @{
1411 */
1412 /**
1413 * @brief Enable timer counter.
1414 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1415 * @param TIMx Timer instance
1416 * @retval None
1417 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1418 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1419 {
1420 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1421 }
1422
1423 /**
1424 * @brief Disable timer counter.
1425 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1426 * @param TIMx Timer instance
1427 * @retval None
1428 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1429 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1430 {
1431 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1432 }
1433
1434 /**
1435 * @brief Indicates whether the timer counter is enabled.
1436 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1437 * @param TIMx Timer instance
1438 * @retval State of bit (1 or 0).
1439 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1440 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1441 {
1442 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1443 }
1444
1445 /**
1446 * @brief Enable update event generation.
1447 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1448 * @param TIMx Timer instance
1449 * @retval None
1450 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1451 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1452 {
1453 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1454 }
1455
1456 /**
1457 * @brief Disable update event generation.
1458 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1459 * @param TIMx Timer instance
1460 * @retval None
1461 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1462 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1463 {
1464 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1465 }
1466
1467 /**
1468 * @brief Indicates whether update event generation is enabled.
1469 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1470 * @param TIMx Timer instance
1471 * @retval Inverted state of bit (0 or 1).
1472 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1473 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1474 {
1475 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1476 }
1477
1478 /**
1479 * @brief Set update event source
1480 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1481 * generate an update interrupt or DMA request if enabled:
1482 * - Counter overflow/underflow
1483 * - Setting the UG bit
1484 * - Update generation through the slave mode controller
1485 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1486 * overflow/underflow generates an update interrupt or DMA request if enabled.
1487 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1488 * @param TIMx Timer instance
1489 * @param UpdateSource This parameter can be one of the following values:
1490 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1491 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1492 * @retval None
1493 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1494 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1495 {
1496 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1497 }
1498
1499 /**
1500 * @brief Get actual event update source
1501 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1502 * @param TIMx Timer instance
1503 * @retval Returned value can be one of the following values:
1504 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1505 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1506 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1507 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1508 {
1509 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1510 }
1511
1512 /**
1513 * @brief Set one pulse mode (one shot v.s. repetitive).
1514 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1515 * @param TIMx Timer instance
1516 * @param OnePulseMode This parameter can be one of the following values:
1517 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1518 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1519 * @retval None
1520 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1521 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1522 {
1523 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1524 }
1525
1526 /**
1527 * @brief Get actual one pulse mode.
1528 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1529 * @param TIMx Timer instance
1530 * @retval Returned value can be one of the following values:
1531 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1532 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1533 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1534 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1535 {
1536 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1537 }
1538
1539 /**
1540 * @brief Set the timer counter counting mode.
1541 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1542 * check whether or not the counter mode selection feature is supported
1543 * by a timer instance.
1544 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1545 * requires a timer reset to avoid unexpected direction
1546 * due to DIR bit readonly in center aligned mode.
1547 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1548 * CR1 CMS LL_TIM_SetCounterMode
1549 * @param TIMx Timer instance
1550 * @param CounterMode This parameter can be one of the following values:
1551 * @arg @ref LL_TIM_COUNTERMODE_UP
1552 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1553 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1554 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1555 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1556 * @retval None
1557 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1558 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1559 {
1560 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1561 }
1562
1563 /**
1564 * @brief Get actual counter mode.
1565 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1566 * check whether or not the counter mode selection feature is supported
1567 * by a timer instance.
1568 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1569 * CR1 CMS LL_TIM_GetCounterMode
1570 * @param TIMx Timer instance
1571 * @retval Returned value can be one of the following values:
1572 * @arg @ref LL_TIM_COUNTERMODE_UP
1573 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1574 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1575 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1576 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1577 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1578 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1579 {
1580 uint32_t counter_mode;
1581
1582 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1583
1584 if (counter_mode == 0U)
1585 {
1586 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1587 }
1588
1589 return counter_mode;
1590 }
1591
1592 /**
1593 * @brief Enable auto-reload (ARR) preload.
1594 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1595 * @param TIMx Timer instance
1596 * @retval None
1597 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1598 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1599 {
1600 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1601 }
1602
1603 /**
1604 * @brief Disable auto-reload (ARR) preload.
1605 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1606 * @param TIMx Timer instance
1607 * @retval None
1608 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1609 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1610 {
1611 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1612 }
1613
1614 /**
1615 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1616 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1617 * @param TIMx Timer instance
1618 * @retval State of bit (1 or 0).
1619 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1620 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1621 {
1622 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1623 }
1624
1625 /**
1626 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1627 * (when supported) and the digital filters.
1628 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1629 * whether or not the clock division feature is supported by the timer
1630 * instance.
1631 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1632 * @param TIMx Timer instance
1633 * @param ClockDivision This parameter can be one of the following values:
1634 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1635 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1636 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1637 * @retval None
1638 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1639 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1640 {
1641 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1642 }
1643
1644 /**
1645 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1646 * generators (when supported) and the digital filters.
1647 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1648 * whether or not the clock division feature is supported by the timer
1649 * instance.
1650 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1651 * @param TIMx Timer instance
1652 * @retval Returned value can be one of the following values:
1653 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1654 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1655 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1656 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1657 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1658 {
1659 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1660 }
1661
1662 /**
1663 * @brief Set the counter value.
1664 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1665 * whether or not a timer instance supports a 32 bits counter.
1666 * @rmtoll CNT CNT LL_TIM_SetCounter
1667 * @param TIMx Timer instance
1668 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1669 * @retval None
1670 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1671 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1672 {
1673 WRITE_REG(TIMx->CNT, Counter);
1674 }
1675
1676 /**
1677 * @brief Get the counter value.
1678 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1679 * whether or not a timer instance supports a 32 bits counter.
1680 * @rmtoll CNT CNT LL_TIM_GetCounter
1681 * @param TIMx Timer instance
1682 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1683 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1684 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1685 {
1686 return (uint32_t)(READ_REG(TIMx->CNT));
1687 }
1688
1689 /**
1690 * @brief Get the current direction of the counter
1691 * @rmtoll CR1 DIR LL_TIM_GetDirection
1692 * @param TIMx Timer instance
1693 * @retval Returned value can be one of the following values:
1694 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1695 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1696 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1697 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1698 {
1699 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1700 }
1701
1702 /**
1703 * @brief Set the prescaler value.
1704 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1705 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1706 * prescaler ratio is taken into account at the next update event.
1707 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1708 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1709 * @param TIMx Timer instance
1710 * @param Prescaler between Min_Data=0 and Max_Data=65535
1711 * @retval None
1712 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1713 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1714 {
1715 WRITE_REG(TIMx->PSC, Prescaler);
1716 }
1717
1718 /**
1719 * @brief Get the prescaler value.
1720 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1721 * @param TIMx Timer instance
1722 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1723 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1724 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1725 {
1726 return (uint32_t)(READ_REG(TIMx->PSC));
1727 }
1728
1729 /**
1730 * @brief Set the auto-reload value.
1731 * @note The counter is blocked while the auto-reload value is null.
1732 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1733 * whether or not a timer instance supports a 32 bits counter.
1734 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1735 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1736 * @param TIMx Timer instance
1737 * @param AutoReload between Min_Data=0 and Max_Data=65535
1738 * @retval None
1739 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1740 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1741 {
1742 WRITE_REG(TIMx->ARR, AutoReload);
1743 }
1744
1745 /**
1746 * @brief Get the auto-reload value.
1747 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1748 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1749 * whether or not a timer instance supports a 32 bits counter.
1750 * @param TIMx Timer instance
1751 * @retval Auto-reload value
1752 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1753 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1754 {
1755 return (uint32_t)(READ_REG(TIMx->ARR));
1756 }
1757
1758 /**
1759 * @brief Set the repetition counter value.
1760 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1761 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1762 * whether or not a timer instance supports a repetition counter.
1763 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1764 * @param TIMx Timer instance
1765 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1766 * @retval None
1767 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1768 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1769 {
1770 WRITE_REG(TIMx->RCR, RepetitionCounter);
1771 }
1772
1773 /**
1774 * @brief Get the repetition counter value.
1775 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1776 * whether or not a timer instance supports a repetition counter.
1777 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1778 * @param TIMx Timer instance
1779 * @retval Repetition counter value
1780 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1781 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1782 {
1783 return (uint32_t)(READ_REG(TIMx->RCR));
1784 }
1785
1786 /**
1787 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1788 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1789 * in an atomic way.
1790 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1791 * @param TIMx Timer instance
1792 * @retval None
1793 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1794 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1795 {
1796 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1797 }
1798
1799 /**
1800 * @brief Disable update interrupt flag (UIF) remapping.
1801 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1802 * @param TIMx Timer instance
1803 * @retval None
1804 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1805 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1806 {
1807 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1808 }
1809
1810 /**
1811 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1812 * @param Counter Counter value
1813 * @retval State of bit (1 or 0).
1814 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1815 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1816 {
1817 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1825 * @{
1826 */
1827 /**
1828 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1829 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1830 * they are updated only when a commutation event (COM) occurs.
1831 * @note Only on channels that have a complementary output.
1832 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1833 * whether or not a timer instance is able to generate a commutation event.
1834 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1835 * @param TIMx Timer instance
1836 * @retval None
1837 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1838 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1839 {
1840 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1841 }
1842
1843 /**
1844 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1845 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1846 * whether or not a timer instance is able to generate a commutation event.
1847 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1848 * @param TIMx Timer instance
1849 * @retval None
1850 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1851 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1852 {
1853 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1854 }
1855
1856 /**
1857 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1858 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1859 * whether or not a timer instance is able to generate a commutation event.
1860 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1861 * @param TIMx Timer instance
1862 * @param CCUpdateSource This parameter can be one of the following values:
1863 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1864 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1865 * @retval None
1866 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1867 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1868 {
1869 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1870 }
1871
1872 /**
1873 * @brief Set the trigger of the capture/compare DMA request.
1874 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1875 * @param TIMx Timer instance
1876 * @param DMAReqTrigger This parameter can be one of the following values:
1877 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1878 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1879 * @retval None
1880 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1881 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1882 {
1883 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1884 }
1885
1886 /**
1887 * @brief Get actual trigger of the capture/compare DMA request.
1888 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1889 * @param TIMx Timer instance
1890 * @retval Returned value can be one of the following values:
1891 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1892 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1893 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1894 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1895 {
1896 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1897 }
1898
1899 /**
1900 * @brief Set the lock level to freeze the
1901 * configuration of several capture/compare parameters.
1902 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1903 * the lock mechanism is supported by a timer instance.
1904 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1905 * @param TIMx Timer instance
1906 * @param LockLevel This parameter can be one of the following values:
1907 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1908 * @arg @ref LL_TIM_LOCKLEVEL_1
1909 * @arg @ref LL_TIM_LOCKLEVEL_2
1910 * @arg @ref LL_TIM_LOCKLEVEL_3
1911 * @retval None
1912 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1913 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1914 {
1915 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1916 }
1917
1918 /**
1919 * @brief Enable capture/compare channels.
1920 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1921 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1922 * CCER CC2E LL_TIM_CC_EnableChannel\n
1923 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1924 * CCER CC3E LL_TIM_CC_EnableChannel\n
1925 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1926 * CCER CC4E LL_TIM_CC_EnableChannel\n
1927 * CCER CC5E LL_TIM_CC_EnableChannel\n
1928 * CCER CC6E LL_TIM_CC_EnableChannel
1929 * @param TIMx Timer instance
1930 * @param Channels This parameter can be a combination of the following values:
1931 * @arg @ref LL_TIM_CHANNEL_CH1
1932 * @arg @ref LL_TIM_CHANNEL_CH1N
1933 * @arg @ref LL_TIM_CHANNEL_CH2
1934 * @arg @ref LL_TIM_CHANNEL_CH2N
1935 * @arg @ref LL_TIM_CHANNEL_CH3
1936 * @arg @ref LL_TIM_CHANNEL_CH3N
1937 * @arg @ref LL_TIM_CHANNEL_CH4
1938 * @arg @ref LL_TIM_CHANNEL_CH5
1939 * @arg @ref LL_TIM_CHANNEL_CH6
1940 * @retval None
1941 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1942 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1943 {
1944 SET_BIT(TIMx->CCER, Channels);
1945 }
1946
1947 /**
1948 * @brief Disable capture/compare channels.
1949 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1950 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1951 * CCER CC2E LL_TIM_CC_DisableChannel\n
1952 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1953 * CCER CC3E LL_TIM_CC_DisableChannel\n
1954 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1955 * CCER CC4E LL_TIM_CC_DisableChannel\n
1956 * CCER CC5E LL_TIM_CC_DisableChannel\n
1957 * CCER CC6E LL_TIM_CC_DisableChannel
1958 * @param TIMx Timer instance
1959 * @param Channels This parameter can be a combination of the following values:
1960 * @arg @ref LL_TIM_CHANNEL_CH1
1961 * @arg @ref LL_TIM_CHANNEL_CH1N
1962 * @arg @ref LL_TIM_CHANNEL_CH2
1963 * @arg @ref LL_TIM_CHANNEL_CH2N
1964 * @arg @ref LL_TIM_CHANNEL_CH3
1965 * @arg @ref LL_TIM_CHANNEL_CH3N
1966 * @arg @ref LL_TIM_CHANNEL_CH4
1967 * @arg @ref LL_TIM_CHANNEL_CH5
1968 * @arg @ref LL_TIM_CHANNEL_CH6
1969 * @retval None
1970 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1971 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1972 {
1973 CLEAR_BIT(TIMx->CCER, Channels);
1974 }
1975
1976 /**
1977 * @brief Indicate whether channel(s) is(are) enabled.
1978 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1979 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1980 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1981 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1982 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1983 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1984 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1985 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1986 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1987 * @param TIMx Timer instance
1988 * @param Channels This parameter can be a combination of the following values:
1989 * @arg @ref LL_TIM_CHANNEL_CH1
1990 * @arg @ref LL_TIM_CHANNEL_CH1N
1991 * @arg @ref LL_TIM_CHANNEL_CH2
1992 * @arg @ref LL_TIM_CHANNEL_CH2N
1993 * @arg @ref LL_TIM_CHANNEL_CH3
1994 * @arg @ref LL_TIM_CHANNEL_CH3N
1995 * @arg @ref LL_TIM_CHANNEL_CH4
1996 * @arg @ref LL_TIM_CHANNEL_CH5
1997 * @arg @ref LL_TIM_CHANNEL_CH6
1998 * @retval State of bit (1 or 0).
1999 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2000 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2001 {
2002 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2003 }
2004
2005 /**
2006 * @}
2007 */
2008
2009 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2010 * @{
2011 */
2012 /**
2013 * @brief Configure an output channel.
2014 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2015 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2016 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2017 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2018 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2019 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2020 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2021 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2022 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2023 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2024 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2025 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2026 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2027 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2028 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2029 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2030 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2031 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2032 * @param TIMx Timer instance
2033 * @param Channel This parameter can be one of the following values:
2034 * @arg @ref LL_TIM_CHANNEL_CH1
2035 * @arg @ref LL_TIM_CHANNEL_CH2
2036 * @arg @ref LL_TIM_CHANNEL_CH3
2037 * @arg @ref LL_TIM_CHANNEL_CH4
2038 * @arg @ref LL_TIM_CHANNEL_CH5
2039 * @arg @ref LL_TIM_CHANNEL_CH6
2040 * @param Configuration This parameter must be a combination of all the following values:
2041 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2042 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2043 * @retval None
2044 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2045 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2046 {
2047 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2048 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2049 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2050 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2051 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2052 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2053 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2054 }
2055
2056 /**
2057 * @brief Define the behavior of the output reference signal OCxREF from which
2058 * OCx and OCxN (when relevant) are derived.
2059 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2060 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2061 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2062 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2063 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2064 * CCMR3 OC6M LL_TIM_OC_SetMode
2065 * @param TIMx Timer instance
2066 * @param Channel This parameter can be one of the following values:
2067 * @arg @ref LL_TIM_CHANNEL_CH1
2068 * @arg @ref LL_TIM_CHANNEL_CH2
2069 * @arg @ref LL_TIM_CHANNEL_CH3
2070 * @arg @ref LL_TIM_CHANNEL_CH4
2071 * @arg @ref LL_TIM_CHANNEL_CH5
2072 * @arg @ref LL_TIM_CHANNEL_CH6
2073 * @param Mode This parameter can be one of the following values:
2074 * @arg @ref LL_TIM_OCMODE_FROZEN
2075 * @arg @ref LL_TIM_OCMODE_ACTIVE
2076 * @arg @ref LL_TIM_OCMODE_INACTIVE
2077 * @arg @ref LL_TIM_OCMODE_TOGGLE
2078 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2079 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2080 * @arg @ref LL_TIM_OCMODE_PWM1
2081 * @arg @ref LL_TIM_OCMODE_PWM2
2082 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2083 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2084 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2085 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2086 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2087 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2088 * @retval None
2089 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2090 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2091 {
2092 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2093 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2094 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2095 }
2096
2097 /**
2098 * @brief Get the output compare mode of an output channel.
2099 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2100 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2101 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2102 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2103 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2104 * CCMR3 OC6M LL_TIM_OC_GetMode
2105 * @param TIMx Timer instance
2106 * @param Channel This parameter can be one of the following values:
2107 * @arg @ref LL_TIM_CHANNEL_CH1
2108 * @arg @ref LL_TIM_CHANNEL_CH2
2109 * @arg @ref LL_TIM_CHANNEL_CH3
2110 * @arg @ref LL_TIM_CHANNEL_CH4
2111 * @arg @ref LL_TIM_CHANNEL_CH5
2112 * @arg @ref LL_TIM_CHANNEL_CH6
2113 * @retval Returned value can be one of the following values:
2114 * @arg @ref LL_TIM_OCMODE_FROZEN
2115 * @arg @ref LL_TIM_OCMODE_ACTIVE
2116 * @arg @ref LL_TIM_OCMODE_INACTIVE
2117 * @arg @ref LL_TIM_OCMODE_TOGGLE
2118 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2119 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2120 * @arg @ref LL_TIM_OCMODE_PWM1
2121 * @arg @ref LL_TIM_OCMODE_PWM2
2122 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2123 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2124 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2125 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2126 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2127 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2128 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2129 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2130 {
2131 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2132 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2133 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2134 }
2135
2136 /**
2137 * @brief Set the polarity of an output channel.
2138 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2139 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2140 * CCER CC2P LL_TIM_OC_SetPolarity\n
2141 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2142 * CCER CC3P LL_TIM_OC_SetPolarity\n
2143 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2144 * CCER CC4P LL_TIM_OC_SetPolarity\n
2145 * CCER CC5P LL_TIM_OC_SetPolarity\n
2146 * CCER CC6P LL_TIM_OC_SetPolarity
2147 * @param TIMx Timer instance
2148 * @param Channel This parameter can be one of the following values:
2149 * @arg @ref LL_TIM_CHANNEL_CH1
2150 * @arg @ref LL_TIM_CHANNEL_CH1N
2151 * @arg @ref LL_TIM_CHANNEL_CH2
2152 * @arg @ref LL_TIM_CHANNEL_CH2N
2153 * @arg @ref LL_TIM_CHANNEL_CH3
2154 * @arg @ref LL_TIM_CHANNEL_CH3N
2155 * @arg @ref LL_TIM_CHANNEL_CH4
2156 * @arg @ref LL_TIM_CHANNEL_CH5
2157 * @arg @ref LL_TIM_CHANNEL_CH6
2158 * @param Polarity This parameter can be one of the following values:
2159 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2160 * @arg @ref LL_TIM_OCPOLARITY_LOW
2161 * @retval None
2162 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2163 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2164 {
2165 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2166 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2167 }
2168
2169 /**
2170 * @brief Get the polarity of an output channel.
2171 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2172 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2173 * CCER CC2P LL_TIM_OC_GetPolarity\n
2174 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2175 * CCER CC3P LL_TIM_OC_GetPolarity\n
2176 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2177 * CCER CC4P LL_TIM_OC_GetPolarity\n
2178 * CCER CC5P LL_TIM_OC_GetPolarity\n
2179 * CCER CC6P LL_TIM_OC_GetPolarity
2180 * @param TIMx Timer instance
2181 * @param Channel This parameter can be one of the following values:
2182 * @arg @ref LL_TIM_CHANNEL_CH1
2183 * @arg @ref LL_TIM_CHANNEL_CH1N
2184 * @arg @ref LL_TIM_CHANNEL_CH2
2185 * @arg @ref LL_TIM_CHANNEL_CH2N
2186 * @arg @ref LL_TIM_CHANNEL_CH3
2187 * @arg @ref LL_TIM_CHANNEL_CH3N
2188 * @arg @ref LL_TIM_CHANNEL_CH4
2189 * @arg @ref LL_TIM_CHANNEL_CH5
2190 * @arg @ref LL_TIM_CHANNEL_CH6
2191 * @retval Returned value can be one of the following values:
2192 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2193 * @arg @ref LL_TIM_OCPOLARITY_LOW
2194 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2195 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2196 {
2197 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2198 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2199 }
2200
2201 /**
2202 * @brief Set the IDLE state of an output channel
2203 * @note This function is significant only for the timer instances
2204 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2205 * can be used to check whether or not a timer instance provides
2206 * a break input.
2207 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2208 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2209 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2210 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2211 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2212 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2213 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2214 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2215 * CR2 OIS6 LL_TIM_OC_SetIdleState
2216 * @param TIMx Timer instance
2217 * @param Channel This parameter can be one of the following values:
2218 * @arg @ref LL_TIM_CHANNEL_CH1
2219 * @arg @ref LL_TIM_CHANNEL_CH1N
2220 * @arg @ref LL_TIM_CHANNEL_CH2
2221 * @arg @ref LL_TIM_CHANNEL_CH2N
2222 * @arg @ref LL_TIM_CHANNEL_CH3
2223 * @arg @ref LL_TIM_CHANNEL_CH3N
2224 * @arg @ref LL_TIM_CHANNEL_CH4
2225 * @arg @ref LL_TIM_CHANNEL_CH5
2226 * @arg @ref LL_TIM_CHANNEL_CH6
2227 * @param IdleState This parameter can be one of the following values:
2228 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2229 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2230 * @retval None
2231 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2232 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2233 {
2234 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2235 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2236 }
2237
2238 /**
2239 * @brief Get the IDLE state of an output channel
2240 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2241 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2242 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2243 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2244 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2245 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2246 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2247 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2248 * CR2 OIS6 LL_TIM_OC_GetIdleState
2249 * @param TIMx Timer instance
2250 * @param Channel This parameter can be one of the following values:
2251 * @arg @ref LL_TIM_CHANNEL_CH1
2252 * @arg @ref LL_TIM_CHANNEL_CH1N
2253 * @arg @ref LL_TIM_CHANNEL_CH2
2254 * @arg @ref LL_TIM_CHANNEL_CH2N
2255 * @arg @ref LL_TIM_CHANNEL_CH3
2256 * @arg @ref LL_TIM_CHANNEL_CH3N
2257 * @arg @ref LL_TIM_CHANNEL_CH4
2258 * @arg @ref LL_TIM_CHANNEL_CH5
2259 * @arg @ref LL_TIM_CHANNEL_CH6
2260 * @retval Returned value can be one of the following values:
2261 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2262 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2263 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2264 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2265 {
2266 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2267 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2268 }
2269
2270 /**
2271 * @brief Enable fast mode for the output channel.
2272 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2273 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2274 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2275 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2276 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2277 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2278 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2279 * @param TIMx Timer instance
2280 * @param Channel This parameter can be one of the following values:
2281 * @arg @ref LL_TIM_CHANNEL_CH1
2282 * @arg @ref LL_TIM_CHANNEL_CH2
2283 * @arg @ref LL_TIM_CHANNEL_CH3
2284 * @arg @ref LL_TIM_CHANNEL_CH4
2285 * @arg @ref LL_TIM_CHANNEL_CH5
2286 * @arg @ref LL_TIM_CHANNEL_CH6
2287 * @retval None
2288 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2289 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2290 {
2291 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2292 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2293 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2294
2295 }
2296
2297 /**
2298 * @brief Disable fast mode for the output channel.
2299 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2300 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2301 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2302 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2303 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2304 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2305 * @param TIMx Timer instance
2306 * @param Channel This parameter can be one of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH2
2309 * @arg @ref LL_TIM_CHANNEL_CH3
2310 * @arg @ref LL_TIM_CHANNEL_CH4
2311 * @arg @ref LL_TIM_CHANNEL_CH5
2312 * @arg @ref LL_TIM_CHANNEL_CH6
2313 * @retval None
2314 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2315 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2316 {
2317 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2318 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2319 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2320
2321 }
2322
2323 /**
2324 * @brief Indicates whether fast mode is enabled for the output channel.
2325 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2326 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2327 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2328 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2329 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2330 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2331 * @param TIMx Timer instance
2332 * @param Channel This parameter can be one of the following values:
2333 * @arg @ref LL_TIM_CHANNEL_CH1
2334 * @arg @ref LL_TIM_CHANNEL_CH2
2335 * @arg @ref LL_TIM_CHANNEL_CH3
2336 * @arg @ref LL_TIM_CHANNEL_CH4
2337 * @arg @ref LL_TIM_CHANNEL_CH5
2338 * @arg @ref LL_TIM_CHANNEL_CH6
2339 * @retval State of bit (1 or 0).
2340 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2341 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2342 {
2343 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2344 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2345 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2346 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2347 }
2348
2349 /**
2350 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2351 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2352 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2353 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2354 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2355 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2356 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2357 * @param TIMx Timer instance
2358 * @param Channel This parameter can be one of the following values:
2359 * @arg @ref LL_TIM_CHANNEL_CH1
2360 * @arg @ref LL_TIM_CHANNEL_CH2
2361 * @arg @ref LL_TIM_CHANNEL_CH3
2362 * @arg @ref LL_TIM_CHANNEL_CH4
2363 * @arg @ref LL_TIM_CHANNEL_CH5
2364 * @arg @ref LL_TIM_CHANNEL_CH6
2365 * @retval None
2366 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2367 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2368 {
2369 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2370 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2371 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2372 }
2373
2374 /**
2375 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2376 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2377 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2378 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2379 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2380 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2381 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2382 * @param TIMx Timer instance
2383 * @param Channel This parameter can be one of the following values:
2384 * @arg @ref LL_TIM_CHANNEL_CH1
2385 * @arg @ref LL_TIM_CHANNEL_CH2
2386 * @arg @ref LL_TIM_CHANNEL_CH3
2387 * @arg @ref LL_TIM_CHANNEL_CH4
2388 * @arg @ref LL_TIM_CHANNEL_CH5
2389 * @arg @ref LL_TIM_CHANNEL_CH6
2390 * @retval None
2391 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2392 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2393 {
2394 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2395 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2396 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2397 }
2398
2399 /**
2400 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2401 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2402 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2403 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2404 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2405 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2406 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2407 * @param TIMx Timer instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_TIM_CHANNEL_CH1
2410 * @arg @ref LL_TIM_CHANNEL_CH2
2411 * @arg @ref LL_TIM_CHANNEL_CH3
2412 * @arg @ref LL_TIM_CHANNEL_CH4
2413 * @arg @ref LL_TIM_CHANNEL_CH5
2414 * @arg @ref LL_TIM_CHANNEL_CH6
2415 * @retval State of bit (1 or 0).
2416 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2417 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2418 {
2419 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2420 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2421 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2422 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2423 }
2424
2425 /**
2426 * @brief Enable clearing the output channel on an external event.
2427 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2428 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2429 * or not a timer instance can clear the OCxREF signal on an external event.
2430 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2431 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2432 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2433 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2434 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2435 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2436 * @param TIMx Timer instance
2437 * @param Channel This parameter can be one of the following values:
2438 * @arg @ref LL_TIM_CHANNEL_CH1
2439 * @arg @ref LL_TIM_CHANNEL_CH2
2440 * @arg @ref LL_TIM_CHANNEL_CH3
2441 * @arg @ref LL_TIM_CHANNEL_CH4
2442 * @arg @ref LL_TIM_CHANNEL_CH5
2443 * @arg @ref LL_TIM_CHANNEL_CH6
2444 * @retval None
2445 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2446 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2447 {
2448 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2449 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2450 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2451 }
2452
2453 /**
2454 * @brief Disable clearing the output channel on an external event.
2455 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2456 * or not a timer instance can clear the OCxREF signal on an external event.
2457 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2458 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2459 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2460 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2461 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2462 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2463 * @param TIMx Timer instance
2464 * @param Channel This parameter can be one of the following values:
2465 * @arg @ref LL_TIM_CHANNEL_CH1
2466 * @arg @ref LL_TIM_CHANNEL_CH2
2467 * @arg @ref LL_TIM_CHANNEL_CH3
2468 * @arg @ref LL_TIM_CHANNEL_CH4
2469 * @arg @ref LL_TIM_CHANNEL_CH5
2470 * @arg @ref LL_TIM_CHANNEL_CH6
2471 * @retval None
2472 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2473 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2474 {
2475 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2476 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2477 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2478 }
2479
2480 /**
2481 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2482 * @note This function enables clearing the output channel on an external event.
2483 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2484 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2485 * or not a timer instance can clear the OCxREF signal on an external event.
2486 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2487 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2488 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2489 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2490 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2491 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2492 * @param TIMx Timer instance
2493 * @param Channel This parameter can be one of the following values:
2494 * @arg @ref LL_TIM_CHANNEL_CH1
2495 * @arg @ref LL_TIM_CHANNEL_CH2
2496 * @arg @ref LL_TIM_CHANNEL_CH3
2497 * @arg @ref LL_TIM_CHANNEL_CH4
2498 * @arg @ref LL_TIM_CHANNEL_CH5
2499 * @arg @ref LL_TIM_CHANNEL_CH6
2500 * @retval State of bit (1 or 0).
2501 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2502 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2503 {
2504 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2505 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2506 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2507 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2508 }
2509
2510 /**
2511 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2512 * the Ocx and OCxN signals).
2513 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2514 * dead-time insertion feature is supported by a timer instance.
2515 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2516 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2517 * @param TIMx Timer instance
2518 * @param DeadTime between Min_Data=0 and Max_Data=255
2519 * @retval None
2520 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2521 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2522 {
2523 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2524 }
2525
2526 /**
2527 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2528 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2529 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2530 * whether or not a timer instance supports a 32 bits counter.
2531 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2532 * output channel 1 is supported by a timer instance.
2533 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2534 * @param TIMx Timer instance
2535 * @param CompareValue between Min_Data=0 and Max_Data=65535
2536 * @retval None
2537 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2538 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2539 {
2540 WRITE_REG(TIMx->CCR1, CompareValue);
2541 }
2542
2543 /**
2544 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2545 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2546 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2547 * whether or not a timer instance supports a 32 bits counter.
2548 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2549 * output channel 2 is supported by a timer instance.
2550 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2551 * @param TIMx Timer instance
2552 * @param CompareValue between Min_Data=0 and Max_Data=65535
2553 * @retval None
2554 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2555 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2556 {
2557 WRITE_REG(TIMx->CCR2, CompareValue);
2558 }
2559
2560 /**
2561 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2562 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2563 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2564 * whether or not a timer instance supports a 32 bits counter.
2565 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2566 * output channel is supported by a timer instance.
2567 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2568 * @param TIMx Timer instance
2569 * @param CompareValue between Min_Data=0 and Max_Data=65535
2570 * @retval None
2571 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2572 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2573 {
2574 WRITE_REG(TIMx->CCR3, CompareValue);
2575 }
2576
2577 /**
2578 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2579 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2580 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2581 * whether or not a timer instance supports a 32 bits counter.
2582 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2583 * output channel 4 is supported by a timer instance.
2584 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2585 * @param TIMx Timer instance
2586 * @param CompareValue between Min_Data=0 and Max_Data=65535
2587 * @retval None
2588 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2589 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2590 {
2591 WRITE_REG(TIMx->CCR4, CompareValue);
2592 }
2593
2594 /**
2595 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2596 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2597 * output channel 5 is supported by a timer instance.
2598 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2599 * @param TIMx Timer instance
2600 * @param CompareValue between Min_Data=0 and Max_Data=65535
2601 * @retval None
2602 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2603 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2604 {
2605 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2606 }
2607
2608 /**
2609 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2610 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2611 * output channel 6 is supported by a timer instance.
2612 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2613 * @param TIMx Timer instance
2614 * @param CompareValue between Min_Data=0 and Max_Data=65535
2615 * @retval None
2616 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2617 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2618 {
2619 WRITE_REG(TIMx->CCR6, CompareValue);
2620 }
2621
2622 /**
2623 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2624 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2625 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2626 * whether or not a timer instance supports a 32 bits counter.
2627 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2628 * output channel 1 is supported by a timer instance.
2629 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2630 * @param TIMx Timer instance
2631 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2632 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2633 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2634 {
2635 return (uint32_t)(READ_REG(TIMx->CCR1));
2636 }
2637
2638 /**
2639 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2640 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2641 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2642 * whether or not a timer instance supports a 32 bits counter.
2643 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2644 * output channel 2 is supported by a timer instance.
2645 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2646 * @param TIMx Timer instance
2647 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2648 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2649 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2650 {
2651 return (uint32_t)(READ_REG(TIMx->CCR2));
2652 }
2653
2654 /**
2655 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2656 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2657 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2658 * whether or not a timer instance supports a 32 bits counter.
2659 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2660 * output channel 3 is supported by a timer instance.
2661 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2662 * @param TIMx Timer instance
2663 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2664 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2665 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2666 {
2667 return (uint32_t)(READ_REG(TIMx->CCR3));
2668 }
2669
2670 /**
2671 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2672 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2673 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2674 * whether or not a timer instance supports a 32 bits counter.
2675 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2676 * output channel 4 is supported by a timer instance.
2677 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2678 * @param TIMx Timer instance
2679 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2680 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2681 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2682 {
2683 return (uint32_t)(READ_REG(TIMx->CCR4));
2684 }
2685
2686 /**
2687 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2688 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2689 * output channel 5 is supported by a timer instance.
2690 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2691 * @param TIMx Timer instance
2692 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2693 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2694 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2695 {
2696 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2697 }
2698
2699 /**
2700 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2701 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2702 * output channel 6 is supported by a timer instance.
2703 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2704 * @param TIMx Timer instance
2705 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2706 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2707 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2708 {
2709 return (uint32_t)(READ_REG(TIMx->CCR6));
2710 }
2711
2712 /**
2713 * @brief Select on which reference signal the OC5REF is combined to.
2714 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2715 * whether or not a timer instance supports the combined 3-phase PWM mode.
2716 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2717 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2718 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2719 * @param TIMx Timer instance
2720 * @param GroupCH5 This parameter can be a combination of the following values:
2721 * @arg @ref LL_TIM_GROUPCH5_NONE
2722 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2723 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2724 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2725 * @retval None
2726 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2727 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2728 {
2729 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2730 }
2731
2732 /**
2733 * @}
2734 */
2735
2736 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2737 * @{
2738 */
2739 /**
2740 * @brief Configure input channel.
2741 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2742 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2743 * CCMR1 IC1F LL_TIM_IC_Config\n
2744 * CCMR1 CC2S LL_TIM_IC_Config\n
2745 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2746 * CCMR1 IC2F LL_TIM_IC_Config\n
2747 * CCMR2 CC3S LL_TIM_IC_Config\n
2748 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2749 * CCMR2 IC3F LL_TIM_IC_Config\n
2750 * CCMR2 CC4S LL_TIM_IC_Config\n
2751 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2752 * CCMR2 IC4F LL_TIM_IC_Config\n
2753 * CCER CC1P LL_TIM_IC_Config\n
2754 * CCER CC1NP LL_TIM_IC_Config\n
2755 * CCER CC2P LL_TIM_IC_Config\n
2756 * CCER CC2NP LL_TIM_IC_Config\n
2757 * CCER CC3P LL_TIM_IC_Config\n
2758 * CCER CC3NP LL_TIM_IC_Config\n
2759 * CCER CC4P LL_TIM_IC_Config\n
2760 * CCER CC4NP LL_TIM_IC_Config
2761 * @param TIMx Timer instance
2762 * @param Channel This parameter can be one of the following values:
2763 * @arg @ref LL_TIM_CHANNEL_CH1
2764 * @arg @ref LL_TIM_CHANNEL_CH2
2765 * @arg @ref LL_TIM_CHANNEL_CH3
2766 * @arg @ref LL_TIM_CHANNEL_CH4
2767 * @param Configuration This parameter must be a combination of all the following values:
2768 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2769 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2770 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2771 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2772 * @retval None
2773 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2774 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2775 {
2776 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2777 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2778 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2779 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2780 << SHIFT_TAB_ICxx[iChannel]);
2781 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2782 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2783 }
2784
2785 /**
2786 * @brief Set the active input.
2787 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2788 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2789 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2790 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2791 * @param TIMx Timer instance
2792 * @param Channel This parameter can be one of the following values:
2793 * @arg @ref LL_TIM_CHANNEL_CH1
2794 * @arg @ref LL_TIM_CHANNEL_CH2
2795 * @arg @ref LL_TIM_CHANNEL_CH3
2796 * @arg @ref LL_TIM_CHANNEL_CH4
2797 * @param ICActiveInput This parameter can be one of the following values:
2798 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2799 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2800 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2801 * @retval None
2802 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2803 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2804 {
2805 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2806 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2807 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2808 }
2809
2810 /**
2811 * @brief Get the current active input.
2812 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2813 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2814 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2815 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2816 * @param TIMx Timer instance
2817 * @param Channel This parameter can be one of the following values:
2818 * @arg @ref LL_TIM_CHANNEL_CH1
2819 * @arg @ref LL_TIM_CHANNEL_CH2
2820 * @arg @ref LL_TIM_CHANNEL_CH3
2821 * @arg @ref LL_TIM_CHANNEL_CH4
2822 * @retval Returned value can be one of the following values:
2823 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2824 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2825 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2826 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2827 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2828 {
2829 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2830 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2831 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2832 }
2833
2834 /**
2835 * @brief Set the prescaler of input channel.
2836 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2837 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2838 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2839 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2840 * @param TIMx Timer instance
2841 * @param Channel This parameter can be one of the following values:
2842 * @arg @ref LL_TIM_CHANNEL_CH1
2843 * @arg @ref LL_TIM_CHANNEL_CH2
2844 * @arg @ref LL_TIM_CHANNEL_CH3
2845 * @arg @ref LL_TIM_CHANNEL_CH4
2846 * @param ICPrescaler This parameter can be one of the following values:
2847 * @arg @ref LL_TIM_ICPSC_DIV1
2848 * @arg @ref LL_TIM_ICPSC_DIV2
2849 * @arg @ref LL_TIM_ICPSC_DIV4
2850 * @arg @ref LL_TIM_ICPSC_DIV8
2851 * @retval None
2852 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2853 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2854 {
2855 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2856 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2857 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2858 }
2859
2860 /**
2861 * @brief Get the current prescaler value acting on an input channel.
2862 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2863 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2864 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2865 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2866 * @param TIMx Timer instance
2867 * @param Channel This parameter can be one of the following values:
2868 * @arg @ref LL_TIM_CHANNEL_CH1
2869 * @arg @ref LL_TIM_CHANNEL_CH2
2870 * @arg @ref LL_TIM_CHANNEL_CH3
2871 * @arg @ref LL_TIM_CHANNEL_CH4
2872 * @retval Returned value can be one of the following values:
2873 * @arg @ref LL_TIM_ICPSC_DIV1
2874 * @arg @ref LL_TIM_ICPSC_DIV2
2875 * @arg @ref LL_TIM_ICPSC_DIV4
2876 * @arg @ref LL_TIM_ICPSC_DIV8
2877 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2878 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2879 {
2880 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2881 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2882 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2883 }
2884
2885 /**
2886 * @brief Set the input filter duration.
2887 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2888 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2889 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2890 * CCMR2 IC4F LL_TIM_IC_SetFilter
2891 * @param TIMx Timer instance
2892 * @param Channel This parameter can be one of the following values:
2893 * @arg @ref LL_TIM_CHANNEL_CH1
2894 * @arg @ref LL_TIM_CHANNEL_CH2
2895 * @arg @ref LL_TIM_CHANNEL_CH3
2896 * @arg @ref LL_TIM_CHANNEL_CH4
2897 * @param ICFilter This parameter can be one of the following values:
2898 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2899 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2900 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2901 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2902 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2903 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2904 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2905 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2906 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2907 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2908 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2909 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2910 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2911 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2912 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2913 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2914 * @retval None
2915 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2916 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2917 {
2918 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2919 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2920 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2921 }
2922
2923 /**
2924 * @brief Get the input filter duration.
2925 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2926 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2927 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2928 * CCMR2 IC4F LL_TIM_IC_GetFilter
2929 * @param TIMx Timer instance
2930 * @param Channel This parameter can be one of the following values:
2931 * @arg @ref LL_TIM_CHANNEL_CH1
2932 * @arg @ref LL_TIM_CHANNEL_CH2
2933 * @arg @ref LL_TIM_CHANNEL_CH3
2934 * @arg @ref LL_TIM_CHANNEL_CH4
2935 * @retval Returned value can be one of the following values:
2936 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2937 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2938 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2939 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2940 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2941 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2942 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2943 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2944 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2945 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2946 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2947 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2948 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2949 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2950 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2951 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2952 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2953 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2954 {
2955 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2956 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2957 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2958 }
2959
2960 /**
2961 * @brief Set the input channel polarity.
2962 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2963 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2964 * CCER CC2P LL_TIM_IC_SetPolarity\n
2965 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2966 * CCER CC3P LL_TIM_IC_SetPolarity\n
2967 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2968 * CCER CC4P LL_TIM_IC_SetPolarity\n
2969 * CCER CC4NP LL_TIM_IC_SetPolarity
2970 * @param TIMx Timer instance
2971 * @param Channel This parameter can be one of the following values:
2972 * @arg @ref LL_TIM_CHANNEL_CH1
2973 * @arg @ref LL_TIM_CHANNEL_CH2
2974 * @arg @ref LL_TIM_CHANNEL_CH3
2975 * @arg @ref LL_TIM_CHANNEL_CH4
2976 * @param ICPolarity This parameter can be one of the following values:
2977 * @arg @ref LL_TIM_IC_POLARITY_RISING
2978 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2979 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2980 * @retval None
2981 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2982 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2983 {
2984 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2985 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2986 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2987 }
2988
2989 /**
2990 * @brief Get the current input channel polarity.
2991 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2992 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2993 * CCER CC2P LL_TIM_IC_GetPolarity\n
2994 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2995 * CCER CC3P LL_TIM_IC_GetPolarity\n
2996 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2997 * CCER CC4P LL_TIM_IC_GetPolarity\n
2998 * CCER CC4NP LL_TIM_IC_GetPolarity
2999 * @param TIMx Timer instance
3000 * @param Channel This parameter can be one of the following values:
3001 * @arg @ref LL_TIM_CHANNEL_CH1
3002 * @arg @ref LL_TIM_CHANNEL_CH2
3003 * @arg @ref LL_TIM_CHANNEL_CH3
3004 * @arg @ref LL_TIM_CHANNEL_CH4
3005 * @retval Returned value can be one of the following values:
3006 * @arg @ref LL_TIM_IC_POLARITY_RISING
3007 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3008 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3009 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3010 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3011 {
3012 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3013 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3014 SHIFT_TAB_CCxP[iChannel]);
3015 }
3016
3017 /**
3018 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3019 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3020 * a timer instance provides an XOR input.
3021 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3022 * @param TIMx Timer instance
3023 * @retval None
3024 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3025 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3026 {
3027 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3028 }
3029
3030 /**
3031 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3032 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3033 * a timer instance provides an XOR input.
3034 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3035 * @param TIMx Timer instance
3036 * @retval None
3037 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3038 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3039 {
3040 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3041 }
3042
3043 /**
3044 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3045 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3046 * a timer instance provides an XOR input.
3047 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3048 * @param TIMx Timer instance
3049 * @retval State of bit (1 or 0).
3050 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3051 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3052 {
3053 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3054 }
3055
3056 /**
3057 * @brief Get captured value for input channel 1.
3058 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3059 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3060 * whether or not a timer instance supports a 32 bits counter.
3061 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3062 * input channel 1 is supported by a timer instance.
3063 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3064 * @param TIMx Timer instance
3065 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3066 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3067 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3068 {
3069 return (uint32_t)(READ_REG(TIMx->CCR1));
3070 }
3071
3072 /**
3073 * @brief Get captured value for input channel 2.
3074 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3075 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3076 * whether or not a timer instance supports a 32 bits counter.
3077 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3078 * input channel 2 is supported by a timer instance.
3079 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3080 * @param TIMx Timer instance
3081 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3082 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3083 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3084 {
3085 return (uint32_t)(READ_REG(TIMx->CCR2));
3086 }
3087
3088 /**
3089 * @brief Get captured value for input channel 3.
3090 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3091 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3092 * whether or not a timer instance supports a 32 bits counter.
3093 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3094 * input channel 3 is supported by a timer instance.
3095 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3096 * @param TIMx Timer instance
3097 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3098 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3099 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3100 {
3101 return (uint32_t)(READ_REG(TIMx->CCR3));
3102 }
3103
3104 /**
3105 * @brief Get captured value for input channel 4.
3106 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3107 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3108 * whether or not a timer instance supports a 32 bits counter.
3109 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3110 * input channel 4 is supported by a timer instance.
3111 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3112 * @param TIMx Timer instance
3113 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3114 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3115 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3116 {
3117 return (uint32_t)(READ_REG(TIMx->CCR4));
3118 }
3119
3120 /**
3121 * @}
3122 */
3123
3124 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3125 * @{
3126 */
3127 /**
3128 * @brief Enable external clock mode 2.
3129 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3130 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3131 * whether or not a timer instance supports external clock mode2.
3132 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3133 * @param TIMx Timer instance
3134 * @retval None
3135 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3136 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3137 {
3138 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3139 }
3140
3141 /**
3142 * @brief Disable external clock mode 2.
3143 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3144 * whether or not a timer instance supports external clock mode2.
3145 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3146 * @param TIMx Timer instance
3147 * @retval None
3148 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3149 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3150 {
3151 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3152 }
3153
3154 /**
3155 * @brief Indicate whether external clock mode 2 is enabled.
3156 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3157 * whether or not a timer instance supports external clock mode2.
3158 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3159 * @param TIMx Timer instance
3160 * @retval State of bit (1 or 0).
3161 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3162 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3163 {
3164 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3165 }
3166
3167 /**
3168 * @brief Set the clock source of the counter clock.
3169 * @note when selected clock source is external clock mode 1, the timer input
3170 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3171 * function. This timer input must be configured by calling
3172 * the @ref LL_TIM_IC_Config() function.
3173 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3174 * whether or not a timer instance supports external clock mode1.
3175 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3176 * whether or not a timer instance supports external clock mode2.
3177 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3178 * SMCR ECE LL_TIM_SetClockSource
3179 * @param TIMx Timer instance
3180 * @param ClockSource This parameter can be one of the following values:
3181 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3182 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3183 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3184 * @retval None
3185 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3186 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3187 {
3188 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3189 }
3190
3191 /**
3192 * @brief Set the encoder interface mode.
3193 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3194 * whether or not a timer instance supports the encoder mode.
3195 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3196 * @param TIMx Timer instance
3197 * @param EncoderMode This parameter can be one of the following values:
3198 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3199 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3200 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3201 * @retval None
3202 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3203 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3204 {
3205 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3206 }
3207
3208 /**
3209 * @}
3210 */
3211
3212 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3213 * @{
3214 */
3215 /**
3216 * @brief Set the trigger output (TRGO) used for timer synchronization .
3217 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3218 * whether or not a timer instance can operate as a master timer.
3219 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3220 * @param TIMx Timer instance
3221 * @param TimerSynchronization This parameter can be one of the following values:
3222 * @arg @ref LL_TIM_TRGO_RESET
3223 * @arg @ref LL_TIM_TRGO_ENABLE
3224 * @arg @ref LL_TIM_TRGO_UPDATE
3225 * @arg @ref LL_TIM_TRGO_CC1IF
3226 * @arg @ref LL_TIM_TRGO_OC1REF
3227 * @arg @ref LL_TIM_TRGO_OC2REF
3228 * @arg @ref LL_TIM_TRGO_OC3REF
3229 * @arg @ref LL_TIM_TRGO_OC4REF
3230 * @retval None
3231 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3232 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3233 {
3234 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3235 }
3236
3237 /**
3238 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3239 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3240 * whether or not a timer instance can be used for ADC synchronization.
3241 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3242 * @param TIMx Timer Instance
3243 * @param ADCSynchronization This parameter can be one of the following values:
3244 * @arg @ref LL_TIM_TRGO2_RESET
3245 * @arg @ref LL_TIM_TRGO2_ENABLE
3246 * @arg @ref LL_TIM_TRGO2_UPDATE
3247 * @arg @ref LL_TIM_TRGO2_CC1F
3248 * @arg @ref LL_TIM_TRGO2_OC1
3249 * @arg @ref LL_TIM_TRGO2_OC2
3250 * @arg @ref LL_TIM_TRGO2_OC3
3251 * @arg @ref LL_TIM_TRGO2_OC4
3252 * @arg @ref LL_TIM_TRGO2_OC5
3253 * @arg @ref LL_TIM_TRGO2_OC6
3254 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3255 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3256 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3257 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3258 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3259 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3260 * @retval None
3261 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3262 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3263 {
3264 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3265 }
3266
3267 /**
3268 * @brief Set the synchronization mode of a slave timer.
3269 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3270 * a timer instance can operate as a slave timer.
3271 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3272 * @param TIMx Timer instance
3273 * @param SlaveMode This parameter can be one of the following values:
3274 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3275 * @arg @ref LL_TIM_SLAVEMODE_RESET
3276 * @arg @ref LL_TIM_SLAVEMODE_GATED
3277 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3278 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3279 * @retval None
3280 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3281 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3282 {
3283 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3284 }
3285
3286 /**
3287 * @brief Set the selects the trigger input to be used to synchronize the counter.
3288 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3289 * a timer instance can operate as a slave timer.
3290 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3291 * @param TIMx Timer instance
3292 * @param TriggerInput This parameter can be one of the following values:
3293 * @arg @ref LL_TIM_TS_ITR0
3294 * @arg @ref LL_TIM_TS_ITR1
3295 * @arg @ref LL_TIM_TS_ITR2
3296 * @arg @ref LL_TIM_TS_ITR3
3297 * @arg @ref LL_TIM_TS_TI1F_ED
3298 * @arg @ref LL_TIM_TS_TI1FP1
3299 * @arg @ref LL_TIM_TS_TI2FP2
3300 * @arg @ref LL_TIM_TS_ETRF
3301 * @retval None
3302 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3303 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3304 {
3305 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3306 }
3307
3308 /**
3309 * @brief Enable the Master/Slave mode.
3310 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3311 * a timer instance can operate as a slave timer.
3312 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3313 * @param TIMx Timer instance
3314 * @retval None
3315 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3316 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3317 {
3318 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3319 }
3320
3321 /**
3322 * @brief Disable the Master/Slave mode.
3323 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3324 * a timer instance can operate as a slave timer.
3325 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3326 * @param TIMx Timer instance
3327 * @retval None
3328 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3329 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3330 {
3331 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3332 }
3333
3334 /**
3335 * @brief Indicates whether the Master/Slave mode is enabled.
3336 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3337 * a timer instance can operate as a slave timer.
3338 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3339 * @param TIMx Timer instance
3340 * @retval State of bit (1 or 0).
3341 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3342 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3343 {
3344 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3345 }
3346
3347 /**
3348 * @brief Configure the external trigger (ETR) input.
3349 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3350 * a timer instance provides an external trigger input.
3351 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3352 * SMCR ETPS LL_TIM_ConfigETR\n
3353 * SMCR ETF LL_TIM_ConfigETR
3354 * @param TIMx Timer instance
3355 * @param ETRPolarity This parameter can be one of the following values:
3356 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3357 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3358 * @param ETRPrescaler This parameter can be one of the following values:
3359 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3360 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3361 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3362 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3363 * @param ETRFilter This parameter can be one of the following values:
3364 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3365 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3366 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3367 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3368 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3369 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3370 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3371 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3372 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3373 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3374 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3375 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3376 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3377 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3378 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3379 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3380 * @retval None
3381 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3382 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3383 uint32_t ETRFilter)
3384 {
3385 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3386 }
3387
3388 /**
3389 * @brief Select the external trigger (ETR) input source.
3390 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3391 * not a timer instance supports ETR source selection.
3392 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3393 * @param TIMx Timer instance
3394 * @param ETRSource This parameter can be one of the following values:
3395 * @arg @ref LL_TIM_ETRSOURCE_LEGACY
3396 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3397 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3398 * @retval None
3399 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3400 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3401 {
3402 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3403 }
3404
3405 /**
3406 * @}
3407 */
3408
3409 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3410 * @{
3411 */
3412 /**
3413 * @brief Enable the break function.
3414 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3415 * a timer instance provides a break input.
3416 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3417 * @param TIMx Timer instance
3418 * @retval None
3419 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3420 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3421 {
3422 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3423 }
3424
3425 /**
3426 * @brief Disable the break function.
3427 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3428 * @param TIMx Timer instance
3429 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3430 * a timer instance provides a break input.
3431 * @retval None
3432 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3433 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3434 {
3435 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3436 }
3437
3438 /**
3439 * @brief Configure the break input.
3440 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3441 * a timer instance provides a break input.
3442 * @note Bidirectional mode is only supported by advanced timer instances.
3443 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3444 * a timer instance is an advanced-control timer.
3445 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3446 * in input mode and in open drain output mode. Any active Break event will
3447 * assert a low logic level on the Break input to indicate an internal break
3448 * event to external devices.
3449 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3450 * LL_TIM_BREAK_AFMODE_INPUT.
3451 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3452 * BDTR BKF LL_TIM_ConfigBRK\n
3453 * BDTR BKBID LL_TIM_ConfigBRK
3454 * @param TIMx Timer instance
3455 * @param BreakPolarity This parameter can be one of the following values:
3456 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3457 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3458 * @param BreakFilter This parameter can be one of the following values:
3459 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3460 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3461 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3462 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3463 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3464 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3465 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3466 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3467 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3468 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3469 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3470 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3471 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3472 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3473 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3474 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3475 * @param BreakAFMode This parameter can be one of the following values:
3476 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3477 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3478 * @retval None
3479 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3480 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3481 uint32_t BreakAFMode)
3482 {
3483 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3484 }
3485
3486 /**
3487 * @brief Disarm the break input (when it operates in bidirectional mode).
3488 * @note The break input can be disarmed only when it is configured in
3489 * bidirectional mode and when when MOE is reset.
3490 * @note Purpose is to be able to have the input voltage back to high-state,
3491 * whatever the time constant on the output .
3492 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3493 * @param TIMx Timer instance
3494 * @retval None
3495 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3496 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3497 {
3498 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3499 }
3500
3501 /**
3502 * @brief Re-arm the break input (when it operates in bidirectional mode).
3503 * @note The Break input is automatically armed as soon as MOE bit is set.
3504 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3505 * @param TIMx Timer instance
3506 * @retval None
3507 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3508 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3509 {
3510 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3511 }
3512
3513 /**
3514 * @brief Enable the break 2 function.
3515 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3516 * a timer instance provides a second break input.
3517 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3518 * @param TIMx Timer instance
3519 * @retval None
3520 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3521 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3522 {
3523 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3524 }
3525
3526 /**
3527 * @brief Disable the break 2 function.
3528 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3529 * a timer instance provides a second break input.
3530 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3531 * @param TIMx Timer instance
3532 * @retval None
3533 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3534 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3535 {
3536 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3537 }
3538
3539 /**
3540 * @brief Configure the break 2 input.
3541 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3542 * a timer instance provides a second break input.
3543 * @note Bidirectional mode is only supported by advanced timer instances.
3544 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3545 * a timer instance is an advanced-control timer.
3546 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3547 * in input mode and in open drain output mode. Any active Break event will
3548 * assert a low logic level on the Break 2 input to indicate an internal break
3549 * event to external devices.
3550 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3551 * LL_TIM_BREAK2_AFMODE_INPUT.
3552 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3553 * BDTR BK2F LL_TIM_ConfigBRK2\n
3554 * BDTR BK2BID LL_TIM_ConfigBRK2
3555 * @param TIMx Timer instance
3556 * @param Break2Polarity This parameter can be one of the following values:
3557 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3558 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3559 * @param Break2Filter This parameter can be one of the following values:
3560 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3561 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3562 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3563 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3564 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3565 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3566 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3567 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3568 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3569 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3570 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3571 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3572 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3573 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3574 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3575 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3576 * @param Break2AFMode This parameter can be one of the following values:
3577 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3578 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3579 * @retval None
3580 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3581 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3582 uint32_t Break2AFMode)
3583 {
3584 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3585 }
3586
3587 /**
3588 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3589 * @note The break 2 input can be disarmed only when it is configured in
3590 * bidirectional mode and when when MOE is reset.
3591 * @note Purpose is to be able to have the input voltage back to high-state,
3592 * whatever the time constant on the output.
3593 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3594 * @param TIMx Timer instance
3595 * @retval None
3596 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3597 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3598 {
3599 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3600 }
3601
3602 /**
3603 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3604 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3605 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3606 * @param TIMx Timer instance
3607 * @retval None
3608 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3609 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3610 {
3611 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3612 }
3613
3614 /**
3615 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3616 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3617 * a timer instance provides a break input.
3618 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3619 * BDTR OSSR LL_TIM_SetOffStates
3620 * @param TIMx Timer instance
3621 * @param OffStateIdle This parameter can be one of the following values:
3622 * @arg @ref LL_TIM_OSSI_DISABLE
3623 * @arg @ref LL_TIM_OSSI_ENABLE
3624 * @param OffStateRun This parameter can be one of the following values:
3625 * @arg @ref LL_TIM_OSSR_DISABLE
3626 * @arg @ref LL_TIM_OSSR_ENABLE
3627 * @retval None
3628 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3629 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3630 {
3631 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3632 }
3633
3634 /**
3635 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3636 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3637 * a timer instance provides a break input.
3638 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3639 * @param TIMx Timer instance
3640 * @retval None
3641 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3642 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3643 {
3644 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3645 }
3646
3647 /**
3648 * @brief Disable automatic output (MOE can be set only by software).
3649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3650 * a timer instance provides a break input.
3651 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3652 * @param TIMx Timer instance
3653 * @retval None
3654 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3655 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3656 {
3657 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3658 }
3659
3660 /**
3661 * @brief Indicate whether automatic output is enabled.
3662 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3663 * a timer instance provides a break input.
3664 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3665 * @param TIMx Timer instance
3666 * @retval State of bit (1 or 0).
3667 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3668 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3669 {
3670 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3671 }
3672
3673 /**
3674 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3675 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3676 * software and is reset in case of break or break2 event
3677 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3678 * a timer instance provides a break input.
3679 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3680 * @param TIMx Timer instance
3681 * @retval None
3682 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3683 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3684 {
3685 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3686 }
3687
3688 /**
3689 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3690 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3691 * software and is reset in case of break or break2 event.
3692 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3693 * a timer instance provides a break input.
3694 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3695 * @param TIMx Timer instance
3696 * @retval None
3697 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3698 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3699 {
3700 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3701 }
3702
3703 /**
3704 * @brief Indicates whether outputs are enabled.
3705 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3706 * a timer instance provides a break input.
3707 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3708 * @param TIMx Timer instance
3709 * @retval State of bit (1 or 0).
3710 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3711 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3712 {
3713 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3714 }
3715
3716 /**
3717 * @brief Enable the signals connected to the designated timer break input.
3718 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3719 * or not a timer instance allows for break input selection.
3720 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3721 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3722 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3723 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3724 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3725 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3726 * @param TIMx Timer instance
3727 * @param BreakInput This parameter can be one of the following values:
3728 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3729 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3730 * @param Source This parameter can be one of the following values:
3731 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3732 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3733 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3734 * @retval None
3735 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3736 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3737 {
3738 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3739 SET_BIT(*pReg, Source);
3740 }
3741
3742 /**
3743 * @brief Disable the signals connected to the designated timer break input.
3744 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3745 * or not a timer instance allows for break input selection.
3746 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3747 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3748 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3749 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3750 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3751 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3752 * @param TIMx Timer instance
3753 * @param BreakInput This parameter can be one of the following values:
3754 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3755 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3756 * @param Source This parameter can be one of the following values:
3757 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3758 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3759 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3760 * @retval None
3761 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3762 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3763 {
3764 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3765 CLEAR_BIT(*pReg, Source);
3766 }
3767
3768 /**
3769 * @brief Set the polarity of the break signal for the timer break input.
3770 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3771 * or not a timer instance allows for break input selection.
3772 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3773 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3774 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3775 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3776 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3777 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3778 * @param TIMx Timer instance
3779 * @param BreakInput This parameter can be one of the following values:
3780 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3781 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3782 * @param Source This parameter can be one of the following values:
3783 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3784 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3785 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3786 * @param Polarity This parameter can be one of the following values:
3787 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3788 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3789 * @retval None
3790 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3791 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3792 uint32_t Polarity)
3793 {
3794 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3795 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3796 }
3797 /**
3798 * @}
3799 */
3800
3801 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3802 * @{
3803 */
3804 /**
3805 * @brief Configures the timer DMA burst feature.
3806 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3807 * not a timer instance supports the DMA burst mode.
3808 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3809 * DCR DBA LL_TIM_ConfigDMABurst
3810 * @param TIMx Timer instance
3811 * @param DMABurstBaseAddress This parameter can be one of the following values:
3812 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3813 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3814 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3815 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3816 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3817 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3818 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3819 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3820 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3821 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3822 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3823 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3824 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3825 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3826 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3827 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3828 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3829 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3830 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3831 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3832 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3833 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3834 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3835 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3836 * @param DMABurstLength This parameter can be one of the following values:
3837 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3838 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3839 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3840 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3841 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3842 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3843 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3844 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3845 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3846 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3847 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3848 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3849 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3850 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3851 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3852 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3853 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3854 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3855 * @retval None
3856 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3857 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3858 {
3859 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3860 }
3861
3862 /**
3863 * @}
3864 */
3865
3866 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3867 * @{
3868 */
3869 /**
3870 * @brief Remap TIM inputs (input channel, internal/external triggers).
3871 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3872 * a some timer inputs can be remapped.
3873 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3874 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3875 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3876 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3877 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3878 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3879 * @param TIMx Timer instance
3880 * @param Remap Remap param depends on the TIMx. Description available only
3881 * in CHM version of the User Manual (not in .pdf).
3882 * Otherwise see Reference Manual description of OR1 registers.
3883 *
3884 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3885 *
3886 * TIM1: any combination of TI1_RMP, ETR_ADC_RMP where
3887 *
3888 * . . ETR_ADC_RMP can be one of the following values
3889 * @arg @ref LL_TIM_TIM1_ETR_ADC_RMP_NC
3890 * @arg @ref LL_TIM_TIM1_ETR_ADC_RMP_AWD1
3891 * @arg @ref LL_TIM_TIM1_ETR_ADC_RMP_AWD2
3892 * @arg @ref LL_TIM_TIM1_ETR_ADC_RMP_AWD3
3893 *
3894 * . . TI1_RMP can be one of the following values
3895 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3896 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3897 *
3898 * TIM2: any combination of ETR_RMP, TI4_RMP where
3899 *
3900 * . . ETR_RMP can be one of the following values
3901 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3902 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3903 *
3904 * . . TI4_RMP can be one of the following values
3905 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3906 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3907 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3908 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3909 *
3910 * TIM16: one of the following values
3911 *
3912 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3913 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3914 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3915 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3916 *
3917 * TIM17: one of the following values
3918 *
3919 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3920 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3921 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3922 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3923 * @retval None
3924 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3925 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3926 {
3927 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
3928 }
3929
3930 /**
3931 * @}
3932 */
3933
3934 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3935 * @{
3936 */
3937 /**
3938 * @brief Set the OCREF clear input source
3939 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3940 * @note This function can only be used in Output compare and PWM modes.
3941 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3942 * @param TIMx Timer instance
3943 * @param OCRefClearInputSource This parameter can be one of the following values:
3944 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3945 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3946 * @retval None
3947 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3948 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3949 {
3950 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3951 }
3952 /**
3953 * @}
3954 */
3955
3956 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3957 * @{
3958 */
3959 /**
3960 * @brief Clear the update interrupt flag (UIF).
3961 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3962 * @param TIMx Timer instance
3963 * @retval None
3964 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3965 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3966 {
3967 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3968 }
3969
3970 /**
3971 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3972 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3973 * @param TIMx Timer instance
3974 * @retval State of bit (1 or 0).
3975 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3976 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3977 {
3978 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3979 }
3980
3981 /**
3982 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3983 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3984 * @param TIMx Timer instance
3985 * @retval None
3986 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3987 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3988 {
3989 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3990 }
3991
3992 /**
3993 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3994 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3995 * @param TIMx Timer instance
3996 * @retval State of bit (1 or 0).
3997 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3998 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3999 {
4000 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4001 }
4002
4003 /**
4004 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4005 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4006 * @param TIMx Timer instance
4007 * @retval None
4008 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4009 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4010 {
4011 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4012 }
4013
4014 /**
4015 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4016 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4017 * @param TIMx Timer instance
4018 * @retval State of bit (1 or 0).
4019 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4020 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4021 {
4022 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4023 }
4024
4025 /**
4026 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4027 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4028 * @param TIMx Timer instance
4029 * @retval None
4030 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4031 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4032 {
4033 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4034 }
4035
4036 /**
4037 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4038 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4039 * @param TIMx Timer instance
4040 * @retval State of bit (1 or 0).
4041 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4042 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4043 {
4044 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4045 }
4046
4047 /**
4048 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4049 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4050 * @param TIMx Timer instance
4051 * @retval None
4052 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4053 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4054 {
4055 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4056 }
4057
4058 /**
4059 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4060 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4061 * @param TIMx Timer instance
4062 * @retval State of bit (1 or 0).
4063 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4064 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4065 {
4066 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4067 }
4068
4069 /**
4070 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4071 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4072 * @param TIMx Timer instance
4073 * @retval None
4074 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4075 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4076 {
4077 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4078 }
4079
4080 /**
4081 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4082 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4083 * @param TIMx Timer instance
4084 * @retval State of bit (1 or 0).
4085 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4086 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4087 {
4088 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4089 }
4090
4091 /**
4092 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4093 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4094 * @param TIMx Timer instance
4095 * @retval None
4096 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4097 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4098 {
4099 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4100 }
4101
4102 /**
4103 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4104 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4105 * @param TIMx Timer instance
4106 * @retval State of bit (1 or 0).
4107 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4108 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4109 {
4110 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4111 }
4112
4113 /**
4114 * @brief Clear the commutation interrupt flag (COMIF).
4115 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4116 * @param TIMx Timer instance
4117 * @retval None
4118 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4119 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4120 {
4121 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4122 }
4123
4124 /**
4125 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4126 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4127 * @param TIMx Timer instance
4128 * @retval State of bit (1 or 0).
4129 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4130 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4131 {
4132 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4133 }
4134
4135 /**
4136 * @brief Clear the trigger interrupt flag (TIF).
4137 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4138 * @param TIMx Timer instance
4139 * @retval None
4140 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4141 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4142 {
4143 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4144 }
4145
4146 /**
4147 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4148 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4149 * @param TIMx Timer instance
4150 * @retval State of bit (1 or 0).
4151 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4152 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4153 {
4154 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4155 }
4156
4157 /**
4158 * @brief Clear the break interrupt flag (BIF).
4159 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4160 * @param TIMx Timer instance
4161 * @retval None
4162 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4163 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4164 {
4165 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4166 }
4167
4168 /**
4169 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4170 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4171 * @param TIMx Timer instance
4172 * @retval State of bit (1 or 0).
4173 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4174 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4175 {
4176 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4177 }
4178
4179 /**
4180 * @brief Clear the break 2 interrupt flag (B2IF).
4181 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4182 * @param TIMx Timer instance
4183 * @retval None
4184 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4185 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4186 {
4187 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4188 }
4189
4190 /**
4191 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4192 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4193 * @param TIMx Timer instance
4194 * @retval State of bit (1 or 0).
4195 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4196 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4197 {
4198 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4199 }
4200
4201 /**
4202 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4203 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4204 * @param TIMx Timer instance
4205 * @retval None
4206 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4207 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4208 {
4209 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4210 }
4211
4212 /**
4213 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4214 * (Capture/Compare 1 interrupt is pending).
4215 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4216 * @param TIMx Timer instance
4217 * @retval State of bit (1 or 0).
4218 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4219 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4220 {
4221 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4222 }
4223
4224 /**
4225 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4226 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4227 * @param TIMx Timer instance
4228 * @retval None
4229 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4230 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4231 {
4232 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4233 }
4234
4235 /**
4236 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4237 * (Capture/Compare 2 over-capture interrupt is pending).
4238 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4239 * @param TIMx Timer instance
4240 * @retval State of bit (1 or 0).
4241 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4242 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4243 {
4244 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4245 }
4246
4247 /**
4248 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4249 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4250 * @param TIMx Timer instance
4251 * @retval None
4252 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4253 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4254 {
4255 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4256 }
4257
4258 /**
4259 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4260 * (Capture/Compare 3 over-capture interrupt is pending).
4261 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4262 * @param TIMx Timer instance
4263 * @retval State of bit (1 or 0).
4264 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4265 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4266 {
4267 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4268 }
4269
4270 /**
4271 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4272 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4273 * @param TIMx Timer instance
4274 * @retval None
4275 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4276 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4277 {
4278 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4279 }
4280
4281 /**
4282 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4283 * (Capture/Compare 4 over-capture interrupt is pending).
4284 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4285 * @param TIMx Timer instance
4286 * @retval State of bit (1 or 0).
4287 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4288 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4289 {
4290 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4291 }
4292
4293 /**
4294 * @brief Clear the system break interrupt flag (SBIF).
4295 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4296 * @param TIMx Timer instance
4297 * @retval None
4298 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4299 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4300 {
4301 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4302 }
4303
4304 /**
4305 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4306 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4307 * @param TIMx Timer instance
4308 * @retval State of bit (1 or 0).
4309 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4310 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4311 {
4312 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4313 }
4314
4315 /**
4316 * @}
4317 */
4318
4319 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4320 * @{
4321 */
4322 /**
4323 * @brief Enable update interrupt (UIE).
4324 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4325 * @param TIMx Timer instance
4326 * @retval None
4327 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4328 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4329 {
4330 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4331 }
4332
4333 /**
4334 * @brief Disable update interrupt (UIE).
4335 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4336 * @param TIMx Timer instance
4337 * @retval None
4338 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4339 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4340 {
4341 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4342 }
4343
4344 /**
4345 * @brief Indicates whether the update interrupt (UIE) is enabled.
4346 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4347 * @param TIMx Timer instance
4348 * @retval State of bit (1 or 0).
4349 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4350 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4351 {
4352 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4353 }
4354
4355 /**
4356 * @brief Enable capture/compare 1 interrupt (CC1IE).
4357 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4358 * @param TIMx Timer instance
4359 * @retval None
4360 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4361 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4362 {
4363 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4364 }
4365
4366 /**
4367 * @brief Disable capture/compare 1 interrupt (CC1IE).
4368 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4369 * @param TIMx Timer instance
4370 * @retval None
4371 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4372 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4373 {
4374 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4375 }
4376
4377 /**
4378 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4379 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4380 * @param TIMx Timer instance
4381 * @retval State of bit (1 or 0).
4382 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4383 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4384 {
4385 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4386 }
4387
4388 /**
4389 * @brief Enable capture/compare 2 interrupt (CC2IE).
4390 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4391 * @param TIMx Timer instance
4392 * @retval None
4393 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4394 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4395 {
4396 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4397 }
4398
4399 /**
4400 * @brief Disable capture/compare 2 interrupt (CC2IE).
4401 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4402 * @param TIMx Timer instance
4403 * @retval None
4404 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4405 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4406 {
4407 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4408 }
4409
4410 /**
4411 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4412 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4413 * @param TIMx Timer instance
4414 * @retval State of bit (1 or 0).
4415 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4416 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4417 {
4418 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4419 }
4420
4421 /**
4422 * @brief Enable capture/compare 3 interrupt (CC3IE).
4423 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4424 * @param TIMx Timer instance
4425 * @retval None
4426 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4427 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4428 {
4429 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4430 }
4431
4432 /**
4433 * @brief Disable capture/compare 3 interrupt (CC3IE).
4434 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4435 * @param TIMx Timer instance
4436 * @retval None
4437 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4438 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4439 {
4440 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4441 }
4442
4443 /**
4444 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4445 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4446 * @param TIMx Timer instance
4447 * @retval State of bit (1 or 0).
4448 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4449 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4450 {
4451 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4452 }
4453
4454 /**
4455 * @brief Enable capture/compare 4 interrupt (CC4IE).
4456 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4457 * @param TIMx Timer instance
4458 * @retval None
4459 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4460 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4461 {
4462 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4463 }
4464
4465 /**
4466 * @brief Disable capture/compare 4 interrupt (CC4IE).
4467 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4468 * @param TIMx Timer instance
4469 * @retval None
4470 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4471 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4472 {
4473 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4474 }
4475
4476 /**
4477 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4478 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4479 * @param TIMx Timer instance
4480 * @retval State of bit (1 or 0).
4481 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4482 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4483 {
4484 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4485 }
4486
4487 /**
4488 * @brief Enable commutation interrupt (COMIE).
4489 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4490 * @param TIMx Timer instance
4491 * @retval None
4492 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4493 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4494 {
4495 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4496 }
4497
4498 /**
4499 * @brief Disable commutation interrupt (COMIE).
4500 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4501 * @param TIMx Timer instance
4502 * @retval None
4503 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4504 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4505 {
4506 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4507 }
4508
4509 /**
4510 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4511 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4512 * @param TIMx Timer instance
4513 * @retval State of bit (1 or 0).
4514 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4516 {
4517 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4518 }
4519
4520 /**
4521 * @brief Enable trigger interrupt (TIE).
4522 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4523 * @param TIMx Timer instance
4524 * @retval None
4525 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4526 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4527 {
4528 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4529 }
4530
4531 /**
4532 * @brief Disable trigger interrupt (TIE).
4533 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4534 * @param TIMx Timer instance
4535 * @retval None
4536 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4537 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4538 {
4539 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4540 }
4541
4542 /**
4543 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4544 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4545 * @param TIMx Timer instance
4546 * @retval State of bit (1 or 0).
4547 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4548 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4549 {
4550 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4551 }
4552
4553 /**
4554 * @brief Enable break interrupt (BIE).
4555 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4556 * @param TIMx Timer instance
4557 * @retval None
4558 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4559 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4560 {
4561 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4562 }
4563
4564 /**
4565 * @brief Disable break interrupt (BIE).
4566 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4567 * @param TIMx Timer instance
4568 * @retval None
4569 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4570 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4571 {
4572 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4573 }
4574
4575 /**
4576 * @brief Indicates whether the break interrupt (BIE) is enabled.
4577 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4578 * @param TIMx Timer instance
4579 * @retval State of bit (1 or 0).
4580 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4581 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4582 {
4583 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4584 }
4585
4586 /**
4587 * @}
4588 */
4589
4590 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4591 * @{
4592 */
4593 /**
4594 * @brief Enable update DMA request (UDE).
4595 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4596 * @param TIMx Timer instance
4597 * @retval None
4598 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4599 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4600 {
4601 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4602 }
4603
4604 /**
4605 * @brief Disable update DMA request (UDE).
4606 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4607 * @param TIMx Timer instance
4608 * @retval None
4609 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4610 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4611 {
4612 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4613 }
4614
4615 /**
4616 * @brief Indicates whether the update DMA request (UDE) is enabled.
4617 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4618 * @param TIMx Timer instance
4619 * @retval State of bit (1 or 0).
4620 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4621 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4622 {
4623 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4624 }
4625
4626 /**
4627 * @brief Enable capture/compare 1 DMA request (CC1DE).
4628 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4629 * @param TIMx Timer instance
4630 * @retval None
4631 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4632 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4633 {
4634 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4635 }
4636
4637 /**
4638 * @brief Disable capture/compare 1 DMA request (CC1DE).
4639 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4640 * @param TIMx Timer instance
4641 * @retval None
4642 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4643 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4644 {
4645 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4646 }
4647
4648 /**
4649 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4650 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4651 * @param TIMx Timer instance
4652 * @retval State of bit (1 or 0).
4653 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4654 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4655 {
4656 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4657 }
4658
4659 /**
4660 * @brief Enable capture/compare 2 DMA request (CC2DE).
4661 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4662 * @param TIMx Timer instance
4663 * @retval None
4664 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4665 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4666 {
4667 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4668 }
4669
4670 /**
4671 * @brief Disable capture/compare 2 DMA request (CC2DE).
4672 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4673 * @param TIMx Timer instance
4674 * @retval None
4675 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4676 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4677 {
4678 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4679 }
4680
4681 /**
4682 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4683 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4684 * @param TIMx Timer instance
4685 * @retval State of bit (1 or 0).
4686 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4687 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4688 {
4689 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4690 }
4691
4692 /**
4693 * @brief Enable capture/compare 3 DMA request (CC3DE).
4694 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4695 * @param TIMx Timer instance
4696 * @retval None
4697 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4698 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4699 {
4700 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4701 }
4702
4703 /**
4704 * @brief Disable capture/compare 3 DMA request (CC3DE).
4705 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4706 * @param TIMx Timer instance
4707 * @retval None
4708 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4709 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4710 {
4711 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4712 }
4713
4714 /**
4715 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4716 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4717 * @param TIMx Timer instance
4718 * @retval State of bit (1 or 0).
4719 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4720 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4721 {
4722 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4723 }
4724
4725 /**
4726 * @brief Enable capture/compare 4 DMA request (CC4DE).
4727 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4728 * @param TIMx Timer instance
4729 * @retval None
4730 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4731 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4732 {
4733 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4734 }
4735
4736 /**
4737 * @brief Disable capture/compare 4 DMA request (CC4DE).
4738 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4739 * @param TIMx Timer instance
4740 * @retval None
4741 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4742 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4743 {
4744 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4745 }
4746
4747 /**
4748 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4749 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4750 * @param TIMx Timer instance
4751 * @retval State of bit (1 or 0).
4752 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4753 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4754 {
4755 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4756 }
4757
4758 /**
4759 * @brief Enable commutation DMA request (COMDE).
4760 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4761 * @param TIMx Timer instance
4762 * @retval None
4763 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4764 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4765 {
4766 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4767 }
4768
4769 /**
4770 * @brief Disable commutation DMA request (COMDE).
4771 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4772 * @param TIMx Timer instance
4773 * @retval None
4774 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4775 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4776 {
4777 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4778 }
4779
4780 /**
4781 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4782 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4783 * @param TIMx Timer instance
4784 * @retval State of bit (1 or 0).
4785 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4786 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4787 {
4788 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4789 }
4790
4791 /**
4792 * @brief Enable trigger interrupt (TDE).
4793 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4794 * @param TIMx Timer instance
4795 * @retval None
4796 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4797 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4798 {
4799 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4800 }
4801
4802 /**
4803 * @brief Disable trigger interrupt (TDE).
4804 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4805 * @param TIMx Timer instance
4806 * @retval None
4807 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4808 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4809 {
4810 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4811 }
4812
4813 /**
4814 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4815 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4816 * @param TIMx Timer instance
4817 * @retval State of bit (1 or 0).
4818 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4820 {
4821 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4822 }
4823
4824 /**
4825 * @}
4826 */
4827
4828 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4829 * @{
4830 */
4831 /**
4832 * @brief Generate an update event.
4833 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4834 * @param TIMx Timer instance
4835 * @retval None
4836 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4837 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4838 {
4839 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4840 }
4841
4842 /**
4843 * @brief Generate Capture/Compare 1 event.
4844 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4845 * @param TIMx Timer instance
4846 * @retval None
4847 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4848 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4849 {
4850 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4851 }
4852
4853 /**
4854 * @brief Generate Capture/Compare 2 event.
4855 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4859 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4860 {
4861 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4862 }
4863
4864 /**
4865 * @brief Generate Capture/Compare 3 event.
4866 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4867 * @param TIMx Timer instance
4868 * @retval None
4869 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4870 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4871 {
4872 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4873 }
4874
4875 /**
4876 * @brief Generate Capture/Compare 4 event.
4877 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4881 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4882 {
4883 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4884 }
4885
4886 /**
4887 * @brief Generate commutation event.
4888 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4889 * @param TIMx Timer instance
4890 * @retval None
4891 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4892 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4893 {
4894 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4895 }
4896
4897 /**
4898 * @brief Generate trigger event.
4899 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4900 * @param TIMx Timer instance
4901 * @retval None
4902 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4903 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4904 {
4905 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4906 }
4907
4908 /**
4909 * @brief Generate break event.
4910 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4911 * @param TIMx Timer instance
4912 * @retval None
4913 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4914 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4915 {
4916 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4917 }
4918
4919 /**
4920 * @brief Generate break 2 event.
4921 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4922 * @param TIMx Timer instance
4923 * @retval None
4924 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4925 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4926 {
4927 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4928 }
4929
4930 /**
4931 * @}
4932 */
4933
4934 #if defined(USE_FULL_LL_DRIVER)
4935 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4936 * @{
4937 */
4938
4939 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4940 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4941 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4942 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4943 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4944 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4945 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4946 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4947 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4948 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4949 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4950 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4951 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4952 /**
4953 * @}
4954 */
4955 #endif /* USE_FULL_LL_DRIVER */
4956
4957 /**
4958 * @}
4959 */
4960
4961 /**
4962 * @}
4963 */
4964
4965 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
4966
4967 /**
4968 * @}
4969 */
4970
4971 #ifdef __cplusplus
4972 }
4973 #endif
4974
4975 #endif /* __STM32WLxx_LL_TIM_H */
4976
