1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F0xx_LL_TIM_H
21 #define __STM32F0xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f0xx.h"
29
30 /** @addtogroup STM32F0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U /* 6: TIMx_CH4 */
54 };
55
56 static const uint8_t SHIFT_TAB_OCxx[] =
57 {
58 0U, /* 0: OC1M, OC1FE, OC1PE */
59 0U, /* 1: - NA */
60 8U, /* 2: OC2M, OC2FE, OC2PE */
61 0U, /* 3: - NA */
62 0U, /* 4: OC3M, OC3FE, OC3PE */
63 0U, /* 5: - NA */
64 8U /* 6: OC4M, OC4FE, OC4PE */
65 };
66
67 static const uint8_t SHIFT_TAB_ICxx[] =
68 {
69 0U, /* 0: CC1S, IC1PSC, IC1F */
70 0U, /* 1: - NA */
71 8U, /* 2: CC2S, IC2PSC, IC2F */
72 0U, /* 3: - NA */
73 0U, /* 4: CC3S, IC3PSC, IC3F */
74 0U, /* 5: - NA */
75 8U /* 6: CC4S, IC4PSC, IC4F */
76 };
77
78 static const uint8_t SHIFT_TAB_CCxP[] =
79 {
80 0U, /* 0: CC1P */
81 2U, /* 1: CC1NP */
82 4U, /* 2: CC2P */
83 6U, /* 3: CC2NP */
84 8U, /* 4: CC3P */
85 10U, /* 5: CC3NP */
86 12U /* 6: CC4P */
87 };
88
89 static const uint8_t SHIFT_TAB_OISx[] =
90 {
91 0U, /* 0: OIS1 */
92 1U, /* 1: OIS1N */
93 2U, /* 2: OIS2 */
94 3U, /* 3: OIS2N */
95 4U, /* 4: OIS3 */
96 5U, /* 5: OIS3N */
97 6U /* 6: OIS4 */
98 };
99 /**
100 * @}
101 */
102
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
105 * @{
106 */
107
108
109 #define TIMx_OR_RMP_SHIFT 16U
110 #define TIMx_OR_RMP_MASK 0x0000FFFFU
111 #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
112
113 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
114 #define DT_DELAY_1 ((uint8_t)0x7F)
115 #define DT_DELAY_2 ((uint8_t)0x3F)
116 #define DT_DELAY_3 ((uint8_t)0x1F)
117 #define DT_DELAY_4 ((uint8_t)0x1F)
118
119 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
120 #define DT_RANGE_1 ((uint8_t)0x00)
121 #define DT_RANGE_2 ((uint8_t)0x80)
122 #define DT_RANGE_3 ((uint8_t)0xC0)
123 #define DT_RANGE_4 ((uint8_t)0xE0)
124
125
126 /**
127 * @}
128 */
129
130 /* Private macros ------------------------------------------------------------*/
131 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
132 * @{
133 */
134 /** @brief Convert channel id into channel index.
135 * @param __CHANNEL__ This parameter can be one of the following values:
136 * @arg @ref LL_TIM_CHANNEL_CH1
137 * @arg @ref LL_TIM_CHANNEL_CH1N
138 * @arg @ref LL_TIM_CHANNEL_CH2
139 * @arg @ref LL_TIM_CHANNEL_CH2N
140 * @arg @ref LL_TIM_CHANNEL_CH3
141 * @arg @ref LL_TIM_CHANNEL_CH3N
142 * @arg @ref LL_TIM_CHANNEL_CH4
143 * @retval none
144 */
145 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
146 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
147 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
148 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
149 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
150 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
152
153 /** @brief Calculate the deadtime sampling period(in ps).
154 * @param __TIMCLK__ timer input clock frequency (in Hz).
155 * @param __CKD__ This parameter can be one of the following values:
156 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
157 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
158 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
159 * @retval none
160 */
161 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
162 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
163 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
164 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
165 /**
166 * @}
167 */
168
169
170 /* Exported types ------------------------------------------------------------*/
171 #if defined(USE_FULL_LL_DRIVER)
172 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
173 * @{
174 */
175
176 /**
177 * @brief TIM Time Base configuration structure definition.
178 */
179 typedef struct
180 {
181 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
182 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
183
184 This feature can be modified afterwards using unitary function
185 @ref LL_TIM_SetPrescaler().*/
186
187 uint32_t CounterMode; /*!< Specifies the counter mode.
188 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
189
190 This feature can be modified afterwards using unitary function
191 @ref LL_TIM_SetCounterMode().*/
192
193 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
194 Auto-Reload Register at the next update event.
195 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
196 Some timer instances may support 32 bits counters. In that case this parameter must
197 be a number between 0x0000 and 0xFFFFFFFF.
198
199 This feature can be modified afterwards using unitary function
200 @ref LL_TIM_SetAutoReload().*/
201
202 uint32_t ClockDivision; /*!< Specifies the clock division.
203 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
204
205 This feature can be modified afterwards using unitary function
206 @ref LL_TIM_SetClockDivision().*/
207
208 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
209 reaches zero, an update event is generated and counting restarts
210 from the RCR value (N).
211 This means in PWM mode that (N+1) corresponds to:
212 - the number of PWM periods in edge-aligned mode
213 - the number of half PWM period in center-aligned mode
214 GP timers: this parameter must be a number between Min_Data = 0x00 and
215 Max_Data = 0xFF.
216 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
217 Max_Data = 0xFFFF.
218
219 This feature can be modified afterwards using unitary function
220 @ref LL_TIM_SetRepetitionCounter().*/
221 } LL_TIM_InitTypeDef;
222
223 /**
224 * @brief TIM Output Compare configuration structure definition.
225 */
226 typedef struct
227 {
228 uint32_t OCMode; /*!< Specifies the output mode.
229 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
230
231 This feature can be modified afterwards using unitary function
232 @ref LL_TIM_OC_SetMode().*/
233
234 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
235 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
236
237 This feature can be modified afterwards using unitary functions
238 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
239
240 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
241 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
242
243 This feature can be modified afterwards using unitary functions
244 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
245
246 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
247 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
248
249 This feature can be modified afterwards using unitary function
250 LL_TIM_OC_SetCompareCHx (x=1..6).*/
251
252 uint32_t OCPolarity; /*!< Specifies the output polarity.
253 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
254
255 This feature can be modified afterwards using unitary function
256 @ref LL_TIM_OC_SetPolarity().*/
257
258 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
259 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
260
261 This feature can be modified afterwards using unitary function
262 @ref LL_TIM_OC_SetPolarity().*/
263
264
265 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
266 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
267
268 This feature can be modified afterwards using unitary function
269 @ref LL_TIM_OC_SetIdleState().*/
270
271 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
272 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
273
274 This feature can be modified afterwards using unitary function
275 @ref LL_TIM_OC_SetIdleState().*/
276 } LL_TIM_OC_InitTypeDef;
277
278 /**
279 * @brief TIM Input Capture configuration structure definition.
280 */
281
282 typedef struct
283 {
284
285 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
286 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
287
288 This feature can be modified afterwards using unitary function
289 @ref LL_TIM_IC_SetPolarity().*/
290
291 uint32_t ICActiveInput; /*!< Specifies the input.
292 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_IC_SetActiveInput().*/
296
297 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
298 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_IC_SetPrescaler().*/
302
303 uint32_t ICFilter; /*!< Specifies the input capture filter.
304 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
305
306 This feature can be modified afterwards using unitary function
307 @ref LL_TIM_IC_SetFilter().*/
308 } LL_TIM_IC_InitTypeDef;
309
310
311 /**
312 * @brief TIM Encoder interface configuration structure definition.
313 */
314 typedef struct
315 {
316 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
317 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_SetEncoderMode().*/
321
322 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
323 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetPolarity().*/
327
328 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
329 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetActiveInput().*/
333
334 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
335 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
336
337 This feature can be modified afterwards using unitary function
338 @ref LL_TIM_IC_SetPrescaler().*/
339
340 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
341 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
342
343 This feature can be modified afterwards using unitary function
344 @ref LL_TIM_IC_SetFilter().*/
345
346 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
347 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
348
349 This feature can be modified afterwards using unitary function
350 @ref LL_TIM_IC_SetPolarity().*/
351
352 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
353 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
354
355 This feature can be modified afterwards using unitary function
356 @ref LL_TIM_IC_SetActiveInput().*/
357
358 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
359 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
360
361 This feature can be modified afterwards using unitary function
362 @ref LL_TIM_IC_SetPrescaler().*/
363
364 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
366
367 This feature can be modified afterwards using unitary function
368 @ref LL_TIM_IC_SetFilter().*/
369
370 } LL_TIM_ENCODER_InitTypeDef;
371
372 /**
373 * @brief TIM Hall sensor interface configuration structure definition.
374 */
375 typedef struct
376 {
377
378 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
379 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPolarity().*/
383
384 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
385 Prescaler must be set to get a maximum counter period longer than the
386 time interval between 2 consecutive changes on the Hall inputs.
387 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
388
389 This feature can be modified afterwards using unitary function
390 @ref LL_TIM_IC_SetPrescaler().*/
391
392 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
393 This parameter can be a value of
394 @ref TIM_LL_EC_IC_FILTER.
395
396 This feature can be modified afterwards using unitary function
397 @ref LL_TIM_IC_SetFilter().*/
398
399 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
400 A positive pulse (TRGO event) is generated with a programmable delay every time
401 a change occurs on the Hall inputs.
402 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
403
404 This feature can be modified afterwards using unitary function
405 @ref LL_TIM_OC_SetCompareCH2().*/
406 } LL_TIM_HALLSENSOR_InitTypeDef;
407
408 /**
409 * @brief BDTR (Break and Dead Time) structure definition
410 */
411 typedef struct
412 {
413 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
414 This parameter can be a value of @ref TIM_LL_EC_OSSR
415
416 This feature can be modified afterwards using unitary function
417 @ref LL_TIM_SetOffStates()
418
419 @note This bit-field cannot be modified as long as LOCK level 2 has been
420 programmed. */
421
422 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
423 This parameter can be a value of @ref TIM_LL_EC_OSSI
424
425 This feature can be modified afterwards using unitary function
426 @ref LL_TIM_SetOffStates()
427
428 @note This bit-field cannot be modified as long as LOCK level 2 has been
429 programmed. */
430
431 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
432 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
433
434 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
435 register has been written, their content is frozen until the next reset.*/
436
437 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
438 switching-on of the outputs.
439 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_OC_SetDeadTime()
443
444 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
445 programmed. */
446
447 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
448 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
449
450 This feature can be modified afterwards using unitary functions
451 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
452
453 @note This bit-field can not be modified as long as LOCK level 1 has been
454 programmed. */
455
456 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
457 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
458
459 This feature can be modified afterwards using unitary function
460 @ref LL_TIM_ConfigBRK()
461
462 @note This bit-field can not be modified as long as LOCK level 1 has been
463 programmed. */
464
465 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
466 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
467
468 This feature can be modified afterwards using unitary functions
469 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
470
471 @note This bit-field can not be modified as long as LOCK level 1 has been
472 programmed. */
473 } LL_TIM_BDTR_InitTypeDef;
474
475 /**
476 * @}
477 */
478 #endif /* USE_FULL_LL_DRIVER */
479
480 /* Exported constants --------------------------------------------------------*/
481 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
482 * @{
483 */
484
485 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
486 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
487 * @{
488 */
489 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
490 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
491 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
492 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
493 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
494 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
495 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
496 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
497 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
498 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
499 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
500 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
501 /**
502 * @}
503 */
504
505 #if defined(USE_FULL_LL_DRIVER)
506 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
507 * @{
508 */
509 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
510 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
511 /**
512 * @}
513 */
514
515 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
516 * @{
517 */
518 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
519 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
520 /**
521 * @}
522 */
523 #endif /* USE_FULL_LL_DRIVER */
524
525 /** @defgroup TIM_LL_EC_IT IT Defines
526 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
527 * @{
528 */
529 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
530 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
531 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
532 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
533 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
534 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
535 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
536 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
537 /**
538 * @}
539 */
540
541 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
542 * @{
543 */
544 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
545 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
546 /**
547 * @}
548 */
549
550 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
551 * @{
552 */
553 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
554 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
555 /**
556 * @}
557 */
558
559 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
560 * @{
561 */
562 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
563 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
564 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
565 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
566 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
567 /**
568 * @}
569 */
570
571 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
572 * @{
573 */
574 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
575 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
576 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
577 /**
578 * @}
579 */
580
581 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
582 * @{
583 */
584 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
585 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
591 * @{
592 */
593 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
594 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
595 /**
596 * @}
597 */
598
599 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
600 * @{
601 */
602 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
603 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
604 /**
605 * @}
606 */
607
608 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
609 * @{
610 */
611 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
612 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
613 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
614 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_LL_EC_CHANNEL Channel
620 * @{
621 */
622 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
623 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
624 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
625 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
626 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
627 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
628 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
629 /**
630 * @}
631 */
632
633 #if defined(USE_FULL_LL_DRIVER)
634 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
635 * @{
636 */
637 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
638 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
639 /**
640 * @}
641 */
642 #endif /* USE_FULL_LL_DRIVER */
643
644 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
645 * @{
646 */
647 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
648 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
649 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
650 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
651 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
652 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
653 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
654 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
655 /**
656 * @}
657 */
658
659 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
660 * @{
661 */
662 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
663 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
664 /**
665 * @}
666 */
667
668 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
669 * @{
670 */
671 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
672 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
673 /**
674 * @}
675 */
676
677
678 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
679 * @{
680 */
681 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
682 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
683 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
684 /**
685 * @}
686 */
687
688 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
689 * @{
690 */
691 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
692 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
693 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
694 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
695 /**
696 * @}
697 */
698
699 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
700 * @{
701 */
702 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
703 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
704 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
705 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
706 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
707 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
708 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
709 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
710 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
711 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
712 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
713 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
714 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
715 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
716 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
717 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
723 * @{
724 */
725 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
726 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
727 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
728 /**
729 * @}
730 */
731
732 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
733 * @{
734 */
735 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
736 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
737 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
738 /**
739 * @}
740 */
741
742 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
743 * @{
744 */
745 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
746 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
747 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
748 /**
749 * @}
750 */
751
752 /** @defgroup TIM_LL_EC_TRGO Trigger Output
753 * @{
754 */
755 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
756 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
757 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
758 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
759 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
760 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
761 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
762 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
763 /**
764 * @}
765 */
766
767
768 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
769 * @{
770 */
771 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
772 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
773 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
774 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_TS Trigger Selection
780 * @{
781 */
782 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
783 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
784 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
785 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
786 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
787 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
788 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
789 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
790 /**
791 * @}
792 */
793
794 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
795 * @{
796 */
797 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
798 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
799 /**
800 * @}
801 */
802
803 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
804 * @{
805 */
806 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
807 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
808 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
809 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
810 /**
811 * @}
812 */
813
814 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
815 * @{
816 */
817 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
818 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
819 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
820 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
821 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
822 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
823 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
824 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
825 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
826 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
827 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
828 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
829 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
830 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
831 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
832 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
833 /**
834 * @}
835 */
836
837
838 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
839 * @{
840 */
841 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
842 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
843 /**
844 * @}
845 */
846
847
848
849
850 /** @defgroup TIM_LL_EC_OSSI OSSI
851 * @{
852 */
853 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
854 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
855 /**
856 * @}
857 */
858
859 /** @defgroup TIM_LL_EC_OSSR OSSR
860 * @{
861 */
862 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
863 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
864 /**
865 * @}
866 */
867
868
869 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
870 * @{
871 */
872 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
873 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
874 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
875 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
876 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
877 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
878 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
879 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
880 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
881 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
882 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
883 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
884 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
885 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
886 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
887 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
888 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
889 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
890 /**
891 * @}
892 */
893
894 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
895 * @{
896 */
897 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
898 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
899 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
900 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
901 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
902 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
903 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
904 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
905 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
906 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
907 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
908 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
909 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
910 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
911 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
912 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
913 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
914 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
915 /**
916 * @}
917 */
918
919
920 #define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to Ored GPIO */
921 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC clock */
922 #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 clock */
923 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
924
925
926 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
927 * @{
928 */
929 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
930 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
931 /**
932 * @}
933 */
934
935
936 /**
937 * @}
938 */
939
940 /* Exported macro ------------------------------------------------------------*/
941 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
942 * @{
943 */
944
945 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
946 * @{
947 */
948 /**
949 * @brief Write a value in TIM register.
950 * @param __INSTANCE__ TIM Instance
951 * @param __REG__ Register to be written
952 * @param __VALUE__ Value to be written in the register
953 * @retval None
954 */
955 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
956
957 /**
958 * @brief Read a value in TIM register.
959 * @param __INSTANCE__ TIM Instance
960 * @param __REG__ Register to be read
961 * @retval Register value
962 */
963 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
964 /**
965 * @}
966 */
967
968 /**
969 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
970 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
971 * @param __TIMCLK__ timer input clock frequency (in Hz)
972 * @param __CKD__ This parameter can be one of the following values:
973 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
974 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
975 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
976 * @param __DT__ deadtime duration (in ns)
977 * @retval DTG[0:7]
978 */
979 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
980 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
981 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
982 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
983 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
984 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
985 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
986 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
987 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
988 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
989 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
990 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
991 0U)
992
993 /**
994 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
995 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
996 * @param __TIMCLK__ timer input clock frequency (in Hz)
997 * @param __CNTCLK__ counter clock frequency (in Hz)
998 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
999 */
1000 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1001 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1002
1003 /**
1004 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1005 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1006 * @param __TIMCLK__ timer input clock frequency (in Hz)
1007 * @param __PSC__ prescaler
1008 * @param __FREQ__ output signal frequency (in Hz)
1009 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1010 */
1011 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1012 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1013
1014 /**
1015 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1016 * active/inactive delay.
1017 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1018 * @param __TIMCLK__ timer input clock frequency (in Hz)
1019 * @param __PSC__ prescaler
1020 * @param __DELAY__ timer output compare active/inactive delay (in us)
1021 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1022 */
1023 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1024 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1025 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1026
1027 /**
1028 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1029 * (when the timer operates in one pulse mode).
1030 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1031 * @param __TIMCLK__ timer input clock frequency (in Hz)
1032 * @param __PSC__ prescaler
1033 * @param __DELAY__ timer output compare active/inactive delay (in us)
1034 * @param __PULSE__ pulse duration (in us)
1035 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1036 */
1037 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1038 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1039 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1040
1041 /**
1042 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1043 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1044 * @param __ICPSC__ This parameter can be one of the following values:
1045 * @arg @ref LL_TIM_ICPSC_DIV1
1046 * @arg @ref LL_TIM_ICPSC_DIV2
1047 * @arg @ref LL_TIM_ICPSC_DIV4
1048 * @arg @ref LL_TIM_ICPSC_DIV8
1049 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1050 */
1051 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1052 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1053
1054
1055 /**
1056 * @}
1057 */
1058
1059 /* Exported functions --------------------------------------------------------*/
1060 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1061 * @{
1062 */
1063
1064 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1065 * @{
1066 */
1067 /**
1068 * @brief Enable timer counter.
1069 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1070 * @param TIMx Timer instance
1071 * @retval None
1072 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1073 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1074 {
1075 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1076 }
1077
1078 /**
1079 * @brief Disable timer counter.
1080 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1081 * @param TIMx Timer instance
1082 * @retval None
1083 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1084 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1085 {
1086 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1087 }
1088
1089 /**
1090 * @brief Indicates whether the timer counter is enabled.
1091 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1092 * @param TIMx Timer instance
1093 * @retval State of bit (1 or 0).
1094 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1095 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1096 {
1097 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1098 }
1099
1100 /**
1101 * @brief Enable update event generation.
1102 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1103 * @param TIMx Timer instance
1104 * @retval None
1105 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1106 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1107 {
1108 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1109 }
1110
1111 /**
1112 * @brief Disable update event generation.
1113 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1114 * @param TIMx Timer instance
1115 * @retval None
1116 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1117 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1118 {
1119 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1120 }
1121
1122 /**
1123 * @brief Indicates whether update event generation is enabled.
1124 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1125 * @param TIMx Timer instance
1126 * @retval Inverted state of bit (0 or 1).
1127 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1128 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1129 {
1130 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1131 }
1132
1133 /**
1134 * @brief Set update event source
1135 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1136 * generate an update interrupt or DMA request if enabled:
1137 * - Counter overflow/underflow
1138 * - Setting the UG bit
1139 * - Update generation through the slave mode controller
1140 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1141 * overflow/underflow generates an update interrupt or DMA request if enabled.
1142 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1143 * @param TIMx Timer instance
1144 * @param UpdateSource This parameter can be one of the following values:
1145 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1146 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1147 * @retval None
1148 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1149 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1150 {
1151 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1152 }
1153
1154 /**
1155 * @brief Get actual event update source
1156 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1157 * @param TIMx Timer instance
1158 * @retval Returned value can be one of the following values:
1159 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1160 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1161 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1162 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1163 {
1164 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1165 }
1166
1167 /**
1168 * @brief Set one pulse mode (one shot v.s. repetitive).
1169 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1170 * @param TIMx Timer instance
1171 * @param OnePulseMode This parameter can be one of the following values:
1172 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1173 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1174 * @retval None
1175 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1176 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1177 {
1178 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1179 }
1180
1181 /**
1182 * @brief Get actual one pulse mode.
1183 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1184 * @param TIMx Timer instance
1185 * @retval Returned value can be one of the following values:
1186 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1187 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1188 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1189 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1190 {
1191 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1192 }
1193
1194 /**
1195 * @brief Set the timer counter counting mode.
1196 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1197 * check whether or not the counter mode selection feature is supported
1198 * by a timer instance.
1199 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1200 * requires a timer reset to avoid unexpected direction
1201 * due to DIR bit readonly in center aligned mode.
1202 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1203 * CR1 CMS LL_TIM_SetCounterMode
1204 * @param TIMx Timer instance
1205 * @param CounterMode This parameter can be one of the following values:
1206 * @arg @ref LL_TIM_COUNTERMODE_UP
1207 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1208 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1209 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1210 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1211 * @retval None
1212 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1213 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1214 {
1215 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1216 }
1217
1218 /**
1219 * @brief Get actual counter mode.
1220 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1221 * check whether or not the counter mode selection feature is supported
1222 * by a timer instance.
1223 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1224 * CR1 CMS LL_TIM_GetCounterMode
1225 * @param TIMx Timer instance
1226 * @retval Returned value can be one of the following values:
1227 * @arg @ref LL_TIM_COUNTERMODE_UP
1228 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1229 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1230 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1231 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1232 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1233 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1234 {
1235 uint32_t counter_mode;
1236
1237 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1238
1239 if (counter_mode == 0U)
1240 {
1241 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1242 }
1243
1244 return counter_mode;
1245 }
1246
1247 /**
1248 * @brief Enable auto-reload (ARR) preload.
1249 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1250 * @param TIMx Timer instance
1251 * @retval None
1252 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1253 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1254 {
1255 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1256 }
1257
1258 /**
1259 * @brief Disable auto-reload (ARR) preload.
1260 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1261 * @param TIMx Timer instance
1262 * @retval None
1263 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1264 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1265 {
1266 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1267 }
1268
1269 /**
1270 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1271 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1272 * @param TIMx Timer instance
1273 * @retval State of bit (1 or 0).
1274 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1275 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1276 {
1277 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1278 }
1279
1280 /**
1281 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1282 * (when supported) and the digital filters.
1283 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1284 * whether or not the clock division feature is supported by the timer
1285 * instance.
1286 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1287 * @param TIMx Timer instance
1288 * @param ClockDivision This parameter can be one of the following values:
1289 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1290 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1291 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1292 * @retval None
1293 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1294 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1295 {
1296 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1297 }
1298
1299 /**
1300 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1301 * generators (when supported) and the digital filters.
1302 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1303 * whether or not the clock division feature is supported by the timer
1304 * instance.
1305 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1306 * @param TIMx Timer instance
1307 * @retval Returned value can be one of the following values:
1308 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1309 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1310 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1311 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1312 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1313 {
1314 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1315 }
1316
1317 /**
1318 * @brief Set the counter value.
1319 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1320 * whether or not a timer instance supports a 32 bits counter.
1321 * @rmtoll CNT CNT LL_TIM_SetCounter
1322 * @param TIMx Timer instance
1323 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1324 * @retval None
1325 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1326 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1327 {
1328 WRITE_REG(TIMx->CNT, Counter);
1329 }
1330
1331 /**
1332 * @brief Get the counter value.
1333 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1334 * whether or not a timer instance supports a 32 bits counter.
1335 * @rmtoll CNT CNT LL_TIM_GetCounter
1336 * @param TIMx Timer instance
1337 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1338 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1339 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1340 {
1341 return (uint32_t)(READ_REG(TIMx->CNT));
1342 }
1343
1344 /**
1345 * @brief Get the current direction of the counter
1346 * @rmtoll CR1 DIR LL_TIM_GetDirection
1347 * @param TIMx Timer instance
1348 * @retval Returned value can be one of the following values:
1349 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1350 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1351 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1352 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1353 {
1354 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1355 }
1356
1357 /**
1358 * @brief Set the prescaler value.
1359 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1360 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1361 * prescaler ratio is taken into account at the next update event.
1362 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1363 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1364 * @param TIMx Timer instance
1365 * @param Prescaler between Min_Data=0 and Max_Data=65535
1366 * @retval None
1367 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1368 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1369 {
1370 WRITE_REG(TIMx->PSC, Prescaler);
1371 }
1372
1373 /**
1374 * @brief Get the prescaler value.
1375 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1376 * @param TIMx Timer instance
1377 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1378 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1379 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1380 {
1381 return (uint32_t)(READ_REG(TIMx->PSC));
1382 }
1383
1384 /**
1385 * @brief Set the auto-reload value.
1386 * @note The counter is blocked while the auto-reload value is null.
1387 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1388 * whether or not a timer instance supports a 32 bits counter.
1389 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1390 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1391 * @param TIMx Timer instance
1392 * @param AutoReload between Min_Data=0 and Max_Data=65535
1393 * @retval None
1394 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1395 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1396 {
1397 WRITE_REG(TIMx->ARR, AutoReload);
1398 }
1399
1400 /**
1401 * @brief Get the auto-reload value.
1402 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1403 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1404 * whether or not a timer instance supports a 32 bits counter.
1405 * @param TIMx Timer instance
1406 * @retval Auto-reload value
1407 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1408 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1409 {
1410 return (uint32_t)(READ_REG(TIMx->ARR));
1411 }
1412
1413 /**
1414 * @brief Set the repetition counter value.
1415 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1416 * whether or not a timer instance supports a repetition counter.
1417 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1418 * @param TIMx Timer instance
1419 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1420 * @retval None
1421 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1422 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1423 {
1424 WRITE_REG(TIMx->RCR, RepetitionCounter);
1425 }
1426
1427 /**
1428 * @brief Get the repetition counter value.
1429 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1430 * whether or not a timer instance supports a repetition counter.
1431 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1432 * @param TIMx Timer instance
1433 * @retval Repetition counter value
1434 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1435 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1436 {
1437 return (uint32_t)(READ_REG(TIMx->RCR));
1438 }
1439
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1445 * @{
1446 */
1447 /**
1448 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1449 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1450 * they are updated only when a commutation event (COM) occurs.
1451 * @note Only on channels that have a complementary output.
1452 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1453 * whether or not a timer instance is able to generate a commutation event.
1454 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1455 * @param TIMx Timer instance
1456 * @retval None
1457 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1458 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1459 {
1460 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1461 }
1462
1463 /**
1464 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1465 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1466 * whether or not a timer instance is able to generate a commutation event.
1467 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1468 * @param TIMx Timer instance
1469 * @retval None
1470 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1471 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1472 {
1473 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1474 }
1475
1476 /**
1477 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1478 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1479 * @param TIMx Timer instance
1480 * @retval State of bit (1 or 0).
1481 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1482 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1483 {
1484 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1485 }
1486
1487 /**
1488 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1489 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1490 * whether or not a timer instance is able to generate a commutation event.
1491 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1492 * @param TIMx Timer instance
1493 * @param CCUpdateSource This parameter can be one of the following values:
1494 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1495 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1496 * @retval None
1497 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1498 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1499 {
1500 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1501 }
1502
1503 /**
1504 * @brief Set the trigger of the capture/compare DMA request.
1505 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1506 * @param TIMx Timer instance
1507 * @param DMAReqTrigger This parameter can be one of the following values:
1508 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1509 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1510 * @retval None
1511 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1512 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1513 {
1514 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1515 }
1516
1517 /**
1518 * @brief Get actual trigger of the capture/compare DMA request.
1519 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1520 * @param TIMx Timer instance
1521 * @retval Returned value can be one of the following values:
1522 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1523 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1524 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1525 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1526 {
1527 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1528 }
1529
1530 /**
1531 * @brief Set the lock level to freeze the
1532 * configuration of several capture/compare parameters.
1533 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1534 * the lock mechanism is supported by a timer instance.
1535 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1536 * @param TIMx Timer instance
1537 * @param LockLevel This parameter can be one of the following values:
1538 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1539 * @arg @ref LL_TIM_LOCKLEVEL_1
1540 * @arg @ref LL_TIM_LOCKLEVEL_2
1541 * @arg @ref LL_TIM_LOCKLEVEL_3
1542 * @retval None
1543 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1544 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1545 {
1546 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1547 }
1548
1549 /**
1550 * @brief Enable capture/compare channels.
1551 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1552 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1553 * CCER CC2E LL_TIM_CC_EnableChannel\n
1554 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1555 * CCER CC3E LL_TIM_CC_EnableChannel\n
1556 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1557 * CCER CC4E LL_TIM_CC_EnableChannel
1558 * @param TIMx Timer instance
1559 * @param Channels This parameter can be a combination of the following values:
1560 * @arg @ref LL_TIM_CHANNEL_CH1
1561 * @arg @ref LL_TIM_CHANNEL_CH1N
1562 * @arg @ref LL_TIM_CHANNEL_CH2
1563 * @arg @ref LL_TIM_CHANNEL_CH2N
1564 * @arg @ref LL_TIM_CHANNEL_CH3
1565 * @arg @ref LL_TIM_CHANNEL_CH3N
1566 * @arg @ref LL_TIM_CHANNEL_CH4
1567 * @retval None
1568 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1569 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1570 {
1571 SET_BIT(TIMx->CCER, Channels);
1572 }
1573
1574 /**
1575 * @brief Disable capture/compare channels.
1576 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1577 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1578 * CCER CC2E LL_TIM_CC_DisableChannel\n
1579 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1580 * CCER CC3E LL_TIM_CC_DisableChannel\n
1581 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1582 * CCER CC4E LL_TIM_CC_DisableChannel
1583 * @param TIMx Timer instance
1584 * @param Channels This parameter can be a combination of the following values:
1585 * @arg @ref LL_TIM_CHANNEL_CH1
1586 * @arg @ref LL_TIM_CHANNEL_CH1N
1587 * @arg @ref LL_TIM_CHANNEL_CH2
1588 * @arg @ref LL_TIM_CHANNEL_CH2N
1589 * @arg @ref LL_TIM_CHANNEL_CH3
1590 * @arg @ref LL_TIM_CHANNEL_CH3N
1591 * @arg @ref LL_TIM_CHANNEL_CH4
1592 * @retval None
1593 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1594 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1595 {
1596 CLEAR_BIT(TIMx->CCER, Channels);
1597 }
1598
1599 /**
1600 * @brief Indicate whether channel(s) is(are) enabled.
1601 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1602 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1603 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1604 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1605 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1606 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1607 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1608 * @param TIMx Timer instance
1609 * @param Channels This parameter can be a combination of the following values:
1610 * @arg @ref LL_TIM_CHANNEL_CH1
1611 * @arg @ref LL_TIM_CHANNEL_CH1N
1612 * @arg @ref LL_TIM_CHANNEL_CH2
1613 * @arg @ref LL_TIM_CHANNEL_CH2N
1614 * @arg @ref LL_TIM_CHANNEL_CH3
1615 * @arg @ref LL_TIM_CHANNEL_CH3N
1616 * @arg @ref LL_TIM_CHANNEL_CH4
1617 * @retval State of bit (1 or 0).
1618 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)1619 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
1620 {
1621 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1622 }
1623
1624 /**
1625 * @}
1626 */
1627
1628 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1629 * @{
1630 */
1631 /**
1632 * @brief Configure an output channel.
1633 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1634 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1635 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1636 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1637 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1638 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1639 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1640 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1641 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1642 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1643 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1644 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1645 * @param TIMx Timer instance
1646 * @param Channel This parameter can be one of the following values:
1647 * @arg @ref LL_TIM_CHANNEL_CH1
1648 * @arg @ref LL_TIM_CHANNEL_CH2
1649 * @arg @ref LL_TIM_CHANNEL_CH3
1650 * @arg @ref LL_TIM_CHANNEL_CH4
1651 * @param Configuration This parameter must be a combination of all the following values:
1652 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1653 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1654 * @retval None
1655 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1656 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1657 {
1658 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1659 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1660 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1661 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1662 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1663 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1664 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1665 }
1666
1667 /**
1668 * @brief Define the behavior of the output reference signal OCxREF from which
1669 * OCx and OCxN (when relevant) are derived.
1670 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1671 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1672 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1673 * CCMR2 OC4M LL_TIM_OC_SetMode
1674 * @param TIMx Timer instance
1675 * @param Channel This parameter can be one of the following values:
1676 * @arg @ref LL_TIM_CHANNEL_CH1
1677 * @arg @ref LL_TIM_CHANNEL_CH2
1678 * @arg @ref LL_TIM_CHANNEL_CH3
1679 * @arg @ref LL_TIM_CHANNEL_CH4
1680 * @param Mode This parameter can be one of the following values:
1681 * @arg @ref LL_TIM_OCMODE_FROZEN
1682 * @arg @ref LL_TIM_OCMODE_ACTIVE
1683 * @arg @ref LL_TIM_OCMODE_INACTIVE
1684 * @arg @ref LL_TIM_OCMODE_TOGGLE
1685 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1686 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1687 * @arg @ref LL_TIM_OCMODE_PWM1
1688 * @arg @ref LL_TIM_OCMODE_PWM2
1689 * @retval None
1690 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1691 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1692 {
1693 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1694 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1695 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1696 }
1697
1698 /**
1699 * @brief Get the output compare mode of an output channel.
1700 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1701 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1702 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1703 * CCMR2 OC4M LL_TIM_OC_GetMode
1704 * @param TIMx Timer instance
1705 * @param Channel This parameter can be one of the following values:
1706 * @arg @ref LL_TIM_CHANNEL_CH1
1707 * @arg @ref LL_TIM_CHANNEL_CH2
1708 * @arg @ref LL_TIM_CHANNEL_CH3
1709 * @arg @ref LL_TIM_CHANNEL_CH4
1710 * @retval Returned value can be one of the following values:
1711 * @arg @ref LL_TIM_OCMODE_FROZEN
1712 * @arg @ref LL_TIM_OCMODE_ACTIVE
1713 * @arg @ref LL_TIM_OCMODE_INACTIVE
1714 * @arg @ref LL_TIM_OCMODE_TOGGLE
1715 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1716 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1717 * @arg @ref LL_TIM_OCMODE_PWM1
1718 * @arg @ref LL_TIM_OCMODE_PWM2
1719 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)1720 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
1721 {
1722 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1723 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1724 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1725 }
1726
1727 /**
1728 * @brief Set the polarity of an output channel.
1729 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1730 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1731 * CCER CC2P LL_TIM_OC_SetPolarity\n
1732 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1733 * CCER CC3P LL_TIM_OC_SetPolarity\n
1734 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1735 * CCER CC4P LL_TIM_OC_SetPolarity
1736 * @param TIMx Timer instance
1737 * @param Channel This parameter can be one of the following values:
1738 * @arg @ref LL_TIM_CHANNEL_CH1
1739 * @arg @ref LL_TIM_CHANNEL_CH1N
1740 * @arg @ref LL_TIM_CHANNEL_CH2
1741 * @arg @ref LL_TIM_CHANNEL_CH2N
1742 * @arg @ref LL_TIM_CHANNEL_CH3
1743 * @arg @ref LL_TIM_CHANNEL_CH3N
1744 * @arg @ref LL_TIM_CHANNEL_CH4
1745 * @param Polarity This parameter can be one of the following values:
1746 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1747 * @arg @ref LL_TIM_OCPOLARITY_LOW
1748 * @retval None
1749 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1750 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1751 {
1752 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1753 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1754 }
1755
1756 /**
1757 * @brief Get the polarity of an output channel.
1758 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1759 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1760 * CCER CC2P LL_TIM_OC_GetPolarity\n
1761 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1762 * CCER CC3P LL_TIM_OC_GetPolarity\n
1763 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1764 * CCER CC4P LL_TIM_OC_GetPolarity
1765 * @param TIMx Timer instance
1766 * @param Channel This parameter can be one of the following values:
1767 * @arg @ref LL_TIM_CHANNEL_CH1
1768 * @arg @ref LL_TIM_CHANNEL_CH1N
1769 * @arg @ref LL_TIM_CHANNEL_CH2
1770 * @arg @ref LL_TIM_CHANNEL_CH2N
1771 * @arg @ref LL_TIM_CHANNEL_CH3
1772 * @arg @ref LL_TIM_CHANNEL_CH3N
1773 * @arg @ref LL_TIM_CHANNEL_CH4
1774 * @retval Returned value can be one of the following values:
1775 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1776 * @arg @ref LL_TIM_OCPOLARITY_LOW
1777 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)1778 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
1779 {
1780 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1781 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1782 }
1783
1784 /**
1785 * @brief Set the IDLE state of an output channel
1786 * @note This function is significant only for the timer instances
1787 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1788 * can be used to check whether or not a timer instance provides
1789 * a break input.
1790 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1791 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1792 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1793 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1794 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1795 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1796 * CR2 OIS4 LL_TIM_OC_SetIdleState
1797 * @param TIMx Timer instance
1798 * @param Channel This parameter can be one of the following values:
1799 * @arg @ref LL_TIM_CHANNEL_CH1
1800 * @arg @ref LL_TIM_CHANNEL_CH1N
1801 * @arg @ref LL_TIM_CHANNEL_CH2
1802 * @arg @ref LL_TIM_CHANNEL_CH2N
1803 * @arg @ref LL_TIM_CHANNEL_CH3
1804 * @arg @ref LL_TIM_CHANNEL_CH3N
1805 * @arg @ref LL_TIM_CHANNEL_CH4
1806 * @param IdleState This parameter can be one of the following values:
1807 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1808 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1809 * @retval None
1810 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1811 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1812 {
1813 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1814 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1815 }
1816
1817 /**
1818 * @brief Get the IDLE state of an output channel
1819 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1820 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1821 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1822 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1823 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1824 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1825 * CR2 OIS4 LL_TIM_OC_GetIdleState
1826 * @param TIMx Timer instance
1827 * @param Channel This parameter can be one of the following values:
1828 * @arg @ref LL_TIM_CHANNEL_CH1
1829 * @arg @ref LL_TIM_CHANNEL_CH1N
1830 * @arg @ref LL_TIM_CHANNEL_CH2
1831 * @arg @ref LL_TIM_CHANNEL_CH2N
1832 * @arg @ref LL_TIM_CHANNEL_CH3
1833 * @arg @ref LL_TIM_CHANNEL_CH3N
1834 * @arg @ref LL_TIM_CHANNEL_CH4
1835 * @retval Returned value can be one of the following values:
1836 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1837 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1838 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)1839 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
1840 {
1841 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1842 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1843 }
1844
1845 /**
1846 * @brief Enable fast mode for the output channel.
1847 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1848 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1849 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1850 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1851 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1852 * @param TIMx Timer instance
1853 * @param Channel This parameter can be one of the following values:
1854 * @arg @ref LL_TIM_CHANNEL_CH1
1855 * @arg @ref LL_TIM_CHANNEL_CH2
1856 * @arg @ref LL_TIM_CHANNEL_CH3
1857 * @arg @ref LL_TIM_CHANNEL_CH4
1858 * @retval None
1859 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1860 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1861 {
1862 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1863 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1864 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1865
1866 }
1867
1868 /**
1869 * @brief Disable fast mode for the output channel.
1870 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1871 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1872 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1873 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1874 * @param TIMx Timer instance
1875 * @param Channel This parameter can be one of the following values:
1876 * @arg @ref LL_TIM_CHANNEL_CH1
1877 * @arg @ref LL_TIM_CHANNEL_CH2
1878 * @arg @ref LL_TIM_CHANNEL_CH3
1879 * @arg @ref LL_TIM_CHANNEL_CH4
1880 * @retval None
1881 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1882 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1883 {
1884 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1885 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1886 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1887
1888 }
1889
1890 /**
1891 * @brief Indicates whether fast mode is enabled for the output channel.
1892 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1893 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1894 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1895 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1896 * @param TIMx Timer instance
1897 * @param Channel This parameter can be one of the following values:
1898 * @arg @ref LL_TIM_CHANNEL_CH1
1899 * @arg @ref LL_TIM_CHANNEL_CH2
1900 * @arg @ref LL_TIM_CHANNEL_CH3
1901 * @arg @ref LL_TIM_CHANNEL_CH4
1902 * @retval State of bit (1 or 0).
1903 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)1904 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
1905 {
1906 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1907 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1908 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1909 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1914 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1915 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1916 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1917 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1918 * @param TIMx Timer instance
1919 * @param Channel This parameter can be one of the following values:
1920 * @arg @ref LL_TIM_CHANNEL_CH1
1921 * @arg @ref LL_TIM_CHANNEL_CH2
1922 * @arg @ref LL_TIM_CHANNEL_CH3
1923 * @arg @ref LL_TIM_CHANNEL_CH4
1924 * @retval None
1925 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1926 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1927 {
1928 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1929 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1930 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1931 }
1932
1933 /**
1934 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1935 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1936 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1937 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1938 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1939 * @param TIMx Timer instance
1940 * @param Channel This parameter can be one of the following values:
1941 * @arg @ref LL_TIM_CHANNEL_CH1
1942 * @arg @ref LL_TIM_CHANNEL_CH2
1943 * @arg @ref LL_TIM_CHANNEL_CH3
1944 * @arg @ref LL_TIM_CHANNEL_CH4
1945 * @retval None
1946 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1947 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1948 {
1949 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1950 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1951 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1952 }
1953
1954 /**
1955 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1956 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1957 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1958 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1959 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1960 * @param TIMx Timer instance
1961 * @param Channel This parameter can be one of the following values:
1962 * @arg @ref LL_TIM_CHANNEL_CH1
1963 * @arg @ref LL_TIM_CHANNEL_CH2
1964 * @arg @ref LL_TIM_CHANNEL_CH3
1965 * @arg @ref LL_TIM_CHANNEL_CH4
1966 * @retval State of bit (1 or 0).
1967 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)1968 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
1969 {
1970 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1971 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1972 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1973 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1974 }
1975
1976 /**
1977 * @brief Enable clearing the output channel on an external event.
1978 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1979 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1980 * or not a timer instance can clear the OCxREF signal on an external event.
1981 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1982 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1983 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1984 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1985 * @param TIMx Timer instance
1986 * @param Channel This parameter can be one of the following values:
1987 * @arg @ref LL_TIM_CHANNEL_CH1
1988 * @arg @ref LL_TIM_CHANNEL_CH2
1989 * @arg @ref LL_TIM_CHANNEL_CH3
1990 * @arg @ref LL_TIM_CHANNEL_CH4
1991 * @retval None
1992 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1993 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1994 {
1995 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1996 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1997 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1998 }
1999
2000 /**
2001 * @brief Disable clearing the output channel on an external event.
2002 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2003 * or not a timer instance can clear the OCxREF signal on an external event.
2004 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2005 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2006 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2007 * CCMR2 OC4CE LL_TIM_OC_DisableClear
2008 * @param TIMx Timer instance
2009 * @param Channel This parameter can be one of the following values:
2010 * @arg @ref LL_TIM_CHANNEL_CH1
2011 * @arg @ref LL_TIM_CHANNEL_CH2
2012 * @arg @ref LL_TIM_CHANNEL_CH3
2013 * @arg @ref LL_TIM_CHANNEL_CH4
2014 * @retval None
2015 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2016 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2017 {
2018 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2019 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2020 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2021 }
2022
2023 /**
2024 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2025 * @note This function enables clearing the output channel on an external event.
2026 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2027 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2028 * or not a timer instance can clear the OCxREF signal on an external event.
2029 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2030 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2031 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2032 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2033 * @param TIMx Timer instance
2034 * @param Channel This parameter can be one of the following values:
2035 * @arg @ref LL_TIM_CHANNEL_CH1
2036 * @arg @ref LL_TIM_CHANNEL_CH2
2037 * @arg @ref LL_TIM_CHANNEL_CH3
2038 * @arg @ref LL_TIM_CHANNEL_CH4
2039 * @retval State of bit (1 or 0).
2040 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2041 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2042 {
2043 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2044 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2045 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2046 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2047 }
2048
2049 /**
2050 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2051 * the Ocx and OCxN signals).
2052 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2053 * dead-time insertion feature is supported by a timer instance.
2054 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2055 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2056 * @param TIMx Timer instance
2057 * @param DeadTime between Min_Data=0 and Max_Data=255
2058 * @retval None
2059 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2060 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2061 {
2062 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2063 }
2064
2065 /**
2066 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2067 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2068 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2069 * whether or not a timer instance supports a 32 bits counter.
2070 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2071 * output channel 1 is supported by a timer instance.
2072 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2073 * @param TIMx Timer instance
2074 * @param CompareValue between Min_Data=0 and Max_Data=65535
2075 * @retval None
2076 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2077 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2078 {
2079 WRITE_REG(TIMx->CCR1, CompareValue);
2080 }
2081
2082 /**
2083 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2084 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2085 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2086 * whether or not a timer instance supports a 32 bits counter.
2087 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2088 * output channel 2 is supported by a timer instance.
2089 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2090 * @param TIMx Timer instance
2091 * @param CompareValue between Min_Data=0 and Max_Data=65535
2092 * @retval None
2093 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2094 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2095 {
2096 WRITE_REG(TIMx->CCR2, CompareValue);
2097 }
2098
2099 /**
2100 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2101 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2102 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2103 * whether or not a timer instance supports a 32 bits counter.
2104 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2105 * output channel is supported by a timer instance.
2106 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2107 * @param TIMx Timer instance
2108 * @param CompareValue between Min_Data=0 and Max_Data=65535
2109 * @retval None
2110 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2111 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2112 {
2113 WRITE_REG(TIMx->CCR3, CompareValue);
2114 }
2115
2116 /**
2117 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2118 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2119 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2120 * whether or not a timer instance supports a 32 bits counter.
2121 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2122 * output channel 4 is supported by a timer instance.
2123 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2124 * @param TIMx Timer instance
2125 * @param CompareValue between Min_Data=0 and Max_Data=65535
2126 * @retval None
2127 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2128 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2129 {
2130 WRITE_REG(TIMx->CCR4, CompareValue);
2131 }
2132
2133 /**
2134 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2135 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2136 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2137 * whether or not a timer instance supports a 32 bits counter.
2138 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2139 * output channel 1 is supported by a timer instance.
2140 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2141 * @param TIMx Timer instance
2142 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2143 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2144 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2145 {
2146 return (uint32_t)(READ_REG(TIMx->CCR1));
2147 }
2148
2149 /**
2150 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2151 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2152 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2153 * whether or not a timer instance supports a 32 bits counter.
2154 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2155 * output channel 2 is supported by a timer instance.
2156 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2157 * @param TIMx Timer instance
2158 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2159 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2160 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2161 {
2162 return (uint32_t)(READ_REG(TIMx->CCR2));
2163 }
2164
2165 /**
2166 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2167 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2168 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2169 * whether or not a timer instance supports a 32 bits counter.
2170 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2171 * output channel 3 is supported by a timer instance.
2172 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2173 * @param TIMx Timer instance
2174 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2175 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2176 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2177 {
2178 return (uint32_t)(READ_REG(TIMx->CCR3));
2179 }
2180
2181 /**
2182 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2183 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2184 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2185 * whether or not a timer instance supports a 32 bits counter.
2186 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2187 * output channel 4 is supported by a timer instance.
2188 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2189 * @param TIMx Timer instance
2190 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2191 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2192 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2193 {
2194 return (uint32_t)(READ_REG(TIMx->CCR4));
2195 }
2196
2197 /**
2198 * @}
2199 */
2200
2201 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2202 * @{
2203 */
2204 /**
2205 * @brief Configure input channel.
2206 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2207 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2208 * CCMR1 IC1F LL_TIM_IC_Config\n
2209 * CCMR1 CC2S LL_TIM_IC_Config\n
2210 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2211 * CCMR1 IC2F LL_TIM_IC_Config\n
2212 * CCMR2 CC3S LL_TIM_IC_Config\n
2213 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2214 * CCMR2 IC3F LL_TIM_IC_Config\n
2215 * CCMR2 CC4S LL_TIM_IC_Config\n
2216 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2217 * CCMR2 IC4F LL_TIM_IC_Config\n
2218 * CCER CC1P LL_TIM_IC_Config\n
2219 * CCER CC1NP LL_TIM_IC_Config\n
2220 * CCER CC2P LL_TIM_IC_Config\n
2221 * CCER CC2NP LL_TIM_IC_Config\n
2222 * CCER CC3P LL_TIM_IC_Config\n
2223 * CCER CC3NP LL_TIM_IC_Config\n
2224 * CCER CC4P LL_TIM_IC_Config\n
2225 * CCER CC4NP LL_TIM_IC_Config
2226 * @param TIMx Timer instance
2227 * @param Channel This parameter can be one of the following values:
2228 * @arg @ref LL_TIM_CHANNEL_CH1
2229 * @arg @ref LL_TIM_CHANNEL_CH2
2230 * @arg @ref LL_TIM_CHANNEL_CH3
2231 * @arg @ref LL_TIM_CHANNEL_CH4
2232 * @param Configuration This parameter must be a combination of all the following values:
2233 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2234 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2235 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2236 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2237 * @retval None
2238 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2239 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2240 {
2241 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2242 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2243 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2244 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2245 << SHIFT_TAB_ICxx[iChannel]);
2246 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2247 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2248 }
2249
2250 /**
2251 * @brief Set the active input.
2252 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2253 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2254 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2255 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2256 * @param TIMx Timer instance
2257 * @param Channel This parameter can be one of the following values:
2258 * @arg @ref LL_TIM_CHANNEL_CH1
2259 * @arg @ref LL_TIM_CHANNEL_CH2
2260 * @arg @ref LL_TIM_CHANNEL_CH3
2261 * @arg @ref LL_TIM_CHANNEL_CH4
2262 * @param ICActiveInput This parameter can be one of the following values:
2263 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2264 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2265 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2266 * @retval None
2267 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2268 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2269 {
2270 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2271 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2272 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2273 }
2274
2275 /**
2276 * @brief Get the current active input.
2277 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2278 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2279 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2280 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2281 * @param TIMx Timer instance
2282 * @param Channel This parameter can be one of the following values:
2283 * @arg @ref LL_TIM_CHANNEL_CH1
2284 * @arg @ref LL_TIM_CHANNEL_CH2
2285 * @arg @ref LL_TIM_CHANNEL_CH3
2286 * @arg @ref LL_TIM_CHANNEL_CH4
2287 * @retval Returned value can be one of the following values:
2288 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2289 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2290 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2291 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2292 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2293 {
2294 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2295 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2296 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2297 }
2298
2299 /**
2300 * @brief Set the prescaler of input channel.
2301 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2302 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2303 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2304 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2305 * @param TIMx Timer instance
2306 * @param Channel This parameter can be one of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH2
2309 * @arg @ref LL_TIM_CHANNEL_CH3
2310 * @arg @ref LL_TIM_CHANNEL_CH4
2311 * @param ICPrescaler This parameter can be one of the following values:
2312 * @arg @ref LL_TIM_ICPSC_DIV1
2313 * @arg @ref LL_TIM_ICPSC_DIV2
2314 * @arg @ref LL_TIM_ICPSC_DIV4
2315 * @arg @ref LL_TIM_ICPSC_DIV8
2316 * @retval None
2317 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2318 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2319 {
2320 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2321 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2322 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2323 }
2324
2325 /**
2326 * @brief Get the current prescaler value acting on an input channel.
2327 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2328 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2329 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2330 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2331 * @param TIMx Timer instance
2332 * @param Channel This parameter can be one of the following values:
2333 * @arg @ref LL_TIM_CHANNEL_CH1
2334 * @arg @ref LL_TIM_CHANNEL_CH2
2335 * @arg @ref LL_TIM_CHANNEL_CH3
2336 * @arg @ref LL_TIM_CHANNEL_CH4
2337 * @retval Returned value can be one of the following values:
2338 * @arg @ref LL_TIM_ICPSC_DIV1
2339 * @arg @ref LL_TIM_ICPSC_DIV2
2340 * @arg @ref LL_TIM_ICPSC_DIV4
2341 * @arg @ref LL_TIM_ICPSC_DIV8
2342 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2343 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2344 {
2345 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2346 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2347 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2348 }
2349
2350 /**
2351 * @brief Set the input filter duration.
2352 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2353 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2354 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2355 * CCMR2 IC4F LL_TIM_IC_SetFilter
2356 * @param TIMx Timer instance
2357 * @param Channel This parameter can be one of the following values:
2358 * @arg @ref LL_TIM_CHANNEL_CH1
2359 * @arg @ref LL_TIM_CHANNEL_CH2
2360 * @arg @ref LL_TIM_CHANNEL_CH3
2361 * @arg @ref LL_TIM_CHANNEL_CH4
2362 * @param ICFilter This parameter can be one of the following values:
2363 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2364 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2365 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2366 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2367 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2368 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2369 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2370 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2371 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2372 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2373 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2374 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2375 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2376 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2377 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2378 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2379 * @retval None
2380 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2381 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2382 {
2383 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2384 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2385 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2386 }
2387
2388 /**
2389 * @brief Get the input filter duration.
2390 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2391 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2392 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2393 * CCMR2 IC4F LL_TIM_IC_GetFilter
2394 * @param TIMx Timer instance
2395 * @param Channel This parameter can be one of the following values:
2396 * @arg @ref LL_TIM_CHANNEL_CH1
2397 * @arg @ref LL_TIM_CHANNEL_CH2
2398 * @arg @ref LL_TIM_CHANNEL_CH3
2399 * @arg @ref LL_TIM_CHANNEL_CH4
2400 * @retval Returned value can be one of the following values:
2401 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2402 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2403 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2404 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2405 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2406 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2407 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2408 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2409 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2410 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2411 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2412 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2413 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2414 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2415 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2416 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2417 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2418 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2419 {
2420 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2421 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2422 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2423 }
2424
2425 /**
2426 * @brief Set the input channel polarity.
2427 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2428 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2429 * CCER CC2P LL_TIM_IC_SetPolarity\n
2430 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2431 * CCER CC3P LL_TIM_IC_SetPolarity\n
2432 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2433 * CCER CC4P LL_TIM_IC_SetPolarity\n
2434 * CCER CC4NP LL_TIM_IC_SetPolarity
2435 * @param TIMx Timer instance
2436 * @param Channel This parameter can be one of the following values:
2437 * @arg @ref LL_TIM_CHANNEL_CH1
2438 * @arg @ref LL_TIM_CHANNEL_CH2
2439 * @arg @ref LL_TIM_CHANNEL_CH3
2440 * @arg @ref LL_TIM_CHANNEL_CH4
2441 * @param ICPolarity This parameter can be one of the following values:
2442 * @arg @ref LL_TIM_IC_POLARITY_RISING
2443 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2444 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2445 * @retval None
2446 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2447 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2448 {
2449 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2450 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2451 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2452 }
2453
2454 /**
2455 * @brief Get the current input channel polarity.
2456 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2457 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2458 * CCER CC2P LL_TIM_IC_GetPolarity\n
2459 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2460 * CCER CC3P LL_TIM_IC_GetPolarity\n
2461 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2462 * CCER CC4P LL_TIM_IC_GetPolarity\n
2463 * CCER CC4NP LL_TIM_IC_GetPolarity
2464 * @param TIMx Timer instance
2465 * @param Channel This parameter can be one of the following values:
2466 * @arg @ref LL_TIM_CHANNEL_CH1
2467 * @arg @ref LL_TIM_CHANNEL_CH2
2468 * @arg @ref LL_TIM_CHANNEL_CH3
2469 * @arg @ref LL_TIM_CHANNEL_CH4
2470 * @retval Returned value can be one of the following values:
2471 * @arg @ref LL_TIM_IC_POLARITY_RISING
2472 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2473 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2474 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2475 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2476 {
2477 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2478 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2479 SHIFT_TAB_CCxP[iChannel]);
2480 }
2481
2482 /**
2483 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2484 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2485 * a timer instance provides an XOR input.
2486 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2487 * @param TIMx Timer instance
2488 * @retval None
2489 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2490 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2491 {
2492 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2493 }
2494
2495 /**
2496 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2497 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2498 * a timer instance provides an XOR input.
2499 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2500 * @param TIMx Timer instance
2501 * @retval None
2502 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2503 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2504 {
2505 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2506 }
2507
2508 /**
2509 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2510 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2511 * a timer instance provides an XOR input.
2512 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2513 * @param TIMx Timer instance
2514 * @retval State of bit (1 or 0).
2515 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)2516 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
2517 {
2518 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2519 }
2520
2521 /**
2522 * @brief Get captured value for input channel 1.
2523 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2524 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2525 * whether or not a timer instance supports a 32 bits counter.
2526 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2527 * input channel 1 is supported by a timer instance.
2528 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2529 * @param TIMx Timer instance
2530 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2531 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)2532 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
2533 {
2534 return (uint32_t)(READ_REG(TIMx->CCR1));
2535 }
2536
2537 /**
2538 * @brief Get captured value for input channel 2.
2539 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2540 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2541 * whether or not a timer instance supports a 32 bits counter.
2542 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2543 * input channel 2 is supported by a timer instance.
2544 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2545 * @param TIMx Timer instance
2546 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2547 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)2548 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
2549 {
2550 return (uint32_t)(READ_REG(TIMx->CCR2));
2551 }
2552
2553 /**
2554 * @brief Get captured value for input channel 3.
2555 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2556 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2557 * whether or not a timer instance supports a 32 bits counter.
2558 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2559 * input channel 3 is supported by a timer instance.
2560 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2561 * @param TIMx Timer instance
2562 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2563 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)2564 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
2565 {
2566 return (uint32_t)(READ_REG(TIMx->CCR3));
2567 }
2568
2569 /**
2570 * @brief Get captured value for input channel 4.
2571 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2572 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2573 * whether or not a timer instance supports a 32 bits counter.
2574 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2575 * input channel 4 is supported by a timer instance.
2576 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2577 * @param TIMx Timer instance
2578 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2579 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)2580 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
2581 {
2582 return (uint32_t)(READ_REG(TIMx->CCR4));
2583 }
2584
2585 /**
2586 * @}
2587 */
2588
2589 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2590 * @{
2591 */
2592 /**
2593 * @brief Enable external clock mode 2.
2594 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2595 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2596 * whether or not a timer instance supports external clock mode2.
2597 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2598 * @param TIMx Timer instance
2599 * @retval None
2600 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2601 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2602 {
2603 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2604 }
2605
2606 /**
2607 * @brief Disable external clock mode 2.
2608 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2609 * whether or not a timer instance supports external clock mode2.
2610 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2611 * @param TIMx Timer instance
2612 * @retval None
2613 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2614 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2615 {
2616 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2617 }
2618
2619 /**
2620 * @brief Indicate whether external clock mode 2 is enabled.
2621 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2622 * whether or not a timer instance supports external clock mode2.
2623 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2624 * @param TIMx Timer instance
2625 * @retval State of bit (1 or 0).
2626 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)2627 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
2628 {
2629 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2630 }
2631
2632 /**
2633 * @brief Set the clock source of the counter clock.
2634 * @note when selected clock source is external clock mode 1, the timer input
2635 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2636 * function. This timer input must be configured by calling
2637 * the @ref LL_TIM_IC_Config() function.
2638 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2639 * whether or not a timer instance supports external clock mode1.
2640 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2641 * whether or not a timer instance supports external clock mode2.
2642 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2643 * SMCR ECE LL_TIM_SetClockSource
2644 * @param TIMx Timer instance
2645 * @param ClockSource This parameter can be one of the following values:
2646 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2647 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2648 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2649 * @retval None
2650 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2651 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2652 {
2653 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2654 }
2655
2656 /**
2657 * @brief Set the encoder interface mode.
2658 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2659 * whether or not a timer instance supports the encoder mode.
2660 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2661 * @param TIMx Timer instance
2662 * @param EncoderMode This parameter can be one of the following values:
2663 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2664 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2665 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2666 * @retval None
2667 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2668 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2669 {
2670 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2671 }
2672
2673 /**
2674 * @}
2675 */
2676
2677 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2678 * @{
2679 */
2680 /**
2681 * @brief Set the trigger output (TRGO) used for timer synchronization .
2682 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2683 * whether or not a timer instance can operate as a master timer.
2684 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2685 * @param TIMx Timer instance
2686 * @param TimerSynchronization This parameter can be one of the following values:
2687 * @arg @ref LL_TIM_TRGO_RESET
2688 * @arg @ref LL_TIM_TRGO_ENABLE
2689 * @arg @ref LL_TIM_TRGO_UPDATE
2690 * @arg @ref LL_TIM_TRGO_CC1IF
2691 * @arg @ref LL_TIM_TRGO_OC1REF
2692 * @arg @ref LL_TIM_TRGO_OC2REF
2693 * @arg @ref LL_TIM_TRGO_OC3REF
2694 * @arg @ref LL_TIM_TRGO_OC4REF
2695 * @retval None
2696 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2697 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2698 {
2699 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2700 }
2701
2702 /**
2703 * @brief Set the synchronization mode of a slave timer.
2704 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2705 * a timer instance can operate as a slave timer.
2706 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2707 * @param TIMx Timer instance
2708 * @param SlaveMode This parameter can be one of the following values:
2709 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2710 * @arg @ref LL_TIM_SLAVEMODE_RESET
2711 * @arg @ref LL_TIM_SLAVEMODE_GATED
2712 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2713 * @retval None
2714 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2715 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2716 {
2717 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2718 }
2719
2720 /**
2721 * @brief Set the selects the trigger input to be used to synchronize the counter.
2722 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2723 * a timer instance can operate as a slave timer.
2724 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2725 * @param TIMx Timer instance
2726 * @param TriggerInput This parameter can be one of the following values:
2727 * @arg @ref LL_TIM_TS_ITR0
2728 * @arg @ref LL_TIM_TS_ITR1
2729 * @arg @ref LL_TIM_TS_ITR2
2730 * @arg @ref LL_TIM_TS_ITR3
2731 * @arg @ref LL_TIM_TS_TI1F_ED
2732 * @arg @ref LL_TIM_TS_TI1FP1
2733 * @arg @ref LL_TIM_TS_TI2FP2
2734 * @arg @ref LL_TIM_TS_ETRF
2735 * @retval None
2736 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2737 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2738 {
2739 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2740 }
2741
2742 /**
2743 * @brief Enable the Master/Slave mode.
2744 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2745 * a timer instance can operate as a slave timer.
2746 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2747 * @param TIMx Timer instance
2748 * @retval None
2749 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2750 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2751 {
2752 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2753 }
2754
2755 /**
2756 * @brief Disable the Master/Slave mode.
2757 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2758 * a timer instance can operate as a slave timer.
2759 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2760 * @param TIMx Timer instance
2761 * @retval None
2762 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2763 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2764 {
2765 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2766 }
2767
2768 /**
2769 * @brief Indicates whether the Master/Slave mode is enabled.
2770 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2771 * a timer instance can operate as a slave timer.
2772 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2773 * @param TIMx Timer instance
2774 * @retval State of bit (1 or 0).
2775 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)2776 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
2777 {
2778 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2779 }
2780
2781 /**
2782 * @brief Configure the external trigger (ETR) input.
2783 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2784 * a timer instance provides an external trigger input.
2785 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2786 * SMCR ETPS LL_TIM_ConfigETR\n
2787 * SMCR ETF LL_TIM_ConfigETR
2788 * @param TIMx Timer instance
2789 * @param ETRPolarity This parameter can be one of the following values:
2790 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2791 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2792 * @param ETRPrescaler This parameter can be one of the following values:
2793 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2794 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2795 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2796 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2797 * @param ETRFilter This parameter can be one of the following values:
2798 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2799 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2800 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2801 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2802 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2803 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2804 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2805 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2806 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2807 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2808 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2809 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2810 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2811 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2812 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2813 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2814 * @retval None
2815 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2816 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2817 uint32_t ETRFilter)
2818 {
2819 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2820 }
2821
2822 /**
2823 * @}
2824 */
2825
2826 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2827 * @{
2828 */
2829 /**
2830 * @brief Enable the break function.
2831 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2832 * a timer instance provides a break input.
2833 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2834 * @param TIMx Timer instance
2835 * @retval None
2836 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2837 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2838 {
2839 __IO uint32_t tmpreg;
2840 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2841 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2842 tmpreg = READ_REG(TIMx->BDTR);
2843 (void)(tmpreg);
2844 }
2845
2846 /**
2847 * @brief Disable the break function.
2848 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2849 * @param TIMx Timer instance
2850 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2851 * a timer instance provides a break input.
2852 * @retval None
2853 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2854 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2855 {
2856 __IO uint32_t tmpreg;
2857 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2858 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2859 tmpreg = READ_REG(TIMx->BDTR);
2860 (void)(tmpreg);
2861 }
2862
2863 /**
2864 * @brief Configure the break input.
2865 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2866 * a timer instance provides a break input.
2867 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2868 * @param TIMx Timer instance
2869 * @param BreakPolarity This parameter can be one of the following values:
2870 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2871 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2872 * @retval None
2873 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2874 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2875 {
2876 __IO uint32_t tmpreg;
2877 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2878 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2879 tmpreg = READ_REG(TIMx->BDTR);
2880 (void)(tmpreg);
2881 }
2882
2883 /**
2884 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2885 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2886 * a timer instance provides a break input.
2887 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2888 * BDTR OSSR LL_TIM_SetOffStates
2889 * @param TIMx Timer instance
2890 * @param OffStateIdle This parameter can be one of the following values:
2891 * @arg @ref LL_TIM_OSSI_DISABLE
2892 * @arg @ref LL_TIM_OSSI_ENABLE
2893 * @param OffStateRun This parameter can be one of the following values:
2894 * @arg @ref LL_TIM_OSSR_DISABLE
2895 * @arg @ref LL_TIM_OSSR_ENABLE
2896 * @retval None
2897 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2898 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2899 {
2900 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2901 }
2902
2903 /**
2904 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2905 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2906 * a timer instance provides a break input.
2907 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2908 * @param TIMx Timer instance
2909 * @retval None
2910 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2911 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2912 {
2913 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2914 }
2915
2916 /**
2917 * @brief Disable automatic output (MOE can be set only by software).
2918 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2919 * a timer instance provides a break input.
2920 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2921 * @param TIMx Timer instance
2922 * @retval None
2923 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2924 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2925 {
2926 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2927 }
2928
2929 /**
2930 * @brief Indicate whether automatic output is enabled.
2931 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2932 * a timer instance provides a break input.
2933 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2934 * @param TIMx Timer instance
2935 * @retval State of bit (1 or 0).
2936 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)2937 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
2938 {
2939 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2940 }
2941
2942 /**
2943 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2944 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2945 * software and is reset in case of break or break2 event
2946 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2947 * a timer instance provides a break input.
2948 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2949 * @param TIMx Timer instance
2950 * @retval None
2951 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2952 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2953 {
2954 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2955 }
2956
2957 /**
2958 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2959 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2960 * software and is reset in case of break or break2 event.
2961 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2962 * a timer instance provides a break input.
2963 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2964 * @param TIMx Timer instance
2965 * @retval None
2966 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)2967 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2968 {
2969 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2970 }
2971
2972 /**
2973 * @brief Indicates whether outputs are enabled.
2974 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2975 * a timer instance provides a break input.
2976 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2977 * @param TIMx Timer instance
2978 * @retval State of bit (1 or 0).
2979 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)2980 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
2981 {
2982 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
2983 }
2984
2985 /**
2986 * @}
2987 */
2988
2989 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2990 * @{
2991 */
2992 /**
2993 * @brief Configures the timer DMA burst feature.
2994 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2995 * not a timer instance supports the DMA burst mode.
2996 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2997 * DCR DBA LL_TIM_ConfigDMABurst
2998 * @param TIMx Timer instance
2999 * @param DMABurstBaseAddress This parameter can be one of the following values:
3000 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3001 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3002 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3003 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3004 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3005 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3006 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3007 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3008 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3009 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3010 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3011 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3012 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3013 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3014 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3015 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3016 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3017 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3018 * @param DMABurstLength This parameter can be one of the following values:
3019 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3020 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3021 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3022 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3023 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3024 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3025 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3026 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3027 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3028 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3029 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3030 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3031 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3032 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3033 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3034 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3035 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3036 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3037 * @retval None
3038 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3039 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3040 {
3041 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3042 }
3043
3044 /**
3045 * @}
3046 */
3047
3048 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3049 * @{
3050 */
3051 /**
3052 * @brief Remap TIM inputs (input channel, internal/external triggers).
3053 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3054 * a some timer inputs can be remapped.
3055 * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
3056 * @param TIMx Timer instance
3057 * @param Remap This parameter can be one of the following values:
3058 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3059 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
3060 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
3061 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
3062 *
3063 * @retval None
3064 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3065 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3066 {
3067 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3068 }
3069
3070 /**
3071 * @}
3072 */
3073
3074 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3075 * @{
3076 */
3077 /**
3078 * @brief Set the OCREF clear input source
3079 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3080 * @note This function can only be used in Output compare and PWM modes.
3081 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3082 * @param TIMx Timer instance
3083 * @param OCRefClearInputSource This parameter can be one of the following values:
3084 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3085 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3086 * @retval None
3087 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3088 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3089 {
3090 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3091 }
3092 /**
3093 * @}
3094 */
3095
3096 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3097 * @{
3098 */
3099 /**
3100 * @brief Clear the update interrupt flag (UIF).
3101 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3102 * @param TIMx Timer instance
3103 * @retval None
3104 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3105 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3106 {
3107 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3108 }
3109
3110 /**
3111 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3112 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3113 * @param TIMx Timer instance
3114 * @retval State of bit (1 or 0).
3115 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)3116 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
3117 {
3118 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3119 }
3120
3121 /**
3122 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3123 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3124 * @param TIMx Timer instance
3125 * @retval None
3126 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3127 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3128 {
3129 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3130 }
3131
3132 /**
3133 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3134 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3135 * @param TIMx Timer instance
3136 * @retval State of bit (1 or 0).
3137 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)3138 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
3139 {
3140 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3141 }
3142
3143 /**
3144 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3145 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3146 * @param TIMx Timer instance
3147 * @retval None
3148 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3149 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3150 {
3151 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3152 }
3153
3154 /**
3155 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3156 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3157 * @param TIMx Timer instance
3158 * @retval State of bit (1 or 0).
3159 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)3160 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
3161 {
3162 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3163 }
3164
3165 /**
3166 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3167 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3168 * @param TIMx Timer instance
3169 * @retval None
3170 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3171 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3172 {
3173 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3174 }
3175
3176 /**
3177 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3178 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3179 * @param TIMx Timer instance
3180 * @retval State of bit (1 or 0).
3181 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)3182 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
3183 {
3184 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3185 }
3186
3187 /**
3188 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3189 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3190 * @param TIMx Timer instance
3191 * @retval None
3192 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3193 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3194 {
3195 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3196 }
3197
3198 /**
3199 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3200 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3201 * @param TIMx Timer instance
3202 * @retval State of bit (1 or 0).
3203 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)3204 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
3205 {
3206 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3207 }
3208
3209 /**
3210 * @brief Clear the commutation interrupt flag (COMIF).
3211 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3212 * @param TIMx Timer instance
3213 * @retval None
3214 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3215 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3216 {
3217 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3218 }
3219
3220 /**
3221 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3222 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3223 * @param TIMx Timer instance
3224 * @retval State of bit (1 or 0).
3225 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)3226 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
3227 {
3228 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3229 }
3230
3231 /**
3232 * @brief Clear the trigger interrupt flag (TIF).
3233 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3234 * @param TIMx Timer instance
3235 * @retval None
3236 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3237 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3238 {
3239 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3240 }
3241
3242 /**
3243 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3244 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3245 * @param TIMx Timer instance
3246 * @retval State of bit (1 or 0).
3247 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)3248 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
3249 {
3250 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3251 }
3252
3253 /**
3254 * @brief Clear the break interrupt flag (BIF).
3255 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3256 * @param TIMx Timer instance
3257 * @retval None
3258 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3259 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3260 {
3261 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3262 }
3263
3264 /**
3265 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3266 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3267 * @param TIMx Timer instance
3268 * @retval State of bit (1 or 0).
3269 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)3270 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
3271 {
3272 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3273 }
3274
3275 /**
3276 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3277 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3278 * @param TIMx Timer instance
3279 * @retval None
3280 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3281 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3282 {
3283 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3284 }
3285
3286 /**
3287 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
3288 * (Capture/Compare 1 interrupt is pending).
3289 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3290 * @param TIMx Timer instance
3291 * @retval State of bit (1 or 0).
3292 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)3293 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
3294 {
3295 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3296 }
3297
3298 /**
3299 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3300 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3301 * @param TIMx Timer instance
3302 * @retval None
3303 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3304 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3305 {
3306 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3307 }
3308
3309 /**
3310 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
3311 * (Capture/Compare 2 over-capture interrupt is pending).
3312 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3313 * @param TIMx Timer instance
3314 * @retval State of bit (1 or 0).
3315 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)3316 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
3317 {
3318 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3319 }
3320
3321 /**
3322 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3323 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3324 * @param TIMx Timer instance
3325 * @retval None
3326 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3327 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3328 {
3329 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3330 }
3331
3332 /**
3333 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
3334 * (Capture/Compare 3 over-capture interrupt is pending).
3335 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3336 * @param TIMx Timer instance
3337 * @retval State of bit (1 or 0).
3338 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)3339 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
3340 {
3341 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3342 }
3343
3344 /**
3345 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3346 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3347 * @param TIMx Timer instance
3348 * @retval None
3349 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3350 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3351 {
3352 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3353 }
3354
3355 /**
3356 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
3357 * (Capture/Compare 4 over-capture interrupt is pending).
3358 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3359 * @param TIMx Timer instance
3360 * @retval State of bit (1 or 0).
3361 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)3362 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
3363 {
3364 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3365 }
3366
3367 /**
3368 * @}
3369 */
3370
3371 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3372 * @{
3373 */
3374 /**
3375 * @brief Enable update interrupt (UIE).
3376 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3377 * @param TIMx Timer instance
3378 * @retval None
3379 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3380 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3381 {
3382 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3383 }
3384
3385 /**
3386 * @brief Disable update interrupt (UIE).
3387 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3388 * @param TIMx Timer instance
3389 * @retval None
3390 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3391 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3392 {
3393 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3394 }
3395
3396 /**
3397 * @brief Indicates whether the update interrupt (UIE) is enabled.
3398 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3399 * @param TIMx Timer instance
3400 * @retval State of bit (1 or 0).
3401 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)3402 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
3403 {
3404 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3405 }
3406
3407 /**
3408 * @brief Enable capture/compare 1 interrupt (CC1IE).
3409 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3410 * @param TIMx Timer instance
3411 * @retval None
3412 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3413 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3414 {
3415 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3416 }
3417
3418 /**
3419 * @brief Disable capture/compare 1 interrupt (CC1IE).
3420 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3421 * @param TIMx Timer instance
3422 * @retval None
3423 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3424 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3425 {
3426 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3427 }
3428
3429 /**
3430 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3431 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3432 * @param TIMx Timer instance
3433 * @retval State of bit (1 or 0).
3434 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)3435 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
3436 {
3437 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3438 }
3439
3440 /**
3441 * @brief Enable capture/compare 2 interrupt (CC2IE).
3442 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3443 * @param TIMx Timer instance
3444 * @retval None
3445 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3446 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3447 {
3448 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3449 }
3450
3451 /**
3452 * @brief Disable capture/compare 2 interrupt (CC2IE).
3453 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3454 * @param TIMx Timer instance
3455 * @retval None
3456 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3457 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3458 {
3459 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3460 }
3461
3462 /**
3463 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3464 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3465 * @param TIMx Timer instance
3466 * @retval State of bit (1 or 0).
3467 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)3468 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
3469 {
3470 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3471 }
3472
3473 /**
3474 * @brief Enable capture/compare 3 interrupt (CC3IE).
3475 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3476 * @param TIMx Timer instance
3477 * @retval None
3478 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3479 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3480 {
3481 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3482 }
3483
3484 /**
3485 * @brief Disable capture/compare 3 interrupt (CC3IE).
3486 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3487 * @param TIMx Timer instance
3488 * @retval None
3489 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3490 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3491 {
3492 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3493 }
3494
3495 /**
3496 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3497 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3498 * @param TIMx Timer instance
3499 * @retval State of bit (1 or 0).
3500 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)3501 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
3502 {
3503 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3504 }
3505
3506 /**
3507 * @brief Enable capture/compare 4 interrupt (CC4IE).
3508 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3509 * @param TIMx Timer instance
3510 * @retval None
3511 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3512 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3513 {
3514 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3515 }
3516
3517 /**
3518 * @brief Disable capture/compare 4 interrupt (CC4IE).
3519 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3520 * @param TIMx Timer instance
3521 * @retval None
3522 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3523 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3524 {
3525 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3526 }
3527
3528 /**
3529 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3530 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3531 * @param TIMx Timer instance
3532 * @retval State of bit (1 or 0).
3533 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)3534 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
3535 {
3536 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3537 }
3538
3539 /**
3540 * @brief Enable commutation interrupt (COMIE).
3541 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3542 * @param TIMx Timer instance
3543 * @retval None
3544 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3545 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3546 {
3547 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3548 }
3549
3550 /**
3551 * @brief Disable commutation interrupt (COMIE).
3552 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3553 * @param TIMx Timer instance
3554 * @retval None
3555 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3556 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3557 {
3558 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3559 }
3560
3561 /**
3562 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3563 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3564 * @param TIMx Timer instance
3565 * @retval State of bit (1 or 0).
3566 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)3567 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
3568 {
3569 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3570 }
3571
3572 /**
3573 * @brief Enable trigger interrupt (TIE).
3574 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3575 * @param TIMx Timer instance
3576 * @retval None
3577 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3578 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3579 {
3580 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3581 }
3582
3583 /**
3584 * @brief Disable trigger interrupt (TIE).
3585 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3586 * @param TIMx Timer instance
3587 * @retval None
3588 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3589 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3590 {
3591 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3592 }
3593
3594 /**
3595 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3596 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3597 * @param TIMx Timer instance
3598 * @retval State of bit (1 or 0).
3599 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)3600 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
3601 {
3602 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3603 }
3604
3605 /**
3606 * @brief Enable break interrupt (BIE).
3607 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3608 * @param TIMx Timer instance
3609 * @retval None
3610 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3611 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3612 {
3613 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3614 }
3615
3616 /**
3617 * @brief Disable break interrupt (BIE).
3618 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3619 * @param TIMx Timer instance
3620 * @retval None
3621 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3622 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3623 {
3624 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3625 }
3626
3627 /**
3628 * @brief Indicates whether the break interrupt (BIE) is enabled.
3629 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3630 * @param TIMx Timer instance
3631 * @retval State of bit (1 or 0).
3632 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)3633 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
3634 {
3635 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3636 }
3637
3638 /**
3639 * @}
3640 */
3641
3642 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
3643 * @{
3644 */
3645 /**
3646 * @brief Enable update DMA request (UDE).
3647 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3648 * @param TIMx Timer instance
3649 * @retval None
3650 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3651 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3652 {
3653 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3654 }
3655
3656 /**
3657 * @brief Disable update DMA request (UDE).
3658 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3659 * @param TIMx Timer instance
3660 * @retval None
3661 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3662 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3663 {
3664 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3665 }
3666
3667 /**
3668 * @brief Indicates whether the update DMA request (UDE) is enabled.
3669 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3670 * @param TIMx Timer instance
3671 * @retval State of bit (1 or 0).
3672 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)3673 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
3674 {
3675 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3676 }
3677
3678 /**
3679 * @brief Enable capture/compare 1 DMA request (CC1DE).
3680 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3681 * @param TIMx Timer instance
3682 * @retval None
3683 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3684 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3685 {
3686 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3687 }
3688
3689 /**
3690 * @brief Disable capture/compare 1 DMA request (CC1DE).
3691 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3692 * @param TIMx Timer instance
3693 * @retval None
3694 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3695 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3696 {
3697 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3698 }
3699
3700 /**
3701 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3702 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3703 * @param TIMx Timer instance
3704 * @retval State of bit (1 or 0).
3705 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)3706 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
3707 {
3708 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3709 }
3710
3711 /**
3712 * @brief Enable capture/compare 2 DMA request (CC2DE).
3713 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3714 * @param TIMx Timer instance
3715 * @retval None
3716 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3717 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3718 {
3719 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3720 }
3721
3722 /**
3723 * @brief Disable capture/compare 2 DMA request (CC2DE).
3724 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3725 * @param TIMx Timer instance
3726 * @retval None
3727 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3728 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3729 {
3730 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3731 }
3732
3733 /**
3734 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3735 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3736 * @param TIMx Timer instance
3737 * @retval State of bit (1 or 0).
3738 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)3739 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
3740 {
3741 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3742 }
3743
3744 /**
3745 * @brief Enable capture/compare 3 DMA request (CC3DE).
3746 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3747 * @param TIMx Timer instance
3748 * @retval None
3749 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3750 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3751 {
3752 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3753 }
3754
3755 /**
3756 * @brief Disable capture/compare 3 DMA request (CC3DE).
3757 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3758 * @param TIMx Timer instance
3759 * @retval None
3760 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3761 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3762 {
3763 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3764 }
3765
3766 /**
3767 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3768 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3769 * @param TIMx Timer instance
3770 * @retval State of bit (1 or 0).
3771 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)3772 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
3773 {
3774 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3775 }
3776
3777 /**
3778 * @brief Enable capture/compare 4 DMA request (CC4DE).
3779 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3780 * @param TIMx Timer instance
3781 * @retval None
3782 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3783 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3784 {
3785 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3786 }
3787
3788 /**
3789 * @brief Disable capture/compare 4 DMA request (CC4DE).
3790 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3791 * @param TIMx Timer instance
3792 * @retval None
3793 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3794 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3795 {
3796 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3797 }
3798
3799 /**
3800 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3801 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3802 * @param TIMx Timer instance
3803 * @retval State of bit (1 or 0).
3804 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)3805 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
3806 {
3807 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3808 }
3809
3810 /**
3811 * @brief Enable commutation DMA request (COMDE).
3812 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3813 * @param TIMx Timer instance
3814 * @retval None
3815 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3816 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3817 {
3818 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3819 }
3820
3821 /**
3822 * @brief Disable commutation DMA request (COMDE).
3823 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3824 * @param TIMx Timer instance
3825 * @retval None
3826 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3827 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3828 {
3829 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3830 }
3831
3832 /**
3833 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3834 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3835 * @param TIMx Timer instance
3836 * @retval State of bit (1 or 0).
3837 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)3838 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
3839 {
3840 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3841 }
3842
3843 /**
3844 * @brief Enable trigger interrupt (TDE).
3845 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3846 * @param TIMx Timer instance
3847 * @retval None
3848 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3849 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3850 {
3851 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3852 }
3853
3854 /**
3855 * @brief Disable trigger interrupt (TDE).
3856 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3857 * @param TIMx Timer instance
3858 * @retval None
3859 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3860 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3861 {
3862 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3863 }
3864
3865 /**
3866 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3867 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3868 * @param TIMx Timer instance
3869 * @retval State of bit (1 or 0).
3870 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)3871 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
3872 {
3873 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3874 }
3875
3876 /**
3877 * @}
3878 */
3879
3880 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3881 * @{
3882 */
3883 /**
3884 * @brief Generate an update event.
3885 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3886 * @param TIMx Timer instance
3887 * @retval None
3888 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3889 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3890 {
3891 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3892 }
3893
3894 /**
3895 * @brief Generate Capture/Compare 1 event.
3896 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3897 * @param TIMx Timer instance
3898 * @retval None
3899 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3900 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3901 {
3902 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3903 }
3904
3905 /**
3906 * @brief Generate Capture/Compare 2 event.
3907 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3908 * @param TIMx Timer instance
3909 * @retval None
3910 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3911 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3912 {
3913 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3914 }
3915
3916 /**
3917 * @brief Generate Capture/Compare 3 event.
3918 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3919 * @param TIMx Timer instance
3920 * @retval None
3921 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3922 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3923 {
3924 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3925 }
3926
3927 /**
3928 * @brief Generate Capture/Compare 4 event.
3929 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3930 * @param TIMx Timer instance
3931 * @retval None
3932 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3933 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3934 {
3935 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3936 }
3937
3938 /**
3939 * @brief Generate commutation event.
3940 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3941 * @param TIMx Timer instance
3942 * @retval None
3943 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)3944 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3945 {
3946 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3947 }
3948
3949 /**
3950 * @brief Generate trigger event.
3951 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3952 * @param TIMx Timer instance
3953 * @retval None
3954 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3955 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3956 {
3957 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3958 }
3959
3960 /**
3961 * @brief Generate break event.
3962 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3963 * @param TIMx Timer instance
3964 * @retval None
3965 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)3966 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3967 {
3968 SET_BIT(TIMx->EGR, TIM_EGR_BG);
3969 }
3970
3971 /**
3972 * @}
3973 */
3974
3975 #if defined(USE_FULL_LL_DRIVER)
3976 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3977 * @{
3978 */
3979
3980 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
3981 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3982 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
3983 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3984 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3985 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3986 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3987 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3988 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3989 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3990 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3991 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3992 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3993 /**
3994 * @}
3995 */
3996 #endif /* USE_FULL_LL_DRIVER */
3997
3998 /**
3999 * @}
4000 */
4001
4002 /**
4003 * @}
4004 */
4005
4006 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
4007
4008 /**
4009 * @}
4010 */
4011
4012 #ifdef __cplusplus
4013 }
4014 #endif
4015
4016 #endif /* __STM32F0xx_LL_TIM_H */
4017
