1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L4xx_LL_TIM_H
21 #define __STM32L4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_OR2 register */
122 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR1_RMP_SHIFT 16U
127 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
128 #if defined(ADC3)
129 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
130 #else
131 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
132 #endif /* ADC3 */
133 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
134 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
135 #if defined(ADC2) && defined(ADC3)
136 #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
137 #else
138 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
139 #endif /* ADC2 & ADC3 */
140 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
141 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
142 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
143
144 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
145 #define DT_DELAY_1 ((uint8_t)0x7F)
146 #define DT_DELAY_2 ((uint8_t)0x3F)
147 #define DT_DELAY_3 ((uint8_t)0x1F)
148 #define DT_DELAY_4 ((uint8_t)0x1F)
149
150 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
151 #define DT_RANGE_1 ((uint8_t)0x00)
152 #define DT_RANGE_2 ((uint8_t)0x80)
153 #define DT_RANGE_3 ((uint8_t)0xC0)
154 #define DT_RANGE_4 ((uint8_t)0xE0)
155
156 /** Legacy definitions for compatibility purpose
157 @cond 0
158 */
159 #if defined(DFSDM1_Channel0)
160 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
161 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
162 #endif /* DFSDM1_Channel0 */
163 /**
164 @endcond
165 */
166
167 /**
168 * @}
169 */
170
171 /* Private macros ------------------------------------------------------------*/
172 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
173 * @{
174 */
175 /** @brief Convert channel id into channel index.
176 * @param __CHANNEL__ This parameter can be one of the following values:
177 * @arg @ref LL_TIM_CHANNEL_CH1
178 * @arg @ref LL_TIM_CHANNEL_CH1N
179 * @arg @ref LL_TIM_CHANNEL_CH2
180 * @arg @ref LL_TIM_CHANNEL_CH2N
181 * @arg @ref LL_TIM_CHANNEL_CH3
182 * @arg @ref LL_TIM_CHANNEL_CH3N
183 * @arg @ref LL_TIM_CHANNEL_CH4
184 * @arg @ref LL_TIM_CHANNEL_CH5
185 * @arg @ref LL_TIM_CHANNEL_CH6
186 * @retval none
187 */
188 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
189 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
197
198 /** @brief Calculate the deadtime sampling period(in ps).
199 * @param __TIMCLK__ timer input clock frequency (in Hz).
200 * @param __CKD__ This parameter can be one of the following values:
201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
203 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
204 * @retval none
205 */
206 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
207 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
208 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
209 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
210 /**
211 * @}
212 */
213
214
215 /* Exported types ------------------------------------------------------------*/
216 #if defined(USE_FULL_LL_DRIVER)
217 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
218 * @{
219 */
220
221 /**
222 * @brief TIM Time Base configuration structure definition.
223 */
224 typedef struct
225 {
226 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
227 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetPrescaler().*/
231
232 uint32_t CounterMode; /*!< Specifies the counter mode.
233 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
234
235 This feature can be modified afterwards using unitary function
236 @ref LL_TIM_SetCounterMode().*/
237
238 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
239 Auto-Reload Register at the next update event.
240 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
241 Some timer instances may support 32 bits counters. In that case this parameter must
242 be a number between 0x0000 and 0xFFFFFFFF.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetAutoReload().*/
246
247 uint32_t ClockDivision; /*!< Specifies the clock division.
248 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_SetClockDivision().*/
252
253 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
254 reaches zero, an update event is generated and counting restarts
255 from the RCR value (N).
256 This means in PWM mode that (N+1) corresponds to:
257 - the number of PWM periods in edge-aligned mode
258 - the number of half PWM period in center-aligned mode
259 GP timers: this parameter must be a number between Min_Data = 0x00 and
260 Max_Data = 0xFF.
261 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
262 Max_Data = 0xFFFF.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_SetRepetitionCounter().*/
266 } LL_TIM_InitTypeDef;
267
268 /**
269 * @brief TIM Output Compare configuration structure definition.
270 */
271 typedef struct
272 {
273 uint32_t OCMode; /*!< Specifies the output mode.
274 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
275
276 This feature can be modified afterwards using unitary function
277 @ref LL_TIM_OC_SetMode().*/
278
279 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
280 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
281
282 This feature can be modified afterwards using unitary functions
283 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
284
285 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
286 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
287
288 This feature can be modified afterwards using unitary functions
289 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
290
291 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
292 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
293
294 This feature can be modified afterwards using unitary function
295 LL_TIM_OC_SetCompareCHx (x=1..6).*/
296
297 uint32_t OCPolarity; /*!< Specifies the output polarity.
298 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetPolarity().*/
302
303 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
304 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
305
306 This feature can be modified afterwards using unitary function
307 @ref LL_TIM_OC_SetPolarity().*/
308
309
310 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
311 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_OC_SetIdleState().*/
315
316 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
317 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_OC_SetIdleState().*/
321 } LL_TIM_OC_InitTypeDef;
322
323 /**
324 * @brief TIM Input Capture configuration structure definition.
325 */
326
327 typedef struct
328 {
329
330 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
331 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPolarity().*/
335
336 uint32_t ICActiveInput; /*!< Specifies the input.
337 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetActiveInput().*/
341
342 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
343 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
344
345 This feature can be modified afterwards using unitary function
346 @ref LL_TIM_IC_SetPrescaler().*/
347
348 uint32_t ICFilter; /*!< Specifies the input capture filter.
349 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
350
351 This feature can be modified afterwards using unitary function
352 @ref LL_TIM_IC_SetFilter().*/
353 } LL_TIM_IC_InitTypeDef;
354
355
356 /**
357 * @brief TIM Encoder interface configuration structure definition.
358 */
359 typedef struct
360 {
361 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
362 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_SetEncoderMode().*/
366
367 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
368 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPolarity().*/
372
373 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
374 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetActiveInput().*/
378
379 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
380 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPrescaler().*/
384
385 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
386 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetFilter().*/
390
391 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
392 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPolarity().*/
396
397 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
398 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetActiveInput().*/
402
403 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
404 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetPrescaler().*/
408
409 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
410 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
411
412 This feature can be modified afterwards using unitary function
413 @ref LL_TIM_IC_SetFilter().*/
414
415 } LL_TIM_ENCODER_InitTypeDef;
416
417 /**
418 * @brief TIM Hall sensor interface configuration structure definition.
419 */
420 typedef struct
421 {
422
423 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
424 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
425
426 This feature can be modified afterwards using unitary function
427 @ref LL_TIM_IC_SetPolarity().*/
428
429 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
430 Prescaler must be set to get a maximum counter period longer than the
431 time interval between 2 consecutive changes on the Hall inputs.
432 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
433
434 This feature can be modified afterwards using unitary function
435 @ref LL_TIM_IC_SetPrescaler().*/
436
437 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
438 This parameter can be a value of
439 @ref TIM_LL_EC_IC_FILTER.
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_IC_SetFilter().*/
443
444 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
445 A positive pulse (TRGO event) is generated with a programmable delay every time
446 a change occurs on the Hall inputs.
447 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_OC_SetCompareCH2().*/
451 } LL_TIM_HALLSENSOR_InitTypeDef;
452
453 /**
454 * @brief BDTR (Break and Dead Time) structure definition
455 */
456 typedef struct
457 {
458 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
459 This parameter can be a value of @ref TIM_LL_EC_OSSR
460
461 This feature can be modified afterwards using unitary function
462 @ref LL_TIM_SetOffStates()
463
464 @note This bit-field cannot be modified as long as LOCK level 2 has been
465 programmed. */
466
467 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
468 This parameter can be a value of @ref TIM_LL_EC_OSSI
469
470 This feature can be modified afterwards using unitary function
471 @ref LL_TIM_SetOffStates()
472
473 @note This bit-field cannot be modified as long as LOCK level 2 has been
474 programmed. */
475
476 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
477 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
478
479 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
480 register has been written, their content is frozen until the next reset.*/
481
482 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
483 switching-on of the outputs.
484 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
485
486 This feature can be modified afterwards using unitary function
487 @ref LL_TIM_OC_SetDeadTime()
488
489 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
490 programmed. */
491
492 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
493 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
494
495 This feature can be modified afterwards using unitary functions
496 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
497
498 @note This bit-field can not be modified as long as LOCK level 1 has been
499 programmed. */
500
501 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
502 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
503
504 This feature can be modified afterwards using unitary function
505 @ref LL_TIM_ConfigBRK()
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been
508 programmed. */
509
510 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
511 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
512
513 This feature can be modified afterwards using unitary function
514 @ref LL_TIM_ConfigBRK()
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
521
522 This feature can be modified afterwards using unitary functions
523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
539
540 This feature can be modified afterwards using unitary function
541 @ref LL_TIM_ConfigBRK2()
542
543 @note This bit-field can not be modified as long as LOCK level 1 has been
544 programmed. */
545
546 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
547 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
551
552 @note This bit-field can not be modified as long as LOCK level 1 has been
553 programmed. */
554 } LL_TIM_BDTR_InitTypeDef;
555
556 /**
557 * @}
558 */
559 #endif /* USE_FULL_LL_DRIVER */
560
561 /* Exported constants --------------------------------------------------------*/
562 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
563 * @{
564 */
565
566 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
567 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
568 * @{
569 */
570 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
571 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
572 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
573 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
574 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
575 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
576 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
580 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
581 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
582 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
583 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
584 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
585 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
586 /**
587 * @}
588 */
589
590 #if defined(USE_FULL_LL_DRIVER)
591 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
592 * @{
593 */
594 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
595 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
596 /**
597 * @}
598 */
599
600 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
601 * @{
602 */
603 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
604 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
610 * @{
611 */
612 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
613 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
614 /**
615 * @}
616 */
617 #endif /* USE_FULL_LL_DRIVER */
618
619 /** @defgroup TIM_LL_EC_IT IT Defines
620 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
621 * @{
622 */
623 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
624 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
625 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
626 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
627 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
628 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
629 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
630 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
636 * @{
637 */
638 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
639 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
645 * @{
646 */
647 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
648 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
654 * @{
655 */
656 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
657 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
658 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
659 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
660 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
661 /**
662 * @}
663 */
664
665 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
666 * @{
667 */
668 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
669 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
670 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
671 /**
672 * @}
673 */
674
675 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
676 * @{
677 */
678 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
679 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
685 * @{
686 */
687 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
688 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
694 * @{
695 */
696 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
697 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
703 * @{
704 */
705 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
706 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
707 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
708 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_CHANNEL Channel
714 * @{
715 */
716 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
717 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
718 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
719 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
720 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
721 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
722 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
723 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
724 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
725 /**
726 * @}
727 */
728
729 #if defined(USE_FULL_LL_DRIVER)
730 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
731 * @{
732 */
733 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
734 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
735 /**
736 * @}
737 */
738 #endif /* USE_FULL_LL_DRIVER */
739
740 /** Legacy definitions for compatibility purpose
741 @cond 0
742 */
743 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
744 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
745 /**
746 @endcond
747 */
748
749 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
750 * @{
751 */
752 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
753 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
754 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
755 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
756 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
757 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
758 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
759 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
760 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
761 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
762 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
763 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
764 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
765 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
771 * @{
772 */
773 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
774 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
780 * @{
781 */
782 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
783 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
789 * @{
790 */
791 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
792 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
793 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
794 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
800 * @{
801 */
802 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
803 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
804 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
805 /**
806 * @}
807 */
808
809 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
810 * @{
811 */
812 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
813 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
814 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
815 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
821 * @{
822 */
823 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
824 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
825 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
826 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
827 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
828 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
830 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
831 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
832 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
833 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
834 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
835 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
836 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
837 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
838 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
844 * @{
845 */
846 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
847 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
848 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
849 /**
850 * @}
851 */
852
853 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
854 * @{
855 */
856 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
857 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
858 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
859 /**
860 * @}
861 */
862
863 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
864 * @{
865 */
866 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
867 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
868 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
869 /**
870 * @}
871 */
872
873 /** @defgroup TIM_LL_EC_TRGO Trigger Output
874 * @{
875 */
876 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
877 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
878 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
879 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
880 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
881 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
882 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
883 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
889 * @{
890 */
891 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
892 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
893 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
894 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
895 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
896 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
907 /**
908 * @}
909 */
910
911 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
912 * @{
913 */
914 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
915 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
916 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
917 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
918 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
919 /**
920 * @}
921 */
922
923 /** @defgroup TIM_LL_EC_TS Trigger Selection
924 * @{
925 */
926 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
927 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
928 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
929 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
930 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
931 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
932 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
933 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
934 /**
935 * @}
936 */
937
938 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
939 * @{
940 */
941 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
942 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
943 /**
944 * @}
945 */
946
947 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
948 * @{
949 */
950 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
951 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
952 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
953 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
959 * @{
960 */
961 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
962 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
963 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
964 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
965 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
966 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
967 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
968 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
969 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
970 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
971 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
972 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
973 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
974 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
975 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
976 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
977 /**
978 * @}
979 */
980
981 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
982 * @{
983 */
984 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
985 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */
986 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */
987 /**
988 * @}
989 */
990
991 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
992 * @{
993 */
994 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
995 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
996 /**
997 * @}
998 */
999
1000 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1001 * @{
1002 */
1003 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1004 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1005 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1006 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1007 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1008 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1009 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1010 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1011 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1012 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1013 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1014 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1015 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1016 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1017 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1018 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1024 * @{
1025 */
1026 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1027 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1033 * @{
1034 */
1035 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1036 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1037 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1038 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1039 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1040 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1041 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1042 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1043 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1044 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1046 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup TIM_LL_EC_OSSI OSSI
1056 * @{
1057 */
1058 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1059 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup TIM_LL_EC_OSSR OSSR
1065 * @{
1066 */
1067 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1068 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1074 * @{
1075 */
1076 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1077 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1078 /**
1079 * @}
1080 */
1081
1082 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1083 * @{
1084 */
1085 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
1086 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
1087 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
1088 #if defined(DFSDM1_Channel0)
1089 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1090 #endif /* DFSDM1_Channel0 */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1096 * @{
1097 */
1098 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */
1099 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1100 /**
1101 * @}
1102 */
1103
1104 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1105 * @{
1106 */
1107 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1108 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1109 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1110 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1111 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1112 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1113 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1114 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1115 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1116 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1117 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1118 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1119 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1120 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1121 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1122 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1123 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1124 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1125 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1126 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1127 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1128 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1129 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */
1130 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1136 * @{
1137 */
1138 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1139 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1140 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1141 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1142 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1143 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1144 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1145 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1146 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1147 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1148 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1149 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1150 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1151 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1152 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1153 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1154 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1155 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1156 /**
1157 * @}
1158 */
1159
1160 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1161 * @{
1162 */
1163 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1164 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1165 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1166 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1167 /**
1168 * @}
1169 */
1170
1171 #if defined(ADC3)
1172 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
1173 * @{
1174 */
1175 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/
1176 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */
1177 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */
1178 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */
1179 /**
1180 * @}
1181 */
1182 #endif /* ADC3 */
1183
1184 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1185 * @{
1186 */
1187 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1188 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1194 * @{
1195 */
1196 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1197 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1198 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1199 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
1200 /* STM32L496xx || STM32L4A6xx || */
1201 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1202 #if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
1203 #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /*!< No internal trigger on TIM2_ITR1 */
1204 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /*!< TIM2_ITR1 is connected to USB SOF */
1205 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
1206 /* STM32L451xx || STM32L452xx || STM32L462xx */
1207 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1208 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1209 /**
1210 * @}
1211 */
1212
1213 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1214 * @{
1215 */
1216 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1217 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1218 #if defined (STM32L412xx) || defined (STM32L422xx)
1219 #else
1220 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1221 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1222 #endif
1223 /**
1224 * @}
1225 */
1226
1227 #if defined(TIM3)
1228 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1229 * @{
1230 */
1231 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */
1232 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */
1233 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */
1234 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1235 /**
1236 * @}
1237 */
1238 #endif /* TIM3 */
1239
1240 #if defined(TIM8)
1241 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1242 * @{
1243 */
1244 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1245 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1246 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1247 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1253 * @{
1254 */
1255 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1256 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1257 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1258 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1259 /**
1260 * @}
1261 */
1262
1263 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1264 * @{
1265 */
1266 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */
1267 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */
1268 /**
1269 * @}
1270 */
1271 #endif /* TIM8 */
1272
1273 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1274 * @{
1275 */
1276 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */
1277 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */
1278 /**
1279 * @}
1280 */
1281
1282 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
1283 * @{
1284 */
1285 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/
1286 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1287 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
1288 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1289 /**
1290 * @}
1291 */
1292
1293 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1294 * @{
1295 */
1296 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1297 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1298 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1299 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1300 #if defined TIM16_OR1_TI1_RMP_2
1301 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */
1302 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */
1303 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1304 #endif
1305 /**
1306 * @}
1307 */
1308
1309 #if defined(TIM17)
1310 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1311 * @{
1312 */
1313 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1314 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1315 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1316 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1317 /**
1318 * @}
1319 */
1320 #endif /* TIM17 */
1321
1322 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1323 * @{
1324 */
1325 #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */
1326 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1327 /**
1328 * @}
1329 */
1330
1331 /** Legacy definitions for compatibility purpose
1332 @cond 0
1333 */
1334 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1335 /**
1336 @endcond
1337 */
1338
1339 /**
1340 * @}
1341 */
1342
1343 /* Exported macro ------------------------------------------------------------*/
1344 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1345 * @{
1346 */
1347
1348 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1349 * @{
1350 */
1351 /**
1352 * @brief Write a value in TIM register.
1353 * @param __INSTANCE__ TIM Instance
1354 * @param __REG__ Register to be written
1355 * @param __VALUE__ Value to be written in the register
1356 * @retval None
1357 */
1358 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1359
1360 /**
1361 * @brief Read a value in TIM register.
1362 * @param __INSTANCE__ TIM Instance
1363 * @param __REG__ Register to be read
1364 * @retval Register value
1365 */
1366 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1367 /**
1368 * @}
1369 */
1370
1371 /**
1372 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1373 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1374 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1375 * to TIMx_CNT register bit 31)
1376 * @param __CNT__ Counter value
1377 * @retval UIF status bit
1378 */
1379 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1380 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1381
1382 /**
1383 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1384 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1385 * @param __TIMCLK__ timer input clock frequency (in Hz)
1386 * @param __CKD__ This parameter can be one of the following values:
1387 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1388 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1389 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1390 * @param __DT__ deadtime duration (in ns)
1391 * @retval DTG[0:7]
1392 */
1393 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1394 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1395 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1396 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1397 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1398 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1399 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1400 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1401 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1402 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1403 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1404 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1405 0U)
1406
1407 /**
1408 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1409 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1410 * @param __TIMCLK__ timer input clock frequency (in Hz)
1411 * @param __CNTCLK__ counter clock frequency (in Hz)
1412 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1413 */
1414 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1415 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1416
1417 /**
1418 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1419 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1420 * @param __TIMCLK__ timer input clock frequency (in Hz)
1421 * @param __PSC__ prescaler
1422 * @param __FREQ__ output signal frequency (in Hz)
1423 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1424 */
1425 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1426 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1427
1428 /**
1429 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1430 * active/inactive delay.
1431 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1432 * @param __TIMCLK__ timer input clock frequency (in Hz)
1433 * @param __PSC__ prescaler
1434 * @param __DELAY__ timer output compare active/inactive delay (in us)
1435 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1436 */
1437 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1438 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1439 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1440
1441 /**
1442 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1443 * (when the timer operates in one pulse mode).
1444 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1445 * @param __TIMCLK__ timer input clock frequency (in Hz)
1446 * @param __PSC__ prescaler
1447 * @param __DELAY__ timer output compare active/inactive delay (in us)
1448 * @param __PULSE__ pulse duration (in us)
1449 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1450 */
1451 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1452 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1453 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1454
1455 /**
1456 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1457 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1458 * @param __ICPSC__ This parameter can be one of the following values:
1459 * @arg @ref LL_TIM_ICPSC_DIV1
1460 * @arg @ref LL_TIM_ICPSC_DIV2
1461 * @arg @ref LL_TIM_ICPSC_DIV4
1462 * @arg @ref LL_TIM_ICPSC_DIV8
1463 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1464 */
1465 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1466 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1467
1468
1469 /**
1470 * @}
1471 */
1472
1473 /* Exported functions --------------------------------------------------------*/
1474 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1475 * @{
1476 */
1477
1478 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1479 * @{
1480 */
1481 /**
1482 * @brief Enable timer counter.
1483 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1484 * @param TIMx Timer instance
1485 * @retval None
1486 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1487 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1488 {
1489 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1490 }
1491
1492 /**
1493 * @brief Disable timer counter.
1494 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1495 * @param TIMx Timer instance
1496 * @retval None
1497 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1498 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1499 {
1500 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1501 }
1502
1503 /**
1504 * @brief Indicates whether the timer counter is enabled.
1505 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1506 * @param TIMx Timer instance
1507 * @retval State of bit (1 or 0).
1508 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1509 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1510 {
1511 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1512 }
1513
1514 /**
1515 * @brief Enable update event generation.
1516 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1517 * @param TIMx Timer instance
1518 * @retval None
1519 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1520 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1521 {
1522 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1523 }
1524
1525 /**
1526 * @brief Disable update event generation.
1527 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1528 * @param TIMx Timer instance
1529 * @retval None
1530 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1531 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1532 {
1533 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1534 }
1535
1536 /**
1537 * @brief Indicates whether update event generation is enabled.
1538 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1539 * @param TIMx Timer instance
1540 * @retval Inverted state of bit (0 or 1).
1541 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1542 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1543 {
1544 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Set update event source
1549 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1550 * generate an update interrupt or DMA request if enabled:
1551 * - Counter overflow/underflow
1552 * - Setting the UG bit
1553 * - Update generation through the slave mode controller
1554 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1555 * overflow/underflow generates an update interrupt or DMA request if enabled.
1556 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1557 * @param TIMx Timer instance
1558 * @param UpdateSource This parameter can be one of the following values:
1559 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1560 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1561 * @retval None
1562 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1563 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1564 {
1565 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1566 }
1567
1568 /**
1569 * @brief Get actual event update source
1570 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1571 * @param TIMx Timer instance
1572 * @retval Returned value can be one of the following values:
1573 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1574 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1575 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1576 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1577 {
1578 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1579 }
1580
1581 /**
1582 * @brief Set one pulse mode (one shot v.s. repetitive).
1583 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1584 * @param TIMx Timer instance
1585 * @param OnePulseMode This parameter can be one of the following values:
1586 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1587 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1588 * @retval None
1589 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1590 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1591 {
1592 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1593 }
1594
1595 /**
1596 * @brief Get actual one pulse mode.
1597 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1598 * @param TIMx Timer instance
1599 * @retval Returned value can be one of the following values:
1600 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1601 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1602 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1603 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1604 {
1605 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1606 }
1607
1608 /**
1609 * @brief Set the timer counter counting mode.
1610 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1611 * check whether or not the counter mode selection feature is supported
1612 * by a timer instance.
1613 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1614 * requires a timer reset to avoid unexpected direction
1615 * due to DIR bit readonly in center aligned mode.
1616 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1617 * CR1 CMS LL_TIM_SetCounterMode
1618 * @param TIMx Timer instance
1619 * @param CounterMode This parameter can be one of the following values:
1620 * @arg @ref LL_TIM_COUNTERMODE_UP
1621 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1622 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1623 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1624 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1625 * @retval None
1626 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1627 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1628 {
1629 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1630 }
1631
1632 /**
1633 * @brief Get actual counter mode.
1634 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1635 * check whether or not the counter mode selection feature is supported
1636 * by a timer instance.
1637 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1638 * CR1 CMS LL_TIM_GetCounterMode
1639 * @param TIMx Timer instance
1640 * @retval Returned value can be one of the following values:
1641 * @arg @ref LL_TIM_COUNTERMODE_UP
1642 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1643 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1644 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1645 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1646 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1647 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1648 {
1649 uint32_t counter_mode;
1650
1651 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1652
1653 if (counter_mode == 0U)
1654 {
1655 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1656 }
1657
1658 return counter_mode;
1659 }
1660
1661 /**
1662 * @brief Enable auto-reload (ARR) preload.
1663 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1664 * @param TIMx Timer instance
1665 * @retval None
1666 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1667 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1668 {
1669 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1670 }
1671
1672 /**
1673 * @brief Disable auto-reload (ARR) preload.
1674 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1675 * @param TIMx Timer instance
1676 * @retval None
1677 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1678 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1679 {
1680 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1681 }
1682
1683 /**
1684 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1685 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1686 * @param TIMx Timer instance
1687 * @retval State of bit (1 or 0).
1688 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1689 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1690 {
1691 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1696 * (when supported) and the digital filters.
1697 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1698 * whether or not the clock division feature is supported by the timer
1699 * instance.
1700 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1701 * @param TIMx Timer instance
1702 * @param ClockDivision This parameter can be one of the following values:
1703 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1704 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1705 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1706 * @retval None
1707 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1708 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1709 {
1710 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1711 }
1712
1713 /**
1714 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1715 * generators (when supported) and the digital filters.
1716 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1717 * whether or not the clock division feature is supported by the timer
1718 * instance.
1719 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1720 * @param TIMx Timer instance
1721 * @retval Returned value can be one of the following values:
1722 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1723 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1724 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1725 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1726 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1727 {
1728 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1729 }
1730
1731 /**
1732 * @brief Set the counter value.
1733 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1734 * whether or not a timer instance supports a 32 bits counter.
1735 * @rmtoll CNT CNT LL_TIM_SetCounter
1736 * @param TIMx Timer instance
1737 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1738 * @retval None
1739 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1740 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1741 {
1742 WRITE_REG(TIMx->CNT, Counter);
1743 }
1744
1745 /**
1746 * @brief Get the counter value.
1747 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1748 * whether or not a timer instance supports a 32 bits counter.
1749 * @rmtoll CNT CNT LL_TIM_GetCounter
1750 * @param TIMx Timer instance
1751 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1752 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1753 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1754 {
1755 return (uint32_t)(READ_REG(TIMx->CNT));
1756 }
1757
1758 /**
1759 * @brief Get the current direction of the counter
1760 * @rmtoll CR1 DIR LL_TIM_GetDirection
1761 * @param TIMx Timer instance
1762 * @retval Returned value can be one of the following values:
1763 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1764 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1765 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1766 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1767 {
1768 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1769 }
1770
1771 /**
1772 * @brief Set the prescaler value.
1773 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1774 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1775 * prescaler ratio is taken into account at the next update event.
1776 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1777 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1778 * @param TIMx Timer instance
1779 * @param Prescaler between Min_Data=0 and Max_Data=65535
1780 * @retval None
1781 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1782 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1783 {
1784 WRITE_REG(TIMx->PSC, Prescaler);
1785 }
1786
1787 /**
1788 * @brief Get the prescaler value.
1789 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1790 * @param TIMx Timer instance
1791 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1792 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1793 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1794 {
1795 return (uint32_t)(READ_REG(TIMx->PSC));
1796 }
1797
1798 /**
1799 * @brief Set the auto-reload value.
1800 * @note The counter is blocked while the auto-reload value is null.
1801 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1802 * whether or not a timer instance supports a 32 bits counter.
1803 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1804 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1805 * @param TIMx Timer instance
1806 * @param AutoReload between Min_Data=0 and Max_Data=65535
1807 * @retval None
1808 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1809 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1810 {
1811 WRITE_REG(TIMx->ARR, AutoReload);
1812 }
1813
1814 /**
1815 * @brief Get the auto-reload value.
1816 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1817 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1818 * whether or not a timer instance supports a 32 bits counter.
1819 * @param TIMx Timer instance
1820 * @retval Auto-reload value
1821 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1822 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1823 {
1824 return (uint32_t)(READ_REG(TIMx->ARR));
1825 }
1826
1827 /**
1828 * @brief Set the repetition counter value.
1829 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1830 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1831 * whether or not a timer instance supports a repetition counter.
1832 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1833 * @param TIMx Timer instance
1834 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1835 * @retval None
1836 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1837 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1838 {
1839 WRITE_REG(TIMx->RCR, RepetitionCounter);
1840 }
1841
1842 /**
1843 * @brief Get the repetition counter value.
1844 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1845 * whether or not a timer instance supports a repetition counter.
1846 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1847 * @param TIMx Timer instance
1848 * @retval Repetition counter value
1849 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1850 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1851 {
1852 return (uint32_t)(READ_REG(TIMx->RCR));
1853 }
1854
1855 /**
1856 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1857 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1858 * in an atomic way.
1859 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1860 * @param TIMx Timer instance
1861 * @retval None
1862 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1863 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1864 {
1865 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1866 }
1867
1868 /**
1869 * @brief Disable update interrupt flag (UIF) remapping.
1870 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1871 * @param TIMx Timer instance
1872 * @retval None
1873 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1874 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1875 {
1876 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1877 }
1878
1879 /**
1880 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1881 * @param Counter Counter value
1882 * @retval State of bit (1 or 0).
1883 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1884 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1885 {
1886 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @}
1891 */
1892
1893 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1894 * @{
1895 */
1896 /**
1897 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1898 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1899 * they are updated only when a commutation event (COM) occurs.
1900 * @note Only on channels that have a complementary output.
1901 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1902 * whether or not a timer instance is able to generate a commutation event.
1903 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1904 * @param TIMx Timer instance
1905 * @retval None
1906 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1907 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1908 {
1909 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1910 }
1911
1912 /**
1913 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1914 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1915 * whether or not a timer instance is able to generate a commutation event.
1916 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1917 * @param TIMx Timer instance
1918 * @retval None
1919 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1920 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1921 {
1922 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1923 }
1924
1925 /**
1926 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1927 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1928 * @param TIMx Timer instance
1929 * @retval State of bit (1 or 0).
1930 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1931 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1932 {
1933 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1934 }
1935
1936 /**
1937 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1938 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1939 * whether or not a timer instance is able to generate a commutation event.
1940 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1941 * @param TIMx Timer instance
1942 * @param CCUpdateSource This parameter can be one of the following values:
1943 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1944 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1945 * @retval None
1946 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1947 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1948 {
1949 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1950 }
1951
1952 /**
1953 * @brief Set the trigger of the capture/compare DMA request.
1954 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1955 * @param TIMx Timer instance
1956 * @param DMAReqTrigger This parameter can be one of the following values:
1957 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1958 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1959 * @retval None
1960 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1961 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1962 {
1963 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1964 }
1965
1966 /**
1967 * @brief Get actual trigger of the capture/compare DMA request.
1968 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1969 * @param TIMx Timer instance
1970 * @retval Returned value can be one of the following values:
1971 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1972 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1973 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1974 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1975 {
1976 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1977 }
1978
1979 /**
1980 * @brief Set the lock level to freeze the
1981 * configuration of several capture/compare parameters.
1982 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1983 * the lock mechanism is supported by a timer instance.
1984 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1985 * @param TIMx Timer instance
1986 * @param LockLevel This parameter can be one of the following values:
1987 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1988 * @arg @ref LL_TIM_LOCKLEVEL_1
1989 * @arg @ref LL_TIM_LOCKLEVEL_2
1990 * @arg @ref LL_TIM_LOCKLEVEL_3
1991 * @retval None
1992 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1993 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1994 {
1995 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1996 }
1997
1998 /**
1999 * @brief Enable capture/compare channels.
2000 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2001 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2002 * CCER CC2E LL_TIM_CC_EnableChannel\n
2003 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2004 * CCER CC3E LL_TIM_CC_EnableChannel\n
2005 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2006 * CCER CC4E LL_TIM_CC_EnableChannel\n
2007 * CCER CC5E LL_TIM_CC_EnableChannel\n
2008 * CCER CC6E LL_TIM_CC_EnableChannel
2009 * @param TIMx Timer instance
2010 * @param Channels This parameter can be a combination of the following values:
2011 * @arg @ref LL_TIM_CHANNEL_CH1
2012 * @arg @ref LL_TIM_CHANNEL_CH1N
2013 * @arg @ref LL_TIM_CHANNEL_CH2
2014 * @arg @ref LL_TIM_CHANNEL_CH2N
2015 * @arg @ref LL_TIM_CHANNEL_CH3
2016 * @arg @ref LL_TIM_CHANNEL_CH3N
2017 * @arg @ref LL_TIM_CHANNEL_CH4
2018 * @arg @ref LL_TIM_CHANNEL_CH5
2019 * @arg @ref LL_TIM_CHANNEL_CH6
2020 * @retval None
2021 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2022 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2023 {
2024 SET_BIT(TIMx->CCER, Channels);
2025 }
2026
2027 /**
2028 * @brief Disable capture/compare channels.
2029 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2030 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2031 * CCER CC2E LL_TIM_CC_DisableChannel\n
2032 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2033 * CCER CC3E LL_TIM_CC_DisableChannel\n
2034 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2035 * CCER CC4E LL_TIM_CC_DisableChannel\n
2036 * CCER CC5E LL_TIM_CC_DisableChannel\n
2037 * CCER CC6E LL_TIM_CC_DisableChannel
2038 * @param TIMx Timer instance
2039 * @param Channels This parameter can be a combination of the following values:
2040 * @arg @ref LL_TIM_CHANNEL_CH1
2041 * @arg @ref LL_TIM_CHANNEL_CH1N
2042 * @arg @ref LL_TIM_CHANNEL_CH2
2043 * @arg @ref LL_TIM_CHANNEL_CH2N
2044 * @arg @ref LL_TIM_CHANNEL_CH3
2045 * @arg @ref LL_TIM_CHANNEL_CH3N
2046 * @arg @ref LL_TIM_CHANNEL_CH4
2047 * @arg @ref LL_TIM_CHANNEL_CH5
2048 * @arg @ref LL_TIM_CHANNEL_CH6
2049 * @retval None
2050 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2051 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2052 {
2053 CLEAR_BIT(TIMx->CCER, Channels);
2054 }
2055
2056 /**
2057 * @brief Indicate whether channel(s) is(are) enabled.
2058 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2059 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2060 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2061 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2062 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2063 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2064 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2065 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2066 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2067 * @param TIMx Timer instance
2068 * @param Channels This parameter can be a combination of the following values:
2069 * @arg @ref LL_TIM_CHANNEL_CH1
2070 * @arg @ref LL_TIM_CHANNEL_CH1N
2071 * @arg @ref LL_TIM_CHANNEL_CH2
2072 * @arg @ref LL_TIM_CHANNEL_CH2N
2073 * @arg @ref LL_TIM_CHANNEL_CH3
2074 * @arg @ref LL_TIM_CHANNEL_CH3N
2075 * @arg @ref LL_TIM_CHANNEL_CH4
2076 * @arg @ref LL_TIM_CHANNEL_CH5
2077 * @arg @ref LL_TIM_CHANNEL_CH6
2078 * @retval State of bit (1 or 0).
2079 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2080 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2081 {
2082 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2083 }
2084
2085 /**
2086 * @}
2087 */
2088
2089 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2090 * @{
2091 */
2092 /**
2093 * @brief Configure an output channel.
2094 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2095 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2096 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2097 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2098 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2099 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2100 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2101 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2102 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2103 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2104 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2105 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2106 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2107 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2108 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2109 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2110 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2111 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2112 * @param TIMx Timer instance
2113 * @param Channel This parameter can be one of the following values:
2114 * @arg @ref LL_TIM_CHANNEL_CH1
2115 * @arg @ref LL_TIM_CHANNEL_CH2
2116 * @arg @ref LL_TIM_CHANNEL_CH3
2117 * @arg @ref LL_TIM_CHANNEL_CH4
2118 * @arg @ref LL_TIM_CHANNEL_CH5
2119 * @arg @ref LL_TIM_CHANNEL_CH6
2120 * @param Configuration This parameter must be a combination of all the following values:
2121 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2122 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2123 * @retval None
2124 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2125 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2126 {
2127 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2128 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2129 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2130 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2131 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2132 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2133 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2134 }
2135
2136 /**
2137 * @brief Define the behavior of the output reference signal OCxREF from which
2138 * OCx and OCxN (when relevant) are derived.
2139 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2140 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2141 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2142 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2143 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2144 * CCMR3 OC6M LL_TIM_OC_SetMode
2145 * @param TIMx Timer instance
2146 * @param Channel This parameter can be one of the following values:
2147 * @arg @ref LL_TIM_CHANNEL_CH1
2148 * @arg @ref LL_TIM_CHANNEL_CH2
2149 * @arg @ref LL_TIM_CHANNEL_CH3
2150 * @arg @ref LL_TIM_CHANNEL_CH4
2151 * @arg @ref LL_TIM_CHANNEL_CH5
2152 * @arg @ref LL_TIM_CHANNEL_CH6
2153 * @param Mode This parameter can be one of the following values:
2154 * @arg @ref LL_TIM_OCMODE_FROZEN
2155 * @arg @ref LL_TIM_OCMODE_ACTIVE
2156 * @arg @ref LL_TIM_OCMODE_INACTIVE
2157 * @arg @ref LL_TIM_OCMODE_TOGGLE
2158 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2159 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2160 * @arg @ref LL_TIM_OCMODE_PWM1
2161 * @arg @ref LL_TIM_OCMODE_PWM2
2162 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2163 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2164 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2165 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2166 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2167 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2168 * @retval None
2169 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2170 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2171 {
2172 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2173 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2174 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2175 }
2176
2177 /**
2178 * @brief Get the output compare mode of an output channel.
2179 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2180 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2181 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2182 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2183 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2184 * CCMR3 OC6M LL_TIM_OC_GetMode
2185 * @param TIMx Timer instance
2186 * @param Channel This parameter can be one of the following values:
2187 * @arg @ref LL_TIM_CHANNEL_CH1
2188 * @arg @ref LL_TIM_CHANNEL_CH2
2189 * @arg @ref LL_TIM_CHANNEL_CH3
2190 * @arg @ref LL_TIM_CHANNEL_CH4
2191 * @arg @ref LL_TIM_CHANNEL_CH5
2192 * @arg @ref LL_TIM_CHANNEL_CH6
2193 * @retval Returned value can be one of the following values:
2194 * @arg @ref LL_TIM_OCMODE_FROZEN
2195 * @arg @ref LL_TIM_OCMODE_ACTIVE
2196 * @arg @ref LL_TIM_OCMODE_INACTIVE
2197 * @arg @ref LL_TIM_OCMODE_TOGGLE
2198 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2199 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2200 * @arg @ref LL_TIM_OCMODE_PWM1
2201 * @arg @ref LL_TIM_OCMODE_PWM2
2202 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2203 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2204 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2205 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2206 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2207 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2208 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2209 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2210 {
2211 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2212 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2213 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2214 }
2215
2216 /**
2217 * @brief Set the polarity of an output channel.
2218 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2219 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2220 * CCER CC2P LL_TIM_OC_SetPolarity\n
2221 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2222 * CCER CC3P LL_TIM_OC_SetPolarity\n
2223 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2224 * CCER CC4P LL_TIM_OC_SetPolarity\n
2225 * CCER CC5P LL_TIM_OC_SetPolarity\n
2226 * CCER CC6P LL_TIM_OC_SetPolarity
2227 * @param TIMx Timer instance
2228 * @param Channel This parameter can be one of the following values:
2229 * @arg @ref LL_TIM_CHANNEL_CH1
2230 * @arg @ref LL_TIM_CHANNEL_CH1N
2231 * @arg @ref LL_TIM_CHANNEL_CH2
2232 * @arg @ref LL_TIM_CHANNEL_CH2N
2233 * @arg @ref LL_TIM_CHANNEL_CH3
2234 * @arg @ref LL_TIM_CHANNEL_CH3N
2235 * @arg @ref LL_TIM_CHANNEL_CH4
2236 * @arg @ref LL_TIM_CHANNEL_CH5
2237 * @arg @ref LL_TIM_CHANNEL_CH6
2238 * @param Polarity This parameter can be one of the following values:
2239 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2240 * @arg @ref LL_TIM_OCPOLARITY_LOW
2241 * @retval None
2242 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2243 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2244 {
2245 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2246 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2247 }
2248
2249 /**
2250 * @brief Get the polarity of an output channel.
2251 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2252 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2253 * CCER CC2P LL_TIM_OC_GetPolarity\n
2254 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2255 * CCER CC3P LL_TIM_OC_GetPolarity\n
2256 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2257 * CCER CC4P LL_TIM_OC_GetPolarity\n
2258 * CCER CC5P LL_TIM_OC_GetPolarity\n
2259 * CCER CC6P LL_TIM_OC_GetPolarity
2260 * @param TIMx Timer instance
2261 * @param Channel This parameter can be one of the following values:
2262 * @arg @ref LL_TIM_CHANNEL_CH1
2263 * @arg @ref LL_TIM_CHANNEL_CH1N
2264 * @arg @ref LL_TIM_CHANNEL_CH2
2265 * @arg @ref LL_TIM_CHANNEL_CH2N
2266 * @arg @ref LL_TIM_CHANNEL_CH3
2267 * @arg @ref LL_TIM_CHANNEL_CH3N
2268 * @arg @ref LL_TIM_CHANNEL_CH4
2269 * @arg @ref LL_TIM_CHANNEL_CH5
2270 * @arg @ref LL_TIM_CHANNEL_CH6
2271 * @retval Returned value can be one of the following values:
2272 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2273 * @arg @ref LL_TIM_OCPOLARITY_LOW
2274 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2275 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2276 {
2277 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2278 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2279 }
2280
2281 /**
2282 * @brief Set the IDLE state of an output channel
2283 * @note This function is significant only for the timer instances
2284 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2285 * can be used to check whether or not a timer instance provides
2286 * a break input.
2287 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2288 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2289 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2290 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2291 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2292 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2293 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2294 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2295 * CR2 OIS6 LL_TIM_OC_SetIdleState
2296 * @param TIMx Timer instance
2297 * @param Channel This parameter can be one of the following values:
2298 * @arg @ref LL_TIM_CHANNEL_CH1
2299 * @arg @ref LL_TIM_CHANNEL_CH1N
2300 * @arg @ref LL_TIM_CHANNEL_CH2
2301 * @arg @ref LL_TIM_CHANNEL_CH2N
2302 * @arg @ref LL_TIM_CHANNEL_CH3
2303 * @arg @ref LL_TIM_CHANNEL_CH3N
2304 * @arg @ref LL_TIM_CHANNEL_CH4
2305 * @arg @ref LL_TIM_CHANNEL_CH5
2306 * @arg @ref LL_TIM_CHANNEL_CH6
2307 * @param IdleState This parameter can be one of the following values:
2308 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2309 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2310 * @retval None
2311 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2312 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2313 {
2314 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2315 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2316 }
2317
2318 /**
2319 * @brief Get the IDLE state of an output channel
2320 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2321 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2322 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2323 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2324 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2325 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2326 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2327 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2328 * CR2 OIS6 LL_TIM_OC_GetIdleState
2329 * @param TIMx Timer instance
2330 * @param Channel This parameter can be one of the following values:
2331 * @arg @ref LL_TIM_CHANNEL_CH1
2332 * @arg @ref LL_TIM_CHANNEL_CH1N
2333 * @arg @ref LL_TIM_CHANNEL_CH2
2334 * @arg @ref LL_TIM_CHANNEL_CH2N
2335 * @arg @ref LL_TIM_CHANNEL_CH3
2336 * @arg @ref LL_TIM_CHANNEL_CH3N
2337 * @arg @ref LL_TIM_CHANNEL_CH4
2338 * @arg @ref LL_TIM_CHANNEL_CH5
2339 * @arg @ref LL_TIM_CHANNEL_CH6
2340 * @retval Returned value can be one of the following values:
2341 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2342 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2343 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2344 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2345 {
2346 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2347 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2348 }
2349
2350 /**
2351 * @brief Enable fast mode for the output channel.
2352 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2353 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2354 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2355 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2356 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2357 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2358 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2359 * @param TIMx Timer instance
2360 * @param Channel This parameter can be one of the following values:
2361 * @arg @ref LL_TIM_CHANNEL_CH1
2362 * @arg @ref LL_TIM_CHANNEL_CH2
2363 * @arg @ref LL_TIM_CHANNEL_CH3
2364 * @arg @ref LL_TIM_CHANNEL_CH4
2365 * @arg @ref LL_TIM_CHANNEL_CH5
2366 * @arg @ref LL_TIM_CHANNEL_CH6
2367 * @retval None
2368 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2369 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2370 {
2371 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2372 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2373 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2374
2375 }
2376
2377 /**
2378 * @brief Disable fast mode for the output channel.
2379 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2380 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2381 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2382 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2383 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2384 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2385 * @param TIMx Timer instance
2386 * @param Channel This parameter can be one of the following values:
2387 * @arg @ref LL_TIM_CHANNEL_CH1
2388 * @arg @ref LL_TIM_CHANNEL_CH2
2389 * @arg @ref LL_TIM_CHANNEL_CH3
2390 * @arg @ref LL_TIM_CHANNEL_CH4
2391 * @arg @ref LL_TIM_CHANNEL_CH5
2392 * @arg @ref LL_TIM_CHANNEL_CH6
2393 * @retval None
2394 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2395 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2396 {
2397 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2398 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2399 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2400
2401 }
2402
2403 /**
2404 * @brief Indicates whether fast mode is enabled for the output channel.
2405 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2406 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2407 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2408 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2409 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2410 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2411 * @param TIMx Timer instance
2412 * @param Channel This parameter can be one of the following values:
2413 * @arg @ref LL_TIM_CHANNEL_CH1
2414 * @arg @ref LL_TIM_CHANNEL_CH2
2415 * @arg @ref LL_TIM_CHANNEL_CH3
2416 * @arg @ref LL_TIM_CHANNEL_CH4
2417 * @arg @ref LL_TIM_CHANNEL_CH5
2418 * @arg @ref LL_TIM_CHANNEL_CH6
2419 * @retval State of bit (1 or 0).
2420 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2421 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2422 {
2423 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2424 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2425 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2426 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2427 }
2428
2429 /**
2430 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2431 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2432 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2433 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2434 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2435 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2436 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2437 * @param TIMx Timer instance
2438 * @param Channel This parameter can be one of the following values:
2439 * @arg @ref LL_TIM_CHANNEL_CH1
2440 * @arg @ref LL_TIM_CHANNEL_CH2
2441 * @arg @ref LL_TIM_CHANNEL_CH3
2442 * @arg @ref LL_TIM_CHANNEL_CH4
2443 * @arg @ref LL_TIM_CHANNEL_CH5
2444 * @arg @ref LL_TIM_CHANNEL_CH6
2445 * @retval None
2446 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2447 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2448 {
2449 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2450 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2451 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2452 }
2453
2454 /**
2455 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2456 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2457 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2458 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2459 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2460 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2461 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2462 * @param TIMx Timer instance
2463 * @param Channel This parameter can be one of the following values:
2464 * @arg @ref LL_TIM_CHANNEL_CH1
2465 * @arg @ref LL_TIM_CHANNEL_CH2
2466 * @arg @ref LL_TIM_CHANNEL_CH3
2467 * @arg @ref LL_TIM_CHANNEL_CH4
2468 * @arg @ref LL_TIM_CHANNEL_CH5
2469 * @arg @ref LL_TIM_CHANNEL_CH6
2470 * @retval None
2471 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2472 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2473 {
2474 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2475 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2476 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2477 }
2478
2479 /**
2480 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2481 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2482 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2483 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2484 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2485 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2486 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2487 * @param TIMx Timer instance
2488 * @param Channel This parameter can be one of the following values:
2489 * @arg @ref LL_TIM_CHANNEL_CH1
2490 * @arg @ref LL_TIM_CHANNEL_CH2
2491 * @arg @ref LL_TIM_CHANNEL_CH3
2492 * @arg @ref LL_TIM_CHANNEL_CH4
2493 * @arg @ref LL_TIM_CHANNEL_CH5
2494 * @arg @ref LL_TIM_CHANNEL_CH6
2495 * @retval State of bit (1 or 0).
2496 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2497 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2498 {
2499 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2500 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2501 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2502 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2503 }
2504
2505 /**
2506 * @brief Enable clearing the output channel on an external event.
2507 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2508 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2509 * or not a timer instance can clear the OCxREF signal on an external event.
2510 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2511 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2512 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2513 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2514 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2515 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2516 * @param TIMx Timer instance
2517 * @param Channel This parameter can be one of the following values:
2518 * @arg @ref LL_TIM_CHANNEL_CH1
2519 * @arg @ref LL_TIM_CHANNEL_CH2
2520 * @arg @ref LL_TIM_CHANNEL_CH3
2521 * @arg @ref LL_TIM_CHANNEL_CH4
2522 * @arg @ref LL_TIM_CHANNEL_CH5
2523 * @arg @ref LL_TIM_CHANNEL_CH6
2524 * @retval None
2525 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2526 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2527 {
2528 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2529 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2530 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2531 }
2532
2533 /**
2534 * @brief Disable clearing the output channel on an external event.
2535 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2536 * or not a timer instance can clear the OCxREF signal on an external event.
2537 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2538 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2539 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2540 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2541 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2542 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2543 * @param TIMx Timer instance
2544 * @param Channel This parameter can be one of the following values:
2545 * @arg @ref LL_TIM_CHANNEL_CH1
2546 * @arg @ref LL_TIM_CHANNEL_CH2
2547 * @arg @ref LL_TIM_CHANNEL_CH3
2548 * @arg @ref LL_TIM_CHANNEL_CH4
2549 * @arg @ref LL_TIM_CHANNEL_CH5
2550 * @arg @ref LL_TIM_CHANNEL_CH6
2551 * @retval None
2552 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2553 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2554 {
2555 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2556 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2557 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2558 }
2559
2560 /**
2561 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2562 * @note This function enables clearing the output channel on an external event.
2563 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2564 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2565 * or not a timer instance can clear the OCxREF signal on an external event.
2566 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2567 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2568 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2569 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2570 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2571 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2572 * @param TIMx Timer instance
2573 * @param Channel This parameter can be one of the following values:
2574 * @arg @ref LL_TIM_CHANNEL_CH1
2575 * @arg @ref LL_TIM_CHANNEL_CH2
2576 * @arg @ref LL_TIM_CHANNEL_CH3
2577 * @arg @ref LL_TIM_CHANNEL_CH4
2578 * @arg @ref LL_TIM_CHANNEL_CH5
2579 * @arg @ref LL_TIM_CHANNEL_CH6
2580 * @retval State of bit (1 or 0).
2581 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2582 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2583 {
2584 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2585 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2586 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2587 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2588 }
2589
2590 /**
2591 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2592 * the Ocx and OCxN signals).
2593 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2594 * dead-time insertion feature is supported by a timer instance.
2595 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2596 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2597 * @param TIMx Timer instance
2598 * @param DeadTime between Min_Data=0 and Max_Data=255
2599 * @retval None
2600 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2601 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2602 {
2603 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2604 }
2605
2606 /**
2607 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2608 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2609 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2610 * whether or not a timer instance supports a 32 bits counter.
2611 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2612 * output channel 1 is supported by a timer instance.
2613 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2614 * @param TIMx Timer instance
2615 * @param CompareValue between Min_Data=0 and Max_Data=65535
2616 * @retval None
2617 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2618 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2619 {
2620 WRITE_REG(TIMx->CCR1, CompareValue);
2621 }
2622
2623 /**
2624 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2625 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2626 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2627 * whether or not a timer instance supports a 32 bits counter.
2628 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2629 * output channel 2 is supported by a timer instance.
2630 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2631 * @param TIMx Timer instance
2632 * @param CompareValue between Min_Data=0 and Max_Data=65535
2633 * @retval None
2634 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2635 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2636 {
2637 WRITE_REG(TIMx->CCR2, CompareValue);
2638 }
2639
2640 /**
2641 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2642 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2643 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2644 * whether or not a timer instance supports a 32 bits counter.
2645 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2646 * output channel is supported by a timer instance.
2647 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2648 * @param TIMx Timer instance
2649 * @param CompareValue between Min_Data=0 and Max_Data=65535
2650 * @retval None
2651 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2652 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2653 {
2654 WRITE_REG(TIMx->CCR3, CompareValue);
2655 }
2656
2657 /**
2658 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2659 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2660 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2661 * whether or not a timer instance supports a 32 bits counter.
2662 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2663 * output channel 4 is supported by a timer instance.
2664 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2665 * @param TIMx Timer instance
2666 * @param CompareValue between Min_Data=0 and Max_Data=65535
2667 * @retval None
2668 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2669 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2670 {
2671 WRITE_REG(TIMx->CCR4, CompareValue);
2672 }
2673
2674 /**
2675 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2676 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2677 * output channel 5 is supported by a timer instance.
2678 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2679 * @param TIMx Timer instance
2680 * @param CompareValue between Min_Data=0 and Max_Data=65535
2681 * @retval None
2682 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2683 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2684 {
2685 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2686 }
2687
2688 /**
2689 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2690 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2691 * output channel 6 is supported by a timer instance.
2692 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2693 * @param TIMx Timer instance
2694 * @param CompareValue between Min_Data=0 and Max_Data=65535
2695 * @retval None
2696 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2697 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2698 {
2699 WRITE_REG(TIMx->CCR6, CompareValue);
2700 }
2701
2702 /**
2703 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2704 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2705 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2706 * whether or not a timer instance supports a 32 bits counter.
2707 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2708 * output channel 1 is supported by a timer instance.
2709 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2710 * @param TIMx Timer instance
2711 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2712 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2713 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2714 {
2715 return (uint32_t)(READ_REG(TIMx->CCR1));
2716 }
2717
2718 /**
2719 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2720 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2721 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2722 * whether or not a timer instance supports a 32 bits counter.
2723 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2724 * output channel 2 is supported by a timer instance.
2725 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2726 * @param TIMx Timer instance
2727 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2728 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2729 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2730 {
2731 return (uint32_t)(READ_REG(TIMx->CCR2));
2732 }
2733
2734 /**
2735 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2736 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2737 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2738 * whether or not a timer instance supports a 32 bits counter.
2739 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2740 * output channel 3 is supported by a timer instance.
2741 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2742 * @param TIMx Timer instance
2743 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2744 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2745 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2746 {
2747 return (uint32_t)(READ_REG(TIMx->CCR3));
2748 }
2749
2750 /**
2751 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2752 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2753 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2754 * whether or not a timer instance supports a 32 bits counter.
2755 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2756 * output channel 4 is supported by a timer instance.
2757 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2758 * @param TIMx Timer instance
2759 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2760 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2761 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2762 {
2763 return (uint32_t)(READ_REG(TIMx->CCR4));
2764 }
2765
2766 /**
2767 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2768 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2769 * output channel 5 is supported by a timer instance.
2770 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2771 * @param TIMx Timer instance
2772 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2773 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2774 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2775 {
2776 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2777 }
2778
2779 /**
2780 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2781 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2782 * output channel 6 is supported by a timer instance.
2783 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2784 * @param TIMx Timer instance
2785 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2786 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2787 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2788 {
2789 return (uint32_t)(READ_REG(TIMx->CCR6));
2790 }
2791
2792 /**
2793 * @brief Select on which reference signal the OC5REF is combined to.
2794 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2795 * whether or not a timer instance supports the combined 3-phase PWM mode.
2796 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2797 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2798 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2799 * @param TIMx Timer instance
2800 * @param GroupCH5 This parameter can be a combination of the following values:
2801 * @arg @ref LL_TIM_GROUPCH5_NONE
2802 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2803 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2804 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2805 * @retval None
2806 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2807 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2808 {
2809 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2810 }
2811
2812 /**
2813 * @}
2814 */
2815
2816 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2817 * @{
2818 */
2819 /**
2820 * @brief Configure input channel.
2821 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2822 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2823 * CCMR1 IC1F LL_TIM_IC_Config\n
2824 * CCMR1 CC2S LL_TIM_IC_Config\n
2825 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2826 * CCMR1 IC2F LL_TIM_IC_Config\n
2827 * CCMR2 CC3S LL_TIM_IC_Config\n
2828 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2829 * CCMR2 IC3F LL_TIM_IC_Config\n
2830 * CCMR2 CC4S LL_TIM_IC_Config\n
2831 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2832 * CCMR2 IC4F LL_TIM_IC_Config\n
2833 * CCER CC1P LL_TIM_IC_Config\n
2834 * CCER CC1NP LL_TIM_IC_Config\n
2835 * CCER CC2P LL_TIM_IC_Config\n
2836 * CCER CC2NP LL_TIM_IC_Config\n
2837 * CCER CC3P LL_TIM_IC_Config\n
2838 * CCER CC3NP LL_TIM_IC_Config\n
2839 * CCER CC4P LL_TIM_IC_Config\n
2840 * CCER CC4NP LL_TIM_IC_Config
2841 * @param TIMx Timer instance
2842 * @param Channel This parameter can be one of the following values:
2843 * @arg @ref LL_TIM_CHANNEL_CH1
2844 * @arg @ref LL_TIM_CHANNEL_CH2
2845 * @arg @ref LL_TIM_CHANNEL_CH3
2846 * @arg @ref LL_TIM_CHANNEL_CH4
2847 * @param Configuration This parameter must be a combination of all the following values:
2848 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2849 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2850 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2851 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2852 * @retval None
2853 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2854 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2855 {
2856 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2857 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2858 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2859 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2860 << SHIFT_TAB_ICxx[iChannel]);
2861 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2862 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2863 }
2864
2865 /**
2866 * @brief Set the active input.
2867 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2868 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2869 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2870 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2871 * @param TIMx Timer instance
2872 * @param Channel This parameter can be one of the following values:
2873 * @arg @ref LL_TIM_CHANNEL_CH1
2874 * @arg @ref LL_TIM_CHANNEL_CH2
2875 * @arg @ref LL_TIM_CHANNEL_CH3
2876 * @arg @ref LL_TIM_CHANNEL_CH4
2877 * @param ICActiveInput This parameter can be one of the following values:
2878 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2879 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2880 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2881 * @retval None
2882 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2883 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2884 {
2885 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2886 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2887 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2888 }
2889
2890 /**
2891 * @brief Get the current active input.
2892 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2893 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2894 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2895 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2896 * @param TIMx Timer instance
2897 * @param Channel This parameter can be one of the following values:
2898 * @arg @ref LL_TIM_CHANNEL_CH1
2899 * @arg @ref LL_TIM_CHANNEL_CH2
2900 * @arg @ref LL_TIM_CHANNEL_CH3
2901 * @arg @ref LL_TIM_CHANNEL_CH4
2902 * @retval Returned value can be one of the following values:
2903 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2904 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2905 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2906 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2907 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2908 {
2909 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2910 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2911 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2912 }
2913
2914 /**
2915 * @brief Set the prescaler of input channel.
2916 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2917 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2918 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2919 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2920 * @param TIMx Timer instance
2921 * @param Channel This parameter can be one of the following values:
2922 * @arg @ref LL_TIM_CHANNEL_CH1
2923 * @arg @ref LL_TIM_CHANNEL_CH2
2924 * @arg @ref LL_TIM_CHANNEL_CH3
2925 * @arg @ref LL_TIM_CHANNEL_CH4
2926 * @param ICPrescaler This parameter can be one of the following values:
2927 * @arg @ref LL_TIM_ICPSC_DIV1
2928 * @arg @ref LL_TIM_ICPSC_DIV2
2929 * @arg @ref LL_TIM_ICPSC_DIV4
2930 * @arg @ref LL_TIM_ICPSC_DIV8
2931 * @retval None
2932 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2933 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2934 {
2935 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2936 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2937 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2938 }
2939
2940 /**
2941 * @brief Get the current prescaler value acting on an input channel.
2942 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2943 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2944 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2945 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2946 * @param TIMx Timer instance
2947 * @param Channel This parameter can be one of the following values:
2948 * @arg @ref LL_TIM_CHANNEL_CH1
2949 * @arg @ref LL_TIM_CHANNEL_CH2
2950 * @arg @ref LL_TIM_CHANNEL_CH3
2951 * @arg @ref LL_TIM_CHANNEL_CH4
2952 * @retval Returned value can be one of the following values:
2953 * @arg @ref LL_TIM_ICPSC_DIV1
2954 * @arg @ref LL_TIM_ICPSC_DIV2
2955 * @arg @ref LL_TIM_ICPSC_DIV4
2956 * @arg @ref LL_TIM_ICPSC_DIV8
2957 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2958 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2959 {
2960 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2961 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2962 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2963 }
2964
2965 /**
2966 * @brief Set the input filter duration.
2967 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2968 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2969 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2970 * CCMR2 IC4F LL_TIM_IC_SetFilter
2971 * @param TIMx Timer instance
2972 * @param Channel This parameter can be one of the following values:
2973 * @arg @ref LL_TIM_CHANNEL_CH1
2974 * @arg @ref LL_TIM_CHANNEL_CH2
2975 * @arg @ref LL_TIM_CHANNEL_CH3
2976 * @arg @ref LL_TIM_CHANNEL_CH4
2977 * @param ICFilter This parameter can be one of the following values:
2978 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2979 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2980 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2981 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2982 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2983 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2984 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2985 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2986 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2987 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2988 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2989 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2990 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2991 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2992 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2993 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2994 * @retval None
2995 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2996 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2997 {
2998 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2999 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3000 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3001 }
3002
3003 /**
3004 * @brief Get the input filter duration.
3005 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3006 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3007 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3008 * CCMR2 IC4F LL_TIM_IC_GetFilter
3009 * @param TIMx Timer instance
3010 * @param Channel This parameter can be one of the following values:
3011 * @arg @ref LL_TIM_CHANNEL_CH1
3012 * @arg @ref LL_TIM_CHANNEL_CH2
3013 * @arg @ref LL_TIM_CHANNEL_CH3
3014 * @arg @ref LL_TIM_CHANNEL_CH4
3015 * @retval Returned value can be one of the following values:
3016 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3017 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3018 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3019 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3020 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3021 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3022 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3023 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3024 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3025 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3026 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3027 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3028 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3029 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3030 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3031 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3032 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3033 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3034 {
3035 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3036 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3037 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3038 }
3039
3040 /**
3041 * @brief Set the input channel polarity.
3042 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3043 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3044 * CCER CC2P LL_TIM_IC_SetPolarity\n
3045 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3046 * CCER CC3P LL_TIM_IC_SetPolarity\n
3047 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3048 * CCER CC4P LL_TIM_IC_SetPolarity\n
3049 * CCER CC4NP LL_TIM_IC_SetPolarity
3050 * @param TIMx Timer instance
3051 * @param Channel This parameter can be one of the following values:
3052 * @arg @ref LL_TIM_CHANNEL_CH1
3053 * @arg @ref LL_TIM_CHANNEL_CH2
3054 * @arg @ref LL_TIM_CHANNEL_CH3
3055 * @arg @ref LL_TIM_CHANNEL_CH4
3056 * @param ICPolarity This parameter can be one of the following values:
3057 * @arg @ref LL_TIM_IC_POLARITY_RISING
3058 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3059 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3060 * @retval None
3061 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3062 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3063 {
3064 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3065 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3066 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3067 }
3068
3069 /**
3070 * @brief Get the current input channel polarity.
3071 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3072 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3073 * CCER CC2P LL_TIM_IC_GetPolarity\n
3074 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3075 * CCER CC3P LL_TIM_IC_GetPolarity\n
3076 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3077 * CCER CC4P LL_TIM_IC_GetPolarity\n
3078 * CCER CC4NP LL_TIM_IC_GetPolarity
3079 * @param TIMx Timer instance
3080 * @param Channel This parameter can be one of the following values:
3081 * @arg @ref LL_TIM_CHANNEL_CH1
3082 * @arg @ref LL_TIM_CHANNEL_CH2
3083 * @arg @ref LL_TIM_CHANNEL_CH3
3084 * @arg @ref LL_TIM_CHANNEL_CH4
3085 * @retval Returned value can be one of the following values:
3086 * @arg @ref LL_TIM_IC_POLARITY_RISING
3087 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3088 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3089 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3090 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3091 {
3092 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3093 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3094 SHIFT_TAB_CCxP[iChannel]);
3095 }
3096
3097 /**
3098 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3099 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3100 * a timer instance provides an XOR input.
3101 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3102 * @param TIMx Timer instance
3103 * @retval None
3104 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3105 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3106 {
3107 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3108 }
3109
3110 /**
3111 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3112 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3113 * a timer instance provides an XOR input.
3114 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3115 * @param TIMx Timer instance
3116 * @retval None
3117 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3118 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3119 {
3120 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3121 }
3122
3123 /**
3124 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3125 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3126 * a timer instance provides an XOR input.
3127 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3128 * @param TIMx Timer instance
3129 * @retval State of bit (1 or 0).
3130 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3131 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3132 {
3133 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3134 }
3135
3136 /**
3137 * @brief Get captured value for input channel 1.
3138 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3139 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3140 * whether or not a timer instance supports a 32 bits counter.
3141 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3142 * input channel 1 is supported by a timer instance.
3143 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3144 * @param TIMx Timer instance
3145 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3146 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3147 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3148 {
3149 return (uint32_t)(READ_REG(TIMx->CCR1));
3150 }
3151
3152 /**
3153 * @brief Get captured value for input channel 2.
3154 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3155 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3156 * whether or not a timer instance supports a 32 bits counter.
3157 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3158 * input channel 2 is supported by a timer instance.
3159 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3160 * @param TIMx Timer instance
3161 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3162 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3163 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3164 {
3165 return (uint32_t)(READ_REG(TIMx->CCR2));
3166 }
3167
3168 /**
3169 * @brief Get captured value for input channel 3.
3170 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3171 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3172 * whether or not a timer instance supports a 32 bits counter.
3173 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3174 * input channel 3 is supported by a timer instance.
3175 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3176 * @param TIMx Timer instance
3177 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3178 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3179 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3180 {
3181 return (uint32_t)(READ_REG(TIMx->CCR3));
3182 }
3183
3184 /**
3185 * @brief Get captured value for input channel 4.
3186 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3187 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3188 * whether or not a timer instance supports a 32 bits counter.
3189 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3190 * input channel 4 is supported by a timer instance.
3191 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3192 * @param TIMx Timer instance
3193 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3194 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3195 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3196 {
3197 return (uint32_t)(READ_REG(TIMx->CCR4));
3198 }
3199
3200 /**
3201 * @}
3202 */
3203
3204 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3205 * @{
3206 */
3207 /**
3208 * @brief Enable external clock mode 2.
3209 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3210 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3211 * whether or not a timer instance supports external clock mode2.
3212 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3213 * @param TIMx Timer instance
3214 * @retval None
3215 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3216 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3217 {
3218 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3219 }
3220
3221 /**
3222 * @brief Disable external clock mode 2.
3223 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3224 * whether or not a timer instance supports external clock mode2.
3225 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3226 * @param TIMx Timer instance
3227 * @retval None
3228 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3229 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3230 {
3231 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3232 }
3233
3234 /**
3235 * @brief Indicate whether external clock mode 2 is enabled.
3236 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3237 * whether or not a timer instance supports external clock mode2.
3238 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3239 * @param TIMx Timer instance
3240 * @retval State of bit (1 or 0).
3241 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3242 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3243 {
3244 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3245 }
3246
3247 /**
3248 * @brief Set the clock source of the counter clock.
3249 * @note when selected clock source is external clock mode 1, the timer input
3250 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3251 * function. This timer input must be configured by calling
3252 * the @ref LL_TIM_IC_Config() function.
3253 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3254 * whether or not a timer instance supports external clock mode1.
3255 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3256 * whether or not a timer instance supports external clock mode2.
3257 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3258 * SMCR ECE LL_TIM_SetClockSource
3259 * @param TIMx Timer instance
3260 * @param ClockSource This parameter can be one of the following values:
3261 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3262 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3263 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3264 * @retval None
3265 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3266 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3267 {
3268 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3269 }
3270
3271 /**
3272 * @brief Set the encoder interface mode.
3273 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3274 * whether or not a timer instance supports the encoder mode.
3275 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3276 * @param TIMx Timer instance
3277 * @param EncoderMode This parameter can be one of the following values:
3278 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3279 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3280 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3281 * @retval None
3282 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3283 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3284 {
3285 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3286 }
3287
3288 /**
3289 * @}
3290 */
3291
3292 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3293 * @{
3294 */
3295 /**
3296 * @brief Set the trigger output (TRGO) used for timer synchronization .
3297 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3298 * whether or not a timer instance can operate as a master timer.
3299 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3300 * @param TIMx Timer instance
3301 * @param TimerSynchronization This parameter can be one of the following values:
3302 * @arg @ref LL_TIM_TRGO_RESET
3303 * @arg @ref LL_TIM_TRGO_ENABLE
3304 * @arg @ref LL_TIM_TRGO_UPDATE
3305 * @arg @ref LL_TIM_TRGO_CC1IF
3306 * @arg @ref LL_TIM_TRGO_OC1REF
3307 * @arg @ref LL_TIM_TRGO_OC2REF
3308 * @arg @ref LL_TIM_TRGO_OC3REF
3309 * @arg @ref LL_TIM_TRGO_OC4REF
3310 * @retval None
3311 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3312 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3313 {
3314 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3315 }
3316
3317 /**
3318 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3319 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3320 * whether or not a timer instance can be used for ADC synchronization.
3321 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3322 * @param TIMx Timer Instance
3323 * @param ADCSynchronization This parameter can be one of the following values:
3324 * @arg @ref LL_TIM_TRGO2_RESET
3325 * @arg @ref LL_TIM_TRGO2_ENABLE
3326 * @arg @ref LL_TIM_TRGO2_UPDATE
3327 * @arg @ref LL_TIM_TRGO2_CC1F
3328 * @arg @ref LL_TIM_TRGO2_OC1
3329 * @arg @ref LL_TIM_TRGO2_OC2
3330 * @arg @ref LL_TIM_TRGO2_OC3
3331 * @arg @ref LL_TIM_TRGO2_OC4
3332 * @arg @ref LL_TIM_TRGO2_OC5
3333 * @arg @ref LL_TIM_TRGO2_OC6
3334 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3335 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3336 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3337 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3338 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3339 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3340 * @retval None
3341 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3342 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3343 {
3344 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3345 }
3346
3347 /**
3348 * @brief Set the synchronization mode of a slave timer.
3349 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3350 * a timer instance can operate as a slave timer.
3351 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3352 * @param TIMx Timer instance
3353 * @param SlaveMode This parameter can be one of the following values:
3354 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3355 * @arg @ref LL_TIM_SLAVEMODE_RESET
3356 * @arg @ref LL_TIM_SLAVEMODE_GATED
3357 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3358 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3359 * @retval None
3360 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3361 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3362 {
3363 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3364 }
3365
3366 /**
3367 * @brief Set the selects the trigger input to be used to synchronize the counter.
3368 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3369 * a timer instance can operate as a slave timer.
3370 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3371 * @param TIMx Timer instance
3372 * @param TriggerInput This parameter can be one of the following values:
3373 * @arg @ref LL_TIM_TS_ITR0
3374 * @arg @ref LL_TIM_TS_ITR1
3375 * @arg @ref LL_TIM_TS_ITR2
3376 * @arg @ref LL_TIM_TS_ITR3
3377 * @arg @ref LL_TIM_TS_TI1F_ED
3378 * @arg @ref LL_TIM_TS_TI1FP1
3379 * @arg @ref LL_TIM_TS_TI2FP2
3380 * @arg @ref LL_TIM_TS_ETRF
3381 * @retval None
3382 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3383 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3384 {
3385 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3386 }
3387
3388 /**
3389 * @brief Enable the Master/Slave mode.
3390 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3391 * a timer instance can operate as a slave timer.
3392 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3393 * @param TIMx Timer instance
3394 * @retval None
3395 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3396 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3397 {
3398 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3399 }
3400
3401 /**
3402 * @brief Disable the Master/Slave mode.
3403 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3404 * a timer instance can operate as a slave timer.
3405 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3406 * @param TIMx Timer instance
3407 * @retval None
3408 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3409 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3410 {
3411 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3412 }
3413
3414 /**
3415 * @brief Indicates whether the Master/Slave mode is enabled.
3416 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3417 * a timer instance can operate as a slave timer.
3418 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3419 * @param TIMx Timer instance
3420 * @retval State of bit (1 or 0).
3421 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3422 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3423 {
3424 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3425 }
3426
3427 /**
3428 * @brief Configure the external trigger (ETR) input.
3429 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3430 * a timer instance provides an external trigger input.
3431 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3432 * SMCR ETPS LL_TIM_ConfigETR\n
3433 * SMCR ETF LL_TIM_ConfigETR
3434 * @param TIMx Timer instance
3435 * @param ETRPolarity This parameter can be one of the following values:
3436 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3437 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3438 * @param ETRPrescaler This parameter can be one of the following values:
3439 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3440 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3441 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3442 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3443 * @param ETRFilter This parameter can be one of the following values:
3444 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3445 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3446 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3447 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3448 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3449 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3450 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3451 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3452 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3453 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3454 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3455 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3456 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3457 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3458 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3459 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3460 * @retval None
3461 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3462 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3463 uint32_t ETRFilter)
3464 {
3465 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3466 }
3467
3468 /**
3469 * @brief Select the external trigger (ETR) input source.
3470 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3471 * not a timer instance supports ETR source selection.
3472 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
3473 * @param TIMx Timer instance
3474 * @param ETRSource This parameter can be one of the following values:
3475 * @arg @ref LL_TIM_ETRSOURCE_LEGACY
3476 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3477 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3478 * @retval None
3479 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3480 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3481 {
3482 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
3483 }
3484
3485 /**
3486 * @}
3487 */
3488
3489 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3490 * @{
3491 */
3492 /**
3493 * @brief Enable the break function.
3494 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3495 * a timer instance provides a break input.
3496 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3497 * @param TIMx Timer instance
3498 * @retval None
3499 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3500 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3501 {
3502 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3503 }
3504
3505 /**
3506 * @brief Disable the break function.
3507 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3508 * @param TIMx Timer instance
3509 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3510 * a timer instance provides a break input.
3511 * @retval None
3512 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3513 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3514 {
3515 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3516 }
3517
3518 /**
3519 * @brief Configure the break input.
3520 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3521 * a timer instance provides a break input.
3522 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3523 * BDTR BKF LL_TIM_ConfigBRK
3524 * @param TIMx Timer instance
3525 * @param BreakPolarity This parameter can be one of the following values:
3526 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3527 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3528 * @param BreakFilter This parameter can be one of the following values:
3529 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3530 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3531 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3532 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3533 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3534 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3535 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3536 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3537 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3538 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3539 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3540 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3541 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3542 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3543 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3544 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3545 * @retval None
3546 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3547 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3548 uint32_t BreakFilter)
3549 {
3550 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3551 }
3552
3553 /**
3554 * @brief Enable the break 2 function.
3555 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3556 * a timer instance provides a second break input.
3557 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3558 * @param TIMx Timer instance
3559 * @retval None
3560 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3561 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3562 {
3563 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3564 }
3565
3566 /**
3567 * @brief Disable the break 2 function.
3568 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3569 * a timer instance provides a second break input.
3570 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3571 * @param TIMx Timer instance
3572 * @retval None
3573 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3574 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3575 {
3576 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3577 }
3578
3579 /**
3580 * @brief Configure the break 2 input.
3581 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3582 * a timer instance provides a second break input.
3583 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3584 * BDTR BK2F LL_TIM_ConfigBRK2
3585 * @param TIMx Timer instance
3586 * @param Break2Polarity This parameter can be one of the following values:
3587 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3588 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3589 * @param Break2Filter This parameter can be one of the following values:
3590 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3591 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3592 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3593 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3594 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3595 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3596 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3597 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3598 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3599 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3600 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3601 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3602 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3603 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3604 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3605 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3606 * @retval None
3607 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3608 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3609 {
3610 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3611 }
3612
3613 /**
3614 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3615 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3616 * a timer instance provides a break input.
3617 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3618 * BDTR OSSR LL_TIM_SetOffStates
3619 * @param TIMx Timer instance
3620 * @param OffStateIdle This parameter can be one of the following values:
3621 * @arg @ref LL_TIM_OSSI_DISABLE
3622 * @arg @ref LL_TIM_OSSI_ENABLE
3623 * @param OffStateRun This parameter can be one of the following values:
3624 * @arg @ref LL_TIM_OSSR_DISABLE
3625 * @arg @ref LL_TIM_OSSR_ENABLE
3626 * @retval None
3627 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3628 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3629 {
3630 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3631 }
3632
3633 /**
3634 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3635 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3636 * a timer instance provides a break input.
3637 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3638 * @param TIMx Timer instance
3639 * @retval None
3640 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3641 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3642 {
3643 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3644 }
3645
3646 /**
3647 * @brief Disable automatic output (MOE can be set only by software).
3648 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3649 * a timer instance provides a break input.
3650 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3651 * @param TIMx Timer instance
3652 * @retval None
3653 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3654 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3655 {
3656 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3657 }
3658
3659 /**
3660 * @brief Indicate whether automatic output is enabled.
3661 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3662 * a timer instance provides a break input.
3663 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3664 * @param TIMx Timer instance
3665 * @retval State of bit (1 or 0).
3666 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3667 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3668 {
3669 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3670 }
3671
3672 /**
3673 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3674 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3675 * software and is reset in case of break or break2 event
3676 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3677 * a timer instance provides a break input.
3678 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3679 * @param TIMx Timer instance
3680 * @retval None
3681 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3682 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3683 {
3684 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3685 }
3686
3687 /**
3688 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3689 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3690 * software and is reset in case of break or break2 event.
3691 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3692 * a timer instance provides a break input.
3693 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3694 * @param TIMx Timer instance
3695 * @retval None
3696 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3697 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3698 {
3699 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3700 }
3701
3702 /**
3703 * @brief Indicates whether outputs are enabled.
3704 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3705 * a timer instance provides a break input.
3706 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3707 * @param TIMx Timer instance
3708 * @retval State of bit (1 or 0).
3709 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3710 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3711 {
3712 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3713 }
3714
3715 /**
3716 * @brief Enable the signals connected to the designated timer break input.
3717 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3718 * or not a timer instance allows for break input selection.
3719 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
3720 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
3721 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
3722 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3723 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
3724 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3725 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3726 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3727 * @param TIMx Timer instance
3728 * @param BreakInput This parameter can be one of the following values:
3729 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3730 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3731 * @param Source This parameter can be one of the following values:
3732 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3733 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3734 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3735 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3736 * @retval None
3737 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3738 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3739 {
3740 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3741 SET_BIT(*pReg, Source);
3742 }
3743
3744 /**
3745 * @brief Disable the signals connected to the designated timer break input.
3746 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3747 * or not a timer instance allows for break input selection.
3748 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
3749 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
3750 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
3751 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3752 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
3753 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3754 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3755 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3756 * @param TIMx Timer instance
3757 * @param BreakInput This parameter can be one of the following values:
3758 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3759 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3760 * @param Source This parameter can be one of the following values:
3761 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3762 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3763 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3764 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3765 * @retval None
3766 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3767 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3768 {
3769 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3770 CLEAR_BIT(*pReg, Source);
3771 }
3772
3773 /**
3774 * @brief Set the polarity of the break signal for the timer break input.
3775 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3776 * or not a timer instance allows for break input selection.
3777 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3778 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3779 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3780 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3781 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3782 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3783 * @param TIMx Timer instance
3784 * @param BreakInput This parameter can be one of the following values:
3785 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3786 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3787 * @param Source This parameter can be one of the following values:
3788 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3789 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3790 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3791 * @param Polarity This parameter can be one of the following values:
3792 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3793 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3794 * @retval None
3795 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3796 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3797 uint32_t Polarity)
3798 {
3799 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3800 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3801 }
3802 /**
3803 * @}
3804 */
3805
3806 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3807 * @{
3808 */
3809 /**
3810 * @brief Configures the timer DMA burst feature.
3811 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3812 * not a timer instance supports the DMA burst mode.
3813 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3814 * DCR DBA LL_TIM_ConfigDMABurst
3815 * @param TIMx Timer instance
3816 * @param DMABurstBaseAddress This parameter can be one of the following values:
3817 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3818 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3819 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3820 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3821 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3822 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3823 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3824 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3825 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3826 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3827 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3828 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3829 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3830 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3831 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3832 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3833 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3834 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3835 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3836 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3837 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3838 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3839 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
3840 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
3841 * @param DMABurstLength This parameter can be one of the following values:
3842 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3843 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3844 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3845 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3846 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3847 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3848 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3849 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3850 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3851 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3852 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3853 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3854 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3855 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3856 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3857 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3858 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3859 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3860 * @retval None
3861 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3862 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3863 {
3864 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3865 }
3866
3867 /**
3868 * @}
3869 */
3870
3871 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3872 * @{
3873 */
3874 /**
3875 * @brief Remap TIM inputs (input channel, internal/external triggers).
3876 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3877 * a some timer inputs can be remapped.
3878 @if STM32L486xx
3879 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3880 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3881 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3882 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
3883 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3884 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
3885 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3886 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3887 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3888 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
3889 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3890 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3891 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3892 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3893 @endif
3894 @if STM32L443xx
3895 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3896 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3897 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3898 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3899 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3900 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3901 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3902 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3903 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3904 @endif
3905 * @param TIMx Timer instance
3906 * @param Remap Remap param depends on the TIMx. Description available only
3907 * in CHM version of the User Manual (not in .pdf).
3908 * Otherwise see Reference Manual description of OR registers.
3909 *
3910 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3911 *
3912 @if STM32L486xx
3913 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3914 *
3915 * . . ADC1_RMP can be one of the following values
3916 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3917 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3918 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3919 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3920 *
3921 * . . ADC3_RMP can be one of the following values
3922 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
3923 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
3924 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
3925 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
3926 *
3927 * . . TI1_RMP can be one of the following values
3928 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3929 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3930 *
3931 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3932 *
3933 * ITR1_RMP can be one of the following values
3934 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3935 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3936 *
3937 * . . ETR1_RMP can be one of the following values
3938 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3939 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3940 *
3941 * . . TI4_RMP can be one of the following values
3942 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3943 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3944 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3945 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3946 *
3947 * TIM3: one of the following values
3948 *
3949 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3950 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3951 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
3952 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
3953 *
3954 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3955 *
3956 * . . ADC1_RMP can be one of the following values
3957 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
3958 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
3959 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
3960 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
3961 *
3962 * . . ADC3_RMP can be one of the following values
3963 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
3964 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
3965 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
3966 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
3967 *
3968 * . . TI1_RMP can be one of the following values
3969 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3970 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
3971 *
3972 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3973 *
3974 * . . TI1_RMP can be one of the following values
3975 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3976 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3977 *
3978 * . . ENCODER_MODE can be one of the following values
3979 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3980 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3981 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3982 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3983 *
3984 * TIM16: one of the following values
3985 *
3986 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3987 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3988 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3989 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3990 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
3991 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
3992 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
3993 *
3994 * TIM17: one of the following values
3995 *
3996 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3997 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3998 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3999 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
4000 @endif
4001 @if STM32L443xx
4002 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
4003 *
4004 * . . ADC1_RMP can be one of the following values
4005 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
4006 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
4007 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
4008 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
4009 *
4010 * . . TI1_RMP can be one of the following values
4011 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
4012 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
4013 *
4014 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
4015 *
4016 * ITR1_RMP can be one of the following values
4017 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
4018 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
4019 *
4020 * . . ETR1_RMP can be one of the following values
4021 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
4022 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
4023 *
4024 * . . TI4_RMP can be one of the following values
4025 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
4026 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
4027 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
4028 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
4029 *
4030 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
4031 *
4032 * . . TI1_RMP can be one of the following values
4033 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4034 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
4035 *
4036 * . . ENCODER_MODE can be one of the following values
4037 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
4038 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
4039 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
4040 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
4041 *
4042 * TIM16: one of the following values
4043 *
4044 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4045 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
4046 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
4047 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
4048 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
4049 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
4050 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
4051 @endif
4052 * @retval None
4053 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4054 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4055 {
4056 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
4057 }
4058
4059 /**
4060 * @}
4061 */
4062
4063 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4064 * @{
4065 */
4066 /**
4067 * @brief Set the OCREF clear input source
4068 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4069 * @note This function can only be used in Output compare and PWM modes.
4070 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4071 * @param TIMx Timer instance
4072 * @param OCRefClearInputSource This parameter can be one of the following values:
4073 * @arg @ref LL_TIM_OCREF_CLR_INT_NC
4074 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4075 * @retval None
4076 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4077 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4078 {
4079 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4080 }
4081 /**
4082 * @}
4083 */
4084
4085 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4086 * @{
4087 */
4088 /**
4089 * @brief Clear the update interrupt flag (UIF).
4090 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4091 * @param TIMx Timer instance
4092 * @retval None
4093 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4094 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4095 {
4096 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4097 }
4098
4099 /**
4100 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4101 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4102 * @param TIMx Timer instance
4103 * @retval State of bit (1 or 0).
4104 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4105 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4106 {
4107 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4108 }
4109
4110 /**
4111 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4112 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4113 * @param TIMx Timer instance
4114 * @retval None
4115 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4116 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4117 {
4118 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4119 }
4120
4121 /**
4122 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4123 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4124 * @param TIMx Timer instance
4125 * @retval State of bit (1 or 0).
4126 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4127 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4128 {
4129 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4130 }
4131
4132 /**
4133 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4134 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4135 * @param TIMx Timer instance
4136 * @retval None
4137 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4138 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4139 {
4140 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4141 }
4142
4143 /**
4144 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4145 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4146 * @param TIMx Timer instance
4147 * @retval State of bit (1 or 0).
4148 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4149 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4150 {
4151 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4152 }
4153
4154 /**
4155 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4156 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4157 * @param TIMx Timer instance
4158 * @retval None
4159 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4160 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4161 {
4162 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4163 }
4164
4165 /**
4166 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4167 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4168 * @param TIMx Timer instance
4169 * @retval State of bit (1 or 0).
4170 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4171 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4172 {
4173 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4174 }
4175
4176 /**
4177 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4178 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4179 * @param TIMx Timer instance
4180 * @retval None
4181 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4182 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4183 {
4184 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4185 }
4186
4187 /**
4188 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4189 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4190 * @param TIMx Timer instance
4191 * @retval State of bit (1 or 0).
4192 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4193 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4194 {
4195 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4196 }
4197
4198 /**
4199 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4200 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4201 * @param TIMx Timer instance
4202 * @retval None
4203 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4204 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4205 {
4206 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4207 }
4208
4209 /**
4210 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4211 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4212 * @param TIMx Timer instance
4213 * @retval State of bit (1 or 0).
4214 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4215 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4216 {
4217 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4218 }
4219
4220 /**
4221 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4222 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4223 * @param TIMx Timer instance
4224 * @retval None
4225 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4226 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4227 {
4228 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4229 }
4230
4231 /**
4232 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4233 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4234 * @param TIMx Timer instance
4235 * @retval State of bit (1 or 0).
4236 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4238 {
4239 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4240 }
4241
4242 /**
4243 * @brief Clear the commutation interrupt flag (COMIF).
4244 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4245 * @param TIMx Timer instance
4246 * @retval None
4247 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4248 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4249 {
4250 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4251 }
4252
4253 /**
4254 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4255 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4256 * @param TIMx Timer instance
4257 * @retval State of bit (1 or 0).
4258 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4260 {
4261 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4262 }
4263
4264 /**
4265 * @brief Clear the trigger interrupt flag (TIF).
4266 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4267 * @param TIMx Timer instance
4268 * @retval None
4269 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4270 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4271 {
4272 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4273 }
4274
4275 /**
4276 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4277 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4278 * @param TIMx Timer instance
4279 * @retval State of bit (1 or 0).
4280 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4281 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4282 {
4283 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4284 }
4285
4286 /**
4287 * @brief Clear the break interrupt flag (BIF).
4288 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4289 * @param TIMx Timer instance
4290 * @retval None
4291 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4292 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4293 {
4294 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4295 }
4296
4297 /**
4298 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4299 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4300 * @param TIMx Timer instance
4301 * @retval State of bit (1 or 0).
4302 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4303 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4304 {
4305 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4306 }
4307
4308 /**
4309 * @brief Clear the break 2 interrupt flag (B2IF).
4310 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4311 * @param TIMx Timer instance
4312 * @retval None
4313 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4314 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4315 {
4316 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4317 }
4318
4319 /**
4320 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4321 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4322 * @param TIMx Timer instance
4323 * @retval State of bit (1 or 0).
4324 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4325 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4326 {
4327 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4328 }
4329
4330 /**
4331 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4332 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4333 * @param TIMx Timer instance
4334 * @retval None
4335 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4336 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4337 {
4338 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4339 }
4340
4341 /**
4342 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4343 * (Capture/Compare 1 interrupt is pending).
4344 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4345 * @param TIMx Timer instance
4346 * @retval State of bit (1 or 0).
4347 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4348 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4349 {
4350 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4351 }
4352
4353 /**
4354 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4355 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4356 * @param TIMx Timer instance
4357 * @retval None
4358 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4359 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4360 {
4361 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4362 }
4363
4364 /**
4365 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4366 * (Capture/Compare 2 over-capture interrupt is pending).
4367 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4368 * @param TIMx Timer instance
4369 * @retval State of bit (1 or 0).
4370 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4371 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4372 {
4373 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4374 }
4375
4376 /**
4377 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4378 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4379 * @param TIMx Timer instance
4380 * @retval None
4381 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4382 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4383 {
4384 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4385 }
4386
4387 /**
4388 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4389 * (Capture/Compare 3 over-capture interrupt is pending).
4390 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4391 * @param TIMx Timer instance
4392 * @retval State of bit (1 or 0).
4393 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4394 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4395 {
4396 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4397 }
4398
4399 /**
4400 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4401 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4402 * @param TIMx Timer instance
4403 * @retval None
4404 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4405 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4406 {
4407 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4408 }
4409
4410 /**
4411 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4412 * (Capture/Compare 4 over-capture interrupt is pending).
4413 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4414 * @param TIMx Timer instance
4415 * @retval State of bit (1 or 0).
4416 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4417 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4418 {
4419 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4420 }
4421
4422 /**
4423 * @brief Clear the system break interrupt flag (SBIF).
4424 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4425 * @param TIMx Timer instance
4426 * @retval None
4427 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4428 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4429 {
4430 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4431 }
4432
4433 /**
4434 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4435 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4436 * @param TIMx Timer instance
4437 * @retval State of bit (1 or 0).
4438 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4439 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4440 {
4441 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4442 }
4443
4444 /**
4445 * @}
4446 */
4447
4448 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4449 * @{
4450 */
4451 /**
4452 * @brief Enable update interrupt (UIE).
4453 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4454 * @param TIMx Timer instance
4455 * @retval None
4456 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4457 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4458 {
4459 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4460 }
4461
4462 /**
4463 * @brief Disable update interrupt (UIE).
4464 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4465 * @param TIMx Timer instance
4466 * @retval None
4467 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4468 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4469 {
4470 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4471 }
4472
4473 /**
4474 * @brief Indicates whether the update interrupt (UIE) is enabled.
4475 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4476 * @param TIMx Timer instance
4477 * @retval State of bit (1 or 0).
4478 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4479 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4480 {
4481 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4482 }
4483
4484 /**
4485 * @brief Enable capture/compare 1 interrupt (CC1IE).
4486 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4487 * @param TIMx Timer instance
4488 * @retval None
4489 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4490 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4491 {
4492 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4493 }
4494
4495 /**
4496 * @brief Disable capture/compare 1 interrupt (CC1IE).
4497 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4498 * @param TIMx Timer instance
4499 * @retval None
4500 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4501 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4502 {
4503 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4504 }
4505
4506 /**
4507 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4508 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4509 * @param TIMx Timer instance
4510 * @retval State of bit (1 or 0).
4511 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4512 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4513 {
4514 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4515 }
4516
4517 /**
4518 * @brief Enable capture/compare 2 interrupt (CC2IE).
4519 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4520 * @param TIMx Timer instance
4521 * @retval None
4522 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4523 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4524 {
4525 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4526 }
4527
4528 /**
4529 * @brief Disable capture/compare 2 interrupt (CC2IE).
4530 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4531 * @param TIMx Timer instance
4532 * @retval None
4533 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4534 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4535 {
4536 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4537 }
4538
4539 /**
4540 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4541 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4542 * @param TIMx Timer instance
4543 * @retval State of bit (1 or 0).
4544 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4545 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4546 {
4547 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4548 }
4549
4550 /**
4551 * @brief Enable capture/compare 3 interrupt (CC3IE).
4552 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4553 * @param TIMx Timer instance
4554 * @retval None
4555 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4556 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4557 {
4558 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4559 }
4560
4561 /**
4562 * @brief Disable capture/compare 3 interrupt (CC3IE).
4563 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4564 * @param TIMx Timer instance
4565 * @retval None
4566 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4567 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4568 {
4569 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4570 }
4571
4572 /**
4573 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4574 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4575 * @param TIMx Timer instance
4576 * @retval State of bit (1 or 0).
4577 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4578 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4579 {
4580 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4581 }
4582
4583 /**
4584 * @brief Enable capture/compare 4 interrupt (CC4IE).
4585 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4586 * @param TIMx Timer instance
4587 * @retval None
4588 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4589 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4590 {
4591 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4592 }
4593
4594 /**
4595 * @brief Disable capture/compare 4 interrupt (CC4IE).
4596 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4597 * @param TIMx Timer instance
4598 * @retval None
4599 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4600 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4601 {
4602 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4603 }
4604
4605 /**
4606 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4607 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4608 * @param TIMx Timer instance
4609 * @retval State of bit (1 or 0).
4610 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4611 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4612 {
4613 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4614 }
4615
4616 /**
4617 * @brief Enable commutation interrupt (COMIE).
4618 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4619 * @param TIMx Timer instance
4620 * @retval None
4621 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4622 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4623 {
4624 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4625 }
4626
4627 /**
4628 * @brief Disable commutation interrupt (COMIE).
4629 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4630 * @param TIMx Timer instance
4631 * @retval None
4632 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4633 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4634 {
4635 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4636 }
4637
4638 /**
4639 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4640 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4641 * @param TIMx Timer instance
4642 * @retval State of bit (1 or 0).
4643 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4644 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4645 {
4646 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4647 }
4648
4649 /**
4650 * @brief Enable trigger interrupt (TIE).
4651 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4652 * @param TIMx Timer instance
4653 * @retval None
4654 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4655 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4656 {
4657 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4658 }
4659
4660 /**
4661 * @brief Disable trigger interrupt (TIE).
4662 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4663 * @param TIMx Timer instance
4664 * @retval None
4665 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4666 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4667 {
4668 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4669 }
4670
4671 /**
4672 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4673 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4674 * @param TIMx Timer instance
4675 * @retval State of bit (1 or 0).
4676 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4677 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4678 {
4679 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4680 }
4681
4682 /**
4683 * @brief Enable break interrupt (BIE).
4684 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4685 * @param TIMx Timer instance
4686 * @retval None
4687 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4688 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4689 {
4690 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4691 }
4692
4693 /**
4694 * @brief Disable break interrupt (BIE).
4695 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4696 * @param TIMx Timer instance
4697 * @retval None
4698 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4699 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4700 {
4701 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4702 }
4703
4704 /**
4705 * @brief Indicates whether the break interrupt (BIE) is enabled.
4706 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4707 * @param TIMx Timer instance
4708 * @retval State of bit (1 or 0).
4709 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4710 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4711 {
4712 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4713 }
4714
4715 /**
4716 * @}
4717 */
4718
4719 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4720 * @{
4721 */
4722 /**
4723 * @brief Enable update DMA request (UDE).
4724 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4725 * @param TIMx Timer instance
4726 * @retval None
4727 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4728 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4729 {
4730 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4731 }
4732
4733 /**
4734 * @brief Disable update DMA request (UDE).
4735 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4736 * @param TIMx Timer instance
4737 * @retval None
4738 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4739 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4740 {
4741 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4742 }
4743
4744 /**
4745 * @brief Indicates whether the update DMA request (UDE) is enabled.
4746 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4747 * @param TIMx Timer instance
4748 * @retval State of bit (1 or 0).
4749 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4750 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4751 {
4752 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4753 }
4754
4755 /**
4756 * @brief Enable capture/compare 1 DMA request (CC1DE).
4757 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4758 * @param TIMx Timer instance
4759 * @retval None
4760 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4761 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4762 {
4763 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4764 }
4765
4766 /**
4767 * @brief Disable capture/compare 1 DMA request (CC1DE).
4768 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4769 * @param TIMx Timer instance
4770 * @retval None
4771 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4772 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4773 {
4774 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4775 }
4776
4777 /**
4778 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4779 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4780 * @param TIMx Timer instance
4781 * @retval State of bit (1 or 0).
4782 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4783 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4784 {
4785 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4786 }
4787
4788 /**
4789 * @brief Enable capture/compare 2 DMA request (CC2DE).
4790 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4791 * @param TIMx Timer instance
4792 * @retval None
4793 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4794 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4795 {
4796 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4797 }
4798
4799 /**
4800 * @brief Disable capture/compare 2 DMA request (CC2DE).
4801 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4802 * @param TIMx Timer instance
4803 * @retval None
4804 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4805 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4806 {
4807 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4808 }
4809
4810 /**
4811 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4812 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4813 * @param TIMx Timer instance
4814 * @retval State of bit (1 or 0).
4815 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4816 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4817 {
4818 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4819 }
4820
4821 /**
4822 * @brief Enable capture/compare 3 DMA request (CC3DE).
4823 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4824 * @param TIMx Timer instance
4825 * @retval None
4826 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4827 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4828 {
4829 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4830 }
4831
4832 /**
4833 * @brief Disable capture/compare 3 DMA request (CC3DE).
4834 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4835 * @param TIMx Timer instance
4836 * @retval None
4837 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4838 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4839 {
4840 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4841 }
4842
4843 /**
4844 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4845 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4846 * @param TIMx Timer instance
4847 * @retval State of bit (1 or 0).
4848 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4849 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4850 {
4851 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4852 }
4853
4854 /**
4855 * @brief Enable capture/compare 4 DMA request (CC4DE).
4856 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4857 * @param TIMx Timer instance
4858 * @retval None
4859 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4860 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4861 {
4862 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4863 }
4864
4865 /**
4866 * @brief Disable capture/compare 4 DMA request (CC4DE).
4867 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4868 * @param TIMx Timer instance
4869 * @retval None
4870 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4871 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4872 {
4873 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4874 }
4875
4876 /**
4877 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4878 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4879 * @param TIMx Timer instance
4880 * @retval State of bit (1 or 0).
4881 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4882 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4883 {
4884 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4885 }
4886
4887 /**
4888 * @brief Enable commutation DMA request (COMDE).
4889 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4890 * @param TIMx Timer instance
4891 * @retval None
4892 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4893 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4894 {
4895 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4896 }
4897
4898 /**
4899 * @brief Disable commutation DMA request (COMDE).
4900 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4901 * @param TIMx Timer instance
4902 * @retval None
4903 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4904 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4905 {
4906 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4907 }
4908
4909 /**
4910 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4911 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4912 * @param TIMx Timer instance
4913 * @retval State of bit (1 or 0).
4914 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4915 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4916 {
4917 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4918 }
4919
4920 /**
4921 * @brief Enable trigger interrupt (TDE).
4922 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4923 * @param TIMx Timer instance
4924 * @retval None
4925 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4926 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4927 {
4928 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4929 }
4930
4931 /**
4932 * @brief Disable trigger interrupt (TDE).
4933 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4934 * @param TIMx Timer instance
4935 * @retval None
4936 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4937 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4938 {
4939 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4940 }
4941
4942 /**
4943 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4944 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4945 * @param TIMx Timer instance
4946 * @retval State of bit (1 or 0).
4947 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4948 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4949 {
4950 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4951 }
4952
4953 /**
4954 * @}
4955 */
4956
4957 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4958 * @{
4959 */
4960 /**
4961 * @brief Generate an update event.
4962 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4963 * @param TIMx Timer instance
4964 * @retval None
4965 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4966 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4967 {
4968 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4969 }
4970
4971 /**
4972 * @brief Generate Capture/Compare 1 event.
4973 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4974 * @param TIMx Timer instance
4975 * @retval None
4976 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4977 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4978 {
4979 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4980 }
4981
4982 /**
4983 * @brief Generate Capture/Compare 2 event.
4984 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4985 * @param TIMx Timer instance
4986 * @retval None
4987 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4988 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4989 {
4990 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4991 }
4992
4993 /**
4994 * @brief Generate Capture/Compare 3 event.
4995 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4996 * @param TIMx Timer instance
4997 * @retval None
4998 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4999 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
5000 {
5001 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
5002 }
5003
5004 /**
5005 * @brief Generate Capture/Compare 4 event.
5006 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
5007 * @param TIMx Timer instance
5008 * @retval None
5009 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)5010 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
5011 {
5012 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
5013 }
5014
5015 /**
5016 * @brief Generate commutation event.
5017 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
5018 * @param TIMx Timer instance
5019 * @retval None
5020 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)5021 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5022 {
5023 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5024 }
5025
5026 /**
5027 * @brief Generate trigger event.
5028 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5029 * @param TIMx Timer instance
5030 * @retval None
5031 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)5032 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5033 {
5034 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5035 }
5036
5037 /**
5038 * @brief Generate break event.
5039 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5040 * @param TIMx Timer instance
5041 * @retval None
5042 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)5043 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5044 {
5045 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5046 }
5047
5048 /**
5049 * @brief Generate break 2 event.
5050 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5051 * @param TIMx Timer instance
5052 * @retval None
5053 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5054 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5055 {
5056 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5057 }
5058
5059 /**
5060 * @}
5061 */
5062
5063 #if defined(USE_FULL_LL_DRIVER)
5064 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5065 * @{
5066 */
5067
5068 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
5069 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5070 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5071 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5072 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5073 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5074 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5075 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5076 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5077 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5078 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5079 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5080 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5081 /**
5082 * @}
5083 */
5084 #endif /* USE_FULL_LL_DRIVER */
5085
5086 /**
5087 * @}
5088 */
5089
5090 /**
5091 * @}
5092 */
5093
5094 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
5095
5096 /**
5097 * @}
5098 */
5099
5100 #ifdef __cplusplus
5101 }
5102 #endif
5103
5104 #endif /* __STM32L4xx_LL_TIM_H */
5105
