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Searched refs:TIM_CCR5_CCR5_Pos (Results 1 – 25 of 176) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wb0x/soc/
Dstm32wb07.h6043 #define TIM_CCR5_CCR5_Pos (0UL) /*!<TIM CCR5: C… macro
6046 …fine TIM_CCR5_CCR5_0 (0x1U << TIM_CCR5_CCR5_Pos)
6047 …fine TIM_CCR5_CCR5_1 (0x2U << TIM_CCR5_CCR5_Pos)
6048 …fine TIM_CCR5_CCR5_2 (0x4U << TIM_CCR5_CCR5_Pos)
6049 …fine TIM_CCR5_CCR5_3 (0x8U << TIM_CCR5_CCR5_Pos)
6050 …ine TIM_CCR5_CCR5_4 (0x10U << TIM_CCR5_CCR5_Pos)
6051 …ine TIM_CCR5_CCR5_5 (0x20U << TIM_CCR5_CCR5_Pos)
6052 …ine TIM_CCR5_CCR5_6 (0x40U << TIM_CCR5_CCR5_Pos)
6053 …ine TIM_CCR5_CCR5_7 (0x80U << TIM_CCR5_CCR5_Pos)
6054 …ne TIM_CCR5_CCR5_8 (0x100U << TIM_CCR5_CCR5_Pos)
[all …]
Dstm32wb06.h6043 #define TIM_CCR5_CCR5_Pos (0UL) /*!<TIM CCR5: C… macro
6046 …fine TIM_CCR5_CCR5_0 (0x1U << TIM_CCR5_CCR5_Pos)
6047 …fine TIM_CCR5_CCR5_1 (0x2U << TIM_CCR5_CCR5_Pos)
6048 …fine TIM_CCR5_CCR5_2 (0x4U << TIM_CCR5_CCR5_Pos)
6049 …fine TIM_CCR5_CCR5_3 (0x8U << TIM_CCR5_CCR5_Pos)
6050 …ine TIM_CCR5_CCR5_4 (0x10U << TIM_CCR5_CCR5_Pos)
6051 …ine TIM_CCR5_CCR5_5 (0x20U << TIM_CCR5_CCR5_Pos)
6052 …ine TIM_CCR5_CCR5_6 (0x40U << TIM_CCR5_CCR5_Pos)
6053 …ine TIM_CCR5_CCR5_7 (0x80U << TIM_CCR5_CCR5_Pos)
6054 …ne TIM_CCR5_CCR5_8 (0x100U << TIM_CCR5_CCR5_Pos)
[all …]
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h5699 #define TIM_CCR5_CCR5_Pos (0U) macro
5700 #define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
Dstm32c031xx.h5862 #define TIM_CCR5_CCR5_Pos (0U) macro
5863 #define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
Dstm32c071xx.h6366 #define TIM_CCR5_CCR5_Pos (0U) macro
6367 #define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h6311 #define TIM_CCR5_CCR5_Pos (0U) macro
6312 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g050xx.h6372 #define TIM_CCR5_CCR5_Pos (0U) macro
6373 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g070xx.h6511 #define TIM_CCR5_CCR5_Pos (0U) macro
6512 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g031xx.h6575 #define TIM_CCR5_CCR5_Pos (0U) macro
6576 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g041xx.h6879 #define TIM_CCR5_CCR5_Pos (0U) macro
6880 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g051xx.h6974 #define TIM_CCR5_CCR5_Pos (0U) macro
6975 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g061xx.h7278 #define TIM_CCR5_CCR5_Pos (0U) macro
7279 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g071xx.h7358 #define TIM_CCR5_CCR5_Pos (0U) macro
7359 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g081xx.h7662 #define TIM_CCR5_CCR5_Pos (0U) macro
7663 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32g0b0xx.h7691 #define TIM_CCR5_CCR5_Pos (0U) macro
7692 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7049 #define TIM_CCR5_CCR5_Pos (0U) macro
7050 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32f318xx.h7036 #define TIM_CCR5_CCR5_Pos (0U) macro
7037 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h9219 #define TIM_CCR5_CCR5_Pos (0U) macro
9220 #define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x0000FFFF */
Dstm32wle5xx.h9219 #define TIM_CCR5_CCR5_Pos (0U) macro
9220 #define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x0000FFFF */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8807 #define TIM_CCR5_CCR5_Pos (0U) macro
8808 #define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF…
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h7751 #define TIM_CCR5_CCR5_Pos (0U) macro
7752 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32u083xx.h8688 #define TIM_CCR5_CCR5_Pos (0U) macro
8689 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h9417 #define TIM_CCR5_CCR5_Pos (0U) macro
9418 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
Dstm32wb1mxx.h9440 #define TIM_CCR5_CCR5_Pos (0U) macro
9441 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h9268 #define TIM_CCR5_CCR5_Pos (0U) macro
9269 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */

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