1 /**
2   ******************************************************************************
3   * @file    stm32wb06.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for stm32wb06 devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2024 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS_Device
28   * @{
29   */
30 
31 /** @addtogroup stm32wb06
32   * @{
33   */
34 
35 #ifndef __STM32WB06_H
36 #define __STM32WB06_H
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif /* __cplusplus */
41 
42 /** @addtogroup Peripheral_interrupt_number_definition
43   * @{
44   */
45 
46 /**
47   * @brief stm32wb06 Interrupt Number Definition, according to the selected device
48   *        in @ref Library_configuration_section
49   */
50 
51 typedef enum
52 {
53   /* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
54   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
55   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
56   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
57   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
58   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
59   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
60   /* =========================================  stm32wb06 Specific Interrupt Numbers  ========================================= */
61   FLASH_IRQn                =   0,              /*!< 0  NVM interrupt                                                          */
62   RCC_IRQn                  =   1,              /*!< 1  RCC interrupt                                                          */
63   PVD_IRQn                  =   2,              /*!< 2  PVD interrupt                                                          */
64   I2C1_IRQn                 =   3,              /*!< 3  I2C1 interrurpt                                                        */
65   I2C2_IRQn                 =   4,              /*!< 4  I2C2 interrupt                                                         */
66   SPI1_IRQn                 =   5,              /*!< 5  SPI1 interrupt                                                         */
67   SPI2_IRQn                 =   6,              /*!< 6  SPI2 interrupt                                                         */
68   SPI3_IRQn                 =   7,              /*!< 7  SPI3 interrupt                                                         */
69   USART1_IRQn               =   8,              /*!< 8  USART interrupt                                                        */
70   LPUART1_IRQn              =   9,              /*!< 9  Low Power UART interrupt                                               */
71   TIM1_IRQn                 =  10,              /*!< 10 Timer 1 interrupt                                                      */
72   RTC_IRQn                  =  11,              /*!< 11 RTC interrupt                                                          */
73   ADC_IRQn                  =  12,              /*!< 12 ADC interrupt                                                          */
74   PKA_IRQn                  =  13,              /*!< 13 PKA interrupt                                                          */
75   UPCONV_IRQn               =  14,              /*!< 14 AHB_UP_CONVERTER interrupt                                             */
76   GPIOA_IRQn                =  15,              /*!< 15 GPIOA interrupt                                                        */
77   GPIOB_IRQn                =  16,              /*!< 16 GPIOB interrupt                                                        */
78   DMA_IRQn                  =  17,              /*!< 17 DMA interrupt                                                          */
79   RADIO_TXRX_IRQn           =  18,              /*!< 18 RADIO Tx/Rx interrupt                                                  */
80   RADIO_TIMER_ERROR_IRQn    =  20,              /*!< 20  RADIO TIMER Error interrupt                                           */
81   RADIO_TIMER_CPU_WKUP_IRQn =  23,              /*!< 23  RADIO TIMER CPU Wakeup interrupt                                      */
82   RADIO_TIMER_TXRX_WKUP_IRQn =  24,             /*!< 24  RADIO TIMER Tx/Rx Wakeup interrupt                                    */
83   RADIO_TXRX_SEQ_IRQn       =  25               /*!< 25 RADIO Tx/Rx sequence interrupt                                         */
84 } IRQn_Type;
85 
86 
87 /* =========================================================================================================================== */
88 /* ================                           Processor and Core Peripheral Section                           ================ */
89 /* =========================================================================================================================== */
90 
91 /* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
92 /** @addtogroup Configuration_of_CMSIS
93   * @{
94   */
95 /**
96   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
97   */
98 
99 #define __CM0PLUS_REV                  1        /*!< CM0PLUS Core Revision r0p1                                                */
100 #define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
101 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
102 #define __VTOR_PRESENT                 1        /*!< Vector Table Offset Register supported                                    */
103 #define __MPU_PRESENT                  1        /*!< M0+ provides an MPU                                                       */
104 #define __FPU_PRESENT                  0        /*!< FPU not present                                                           */
105 /**
106   * @}
107   */
108 
109 
110 /*!< Device Electronic Signature */
111 #define PACKAGE_BASE          ((uint32_t)0x10001EECU)        /*!< Package data register base address                    */
112 #define UID64_BASE            ((uint32_t)0x10001EF0U)        /*!< 64-bit Unique device Identification                   */
113 #define FLASHSIZE_BASE        ((uint32_t)0x40001014U)        /*!< Flash size data register base address                 */
114 #define RAMSIZE_BASE          ((uint32_t)0x48500090U)        /*!< RAM size data register base address                   */
115 #define DEV_ID_BASE           ((uint32_t)0x40000000U)        /*!< Device version and cut version register base address  */
116 
117 
118 /** @} */ /* End of group Configuration_of_CMSIS */
119 
120 #include "core_cm0plus.h"            /* Cortex-M0+ processor and core peripherals */
121 #include <stdint.h>
122 
123 /* ========================================  Start of section using anonymous unions  ======================================== */
124 #if defined (__CC_ARM)
125 #pragma push
126 #pragma anon_unions
127 #elif defined (__ICCARM__)
128 #pragma language=extended
129 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
130 #pragma clang diagnostic push
131 #pragma clang diagnostic ignored "-Wc11-extensions"
132 #pragma clang diagnostic ignored "-Wreserved-id-macro"
133 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
134 #pragma clang diagnostic ignored "-Wnested-anon-types"
135 #elif defined (__GNUC__)
136 /* anonymous unions are enabled by default */
137 #elif defined (__TMS470__)
138 /* anonymous unions are enabled by default */
139 #elif defined (__TASKING__)
140 #pragma warning 586
141 #elif defined (__CSMC__)
142 /* anonymous unions are enabled by default */
143 #else
144 #warning Not supported compiler type
145 #endif
146 
147 
148 /* =========================================================================================================================== */
149 /* ================                            Device Specific Peripheral Section                             ================ */
150 /* =========================================================================================================================== */
151 
152 
153 /** @addtogroup Device_Peripheral_peripherals
154   * @{
155   */
156 
157 
158 /* =========================================================================================================================== */
159 /* ================                                            DMA                                            ================ */
160 /* =========================================================================================================================== */
161 
162 
163 /**
164   * @brief Direct memory access controller (DMA)
165   */
166 
167 typedef struct                                  /*!< DMA Structure                                                             */
168 {
169   __IO uint32_t  ISR;                          /*!< (@ 0x00000000) Interrupt status register                                  */
170   __IO uint32_t  IFCR;                         /*!< (@ 0x00000004) Interrupt flag clear register                              */
171 } DMA_TypeDef;
172 
173 typedef struct
174 {
175   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
176   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
177   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
178   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
179   __IO uint32_t RESERVED;
180 } DMA_Channel_TypeDef;
181 
182 
183 /* =========================================================================================================================== */
184 /* ================                                          DMAMUX                                           ================ */
185 /* =========================================================================================================================== */
186 
187 
188 /**
189   * @brief Direct memory access Multiplexer (DMAMUX)
190   */
191 
192 /**
193   * @brief DMA Multiplexer
194   */
195 typedef struct               /*!< DMAMUX Structure                                                                   */
196 {
197   __IO uint32_t   CxCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
198 } DMAMUX_Channel_TypeDef;
199 
200 
201 /* =========================================================================================================================== */
202 /* ================                                            CRC                                            ================ */
203 /* =========================================================================================================================== */
204 
205 
206 /**
207   * @brief Cyclic redundancy check calculation unit (CRC)
208   */
209 
210 typedef struct                                  /*!< CRC Structure                                                             */
211 {
212   __IO uint32_t  DR;                           /*!< (@ 0x00000000) Data register                                              */
213   __IO uint32_t  IDR;                          /*!< (@ 0x00000004) Independent data register                                  */
214   __IO uint32_t  CR;                           /*!< (@ 0x00000008) Control register                                           */
215   __IO uint32_t  RESERVED;
216   __IO uint32_t  INIT;                         /*!< (@ 0x00000010) Initial CRC value                                          */
217   __IO uint32_t  POL;                          /*!< (@ 0x00000014) Polynomial                                                 */
218 } CRC_TypeDef;                                  /*!< Size = 24 (0x18)                                                          */
219 
220 
221 /* =========================================================================================================================== */
222 /* ================                                           IWDG                                            ================ */
223 /* =========================================================================================================================== */
224 
225 
226 /**
227   * @brief Independent watchdog (IWDG)
228   */
229 
230 typedef struct                                  /*!< IWDG Structure                                                            */
231 {
232   __IO uint32_t  KR;                           /*!< (@ 0x00000000) Key register                                               */
233   __IO uint32_t  PR;                           /*!< (@ 0x00000004) Prescaler register                                         */
234   __IO uint32_t  RLR;                          /*!< (@ 0x00000008) Reload register                                            */
235   __IO uint32_t  SR;                           /*!< (@ 0x0000000C) Status register                                            */
236   __IO uint32_t  WINR;                         /*!< (@ 0x00000010) Window register                                            */
237 } IWDG_TypeDef;                                 /*!< Size = 20 (0x14)                                                          */
238 
239 
240 /* =========================================================================================================================== */
241 /* ================                                            I2C                                            ================ */
242 /* =========================================================================================================================== */
243 
244 
245 /**
246   * @brief Inter-integrated circuit (I2C)
247   */
248 
249 typedef struct                                  /*!< I2C Structure                                                             */
250 {
251   __IO uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
252   __IO uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
253   __IO uint32_t  OAR1;                         /*!< (@ 0x00000008) Own address register 1                                     */
254   __IO uint32_t  OAR2;                         /*!< (@ 0x0000000C) Own address register 2                                     */
255   __IO uint32_t  TIMINGR;                      /*!< (@ 0x00000010) Timing register                                            */
256   __IO uint32_t  TIMEOUTR;                     /*!< (@ 0x00000014) Status register 1                                          */
257   __IO uint32_t  ISR;                          /*!< (@ 0x00000018) Interrupt and Status register                              */
258   __IO uint32_t  ICR;                          /*!< (@ 0x0000001C) Interrupt clear register                                   */
259   __IO uint32_t  PECR;                         /*!< (@ 0x00000020) PEC register                                               */
260   __IO uint32_t  RXDR;                         /*!< (@ 0x00000024) Receive data register                                      */
261   __IO uint32_t  TXDR;                         /*!< (@ 0x00000028) Transmit data register                                     */
262 } I2C_TypeDef;                                  /*!< Size = 44 (0x2c)                                                          */
263 
264 
265 /* =========================================================================================================================== */
266 /* ================                                           FLASH                                           ================ */
267 /* =========================================================================================================================== */
268 
269 
270 /**
271   * @brief FLASH (FLASH)
272   */
273 
274 typedef struct                                  /*!< FLASH Structure                                                           */
275 {
276   __IO uint32_t  COMMAND;                      /*!< (@ 0x00000000) Command register                                           */
277   __IO uint32_t  CONFIG;                       /*!< (@ 0x00000004) Configuration register                                     */
278   __IO uint32_t  IRQSTAT;                      /*!< (@ 0x00000008) The interrupt status register shows the masked
279                                                                     version of the interrupt raw register.                     */
280   __IO uint32_t  IRQMASK;                      /*!< (@ 0x0000000C) The mask bit in IRQMASK will mask the condition
281                                                                     in the status register IRQSTAT and prevent
282                                                                     the generation of the interrupt.                           */
283   __IO uint32_t  IRQRAW;                       /*!< (@ 0x00000010) The raw status register shows the unmasked condition
284                                                                     of interrupt events.                                       */
285   __IO uint32_t  SIZE;                         /*!< (@ 0x00000014) SIZE register                                              */
286   __IO uint32_t  ADDRESS;                      /*!< (@ 0x00000018) Address register                                           */
287   __IO uint32_t  RESERVED[2];
288   __IO uint32_t  LFSRVAL;                      /*!< (@ 0x00000024) LFSRVAL register                                           */
289   __IO uint32_t  RESERVED2[3];
290   __IO uint32_t  PAGEPROT0;                    /*!< (@ 0x00000034) Main Flash page protection register 0                      */
291   __IO uint32_t  PAGEPROT1;                    /*!< (@ 0x00000038) Main Flash page protection register 1                      */
292   __IO uint32_t  RESERVED1;
293   __IO uint32_t  DATA0;                        /*!< (@ 0x00000040) Data register 0                                            */
294   __IO uint32_t  DATA1;                        /*!< (@ 0x00000044) Data register 1                                            */
295   __IO uint32_t  DATA2;                        /*!< (@ 0x00000048) Data register 2                                            */
296   __IO uint32_t  DATA3;                        /*!< (@ 0x0000004C) Data register 3                                            */
297 } FLASH_TypeDef;                                /*!< Size = 80 (0x50)                                                          */
298 
299 
300 /* =========================================================================================================================== */
301 /* ================                                            SPI                                            ================ */
302 /* =========================================================================================================================== */
303 
304 
305 /**
306   * @brief Serial peripheral interface/Inter-IC sound (SPI)
307   */
308 
309 typedef struct                                  /*!< SPI Structure                                                             */
310 {
311   __IO uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
312   __IO uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
313   __IO uint32_t  SR;                           /*!< (@ 0x00000008) Status register                                            */
314   __IO uint32_t  DR;                           /*!< (@ 0x0000000C) Data register                                              */
315   __IO uint32_t  CRCPR;                        /*!< (@ 0x00000010) CRC polynomial register                                    */
316   __IO uint32_t  RXCRCR;                       /*!< (@ 0x00000014) RX CRC register                                            */
317   __IO uint32_t  TXCRCR;                       /*!< (@ 0x00000018) TX CRC register                                            */
318   __IO uint32_t  I2SCFGR;                      /*!< (@ 0x0000001C) I2S configuration register                                 */
319   __IO uint32_t  I2SPR;                        /*!< (@ 0x00000020) I2S prescaler register                                     */
320 } SPI_TypeDef;                                  /*!< Size = 36 (0x24)                                                          */
321 
322 
323 /* =========================================================================================================================== */
324 /* ================                                            RCC                                            ================ */
325 /* =========================================================================================================================== */
326 
327 
328 /**
329   * @brief Reset and clock control (RCC)
330   */
331 
332 typedef struct                                  /*!< RCC Structure                                                             */
333 {
334   __IO uint32_t  CR;                           /*!< (@ 0x00000000) Clock control register                                     */
335   __IO uint32_t  ICSCR;                        /*!< (@ 0x00000004) Internal clock sources calibration register                */
336   __IO uint32_t  CFGR;                         /*!< (@ 0x00000008) Clock configuration register                               */
337   __IO uint32_t  CSSWCR;                       /*!< (@ 0x0000000C) Clocks Sources Software Calibration register               */
338   __IO uint32_t  RESERVED[2];
339   __IO uint32_t  CIER;                         /*!< (@ 0x00000018) Clock interrupt enable register                            */
340   __IO uint32_t  CIFR;                         /*!< (@ 0x0000001C) Clock interrupt flag register                              */
341   __IO uint32_t  CSCMDR;                       /*!< (@ 0x00000020) Clock Switch Command register                              */
342   __IO uint32_t  RESERVED1[3];
343   __IO uint32_t  AHBRSTR;                      /*!< (@ 0x00000030) AHB0 macro cells reset register                            */
344   __IO uint32_t  APB0RSTR;                     /*!< (@ 0x00000034) APB0 macro cells reset register                            */
345   __IO uint32_t  APB1RSTR;                     /*!< (@ 0x00000038) APB1 peripheral reset register 1                           */
346   __IO uint32_t  RESERVED2;
347   __IO uint32_t  APB2RSTR;                     /*!< (@ 0x00000040) APB2 peripheral reset register 2                           */
348   __IO uint32_t  RESERVED3[3];
349   __IO uint32_t  AHBENR;                       /*!< (@ 0x00000050) AHB0 macro cells clock enable register                     */
350   __IO uint32_t  APB0ENR;                      /*!< (@ 0x00000054) APB0 macro cells clock enable register                     */
351   __IO uint32_t  APB1ENR;                      /*!< (@ 0x00000058) APB1ENR1                                                   */
352   __IO uint32_t  RESERVED4;
353   __IO uint32_t  APB2ENR;                      /*!< (@ 0x00000060) APB2ENR                                                    */
354   __IO uint32_t  RESERVED5[12];
355   __IO uint32_t  CSR;                          /*!< (@ 0x00000094) CSR                                                        */
356   __IO uint32_t  RFSWHSECR;                    /*!< (@ 0x00000098) RF Software High Speed External register                   */
357   __IO uint32_t  RFHSECR;                      /*!< (@ 0x0000009C) RF High Speed External register                            */
358 } RCC_TypeDef;                                  /*!< Size = 160 (0xA0)                                                         */
359 
360 
361 /* =========================================================================================================================== */
362 /* ================                                            PWR                                            ================ */
363 /* =========================================================================================================================== */
364 
365 
366 /**
367   * @brief Power control (PWR)
368   */
369 
370 typedef struct                                  /*!< PWR Structure                                                             */
371 {
372   __IO uint32_t  CR1;                          /*!< (@ 0x00000000) Power control register 1                                   */
373   __IO uint32_t  CR2;                          /*!< (@ 0x00000004) Power control register 2                                   */
374   __IO uint32_t  CR3;                          /*!< (@ 0x00000008) Power control register 3                                   */
375   __IO uint32_t  CR4;                          /*!< (@ 0x0000000C) Power control register 4                                   */
376   __IO uint32_t  SR1;                          /*!< (@ 0x00000010) Power status register 1                                    */
377   __IO uint32_t  SR2;                          /*!< (@ 0x00000014) Power status register 2                                    */
378   __IO uint32_t  RESERVED;
379   __IO uint32_t  CR5;                          /*!< (@ 0x0000001C) Power control register 5                                   */
380   __IO uint32_t  PUCRA;                        /*!< (@ 0x00000020) Power Port A pull-up control register                      */
381   __IO uint32_t  PDCRA;                        /*!< (@ 0x00000024) Power Port A pull-down control register                    */
382   __IO uint32_t  PUCRB;                        /*!< (@ 0x00000028) Power Port B pull-up control register                      */
383   __IO uint32_t  PDCRB;                        /*!< (@ 0x0000002C) Power Port B pull-down control register                    */
384   __IO uint32_t  CR6;                          /*!< (@ 0x00000030) Power control register 6                                   */
385   __IO uint32_t  CR7;                          /*!< (@ 0x00000034) Power control register 7                                   */
386   __IO uint32_t  SR3;                          /*!< (@ 0x00000038) Power status register 3                                    */
387   __IO uint32_t  RESERVED1;
388   __IO uint32_t  IOxCFG;                       /*!< (@ 0x00000040) IO DEEPSTOP drive configuration register                   */
389   __IO uint32_t  RESERVED2[16];
390   __IO uint32_t  DBGR;                         /*!< (@ 0x00000084) Debug register                                             */
391   __IO uint32_t  EXTSRR;                       /*!< (@ 0x00000088) Power status clear register                                */
392   __IO uint32_t  DBGSMPS;                      /*!< (@ 0x0000008C) This register drives some control signals for
393                                                                     the SMPS                                                   */
394   __IO uint32_t  TRIMR;                        /*!< (@ 0x00000090) This register provides the trimming values applied
395                                                                     by hardware according to the trimmingdone
396                                                                     at EWS.                                                    */
397   __IO uint32_t  ENGTRIM;                      /*!< (@ 0x00000094) This register allows the software overloading
398                                                                     the hardware trimming flashed at EWS.                      */
399   __IO uint32_t  DBG1;                         /*!< (@ 0x00000098) This register shows the current states of the
400                                                                     FLASH FSM and SMPS FSM.                                    */
401   __IO uint32_t  DBG2;                         /*!< (@ 0x0000009C) This register shows the current states of the
402                                                                     FLASH FSM and SMPS FSM.                                    */
403 } PWR_TypeDef;                                  /*!< Size = 160 (0xA0)                                                         */
404 
405 
406 /* =========================================================================================================================== */
407 /* ================                                          SYSCFG                                           ================ */
408 /* =========================================================================================================================== */
409 
410 
411 /**
412   * @brief System configuration controller (SYSCFG)
413   */
414 
415 typedef struct                                  /*!< SYSCFG Structure                                                          */
416 {
417   __IO uint32_t  DIE_ID;                       /*!< (@ 0x00000000) This register provides the device version and
418                                                                     cut information.                                           */
419   __IO uint32_t  JTAG_ID;                      /*!< (@ 0x00000004) This register provides the JTAG ID of the stm32wb06.       */
420   __IO uint32_t  I2C_FMP_CTRL;                 /*!< (@ 0x00000008) This register allows activating the Fast-mode
421                                                                     Plus driving capability on I2C open-drain
422                                                                     pads.                                                      */
423   __IO uint32_t  IO_DTR;                       /*!< (@ 0x0000000C) IO_DTR                                                     */
424   __IO uint32_t  IO_IBER;                      /*!< (@ 0x00000010) IO_IBER                                                    */
425   __IO uint32_t  IO_IEVR;                      /*!< (@ 0x00000014) I/O Interrupt polarity event register                      */
426   __IO uint32_t  IO_IER;                       /*!< (@ 0x00000018) I/O Interrupt Enable register                              */
427   __IO uint32_t  IO_ISCR;                      /*!< (@ 0x0000001C) I/O Interrupt Status and Clear register                    */
428   __IO uint32_t  PWRC_IER;                     /*!< (@ 0x00000020) This register allows control of the enable or
429                                                                     mask on the interrupt sources of the Power
430                                                                     Controller (PWRC) block.                                   */
431   __IO uint32_t  PWRC_ISCR;                    /*!< (@ 0x00000024) Power Controller Interrupt Status and Clear register       */
432   __IO uint32_t  RESERVED;                     /*!< (@ 0x00000028)                                                            */
433   __IO uint32_t  BLERXTX_DTR;                  /*!< (@ 0x0000002C) MR_BLE RX or TX sequence information
434                                                                     detection type register                                    */
435   __IO uint32_t  BLERXTX_IBER;                 /*!< (@ 0x00000030) MR_BLE RX or TX sequence information
436                                                                     detection type register                                    */
437   __IO uint32_t  BLERXTX_IEVR;                 /*!< (@ 0x00000034) MR_BLE RX or TX sequence information
438                                                                     detection event register                                   */
439   __IO uint32_t  BLERXTX_IER;                  /*!< (@ 0x00000038) MR_BLE RX or TX Interrupt Enable Register                  */
440   __IO uint32_t  BLERXTX_ISCR;                 /*!< (@ 0x0000003C) MR_BLE RX or TX sequence information detection
441                                                                     status and clear register                                  */
442 } SYSCFG_TypeDef;                               /*!< Size = 64 (0x40)                                                          */
443 
444 
445 /* =========================================================================================================================== */
446 /* ================                                            RNG                                            ================ */
447 /* =========================================================================================================================== */
448 
449 
450 /**
451   * @brief Random number generator (RNG)
452   */
453 
454 typedef struct                                  /*!< RNG Structure                                                             */
455 {
456   __IO uint32_t  CR;                           /*!< (@ 0x00000000) Control register                                           */
457   __IO uint32_t  SR;                           /*!< (@ 0x00000004) Status register                                            */
458   __IO uint32_t  VAL;                          /*!< (@ 0x00000008) Data register                                              */
459 } RNG_TypeDef;                                  /*!< Size = 12 (0xC)                                                           */
460 
461 
462 /* =========================================================================================================================== */
463 /* ================                                           GPIO                                            ================ */
464 /* =========================================================================================================================== */
465 
466 
467 /**
468   * @brief General-purpose I/Os (GPIO)
469   */
470 
471 typedef struct                                  /*!< GPIO Structure                                                            */
472 {
473   __IO uint32_t  MODER;                        /*!< (@ 0x00000000) GPIO port mode register                                    */
474   __IO uint32_t  OTYPER;                       /*!< (@ 0x00000004) GPIO port output type register                             */
475   __IO uint32_t  OSPEEDR;                      /*!< (@ 0x00000008) GPIO port output speed register                            */
476   __IO uint32_t  PUPDR;                        /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register                       */
477   __IO uint32_t  IDR;                          /*!< (@ 0x00000010) GPIO port input data register                              */
478   __IO uint32_t  ODR;                          /*!< (@ 0x00000014) GPIO port output data register                             */
479   __IO uint32_t  BSRR;                         /*!< (@ 0x00000018) GPIO port bit set/reset register                           */
480   __IO uint32_t  LCKR;                         /*!< (@ 0x0000001C) GPIO port configuration lock register                      */
481   __IO uint32_t  AFR[2];                       /*!< (@ 0x00000020) GPIO alternate function register                           */
482   __IO uint32_t  BRR;                          /*!< (@ 0x00000028) GPIO bit reset register                                    */
483 } GPIO_TypeDef;                                 /*!< Size = 44 (0x2C)                                                          */
484 
485 
486 /* =========================================================================================================================== */
487 /* ================                                            TIM                                            ================ */
488 /* =========================================================================================================================== */
489 
490 
491 /**
492   * @brief Advanced-timers (TIM)
493   */
494 
495 typedef struct                                  /*!< TIM Structure                                                             */
496 {
497   __IO uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
498   __IO uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
499   __IO uint32_t  SMCR;                         /*!< (@ 0x00000008) Slave mode control register                                */
500   __IO uint32_t  DIER;                         /*!< (@ 0x0000000C) Interrupt enable register                              */
501   __IO uint32_t  SR;                           /*!< (@ 0x00000010) Status register                                            */
502   __IO uint32_t  EGR;                          /*!< (@ 0x00000014) Event generation register                                  */
503   __IO uint32_t  CCMR1;                        /*!< (@ 0x00000018) Input capture and output compare mode register 1           */
504   __IO uint32_t  CCMR2;                        /*!< (@ 0x0000001C) Input capture and output compare mode register 2           */
505   __IO uint32_t  CCER;                         /*!< (@ 0x00000020) Capture/compare enable register                            */
506   __IO uint32_t  CNT;                          /*!< (@ 0x00000024) Counter                                                    */
507   __IO uint32_t  PSC;                          /*!< (@ 0x00000028) Prescaler                                                  */
508   __IO uint32_t  ARR;                          /*!< (@ 0x0000002C) Auto-reload register                                       */
509   __IO uint32_t  RCR;                          /*!< (@ 0x00000030) Repetition counter register                                */
510   __IO uint32_t  CCR1;                         /*!< (@ 0x00000034) Capture/compare register 1                                 */
511   __IO uint32_t  CCR2;                         /*!< (@ 0x00000038) Capture/compare register 2                                 */
512   __IO uint32_t  CCR3;                         /*!< (@ 0x0000003C) Capture/compare register 3                                 */
513   __IO uint32_t  CCR4;                         /*!< (@ 0x00000040) Capture/compare register 4                                 */
514   __IO uint32_t  BDTR;                         /*!< (@ 0x00000044) Break and dead-time register                               */
515   __IO uint32_t  RESERVED[3];
516   __IO uint32_t  CCMR3;                        /*!< (@ 0x00000054) Output compare mode register 3                             */
517   __IO uint32_t  CCR5;                         /*!< (@ 0x00000058) Capture/compare register 4                                 */
518   __IO uint32_t  CCR6;                         /*!< (@ 0x0000005C) Capture/compare register 4                                 */
519   __IO uint32_t  AF1;                          /*!< (@ 0x00000060) TIM1 alternate function option register 1                  */
520   __IO uint32_t  AF2;                          /*!< (@ 0x00000064) TIM1 alternate function option register 2                  */
521 } TIM_TypeDef;                                  /*!< Size = 104 (0x68)                                                         */
522 
523 
524 /* =========================================================================================================================== */
525 /* ================                                           USART                                           ================ */
526 /* =========================================================================================================================== */
527 
528 
529 /**
530   * @brief Universal synchronous asynchronous receiver transmitter (USART)
531   */
532 
533 typedef struct                                  /*!< USART Structure                                                           */
534 {
535   __IO uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
536   __IO uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
537   __IO uint32_t  CR3;                          /*!< (@ 0x00000008) Control register 3                                         */
538   __IO uint32_t  BRR;                          /*!< (@ 0x0000000C) Baud rate register                                         */
539   __IO uint32_t  GTPR;                         /*!< (@ 0x00000010) Guard time and prescaler register                          */
540   __IO uint32_t  RTOR;                         /*!< (@ 0x00000014) Receiver timeout register                                  */
541   __IO uint32_t  RQR;                          /*!< (@ 0x00000018) Request register                                           */
542   __IO uint32_t  ISR;                          /*!< (@ 0x0000001C) Interrupt & status register                                */
543   __IO uint32_t  ICR;                          /*!< (@ 0x00000020) Interrupt flag clear register                              */
544   __IO uint32_t  RDR;                          /*!< (@ 0x00000024) Receive data register                                      */
545   __IO uint32_t  TDR;                          /*!< (@ 0x00000028) Transmit data register                                     */
546   __IO uint32_t  PRESC;                        /*!< (@ 0x0000002C) Prescaler register                                         */
547 } USART_TypeDef;                                /*!< Size = 48 (0x30)                                                          */
548 
549 
550 /* =========================================================================================================================== */
551 /* ================                                            RTC                                            ================ */
552 /* =========================================================================================================================== */
553 
554 
555 /**
556   * @brief Real-time clock (RTC)
557   */
558 
559 typedef struct                                  /*!< RTC Structure                                                             */
560 {
561   __IO uint32_t  TR;                           /*!< (@ 0x00000000) Time register                                              */
562   __IO uint32_t  DR;                           /*!< (@ 0x00000004) Date register                                              */
563   __IO uint32_t  CR;                           /*!< (@ 0x00000008) Control register                                           */
564   __IO uint32_t  ISR;                          /*!< (@ 0x0000000C) Initialization and status register                         */
565   __IO uint32_t  PRER;                         /*!< (@ 0x00000010) Prescaler register                                         */
566   __IO uint32_t  WUTR;                         /*!< (@ 0x00000014) Wakeup timer register                                      */
567   __IO uint32_t  RESERVED;
568   __IO uint32_t  ALRMAR;                       /*!< (@ 0x0000001C) Alarm A register                                           */
569   __IO uint32_t  RESERVED1;
570   __IO uint32_t  WPR;                          /*!< (@ 0x00000024) Write protection register                                  */
571   __IO uint32_t  SSR;                          /*!< (@ 0x00000028) Sub second register                                        */
572   __IO uint32_t  SHIFTR;                       /*!< (@ 0x0000002C) Shift control register                                     */
573   __IO uint32_t  RESERVED2[3];
574   __IO uint32_t  CALR;                         /*!< (@ 0x0000003C) Calibration register                                       */
575   __IO uint32_t  RESERVED3;
576   __IO uint32_t  ALRMASSR;                     /*!< (@ 0x00000044) Alarm A sub second register                                */
577   __IO uint32_t  RESERVED4[2];
578   __IO uint32_t  BKP0R;                        /*!< (@ 0x00000050) Backup register 0                                          */
579   __IO uint32_t  BKP1R;                        /*!< (@ 0x00000054) Backup register 1                                          */
580 } RTC_TypeDef;                                  /*!< Size = 88 (0x58)                                                          */
581 
582 
583 /* =========================================================================================================================== */
584 /* ================                                            PKA                                            ================ */
585 /* =========================================================================================================================== */
586 
587 
588 /**
589   * @brief PKA (PKA)
590   */
591 
592 typedef struct                                  /*!< PKA Structure                                                             */
593 {
594   __IO uint32_t  CSR;                          /*!< (@ 0x00000000) Command and status register                                */
595   __IO uint32_t  ISR;                          /*!< (@ 0x00000004) Interrupt register                                         */
596   __IO uint32_t  IEN;                          /*!< (@ 0x00000008) Interrupt enable register                                  */
597   uint32_t Reserved[253];                      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC         */
598   __IO uint32_t RAM[256];                       /*!< PKA RAM                           Address offset: 0x400 -> 0x07FF         */
599 } PKA_TypeDef;                                  /*!< Size = 12 (0x0C)                                                          */
600 
601 /* =====================================================   Bits definition for PKA RAM   ===================================================== */
602 #define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
603 
604 /* Compute ECC scalar multiplication input data */
605 #define PKA_ECC_SCALAR_MUL_IN_K                    ((0x046CU - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
606 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X      ((0x0490U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
607 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y      ((0x04B4U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
608 
609 /* Compute ECC scalar multiplication output data */
610 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X            ((0x0490U - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
611 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y            ((0x04B4U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
612 #define PKA_ECC_SCALAR_MUL_OUT_ERROR               ((0x0400U - PKA_RAM_OFFSET)>>2)   /*!< Output ERROR */
613 
614 
615 /* =========================================================================================================================== */
616 /* ================                                            ADC                                            ================ */
617 /* =========================================================================================================================== */
618 
619 
620 /**
621   * @brief ADC (ADC)
622   */
623 
624 typedef struct                                  /*!< ADC Structure                                                             */
625 {
626   __IO uint32_t  VERSION_ID;                   /*!< (@ 0x00000000) VERSION_ID register                                        */
627   __IO uint32_t  CONF;                         /*!< (@ 0x00000004) ADC configuration register                                 */
628   __IO uint32_t  CTRL;                         /*!< (@ 0x00000008) ADC control register                                       */
629   __IO uint32_t  OCM_CTRL;                     /*!< (@ 0x0000000C) Occasionnal mode control register                          */
630   __IO uint32_t  PGA_CONF;                     /*!< (@ 0x00000010) PGA configuration register                                 */
631   __IO uint32_t  SWITCH;                       /*!< (@ 0x00000014) ADC switch control for Input Selection                     */
632   __IO uint32_t  DF_CONF;                      /*!< (@ 0x00000018) Decimation filter configuration register                   */
633   __IO uint32_t  DS_CONF;                      /*!< (@ 0x0000001C) Downsampler configuration register                         */
634   __IO uint32_t  SEQ_1;                        /*!< (@ 0x00000020) ADC regular sequence configuration register 1              */
635   __IO uint32_t  SEQ_2;                        /*!< (@ 0x00000024) ADC regular sequence configuration register 2              */
636   __IO uint32_t  COMP_1;                       /*!< (@ 0x00000028) ADC Gain & offset correction values register 1             */
637   __IO uint32_t  COMP_2;                       /*!< (@ 0x0000002C) ADC Gain & offset correction values register 2             */
638   __IO uint32_t  COMP_3;                       /*!< (@ 0x00000030) ADC Gain & offset correction values register 3             */
639   __IO uint32_t  COMP_4;                       /*!< (@ 0x00000034) ADC Gain & offset correction values register 4             */
640   __IO uint32_t  COMP_SEL;                     /*!< (@ 0x00000038) ADC Gain & Offset selection values register                */
641   __IO uint32_t  WD_TH;                        /*!< (@ 0x0000003C) High/low limits for event monitoring a channel register    */
642   __IO uint32_t  WD_CONF;                      /*!< (@ 0x00000040) Channel selection for event monitoring register            */
643   __IO uint32_t  DS_DATAOUT;                   /*!< (@ 0x00000044) Downsampler Data output register                           */
644   __IO uint32_t  DF_DATAOUT;                   /*!< (@ 0x00000048) Decimation filter Data output register                     */
645   __IO uint32_t  IRQ_STATUS;                   /*!< (@ 0x0000004C) Interrupt Status register                                  */
646   __IO uint32_t  IRQ_ENABLE;                   /*!< (@ 0x00000050) Enable/disable Interrupts                                  */
647   __IO uint32_t  TIMER_CONF;                   /*!< (@ 0x00000054) Time to add after an LDO Enable or ADC Enable
648                                                                     to let the HW to be stable before using it                 */
649 } ADC_TypeDef;                                  /*!< Size = 88 (0x58)                                                          */
650 
651 
652 /* =========================================================================================================================== */
653 /* ================                                     AHBUPCONV                                             ================ */
654 /* =========================================================================================================================== */
655 
656 
657 /**
658   * @brief AHBUPCONV (AHBUPCONV)
659   */
660 
661 typedef struct                                  /*!< AHBUPCONV structure                                                       */
662 {
663   __IO uint32_t  COMMAND;                      /*!< (@ 0x00000000) Command register                                           */
664   __IO uint32_t  STATUS;                       /*!< (@ 0x00000004) Status register                                            */
665 } AHBUPCONV_TypeDef;                            /*!< Size = 8 (0x8)                                                            */
666 
667 
668 /* =========================================================================================================================== */
669 /* ================                                     BLUE                                                  ================ */
670 /* =========================================================================================================================== */
671 
672 
673 /**
674   * @brief BLUE Radio (BLUE)
675   */
676 
677 typedef struct                                  /*!< BLUE structure                                                            */
678 {
679   __IO uint32_t  CONTROLLERVERNUMREG;          /*!< (@ 0x00000000) Controller Version Number register                         */
680   __IO uint32_t  INTERRUPT1REG;                /*!< (@ 0x00000004) Interrupt1 register                                        */
681   __IO uint32_t  INTERRUPT2REG;                /*!< (@ 0x00000008) Interrupt2 register                                        */
682   __IO uint32_t  TIMEOUTDESTREG;               /*!< (@ 0x0000000C) TimeoutDest register                                       */
683   __IO uint32_t  TIMEOUTREG;                   /*!< (@ 0x00000010) Timeout register                                           */
684   __IO uint32_t  TIMERCAPTUREREG;              /*!< (@ 0x00000014) TimerCapture register                                      */
685   __IO uint32_t  CMDREG;                       /*!< (@ 0x00000018) Cmd register                                               */
686   __IO uint32_t  STATUSREG;                    /*!< (@ 0x0000001C) Status register                                            */
687   __IO uint32_t  INTERRUPT1ENABLEREG;          /*!< (@ 0x00000020) Interrupt1Enable register                                  */
688   __IO uint32_t  INTERRUPT1LATENCYREG;         /*!< (@ 0x00000024) Interrupt1Latency register                                 */
689   __IO uint32_t  MANAESKEY0REG;                /*!< (@ 0x00000028) ManAesKey0 register                                        */
690   __IO uint32_t  MANAESKEY1REG;                /*!< (@ 0x0000002C) ManAesKey1 register                                        */
691   __IO uint32_t  MANAESKEY2REG;                /*!< (@ 0x00000030) ManAesKey2 register                                        */
692   __IO uint32_t  MANAESKEY3REG;                /*!< (@ 0x00000034) ManAesKey3 register                                        */
693   __IO uint32_t  MANAESCLEARTEXT0REG;          /*!< (@ 0x00000038) ManAesClearText0 register                                  */
694   __IO uint32_t  MANAESCLEARTEXT1REG;          /*!< (@ 0x0000003C) ManAesClearText1 register                                  */
695   __IO uint32_t  MANAESCLEARTEXT2REG;          /*!< (@ 0x00000040) ManAesClearText2 register                                  */
696   __IO uint32_t  MANAESCLEARTEXT3REG;          /*!< (@ 0x00000044) ManAesClearText3 register                                  */
697   __IO uint32_t  MANAESCIPHERTEXT0REG;         /*!< (@ 0x00000048) ManAESCipherText0 register                                 */
698   __IO uint32_t  MANAESCIPHERTEXT1REG;         /*!< (@ 0x0000004C) ManAESCipherText1 register                                 */
699   __IO uint32_t  MANAESCIPHERTEXT2REG;         /*!< (@ 0x00000050) ManAESCipherText2 register                                 */
700   __IO uint32_t  MANAESCIPHERTEXT3REG;         /*!< (@ 0x00000054) ManAESCipherText3 register                                 */
701   __IO uint32_t  MANAESCMDREG;                 /*!< (@ 0x00000058) ManAESCmd register                                         */
702   __IO uint32_t  MANAESSTATREG;                /*!< (@ 0x0000005C) ManAESStat register                                        */
703   __IO uint32_t  AESLEPRIVPOINTERREG;          /*!< (@ 0x00000060) AesLePrivPointer register                                  */
704   __IO uint32_t  AESLEPRIVHASHREG;             /*!< (@ 0x00000064) AesLePrivHash register                                     */
705   __IO uint32_t  AESLEPRIVPRANDREG;            /*!< (@ 0x00000068) AesLePrivPrand register                                    */
706   __IO uint32_t  AESLEPRIVCMDREG;              /*!< (@ 0x0000006C) AesLePrivCmd register                                      */
707   __IO uint32_t  AESLEPRIVSTATREG;             /*!< (@ 0x00000070) AesLePrivStat register                                     */
708   __IO uint32_t  DEBUGCMDREG;                  /*!< (@ 0x00000074) DebugCmd register                                          */
709   __IO uint32_t  DEBUGSTATUSREG;               /*!< (@ 0x00000078) DebugStatus register                                       */
710   __IO uint32_t  RESERVED;
711 } BLUE_TypeDef;                                 /*!< Size = 128 (0x80)                                                         */
712 
713 
714 /* =========================================================================================================================== */
715 /* ================                                     RADIO_CTRL                                            ================ */
716 /* =========================================================================================================================== */
717 
718 
719 /**
720   * @brief Radio Controller (RADIO_CTRL)
721   */
722 
723 typedef struct                                  /*!< Radio Control structure                                                   */
724 {
725   __IO uint32_t  RADIO_CONTROL_ID;            /*!< (@ 0x00000000) Radio Controller ID register                               */
726   __IO uint32_t  CLK32COUNT_REG;              /*!< (@ 0x00000004) Window length register                                     */
727   __IO uint32_t  CLK32PERIOD_REG;             /*!< (@ 0x00000008) Slow clock period register                                 */
728   __IO uint32_t CLK32FREQUENCY_REG;          /*!< (@ 0x0000000C) Slow clock frequency register                              */
729   __IO uint32_t  RADIO_CONTROL_IRQ_STATUS;    /*!< (@ 0x00000010) Radio Controller Interrupt Status register                 */
730   __IO uint32_t  RADIO_CONTROL_IRQ_ENABLE;    /*!< (@ 0x00000014) Radio Controller Interrupt Control register                */
731   __IO uint32_t  RESERVED;
732 } RADIO_CTRL_TypeDef;                           /*!< Size = 28 (0x1C)                                                          */
733 
734 
735 /* =========================================================================================================================== */
736 /* ================                                     RRM                                                   ================ */
737 /* =========================================================================================================================== */
738 
739 
740 /**
741   * @brief RRM (RRM)
742  */
743 
744 typedef struct                                  /*!<  RRM structure                                                            */
745 {
746   __IO uint32_t  RRM_ID;             /*!<  (@ 0x00) RRM_ID register                                                 */
747   __IO uint32_t  RRM_CTRL;           /*!<  (@ 0x04) RRM_CTRL register                                               */
748   __IO uint32_t  RESERVED[2];
749   __IO uint32_t  UDRA_CTRL0;         /*!<  (@ 0x10) UDRA_CTRL0 register                                             */
750   __IO uint32_t  UDRA_IRQ_ENABLE;    /*!<  (@ 0x14) UDRA_IRQ_ENABLE register                                        */
751   __IO uint32_t  UDRA_IRQ_STATUS;    /*!<  (@ 0x18) UDRA_IRQ_STATUS register                                        */
752   __IO uint32_t  UDRA_RADIO_CFG_PTR; /*!<  (@ 0x1C) UDRA_RADIO_CFG_PTR register                                     */
753   __IO uint32_t  SEMA_IRQ_ENABLE;    /*!<  (@ 0x20) SEMA_IRQ_ENABLE register                                        */
754   __IO uint32_t  SEMA_IRQ_STATUS;    /*!<  (@ 0x24) SEMA_IRQ_STATUS register                                        */
755   __IO uint32_t  BLE_IRQ_ENABLE;     /*!<  (@ 0x28) BLE_IRQ_ENABLE register                                         */
756   __IO uint32_t  BLE_IRQ_STATUS;     /*!<  (@ 0x2C) BLE_IRQ_STATUS register                                         */
757   __IO uint32_t  RESERVED1[12];
758   __IO uint32_t  VP_CPU_CMD_BUS;     /*!<  (@ 0x60) VP_CPU_CMD_BUS register                                         */
759   __IO uint32_t  VP_CPU_SEMA_BUS;    /*!<  (@ 0x64) VP_CPU_SEMA_BUS register                                        */
760   __IO uint32_t  VP_CPU_IRQ_ENABLE;  /*!<  (@ 0x68) VP_CPU_IRQ_ENABLE register                                      */
761   __IO uint32_t  VP_CPU_IRQ_STATUS;  /*!<  (@ 0x6C) VP_CPU_IRQ_STATUS register                                      */
762   __IO uint32_t  RESERVED2[36];
763   __IO uint32_t  AA0_DIG_USR;        /*!<  (@ 0x100+0x00) AA0_DIG_USR register                                      */
764   __IO uint32_t  AA1_DIG_USR;        /*!<  (@ 0x100+0x04) AA1_DIG_USR register                                      */
765   __IO uint32_t  AA2_DIG_USR;        /*!<  (@ 0x100+0x08) AA2_DIG_USR register                                      */
766   __IO uint32_t  AA3_DIG_USR;        /*!<  (@ 0x100+0x0C) AA3_DIG_USR register                                      */
767   __IO uint32_t  DEM_MOD_DIG_USR;    /*!<  (@ 0x100+0x10) DEM_MOD_DIG_USR register                                  */
768   __IO uint32_t  RADIO_FSM_USR;      /*!<  (@ 0x100+0x14) RADIO_FSM_USR register                                    */
769   __IO uint32_t  PHYCTRL_DIG_USR;    /*!<  (@ 0x100+0x18) PHYCTRL_DIG_USR register                                  */
770   __IO uint32_t  RESERVED3[10];
771   __IO uint32_t  AFC0_DIG_ENG;      /*!<  (@ 0x100+0x44) AFC0_DIG_ENG register                                     */
772   __IO uint32_t  AFC1_DIG_ENG;      /*!<  (@ 0x100+0x48) AFC1_DIG_ENG register                                     */
773   __IO uint32_t  AFC2_DIG_ENG;      /*!<  (@ 0x100+0x4C) AFC2_DIG_ENG register                                     */
774   __IO uint32_t  AFC3_DIG_ENG;      /*!<  (@ 0x100+0x50) AFC3_DIG_ENG register                                     */
775   __IO uint32_t  CR0_DIG_ENG;            /*!<  (@ 0x100+0x54) CR0_DIG_ENG register                                      */
776   __IO uint32_t  RESERVED4[4];
777   __IO uint32_t  CR0_LR;            /*!<  (@ 0x100+0x68) CR0_LR register                                           */
778   __IO uint32_t  VIT_CONF_DIG_ENG;  /*!<  (@ 0x100+0x6C) VIT_CONF_DIG_ENG register                                 */
779   __IO uint32_t  RESERVED5[5];
780   __IO uint32_t  LR_PD_THR_DIG_ENG;      /*!<  (@ 0x100+0x84) LR_PD_THR_DIG_ENG register                                */
781   __IO uint32_t  LR_RSSI_THR_DIG_ENG;    /*!<  (@ 0x100+0x88) LR_RSSI_THR_DIG_ENG register                              */
782   __IO uint32_t  LR_AAC_THR_DIG_ENG;     /*!<  (@ 0x100+0x8C) LR_AAC_THR_DIG_ENG register                               */
783   __IO uint32_t  RESERVED6[19];
784   __IO uint32_t  DTB0_DIG_ENG;      /*!<  (@ 0x100+0xDC) DTB0_DIG_ENG register                                     */
785   __IO uint32_t  RESERVED7[4];
786   __IO uint32_t  DTB5_DIG_ENG;      /*!<  (@ 0x100+0xF0) DTB5_DIG_ENG register                                     */
787   __IO uint32_t  RESERVED8[16];
788   __IO uint32_t  MOD0_DIG_TST;      /*!<  (@ 0x100+0x134) MOD0_DIG_TST register                                    */
789   __IO uint32_t  MOD1_DIG_TST;      /*!<  (@ 0x100+0x138) MOD1_DIG_TST register                                    */
790   __IO uint32_t  MOD2_DIG_TST;      /*!<  (@ 0x100+0x13C) MOD2_DIG_TST register                                    */
791   __IO uint32_t  MOD3_DIG_TST;      /*!<  (@ 0x100+0x140) MOD3_DIG_TST register                                    */
792   __IO uint32_t  RESERVED9;
793   __IO uint32_t  RXADC_ANA_USR;     /*!<  (@ 0x100+0x148) RXADC_ANA_USR register                                   */
794   __IO uint32_t  RESERVED10[2];
795   __IO uint32_t  LDO_ANA_ENG;            /*!<  (@ 0x100+0x154) LDO_ANA_ENG register                                     */
796   __IO uint32_t  RESERVED11[7];
797   __IO uint32_t  CBIAS0_ANA_ENG;    /*!<  (@ 0x100+0x174) CBIAS0_ANA_ENG register                                  */
798   __IO uint32_t  CBIAS1_ANA_ENG;    /*!<  (@ 0x100+0x178) CBIAS1_ANA_ENG register                                  */
799   __IO uint32_t  CBIAS_ANA_TEST;    /*!<  (@ 0x100+0x17C) CBIAS_ANA_TEST register                                  */
800   __IO uint32_t  SYNTHCAL0_DIG_OUT; /*!<  (@ 0x100+0x180) SYNTHCAL0_DIG_OUT register                               */
801   __IO uint32_t  SYNTHCAL1_DIG_OUT; /*!<  (@ 0x100+0x184) SYNTHCAL1_DIG_OUT register                               */
802   __IO uint32_t  SYNTHCAL2_DIG_OUT; /*!<  (@ 0x100+0x188) SYNTHCAL2_DIG_OUT register                               */
803   __IO uint32_t  SYNTHCAL3_DIG_OUT; /*!<  (@ 0x100+0x18C) SYNTHCAL3_DIG_OUT register                               */
804   __IO uint32_t  SYNTHCAL4_DIG_OUT; /*!<  (@ 0x100+0x190) SYNTHCAL4_DIG_OUT register                               */
805   __IO uint32_t  SYNTHCAL5_DIG_OUT; /*!<  (@ 0x100+0x194) SYNTHCAL5_DIG_OUT register                               */
806   __IO uint32_t  FSM_STATUS_DIG_OUT;/*!<  (@ 0x100+0x198) FSM_STATUS_DIG_OUT register                              */
807   __IO uint32_t  IRQ_STATUS_DIG_OUT;/*!<  (@ 0x100+0x19C) IRQ_STATUS_DIG_OUT register                              */
808   __IO uint32_t  RESERVED12;
809   __IO uint32_t  RSSI0_DIG_OUT;     /*!<  (@ 0x100+0x1A4) RSSI0_DIG_OUT register                                   */
810   __IO uint32_t  RSSI1_DIG_OUT;     /*!<  (@ 0x100+0x1A8) RSSI1_DIG_OUT register                                   */
811   __IO uint32_t  AGC_DIG_OUT;       /*!<  (@ 0x100+0x1AC) AGC_DIG_OUT register                                     */
812   __IO uint32_t  DEMOD_DIG_OUT;     /*!<  (@ 0x100+0x1B0) DEMOD_DIG_OUT register                                   */
813   __IO uint32_t  AGC0_ANA_TST;      /*!<  (@ 0x100+0x1B4) AGC0_ANA_TST register                                    */
814   __IO uint32_t  AGC1_ANA_TST;      /*!<  (@ 0x100+0x1B8) AGC1_ANA_TST register                                    */
815   __IO uint32_t  AGC2_ANA_TST;      /*!<  (@ 0x100+0x1BC) AGC2_ANA_TST register                                    */
816   __IO uint32_t  AGC0_DIG_ENG;      /*!<  (@ 0x100+0x1C0) AGC0_DIG_ENG register                                    */
817   __IO uint32_t  AGC1_DIG_ENG;      /*!<  (@ 0x100+0x1C4) AGC1_DIG_ENG register                                    */
818   __IO uint32_t  AGC2_DIG_ENG;      /*!<  (@ 0x100+0x1C8) AGC2_DIG_ENG register                                    */
819   __IO uint32_t  AGC3_DIG_ENG;      /*!<  (@ 0x100+0x1CC) AGC3_DIG_ENG register                                    */
820   __IO uint32_t  AGC4_DIG_ENG;      /*!<  (@ 0x100+0x1D0) AGC4_DIG_ENG register                                    */
821   __IO uint32_t  AGC5_DIG_ENG;      /*!<  (@ 0x100+0x1D4) AGC5_DIG_ENG register                                    */
822   __IO uint32_t  AGC6_DIG_ENG;      /*!<  (@ 0x100+0x1D8) AGC6_DIG_ENG register                                    */
823   __IO uint32_t  AGC7_DIG_ENG;      /*!<  (@ 0x100+0x1DC) AGC7_DIG_ENG register                                    */
824   __IO uint32_t  AGC8_DIG_ENG;      /*!<  (@ 0x100+0x1E0) AGC8_DIG_ENG register                                    */
825   __IO uint32_t  AGC9_DIG_ENG;      /*!<  (@ 0x100+0x1E4) AGC9_DIG_ENG register                                    */
826   __IO uint32_t  AGC10_DIG_ENG;     /*!<  (@ 0x100+0x1E8) AGC10_DIG_ENG register                                   */
827   __IO uint32_t  AGC11_DIG_ENG;     /*!<  (@ 0x100+0x1EC) AGC11_DIG_ENG register                                   */
828   __IO uint32_t  AGC12_DIG_ENG;     /*!<  (@ 0x100+0x1F0) AGC12_DIG_ENG register                                   */
829   __IO uint32_t  AGC13_DIG_ENG;     /*!<  (@ 0x100+0x1F4) AGC13_DIG_ENG register                                   */
830   __IO uint32_t  AGC14_DIG_ENG;     /*!<  (@ 0x100+0x1F8) AGC14_DIG_ENG register                                   */
831   __IO uint32_t  AGC15_DIG_ENG;     /*!<  (@ 0x100+0x1FC) AGC15_DIG_ENG register                                   */
832   __IO uint32_t  AGC16_DIG_ENG;     /*!<  (@ 0x100+0x200) AGC16_DIG_ENG register                                   */
833   __IO uint32_t  AGC17_DIG_ENG;     /*!<  (@ 0x100+0x204) AGC17_DIG_ENG register                                   */
834   __IO uint32_t  AGC18_DIG_ENG;     /*!<  (@ 0x100+0x208) AGC18_DIG_ENG register                                   */
835   __IO uint32_t  AGC19_DIG_ENG;     /*!<  (@ 0x100+0x20C) AGC19_DIG_ENG register                                   */
836   __IO uint32_t  AGC20_DIG_ENG;     /*!<  (@ 0x100+0x210) AGC20_DIG_ENG register                                   */
837   __IO uint32_t  RESERVED13[4];
838   __IO uint32_t  RXADC_HW_TRIM_OUT; /*!<  (@ 0x100+0x224) RXADC_HW_TRIM_OUT register                               */
839   __IO uint32_t  CBIAS0_HW_TRIM_OUT; /*!<  (@ 0x100+0x228) CBIAS0_HW_TRIM_OUT register                              */
840   __IO uint32_t  CBIAS1_HW_TRIM_OUT; /*!<  (@ 0x100+0x22C) CBIAS1_HW_TRIM_OUT register                              */
841   __IO uint32_t  AGC_HW_TRIM_OUT;   /*!<  (@ 0x100+0x230) AGC_HW_TRIM_OUT register                                 */
842   __IO uint32_t  RESERVED14;
843 } RRM_TypeDef;                                  /*!< Size = 824 (0x338)                                                        */
844 
845 
846 /* =========================================================================================================================== */
847 /* ================                                     WAKEUP                                                ================ */
848 /* =========================================================================================================================== */
849 
850 
851 /**
852   * @brief Wakeup (WAKEUP)
853   */
854 
855 typedef struct                                  /*!< Wakeup structure                                                          */
856 {
857   __IO uint32_t  WAKEUP_BLOCK_VERSION;        /*!< (@ 0x00000000) Wakeup block version register                              */
858   __IO uint32_t  RESERVED;
859   __IO uint32_t  WAKEUP_OFFSET[2];            /*!< (@ 0x00000008) Wakeup offset_x register                                   */
860   __IO uint32_t  ABSOLUTE_TIME;               /*!< (@ 0x00000010) Absolute time register                                     */
861   __IO uint32_t  MINIMUM_PERIOD_LENGTH;       /*!< (@ 0x00000014) Minimum period length register                             */
862   __IO uint32_t  AVERAGE_PERIOD_LENGTH;       /*!< (@ 0x00000018) Average period length register                             */
863   __IO uint32_t  MAXIMUM_PERIOD_LENGTH;       /*!< (@ 0x0000001C) Maximum period length register                             */
864   __IO uint32_t  STATISTICS_RESTART;          /*!< (@ 0x00000020) Statistics restart register                                */
865   __IO uint32_t  BLUE_WAKEUP_TIME;            /*!< (@ 0x00000024) BLE wakeup time register                                   */
866   __IO uint32_t  BLUE_SLEEP_REQUEST_MODE;     /*!< (@ 0x00000028) BLE sleep request mode register                            */
867   __IO uint32_t  CM0_WAKEUP_TIME;             /*!< (@ 0x0000002C) CPU wakeup time register                                   */
868   __IO uint32_t  CM0_SLEEP_REQUEST_MODE;      /*!< (@ 0x00000030) CPU sleep request mode register                            */
869   __IO uint32_t  RESERVED1[3];
870   __IO uint32_t  WAKEUP_BLE_IRQ_ENABLE;       /*!< (@ 0x00000040) Wakeup BLE interrupt enable register                       */
871   __IO uint32_t  WAKEUP_BLE_IRQ_STATUS;       /*!< (@ 0x00000044) Wakeup BLE interrupt status register                       */
872   __IO uint32_t  WAKEUP_CM0_IRQ_ENABLE;       /*!< (@ 0x00000048) Wakeup CPU interrupt enable register                       */
873   __IO uint32_t  WAKEUP_CM0_IRQ_STATUS;       /*!< (@ 0x0000004C) Wakeup CPU interrupt status register                       */
874   __IO uint32_t  RESERVED2;
875 } WAKEUP_TypeDef;                               /*!< Size = 84 (0x54)                                                          */
876 
877 
878 /** @} */ /* End of group Device_Peripheral_peripherals */
879 
880 
881 /* =========================================================================================================================== */
882 /* ================                          Device Specific Peripheral Address Map                           ================ */
883 /* =========================================================================================================================== */
884 
885 
886 /** @addtogroup Device_Peripheral_peripheralAddr
887   * @{
888   */
889 #define NVM_BASE               (0x10040000U) /*!< Main FLASH base address */
890 #define SRAM_BASE              (0x20000000U) /*!< SRAM base address */
891 #define PERIPH_BASE            (0x40000000U) /*!< Peripheral base address */
892 
893 
894 /*!< Memory, OTP bytes */
895 
896 /* Base addresses */
897 #define SYSTEM_MEMORY_BASE     (0x10000000U)   /*!< System Memory : 6KB (0x10000000 – 0x100017FF)  */
898 #define OTP_AREA_BASE          (0x10001800U)   /*!< OTP area : 1kB (0x10001800 – 0x10001BFF)       */
899 
900 #define SRAM0_BASE             SRAM_BASE                 /*!< SRAM0 (16 KB) base address */
901 #define SRAM1_BASE            (SRAM_BASE + 0x00004000U)  /*!< SRAM1 (16 KB) base address       */
902 #define SRAM2_BASE            (SRAM_BASE + 0x00008000U)  /*!< SRAM2 (16 KB) base address       */
903 #define SRAM3_BASE            (SRAM_BASE + 0x0000C000U)  /*!< SRAM3 (16 KB) base address       */
904 
905 /* End addresses */
906 #define SRAM0_END_ADDR         (0x20003FFFU)   /*!< RAM0  : 16KB (0x20000000 – 0x20003FFF)         */
907 #define SRAM1_END_ADDR         (0x20007FFFU)   /*!< RAM1  : 16KB (0x20000000 – 0x20007FFF)         */
908 #define SRAM2_END_ADDR         (0x2000BFFFU)   /*!< RAM2  : 16KB (0x20000000 – 0x2000BFFF)         */
909 #define SRAM3_END_ADDR         (0x2000FFFFU)   /*!< RAM3  : 16KB (0x20000000 – 0x2000FFFF)         */
910 
911 #define SYSTEM_MEMORY_END_ADDR (0x100017FFU)   /*!< System Memory : 6KB (0x10000000 – 0x100017FF)   */
912 #define OTP_AREA_END_ADDR      (0x10001BFFU)   /*!< OTP area : 1KB (0x10001800 – 0x10001BFF)        */
913 
914 /*!< Peripheral memory map */
915 #define APB0PERIPH_BASE        PERIPH_BASE
916 #define APB1PERIPH_BASE       (PERIPH_BASE + 0x01000000U)
917 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x08000000U)
918 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x20000000U)
919 
920 
921 /*!< APB0 peripherals */
922 #define SYSCFG_BASE        (APB0PERIPH_BASE + 0x0000U)
923 #define FLASH_BASE         (APB0PERIPH_BASE + 0x1000U)
924 #define TIM1_BASE          (APB0PERIPH_BASE + 0x2000U)
925 #define IWDG_BASE          (APB0PERIPH_BASE + 0x3000U)
926 #define RTC_BASE           (APB0PERIPH_BASE + 0x4000U)
927 #define AHBUPCONV_BASE     (APB0PERIPH_BASE + 0x5000U)
928 
929 /*!< APB1 peripherals */
930 #define I2C1_BASE          (APB1PERIPH_BASE + 0x0000U)
931 #define I2C2_BASE          (APB1PERIPH_BASE + 0x1000U)
932 #define SPI1_BASE          (APB1PERIPH_BASE + 0x2000U)
933 #define SPI2_BASE          (APB1PERIPH_BASE + 0x3000U)
934 #define USART1_BASE        (APB1PERIPH_BASE + 0x4000U)
935 #define LPUART1_BASE       (APB1PERIPH_BASE + 0x5000U)
936 #define ADC1_BASE          (APB1PERIPH_BASE + 0x6000U)
937 #define SPI3_BASE          (APB1PERIPH_BASE + 0x7000U)
938 
939 /*!< AHB peripherals */
940 #define GPIOA_BASE                 (AHBPERIPH_BASE + 0x000000UL)
941 #define GPIOB_BASE                 (AHBPERIPH_BASE + 0x100000UL)
942 #define CRC_BASE                   (AHBPERIPH_BASE + 0x200000UL)
943 #define PKA_BASE                   (AHBPERIPH_BASE + 0x300000UL)
944 #define PKA_RAM_BASE               (AHBPERIPH_BASE + 0x300400UL)
945 #define RCC_BASE                   (AHBPERIPH_BASE + 0x400000UL)
946 #define PWR_BASE                   (AHBPERIPH_BASE + 0x500000UL)
947 #define RNG_BASE                   (AHBPERIPH_BASE + 0x600000UL)
948 #define DMA1_BASE                  (AHBPERIPH_BASE + 0x700000UL)
949 #define DMAMUX1_BASE               (AHBPERIPH_BASE + 0x800000UL)
950 
951 #define DMA1_Channel1_BASE         (DMA1_BASE + 0x0008)
952 #define DMA1_Channel2_BASE         (DMA1_BASE + 0x001C)
953 #define DMA1_Channel3_BASE         (DMA1_BASE + 0x0030)
954 #define DMA1_Channel4_BASE         (DMA1_BASE + 0x0044)
955 #define DMA1_Channel5_BASE         (DMA1_BASE + 0x0058)
956 #define DMA1_Channel6_BASE         (DMA1_BASE + 0x006C)
957 #define DMA1_Channel7_BASE         (DMA1_BASE + 0x0080)
958 #define DMA1_Channel8_BASE         (DMA1_BASE + 0x0094)
959 
960 #define DMAMUX1_Channel0_BASE      (DMAMUX1_BASE)
961 #define DMAMUX1_Channel1_BASE      (DMAMUX1_BASE + 0x00000004)
962 #define DMAMUX1_Channel2_BASE      (DMAMUX1_BASE + 0x00000008)
963 #define DMAMUX1_Channel3_BASE      (DMAMUX1_BASE + 0x0000000C)
964 #define DMAMUX1_Channel4_BASE      (DMAMUX1_BASE + 0x00000010)
965 #define DMAMUX1_Channel5_BASE      (DMAMUX1_BASE + 0x00000014)
966 #define DMAMUX1_Channel6_BASE      (DMAMUX1_BASE + 0x00000018)
967 #define DMAMUX1_Channel7_BASE      (DMAMUX1_BASE + 0x0000001C)
968 
969 /*!< APB2 peripherals */
970 #define BLUE_BASE                  (APB2PERIPH_BASE + 0x0000U)
971 #define RADIO_CTRL_BASE            (APB2PERIPH_BASE + 0x1000U)
972 #define RRM_BASE                   (APB2PERIPH_BASE + 0x1400U)
973 #define WAKEUP_BASE                (APB2PERIPH_BASE + 0x1800U)
974 
975 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
976 
977 
978 /* =========================================================================================================================== */
979 /* ================                                  Peripheral declaration                                   ================ */
980 /* =========================================================================================================================== */
981 
982 
983 /** @addtogroup Device_Peripheral_declaration
984   * @{
985   */
986 
987 
988 /* Peripherals available on APB0 bus */
989 #define SYSCFG                      ((SYSCFG_TypeDef*)           SYSCFG_BASE)
990 #define FLASH                       ((FLASH_TypeDef*)             FLASH_BASE)
991 #define TIM1                        ((TIM_TypeDef*)               TIM1_BASE)
992 #define IWDG                        ((IWDG_TypeDef*)               IWDG_BASE)
993 #define RTC                         ((RTC_TypeDef*)                 RTC_BASE)
994 #define AHBUPCONV                   ((AHBUPCONV_TypeDef*)     AHBUPCONV_BASE)
995 
996 /* Peripherals available on APB1 bus */
997 #define I2C1                        ((I2C_TypeDef*)                I2C1_BASE)
998 #define I2C2                        ((I2C_TypeDef*)                I2C2_BASE)
999 #define SPI1                        ((SPI_TypeDef*)                SPI1_BASE)
1000 #define SPI2                        ((SPI_TypeDef*)                SPI2_BASE)
1001 #define USART1                      ((USART_TypeDef*)            USART1_BASE)
1002 #define LPUART1                     ((USART_TypeDef*)           LPUART1_BASE)
1003 #define ADC1                        ((ADC_TypeDef*)                ADC1_BASE)
1004 #define SPI3                        ((SPI_TypeDef*)                SPI3_BASE)
1005 
1006 /* Peripherals available on AHB bus */
1007 #define GPIOA                       ((GPIO_TypeDef*)                                  GPIOA_BASE)
1008 #define GPIOB                       ((GPIO_TypeDef*)                                  GPIOB_BASE)
1009 #define CRC                         ((CRC_TypeDef*)                                     CRC_BASE)
1010 #define PKA                         ((PKA_TypeDef*)                                     PKA_BASE)
1011 #define RCC                         ((RCC_TypeDef*)                                     RCC_BASE)
1012 #define PWR                         ((PWR_TypeDef*)                                     PWR_BASE)
1013 #define RNG                         ((RNG_TypeDef*)                                     RNG_BASE)
1014 #define DMA1                        ((DMA_TypeDef*)                                    DMA1_BASE)
1015 #define DMA1_Channel1               ((DMA_Channel_TypeDef *)                  DMA1_Channel1_BASE)
1016 #define DMA1_Channel2               ((DMA_Channel_TypeDef *)                  DMA1_Channel2_BASE)
1017 #define DMA1_Channel3               ((DMA_Channel_TypeDef *)                  DMA1_Channel3_BASE)
1018 #define DMA1_Channel4               ((DMA_Channel_TypeDef *)                  DMA1_Channel4_BASE)
1019 #define DMA1_Channel5               ((DMA_Channel_TypeDef *)                  DMA1_Channel5_BASE)
1020 #define DMA1_Channel6               ((DMA_Channel_TypeDef *)                  DMA1_Channel6_BASE)
1021 #define DMA1_Channel7               ((DMA_Channel_TypeDef *)                  DMA1_Channel7_BASE)
1022 #define DMA1_Channel8               ((DMA_Channel_TypeDef *)                  DMA1_Channel8_BASE)
1023 #define DMAMUX1                     ((DMAMUX_Channel_TypeDef *)                     DMAMUX1_BASE)
1024 #define DMAMUX1_Channel0            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel0_BASE)
1025 #define DMAMUX1_Channel1            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel1_BASE)
1026 #define DMAMUX1_Channel2            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel2_BASE)
1027 #define DMAMUX1_Channel3            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel3_BASE)
1028 #define DMAMUX1_Channel4            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel4_BASE)
1029 #define DMAMUX1_Channel5            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel5_BASE)
1030 #define DMAMUX1_Channel6            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel6_BASE)
1031 #define DMAMUX1_Channel7            ((DMAMUX_Channel_TypeDef *)            DMAMUX1_Channel7_BASE)
1032 
1033 /* Peripherals available on APB2 bus */
1034 #define BLUE                        ((BLUE_TypeDef*)                BLUE_BASE)
1035 #define RADIO                       (BLUE)
1036 #define RADIO_CTRL                  ((RADIO_CTRL_TypeDef*)    RADIO_CTRL_BASE)
1037 #define RRM                         ((RRM_TypeDef*)                  RRM_BASE)
1038 #define WAKEUP                      ((WAKEUP_TypeDef*)            WAKEUP_BASE)
1039 
1040 /** @} */ /* End of group Device_Peripheral_declaration */
1041 
1042 /* =========================================  End of section using anonymous unions  ========================================= */
1043 #if defined (__CC_ARM)
1044 #pragma pop
1045 #elif defined (__ICCARM__)
1046 /* leave anonymous unions enabled */
1047 #elif (__ARMCC_VERSION >= 6010050)
1048 #pragma clang diagnostic pop
1049 #elif defined (__GNUC__)
1050 /* anonymous unions are enabled by default */
1051 #elif defined (__TMS470__)
1052 /* anonymous unions are enabled by default */
1053 #elif defined (__TASKING__)
1054 #pragma warning restore
1055 #elif defined (__CSMC__)
1056 /* anonymous unions are enabled by default */
1057 #endif
1058 
1059 
1060 /* =========================================================================================================================== */
1061 /* ================                                Pos/Mask Peripheral Section                                ================ */
1062 /* =========================================================================================================================== */
1063 
1064 
1065 /** @addtogroup PosMask_peripherals
1066   * @{
1067   */
1068 
1069 /* =========================================================================================================================== */
1070 /*=====================                                    AHBUPCONV                                    ===================== */
1071 /* =========================================================================================================================== */
1072 
1073 /* =====================================================    COMMAND    ===================================================== */
1074 #define AHBUPCONV_COMMAND_STALL_AUTO_CLEAR_Pos                             (5UL)    /*!<AHBUPCONV COMMAND: STALL_AUTO_CLEAR (Bit 5) */
1075 #define AHBUPCONV_COMMAND_STALL_AUTO_CLEAR_Msk                             (0x20UL)   /*!< AHBUPCONV COMMAND: STALL_AUTO_CLEAR (Bitfield-Mask: 0x01) */
1076 #define AHBUPCONV_COMMAND_STALL_AUTO_CLEAR                                 AHBUPCONV_COMMAND_STALL_AUTO_CLEAR_Msk
1077 #define AHBUPCONV_COMMAND_STALL_IEN_Pos                                    (4UL)    /*!<AHBUPCONV COMMAND: STALL_IEN (Bit 4) */
1078 #define AHBUPCONV_COMMAND_STALL_IEN_Msk                                    (0x10UL)   /*!< AHBUPCONV COMMAND: STALL_IEN (Bitfield-Mask: 0x01) */
1079 #define AHBUPCONV_COMMAND_STALL_IEN                                        AHBUPCONV_COMMAND_STALL_IEN_Msk
1080 #define AHBUPCONV_COMMAND_STALL_REQ_Pos                                    (3UL)    /*!<AHBUPCONV COMMAND: STALL_REQ (Bit 3) */
1081 #define AHBUPCONV_COMMAND_STALL_REQ_Msk                                    (0x8UL)    /*!< AHBUPCONV COMMAND: STALL_REQ (Bitfield-Mask: 0x01) */
1082 #define AHBUPCONV_COMMAND_STALL_REQ                                        AHBUPCONV_COMMAND_STALL_REQ_Msk
1083 #define AHBUPCONV_COMMAND_ERROR_IEN_Pos                                    (2UL)    /*!<AHBUPCONV COMMAND: ERROR_IEN (Bit 2) */
1084 #define AHBUPCONV_COMMAND_ERROR_IEN_Msk                                    (0x4UL)    /*!< AHBUPCONV COMMAND: ERROR_IEN (Bitfield-Mask: 0x01) */
1085 #define AHBUPCONV_COMMAND_ERROR_IEN                                        AHBUPCONV_COMMAND_ERROR_IEN_Msk
1086 #define AHBUPCONV_COMMAND_CLK_DIV_SEL_Pos                                  (0UL)    /*!<AHBUPCONV COMMAND: CLK_DIV_SEL (Bit 0) */
1087 #define AHBUPCONV_COMMAND_CLK_DIV_SEL_Msk                                  (0x3UL)    /*!< AHBUPCONV COMMAND: CLK_DIV_SEL (Bitfield-Mask: 0x03) */
1088 #define AHBUPCONV_COMMAND_CLK_DIV_SEL                                      AHBUPCONV_COMMAND_CLK_DIV_SEL_Msk
1089 #define AHBUPCONV_COMMAND_CLK_DIV_SEL_0                                    (0x1U << AHBUPCONV_COMMAND_CLK_DIV_SEL_Pos)
1090 #define AHBUPCONV_COMMAND_CLK_DIV_SEL_1                                    (0x2U << AHBUPCONV_COMMAND_CLK_DIV_SEL_Pos)
1091 
1092 /* =====================================================    STATUS    ===================================================== */
1093 #define AHBUPCONV_STATUS_ACTIVE_STALL_Pos                                  (3UL)    /*!<AHBUPCONV STATUS: ACTIVE_STALL (Bit 3) */
1094 #define AHBUPCONV_STATUS_ACTIVE_STALL_Msk                                  (0x8UL)    /*!< AHBUPCONV STATUS: ACTIVE_STALL (Bitfield-Mask: 0x01) */
1095 #define AHBUPCONV_STATUS_ACTIVE_STALL                                      AHBUPCONV_STATUS_ACTIVE_STALL_Msk
1096 #define AHBUPCONV_STATUS_ERROR_STAT_Pos                                    (2UL)    /*!<AHBUPCONV STATUS: ERROR_STAT (Bit 2) */
1097 #define AHBUPCONV_STATUS_ERROR_STAT_Msk                                    (0x4UL)    /*!< AHBUPCONV STATUS: ERROR_STAT (Bitfield-Mask: 0x01) */
1098 #define AHBUPCONV_STATUS_ERROR_STAT                                        AHBUPCONV_STATUS_ERROR_STAT_Msk
1099 #define AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_Pos                              (0UL)    /*!<AHBUPCONV STATUS: CLK_DIV_SEL_STAT (Bit 0) */
1100 #define AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_Msk                              (0x3UL)    /*!< AHBUPCONV STATUS: CLK_DIV_SEL_STAT (Bitfield-Mask: 0x03) */
1101 #define AHBUPCONV_STATUS_CLK_DIV_SEL_STAT                                  AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_Msk
1102 #define AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_0                                (0x1U << AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_Pos)
1103 #define AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_1                                (0x2U << AHBUPCONV_STATUS_CLK_DIV_SEL_STAT_Pos)
1104 
1105 
1106 /* =========================================================================================================================== */
1107 /*=====================                                       DMA                                       ===================== */
1108 /* =========================================================================================================================== */
1109 
1110 /* =====================================================    ISR    ===================================================== */
1111 #define DMA_ISR_TEIF8_Pos                                                  (31UL)   /*!<DMA ISR: TEIF8 (Bit 31) */
1112 #define DMA_ISR_TEIF8_Msk                                                  (0x80000000UL)   /*!< DMA ISR: TEIF8 (Bitfield-Mask: 0x01) */
1113 #define DMA_ISR_TEIF8                                                      DMA_ISR_TEIF8_Msk
1114 #define DMA_ISR_HTIF8_Pos                                                  (30UL)   /*!<DMA ISR: HTIF8 (Bit 30) */
1115 #define DMA_ISR_HTIF8_Msk                                                  (0x40000000UL)   /*!< DMA ISR: HTIF8 (Bitfield-Mask: 0x01) */
1116 #define DMA_ISR_HTIF8                                                      DMA_ISR_HTIF8_Msk
1117 #define DMA_ISR_TCIF8_Pos                                                  (29UL)   /*!<DMA ISR: TCIF8 (Bit 29) */
1118 #define DMA_ISR_TCIF8_Msk                                                  (0x20000000UL)   /*!< DMA ISR: TCIF8 (Bitfield-Mask: 0x01) */
1119 #define DMA_ISR_TCIF8                                                      DMA_ISR_TCIF8_Msk
1120 #define DMA_ISR_GIF8_Pos                                                   (28UL)   /*!<DMA ISR: GIF8 (Bit 28) */
1121 #define DMA_ISR_GIF8_Msk                                                   (0x10000000UL)   /*!< DMA ISR: GIF8 (Bitfield-Mask: 0x01) */
1122 #define DMA_ISR_GIF8                                                       DMA_ISR_GIF8_Msk
1123 #define DMA_ISR_TEIF7_Pos                                                  (27UL)   /*!<DMA ISR: TEIF7 (Bit 27) */
1124 #define DMA_ISR_TEIF7_Msk                                                  (0x8000000UL)    /*!< DMA ISR: TEIF7 (Bitfield-Mask: 0x01) */
1125 #define DMA_ISR_TEIF7                                                      DMA_ISR_TEIF7_Msk
1126 #define DMA_ISR_HTIF7_Pos                                                  (26UL)   /*!<DMA ISR: HTIF7 (Bit 26) */
1127 #define DMA_ISR_HTIF7_Msk                                                  (0x4000000UL)    /*!< DMA ISR: HTIF7 (Bitfield-Mask: 0x01) */
1128 #define DMA_ISR_HTIF7                                                      DMA_ISR_HTIF7_Msk
1129 #define DMA_ISR_TCIF7_Pos                                                  (25UL)   /*!<DMA ISR: TCIF7 (Bit 25) */
1130 #define DMA_ISR_TCIF7_Msk                                                  (0x2000000UL)    /*!< DMA ISR: TCIF7 (Bitfield-Mask: 0x01) */
1131 #define DMA_ISR_TCIF7                                                      DMA_ISR_TCIF7_Msk
1132 #define DMA_ISR_GIF7_Pos                                                   (24UL)   /*!<DMA ISR: GIF7 (Bit 24) */
1133 #define DMA_ISR_GIF7_Msk                                                   (0x1000000UL)    /*!< DMA ISR: GIF7 (Bitfield-Mask: 0x01) */
1134 #define DMA_ISR_GIF7                                                       DMA_ISR_GIF7_Msk
1135 #define DMA_ISR_TEIF6_Pos                                                  (23UL)   /*!<DMA ISR: TEIF6 (Bit 23) */
1136 #define DMA_ISR_TEIF6_Msk                                                  (0x800000UL)   /*!< DMA ISR: TEIF6 (Bitfield-Mask: 0x01) */
1137 #define DMA_ISR_TEIF6                                                      DMA_ISR_TEIF6_Msk
1138 #define DMA_ISR_HTIF6_Pos                                                  (22UL)   /*!<DMA ISR: HTIF6 (Bit 22) */
1139 #define DMA_ISR_HTIF6_Msk                                                  (0x400000UL)   /*!< DMA ISR: HTIF6 (Bitfield-Mask: 0x01) */
1140 #define DMA_ISR_HTIF6                                                      DMA_ISR_HTIF6_Msk
1141 #define DMA_ISR_TCIF6_Pos                                                  (21UL)   /*!<DMA ISR: TCIF6 (Bit 21) */
1142 #define DMA_ISR_TCIF6_Msk                                                  (0x200000UL)   /*!< DMA ISR: TCIF6 (Bitfield-Mask: 0x01) */
1143 #define DMA_ISR_TCIF6                                                      DMA_ISR_TCIF6_Msk
1144 #define DMA_ISR_GIF6_Pos                                                   (20UL)   /*!<DMA ISR: GIF6 (Bit 20) */
1145 #define DMA_ISR_GIF6_Msk                                                   (0x100000UL)   /*!< DMA ISR: GIF6 (Bitfield-Mask: 0x01) */
1146 #define DMA_ISR_GIF6                                                       DMA_ISR_GIF6_Msk
1147 #define DMA_ISR_TEIF5_Pos                                                  (19UL)   /*!<DMA ISR: TEIF5 (Bit 19) */
1148 #define DMA_ISR_TEIF5_Msk                                                  (0x80000UL)    /*!< DMA ISR: TEIF5 (Bitfield-Mask: 0x01) */
1149 #define DMA_ISR_TEIF5                                                      DMA_ISR_TEIF5_Msk
1150 #define DMA_ISR_HTIF5_Pos                                                  (18UL)   /*!<DMA ISR: HTIF5 (Bit 18) */
1151 #define DMA_ISR_HTIF5_Msk                                                  (0x40000UL)    /*!< DMA ISR: HTIF5 (Bitfield-Mask: 0x01) */
1152 #define DMA_ISR_HTIF5                                                      DMA_ISR_HTIF5_Msk
1153 #define DMA_ISR_TCIF5_Pos                                                  (17UL)   /*!<DMA ISR: TCIF5 (Bit 17) */
1154 #define DMA_ISR_TCIF5_Msk                                                  (0x20000UL)    /*!< DMA ISR: TCIF5 (Bitfield-Mask: 0x01) */
1155 #define DMA_ISR_TCIF5                                                      DMA_ISR_TCIF5_Msk
1156 #define DMA_ISR_GIF5_Pos                                                   (16UL)   /*!<DMA ISR: GIF5 (Bit 16) */
1157 #define DMA_ISR_GIF5_Msk                                                   (0x10000UL)    /*!< DMA ISR: GIF5 (Bitfield-Mask: 0x01) */
1158 #define DMA_ISR_GIF5                                                       DMA_ISR_GIF5_Msk
1159 #define DMA_ISR_TEIF4_Pos                                                  (15UL)   /*!<DMA ISR: TEIF4 (Bit 15) */
1160 #define DMA_ISR_TEIF4_Msk                                                  (0x8000UL)   /*!< DMA ISR: TEIF4 (Bitfield-Mask: 0x01) */
1161 #define DMA_ISR_TEIF4                                                      DMA_ISR_TEIF4_Msk
1162 #define DMA_ISR_HTIF4_Pos                                                  (14UL)   /*!<DMA ISR: HTIF4 (Bit 14) */
1163 #define DMA_ISR_HTIF4_Msk                                                  (0x4000UL)   /*!< DMA ISR: HTIF4 (Bitfield-Mask: 0x01) */
1164 #define DMA_ISR_HTIF4                                                      DMA_ISR_HTIF4_Msk
1165 #define DMA_ISR_TCIF4_Pos                                                  (13UL)   /*!<DMA ISR: TCIF4 (Bit 13) */
1166 #define DMA_ISR_TCIF4_Msk                                                  (0x2000UL)   /*!< DMA ISR: TCIF4 (Bitfield-Mask: 0x01) */
1167 #define DMA_ISR_TCIF4                                                      DMA_ISR_TCIF4_Msk
1168 #define DMA_ISR_GIF4_Pos                                                   (12UL)   /*!<DMA ISR: GIF4 (Bit 12) */
1169 #define DMA_ISR_GIF4_Msk                                                   (0x1000UL)   /*!< DMA ISR: GIF4 (Bitfield-Mask: 0x01) */
1170 #define DMA_ISR_GIF4                                                       DMA_ISR_GIF4_Msk
1171 #define DMA_ISR_TEIF3_Pos                                                  (11UL)   /*!<DMA ISR: TEIF3 (Bit 11) */
1172 #define DMA_ISR_TEIF3_Msk                                                  (0x800UL)    /*!< DMA ISR: TEIF3 (Bitfield-Mask: 0x01) */
1173 #define DMA_ISR_TEIF3                                                      DMA_ISR_TEIF3_Msk
1174 #define DMA_ISR_HTIF3_Pos                                                  (10UL)   /*!<DMA ISR: HTIF3 (Bit 10) */
1175 #define DMA_ISR_HTIF3_Msk                                                  (0x400UL)    /*!< DMA ISR: HTIF3 (Bitfield-Mask: 0x01) */
1176 #define DMA_ISR_HTIF3                                                      DMA_ISR_HTIF3_Msk
1177 #define DMA_ISR_TCIF3_Pos                                                  (9UL)    /*!<DMA ISR: TCIF3 (Bit 9) */
1178 #define DMA_ISR_TCIF3_Msk                                                  (0x200UL)    /*!< DMA ISR: TCIF3 (Bitfield-Mask: 0x01) */
1179 #define DMA_ISR_TCIF3                                                      DMA_ISR_TCIF3_Msk
1180 #define DMA_ISR_GIF3_Pos                                                   (8UL)    /*!<DMA ISR: GIF3 (Bit 8) */
1181 #define DMA_ISR_GIF3_Msk                                                   (0x100UL)    /*!< DMA ISR: GIF3 (Bitfield-Mask: 0x01) */
1182 #define DMA_ISR_GIF3                                                       DMA_ISR_GIF3_Msk
1183 #define DMA_ISR_TEIF2_Pos                                                  (7UL)    /*!<DMA ISR: TEIF2 (Bit 7) */
1184 #define DMA_ISR_TEIF2_Msk                                                  (0x80UL)   /*!< DMA ISR: TEIF2 (Bitfield-Mask: 0x01) */
1185 #define DMA_ISR_TEIF2                                                      DMA_ISR_TEIF2_Msk
1186 #define DMA_ISR_HTIF2_Pos                                                  (6UL)    /*!<DMA ISR: HTIF2 (Bit 6) */
1187 #define DMA_ISR_HTIF2_Msk                                                  (0x40UL)   /*!< DMA ISR: HTIF2 (Bitfield-Mask: 0x01) */
1188 #define DMA_ISR_HTIF2                                                      DMA_ISR_HTIF2_Msk
1189 #define DMA_ISR_TCIF2_Pos                                                  (5UL)    /*!<DMA ISR: TCIF2 (Bit 5) */
1190 #define DMA_ISR_TCIF2_Msk                                                  (0x20UL)   /*!< DMA ISR: TCIF2 (Bitfield-Mask: 0x01) */
1191 #define DMA_ISR_TCIF2                                                      DMA_ISR_TCIF2_Msk
1192 #define DMA_ISR_GIF2_Pos                                                   (4UL)    /*!<DMA ISR: GIF2 (Bit 4) */
1193 #define DMA_ISR_GIF2_Msk                                                   (0x10UL)   /*!< DMA ISR: GIF2 (Bitfield-Mask: 0x01) */
1194 #define DMA_ISR_GIF2                                                       DMA_ISR_GIF2_Msk
1195 #define DMA_ISR_TEIF1_Pos                                                  (3UL)    /*!<DMA ISR: TEIF1 (Bit 3) */
1196 #define DMA_ISR_TEIF1_Msk                                                  (0x8UL)    /*!< DMA ISR: TEIF1 (Bitfield-Mask: 0x01) */
1197 #define DMA_ISR_TEIF1                                                      DMA_ISR_TEIF1_Msk
1198 #define DMA_ISR_HTIF1_Pos                                                  (2UL)    /*!<DMA ISR: HTIF1 (Bit 2) */
1199 #define DMA_ISR_HTIF1_Msk                                                  (0x4UL)    /*!< DMA ISR: HTIF1 (Bitfield-Mask: 0x01) */
1200 #define DMA_ISR_HTIF1                                                      DMA_ISR_HTIF1_Msk
1201 #define DMA_ISR_TCIF1_Pos                                                  (1UL)    /*!<DMA ISR: TCIF1 (Bit 1) */
1202 #define DMA_ISR_TCIF1_Msk                                                  (0x2UL)    /*!< DMA ISR: TCIF1 (Bitfield-Mask: 0x01) */
1203 #define DMA_ISR_TCIF1                                                      DMA_ISR_TCIF1_Msk
1204 #define DMA_ISR_GIF1_Pos                                                   (0UL)    /*!<DMA ISR: GIF1 (Bit 0) */
1205 #define DMA_ISR_GIF1_Msk                                                   (0x1UL)    /*!< DMA ISR: GIF1 (Bitfield-Mask: 0x01) */
1206 #define DMA_ISR_GIF1                                                       DMA_ISR_GIF1_Msk
1207 
1208 /* =====================================================    IFCR    ===================================================== */
1209 #define DMA_IFCR_CTEIF8_Pos                                                (31UL)   /*!<DMA IFCR: CTEIF8 (Bit 31) */
1210 #define DMA_IFCR_CTEIF8_Msk                                                (0x80000000UL)   /*!< DMA IFCR: CTEIF8 (Bitfield-Mask: 0x01) */
1211 #define DMA_IFCR_CTEIF8                                                    DMA_IFCR_CTEIF8_Msk
1212 #define DMA_IFCR_CHTIF8_Pos                                                (30UL)   /*!<DMA IFCR: CHTIF8 (Bit 30) */
1213 #define DMA_IFCR_CHTIF8_Msk                                                (0x40000000UL)   /*!< DMA IFCR: CHTIF8 (Bitfield-Mask: 0x01) */
1214 #define DMA_IFCR_CHTIF8                                                    DMA_IFCR_CHTIF8_Msk
1215 #define DMA_IFCR_CTCIF8_Pos                                                (29UL)   /*!<DMA IFCR: CTCIF8 (Bit 29) */
1216 #define DMA_IFCR_CTCIF8_Msk                                                (0x20000000UL)   /*!< DMA IFCR: CTCIF8 (Bitfield-Mask: 0x01) */
1217 #define DMA_IFCR_CTCIF8                                                    DMA_IFCR_CTCIF8_Msk
1218 #define DMA_IFCR_CGIF8_Pos                                                 (28UL)   /*!<DMA IFCR: CGIF8 (Bit 28) */
1219 #define DMA_IFCR_CGIF8_Msk                                                 (0x10000000UL)   /*!< DMA IFCR: CGIF8 (Bitfield-Mask: 0x01) */
1220 #define DMA_IFCR_CGIF8                                                     DMA_IFCR_CGIF8_Msk
1221 #define DMA_IFCR_CTEIF7_Pos                                                (27UL)   /*!<DMA IFCR: CTEIF7 (Bit 27) */
1222 #define DMA_IFCR_CTEIF7_Msk                                                (0x8000000UL)    /*!< DMA IFCR: CTEIF7 (Bitfield-Mask: 0x01) */
1223 #define DMA_IFCR_CTEIF7                                                    DMA_IFCR_CTEIF7_Msk
1224 #define DMA_IFCR_CHTIF7_Pos                                                (26UL)   /*!<DMA IFCR: CHTIF7 (Bit 26) */
1225 #define DMA_IFCR_CHTIF7_Msk                                                (0x4000000UL)    /*!< DMA IFCR: CHTIF7 (Bitfield-Mask: 0x01) */
1226 #define DMA_IFCR_CHTIF7                                                    DMA_IFCR_CHTIF7_Msk
1227 #define DMA_IFCR_CTCIF7_Pos                                                (25UL)   /*!<DMA IFCR: CTCIF7 (Bit 25) */
1228 #define DMA_IFCR_CTCIF7_Msk                                                (0x2000000UL)    /*!< DMA IFCR: CTCIF7 (Bitfield-Mask: 0x01) */
1229 #define DMA_IFCR_CTCIF7                                                    DMA_IFCR_CTCIF7_Msk
1230 #define DMA_IFCR_CGIF7_Pos                                                 (24UL)   /*!<DMA IFCR: CGIF7 (Bit 24) */
1231 #define DMA_IFCR_CGIF7_Msk                                                 (0x1000000UL)    /*!< DMA IFCR: CGIF7 (Bitfield-Mask: 0x01) */
1232 #define DMA_IFCR_CGIF7                                                     DMA_IFCR_CGIF7_Msk
1233 #define DMA_IFCR_CTEIF6_Pos                                                (23UL)   /*!<DMA IFCR: CTEIF6 (Bit 23) */
1234 #define DMA_IFCR_CTEIF6_Msk                                                (0x800000UL)   /*!< DMA IFCR: CTEIF6 (Bitfield-Mask: 0x01) */
1235 #define DMA_IFCR_CTEIF6                                                    DMA_IFCR_CTEIF6_Msk
1236 #define DMA_IFCR_CHTIF6_Pos                                                (22UL)   /*!<DMA IFCR: CHTIF6 (Bit 22) */
1237 #define DMA_IFCR_CHTIF6_Msk                                                (0x400000UL)   /*!< DMA IFCR: CHTIF6 (Bitfield-Mask: 0x01) */
1238 #define DMA_IFCR_CHTIF6                                                    DMA_IFCR_CHTIF6_Msk
1239 #define DMA_IFCR_CTCIF6_Pos                                                (21UL)   /*!<DMA IFCR: CTCIF6 (Bit 21) */
1240 #define DMA_IFCR_CTCIF6_Msk                                                (0x200000UL)   /*!< DMA IFCR: CTCIF6 (Bitfield-Mask: 0x01) */
1241 #define DMA_IFCR_CTCIF6                                                    DMA_IFCR_CTCIF6_Msk
1242 #define DMA_IFCR_CGIF6_Pos                                                 (20UL)   /*!<DMA IFCR: CGIF6 (Bit 20) */
1243 #define DMA_IFCR_CGIF6_Msk                                                 (0x100000UL)   /*!< DMA IFCR: CGIF6 (Bitfield-Mask: 0x01) */
1244 #define DMA_IFCR_CGIF6                                                     DMA_IFCR_CGIF6_Msk
1245 #define DMA_IFCR_CTEIF5_Pos                                                (19UL)   /*!<DMA IFCR: CTEIF5 (Bit 19) */
1246 #define DMA_IFCR_CTEIF5_Msk                                                (0x80000UL)    /*!< DMA IFCR: CTEIF5 (Bitfield-Mask: 0x01) */
1247 #define DMA_IFCR_CTEIF5                                                    DMA_IFCR_CTEIF5_Msk
1248 #define DMA_IFCR_CHTIF5_Pos                                                (18UL)   /*!<DMA IFCR: CHTIF5 (Bit 18) */
1249 #define DMA_IFCR_CHTIF5_Msk                                                (0x40000UL)    /*!< DMA IFCR: CHTIF5 (Bitfield-Mask: 0x01) */
1250 #define DMA_IFCR_CHTIF5                                                    DMA_IFCR_CHTIF5_Msk
1251 #define DMA_IFCR_CTCIF5_Pos                                                (17UL)   /*!<DMA IFCR: CTCIF5 (Bit 17) */
1252 #define DMA_IFCR_CTCIF5_Msk                                                (0x20000UL)    /*!< DMA IFCR: CTCIF5 (Bitfield-Mask: 0x01) */
1253 #define DMA_IFCR_CTCIF5                                                    DMA_IFCR_CTCIF5_Msk
1254 #define DMA_IFCR_CGIF5_Pos                                                 (16UL)   /*!<DMA IFCR: CGIF5 (Bit 16) */
1255 #define DMA_IFCR_CGIF5_Msk                                                 (0x10000UL)    /*!< DMA IFCR: CGIF5 (Bitfield-Mask: 0x01) */
1256 #define DMA_IFCR_CGIF5                                                     DMA_IFCR_CGIF5_Msk
1257 #define DMA_IFCR_CTEIF4_Pos                                                (15UL)   /*!<DMA IFCR: CTEIF4 (Bit 15) */
1258 #define DMA_IFCR_CTEIF4_Msk                                                (0x8000UL)   /*!< DMA IFCR: CTEIF4 (Bitfield-Mask: 0x01) */
1259 #define DMA_IFCR_CTEIF4                                                    DMA_IFCR_CTEIF4_Msk
1260 #define DMA_IFCR_CHTIF4_Pos                                                (14UL)   /*!<DMA IFCR: CHTIF4 (Bit 14) */
1261 #define DMA_IFCR_CHTIF4_Msk                                                (0x4000UL)   /*!< DMA IFCR: CHTIF4 (Bitfield-Mask: 0x01) */
1262 #define DMA_IFCR_CHTIF4                                                    DMA_IFCR_CHTIF4_Msk
1263 #define DMA_IFCR_CTCIF4_Pos                                                (13UL)   /*!<DMA IFCR: CTCIF4 (Bit 13) */
1264 #define DMA_IFCR_CTCIF4_Msk                                                (0x2000UL)   /*!< DMA IFCR: CTCIF4 (Bitfield-Mask: 0x01) */
1265 #define DMA_IFCR_CTCIF4                                                    DMA_IFCR_CTCIF4_Msk
1266 #define DMA_IFCR_CGIF4_Pos                                                 (12UL)   /*!<DMA IFCR: CGIF4 (Bit 12) */
1267 #define DMA_IFCR_CGIF4_Msk                                                 (0x1000UL)   /*!< DMA IFCR: CGIF4 (Bitfield-Mask: 0x01) */
1268 #define DMA_IFCR_CGIF4                                                     DMA_IFCR_CGIF4_Msk
1269 #define DMA_IFCR_CTEIF3_Pos                                                (11UL)   /*!<DMA IFCR: CTEIF3 (Bit 11) */
1270 #define DMA_IFCR_CTEIF3_Msk                                                (0x800UL)    /*!< DMA IFCR: CTEIF3 (Bitfield-Mask: 0x01) */
1271 #define DMA_IFCR_CTEIF3                                                    DMA_IFCR_CTEIF3_Msk
1272 #define DMA_IFCR_CHTIF3_Pos                                                (10UL)   /*!<DMA IFCR: CHTIF3 (Bit 10) */
1273 #define DMA_IFCR_CHTIF3_Msk                                                (0x400UL)    /*!< DMA IFCR: CHTIF3 (Bitfield-Mask: 0x01) */
1274 #define DMA_IFCR_CHTIF3                                                    DMA_IFCR_CHTIF3_Msk
1275 #define DMA_IFCR_CTCIF3_Pos                                                (9UL)    /*!<DMA IFCR: CTCIF3 (Bit 9) */
1276 #define DMA_IFCR_CTCIF3_Msk                                                (0x200UL)    /*!< DMA IFCR: CTCIF3 (Bitfield-Mask: 0x01) */
1277 #define DMA_IFCR_CTCIF3                                                    DMA_IFCR_CTCIF3_Msk
1278 #define DMA_IFCR_CGIF3_Pos                                                 (8UL)    /*!<DMA IFCR: CGIF3 (Bit 8) */
1279 #define DMA_IFCR_CGIF3_Msk                                                 (0x100UL)    /*!< DMA IFCR: CGIF3 (Bitfield-Mask: 0x01) */
1280 #define DMA_IFCR_CGIF3                                                     DMA_IFCR_CGIF3_Msk
1281 #define DMA_IFCR_CTEIF2_Pos                                                (7UL)    /*!<DMA IFCR: CTEIF2 (Bit 7) */
1282 #define DMA_IFCR_CTEIF2_Msk                                                (0x80UL)   /*!< DMA IFCR: CTEIF2 (Bitfield-Mask: 0x01) */
1283 #define DMA_IFCR_CTEIF2                                                    DMA_IFCR_CTEIF2_Msk
1284 #define DMA_IFCR_CHTIF2_Pos                                                (6UL)    /*!<DMA IFCR: CHTIF2 (Bit 6) */
1285 #define DMA_IFCR_CHTIF2_Msk                                                (0x40UL)   /*!< DMA IFCR: CHTIF2 (Bitfield-Mask: 0x01) */
1286 #define DMA_IFCR_CHTIF2                                                    DMA_IFCR_CHTIF2_Msk
1287 #define DMA_IFCR_CTCIF2_Pos                                                (5UL)    /*!<DMA IFCR: CTCIF2 (Bit 5) */
1288 #define DMA_IFCR_CTCIF2_Msk                                                (0x20UL)   /*!< DMA IFCR: CTCIF2 (Bitfield-Mask: 0x01) */
1289 #define DMA_IFCR_CTCIF2                                                    DMA_IFCR_CTCIF2_Msk
1290 #define DMA_IFCR_CGIF2_Pos                                                 (4UL)    /*!<DMA IFCR: CGIF2 (Bit 4) */
1291 #define DMA_IFCR_CGIF2_Msk                                                 (0x10UL)   /*!< DMA IFCR: CGIF2 (Bitfield-Mask: 0x01) */
1292 #define DMA_IFCR_CGIF2                                                     DMA_IFCR_CGIF2_Msk
1293 #define DMA_IFCR_CTEIF1_Pos                                                (3UL)    /*!<DMA IFCR: CTEIF1 (Bit 3) */
1294 #define DMA_IFCR_CTEIF1_Msk                                                (0x8UL)    /*!< DMA IFCR: CTEIF1 (Bitfield-Mask: 0x01) */
1295 #define DMA_IFCR_CTEIF1                                                    DMA_IFCR_CTEIF1_Msk
1296 #define DMA_IFCR_CHTIF1_Pos                                                (2UL)    /*!<DMA IFCR: CHTIF1 (Bit 2) */
1297 #define DMA_IFCR_CHTIF1_Msk                                                (0x4UL)    /*!< DMA IFCR: CHTIF1 (Bitfield-Mask: 0x01) */
1298 #define DMA_IFCR_CHTIF1                                                    DMA_IFCR_CHTIF1_Msk
1299 #define DMA_IFCR_CTCIF1_Pos                                                (1UL)    /*!<DMA IFCR: CTCIF1 (Bit 1) */
1300 #define DMA_IFCR_CTCIF1_Msk                                                (0x2UL)    /*!< DMA IFCR: CTCIF1 (Bitfield-Mask: 0x01) */
1301 #define DMA_IFCR_CTCIF1                                                    DMA_IFCR_CTCIF1_Msk
1302 #define DMA_IFCR_CGIF1_Pos                                                 (0UL)    /*!<DMA IFCR: CGIF1 (Bit 0) */
1303 #define DMA_IFCR_CGIF1_Msk                                                 (0x1UL)    /*!< DMA IFCR: CGIF1 (Bitfield-Mask: 0x01) */
1304 #define DMA_IFCR_CGIF1                                                     DMA_IFCR_CGIF1_Msk
1305 
1306 /* =====================================================    CCR    ===================================================== */
1307 #define DMA_CCR_MEM2MEM_Pos                                                (14UL)   /*!<DMA CCR: MEM2MEM (Bit 14) */
1308 #define DMA_CCR_MEM2MEM_Msk                                                (0x4000UL)   /*!< DMA CCR: MEM2MEM (Bitfield-Mask: 0x01) */
1309 #define DMA_CCR_MEM2MEM                                                    DMA_CCR_MEM2MEM_Msk
1310 #define DMA_CCR_PL_Pos                                                     (12UL)   /*!<DMA CCR: PL (Bit 12) */
1311 #define DMA_CCR_PL_Msk                                                     (0x3000UL)   /*!< DMA CCR: PL (Bitfield-Mask: 0x03) */
1312 #define DMA_CCR_PL                                                         DMA_CCR_PL_Msk
1313 #define DMA_CCR_PL_0                                                       (0x1U << DMA_CCR_PL_Pos)
1314 #define DMA_CCR_PL_1                                                       (0x2U << DMA_CCR_PL_Pos)
1315 #define DMA_CCR_MSIZE_Pos                                                  (10UL)   /*!<DMA CCR: MSIZE (Bit 10) */
1316 #define DMA_CCR_MSIZE_Msk                                                  (0xc00UL)    /*!< DMA CCR: MSIZE (Bitfield-Mask: 0x03) */
1317 #define DMA_CCR_MSIZE                                                      DMA_CCR_MSIZE_Msk
1318 #define DMA_CCR_MSIZE_0                                                    (0x1U << DMA_CCR_MSIZE_Pos)
1319 #define DMA_CCR_MSIZE_1                                                    (0x2U << DMA_CCR_MSIZE_Pos)
1320 #define DMA_CCR_PSIZE_Pos                                                  (8UL)    /*!<DMA CCR: PSIZE (Bit 8) */
1321 #define DMA_CCR_PSIZE_Msk                                                  (0x300UL)    /*!< DMA CCR: PSIZE (Bitfield-Mask: 0x03) */
1322 #define DMA_CCR_PSIZE                                                      DMA_CCR_PSIZE_Msk
1323 #define DMA_CCR_PSIZE_0                                                    (0x1U << DMA_CCR_PSIZE_Pos)
1324 #define DMA_CCR_PSIZE_1                                                    (0x2U << DMA_CCR_PSIZE_Pos)
1325 #define DMA_CCR_MINC_Pos                                                   (7UL)    /*!<DMA CCR: MINC (Bit 7) */
1326 #define DMA_CCR_MINC_Msk                                                   (0x80UL)   /*!< DMA CCR: MINC (Bitfield-Mask: 0x01) */
1327 #define DMA_CCR_MINC                                                       DMA_CCR_MINC_Msk
1328 #define DMA_CCR_PINC_Pos                                                   (6UL)    /*!<DMA CCR: PINC (Bit 6) */
1329 #define DMA_CCR_PINC_Msk                                                   (0x40UL)   /*!< DMA CCR: PINC (Bitfield-Mask: 0x01) */
1330 #define DMA_CCR_PINC                                                       DMA_CCR_PINC_Msk
1331 #define DMA_CCR_CIRC_Pos                                                   (5UL)    /*!<DMA CCR: CIRC (Bit 5) */
1332 #define DMA_CCR_CIRC_Msk                                                   (0x20UL)   /*!< DMA CCR: CIRC (Bitfield-Mask: 0x01) */
1333 #define DMA_CCR_CIRC                                                       DMA_CCR_CIRC_Msk
1334 #define DMA_CCR_DIR_Pos                                                    (4UL)    /*!<DMA CCR: DIR (Bit 4) */
1335 #define DMA_CCR_DIR_Msk                                                    (0x10UL)   /*!< DMA CCR: DIR (Bitfield-Mask: 0x01) */
1336 #define DMA_CCR_DIR                                                        DMA_CCR_DIR_Msk
1337 #define DMA_CCR_TEIE_Pos                                                   (3UL)    /*!<DMA CCR: TEIE (Bit 3) */
1338 #define DMA_CCR_TEIE_Msk                                                   (0x8UL)    /*!< DMA CCR: TEIE (Bitfield-Mask: 0x01) */
1339 #define DMA_CCR_TEIE                                                       DMA_CCR_TEIE_Msk
1340 #define DMA_CCR_HTIE_Pos                                                   (2UL)    /*!<DMA CCR: HTIE (Bit 2) */
1341 #define DMA_CCR_HTIE_Msk                                                   (0x4UL)    /*!< DMA CCR: HTIE (Bitfield-Mask: 0x01) */
1342 #define DMA_CCR_HTIE                                                       DMA_CCR_HTIE_Msk
1343 #define DMA_CCR_TCIE_Pos                                                   (1UL)    /*!<DMA CCR: TCIE (Bit 1) */
1344 #define DMA_CCR_TCIE_Msk                                                   (0x2UL)    /*!< DMA CCR: TCIE (Bitfield-Mask: 0x01) */
1345 #define DMA_CCR_TCIE                                                       DMA_CCR_TCIE_Msk
1346 #define DMA_CCR_EN_Pos                                                     (0UL)    /*!<DMA CCR: EN (Bit 0) */
1347 #define DMA_CCR_EN_Msk                                                     (0x1UL)    /*!< DMA CCR: EN (Bitfield-Mask: 0x01) */
1348 #define DMA_CCR_EN                                                         DMA_CCR_EN_Msk
1349 
1350 /* =====================================================    CNDTR    ===================================================== */
1351 #define DMA_CNDTR_NDT_Pos                                                  (0UL)    /*!<DMA CNDTR: NDT (Bit 0) */
1352 #define DMA_CNDTR_NDT_Msk                                                  (0xffffUL)   /*!< DMA CNDTR: NDT (Bitfield-Mask: 0xffff) */
1353 #define DMA_CNDTR_NDT                                                      DMA_CNDTR_NDT_Msk
1354 #define DMA_CNDTR_NDT_0                                                    (0x1U << DMA_CNDTR_NDT_Pos)
1355 #define DMA_CNDTR_NDT_1                                                    (0x2U << DMA_CNDTR_NDT_Pos)
1356 #define DMA_CNDTR_NDT_2                                                    (0x4U << DMA_CNDTR_NDT_Pos)
1357 #define DMA_CNDTR_NDT_3                                                    (0x8U << DMA_CNDTR_NDT_Pos)
1358 #define DMA_CNDTR_NDT_4                                                    (0x10U << DMA_CNDTR_NDT_Pos)
1359 #define DMA_CNDTR_NDT_5                                                    (0x20U << DMA_CNDTR_NDT_Pos)
1360 #define DMA_CNDTR_NDT_6                                                    (0x40U << DMA_CNDTR_NDT_Pos)
1361 #define DMA_CNDTR_NDT_7                                                    (0x80U << DMA_CNDTR_NDT_Pos)
1362 #define DMA_CNDTR_NDT_8                                                    (0x100U << DMA_CNDTR_NDT_Pos)
1363 #define DMA_CNDTR_NDT_9                                                    (0x200U << DMA_CNDTR_NDT_Pos)
1364 #define DMA_CNDTR_NDT_10                                                   (0x400U << DMA_CNDTR_NDT_Pos)
1365 #define DMA_CNDTR_NDT_11                                                   (0x800U << DMA_CNDTR_NDT_Pos)
1366 #define DMA_CNDTR_NDT_12                                                   (0x1000U << DMA_CNDTR_NDT_Pos)
1367 #define DMA_CNDTR_NDT_13                                                   (0x2000U << DMA_CNDTR_NDT_Pos)
1368 #define DMA_CNDTR_NDT_14                                                   (0x4000U << DMA_CNDTR_NDT_Pos)
1369 #define DMA_CNDTR_NDT_15                                                   (0x8000U << DMA_CNDTR_NDT_Pos)
1370 
1371 /* =====================================================    CPAR    ===================================================== */
1372 #define DMA_CPAR_PA_Pos                                                    (0UL)    /*!<DMA CPAR: PA (Bit 0) */
1373 #define DMA_CPAR_PA_Msk                                                    (0xffffffffUL)   /*!< DMA CPAR: PA (Bitfield-Mask: 0xffffffff) */
1374 #define DMA_CPAR_PA                                                        DMA_CPAR_PA_Msk
1375 #define DMA_CPAR_PA_0                                                      (0x1U << DMA_CPAR_PA_Pos)
1376 #define DMA_CPAR_PA_1                                                      (0x2U << DMA_CPAR_PA_Pos)
1377 #define DMA_CPAR_PA_2                                                      (0x4U << DMA_CPAR_PA_Pos)
1378 #define DMA_CPAR_PA_3                                                      (0x8U << DMA_CPAR_PA_Pos)
1379 #define DMA_CPAR_PA_4                                                      (0x10U << DMA_CPAR_PA_Pos)
1380 #define DMA_CPAR_PA_5                                                      (0x20U << DMA_CPAR_PA_Pos)
1381 #define DMA_CPAR_PA_6                                                      (0x40U << DMA_CPAR_PA_Pos)
1382 #define DMA_CPAR_PA_7                                                      (0x80U << DMA_CPAR_PA_Pos)
1383 #define DMA_CPAR_PA_8                                                      (0x100U << DMA_CPAR_PA_Pos)
1384 #define DMA_CPAR_PA_9                                                      (0x200U << DMA_CPAR_PA_Pos)
1385 #define DMA_CPAR_PA_10                                                     (0x400U << DMA_CPAR_PA_Pos)
1386 #define DMA_CPAR_PA_11                                                     (0x800U << DMA_CPAR_PA_Pos)
1387 #define DMA_CPAR_PA_12                                                     (0x1000U << DMA_CPAR_PA_Pos)
1388 #define DMA_CPAR_PA_13                                                     (0x2000U << DMA_CPAR_PA_Pos)
1389 #define DMA_CPAR_PA_14                                                     (0x4000U << DMA_CPAR_PA_Pos)
1390 #define DMA_CPAR_PA_15                                                     (0x8000U << DMA_CPAR_PA_Pos)
1391 #define DMA_CPAR_PA_16                                                     (0x10000U << DMA_CPAR_PA_Pos)
1392 #define DMA_CPAR_PA_17                                                     (0x20000U << DMA_CPAR_PA_Pos)
1393 #define DMA_CPAR_PA_18                                                     (0x40000U << DMA_CPAR_PA_Pos)
1394 #define DMA_CPAR_PA_19                                                     (0x80000U << DMA_CPAR_PA_Pos)
1395 #define DMA_CPAR_PA_20                                                     (0x100000U << DMA_CPAR_PA_Pos)
1396 #define DMA_CPAR_PA_21                                                     (0x200000U << DMA_CPAR_PA_Pos)
1397 #define DMA_CPAR_PA_22                                                     (0x400000U << DMA_CPAR_PA_Pos)
1398 #define DMA_CPAR_PA_23                                                     (0x800000U << DMA_CPAR_PA_Pos)
1399 #define DMA_CPAR_PA_24                                                     (0x1000000U << DMA_CPAR_PA_Pos)
1400 #define DMA_CPAR_PA_25                                                     (0x2000000U << DMA_CPAR_PA_Pos)
1401 #define DMA_CPAR_PA_26                                                     (0x4000000U << DMA_CPAR_PA_Pos)
1402 #define DMA_CPAR_PA_27                                                     (0x8000000U << DMA_CPAR_PA_Pos)
1403 #define DMA_CPAR_PA_28                                                     (0x10000000U << DMA_CPAR_PA_Pos)
1404 #define DMA_CPAR_PA_29                                                     (0x20000000U << DMA_CPAR_PA_Pos)
1405 #define DMA_CPAR_PA_30                                                     (0x40000000U << DMA_CPAR_PA_Pos)
1406 #define DMA_CPAR_PA_31                                                     (0x80000000UL << DMA_CPAR_PA_Pos)
1407 
1408 /* =====================================================    CMAR    ===================================================== */
1409 #define DMA_CMAR_MA_Pos                                                    (0UL)    /*!<DMA CMAR: MA (Bit 0) */
1410 #define DMA_CMAR_MA_Msk                                                    (0xffffffffUL)   /*!< DMA CMAR: MA (Bitfield-Mask: 0xffffffff) */
1411 #define DMA_CMAR_MA                                                        DMA_CMAR_MA_Msk
1412 #define DMA_CMAR_MA_0                                                      (0x1U << DMA_CMAR_MA_Pos)
1413 #define DMA_CMAR_MA_1                                                      (0x2U << DMA_CMAR_MA_Pos)
1414 #define DMA_CMAR_MA_2                                                      (0x4U << DMA_CMAR_MA_Pos)
1415 #define DMA_CMAR_MA_3                                                      (0x8U << DMA_CMAR_MA_Pos)
1416 #define DMA_CMAR_MA_4                                                      (0x10U << DMA_CMAR_MA_Pos)
1417 #define DMA_CMAR_MA_5                                                      (0x20U << DMA_CMAR_MA_Pos)
1418 #define DMA_CMAR_MA_6                                                      (0x40U << DMA_CMAR_MA_Pos)
1419 #define DMA_CMAR_MA_7                                                      (0x80U << DMA_CMAR_MA_Pos)
1420 #define DMA_CMAR_MA_8                                                      (0x100U << DMA_CMAR_MA_Pos)
1421 #define DMA_CMAR_MA_9                                                      (0x200U << DMA_CMAR_MA_Pos)
1422 #define DMA_CMAR_MA_10                                                     (0x400U << DMA_CMAR_MA_Pos)
1423 #define DMA_CMAR_MA_11                                                     (0x800U << DMA_CMAR_MA_Pos)
1424 #define DMA_CMAR_MA_12                                                     (0x1000U << DMA_CMAR_MA_Pos)
1425 #define DMA_CMAR_MA_13                                                     (0x2000U << DMA_CMAR_MA_Pos)
1426 #define DMA_CMAR_MA_14                                                     (0x4000U << DMA_CMAR_MA_Pos)
1427 #define DMA_CMAR_MA_15                                                     (0x8000U << DMA_CMAR_MA_Pos)
1428 #define DMA_CMAR_MA_16                                                     (0x10000U << DMA_CMAR_MA_Pos)
1429 #define DMA_CMAR_MA_17                                                     (0x20000U << DMA_CMAR_MA_Pos)
1430 #define DMA_CMAR_MA_18                                                     (0x40000U << DMA_CMAR_MA_Pos)
1431 #define DMA_CMAR_MA_19                                                     (0x80000U << DMA_CMAR_MA_Pos)
1432 #define DMA_CMAR_MA_20                                                     (0x100000U << DMA_CMAR_MA_Pos)
1433 #define DMA_CMAR_MA_21                                                     (0x200000U << DMA_CMAR_MA_Pos)
1434 #define DMA_CMAR_MA_22                                                     (0x400000U << DMA_CMAR_MA_Pos)
1435 #define DMA_CMAR_MA_23                                                     (0x800000U << DMA_CMAR_MA_Pos)
1436 #define DMA_CMAR_MA_24                                                     (0x1000000U << DMA_CMAR_MA_Pos)
1437 #define DMA_CMAR_MA_25                                                     (0x2000000U << DMA_CMAR_MA_Pos)
1438 #define DMA_CMAR_MA_26                                                     (0x4000000U << DMA_CMAR_MA_Pos)
1439 #define DMA_CMAR_MA_27                                                     (0x8000000U << DMA_CMAR_MA_Pos)
1440 #define DMA_CMAR_MA_28                                                     (0x10000000U << DMA_CMAR_MA_Pos)
1441 #define DMA_CMAR_MA_29                                                     (0x20000000U << DMA_CMAR_MA_Pos)
1442 #define DMA_CMAR_MA_30                                                     (0x40000000U << DMA_CMAR_MA_Pos)
1443 #define DMA_CMAR_MA_31                                                     (0x80000000UL << DMA_CMAR_MA_Pos)
1444 
1445 
1446 /* =========================================================================================================================== */
1447 /*=====================                                      DMAMUX                                      ===================== */
1448 /* =========================================================================================================================== */
1449 
1450 /* =====================================================    CxCR    ===================================================== */
1451 #define DMAMUX_CxCR_DMAREQ_ID_Pos                                          (0UL)    /*!<DMAMUX CxCR: DMAREQ_ID (Bit 0) */
1452 #define DMAMUX_CxCR_DMAREQ_ID_Msk                                          (0x1fUL)   /*!< DMAMUX CxCR: DMAREQ_ID (Bitfield-Mask: 0x1f) */
1453 #define DMAMUX_CxCR_DMAREQ_ID                                              DMAMUX_CxCR_DMAREQ_ID_Msk
1454 #define DMAMUX_CxCR_DMAREQ_ID_0                                            (0x1U << DMAMUX_CxCR_DMAREQ_ID_Pos)
1455 #define DMAMUX_CxCR_DMAREQ_ID_1                                            (0x2U << DMAMUX_CxCR_DMAREQ_ID_Pos)
1456 #define DMAMUX_CxCR_DMAREQ_ID_2                                            (0x4U << DMAMUX_CxCR_DMAREQ_ID_Pos)
1457 #define DMAMUX_CxCR_DMAREQ_ID_3                                            (0x8U << DMAMUX_CxCR_DMAREQ_ID_Pos)
1458 #define DMAMUX_CxCR_DMAREQ_ID_4                                            (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos)
1459 
1460 
1461 /* =========================================================================================================================== */
1462 /*=====================                                       CRC                                       ===================== */
1463 /* =========================================================================================================================== */
1464 
1465 /* =====================================================    DR    ===================================================== */
1466 #define CRC_DR_DR_Pos                                                      (0UL)    /*!<CRC DR: DR (Bit 0) */
1467 #define CRC_DR_DR_Msk                                                      (0xffffffffUL)   /*!< CRC DR: DR (Bitfield-Mask: 0xffffffff) */
1468 #define CRC_DR_DR                                                          CRC_DR_DR_Msk
1469 #define CRC_DR_DR_0                                                        (0x1U << CRC_DR_DR_Pos)
1470 #define CRC_DR_DR_1                                                        (0x2U << CRC_DR_DR_Pos)
1471 #define CRC_DR_DR_2                                                        (0x4U << CRC_DR_DR_Pos)
1472 #define CRC_DR_DR_3                                                        (0x8U << CRC_DR_DR_Pos)
1473 #define CRC_DR_DR_4                                                        (0x10U << CRC_DR_DR_Pos)
1474 #define CRC_DR_DR_5                                                        (0x20U << CRC_DR_DR_Pos)
1475 #define CRC_DR_DR_6                                                        (0x40U << CRC_DR_DR_Pos)
1476 #define CRC_DR_DR_7                                                        (0x80U << CRC_DR_DR_Pos)
1477 #define CRC_DR_DR_8                                                        (0x100U << CRC_DR_DR_Pos)
1478 #define CRC_DR_DR_9                                                        (0x200U << CRC_DR_DR_Pos)
1479 #define CRC_DR_DR_10                                                       (0x400U << CRC_DR_DR_Pos)
1480 #define CRC_DR_DR_11                                                       (0x800U << CRC_DR_DR_Pos)
1481 #define CRC_DR_DR_12                                                       (0x1000U << CRC_DR_DR_Pos)
1482 #define CRC_DR_DR_13                                                       (0x2000U << CRC_DR_DR_Pos)
1483 #define CRC_DR_DR_14                                                       (0x4000U << CRC_DR_DR_Pos)
1484 #define CRC_DR_DR_15                                                       (0x8000U << CRC_DR_DR_Pos)
1485 #define CRC_DR_DR_16                                                       (0x10000U << CRC_DR_DR_Pos)
1486 #define CRC_DR_DR_17                                                       (0x20000U << CRC_DR_DR_Pos)
1487 #define CRC_DR_DR_18                                                       (0x40000U << CRC_DR_DR_Pos)
1488 #define CRC_DR_DR_19                                                       (0x80000U << CRC_DR_DR_Pos)
1489 #define CRC_DR_DR_20                                                       (0x100000U << CRC_DR_DR_Pos)
1490 #define CRC_DR_DR_21                                                       (0x200000U << CRC_DR_DR_Pos)
1491 #define CRC_DR_DR_22                                                       (0x400000U << CRC_DR_DR_Pos)
1492 #define CRC_DR_DR_23                                                       (0x800000U << CRC_DR_DR_Pos)
1493 #define CRC_DR_DR_24                                                       (0x1000000U << CRC_DR_DR_Pos)
1494 #define CRC_DR_DR_25                                                       (0x2000000U << CRC_DR_DR_Pos)
1495 #define CRC_DR_DR_26                                                       (0x4000000U << CRC_DR_DR_Pos)
1496 #define CRC_DR_DR_27                                                       (0x8000000U << CRC_DR_DR_Pos)
1497 #define CRC_DR_DR_28                                                       (0x10000000U << CRC_DR_DR_Pos)
1498 #define CRC_DR_DR_29                                                       (0x20000000U << CRC_DR_DR_Pos)
1499 #define CRC_DR_DR_30                                                       (0x40000000U << CRC_DR_DR_Pos)
1500 #define CRC_DR_DR_31                                                       (0x80000000UL << CRC_DR_DR_Pos)
1501 
1502 /* =====================================================    IDR    ===================================================== */
1503 #define CRC_IDR_IDR_Pos                                                    (0UL)    /*!<CRC IDR: IDR (Bit 0) */
1504 #define CRC_IDR_IDR_Msk                                                    (0xffffffffUL)   /*!< CRC IDR: IDR (Bitfield-Mask: 0xffffffff) */
1505 #define CRC_IDR_IDR                                                        CRC_IDR_IDR_Msk
1506 #define CRC_IDR_IDR_0                                                      (0x1U << CRC_IDR_IDR_Pos)
1507 #define CRC_IDR_IDR_1                                                      (0x2U << CRC_IDR_IDR_Pos)
1508 #define CRC_IDR_IDR_2                                                      (0x4U << CRC_IDR_IDR_Pos)
1509 #define CRC_IDR_IDR_3                                                      (0x8U << CRC_IDR_IDR_Pos)
1510 #define CRC_IDR_IDR_4                                                      (0x10U << CRC_IDR_IDR_Pos)
1511 #define CRC_IDR_IDR_5                                                      (0x20U << CRC_IDR_IDR_Pos)
1512 #define CRC_IDR_IDR_6                                                      (0x40U << CRC_IDR_IDR_Pos)
1513 #define CRC_IDR_IDR_7                                                      (0x80U << CRC_IDR_IDR_Pos)
1514 #define CRC_IDR_IDR_8                                                      (0x100U << CRC_IDR_IDR_Pos)
1515 #define CRC_IDR_IDR_9                                                      (0x200U << CRC_IDR_IDR_Pos)
1516 #define CRC_IDR_IDR_10                                                     (0x400U << CRC_IDR_IDR_Pos)
1517 #define CRC_IDR_IDR_11                                                     (0x800U << CRC_IDR_IDR_Pos)
1518 #define CRC_IDR_IDR_12                                                     (0x1000U << CRC_IDR_IDR_Pos)
1519 #define CRC_IDR_IDR_13                                                     (0x2000U << CRC_IDR_IDR_Pos)
1520 #define CRC_IDR_IDR_14                                                     (0x4000U << CRC_IDR_IDR_Pos)
1521 #define CRC_IDR_IDR_15                                                     (0x8000U << CRC_IDR_IDR_Pos)
1522 #define CRC_IDR_IDR_16                                                     (0x10000U << CRC_IDR_IDR_Pos)
1523 #define CRC_IDR_IDR_17                                                     (0x20000U << CRC_IDR_IDR_Pos)
1524 #define CRC_IDR_IDR_18                                                     (0x40000U << CRC_IDR_IDR_Pos)
1525 #define CRC_IDR_IDR_19                                                     (0x80000U << CRC_IDR_IDR_Pos)
1526 #define CRC_IDR_IDR_20                                                     (0x100000U << CRC_IDR_IDR_Pos)
1527 #define CRC_IDR_IDR_21                                                     (0x200000U << CRC_IDR_IDR_Pos)
1528 #define CRC_IDR_IDR_22                                                     (0x400000U << CRC_IDR_IDR_Pos)
1529 #define CRC_IDR_IDR_23                                                     (0x800000U << CRC_IDR_IDR_Pos)
1530 #define CRC_IDR_IDR_24                                                     (0x1000000U << CRC_IDR_IDR_Pos)
1531 #define CRC_IDR_IDR_25                                                     (0x2000000U << CRC_IDR_IDR_Pos)
1532 #define CRC_IDR_IDR_26                                                     (0x4000000U << CRC_IDR_IDR_Pos)
1533 #define CRC_IDR_IDR_27                                                     (0x8000000U << CRC_IDR_IDR_Pos)
1534 #define CRC_IDR_IDR_28                                                     (0x10000000U << CRC_IDR_IDR_Pos)
1535 #define CRC_IDR_IDR_29                                                     (0x20000000U << CRC_IDR_IDR_Pos)
1536 #define CRC_IDR_IDR_30                                                     (0x40000000U << CRC_IDR_IDR_Pos)
1537 #define CRC_IDR_IDR_31                                                     (0x80000000UL << CRC_IDR_IDR_Pos)
1538 
1539 /* =====================================================    CR    ===================================================== */
1540 #define CRC_CR_REV_OUT_Pos                                                 (7UL)    /*!<CRC CR: REV_OUT (Bit 7) */
1541 #define CRC_CR_REV_OUT_Msk                                                 (0x80UL)   /*!< CRC CR: REV_OUT (Bitfield-Mask: 0x01) */
1542 #define CRC_CR_REV_OUT                                                     CRC_CR_REV_OUT_Msk
1543 #define CRC_CR_REV_IN_Pos                                                  (5UL)    /*!<CRC CR: REV_IN (Bit 5) */
1544 #define CRC_CR_REV_IN_Msk                                                  (0x60UL)   /*!< CRC CR: REV_IN (Bitfield-Mask: 0x03) */
1545 #define CRC_CR_REV_IN                                                      CRC_CR_REV_IN_Msk
1546 #define CRC_CR_REV_IN_0                                                    (0x1U << CRC_CR_REV_IN_Pos)
1547 #define CRC_CR_REV_IN_1                                                    (0x2U << CRC_CR_REV_IN_Pos)
1548 #define CRC_CR_POLYSIZE_Pos                                                (3UL)    /*!<CRC CR: POLYSIZE (Bit 3) */
1549 #define CRC_CR_POLYSIZE_Msk                                                (0x18UL)   /*!< CRC CR: POLYSIZE (Bitfield-Mask: 0x03) */
1550 #define CRC_CR_POLYSIZE                                                    CRC_CR_POLYSIZE_Msk
1551 #define CRC_CR_POLYSIZE_0                                                  (0x1U << CRC_CR_POLYSIZE_Pos)
1552 #define CRC_CR_POLYSIZE_1                                                  (0x2U << CRC_CR_POLYSIZE_Pos)
1553 #define CRC_CR_RESET_Pos                                                   (0UL)    /*!<CRC CR: RESET (Bit 0) */
1554 #define CRC_CR_RESET_Msk                                                   (0x1UL)    /*!< CRC CR: RESET (Bitfield-Mask: 0x01) */
1555 #define CRC_CR_RESET                                                       CRC_CR_RESET_Msk
1556 
1557 /* =====================================================    INIT    ===================================================== */
1558 #define CRC_INIT_CRC_INIT_Pos                                              (0UL)    /*!<CRC INIT: CRC_INIT (Bit 0) */
1559 #define CRC_INIT_CRC_INIT_Msk                                              (0xffffffffUL)   /*!< CRC INIT: CRC_INIT (Bitfield-Mask: 0xffffffff) */
1560 #define CRC_INIT_CRC_INIT                                                  CRC_INIT_CRC_INIT_Msk
1561 #define CRC_INIT_CRC_INIT_0                                                (0x1U << CRC_INIT_CRC_INIT_Pos)
1562 #define CRC_INIT_CRC_INIT_1                                                (0x2U << CRC_INIT_CRC_INIT_Pos)
1563 #define CRC_INIT_CRC_INIT_2                                                (0x4U << CRC_INIT_CRC_INIT_Pos)
1564 #define CRC_INIT_CRC_INIT_3                                                (0x8U << CRC_INIT_CRC_INIT_Pos)
1565 #define CRC_INIT_CRC_INIT_4                                                (0x10U << CRC_INIT_CRC_INIT_Pos)
1566 #define CRC_INIT_CRC_INIT_5                                                (0x20U << CRC_INIT_CRC_INIT_Pos)
1567 #define CRC_INIT_CRC_INIT_6                                                (0x40U << CRC_INIT_CRC_INIT_Pos)
1568 #define CRC_INIT_CRC_INIT_7                                                (0x80U << CRC_INIT_CRC_INIT_Pos)
1569 #define CRC_INIT_CRC_INIT_8                                                (0x100U << CRC_INIT_CRC_INIT_Pos)
1570 #define CRC_INIT_CRC_INIT_9                                                (0x200U << CRC_INIT_CRC_INIT_Pos)
1571 #define CRC_INIT_CRC_INIT_10                                               (0x400U << CRC_INIT_CRC_INIT_Pos)
1572 #define CRC_INIT_CRC_INIT_11                                               (0x800U << CRC_INIT_CRC_INIT_Pos)
1573 #define CRC_INIT_CRC_INIT_12                                               (0x1000U << CRC_INIT_CRC_INIT_Pos)
1574 #define CRC_INIT_CRC_INIT_13                                               (0x2000U << CRC_INIT_CRC_INIT_Pos)
1575 #define CRC_INIT_CRC_INIT_14                                               (0x4000U << CRC_INIT_CRC_INIT_Pos)
1576 #define CRC_INIT_CRC_INIT_15                                               (0x8000U << CRC_INIT_CRC_INIT_Pos)
1577 #define CRC_INIT_CRC_INIT_16                                               (0x10000U << CRC_INIT_CRC_INIT_Pos)
1578 #define CRC_INIT_CRC_INIT_17                                               (0x20000U << CRC_INIT_CRC_INIT_Pos)
1579 #define CRC_INIT_CRC_INIT_18                                               (0x40000U << CRC_INIT_CRC_INIT_Pos)
1580 #define CRC_INIT_CRC_INIT_19                                               (0x80000U << CRC_INIT_CRC_INIT_Pos)
1581 #define CRC_INIT_CRC_INIT_20                                               (0x100000U << CRC_INIT_CRC_INIT_Pos)
1582 #define CRC_INIT_CRC_INIT_21                                               (0x200000U << CRC_INIT_CRC_INIT_Pos)
1583 #define CRC_INIT_CRC_INIT_22                                               (0x400000U << CRC_INIT_CRC_INIT_Pos)
1584 #define CRC_INIT_CRC_INIT_23                                               (0x800000U << CRC_INIT_CRC_INIT_Pos)
1585 #define CRC_INIT_CRC_INIT_24                                               (0x1000000U << CRC_INIT_CRC_INIT_Pos)
1586 #define CRC_INIT_CRC_INIT_25                                               (0x2000000U << CRC_INIT_CRC_INIT_Pos)
1587 #define CRC_INIT_CRC_INIT_26                                               (0x4000000U << CRC_INIT_CRC_INIT_Pos)
1588 #define CRC_INIT_CRC_INIT_27                                               (0x8000000U << CRC_INIT_CRC_INIT_Pos)
1589 #define CRC_INIT_CRC_INIT_28                                               (0x10000000U << CRC_INIT_CRC_INIT_Pos)
1590 #define CRC_INIT_CRC_INIT_29                                               (0x20000000U << CRC_INIT_CRC_INIT_Pos)
1591 #define CRC_INIT_CRC_INIT_30                                               (0x40000000U << CRC_INIT_CRC_INIT_Pos)
1592 #define CRC_INIT_CRC_INIT_31                                               (0x80000000UL << CRC_INIT_CRC_INIT_Pos)
1593 
1594 /* =====================================================    POL    ===================================================== */
1595 #define CRC_POL_POL_Pos                                                    (0UL)    /*!<CRC POL: POL (Bit 0) */
1596 #define CRC_POL_POL_Msk                                                    (0xffffffffUL)   /*!< CRC POL: POL (Bitfield-Mask: 0xffffffff) */
1597 #define CRC_POL_POL                                                        CRC_POL_POL_Msk
1598 #define CRC_POL_POL_0                                                      (0x1U << CRC_POL_POL_Pos)
1599 #define CRC_POL_POL_1                                                      (0x2U << CRC_POL_POL_Pos)
1600 #define CRC_POL_POL_2                                                      (0x4U << CRC_POL_POL_Pos)
1601 #define CRC_POL_POL_3                                                      (0x8U << CRC_POL_POL_Pos)
1602 #define CRC_POL_POL_4                                                      (0x10U << CRC_POL_POL_Pos)
1603 #define CRC_POL_POL_5                                                      (0x20U << CRC_POL_POL_Pos)
1604 #define CRC_POL_POL_6                                                      (0x40U << CRC_POL_POL_Pos)
1605 #define CRC_POL_POL_7                                                      (0x80U << CRC_POL_POL_Pos)
1606 #define CRC_POL_POL_8                                                      (0x100U << CRC_POL_POL_Pos)
1607 #define CRC_POL_POL_9                                                      (0x200U << CRC_POL_POL_Pos)
1608 #define CRC_POL_POL_10                                                     (0x400U << CRC_POL_POL_Pos)
1609 #define CRC_POL_POL_11                                                     (0x800U << CRC_POL_POL_Pos)
1610 #define CRC_POL_POL_12                                                     (0x1000U << CRC_POL_POL_Pos)
1611 #define CRC_POL_POL_13                                                     (0x2000U << CRC_POL_POL_Pos)
1612 #define CRC_POL_POL_14                                                     (0x4000U << CRC_POL_POL_Pos)
1613 #define CRC_POL_POL_15                                                     (0x8000U << CRC_POL_POL_Pos)
1614 #define CRC_POL_POL_16                                                     (0x10000U << CRC_POL_POL_Pos)
1615 #define CRC_POL_POL_17                                                     (0x20000U << CRC_POL_POL_Pos)
1616 #define CRC_POL_POL_18                                                     (0x40000U << CRC_POL_POL_Pos)
1617 #define CRC_POL_POL_19                                                     (0x80000U << CRC_POL_POL_Pos)
1618 #define CRC_POL_POL_20                                                     (0x100000U << CRC_POL_POL_Pos)
1619 #define CRC_POL_POL_21                                                     (0x200000U << CRC_POL_POL_Pos)
1620 #define CRC_POL_POL_22                                                     (0x400000U << CRC_POL_POL_Pos)
1621 #define CRC_POL_POL_23                                                     (0x800000U << CRC_POL_POL_Pos)
1622 #define CRC_POL_POL_24                                                     (0x1000000U << CRC_POL_POL_Pos)
1623 #define CRC_POL_POL_25                                                     (0x2000000U << CRC_POL_POL_Pos)
1624 #define CRC_POL_POL_26                                                     (0x4000000U << CRC_POL_POL_Pos)
1625 #define CRC_POL_POL_27                                                     (0x8000000U << CRC_POL_POL_Pos)
1626 #define CRC_POL_POL_28                                                     (0x10000000U << CRC_POL_POL_Pos)
1627 #define CRC_POL_POL_29                                                     (0x20000000U << CRC_POL_POL_Pos)
1628 #define CRC_POL_POL_30                                                     (0x40000000U << CRC_POL_POL_Pos)
1629 #define CRC_POL_POL_31                                                     (0x80000000UL << CRC_POL_POL_Pos)
1630 
1631 
1632 /* =========================================================================================================================== */
1633 /* ================                                           IWDG                                            ================ */
1634 /* =========================================================================================================================== */
1635 
1636 /* ==========================================================  KR  =========================================================== */
1637 #define IWDG_KR_KEY_Pos                   (0UL)                     /*!< IWDG KR: KEY (Bit 0)                                  */
1638 #define IWDG_KR_KEY_Msk                   (0xffffUL)                /*!< IWDG KR: KEY (Bitfield-Mask: 0xffff)                  */
1639 #define IWDG_KR_KEY                       IWDG_KR_KEY_Msk
1640 #define IWDG_KR_KEY_0                     (0x1U << IWDG_KR_KEY_Pos)
1641 #define IWDG_KR_KEY_1                     (0x2U << IWDG_KR_KEY_Pos)
1642 #define IWDG_KR_KEY_2                     (0x4U << IWDG_KR_KEY_Pos)
1643 #define IWDG_KR_KEY_3                     (0x8U << IWDG_KR_KEY_Pos)
1644 #define IWDG_KR_KEY_4                     (0x10U << IWDG_KR_KEY_Pos)
1645 #define IWDG_KR_KEY_5                     (0x20U << IWDG_KR_KEY_Pos)
1646 #define IWDG_KR_KEY_6                     (0x40U << IWDG_KR_KEY_Pos)
1647 #define IWDG_KR_KEY_7                     (0x80U << IWDG_KR_KEY_Pos)
1648 #define IWDG_KR_KEY_8                     (0x100U << IWDG_KR_KEY_Pos)
1649 #define IWDG_KR_KEY_9                     (0x200U << IWDG_KR_KEY_Pos)
1650 #define IWDG_KR_KEY_10                    (0x400U << IWDG_KR_KEY_Pos)
1651 #define IWDG_KR_KEY_11                    (0x800U << IWDG_KR_KEY_Pos)
1652 #define IWDG_KR_KEY_12                    (0x1000U << IWDG_KR_KEY_Pos)
1653 #define IWDG_KR_KEY_13                    (0x2000U << IWDG_KR_KEY_Pos)
1654 #define IWDG_KR_KEY_14                    (0x4000U << IWDG_KR_KEY_Pos)
1655 #define IWDG_KR_KEY_15                    (0x8000U << IWDG_KR_KEY_Pos)
1656 
1657 /* ==========================================================  PR  =========================================================== */
1658 #define IWDG_PR_PR_Pos                    (0UL)                     /*!< IWDG PR: PR (Bit 0)                                   */
1659 #define IWDG_PR_PR_Msk                    (0x7UL)                   /*!< IWDG PR: PR (Bitfield-Mask: 0x07)                     */
1660 #define IWDG_PR_PR                        IWDG_PR_PR_Msk
1661 #define IWDG_PR_PR_0                      (0x1U << IWDG_PR_PR_Pos)
1662 #define IWDG_PR_PR_1                      (0x2U << IWDG_PR_PR_Pos)
1663 #define IWDG_PR_PR_2                      (0x4U << IWDG_PR_PR_Pos)
1664 
1665 /* ==========================================================  RLR  ========================================================== */
1666 #define IWDG_RLR_RL_Pos                   (0UL)                     /*!< IWDG RLR: RL (Bit 0)                                  */
1667 #define IWDG_RLR_RL_Msk                   (0xfffUL)                 /*!< IWDG RLR: RL (Bitfield-Mask: 0xfff)                   */
1668 #define IWDG_RLR_RL                       IWDG_RLR_RL_Msk
1669 #define IWDG_RLR_RL_0                     (0x1U << IWDG_RLR_RL_Pos)
1670 #define IWDG_RLR_RL_1                     (0x2U << IWDG_RLR_RL_Pos)
1671 #define IWDG_RLR_RL_2                     (0x4U << IWDG_RLR_RL_Pos)
1672 #define IWDG_RLR_RL_3                     (0x8U << IWDG_RLR_RL_Pos)
1673 #define IWDG_RLR_RL_4                     (0x10U << IWDG_RLR_RL_Pos)
1674 #define IWDG_RLR_RL_5                     (0x20U << IWDG_RLR_RL_Pos)
1675 #define IWDG_RLR_RL_6                     (0x40U << IWDG_RLR_RL_Pos)
1676 #define IWDG_RLR_RL_7                     (0x80U << IWDG_RLR_RL_Pos)
1677 #define IWDG_RLR_RL_8                     (0x100U << IWDG_RLR_RL_Pos)
1678 #define IWDG_RLR_RL_9                     (0x200U << IWDG_RLR_RL_Pos)
1679 #define IWDG_RLR_RL_10                    (0x400U << IWDG_RLR_RL_Pos)
1680 #define IWDG_RLR_RL_11                    (0x800U << IWDG_RLR_RL_Pos)
1681 
1682 /* ==========================================================  SR  =========================================================== */
1683 #define IWDG_SR_WVU_Pos                   (2UL)                     /*!< IWDG SR: WVU (Bit 2)                                  */
1684 #define IWDG_SR_WVU_Msk                   (0x4UL)                   /*!< IWDG SR: WVU (Bitfield-Mask: 0x01)                    */
1685 #define IWDG_SR_WVU                       IWDG_SR_WVU_Msk
1686 #define IWDG_SR_RVU_Pos                   (1UL)                     /*!< IWDG SR: RVU (Bit 1)                                  */
1687 #define IWDG_SR_RVU_Msk                   (0x2UL)                   /*!< IWDG SR: RVU (Bitfield-Mask: 0x01)                    */
1688 #define IWDG_SR_RVU                       IWDG_SR_RVU_Msk
1689 #define IWDG_SR_PVU_Pos                   (0UL)                     /*!< IWDG SR: PVU (Bit 0)                                  */
1690 #define IWDG_SR_PVU_Msk                   (0x1UL)                   /*!< IWDG SR: PVU (Bitfield-Mask: 0x01)                    */
1691 #define IWDG_SR_PVU                       IWDG_SR_PVU_Msk
1692 
1693 /* =========================================================  WINR  ========================================================== */
1694 #define IWDG_WINR_WIN_Pos                 (0UL)                     /*!< IWDG WINR: WIN (Bit 0)                                */
1695 #define IWDG_WINR_WIN_Msk                 (0xfffUL)                 /*!< IWDG WINR: WIN (Bitfield-Mask: 0xfff)                 */
1696 #define IWDG_WINR_WIN                     IWDG_WINR_WIN_Msk
1697 #define IWDG_WINR_WIN_0                   (0x1U << IWDG_WINR_WIN_Pos)
1698 #define IWDG_WINR_WIN_1                   (0x2U << IWDG_WINR_WIN_Pos)
1699 #define IWDG_WINR_WIN_2                   (0x4U << IWDG_WINR_WIN_Pos)
1700 #define IWDG_WINR_WIN_3                   (0x8U << IWDG_WINR_WIN_Pos)
1701 #define IWDG_WINR_WIN_4                   (0x10U << IWDG_WINR_WIN_Pos)
1702 #define IWDG_WINR_WIN_5                   (0x20U << IWDG_WINR_WIN_Pos)
1703 #define IWDG_WINR_WIN_6                   (0x40U << IWDG_WINR_WIN_Pos)
1704 #define IWDG_WINR_WIN_7                   (0x80U << IWDG_WINR_WIN_Pos)
1705 #define IWDG_WINR_WIN_8                   (0x100U << IWDG_WINR_WIN_Pos)
1706 #define IWDG_WINR_WIN_9                   (0x200U << IWDG_WINR_WIN_Pos)
1707 #define IWDG_WINR_WIN_10                  (0x400U << IWDG_WINR_WIN_Pos)
1708 #define IWDG_WINR_WIN_11                  (0x800U << IWDG_WINR_WIN_Pos)
1709 
1710 
1711 /* =========================================================================================================================== */
1712 /*=====================                                       I2C                                       ===================== */
1713 /* =========================================================================================================================== */
1714 
1715 /* =====================================================    CR1    ===================================================== */
1716 #define I2C_CR1_PECEN_Pos                                                  (23UL)                             /*!<I2C CR1: PECEN (Bit 23) */
1717 #define I2C_CR1_PECEN_Msk                                                  (0x1UL << I2C_CR1_PECEN_Pos)       /*!< I2C CR1: PECEN (Bitfield-Mask: 0x01) */
1718 #define I2C_CR1_PECEN                                                      I2C_CR1_PECEN_Msk
1719 #define I2C_CR1_ALERTEN_Pos                                                (22UL)                             /*!<I2C CR1: ALERTEN (Bit 22) */
1720 #define I2C_CR1_ALERTEN_Msk                                                (0x1UL << I2C_CR1_ALERTEN_Pos)     /*!< I2C CR1: ALERTEN (Bitfield-Mask: 0x01) */
1721 #define I2C_CR1_ALERTEN                                                    I2C_CR1_ALERTEN_Msk
1722 #define I2C_CR1_SMBDEN_Pos                                                 (21UL)                             /*!<I2C CR1: SMBDEN (Bit 21) */
1723 #define I2C_CR1_SMBDEN_Msk                                                 (0x1UL << I2C_CR1_SMBDEN_Pos)      /*!< I2C CR1: SMBDEN (Bitfield-Mask: 0x01) */
1724 #define I2C_CR1_SMBDEN                                                     I2C_CR1_SMBDEN_Msk
1725 #define I2C_CR1_SMBHEN_Pos                                                 (20UL)                             /*!<I2C CR1: SMBHEN (Bit 20) */
1726 #define I2C_CR1_SMBHEN_Msk                                                 (0x1UL << I2C_CR1_SMBHEN_Pos)      /*!< I2C CR1: SMBHEN (Bitfield-Mask: 0x01) */
1727 #define I2C_CR1_SMBHEN                                                     I2C_CR1_SMBHEN_Msk
1728 #define I2C_CR1_GCEN_Pos                                                   (19UL)                             /*!<I2C CR1: GCEN (Bit 19) */
1729 #define I2C_CR1_GCEN_Msk                                                   (0x1UL << I2C_CR1_GCEN_Pos)        /*!< I2C CR1: GCEN (Bitfield-Mask: 0x01) */
1730 #define I2C_CR1_GCEN                                                       I2C_CR1_GCEN_Msk
1731 #define I2C_CR1_NOSTRETCH_Pos                                              (17UL)                             /*!<I2C CR1: NOSTRETCH (Bit 17) */
1732 #define I2C_CR1_NOSTRETCH_Msk                                              (0x1UL << I2C_CR1_NOSTRETCH_Pos)   /*!< I2C CR1: NOSTRETCH (Bitfield-Mask: 0x01) */
1733 #define I2C_CR1_NOSTRETCH                                                  I2C_CR1_NOSTRETCH_Msk
1734 #define I2C_CR1_SBC_Pos                                                    (16UL)                             /*!<I2C CR1: SBC (Bit 16) */
1735 #define I2C_CR1_SBC_Msk                                                    (0x1UL << I2C_CR1_SBC_Pos)         /*!< I2C CR1: SBC (Bitfield-Mask: 0x01) */
1736 #define I2C_CR1_SBC                                                        I2C_CR1_SBC_Msk
1737 #define I2C_CR1_RXDMAEN_Pos                                                (15UL)                             /*!<I2C CR1: RXDMAEN (Bit 15) */
1738 #define I2C_CR1_RXDMAEN_Msk                                                (0x1UL << I2C_CR1_RXDMAEN_Pos)     /*!< I2C CR1: RXDMAEN (Bitfield-Mask: 0x01) */
1739 #define I2C_CR1_RXDMAEN                                                    I2C_CR1_RXDMAEN_Msk
1740 #define I2C_CR1_TXDMAEN_Pos                                                (14UL)                             /*!<I2C CR1: TXDMAEN (Bit 14) */
1741 #define I2C_CR1_TXDMAEN_Msk                                                (0x1UL << I2C_CR1_TXDMAEN_Pos)     /*!< I2C CR1: TXDMAEN (Bitfield-Mask: 0x01) */
1742 #define I2C_CR1_TXDMAEN                                                    I2C_CR1_TXDMAEN_Msk
1743 #define I2C_CR1_ANFOFF_Pos                                                 (12UL)                             /*!<I2C CR1: ANFOFF (Bit 12) */
1744 #define I2C_CR1_ANFOFF_Msk                                                 (0x1UL << I2C_CR1_ANFOFF_Pos)      /*!< I2C CR1: ANFOFF (Bitfield-Mask: 0x01) */
1745 #define I2C_CR1_ANFOFF                                                     I2C_CR1_ANFOFF_Msk
1746 #define I2C_CR1_DNF_Pos                                                    (8UL)                              /*!<I2C CR1: DNF (Bit 8) */
1747 #define I2C_CR1_DNF_Msk                                                    (0xFUL << I2C_CR1_DNF_Pos)         /*!< I2C CR1: DNF (Bitfield-Mask: 0x0f) */
1748 #define I2C_CR1_DNF                                                        I2C_CR1_DNF_Msk
1749 #define I2C_CR1_DNF_0                                                      (0x1U << I2C_CR1_DNF_Pos)
1750 #define I2C_CR1_DNF_1                                                      (0x2U << I2C_CR1_DNF_Pos)
1751 #define I2C_CR1_DNF_2                                                      (0x4U << I2C_CR1_DNF_Pos)
1752 #define I2C_CR1_DNF_3                                                      (0x8U << I2C_CR1_DNF_Pos)
1753 #define I2C_CR1_ERRIE_Pos                                                  (7UL)                              /*!<I2C CR1: ERRIE (Bit 7) */
1754 #define I2C_CR1_ERRIE_Msk                                                  (0x1UL << I2C_CR1_ERRIE_Pos)       /*!< I2C CR1: ERRIE (Bitfield-Mask: 0x01) */
1755 #define I2C_CR1_ERRIE                                                      I2C_CR1_ERRIE_Msk
1756 #define I2C_CR1_TCIE_Pos                                                   (6UL)                              /*!<I2C CR1: TCIE (Bit 6) */
1757 #define I2C_CR1_TCIE_Msk                                                   (0x1UL << I2C_CR1_TCIE_Pos)        /*!< I2C CR1: TCIE (Bitfield-Mask: 0x01) */
1758 #define I2C_CR1_TCIE                                                       I2C_CR1_TCIE_Msk
1759 #define I2C_CR1_STOPIE_Pos                                                 (5UL)                              /*!<I2C CR1: STOPIE (Bit 5) */
1760 #define I2C_CR1_STOPIE_Msk                                                 (0x1UL << I2C_CR1_STOPIE_Pos)      /*!< I2C CR1: STOPIE (Bitfield-Mask: 0x01) */
1761 #define I2C_CR1_STOPIE                                                     I2C_CR1_STOPIE_Msk
1762 #define I2C_CR1_NACKIE_Pos                                                 (4UL)                              /*!<I2C CR1: NACKIE (Bit 4) */
1763 #define I2C_CR1_NACKIE_Msk                                                 (0x1UL << I2C_CR1_NACKIE_Pos)      /*!< I2C CR1: NACKIE (Bitfield-Mask: 0x01) */
1764 #define I2C_CR1_NACKIE                                                     I2C_CR1_NACKIE_Msk
1765 #define I2C_CR1_ADDRIE_Pos                                                 (3UL)                              /*!<I2C CR1: ADDRIE (Bit 3) */
1766 #define I2C_CR1_ADDRIE_Msk                                                 (0x1UL << I2C_CR1_ADDRIE_Pos)      /*!< I2C CR1: ADDRIE (Bitfield-Mask: 0x01) */
1767 #define I2C_CR1_ADDRIE                                                     I2C_CR1_ADDRIE_Msk
1768 #define I2C_CR1_RXIE_Pos                                                   (2UL)                              /*!<I2C CR1: RXIE (Bit 2) */
1769 #define I2C_CR1_RXIE_Msk                                                   (0x1UL << I2C_CR1_RXIE_Pos)        /*!< I2C CR1: RXIE (Bitfield-Mask: 0x01) */
1770 #define I2C_CR1_RXIE                                                       I2C_CR1_RXIE_Msk
1771 #define I2C_CR1_TXIE_Pos                                                   (1UL)                              /*!<I2C CR1: TXIE (Bit 1) */
1772 #define I2C_CR1_TXIE_Msk                                                   (0x1UL << I2C_CR1_TXIE_Pos)        /*!< I2C CR1: TXIE (Bitfield-Mask: 0x01) */
1773 #define I2C_CR1_TXIE                                                       I2C_CR1_TXIE_Msk
1774 #define I2C_CR1_PE_Pos                                                     (0UL)                              /*!<I2C CR1: PE (Bit 0) */
1775 #define I2C_CR1_PE_Msk                                                     (0x1UL << I2C_CR1_PE_Pos)          /*!< I2C CR1: PE (Bitfield-Mask: 0x01) */
1776 #define I2C_CR1_PE                                                         I2C_CR1_PE_Msk
1777 
1778 /* =====================================================    CR2    ===================================================== */
1779 #define I2C_CR2_PECBYTE_Pos                                                (26UL)                             /*!<I2C CR2: PECBYTE (Bit 26) */
1780 #define I2C_CR2_PECBYTE_Msk                                                (0x1UL << I2C_CR2_PECBYTE_Pos)     /*!< I2C CR2: PECBYTE (Bitfield-Mask: 0x01) */
1781 #define I2C_CR2_PECBYTE                                                    I2C_CR2_PECBYTE_Msk
1782 #define I2C_CR2_AUTOEND_Pos                                                (25UL)                             /*!<I2C CR2: AUTOEND (Bit 25) */
1783 #define I2C_CR2_AUTOEND_Msk                                                (0x1UL << I2C_CR2_AUTOEND_Pos)     /*!< I2C CR2: AUTOEND (Bitfield-Mask: 0x01) */
1784 #define I2C_CR2_AUTOEND                                                    I2C_CR2_AUTOEND_Msk
1785 #define I2C_CR2_RELOAD_Pos                                                 (24UL)                             /*!<I2C CR2: RELOAD (Bit 24) */
1786 #define I2C_CR2_RELOAD_Msk                                                 (0x1UL << I2C_CR2_RELOAD_Pos)      /*!< I2C CR2: RELOAD (Bitfield-Mask: 0x01) */
1787 #define I2C_CR2_RELOAD                                                     I2C_CR2_RELOAD_Msk
1788 #define I2C_CR2_NBYTES_Pos                                                 (16UL)                             /*!<I2C CR2: NBYTES (Bit 16) */
1789 #define I2C_CR2_NBYTES_Msk                                                 (0xFFUL << I2C_CR2_NBYTES_Pos)     /*!< I2C CR2: NBYTES (Bitfield-Mask: 0xff) */
1790 #define I2C_CR2_NBYTES                                                     I2C_CR2_NBYTES_Msk
1791 #define I2C_CR2_NBYTES_0                                                   (0x1U << I2C_CR2_NBYTES_Pos)
1792 #define I2C_CR2_NBYTES_1                                                   (0x2U << I2C_CR2_NBYTES_Pos)
1793 #define I2C_CR2_NBYTES_2                                                   (0x4U << I2C_CR2_NBYTES_Pos)
1794 #define I2C_CR2_NBYTES_3                                                   (0x8U << I2C_CR2_NBYTES_Pos)
1795 #define I2C_CR2_NBYTES_4                                                   (0x10U << I2C_CR2_NBYTES_Pos)
1796 #define I2C_CR2_NBYTES_5                                                   (0x20U << I2C_CR2_NBYTES_Pos)
1797 #define I2C_CR2_NBYTES_6                                                   (0x40U << I2C_CR2_NBYTES_Pos)
1798 #define I2C_CR2_NBYTES_7                                                   (0x80U << I2C_CR2_NBYTES_Pos)
1799 #define I2C_CR2_NACK_Pos                                                   (15UL)                             /*!<I2C CR2: NACK (Bit 15) */
1800 #define I2C_CR2_NACK_Msk                                                   (0x1UL << I2C_CR2_NACK_Pos)        /*!< I2C CR2: NACK (Bitfield-Mask: 0x01) */
1801 #define I2C_CR2_NACK                                                       I2C_CR2_NACK_Msk
1802 #define I2C_CR2_STOP_Pos                                                   (14UL)                             /*!<I2C CR2: STOP (Bit 14) */
1803 #define I2C_CR2_STOP_Msk                                                   (0x1UL << I2C_CR2_STOP_Pos)        /*!< I2C CR2: STOP (Bitfield-Mask: 0x01) */
1804 #define I2C_CR2_STOP                                                       I2C_CR2_STOP_Msk
1805 #define I2C_CR2_START_Pos                                                  (13UL)                             /*!<I2C CR2: START (Bit 13) */
1806 #define I2C_CR2_START_Msk                                                  (0x1UL << I2C_CR2_START_Pos)       /*!< I2C CR2: START (Bitfield-Mask: 0x01) */
1807 #define I2C_CR2_START                                                      I2C_CR2_START_Msk
1808 #define I2C_CR2_HEAD10R_Pos                                                (12UL)                             /*!<I2C CR2: HEAD10R (Bit 12) */
1809 #define I2C_CR2_HEAD10R_Msk                                                (0x1UL << I2C_CR2_HEAD10R_Pos)     /*!< I2C CR2: HEAD10R (Bitfield-Mask: 0x01) */
1810 #define I2C_CR2_HEAD10R                                                    I2C_CR2_HEAD10R_Msk
1811 #define I2C_CR2_ADD10_Pos                                                  (11UL)                             /*!<I2C CR2: ADD10 (Bit 11) */
1812 #define I2C_CR2_ADD10_Msk                                                  (0x1UL << I2C_CR2_ADD10_Pos)       /*!< I2C CR2: ADD10 (Bitfield-Mask: 0x01) */
1813 #define I2C_CR2_ADD10                                                      I2C_CR2_ADD10_Msk
1814 #define I2C_CR2_RD_WRN_Pos                                                 (10UL)                             /*!<I2C CR2: RD_WRN (Bit 10) */
1815 #define I2C_CR2_RD_WRN_Msk                                                 (0x1UL << I2C_CR2_RD_WRN_Pos)      /*!< I2C CR2: RD_WRN (Bitfield-Mask: 0x01) */
1816 #define I2C_CR2_RD_WRN                                                     I2C_CR2_RD_WRN_Msk
1817 #define I2C_CR2_SADD_Pos                                                   (0UL)                              /*!<I2C CR2: SADD (Bit 0) */
1818 #define I2C_CR2_SADD_Msk                                                   (0x3FFUL << I2C_CR2_SADD_Pos)      /*!< I2C CR2: SADD (Bitfield-Mask: 0x3ff) */
1819 #define I2C_CR2_SADD                                                       I2C_CR2_SADD_Msk
1820 #define I2C_CR2_SADD_0                                                     (0x1U << I2C_CR2_SADD_Pos)
1821 #define I2C_CR2_SADD_1                                                     (0x2U << I2C_CR2_SADD_Pos)
1822 #define I2C_CR2_SADD_2                                                     (0x4U << I2C_CR2_SADD_Pos)
1823 #define I2C_CR2_SADD_3                                                     (0x8U << I2C_CR2_SADD_Pos)
1824 #define I2C_CR2_SADD_4                                                     (0x10U << I2C_CR2_SADD_Pos)
1825 #define I2C_CR2_SADD_5                                                     (0x20U << I2C_CR2_SADD_Pos)
1826 #define I2C_CR2_SADD_6                                                     (0x40U << I2C_CR2_SADD_Pos)
1827 #define I2C_CR2_SADD_7                                                     (0x80U << I2C_CR2_SADD_Pos)
1828 #define I2C_CR2_SADD_8                                                     (0x100U << I2C_CR2_SADD_Pos)
1829 #define I2C_CR2_SADD_9                                                     (0x200U << I2C_CR2_SADD_Pos)
1830 
1831 /* =====================================================    OAR1    ===================================================== */
1832 #define I2C_OAR1_OA1EN_Pos                                                 (15UL)                             /*!<I2C OAR1: OA1EN (Bit 15) */
1833 #define I2C_OAR1_OA1EN_Msk                                                 (0x1UL << I2C_OAR1_OA1EN_Pos)      /*!< I2C OAR1: OA1EN (Bitfield-Mask: 0x01) */
1834 #define I2C_OAR1_OA1EN                                                     I2C_OAR1_OA1EN_Msk
1835 #define I2C_OAR1_OA1MODE_Pos                                               (10UL)                             /*!<I2C OAR1: OA1MODE (Bit 10) */
1836 #define I2C_OAR1_OA1MODE_Msk                                               (0x1UL << I2C_OAR1_OA1MODE_Pos)    /*!< I2C OAR1: OA1MODE (Bitfield-Mask: 0x01) */
1837 #define I2C_OAR1_OA1MODE                                                   I2C_OAR1_OA1MODE_Msk
1838 #define I2C_OAR1_OA1_Pos                                                   (0UL)                              /*!<I2C OAR1: OA1 (Bit 0) */
1839 #define I2C_OAR1_OA1_Msk                                                   (0x3FFUL << I2C_OAR1_OA1_Pos)      /*!< I2C OAR1: OA1 (Bitfield-Mask: 0x3ff) */
1840 #define I2C_OAR1_OA1                                                       I2C_OAR1_OA1_Msk
1841 #define I2C_OAR1_OA1_0                                                     (0x1U << I2C_OAR1_OA1_Pos)
1842 #define I2C_OAR1_OA1_1                                                     (0x2U << I2C_OAR1_OA1_Pos)
1843 #define I2C_OAR1_OA1_2                                                     (0x4U << I2C_OAR1_OA1_Pos)
1844 #define I2C_OAR1_OA1_3                                                     (0x8U << I2C_OAR1_OA1_Pos)
1845 #define I2C_OAR1_OA1_4                                                     (0x10U << I2C_OAR1_OA1_Pos)
1846 #define I2C_OAR1_OA1_5                                                     (0x20U << I2C_OAR1_OA1_Pos)
1847 #define I2C_OAR1_OA1_6                                                     (0x40U << I2C_OAR1_OA1_Pos)
1848 #define I2C_OAR1_OA1_7                                                     (0x80U << I2C_OAR1_OA1_Pos)
1849 #define I2C_OAR1_OA1_8                                                     (0x100U << I2C_OAR1_OA1_Pos)
1850 #define I2C_OAR1_OA1_9                                                     (0x200U << I2C_OAR1_OA1_Pos)
1851 
1852 /* =====================================================    OAR2    ===================================================== */
1853 #define I2C_OAR2_OA2EN_Pos                                                 (15UL)                             /*!<I2C OAR2: OA2EN (Bit 15) */
1854 #define I2C_OAR2_OA2EN_Msk                                                 (0x1UL << I2C_OAR2_OA2EN_Pos)      /*!< I2C OAR2: OA2EN (Bitfield-Mask: 0x01) */
1855 #define I2C_OAR2_OA2EN                                                     I2C_OAR2_OA2EN_Msk
1856 #define I2C_OAR2_OA2MSK_Pos                                                (8UL)                              /*!<I2C OAR2: OA2MSK (Bit 8) */
1857 #define I2C_OAR2_OA2MSK_Msk                                                (0x7UL << I2C_OAR2_OA2MSK_Pos)     /*!< I2C OAR2: OA2MSK (Bitfield-Mask: 0x07) */
1858 #define I2C_OAR2_OA2MSK                                                    I2C_OAR2_OA2MSK_Msk
1859 #define I2C_OAR2_OA2NOMASK                                                 (0x00000000UL)                     /*!< No mask                                        */
1860 #define I2C_OAR2_OA2MASK01_Pos                                             (8U)
1861 #define I2C_OAR2_OA2MASK01_Msk                                             (0x1UL << I2C_OAR2_OA2MASK01_Pos)  /*!< 0x00000100 */
1862 #define I2C_OAR2_OA2MASK01                                                 I2C_OAR2_OA2MASK01_Msk             /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
1863 #define I2C_OAR2_OA2MASK02_Pos                                             (9U)
1864 #define I2C_OAR2_OA2MASK02_Msk                                             (0x1UL << I2C_OAR2_OA2MASK02_Pos)  /*!< 0x00000200 */
1865 #define I2C_OAR2_OA2MASK02                                                 I2C_OAR2_OA2MASK02_Msk             /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
1866 #define I2C_OAR2_OA2MASK03_Pos                                             (8U)
1867 #define I2C_OAR2_OA2MASK03_Msk                                             (0x3UL << I2C_OAR2_OA2MASK03_Pos)  /*!< 0x00000300 */
1868 #define I2C_OAR2_OA2MASK03                                                 I2C_OAR2_OA2MASK03_Msk             /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
1869 #define I2C_OAR2_OA2MASK04_Pos                                             (10U)
1870 #define I2C_OAR2_OA2MASK04_Msk                                             (0x1UL << I2C_OAR2_OA2MASK04_Pos)  /*!< 0x00000400 */
1871 #define I2C_OAR2_OA2MASK04                                                 I2C_OAR2_OA2MASK04_Msk             /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
1872 #define I2C_OAR2_OA2MASK05_Pos                                             (8U)
1873 #define I2C_OAR2_OA2MASK05_Msk                                             (0x5UL << I2C_OAR2_OA2MASK05_Pos)  /*!< 0x00000500 */
1874 #define I2C_OAR2_OA2MASK05                                                 I2C_OAR2_OA2MASK05_Msk             /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
1875 #define I2C_OAR2_OA2MASK06_Pos                                             (9U)
1876 #define I2C_OAR2_OA2MASK06_Msk                                             (0x3UL << I2C_OAR2_OA2MASK06_Pos)  /*!< 0x00000600 */
1877 #define I2C_OAR2_OA2MASK06                                                 I2C_OAR2_OA2MASK06_Msk             /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
1878 #define I2C_OAR2_OA2MASK07_Pos                                             (8U)
1879 #define I2C_OAR2_OA2MASK07_Msk                                             (0x7UL << I2C_OAR2_OA2MASK07_Pos)  /*!< 0x00000700 */
1880 #define I2C_OAR2_OA2MASK07                                                 I2C_OAR2_OA2MASK07_Msk             /*!< OA2[7:1] is masked, No comparison is done      */
1881 #define I2C_OAR2_OA2_Pos                                                   (1UL)                              /*!<I2C OAR2: OA2 (Bit 1) */
1882 #define I2C_OAR2_OA2_Msk                                                   (0x7FUL << I2C_OAR2_OA2_Pos)       /*!< I2C OAR2: OA2 (Bitfield-Mask: 0x7f) */
1883 #define I2C_OAR2_OA2                                                       I2C_OAR2_OA2_Msk
1884 #define I2C_OAR2_OA2_0                                                     (0x1U << I2C_OAR2_OA2_Pos)
1885 #define I2C_OAR2_OA2_1                                                     (0x2U << I2C_OAR2_OA2_Pos)
1886 #define I2C_OAR2_OA2_2                                                     (0x4U << I2C_OAR2_OA2_Pos)
1887 #define I2C_OAR2_OA2_3                                                     (0x8U << I2C_OAR2_OA2_Pos)
1888 #define I2C_OAR2_OA2_4                                                     (0x10U << I2C_OAR2_OA2_Pos)
1889 #define I2C_OAR2_OA2_5                                                     (0x20U << I2C_OAR2_OA2_Pos)
1890 #define I2C_OAR2_OA2_6                                                     (0x40U << I2C_OAR2_OA2_Pos)
1891 
1892 /* =====================================================    TIMINGR    ===================================================== */
1893 #define I2C_TIMINGR_PRESC_Pos                                              (28UL)                             /*!<I2C TIMINGR: PRESC (Bit 28) */
1894 #define I2C_TIMINGR_PRESC_Msk                                              (0xFUL << I2C_TIMINGR_PRESC_Pos)   /*!< I2C TIMINGR: PRESC (Bitfield-Mask: 0x0f) */
1895 #define I2C_TIMINGR_PRESC                                                  I2C_TIMINGR_PRESC_Msk
1896 #define I2C_TIMINGR_PRESC_0                                                (0x1U << I2C_TIMINGR_PRESC_Pos)
1897 #define I2C_TIMINGR_PRESC_1                                                (0x2U << I2C_TIMINGR_PRESC_Pos)
1898 #define I2C_TIMINGR_PRESC_2                                                (0x4U << I2C_TIMINGR_PRESC_Pos)
1899 #define I2C_TIMINGR_PRESC_3                                                (0x8U << I2C_TIMINGR_PRESC_Pos)
1900 #define I2C_TIMINGR_SCLDEL_Pos                                             (20UL)                             /*!<I2C TIMINGR: SCLDEL (Bit 20) */
1901 #define I2C_TIMINGR_SCLDEL_Msk                                             (0xFUL << I2C_TIMINGR_SCLDEL_Pos)  /*!< I2C TIMINGR: SCLDEL (Bitfield-Mask: 0x0f) */
1902 #define I2C_TIMINGR_SCLDEL                                                 I2C_TIMINGR_SCLDEL_Msk
1903 #define I2C_TIMINGR_SCLDEL_0                                               (0x1U << I2C_TIMINGR_SCLDEL_Pos)
1904 #define I2C_TIMINGR_SCLDEL_1                                               (0x2U << I2C_TIMINGR_SCLDEL_Pos)
1905 #define I2C_TIMINGR_SCLDEL_2                                               (0x4U << I2C_TIMINGR_SCLDEL_Pos)
1906 #define I2C_TIMINGR_SCLDEL_3                                               (0x8U << I2C_TIMINGR_SCLDEL_Pos)
1907 #define I2C_TIMINGR_SDADEL_Pos                                             (16UL)                             /*!<I2C TIMINGR: SDADEL (Bit 16) */
1908 #define I2C_TIMINGR_SDADEL_Msk                                             (0xFUL << I2C_TIMINGR_SDADEL_Pos)  /*!< I2C TIMINGR: SDADEL (Bitfield-Mask: 0x0f) */
1909 #define I2C_TIMINGR_SDADEL                                                 I2C_TIMINGR_SDADEL_Msk
1910 #define I2C_TIMINGR_SDADEL_0                                               (0x1U << I2C_TIMINGR_SDADEL_Pos)
1911 #define I2C_TIMINGR_SDADEL_1                                               (0x2U << I2C_TIMINGR_SDADEL_Pos)
1912 #define I2C_TIMINGR_SDADEL_2                                               (0x4U << I2C_TIMINGR_SDADEL_Pos)
1913 #define I2C_TIMINGR_SDADEL_3                                               (0x8U << I2C_TIMINGR_SDADEL_Pos)
1914 #define I2C_TIMINGR_SCLH_Pos                                               (8UL)                              /*!<I2C TIMINGR: SCLH (Bit 8) */
1915 #define I2C_TIMINGR_SCLH_Msk                                               (0xFFUL << I2C_TIMINGR_SCLH_Pos)   /*!< I2C TIMINGR: SCLH (Bitfield-Mask: 0xff) */
1916 #define I2C_TIMINGR_SCLH                                                   I2C_TIMINGR_SCLH_Msk
1917 #define I2C_TIMINGR_SCLH_0                                                 (0x1U << I2C_TIMINGR_SCLH_Pos)
1918 #define I2C_TIMINGR_SCLH_1                                                 (0x2U << I2C_TIMINGR_SCLH_Pos)
1919 #define I2C_TIMINGR_SCLH_2                                                 (0x4U << I2C_TIMINGR_SCLH_Pos)
1920 #define I2C_TIMINGR_SCLH_3                                                 (0x8U << I2C_TIMINGR_SCLH_Pos)
1921 #define I2C_TIMINGR_SCLH_4                                                 (0x10U << I2C_TIMINGR_SCLH_Pos)
1922 #define I2C_TIMINGR_SCLH_5                                                 (0x20U << I2C_TIMINGR_SCLH_Pos)
1923 #define I2C_TIMINGR_SCLH_6                                                 (0x40U << I2C_TIMINGR_SCLH_Pos)
1924 #define I2C_TIMINGR_SCLH_7                                                 (0x80U << I2C_TIMINGR_SCLH_Pos)
1925 #define I2C_TIMINGR_SCLL_Pos                                               (0UL)                              /*!<I2C TIMINGR: SCLL (Bit 0) */
1926 #define I2C_TIMINGR_SCLL_Msk                                               (0xFFUL << I2C_TIMINGR_SCLL_Pos)   /*!< I2C TIMINGR: SCLL (Bitfield-Mask: 0xff) */
1927 #define I2C_TIMINGR_SCLL                                                   I2C_TIMINGR_SCLL_Msk
1928 #define I2C_TIMINGR_SCLL_0                                                 (0x1U << I2C_TIMINGR_SCLL_Pos)
1929 #define I2C_TIMINGR_SCLL_1                                                 (0x2U << I2C_TIMINGR_SCLL_Pos)
1930 #define I2C_TIMINGR_SCLL_2                                                 (0x4U << I2C_TIMINGR_SCLL_Pos)
1931 #define I2C_TIMINGR_SCLL_3                                                 (0x8U << I2C_TIMINGR_SCLL_Pos)
1932 #define I2C_TIMINGR_SCLL_4                                                 (0x10U << I2C_TIMINGR_SCLL_Pos)
1933 #define I2C_TIMINGR_SCLL_5                                                 (0x20U << I2C_TIMINGR_SCLL_Pos)
1934 #define I2C_TIMINGR_SCLL_6                                                 (0x40U << I2C_TIMINGR_SCLL_Pos)
1935 #define I2C_TIMINGR_SCLL_7                                                 (0x80U << I2C_TIMINGR_SCLL_Pos)
1936 
1937 /* =====================================================    TIMEOUTR    ===================================================== */
1938 #define I2C_TIMEOUTR_TEXTEN_Pos                                            (31UL)                                 /*!<I2C TIMEOUTR: TEXTEN (Bit 31) */
1939 #define I2C_TIMEOUTR_TEXTEN_Msk                                            (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)     /*!< I2C TIMEOUTR: TEXTEN (Bitfield-Mask: 0x01) */
1940 #define I2C_TIMEOUTR_TEXTEN                                                I2C_TIMEOUTR_TEXTEN_Msk
1941 #define I2C_TIMEOUTR_TIMEOUTB_Pos                                          (16UL)                                 /*!<I2C TIMEOUTR: TIMEOUTB (Bit 16) */
1942 #define I2C_TIMEOUTR_TIMEOUTB_Msk                                          (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< I2C TIMEOUTR: TIMEOUTB (Bitfield-Mask: 0xfff) */
1943 #define I2C_TIMEOUTR_TIMEOUTB                                              I2C_TIMEOUTR_TIMEOUTB_Msk
1944 #define I2C_TIMEOUTR_TIMEOUTB_0                                            (0x1U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1945 #define I2C_TIMEOUTR_TIMEOUTB_1                                            (0x2U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1946 #define I2C_TIMEOUTR_TIMEOUTB_2                                            (0x4U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1947 #define I2C_TIMEOUTR_TIMEOUTB_3                                            (0x8U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1948 #define I2C_TIMEOUTR_TIMEOUTB_4                                            (0x10U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1949 #define I2C_TIMEOUTR_TIMEOUTB_5                                            (0x20U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1950 #define I2C_TIMEOUTR_TIMEOUTB_6                                            (0x40U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1951 #define I2C_TIMEOUTR_TIMEOUTB_7                                            (0x80U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1952 #define I2C_TIMEOUTR_TIMEOUTB_8                                            (0x100U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1953 #define I2C_TIMEOUTR_TIMEOUTB_9                                            (0x200U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1954 #define I2C_TIMEOUTR_TIMEOUTB_10                                           (0x400U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1955 #define I2C_TIMEOUTR_TIMEOUTB_11                                           (0x800U << I2C_TIMEOUTR_TIMEOUTB_Pos)
1956 #define I2C_TIMEOUTR_TIMOUTEN_Pos                                          (15UL)                                 /*!<I2C TIMEOUTR: TIMOUTEN (Bit 15) */
1957 #define I2C_TIMEOUTR_TIMOUTEN_Msk                                          (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)   /*!< I2C TIMEOUTR: TIMOUTEN (Bitfield-Mask: 0x01) */
1958 #define I2C_TIMEOUTR_TIMOUTEN                                              I2C_TIMEOUTR_TIMOUTEN_Msk
1959 #define I2C_TIMEOUTR_TIDLE_Pos                                             (12UL)                                 /*!<I2C TIMEOUTR: TIDLE (Bit 12) */
1960 #define I2C_TIMEOUTR_TIDLE_Msk                                             (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)      /*!< I2C TIMEOUTR: TIDLE (Bitfield-Mask: 0x01) */
1961 #define I2C_TIMEOUTR_TIDLE                                                 I2C_TIMEOUTR_TIDLE_Msk
1962 #define I2C_TIMEOUTR_TIMEOUTA_Pos                                          (0UL)                                  /*!<I2C TIMEOUTR: TIMEOUTA (Bit 0) */
1963 #define I2C_TIMEOUTR_TIMEOUTA_Msk                                          (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< I2C TIMEOUTR: TIMEOUTA (Bitfield-Mask: 0xfff) */
1964 #define I2C_TIMEOUTR_TIMEOUTA                                              I2C_TIMEOUTR_TIMEOUTA_Msk
1965 #define I2C_TIMEOUTR_TIMEOUTA_0                                            (0x1U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1966 #define I2C_TIMEOUTR_TIMEOUTA_1                                            (0x2U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1967 #define I2C_TIMEOUTR_TIMEOUTA_2                                            (0x4U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1968 #define I2C_TIMEOUTR_TIMEOUTA_3                                            (0x8U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1969 #define I2C_TIMEOUTR_TIMEOUTA_4                                            (0x10U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1970 #define I2C_TIMEOUTR_TIMEOUTA_5                                            (0x20U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1971 #define I2C_TIMEOUTR_TIMEOUTA_6                                            (0x40U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1972 #define I2C_TIMEOUTR_TIMEOUTA_7                                            (0x80U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1973 #define I2C_TIMEOUTR_TIMEOUTA_8                                            (0x100U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1974 #define I2C_TIMEOUTR_TIMEOUTA_9                                            (0x200U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1975 #define I2C_TIMEOUTR_TIMEOUTA_10                                           (0x400U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1976 #define I2C_TIMEOUTR_TIMEOUTA_11                                           (0x800U << I2C_TIMEOUTR_TIMEOUTA_Pos)
1977 
1978 /* =====================================================    ISR    ===================================================== */
1979 #define I2C_ISR_ADDCODE_Pos                                                (17U)                             /*!<I2C ISR: ADDCODE (Bit 17) */
1980 #define I2C_ISR_ADDCODE_Msk                                                (0x7FUL << I2C_ISR_ADDCODE_Pos)   /*!< I2C ISR: ADDCODE (Bitfield-Mask: 0x7f) */
1981 #define I2C_ISR_ADDCODE                                                    I2C_ISR_ADDCODE_Msk
1982 #define I2C_ISR_ADDCODE_0                                                  (0x1U << I2C_ISR_ADDCODE_Pos)
1983 #define I2C_ISR_ADDCODE_1                                                  (0x2U << I2C_ISR_ADDCODE_Pos)
1984 #define I2C_ISR_ADDCODE_2                                                  (0x4U << I2C_ISR_ADDCODE_Pos)
1985 #define I2C_ISR_ADDCODE_3                                                  (0x8U << I2C_ISR_ADDCODE_Pos)
1986 #define I2C_ISR_ADDCODE_4                                                  (0x10U << I2C_ISR_ADDCODE_Pos)
1987 #define I2C_ISR_ADDCODE_5                                                  (0x20U << I2C_ISR_ADDCODE_Pos)
1988 #define I2C_ISR_ADDCODE_6                                                  (0x40U << I2C_ISR_ADDCODE_Pos)
1989 #define I2C_ISR_DIR_Pos                                                    (16U)                             /*!<I2C ISR: DIR (Bit 16) */
1990 #define I2C_ISR_DIR_Msk                                                    (0x1UL << I2C_ISR_DIR_Pos)        /*!< I2C ISR: DIR (Bitfield-Mask: 0x01) */
1991 #define I2C_ISR_DIR                                                        I2C_ISR_DIR_Msk
1992 #define I2C_ISR_BUSY_Pos                                                   (15U)                             /*!<I2C ISR: BUSY (Bit 15) */
1993 #define I2C_ISR_BUSY_Msk                                                   (0x1UL << I2C_ISR_BUSY_Pos)       /*!< I2C ISR: BUSY (Bitfield-Mask: 0x01) */
1994 #define I2C_ISR_BUSY                                                       I2C_ISR_BUSY_Msk
1995 #define I2C_ISR_ALERT_Pos                                                  (13UL)                             /*!<I2C ISR: ALERT (Bit 13) */
1996 #define I2C_ISR_ALERT_Msk                                                  (0x1UL << I2C_ISR_ALERT_Pos)       /*!< I2C ISR: ALERT (Bitfield-Mask: 0x01) */
1997 #define I2C_ISR_ALERT                                                      I2C_ISR_ALERT_Msk
1998 #define I2C_ISR_TIMEOUT_Pos                                                (12UL)                             /*!<I2C ISR: TIMEOUT (Bit 12) */
1999 #define I2C_ISR_TIMEOUT_Msk                                                (0x1UL << I2C_ISR_TIMEOUT_Pos)     /*!< I2C ISR: TIMEOUT (Bitfield-Mask: 0x01) */
2000 #define I2C_ISR_TIMEOUT                                                    I2C_ISR_TIMEOUT_Msk
2001 #define I2C_ISR_PECERR_Pos                                                 (11UL)                             /*!<I2C ISR: PECERR (Bit 11) */
2002 #define I2C_ISR_PECERR_Msk                                                 (0x1UL << I2C_ISR_PECERR_Pos)      /*!< I2C ISR: PECERR (Bitfield-Mask: 0x01) */
2003 #define I2C_ISR_PECERR                                                     I2C_ISR_PECERR_Msk
2004 #define I2C_ISR_OVR_Pos                                                    (10UL)                             /*!<I2C ISR: OVR (Bit 10) */
2005 #define I2C_ISR_OVR_Msk                                                    (0x1UL << I2C_ISR_OVR_Pos)         /*!< I2C ISR: OVR (Bitfield-Mask: 0x01) */
2006 #define I2C_ISR_OVR                                                        I2C_ISR_OVR_Msk
2007 #define I2C_ISR_ARLO_Pos                                                   (9UL)                              /*!<I2C ISR: ARLO (Bit 9) */
2008 #define I2C_ISR_ARLO_Msk                                                   (0x1UL << I2C_ISR_ARLO_Pos)        /*!< I2C ISR: ARLO (Bitfield-Mask: 0x01) */
2009 #define I2C_ISR_ARLO                                                       I2C_ISR_ARLO_Msk
2010 #define I2C_ISR_BERR_Pos                                                   (8UL)                              /*!<I2C ISR: BERR (Bit 8) */
2011 #define I2C_ISR_BERR_Msk                                                   (0x1UL << I2C_ISR_BERR_Pos)        /*!< I2C ISR: BERR (Bitfield-Mask: 0x01) */
2012 #define I2C_ISR_BERR                                                       I2C_ISR_BERR_Msk
2013 #define I2C_ISR_TCR_Pos                                                    (7UL)                              /*!<I2C ISR: TCR (Bit 7) */
2014 #define I2C_ISR_TCR_Msk                                                    (0x1UL << I2C_ISR_TCR_Pos)         /*!< I2C ISR: TCR (Bitfield-Mask: 0x01) */
2015 #define I2C_ISR_TCR                                                        I2C_ISR_TCR_Msk
2016 #define I2C_ISR_TC_Pos                                                     (6UL)                              /*!<I2C ISR: TC (Bit 6) */
2017 #define I2C_ISR_TC_Msk                                                     (0x1UL << I2C_ISR_TC_Pos)          /*!< I2C ISR: TC (Bitfield-Mask: 0x01) */
2018 #define I2C_ISR_TC                                                         I2C_ISR_TC_Msk
2019 #define I2C_ISR_STOPF_Pos                                                  (5UL)                              /*!<I2C ISR: STOPF (Bit 5) */
2020 #define I2C_ISR_STOPF_Msk                                                  (0x1UL << I2C_ISR_STOPF_Pos)       /*!< I2C ISR: STOPF (Bitfield-Mask: 0x01) */
2021 #define I2C_ISR_STOPF                                                      I2C_ISR_STOPF_Msk
2022 #define I2C_ISR_NACKF_Pos                                                  (4UL)                              /*!<I2C ISR: NACKF (Bit 4) */
2023 #define I2C_ISR_NACKF_Msk                                                  (0x1UL << I2C_ISR_NACKF_Pos)       /*!< I2C ISR: NACKF (Bitfield-Mask: 0x01) */
2024 #define I2C_ISR_NACKF                                                      I2C_ISR_NACKF_Msk
2025 #define I2C_ISR_ADDR_Pos                                                   (3UL)                              /*!<I2C ISR: ADDR (Bit 3) */
2026 #define I2C_ISR_ADDR_Msk                                                   (0x1UL << I2C_ISR_ADDR_Pos)        /*!< I2C ISR: ADDR (Bitfield-Mask: 0x01) */
2027 #define I2C_ISR_ADDR                                                       I2C_ISR_ADDR_Msk
2028 #define I2C_ISR_RXNE_Pos                                                   (2UL)                              /*!<I2C ISR: RXNE (Bit 2) */
2029 #define I2C_ISR_RXNE_Msk                                                   (0x1UL << I2C_ISR_RXNE_Pos)        /*!< I2C ISR: RXNE (Bitfield-Mask: 0x01) */
2030 #define I2C_ISR_RXNE                                                       I2C_ISR_RXNE_Msk
2031 #define I2C_ISR_TXIS_Pos                                                   (1UL)                              /*!<I2C ISR: TXIS (Bit 1) */
2032 #define I2C_ISR_TXIS_Msk                                                   (0x1UL << I2C_ISR_TXIS_Pos)        /*!< I2C ISR: TXIS (Bitfield-Mask: 0x01) */
2033 #define I2C_ISR_TXIS                                                       I2C_ISR_TXIS_Msk
2034 #define I2C_ISR_TXE_Pos                                                    (0UL)                              /*!<I2C ISR: TXE (Bit 0) */
2035 #define I2C_ISR_TXE_Msk                                                    (0x1UL << I2C_ISR_TXE_Pos)         /*!< I2C ISR: TXE (Bitfield-Mask: 0x01) */
2036 #define I2C_ISR_TXE                                                        I2C_ISR_TXE_Msk
2037 
2038 /* =====================================================    ICR    ===================================================== */
2039 #define I2C_ICR_ALERTCF_Pos                                                (13UL)                             /*!<I2C ICR: ALERTCF (Bit 13) */
2040 #define I2C_ICR_ALERTCF_Msk                                                (0x1UL << I2C_ICR_ALERTCF_Pos)     /*!< I2C ICR: ALERTCF (Bitfield-Mask: 0x01) */
2041 #define I2C_ICR_ALERTCF                                                    I2C_ICR_ALERTCF_Msk
2042 #define I2C_ICR_TIMOUTCF_Pos                                               (12UL)                             /*!<I2C ICR: TIMOUTCF (Bit 12) */
2043 #define I2C_ICR_TIMOUTCF_Msk                                               (0x1UL << I2C_ICR_TIMOUTCF_Pos)    /*!< I2C ICR: TIMOUTCF (Bitfield-Mask: 0x01) */
2044 #define I2C_ICR_TIMOUTCF                                                   I2C_ICR_TIMOUTCF_Msk
2045 #define I2C_ICR_PECCF_Pos                                                  (11UL)                             /*!<I2C ICR: PECCF (Bit 11) */
2046 #define I2C_ICR_PECCF_Msk                                                  (0x1UL << I2C_ICR_PECCF_Pos)       /*!< I2C ICR: PECCF (Bitfield-Mask: 0x01) */
2047 #define I2C_ICR_PECCF                                                      I2C_ICR_PECCF_Msk
2048 #define I2C_ICR_OVRCF_Pos                                                  (10UL)                             /*!<I2C ICR: OVRCF (Bit 10) */
2049 #define I2C_ICR_OVRCF_Msk                                                  (0x1UL << I2C_ICR_OVRCF_Pos)       /*!< I2C ICR: OVRCF (Bitfield-Mask: 0x01) */
2050 #define I2C_ICR_OVRCF                                                      I2C_ICR_OVRCF_Msk
2051 #define I2C_ICR_ARLOCF_Pos                                                 (9UL)                              /*!<I2C ICR: ARLOCF (Bit 9) */
2052 #define I2C_ICR_ARLOCF_Msk                                                 (0x1UL << I2C_ICR_ARLOCF_Pos)      /*!< I2C ICR: ARLOCF (Bitfield-Mask: 0x01) */
2053 #define I2C_ICR_ARLOCF                                                     I2C_ICR_ARLOCF_Msk
2054 #define I2C_ICR_BERRCF_Pos                                                 (8UL)                              /*!<I2C ICR: BERRCF (Bit 8) */
2055 #define I2C_ICR_BERRCF_Msk                                                 (0x1UL << I2C_ICR_BERRCF_Pos)      /*!< I2C ICR: BERRCF (Bitfield-Mask: 0x01) */
2056 #define I2C_ICR_BERRCF                                                     I2C_ICR_BERRCF_Msk
2057 #define I2C_ICR_STOPCF_Pos                                                 (5UL)                              /*!<I2C ICR: STOPCF (Bit 5) */
2058 #define I2C_ICR_STOPCF_Msk                                                 (0x1UL << I2C_ICR_STOPCF_Pos)      /*!< I2C ICR: STOPCF (Bitfield-Mask: 0x01) */
2059 #define I2C_ICR_STOPCF                                                     I2C_ICR_STOPCF_Msk
2060 #define I2C_ICR_NACKCF_Pos                                                 (4UL)                              /*!<I2C ICR: NACKCF (Bit 4) */
2061 #define I2C_ICR_NACKCF_Msk                                                 (0x1UL << I2C_ICR_NACKCF_Pos)      /*!< I2C ICR: NACKCF (Bitfield-Mask: 0x01) */
2062 #define I2C_ICR_NACKCF                                                     I2C_ICR_NACKCF_Msk
2063 #define I2C_ICR_ADDRCF_Pos                                                 (3UL)                              /*!<I2C ICR: ADDRCF (Bit 3) */
2064 #define I2C_ICR_ADDRCF_Msk                                                 (0x1UL << I2C_ICR_ADDRCF_Pos)      /*!< I2C ICR: ADDRCF (Bitfield-Mask: 0x01) */
2065 #define I2C_ICR_ADDRCF                                                     I2C_ICR_ADDRCF_Msk
2066 
2067 /* =====================================================    PECR    ===================================================== */
2068 #define I2C_PECR_PEC_Pos                                                   (0UL)                              /*!<I2C PECR: PEC (Bit 0) */
2069 #define I2C_PECR_PEC_Msk                                                   (0xFFUL << I2C_PECR_PEC_Pos)       /*!< I2C PECR: PEC (Bitfield-Mask: 0xff) */
2070 #define I2C_PECR_PEC                                                       I2C_PECR_PEC_Msk
2071 #define I2C_PECR_PEC_0                                                     (0x1U << I2C_PECR_PEC_Pos)
2072 #define I2C_PECR_PEC_1                                                     (0x2U << I2C_PECR_PEC_Pos)
2073 #define I2C_PECR_PEC_2                                                     (0x4U << I2C_PECR_PEC_Pos)
2074 #define I2C_PECR_PEC_3                                                     (0x8U << I2C_PECR_PEC_Pos)
2075 #define I2C_PECR_PEC_4                                                     (0x10U << I2C_PECR_PEC_Pos)
2076 #define I2C_PECR_PEC_5                                                     (0x20U << I2C_PECR_PEC_Pos)
2077 #define I2C_PECR_PEC_6                                                     (0x40U << I2C_PECR_PEC_Pos)
2078 #define I2C_PECR_PEC_7                                                     (0x80U << I2C_PECR_PEC_Pos)
2079 
2080 /* =====================================================    RXDR    ===================================================== */
2081 #define I2C_RXDR_RXDATA_Pos                                                (0UL)                  /*!<I2C RXDR: RXDATA (Bit 0) */
2082 #define I2C_RXDR_RXDATA_Msk                                                (0xFFUL << I2C_RXDR_RXDATA_Pos)    /*!< I2C RXDR: RXDATA (Bitfield-Mask: 0xff) */
2083 #define I2C_RXDR_RXDATA                                                    I2C_RXDR_RXDATA_Msk
2084 #define I2C_RXDR_RXDATA_0                                                  (0x1U << I2C_RXDR_RXDATA_Pos)
2085 #define I2C_RXDR_RXDATA_1                                                  (0x2U << I2C_RXDR_RXDATA_Pos)
2086 #define I2C_RXDR_RXDATA_2                                                  (0x4U << I2C_RXDR_RXDATA_Pos)
2087 #define I2C_RXDR_RXDATA_3                                                  (0x8U << I2C_RXDR_RXDATA_Pos)
2088 #define I2C_RXDR_RXDATA_4                                                  (0x10U << I2C_RXDR_RXDATA_Pos)
2089 #define I2C_RXDR_RXDATA_5                                                  (0x20U << I2C_RXDR_RXDATA_Pos)
2090 #define I2C_RXDR_RXDATA_6                                                  (0x40U << I2C_RXDR_RXDATA_Pos)
2091 #define I2C_RXDR_RXDATA_7                                                  (0x80U << I2C_RXDR_RXDATA_Pos)
2092 
2093 /* =====================================================    TXDR    ===================================================== */
2094 #define I2C_TXDR_TXDATA_Pos                                                (0UL)                  /*!<I2C TXDR: TXDATA (Bit 0) */
2095 #define I2C_TXDR_TXDATA_Msk                                                (0xFFUL << I2C_TXDR_TXDATA_Pos)    /*!< I2C TXDR: TXDATA (Bitfield-Mask: 0xff) */
2096 #define I2C_TXDR_TXDATA                                                    I2C_TXDR_TXDATA_Msk
2097 #define I2C_TXDR_TXDATA_0                                                  (0x1U << I2C_TXDR_TXDATA_Pos)
2098 #define I2C_TXDR_TXDATA_1                                                  (0x2U << I2C_TXDR_TXDATA_Pos)
2099 #define I2C_TXDR_TXDATA_2                                                  (0x4U << I2C_TXDR_TXDATA_Pos)
2100 #define I2C_TXDR_TXDATA_3                                                  (0x8U << I2C_TXDR_TXDATA_Pos)
2101 #define I2C_TXDR_TXDATA_4                                                  (0x10U << I2C_TXDR_TXDATA_Pos)
2102 #define I2C_TXDR_TXDATA_5                                                  (0x20U << I2C_TXDR_TXDATA_Pos)
2103 #define I2C_TXDR_TXDATA_6                                                  (0x40U << I2C_TXDR_TXDATA_Pos)
2104 #define I2C_TXDR_TXDATA_7                                                  (0x80U << I2C_TXDR_TXDATA_Pos)
2105 
2106 
2107 /* =========================================================================================================================== */
2108 /*=====================                                      FLASH                                      ===================== */
2109 /* =========================================================================================================================== */
2110 
2111 /* =====================================================    COMMAND    ===================================================== */
2112 #define FLASH_COMMAND_COMMAND_Pos                                          (0UL)    /*!<FLASH COMMAND: COMMAND (Bit 0) */
2113 #define FLASH_COMMAND_COMMAND_Msk                                          (0xffUL)   /*!< FLASH COMMAND: COMMAND (Bitfield-Mask: 0xff) */
2114 #define FLASH_COMMAND_COMMAND                                              FLASH_COMMAND_COMMAND_Msk
2115 #define FLASH_COMMAND_COMMAND_0                                            (0x1U << FLASH_COMMAND_COMMAND_Pos)
2116 #define FLASH_COMMAND_COMMAND_1                                            (0x2U << FLASH_COMMAND_COMMAND_Pos)
2117 #define FLASH_COMMAND_COMMAND_2                                            (0x4U << FLASH_COMMAND_COMMAND_Pos)
2118 #define FLASH_COMMAND_COMMAND_3                                            (0x8U << FLASH_COMMAND_COMMAND_Pos)
2119 #define FLASH_COMMAND_COMMAND_4                                            (0x10U << FLASH_COMMAND_COMMAND_Pos)
2120 #define FLASH_COMMAND_COMMAND_5                                            (0x20U << FLASH_COMMAND_COMMAND_Pos)
2121 #define FLASH_COMMAND_COMMAND_6                                            (0x40U << FLASH_COMMAND_COMMAND_Pos)
2122 #define FLASH_COMMAND_COMMAND_7                                            (0x80U << FLASH_COMMAND_COMMAND_Pos)
2123 
2124 /* =====================================================    CONFIG    ===================================================== */
2125 #define FLASH_CONFIG_WAIT_STATES_Pos                                       (4UL)    /*!<FLASH CONFIG: WAIT_STATES (Bit 4) */
2126 #define FLASH_CONFIG_WAIT_STATES_Msk                                       (0x30UL)   /*!< FLASH CONFIG: WAIT_STATES (Bitfield-Mask: 0x03) */
2127 #define FLASH_CONFIG_WAIT_STATES                                           FLASH_CONFIG_WAIT_STATES_Msk
2128 #define FLASH_CONFIG_WAIT_STATES_0                                         (0x1U << FLASH_CONFIG_WAIT_STATES_Pos)
2129 #define FLASH_CONFIG_WAIT_STATES_1                                         (0x2U << FLASH_CONFIG_WAIT_STATES_Pos)
2130 #define FLASH_CONFIG_DIS_GROUP_WRITE_Pos                                   (2UL)    /*!<FLASH CONFIG: DIS_GROUP_WRITE (Bit 2) */
2131 #define FLASH_CONFIG_DIS_GROUP_WRITE_Msk                                   (0x4UL)    /*!< FLASH CONFIG: DIS_GROUP_WRITE (Bitfield-Mask: 0x01) */
2132 #define FLASH_CONFIG_DIS_GROUP_WRITE                                       FLASH_CONFIG_DIS_GROUP_WRITE_Msk
2133 #define FLASH_CONFIG_REMAP_Pos                                             (1UL)    /*!<FLASH CONFIG: REMAP (Bit 1) */
2134 #define FLASH_CONFIG_REMAP_Msk                                             (0x2UL)    /*!< FLASH CONFIG: REMAP (Bitfield-Mask: 0x01) */
2135 #define FLASH_CONFIG_REMAP                                                 FLASH_CONFIG_REMAP_Msk
2136 
2137 /* =====================================================    IRQSTAT    ===================================================== */
2138 #define FLASH_IRQSTAT_READOK_MIS_Pos                                       (4UL)    /*!<FLASH IRQSTAT: READOK_MIS (Bit 4) */
2139 #define FLASH_IRQSTAT_READOK_MIS_Msk                                       (0x10UL)   /*!< FLASH IRQSTAT: READOK_MIS (Bitfield-Mask: 0x01) */
2140 #define FLASH_IRQSTAT_READOK_MIS                                           FLASH_IRQSTAT_READOK_MIS_Msk
2141 #define FLASH_IRQSTAT_ILLCMD_MIS_Pos                                       (3UL)    /*!<FLASH IRQSTAT: ILLCMD_MIS (Bit 3) */
2142 #define FLASH_IRQSTAT_ILLCMD_MIS_Msk                                       (0x8UL)    /*!< FLASH IRQSTAT: ILLCMD_MIS (Bitfield-Mask: 0x01) */
2143 #define FLASH_IRQSTAT_ILLCMD_MIS                                           FLASH_IRQSTAT_ILLCMD_MIS_Msk
2144 #define FLASH_IRQSTAT_CMDERR_MIS_Pos                                       (2UL)    /*!<FLASH IRQSTAT: CMDERR_MIS (Bit 2) */
2145 #define FLASH_IRQSTAT_CMDERR_MIS_Msk                                       (0x4UL)    /*!< FLASH IRQSTAT: CMDERR_MIS (Bitfield-Mask: 0x01) */
2146 #define FLASH_IRQSTAT_CMDERR_MIS                                           FLASH_IRQSTAT_CMDERR_MIS_Msk
2147 #define FLASH_IRQSTAT_CMDSTART_MIS_Pos                                     (1UL)    /*!<FLASH IRQSTAT: CMDSTART_MIS (Bit 1) */
2148 #define FLASH_IRQSTAT_CMDSTART_MIS_Msk                                     (0x2UL)    /*!< FLASH IRQSTAT: CMDSTART_MIS (Bitfield-Mask: 0x01) */
2149 #define FLASH_IRQSTAT_CMDSTART_MIS                                         FLASH_IRQSTAT_CMDSTART_MIS_Msk
2150 #define FLASH_IRQSTAT_CMDDONE_MIS_Pos                                      (0UL)    /*!<FLASH IRQSTAT: CMDDONE_MIS (Bit 0) */
2151 #define FLASH_IRQSTAT_CMDDONE_MIS_Msk                                      (0x1UL)    /*!< FLASH IRQSTAT: CMDDONE_MIS (Bitfield-Mask: 0x01) */
2152 #define FLASH_IRQSTAT_CMDDONE_MIS                                          FLASH_IRQSTAT_CMDDONE_MIS_Msk
2153 
2154 /* =====================================================    IRQMASK    ===================================================== */
2155 #define FLASH_IRQMASK_READOKM_Pos                                          (4UL)    /*!<FLASH IRQMASK: READOKM (Bit 4) */
2156 #define FLASH_IRQMASK_READOKM_Msk                                          (0x10UL)   /*!< FLASH IRQMASK: READOKM (Bitfield-Mask: 0x01) */
2157 #define FLASH_IRQMASK_READOKM                                              FLASH_IRQMASK_READOKM_Msk
2158 #define FLASH_IRQMASK_ILLCMDM_Pos                                          (3UL)    /*!<FLASH IRQMASK: ILLCMDM (Bit 3) */
2159 #define FLASH_IRQMASK_ILLCMDM_Msk                                          (0x8UL)    /*!< FLASH IRQMASK: ILLCMDM (Bitfield-Mask: 0x01) */
2160 #define FLASH_IRQMASK_ILLCMDM                                              FLASH_IRQMASK_ILLCMDM_Msk
2161 #define FLASH_IRQMASK_CMDERRM_Pos                                          (2UL)    /*!<FLASH IRQMASK: CMDERRM (Bit 2) */
2162 #define FLASH_IRQMASK_CMDERRM_Msk                                          (0x4UL)    /*!< FLASH IRQMASK: CMDERRM (Bitfield-Mask: 0x01) */
2163 #define FLASH_IRQMASK_CMDERRM                                              FLASH_IRQMASK_CMDERRM_Msk
2164 #define FLASH_IRQMASK_CMDSTARTM_Pos                                        (1UL)    /*!<FLASH IRQMASK: CMDSTARTM (Bit 1) */
2165 #define FLASH_IRQMASK_CMDSTARTM_Msk                                        (0x2UL)    /*!< FLASH IRQMASK: CMDSTARTM (Bitfield-Mask: 0x01) */
2166 #define FLASH_IRQMASK_CMDSTARTM                                            FLASH_IRQMASK_CMDSTARTM_Msk
2167 #define FLASH_IRQMASK_CMDDONEM_Pos                                         (0UL)    /*!<FLASH IRQMASK: CMDDONEM (Bit 0) */
2168 #define FLASH_IRQMASK_CMDDONEM_Msk                                         (0x1UL)    /*!< FLASH IRQMASK: CMDDONEM (Bitfield-Mask: 0x01) */
2169 #define FLASH_IRQMASK_CMDDONEM                                             FLASH_IRQMASK_CMDDONEM_Msk
2170 
2171 /* =====================================================    IRQRAW    ===================================================== */
2172 #define FLASH_IRQRAW_READOK_RIS_Pos                                        (4UL)    /*!<FLASH IRQRAW: READOK_RIS (Bit 4) */
2173 #define FLASH_IRQRAW_READOK_RIS_Msk                                        (0x10UL)   /*!< FLASH IRQRAW: READOK_RIS (Bitfield-Mask: 0x01) */
2174 #define FLASH_IRQRAW_READOK_RIS                                            FLASH_IRQRAW_READOK_RIS_Msk
2175 #define FLASH_IRQRAW_ILLCMD_RIS_Pos                                        (3UL)    /*!<FLASH IRQRAW: ILLCMD_RIS (Bit 3) */
2176 #define FLASH_IRQRAW_ILLCMD_RIS_Msk                                        (0x8UL)    /*!< FLASH IRQRAW: ILLCMD_RIS (Bitfield-Mask: 0x01) */
2177 #define FLASH_IRQRAW_ILLCMD_RIS                                            FLASH_IRQRAW_ILLCMD_RIS_Msk
2178 #define FLASH_IRQRAW_CMDERR_RIS_Pos                                        (2UL)    /*!<FLASH IRQRAW: CMDERR_RIS (Bit 2) */
2179 #define FLASH_IRQRAW_CMDERR_RIS_Msk                                        (0x4UL)    /*!< FLASH IRQRAW: CMDERR_RIS (Bitfield-Mask: 0x01) */
2180 #define FLASH_IRQRAW_CMDERR_RIS                                            FLASH_IRQRAW_CMDERR_RIS_Msk
2181 #define FLASH_IRQRAW_CMDSTART_RIS_Pos                                      (1UL)    /*!<FLASH IRQRAW: CMDSTART_RIS (Bit 1) */
2182 #define FLASH_IRQRAW_CMDSTART_RIS_Msk                                      (0x2UL)    /*!< FLASH IRQRAW: CMDSTART_RIS (Bitfield-Mask: 0x01) */
2183 #define FLASH_IRQRAW_CMDSTART_RIS                                          FLASH_IRQRAW_CMDSTART_RIS_Msk
2184 #define FLASH_IRQRAW_CMDDONE_RIS_Pos                                       (0UL)    /*!<FLASH IRQRAW: CMDDONE_RIS (Bit 0) */
2185 #define FLASH_IRQRAW_CMDDONE_RIS_Msk                                       (0x1UL)    /*!< FLASH IRQRAW: CMDDONE_RIS (Bitfield-Mask: 0x01) */
2186 #define FLASH_IRQRAW_CMDDONE_RIS                                           FLASH_IRQRAW_CMDDONE_RIS_Msk
2187 
2188 /* =====================================================    FLASH_SIZE    ===================================================== */
2189 #define FLASH_FLASH_SIZE_SWD_DISABLE_Pos                                   (20UL)   /*!<FLASH FLASH_SIZE: SWD_DISABLE (Bit 20) */
2190 #define FLASH_FLASH_SIZE_SWD_DISABLE_Msk                                   (0x100000UL)   /*!< FLASH FLASH_SIZE: SWD_DISABLE (Bitfield-Mask: 0x01) */
2191 #define FLASH_FLASH_SIZE_SWD_DISABLE                                       FLASH_FLASH_SIZE_SWD_DISABLE_Msk
2192 #define FLASH_FLASH_SIZE_FLASH_SECURE_Pos                                  (19UL)   /*!<FLASH FLASH_SIZE: FLASH_SECURE (Bit 19) */
2193 #define FLASH_FLASH_SIZE_FLASH_SECURE_Msk                                  (0x80000UL)    /*!< FLASH FLASH_SIZE: FLASH_SECURE (Bitfield-Mask: 0x01) */
2194 #define FLASH_FLASH_SIZE_FLASH_SECURE                                      FLASH_FLASH_SIZE_FLASH_SECURE_Msk
2195 #define FLASH_FLASH_SIZE_RAM_SIZE_Pos                                      (17UL)   /*!<FLASH FLASH_SIZE: RAM_SIZE (Bit 17) */
2196 #define FLASH_FLASH_SIZE_RAM_SIZE_Msk                                      (0x60000UL)    /*!< FLASH FLASH_SIZE: RAM_SIZE (Bitfield-Mask: 0x03) */
2197 #define FLASH_FLASH_SIZE_RAM_SIZE                                          FLASH_FLASH_SIZE_RAM_SIZE_Msk
2198 #define FLASH_FLASH_SIZE_RAM_SIZE_0                                        (0x1U << FLASH_FLASH_SIZE_RAM_SIZE_Pos)
2199 #define FLASH_FLASH_SIZE_RAM_SIZE_1                                        (0x2U << FLASH_FLASH_SIZE_RAM_SIZE_Pos)
2200 #define FLASH_FLASH_SIZE_FLASH_SIZE_Pos                                    (0UL)    /*!<FLASH FLASH_SIZE: FLASH_SIZE (Bit 0) */
2201 #define FLASH_FLASH_SIZE_FLASH_SIZE_Msk                                    (0xffffUL)   /*!< FLASH FLASH_SIZE: FLASH_SIZE (Bitfield-Mask: 0xffff) */
2202 #define FLASH_FLASH_SIZE_FLASH_SIZE                                        FLASH_FLASH_SIZE_FLASH_SIZE_Msk
2203 #define FLASH_FLASH_SIZE_FLASH_SIZE_0                                      (0x1U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2204 #define FLASH_FLASH_SIZE_FLASH_SIZE_1                                      (0x2U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2205 #define FLASH_FLASH_SIZE_FLASH_SIZE_2                                      (0x4U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2206 #define FLASH_FLASH_SIZE_FLASH_SIZE_3                                      (0x8U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2207 #define FLASH_FLASH_SIZE_FLASH_SIZE_4                                      (0x10U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2208 #define FLASH_FLASH_SIZE_FLASH_SIZE_5                                      (0x20U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2209 #define FLASH_FLASH_SIZE_FLASH_SIZE_6                                      (0x40U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2210 #define FLASH_FLASH_SIZE_FLASH_SIZE_7                                      (0x80U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2211 #define FLASH_FLASH_SIZE_FLASH_SIZE_8                                      (0x100U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2212 #define FLASH_FLASH_SIZE_FLASH_SIZE_9                                      (0x200U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2213 #define FLASH_FLASH_SIZE_FLASH_SIZE_10                                     (0x400U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2214 #define FLASH_FLASH_SIZE_FLASH_SIZE_11                                     (0x800U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2215 #define FLASH_FLASH_SIZE_FLASH_SIZE_12                                     (0x1000U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2216 #define FLASH_FLASH_SIZE_FLASH_SIZE_13                                     (0x2000U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2217 #define FLASH_FLASH_SIZE_FLASH_SIZE_14                                     (0x4000U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2218 #define FLASH_FLASH_SIZE_FLASH_SIZE_15                                     (0x8000U << FLASH_FLASH_SIZE_FLASH_SIZE_Pos)
2219 
2220 /* =====================================================    ADDRESS    ===================================================== */
2221 #define FLASH_ADDRESS_XADDR_Pos                                            (6UL)    /*!<FLASH ADDRESS: XADDR (Bit 6) */
2222 #define FLASH_ADDRESS_XADDR_Msk                                            (0xffc0UL)   /*!< FLASH ADDRESS: XADDR (Bitfield-Mask: 0x3ff) */
2223 #define FLASH_ADDRESS_XADDR                                                FLASH_ADDRESS_XADDR_Msk
2224 #define FLASH_ADDRESS_XADDR_0                                              (0x1U << FLASH_ADDRESS_XADDR_Pos)
2225 #define FLASH_ADDRESS_XADDR_1                                              (0x2U << FLASH_ADDRESS_XADDR_Pos)
2226 #define FLASH_ADDRESS_XADDR_2                                              (0x4U << FLASH_ADDRESS_XADDR_Pos)
2227 #define FLASH_ADDRESS_XADDR_3                                              (0x8U << FLASH_ADDRESS_XADDR_Pos)
2228 #define FLASH_ADDRESS_XADDR_4                                              (0x10U << FLASH_ADDRESS_XADDR_Pos)
2229 #define FLASH_ADDRESS_XADDR_5                                              (0x20U << FLASH_ADDRESS_XADDR_Pos)
2230 #define FLASH_ADDRESS_XADDR_6                                              (0x40U << FLASH_ADDRESS_XADDR_Pos)
2231 #define FLASH_ADDRESS_XADDR_7                                              (0x80U << FLASH_ADDRESS_XADDR_Pos)
2232 #define FLASH_ADDRESS_XADDR_8                                              (0x100U << FLASH_ADDRESS_XADDR_Pos)
2233 #define FLASH_ADDRESS_XADDR_9                                              (0x200U << FLASH_ADDRESS_XADDR_Pos)
2234 #define FLASH_ADDRESS_YADDR_Pos                                            (0UL)    /*!<FLASH ADDRESS: YADDR (Bit 0) */
2235 #define FLASH_ADDRESS_YADDR_Msk                                            (0x3fUL)   /*!< FLASH ADDRESS: YADDR (Bitfield-Mask: 0x3f) */
2236 #define FLASH_ADDRESS_YADDR                                                FLASH_ADDRESS_YADDR_Msk
2237 #define FLASH_ADDRESS_YADDR_0                                              (0x1U << FLASH_ADDRESS_YADDR_Pos)
2238 #define FLASH_ADDRESS_YADDR_1                                              (0x2U << FLASH_ADDRESS_YADDR_Pos)
2239 #define FLASH_ADDRESS_YADDR_2                                              (0x4U << FLASH_ADDRESS_YADDR_Pos)
2240 #define FLASH_ADDRESS_YADDR_3                                              (0x8U << FLASH_ADDRESS_YADDR_Pos)
2241 #define FLASH_ADDRESS_YADDR_4                                              (0x10U << FLASH_ADDRESS_YADDR_Pos)
2242 #define FLASH_ADDRESS_YADDR_5                                              (0x20U << FLASH_ADDRESS_YADDR_Pos)
2243 
2244 /* =====================================================    LFSRVAL      =====================================================*/
2245 #define FLASH_LFSRVAL_Pos                                                  (0UL)    /*!< Linear feedback shift*/
2246 #define FLASH_LFSRVAL_Msk                                                  (0xFFFFFFFFUL << FLASH_LFSRVAL_Pos)        /*! 0xFFFFFFFF */
2247 #define FLASH_LFSRVAL                                                      FLASH_LFSRVAL_Msk
2248 #define FLASH_LFSRVAL_0                                                    (0x00000001U << FLASH_LFSRVAL_Pos)             /*! 0x00000001 */
2249 #define FLASH_LFSRVAL_1                                                    (0x00000002U << FLASH_LFSRVAL_Pos)             /*! 0x00000002 */
2250 #define FLASH_LFSRVAL_2                                                    (0x00000004U << FLASH_LFSRVAL_Pos)             /*! 0x00000004 */
2251 #define FLASH_LFSRVAL_3                                                    (0x00000008U << FLASH_LFSRVAL_Pos)             /*! 0x00000008 */
2252 #define FLASH_LFSRVAL_4                                                    (0x00000010U << FLASH_LFSRVAL_Pos)             /*! 0x00000010 */
2253 #define FLASH_LFSRVAL_5                                                    (0x00000020U << FLASH_LFSRVAL_Pos)             /*! 0x00000020 */
2254 #define FLASH_LFSRVAL_6                                                    (0x00000040U << FLASH_LFSRVAL_Pos)             /*! 0x00000040 */
2255 #define FLASH_LFSRVAL_7                                                    (0x00000080U << FLASH_LFSRVAL_Pos)             /*! 0x00000080 */
2256 #define FLASH_LFSRVAL_8                                                    (0x00000100U << FLASH_LFSRVAL_Pos)             /*! 0x00000100 */
2257 #define FLASH_LFSRVAL_9                                                    (0x00000200U << FLASH_LFSRVAL_Pos)             /*! 0x00000200 */
2258 #define FLASH_LFSRVAL_10                                                   (0x00000400U << FLASH_LFSRVAL_Pos)             /*! 0x00000400 */
2259 #define FLASH_LFSRVAL_11                                                   (0x00000800U << FLASH_LFSRVAL_Pos)             /*! 0x00000800 */
2260 #define FLASH_LFSRVAL_12                                                   (0x00001000U << FLASH_LFSRVAL_Pos)             /*! 0x00001000 */
2261 #define FLASH_LFSRVAL_13                                                   (0x00002000U << FLASH_LFSRVAL_Pos)             /*! 0x00002000 */
2262 #define FLASH_LFSRVAL_14                                                   (0x00004000U << FLASH_LFSRVAL_Pos)             /*! 0x00004000 */
2263 #define FLASH_LFSRVAL_15                                                   (0x00008000U << FLASH_LFSRVAL_Pos)             /*! 0x00008000 */
2264 #define FLASH_LFSRVAL_16                                                   (0x00010000U << FLASH_LFSRVAL_Pos)             /*! 0x00010000 */
2265 #define FLASH_LFSRVAL_17                                                   (0x00020000U << FLASH_LFSRVAL_Pos)             /*! 0x00020000 */
2266 #define FLASH_LFSRVAL_18                                                   (0x00040000U << FLASH_LFSRVAL_Pos)             /*! 0x00040000 */
2267 #define FLASH_LFSRVAL_19                                                   (0x00080000U << FLASH_LFSRVAL_Pos)             /*! 0x00080000 */
2268 #define FLASH_LFSRVAL_20                                                   (0x00100000U << FLASH_LFSRVAL_Pos)             /*! 0x00100000 */
2269 #define FLASH_LFSRVAL_21                                                   (0x00200000U << FLASH_LFSRVAL_Pos)             /*! 0x00200000 */
2270 #define FLASH_LFSRVAL_22                                                   (0x00400000U << FLASH_LFSRVAL_Pos)             /*! 0x00400000 */
2271 #define FLASH_LFSRVAL_23                                                   (0x00800000U << FLASH_LFSRVAL_Pos)             /*! 0x00800000 */
2272 #define FLASH_LFSRVAL_24                                                   (0x01000000U << FLASH_LFSRVAL_Pos)             /*! 0x01000000 */
2273 #define FLASH_LFSRVAL_25                                                   (0x02000000U << FLASH_LFSRVAL_Pos)             /*! 0x02000000 */
2274 #define FLASH_LFSRVAL_26                                                   (0x04000000U << FLASH_LFSRVAL_Pos)             /*! 0x04000000 */
2275 #define FLASH_LFSRVAL_27                                                   (0x08000000U << FLASH_LFSRVAL_Pos)             /*! 0x08000000 */
2276 #define FLASH_LFSRVAL_28                                                   (0x10000000U << FLASH_LFSRVAL_Pos)             /*! 0x10000000 */
2277 #define FLASH_LFSRVAL_29                                                   (0x20000000U << FLASH_LFSRVAL_Pos)             /*! 0x20000000 */
2278 #define FLASH_LFSRVAL_30                                                   (0x40000000U << FLASH_LFSRVAL_Pos)             /*! 0x40000000 */
2279 #define FLASH_LFSRVAL_31                                                   (0x80000000U << FLASH_LFSRVAL_Pos)             /*! 0x80000000 */
2280 
2281 /* =====================================================    PAGEPROT0    ===================================================== */
2282 #define FLASH_PAGEPROT0_SEG1_Pos                                           (16UL)   /*!<FLASH PAGEPROT0: SEG1 (Bit 16) */
2283 #define FLASH_PAGEPROT0_SEG1_Msk                                           (0xffff0000UL)   /*!< FLASH PAGEPROT0: SEG1 (Bitfield-Mask: 0xffff) */
2284 #define FLASH_PAGEPROT0_SEG1                                               FLASH_PAGEPROT0_SEG1_Msk
2285 #define FLASH_PAGEPROT0_SEG1_0                                             (0x1U << FLASH_PAGEPROT0_SEG1_Pos)
2286 #define FLASH_PAGEPROT0_SEG1_1                                             (0x2U << FLASH_PAGEPROT0_SEG1_Pos)
2287 #define FLASH_PAGEPROT0_SEG1_2                                             (0x4U << FLASH_PAGEPROT0_SEG1_Pos)
2288 #define FLASH_PAGEPROT0_SEG1_3                                             (0x8U << FLASH_PAGEPROT0_SEG1_Pos)
2289 #define FLASH_PAGEPROT0_SEG1_4                                             (0x10U << FLASH_PAGEPROT0_SEG1_Pos)
2290 #define FLASH_PAGEPROT0_SEG1_5                                             (0x20U << FLASH_PAGEPROT0_SEG1_Pos)
2291 #define FLASH_PAGEPROT0_SEG1_6                                             (0x40U << FLASH_PAGEPROT0_SEG1_Pos)
2292 #define FLASH_PAGEPROT0_SEG1_7                                             (0x80U << FLASH_PAGEPROT0_SEG1_Pos)
2293 #define FLASH_PAGEPROT0_SEG1_8                                             (0x100U << FLASH_PAGEPROT0_SEG1_Pos)
2294 #define FLASH_PAGEPROT0_SEG1_9                                             (0x200U << FLASH_PAGEPROT0_SEG1_Pos)
2295 #define FLASH_PAGEPROT0_SEG1_10                                            (0x400U << FLASH_PAGEPROT0_SEG1_Pos)
2296 #define FLASH_PAGEPROT0_SEG1_11                                            (0x800U << FLASH_PAGEPROT0_SEG1_Pos)
2297 #define FLASH_PAGEPROT0_SEG1_12                                            (0x1000U << FLASH_PAGEPROT0_SEG1_Pos)
2298 #define FLASH_PAGEPROT0_SEG1_13                                            (0x2000U << FLASH_PAGEPROT0_SEG1_Pos)
2299 #define FLASH_PAGEPROT0_SEG1_14                                            (0x4000U << FLASH_PAGEPROT0_SEG1_Pos)
2300 #define FLASH_PAGEPROT0_SEG1_15                                            (0x8000U << FLASH_PAGEPROT0_SEG1_Pos)
2301 #define FLASH_PAGEPROT0_SEG0_Pos                                           (0UL)    /*!<FLASH PAGEPROT0: SEG0 (Bit 0) */
2302 #define FLASH_PAGEPROT0_SEG0_Msk                                           (0xffffUL)   /*!< FLASH PAGEPROT0: SEG0 (Bitfield-Mask: 0xffff) */
2303 #define FLASH_PAGEPROT0_SEG0                                               FLASH_PAGEPROT0_SEG0_Msk
2304 #define FLASH_PAGEPROT0_SEG0_0                                             (0x1U << FLASH_PAGEPROT0_SEG0_Pos)
2305 #define FLASH_PAGEPROT0_SEG0_1                                             (0x2U << FLASH_PAGEPROT0_SEG0_Pos)
2306 #define FLASH_PAGEPROT0_SEG0_2                                             (0x4U << FLASH_PAGEPROT0_SEG0_Pos)
2307 #define FLASH_PAGEPROT0_SEG0_3                                             (0x8U << FLASH_PAGEPROT0_SEG0_Pos)
2308 #define FLASH_PAGEPROT0_SEG0_4                                             (0x10U << FLASH_PAGEPROT0_SEG0_Pos)
2309 #define FLASH_PAGEPROT0_SEG0_5                                             (0x20U << FLASH_PAGEPROT0_SEG0_Pos)
2310 #define FLASH_PAGEPROT0_SEG0_6                                             (0x40U << FLASH_PAGEPROT0_SEG0_Pos)
2311 #define FLASH_PAGEPROT0_SEG0_7                                             (0x80U << FLASH_PAGEPROT0_SEG0_Pos)
2312 #define FLASH_PAGEPROT0_SEG0_8                                             (0x100U << FLASH_PAGEPROT0_SEG0_Pos)
2313 #define FLASH_PAGEPROT0_SEG0_9                                             (0x200U << FLASH_PAGEPROT0_SEG0_Pos)
2314 #define FLASH_PAGEPROT0_SEG0_10                                            (0x400U << FLASH_PAGEPROT0_SEG0_Pos)
2315 #define FLASH_PAGEPROT0_SEG0_11                                            (0x800U << FLASH_PAGEPROT0_SEG0_Pos)
2316 #define FLASH_PAGEPROT0_SEG0_12                                            (0x1000U << FLASH_PAGEPROT0_SEG0_Pos)
2317 #define FLASH_PAGEPROT0_SEG0_13                                            (0x2000U << FLASH_PAGEPROT0_SEG0_Pos)
2318 #define FLASH_PAGEPROT0_SEG0_14                                            (0x4000U << FLASH_PAGEPROT0_SEG0_Pos)
2319 #define FLASH_PAGEPROT0_SEG0_15                                            (0x8000U << FLASH_PAGEPROT0_SEG0_Pos)
2320 
2321 /* =====================================================    PAGEPROT1    ===================================================== */
2322 #define FLASH_PAGEPROT1_SEG3_Pos                                           (16UL)   /*!<FLASH PAGEPROT1: SEG3 (Bit 16) */
2323 #define FLASH_PAGEPROT1_SEG3_Msk                                           (0xffff0000UL)   /*!< FLASH PAGEPROT1: SEG3 (Bitfield-Mask: 0xffff) */
2324 #define FLASH_PAGEPROT1_SEG3                                               FLASH_PAGEPROT1_SEG3_Msk
2325 #define FLASH_PAGEPROT1_SEG3_0                                             (0x1U << FLASH_PAGEPROT1_SEG3_Pos)
2326 #define FLASH_PAGEPROT1_SEG3_1                                             (0x2U << FLASH_PAGEPROT1_SEG3_Pos)
2327 #define FLASH_PAGEPROT1_SEG3_2                                             (0x4U << FLASH_PAGEPROT1_SEG3_Pos)
2328 #define FLASH_PAGEPROT1_SEG3_3                                             (0x8U << FLASH_PAGEPROT1_SEG3_Pos)
2329 #define FLASH_PAGEPROT1_SEG3_4                                             (0x10U << FLASH_PAGEPROT1_SEG3_Pos)
2330 #define FLASH_PAGEPROT1_SEG3_5                                             (0x20U << FLASH_PAGEPROT1_SEG3_Pos)
2331 #define FLASH_PAGEPROT1_SEG3_6                                             (0x40U << FLASH_PAGEPROT1_SEG3_Pos)
2332 #define FLASH_PAGEPROT1_SEG3_7                                             (0x80U << FLASH_PAGEPROT1_SEG3_Pos)
2333 #define FLASH_PAGEPROT1_SEG3_8                                             (0x100U << FLASH_PAGEPROT1_SEG3_Pos)
2334 #define FLASH_PAGEPROT1_SEG3_9                                             (0x200U << FLASH_PAGEPROT1_SEG3_Pos)
2335 #define FLASH_PAGEPROT1_SEG3_10                                            (0x400U << FLASH_PAGEPROT1_SEG3_Pos)
2336 #define FLASH_PAGEPROT1_SEG3_11                                            (0x800U << FLASH_PAGEPROT1_SEG3_Pos)
2337 #define FLASH_PAGEPROT1_SEG3_12                                            (0x1000U << FLASH_PAGEPROT1_SEG3_Pos)
2338 #define FLASH_PAGEPROT1_SEG3_13                                            (0x2000U << FLASH_PAGEPROT1_SEG3_Pos)
2339 #define FLASH_PAGEPROT1_SEG3_14                                            (0x4000U << FLASH_PAGEPROT1_SEG3_Pos)
2340 #define FLASH_PAGEPROT1_SEG3_15                                            (0x8000U << FLASH_PAGEPROT1_SEG3_Pos)
2341 #define FLASH_PAGEPROT1_SEG2_Pos                                           (0UL)    /*!<FLASH PAGEPROT1: SEG2 (Bit 0) */
2342 #define FLASH_PAGEPROT1_SEG2_Msk                                           (0xffffUL)   /*!< FLASH PAGEPROT1: SEG2 (Bitfield-Mask: 0xffff) */
2343 #define FLASH_PAGEPROT1_SEG2                                               FLASH_PAGEPROT1_SEG2_Msk
2344 #define FLASH_PAGEPROT1_SEG2_0                                             (0x1U << FLASH_PAGEPROT1_SEG2_Pos)
2345 #define FLASH_PAGEPROT1_SEG2_1                                             (0x2U << FLASH_PAGEPROT1_SEG2_Pos)
2346 #define FLASH_PAGEPROT1_SEG2_2                                             (0x4U << FLASH_PAGEPROT1_SEG2_Pos)
2347 #define FLASH_PAGEPROT1_SEG2_3                                             (0x8U << FLASH_PAGEPROT1_SEG2_Pos)
2348 #define FLASH_PAGEPROT1_SEG2_4                                             (0x10U << FLASH_PAGEPROT1_SEG2_Pos)
2349 #define FLASH_PAGEPROT1_SEG2_5                                             (0x20U << FLASH_PAGEPROT1_SEG2_Pos)
2350 #define FLASH_PAGEPROT1_SEG2_6                                             (0x40U << FLASH_PAGEPROT1_SEG2_Pos)
2351 #define FLASH_PAGEPROT1_SEG2_7                                             (0x80U << FLASH_PAGEPROT1_SEG2_Pos)
2352 #define FLASH_PAGEPROT1_SEG2_8                                             (0x100U << FLASH_PAGEPROT1_SEG2_Pos)
2353 #define FLASH_PAGEPROT1_SEG2_9                                             (0x200U << FLASH_PAGEPROT1_SEG2_Pos)
2354 #define FLASH_PAGEPROT1_SEG2_10                                            (0x400U << FLASH_PAGEPROT1_SEG2_Pos)
2355 #define FLASH_PAGEPROT1_SEG2_11                                            (0x800U << FLASH_PAGEPROT1_SEG2_Pos)
2356 #define FLASH_PAGEPROT1_SEG2_12                                            (0x1000U << FLASH_PAGEPROT1_SEG2_Pos)
2357 #define FLASH_PAGEPROT1_SEG2_13                                            (0x2000U << FLASH_PAGEPROT1_SEG2_Pos)
2358 #define FLASH_PAGEPROT1_SEG2_14                                            (0x4000U << FLASH_PAGEPROT1_SEG2_Pos)
2359 #define FLASH_PAGEPROT1_SEG2_15                                            (0x8000U << FLASH_PAGEPROT1_SEG2_Pos)
2360 
2361 /* =====================================================    DATA0    ===================================================== */
2362 #define FLASH_DATA0_DATA0_Pos                                              (0UL)    /*!<FLASH DATA0: DATA0 (Bit 0) */
2363 #define FLASH_DATA0_DATA0_Msk                                              (0xffffffffUL)   /*!< FLASH DATA0: DATA0 (Bitfield-Mask: 0xffffffff) */
2364 #define FLASH_DATA0_DATA0                                                  FLASH_DATA0_DATA0_Msk
2365 #define FLASH_DATA0_DATA0_0                                                (0x1U << FLASH_DATA0_DATA0_Pos)
2366 #define FLASH_DATA0_DATA0_1                                                (0x2U << FLASH_DATA0_DATA0_Pos)
2367 #define FLASH_DATA0_DATA0_2                                                (0x4U << FLASH_DATA0_DATA0_Pos)
2368 #define FLASH_DATA0_DATA0_3                                                (0x8U << FLASH_DATA0_DATA0_Pos)
2369 #define FLASH_DATA0_DATA0_4                                                (0x10U << FLASH_DATA0_DATA0_Pos)
2370 #define FLASH_DATA0_DATA0_5                                                (0x20U << FLASH_DATA0_DATA0_Pos)
2371 #define FLASH_DATA0_DATA0_6                                                (0x40U << FLASH_DATA0_DATA0_Pos)
2372 #define FLASH_DATA0_DATA0_7                                                (0x80U << FLASH_DATA0_DATA0_Pos)
2373 #define FLASH_DATA0_DATA0_8                                                (0x100U << FLASH_DATA0_DATA0_Pos)
2374 #define FLASH_DATA0_DATA0_9                                                (0x200U << FLASH_DATA0_DATA0_Pos)
2375 #define FLASH_DATA0_DATA0_10                                               (0x400U << FLASH_DATA0_DATA0_Pos)
2376 #define FLASH_DATA0_DATA0_11                                               (0x800U << FLASH_DATA0_DATA0_Pos)
2377 #define FLASH_DATA0_DATA0_12                                               (0x1000U << FLASH_DATA0_DATA0_Pos)
2378 #define FLASH_DATA0_DATA0_13                                               (0x2000U << FLASH_DATA0_DATA0_Pos)
2379 #define FLASH_DATA0_DATA0_14                                               (0x4000U << FLASH_DATA0_DATA0_Pos)
2380 #define FLASH_DATA0_DATA0_15                                               (0x8000U << FLASH_DATA0_DATA0_Pos)
2381 #define FLASH_DATA0_DATA0_16                                               (0x10000U << FLASH_DATA0_DATA0_Pos)
2382 #define FLASH_DATA0_DATA0_17                                               (0x20000U << FLASH_DATA0_DATA0_Pos)
2383 #define FLASH_DATA0_DATA0_18                                               (0x40000U << FLASH_DATA0_DATA0_Pos)
2384 #define FLASH_DATA0_DATA0_19                                               (0x80000U << FLASH_DATA0_DATA0_Pos)
2385 #define FLASH_DATA0_DATA0_20                                               (0x100000U << FLASH_DATA0_DATA0_Pos)
2386 #define FLASH_DATA0_DATA0_21                                               (0x200000U << FLASH_DATA0_DATA0_Pos)
2387 #define FLASH_DATA0_DATA0_22                                               (0x400000U << FLASH_DATA0_DATA0_Pos)
2388 #define FLASH_DATA0_DATA0_23                                               (0x800000U << FLASH_DATA0_DATA0_Pos)
2389 #define FLASH_DATA0_DATA0_24                                               (0x1000000U << FLASH_DATA0_DATA0_Pos)
2390 #define FLASH_DATA0_DATA0_25                                               (0x2000000U << FLASH_DATA0_DATA0_Pos)
2391 #define FLASH_DATA0_DATA0_26                                               (0x4000000U << FLASH_DATA0_DATA0_Pos)
2392 #define FLASH_DATA0_DATA0_27                                               (0x8000000U << FLASH_DATA0_DATA0_Pos)
2393 #define FLASH_DATA0_DATA0_28                                               (0x10000000U << FLASH_DATA0_DATA0_Pos)
2394 #define FLASH_DATA0_DATA0_29                                               (0x20000000U << FLASH_DATA0_DATA0_Pos)
2395 #define FLASH_DATA0_DATA0_30                                               (0x40000000U << FLASH_DATA0_DATA0_Pos)
2396 #define FLASH_DATA0_DATA0_31                                               (0x80000000UL << FLASH_DATA0_DATA0_Pos)
2397 
2398 /* =====================================================    DATA1    ===================================================== */
2399 #define FLASH_DATA1_DATA1_Pos                                              (0UL)    /*!<FLASH DATA1: DATA1 (Bit 0) */
2400 #define FLASH_DATA1_DATA1_Msk                                              (0xffffffffUL)   /*!< FLASH DATA1: DATA1 (Bitfield-Mask: 0xffffffff) */
2401 #define FLASH_DATA1_DATA1                                                  FLASH_DATA1_DATA1_Msk
2402 #define FLASH_DATA1_DATA1_0                                                (0x1U << FLASH_DATA1_DATA1_Pos)
2403 #define FLASH_DATA1_DATA1_1                                                (0x2U << FLASH_DATA1_DATA1_Pos)
2404 #define FLASH_DATA1_DATA1_2                                                (0x4U << FLASH_DATA1_DATA1_Pos)
2405 #define FLASH_DATA1_DATA1_3                                                (0x8U << FLASH_DATA1_DATA1_Pos)
2406 #define FLASH_DATA1_DATA1_4                                                (0x10U << FLASH_DATA1_DATA1_Pos)
2407 #define FLASH_DATA1_DATA1_5                                                (0x20U << FLASH_DATA1_DATA1_Pos)
2408 #define FLASH_DATA1_DATA1_6                                                (0x40U << FLASH_DATA1_DATA1_Pos)
2409 #define FLASH_DATA1_DATA1_7                                                (0x80U << FLASH_DATA1_DATA1_Pos)
2410 #define FLASH_DATA1_DATA1_8                                                (0x100U << FLASH_DATA1_DATA1_Pos)
2411 #define FLASH_DATA1_DATA1_9                                                (0x200U << FLASH_DATA1_DATA1_Pos)
2412 #define FLASH_DATA1_DATA1_10                                               (0x400U << FLASH_DATA1_DATA1_Pos)
2413 #define FLASH_DATA1_DATA1_11                                               (0x800U << FLASH_DATA1_DATA1_Pos)
2414 #define FLASH_DATA1_DATA1_12                                               (0x1000U << FLASH_DATA1_DATA1_Pos)
2415 #define FLASH_DATA1_DATA1_13                                               (0x2000U << FLASH_DATA1_DATA1_Pos)
2416 #define FLASH_DATA1_DATA1_14                                               (0x4000U << FLASH_DATA1_DATA1_Pos)
2417 #define FLASH_DATA1_DATA1_15                                               (0x8000U << FLASH_DATA1_DATA1_Pos)
2418 #define FLASH_DATA1_DATA1_16                                               (0x10000U << FLASH_DATA1_DATA1_Pos)
2419 #define FLASH_DATA1_DATA1_17                                               (0x20000U << FLASH_DATA1_DATA1_Pos)
2420 #define FLASH_DATA1_DATA1_18                                               (0x40000U << FLASH_DATA1_DATA1_Pos)
2421 #define FLASH_DATA1_DATA1_19                                               (0x80000U << FLASH_DATA1_DATA1_Pos)
2422 #define FLASH_DATA1_DATA1_20                                               (0x100000U << FLASH_DATA1_DATA1_Pos)
2423 #define FLASH_DATA1_DATA1_21                                               (0x200000U << FLASH_DATA1_DATA1_Pos)
2424 #define FLASH_DATA1_DATA1_22                                               (0x400000U << FLASH_DATA1_DATA1_Pos)
2425 #define FLASH_DATA1_DATA1_23                                               (0x800000U << FLASH_DATA1_DATA1_Pos)
2426 #define FLASH_DATA1_DATA1_24                                               (0x1000000U << FLASH_DATA1_DATA1_Pos)
2427 #define FLASH_DATA1_DATA1_25                                               (0x2000000U << FLASH_DATA1_DATA1_Pos)
2428 #define FLASH_DATA1_DATA1_26                                               (0x4000000U << FLASH_DATA1_DATA1_Pos)
2429 #define FLASH_DATA1_DATA1_27                                               (0x8000000U << FLASH_DATA1_DATA1_Pos)
2430 #define FLASH_DATA1_DATA1_28                                               (0x10000000U << FLASH_DATA1_DATA1_Pos)
2431 #define FLASH_DATA1_DATA1_29                                               (0x20000000U << FLASH_DATA1_DATA1_Pos)
2432 #define FLASH_DATA1_DATA1_30                                               (0x40000000U << FLASH_DATA1_DATA1_Pos)
2433 #define FLASH_DATA1_DATA1_31                                               (0x80000000UL << FLASH_DATA1_DATA1_Pos)
2434 
2435 /* =====================================================    DATA2    ===================================================== */
2436 #define FLASH_DATA2_DATA2_Pos                                              (0UL)    /*!<FLASH DATA2: DATA2 (Bit 0) */
2437 #define FLASH_DATA2_DATA2_Msk                                              (0xffffffffUL)   /*!< FLASH DATA2: DATA2 (Bitfield-Mask: 0xffffffff) */
2438 #define FLASH_DATA2_DATA2                                                  FLASH_DATA2_DATA2_Msk
2439 #define FLASH_DATA2_DATA2_0                                                (0x1U << FLASH_DATA2_DATA2_Pos)
2440 #define FLASH_DATA2_DATA2_1                                                (0x2U << FLASH_DATA2_DATA2_Pos)
2441 #define FLASH_DATA2_DATA2_2                                                (0x4U << FLASH_DATA2_DATA2_Pos)
2442 #define FLASH_DATA2_DATA2_3                                                (0x8U << FLASH_DATA2_DATA2_Pos)
2443 #define FLASH_DATA2_DATA2_4                                                (0x10U << FLASH_DATA2_DATA2_Pos)
2444 #define FLASH_DATA2_DATA2_5                                                (0x20U << FLASH_DATA2_DATA2_Pos)
2445 #define FLASH_DATA2_DATA2_6                                                (0x40U << FLASH_DATA2_DATA2_Pos)
2446 #define FLASH_DATA2_DATA2_7                                                (0x80U << FLASH_DATA2_DATA2_Pos)
2447 #define FLASH_DATA2_DATA2_8                                                (0x100U << FLASH_DATA2_DATA2_Pos)
2448 #define FLASH_DATA2_DATA2_9                                                (0x200U << FLASH_DATA2_DATA2_Pos)
2449 #define FLASH_DATA2_DATA2_10                                               (0x400U << FLASH_DATA2_DATA2_Pos)
2450 #define FLASH_DATA2_DATA2_11                                               (0x800U << FLASH_DATA2_DATA2_Pos)
2451 #define FLASH_DATA2_DATA2_12                                               (0x1000U << FLASH_DATA2_DATA2_Pos)
2452 #define FLASH_DATA2_DATA2_13                                               (0x2000U << FLASH_DATA2_DATA2_Pos)
2453 #define FLASH_DATA2_DATA2_14                                               (0x4000U << FLASH_DATA2_DATA2_Pos)
2454 #define FLASH_DATA2_DATA2_15                                               (0x8000U << FLASH_DATA2_DATA2_Pos)
2455 #define FLASH_DATA2_DATA2_16                                               (0x10000U << FLASH_DATA2_DATA2_Pos)
2456 #define FLASH_DATA2_DATA2_17                                               (0x20000U << FLASH_DATA2_DATA2_Pos)
2457 #define FLASH_DATA2_DATA2_18                                               (0x40000U << FLASH_DATA2_DATA2_Pos)
2458 #define FLASH_DATA2_DATA2_19                                               (0x80000U << FLASH_DATA2_DATA2_Pos)
2459 #define FLASH_DATA2_DATA2_20                                               (0x100000U << FLASH_DATA2_DATA2_Pos)
2460 #define FLASH_DATA2_DATA2_21                                               (0x200000U << FLASH_DATA2_DATA2_Pos)
2461 #define FLASH_DATA2_DATA2_22                                               (0x400000U << FLASH_DATA2_DATA2_Pos)
2462 #define FLASH_DATA2_DATA2_23                                               (0x800000U << FLASH_DATA2_DATA2_Pos)
2463 #define FLASH_DATA2_DATA2_24                                               (0x1000000U << FLASH_DATA2_DATA2_Pos)
2464 #define FLASH_DATA2_DATA2_25                                               (0x2000000U << FLASH_DATA2_DATA2_Pos)
2465 #define FLASH_DATA2_DATA2_26                                               (0x4000000U << FLASH_DATA2_DATA2_Pos)
2466 #define FLASH_DATA2_DATA2_27                                               (0x8000000U << FLASH_DATA2_DATA2_Pos)
2467 #define FLASH_DATA2_DATA2_28                                               (0x10000000U << FLASH_DATA2_DATA2_Pos)
2468 #define FLASH_DATA2_DATA2_29                                               (0x20000000U << FLASH_DATA2_DATA2_Pos)
2469 #define FLASH_DATA2_DATA2_30                                               (0x40000000U << FLASH_DATA2_DATA2_Pos)
2470 #define FLASH_DATA2_DATA2_31                                               (0x80000000UL << FLASH_DATA2_DATA2_Pos)
2471 
2472 /* =====================================================    DATA3    ===================================================== */
2473 #define FLASH_DATA3_DATA3_Pos                                              (0UL)    /*!<FLASH DATA3: DATA3 (Bit 0) */
2474 #define FLASH_DATA3_DATA3_Msk                                              (0xffffffffUL)   /*!< FLASH DATA3: DATA3 (Bitfield-Mask: 0xffffffff) */
2475 #define FLASH_DATA3_DATA3                                                  FLASH_DATA3_DATA3_Msk
2476 #define FLASH_DATA3_DATA3_0                                                (0x1U << FLASH_DATA3_DATA3_Pos)
2477 #define FLASH_DATA3_DATA3_1                                                (0x2U << FLASH_DATA3_DATA3_Pos)
2478 #define FLASH_DATA3_DATA3_2                                                (0x4U << FLASH_DATA3_DATA3_Pos)
2479 #define FLASH_DATA3_DATA3_3                                                (0x8U << FLASH_DATA3_DATA3_Pos)
2480 #define FLASH_DATA3_DATA3_4                                                (0x10U << FLASH_DATA3_DATA3_Pos)
2481 #define FLASH_DATA3_DATA3_5                                                (0x20U << FLASH_DATA3_DATA3_Pos)
2482 #define FLASH_DATA3_DATA3_6                                                (0x40U << FLASH_DATA3_DATA3_Pos)
2483 #define FLASH_DATA3_DATA3_7                                                (0x80U << FLASH_DATA3_DATA3_Pos)
2484 #define FLASH_DATA3_DATA3_8                                                (0x100U << FLASH_DATA3_DATA3_Pos)
2485 #define FLASH_DATA3_DATA3_9                                                (0x200U << FLASH_DATA3_DATA3_Pos)
2486 #define FLASH_DATA3_DATA3_10                                               (0x400U << FLASH_DATA3_DATA3_Pos)
2487 #define FLASH_DATA3_DATA3_11                                               (0x800U << FLASH_DATA3_DATA3_Pos)
2488 #define FLASH_DATA3_DATA3_12                                               (0x1000U << FLASH_DATA3_DATA3_Pos)
2489 #define FLASH_DATA3_DATA3_13                                               (0x2000U << FLASH_DATA3_DATA3_Pos)
2490 #define FLASH_DATA3_DATA3_14                                               (0x4000U << FLASH_DATA3_DATA3_Pos)
2491 #define FLASH_DATA3_DATA3_15                                               (0x8000U << FLASH_DATA3_DATA3_Pos)
2492 #define FLASH_DATA3_DATA3_16                                               (0x10000U << FLASH_DATA3_DATA3_Pos)
2493 #define FLASH_DATA3_DATA3_17                                               (0x20000U << FLASH_DATA3_DATA3_Pos)
2494 #define FLASH_DATA3_DATA3_18                                               (0x40000U << FLASH_DATA3_DATA3_Pos)
2495 #define FLASH_DATA3_DATA3_19                                               (0x80000U << FLASH_DATA3_DATA3_Pos)
2496 #define FLASH_DATA3_DATA3_20                                               (0x100000U << FLASH_DATA3_DATA3_Pos)
2497 #define FLASH_DATA3_DATA3_21                                               (0x200000U << FLASH_DATA3_DATA3_Pos)
2498 #define FLASH_DATA3_DATA3_22                                               (0x400000U << FLASH_DATA3_DATA3_Pos)
2499 #define FLASH_DATA3_DATA3_23                                               (0x800000U << FLASH_DATA3_DATA3_Pos)
2500 #define FLASH_DATA3_DATA3_24                                               (0x1000000U << FLASH_DATA3_DATA3_Pos)
2501 #define FLASH_DATA3_DATA3_25                                               (0x2000000U << FLASH_DATA3_DATA3_Pos)
2502 #define FLASH_DATA3_DATA3_26                                               (0x4000000U << FLASH_DATA3_DATA3_Pos)
2503 #define FLASH_DATA3_DATA3_27                                               (0x8000000U << FLASH_DATA3_DATA3_Pos)
2504 #define FLASH_DATA3_DATA3_28                                               (0x10000000U << FLASH_DATA3_DATA3_Pos)
2505 #define FLASH_DATA3_DATA3_29                                               (0x20000000U << FLASH_DATA3_DATA3_Pos)
2506 #define FLASH_DATA3_DATA3_30                                               (0x40000000U << FLASH_DATA3_DATA3_Pos)
2507 #define FLASH_DATA3_DATA3_31                                               (0x80000000UL << FLASH_DATA3_DATA3_Pos)
2508 
2509 
2510 /* =========================================================================================================================== */
2511 /*=====================                                       SPI                                       ===================== */
2512 /* =========================================================================================================================== */
2513 
2514 /* =====================================================    CR1    ===================================================== */
2515 #define SPI_CR1_BIDIMODE_Pos                                               (15UL)   /*!<SPI CR1: BIDIMODE (Bit 15) */
2516 #define SPI_CR1_BIDIMODE_Msk                                               (0x8000UL)   /*!< SPI CR1: BIDIMODE (Bitfield-Mask: 0x01) */
2517 #define SPI_CR1_BIDIMODE                                                   SPI_CR1_BIDIMODE_Msk
2518 #define SPI_CR1_BIDIOE_Pos                                                 (14UL)   /*!<SPI CR1: BIDIOE (Bit 14) */
2519 #define SPI_CR1_BIDIOE_Msk                                                 (0x4000UL)   /*!< SPI CR1: BIDIOE (Bitfield-Mask: 0x01) */
2520 #define SPI_CR1_BIDIOE                                                     SPI_CR1_BIDIOE_Msk
2521 #define SPI_CR1_CRCEN_Pos                                                  (13UL)   /*!<SPI CR1: CRCEN (Bit 13) */
2522 #define SPI_CR1_CRCEN_Msk                                                  (0x2000UL)   /*!< SPI CR1: CRCEN (Bitfield-Mask: 0x01) */
2523 #define SPI_CR1_CRCEN                                                      SPI_CR1_CRCEN_Msk
2524 #define SPI_CR1_CRCNEXT_Pos                                                (12UL)   /*!<SPI CR1: CRCNEXT (Bit 12) */
2525 #define SPI_CR1_CRCNEXT_Msk                                                (0x1000UL)   /*!< SPI CR1: CRCNEXT (Bitfield-Mask: 0x01) */
2526 #define SPI_CR1_CRCNEXT                                                    SPI_CR1_CRCNEXT_Msk
2527 #define SPI_CR1_CRCL_Pos                                                   (11UL)   /*!<SPI CR1: CRCL (Bit 11) */
2528 #define SPI_CR1_CRCL_Msk                                                   (0x800UL)    /*!< SPI CR1: CRCL (Bitfield-Mask: 0x01) */
2529 #define SPI_CR1_CRCL                                                       SPI_CR1_CRCL_Msk
2530 #define SPI_CR1_RXONLY_Pos                                                 (10UL)   /*!<SPI CR1: RXONLY (Bit 10) */
2531 #define SPI_CR1_RXONLY_Msk                                                 (0x400UL)    /*!< SPI CR1: RXONLY (Bitfield-Mask: 0x01) */
2532 #define SPI_CR1_RXONLY                                                     SPI_CR1_RXONLY_Msk
2533 #define SPI_CR1_SSM_Pos                                                    (9UL)    /*!<SPI CR1: SSM (Bit 9) */
2534 #define SPI_CR1_SSM_Msk                                                    (0x200UL)    /*!< SPI CR1: SSM (Bitfield-Mask: 0x01) */
2535 #define SPI_CR1_SSM                                                        SPI_CR1_SSM_Msk
2536 #define SPI_CR1_SSI_Pos                                                    (8UL)    /*!<SPI CR1: SSI (Bit 8) */
2537 #define SPI_CR1_SSI_Msk                                                    (0x100UL)    /*!< SPI CR1: SSI (Bitfield-Mask: 0x01) */
2538 #define SPI_CR1_SSI                                                        SPI_CR1_SSI_Msk
2539 #define SPI_CR1_LSBFIRST_Pos                                               (7UL)    /*!<SPI CR1: LSBFIRST (Bit 7) */
2540 #define SPI_CR1_LSBFIRST_Msk                                               (0x80UL)   /*!< SPI CR1: LSBFIRST (Bitfield-Mask: 0x01) */
2541 #define SPI_CR1_LSBFIRST                                                   SPI_CR1_LSBFIRST_Msk
2542 #define SPI_CR1_SPE_Pos                                                    (6UL)    /*!<SPI CR1: SPE (Bit 6) */
2543 #define SPI_CR1_SPE_Msk                                                    (0x40UL)   /*!< SPI CR1: SPE (Bitfield-Mask: 0x01) */
2544 #define SPI_CR1_SPE                                                        SPI_CR1_SPE_Msk
2545 #define SPI_CR1_BR_Pos                                                     (3UL)    /*!<SPI CR1: BR (Bit 3) */
2546 #define SPI_CR1_BR_Msk                                                     (0x38UL)   /*!< SPI CR1: BR (Bitfield-Mask: 0x07) */
2547 #define SPI_CR1_BR                                                         SPI_CR1_BR_Msk
2548 #define SPI_CR1_BR_0                                                       (0x1U << SPI_CR1_BR_Pos)
2549 #define SPI_CR1_BR_1                                                       (0x2U << SPI_CR1_BR_Pos)
2550 #define SPI_CR1_BR_2                                                       (0x4U << SPI_CR1_BR_Pos)
2551 #define SPI_CR1_MSTR_Pos                                                   (2UL)    /*!<SPI CR1: MSTR (Bit 2) */
2552 #define SPI_CR1_MSTR_Msk                                                   (0x4UL)    /*!< SPI CR1: MSTR (Bitfield-Mask: 0x01) */
2553 #define SPI_CR1_MSTR                                                       SPI_CR1_MSTR_Msk
2554 #define SPI_CR1_CPOL_Pos                                                   (1UL)    /*!<SPI CR1: CPOL (Bit 1) */
2555 #define SPI_CR1_CPOL_Msk                                                   (0x2UL)    /*!< SPI CR1: CPOL (Bitfield-Mask: 0x01) */
2556 #define SPI_CR1_CPOL                                                       SPI_CR1_CPOL_Msk
2557 #define SPI_CR1_CPHA_Pos                                                   (0UL)    /*!<SPI CR1: CPHA (Bit 0) */
2558 #define SPI_CR1_CPHA_Msk                                                   (0x1UL)    /*!< SPI CR1: CPHA (Bitfield-Mask: 0x01) */
2559 #define SPI_CR1_CPHA                                                       SPI_CR1_CPHA_Msk
2560 
2561 /* =====================================================    CR2    ===================================================== */
2562 #define SPI_CR2_LDMATX_Pos                                                 (14UL)   /*!<SPI CR2: LDMATX (Bit 14) */
2563 #define SPI_CR2_LDMATX_Msk                                                 (0x4000UL)   /*!< SPI CR2: LDMATX (Bitfield-Mask: 0x01) */
2564 #define SPI_CR2_LDMATX                                                     SPI_CR2_LDMATX_Msk
2565 #define SPI_CR2_LDMARX_Pos                                                 (13UL)   /*!<SPI CR2: LDMARX (Bit 13) */
2566 #define SPI_CR2_LDMARX_Msk                                                 (0x2000UL)   /*!< SPI CR2: LDMARX (Bitfield-Mask: 0x01) */
2567 #define SPI_CR2_LDMARX                                                     SPI_CR2_LDMARX_Msk
2568 #define SPI_CR2_FRXTH_Pos                                                  (12UL)   /*!<SPI CR2: FRXTH (Bit 12) */
2569 #define SPI_CR2_FRXTH_Msk                                                  (0x1000UL)   /*!< SPI CR2: FRXTH (Bitfield-Mask: 0x01) */
2570 #define SPI_CR2_FRXTH                                                      SPI_CR2_FRXTH_Msk
2571 #define SPI_CR2_DS_Pos                                                     (8UL)    /*!<SPI CR2: DS (Bit 8) */
2572 #define SPI_CR2_DS_Msk                                                     (0xf00UL)    /*!< SPI CR2: DS (Bitfield-Mask: 0x0f) */
2573 #define SPI_CR2_DS                                                         SPI_CR2_DS_Msk
2574 #define SPI_CR2_DS_0                                                       (0x1U << SPI_CR2_DS_Pos)
2575 #define SPI_CR2_DS_1                                                       (0x2U << SPI_CR2_DS_Pos)
2576 #define SPI_CR2_DS_2                                                       (0x4U << SPI_CR2_DS_Pos)
2577 #define SPI_CR2_DS_3                                                       (0x8U << SPI_CR2_DS_Pos)
2578 #define SPI_CR2_TXEIE_Pos                                                  (7UL)    /*!<SPI CR2: TXEIE (Bit 7) */
2579 #define SPI_CR2_TXEIE_Msk                                                  (0x80UL)   /*!< SPI CR2: TXEIE (Bitfield-Mask: 0x01) */
2580 #define SPI_CR2_TXEIE                                                      SPI_CR2_TXEIE_Msk
2581 #define SPI_CR2_RXNEIE_Pos                                                 (6UL)    /*!<SPI CR2: RXNEIE (Bit 6) */
2582 #define SPI_CR2_RXNEIE_Msk                                                 (0x40UL)   /*!< SPI CR2: RXNEIE (Bitfield-Mask: 0x01) */
2583 #define SPI_CR2_RXNEIE                                                     SPI_CR2_RXNEIE_Msk
2584 #define SPI_CR2_ERRIE_Pos                                                  (5UL)    /*!<SPI CR2: ERRIE (Bit 5) */
2585 #define SPI_CR2_ERRIE_Msk                                                  (0x20UL)   /*!< SPI CR2: ERRIE (Bitfield-Mask: 0x01) */
2586 #define SPI_CR2_ERRIE                                                      SPI_CR2_ERRIE_Msk
2587 #define SPI_CR2_FRF_Pos                                                    (4UL)    /*!<SPI CR2: FRF (Bit 4) */
2588 #define SPI_CR2_FRF_Msk                                                    (0x10UL)   /*!< SPI CR2: FRF (Bitfield-Mask: 0x01) */
2589 #define SPI_CR2_FRF                                                        SPI_CR2_FRF_Msk
2590 #define SPI_CR2_NSSP_Pos                                                   (3UL)    /*!<SPI CR2: NSSP (Bit 3) */
2591 #define SPI_CR2_NSSP_Msk                                                   (0x8UL)    /*!< SPI CR2: NSSP (Bitfield-Mask: 0x01) */
2592 #define SPI_CR2_NSSP                                                       SPI_CR2_NSSP_Msk
2593 #define SPI_CR2_SSOE_Pos                                                   (2UL)    /*!<SPI CR2: SSOE (Bit 2) */
2594 #define SPI_CR2_SSOE_Msk                                                   (0x4UL)    /*!< SPI CR2: SSOE (Bitfield-Mask: 0x01) */
2595 #define SPI_CR2_SSOE                                                       SPI_CR2_SSOE_Msk
2596 #define SPI_CR2_TXDMAEN_Pos                                                (1UL)    /*!<SPI CR2: TXDMAEN (Bit 1) */
2597 #define SPI_CR2_TXDMAEN_Msk                                                (0x2UL)    /*!< SPI CR2: TXDMAEN (Bitfield-Mask: 0x01) */
2598 #define SPI_CR2_TXDMAEN                                                    SPI_CR2_TXDMAEN_Msk
2599 #define SPI_CR2_RXDMAEN_Pos                                                (0UL)    /*!<SPI CR2: RXDMAEN (Bit 0) */
2600 #define SPI_CR2_RXDMAEN_Msk                                                (0x1UL)    /*!< SPI CR2: RXDMAEN (Bitfield-Mask: 0x01) */
2601 #define SPI_CR2_RXDMAEN                                                    SPI_CR2_RXDMAEN_Msk
2602 
2603 /* =====================================================    SR    ===================================================== */
2604 #define SPI_SR_FTLVL_Pos                                                   (11UL)   /*!<SPI SR: FTLVL (Bit 11) */
2605 #define SPI_SR_FTLVL_Msk                                                   (0x1800UL)   /*!< SPI SR: FTLVL (Bitfield-Mask: 0x03) */
2606 #define SPI_SR_FTLVL                                                       SPI_SR_FTLVL_Msk
2607 #define SPI_SR_FTLVL_0                                                     (0x1U << SPI_SR_FTLVL_Pos)
2608 #define SPI_SR_FTLVL_1                                                     (0x2U << SPI_SR_FTLVL_Pos)
2609 #define SPI_SR_FRLVL_Pos                                                   (9UL)    /*!<SPI SR: FRLVL (Bit 9) */
2610 #define SPI_SR_FRLVL_Msk                                                   (0x600UL)    /*!< SPI SR: FRLVL (Bitfield-Mask: 0x03) */
2611 #define SPI_SR_FRLVL                                                       SPI_SR_FRLVL_Msk
2612 #define SPI_SR_FRLVL_0                                                     (0x1U << SPI_SR_FRLVL_Pos)
2613 #define SPI_SR_FRLVL_1                                                     (0x2U << SPI_SR_FRLVL_Pos)
2614 #define SPI_SR_FRE_Pos                                                     (8UL)    /*!<SPI SR: FRE (Bit 8) */
2615 #define SPI_SR_FRE_Msk                                                     (0x100UL)    /*!< SPI SR: FRE (Bitfield-Mask: 0x01) */
2616 #define SPI_SR_FRE                                                         SPI_SR_FRE_Msk
2617 #define SPI_SR_BSY_Pos                                                     (7UL)    /*!<SPI SR: BSY (Bit 7) */
2618 #define SPI_SR_BSY_Msk                                                     (0x80UL)   /*!< SPI SR: BSY (Bitfield-Mask: 0x01) */
2619 #define SPI_SR_BSY                                                         SPI_SR_BSY_Msk
2620 #define SPI_SR_OVR_Pos                                                     (6UL)    /*!<SPI SR: OVR (Bit 6) */
2621 #define SPI_SR_OVR_Msk                                                     (0x40UL)   /*!< SPI SR: OVR (Bitfield-Mask: 0x01) */
2622 #define SPI_SR_OVR                                                         SPI_SR_OVR_Msk
2623 #define SPI_SR_MODF_Pos                                                    (5UL)    /*!<SPI SR: MODF (Bit 5) */
2624 #define SPI_SR_MODF_Msk                                                    (0x20UL)   /*!< SPI SR: MODF (Bitfield-Mask: 0x01) */
2625 #define SPI_SR_MODF                                                        SPI_SR_MODF_Msk
2626 #define SPI_SR_CRCERR_Pos                                                  (4UL)    /*!<SPI SR: CRCERR (Bit 4) */
2627 #define SPI_SR_CRCERR_Msk                                                  (0x10UL)   /*!< SPI SR: CRCERR (Bitfield-Mask: 0x01) */
2628 #define SPI_SR_CRCERR                                                      SPI_SR_CRCERR_Msk
2629 #define SPI_SR_UDR_Pos                                                     (3UL)    /*!<SPI SR: UDR (Bit 3) */
2630 #define SPI_SR_UDR_Msk                                                     (0x8UL)    /*!< SPI SR: UDR (Bitfield-Mask: 0x01) */
2631 #define SPI_SR_UDR                                                         SPI_SR_UDR_Msk
2632 #define SPI_SR_CHSIDE_Pos                                                  (2UL)    /*!<SPI SR: CHSIDE (Bit 2) */
2633 #define SPI_SR_CHSIDE_Msk                                                  (0x4UL)    /*!< SPI SR: CHSIDE (Bitfield-Mask: 0x01) */
2634 #define SPI_SR_CHSIDE                                                      SPI_SR_CHSIDE_Msk
2635 #define SPI_SR_TXE_Pos                                                     (1UL)    /*!<SPI SR: TXE (Bit 1) */
2636 #define SPI_SR_TXE_Msk                                                     (0x2UL)    /*!< SPI SR: TXE (Bitfield-Mask: 0x01) */
2637 #define SPI_SR_TXE                                                         SPI_SR_TXE_Msk
2638 #define SPI_SR_RXNE_Pos                                                    (0UL)    /*!<SPI SR: RXNE (Bit 0) */
2639 #define SPI_SR_RXNE_Msk                                                    (0x1UL)    /*!< SPI SR: RXNE (Bitfield-Mask: 0x01) */
2640 #define SPI_SR_RXNE                                                        SPI_SR_RXNE_Msk
2641 
2642 /* =====================================================    DR    ===================================================== */
2643 #define SPI_DR_DR_Pos                                                      (0UL)    /*!<SPI DR: DR (Bit 0) */
2644 #define SPI_DR_DR_Msk                                                      (0xffffUL)   /*!< SPI DR: DR (Bitfield-Mask: 0xffff) */
2645 #define SPI_DR_DR                                                          SPI_DR_DR_Msk
2646 #define SPI_DR_DR_0                                                        (0x1U << SPI_DR_DR_Pos)
2647 #define SPI_DR_DR_1                                                        (0x2U << SPI_DR_DR_Pos)
2648 #define SPI_DR_DR_2                                                        (0x4U << SPI_DR_DR_Pos)
2649 #define SPI_DR_DR_3                                                        (0x8U << SPI_DR_DR_Pos)
2650 #define SPI_DR_DR_4                                                        (0x10U << SPI_DR_DR_Pos)
2651 #define SPI_DR_DR_5                                                        (0x20U << SPI_DR_DR_Pos)
2652 #define SPI_DR_DR_6                                                        (0x40U << SPI_DR_DR_Pos)
2653 #define SPI_DR_DR_7                                                        (0x80U << SPI_DR_DR_Pos)
2654 #define SPI_DR_DR_8                                                        (0x100U << SPI_DR_DR_Pos)
2655 #define SPI_DR_DR_9                                                        (0x200U << SPI_DR_DR_Pos)
2656 #define SPI_DR_DR_10                                                       (0x400U << SPI_DR_DR_Pos)
2657 #define SPI_DR_DR_11                                                       (0x800U << SPI_DR_DR_Pos)
2658 #define SPI_DR_DR_12                                                       (0x1000U << SPI_DR_DR_Pos)
2659 #define SPI_DR_DR_13                                                       (0x2000U << SPI_DR_DR_Pos)
2660 #define SPI_DR_DR_14                                                       (0x4000U << SPI_DR_DR_Pos)
2661 #define SPI_DR_DR_15                                                       (0x8000U << SPI_DR_DR_Pos)
2662 
2663 /* =====================================================    CRCPR    ===================================================== */
2664 #define SPI_CRCPR_CRCPOLY_Pos                                              (0UL)    /*!<SPI CRCPR: CRCPOLY (Bit 0) */
2665 #define SPI_CRCPR_CRCPOLY_Msk                                              (0xffffUL)   /*!< SPI CRCPR: CRCPOLY (Bitfield-Mask: 0xffff) */
2666 #define SPI_CRCPR_CRCPOLY                                                  SPI_CRCPR_CRCPOLY_Msk
2667 #define SPI_CRCPR_CRCPOLY_0                                                (0x1U << SPI_CRCPR_CRCPOLY_Pos)
2668 #define SPI_CRCPR_CRCPOLY_1                                                (0x2U << SPI_CRCPR_CRCPOLY_Pos)
2669 #define SPI_CRCPR_CRCPOLY_2                                                (0x4U << SPI_CRCPR_CRCPOLY_Pos)
2670 #define SPI_CRCPR_CRCPOLY_3                                                (0x8U << SPI_CRCPR_CRCPOLY_Pos)
2671 #define SPI_CRCPR_CRCPOLY_4                                                (0x10U << SPI_CRCPR_CRCPOLY_Pos)
2672 #define SPI_CRCPR_CRCPOLY_5                                                (0x20U << SPI_CRCPR_CRCPOLY_Pos)
2673 #define SPI_CRCPR_CRCPOLY_6                                                (0x40U << SPI_CRCPR_CRCPOLY_Pos)
2674 #define SPI_CRCPR_CRCPOLY_7                                                (0x80U << SPI_CRCPR_CRCPOLY_Pos)
2675 #define SPI_CRCPR_CRCPOLY_8                                                (0x100U << SPI_CRCPR_CRCPOLY_Pos)
2676 #define SPI_CRCPR_CRCPOLY_9                                                (0x200U << SPI_CRCPR_CRCPOLY_Pos)
2677 #define SPI_CRCPR_CRCPOLY_10                                               (0x400U << SPI_CRCPR_CRCPOLY_Pos)
2678 #define SPI_CRCPR_CRCPOLY_11                                               (0x800U << SPI_CRCPR_CRCPOLY_Pos)
2679 #define SPI_CRCPR_CRCPOLY_12                                               (0x1000U << SPI_CRCPR_CRCPOLY_Pos)
2680 #define SPI_CRCPR_CRCPOLY_13                                               (0x2000U << SPI_CRCPR_CRCPOLY_Pos)
2681 #define SPI_CRCPR_CRCPOLY_14                                               (0x4000U << SPI_CRCPR_CRCPOLY_Pos)
2682 #define SPI_CRCPR_CRCPOLY_15                                               (0x8000U << SPI_CRCPR_CRCPOLY_Pos)
2683 
2684 /* =====================================================    RXCRCR    ===================================================== */
2685 #define SPI_RXCRCR_RXCRC_Pos                                               (0UL)    /*!<SPI RXCRCR: RXCRC (Bit 0) */
2686 #define SPI_RXCRCR_RXCRC_Msk                                               (0xffffUL)   /*!< SPI RXCRCR: RXCRC (Bitfield-Mask: 0xffff) */
2687 #define SPI_RXCRCR_RXCRC                                                   SPI_RXCRCR_RXCRC_Msk
2688 #define SPI_RXCRCR_RXCRC_0                                                 (0x1U << SPI_RXCRCR_RXCRC_Pos)
2689 #define SPI_RXCRCR_RXCRC_1                                                 (0x2U << SPI_RXCRCR_RXCRC_Pos)
2690 #define SPI_RXCRCR_RXCRC_2                                                 (0x4U << SPI_RXCRCR_RXCRC_Pos)
2691 #define SPI_RXCRCR_RXCRC_3                                                 (0x8U << SPI_RXCRCR_RXCRC_Pos)
2692 #define SPI_RXCRCR_RXCRC_4                                                 (0x10U << SPI_RXCRCR_RXCRC_Pos)
2693 #define SPI_RXCRCR_RXCRC_5                                                 (0x20U << SPI_RXCRCR_RXCRC_Pos)
2694 #define SPI_RXCRCR_RXCRC_6                                                 (0x40U << SPI_RXCRCR_RXCRC_Pos)
2695 #define SPI_RXCRCR_RXCRC_7                                                 (0x80U << SPI_RXCRCR_RXCRC_Pos)
2696 #define SPI_RXCRCR_RXCRC_8                                                 (0x100U << SPI_RXCRCR_RXCRC_Pos)
2697 #define SPI_RXCRCR_RXCRC_9                                                 (0x200U << SPI_RXCRCR_RXCRC_Pos)
2698 #define SPI_RXCRCR_RXCRC_10                                                (0x400U << SPI_RXCRCR_RXCRC_Pos)
2699 #define SPI_RXCRCR_RXCRC_11                                                (0x800U << SPI_RXCRCR_RXCRC_Pos)
2700 #define SPI_RXCRCR_RXCRC_12                                                (0x1000U << SPI_RXCRCR_RXCRC_Pos)
2701 #define SPI_RXCRCR_RXCRC_13                                                (0x2000U << SPI_RXCRCR_RXCRC_Pos)
2702 #define SPI_RXCRCR_RXCRC_14                                                (0x4000U << SPI_RXCRCR_RXCRC_Pos)
2703 #define SPI_RXCRCR_RXCRC_15                                                (0x8000U << SPI_RXCRCR_RXCRC_Pos)
2704 
2705 /* =====================================================    TXCRCR    ===================================================== */
2706 #define SPI_TXCRCR_TXCRC_Pos                                               (0UL)    /*!<SPI TXCRCR: TXCRC (Bit 0) */
2707 #define SPI_TXCRCR_TXCRC_Msk                                               (0xffffUL)   /*!< SPI TXCRCR: TXCRC (Bitfield-Mask: 0xffff) */
2708 #define SPI_TXCRCR_TXCRC                                                   SPI_TXCRCR_TXCRC_Msk
2709 #define SPI_TXCRCR_TXCRC_0                                                 (0x1U << SPI_TXCRCR_TXCRC_Pos)
2710 #define SPI_TXCRCR_TXCRC_1                                                 (0x2U << SPI_TXCRCR_TXCRC_Pos)
2711 #define SPI_TXCRCR_TXCRC_2                                                 (0x4U << SPI_TXCRCR_TXCRC_Pos)
2712 #define SPI_TXCRCR_TXCRC_3                                                 (0x8U << SPI_TXCRCR_TXCRC_Pos)
2713 #define SPI_TXCRCR_TXCRC_4                                                 (0x10U << SPI_TXCRCR_TXCRC_Pos)
2714 #define SPI_TXCRCR_TXCRC_5                                                 (0x20U << SPI_TXCRCR_TXCRC_Pos)
2715 #define SPI_TXCRCR_TXCRC_6                                                 (0x40U << SPI_TXCRCR_TXCRC_Pos)
2716 #define SPI_TXCRCR_TXCRC_7                                                 (0x80U << SPI_TXCRCR_TXCRC_Pos)
2717 #define SPI_TXCRCR_TXCRC_8                                                 (0x100U << SPI_TXCRCR_TXCRC_Pos)
2718 #define SPI_TXCRCR_TXCRC_9                                                 (0x200U << SPI_TXCRCR_TXCRC_Pos)
2719 #define SPI_TXCRCR_TXCRC_10                                                (0x400U << SPI_TXCRCR_TXCRC_Pos)
2720 #define SPI_TXCRCR_TXCRC_11                                                (0x800U << SPI_TXCRCR_TXCRC_Pos)
2721 #define SPI_TXCRCR_TXCRC_12                                                (0x1000U << SPI_TXCRCR_TXCRC_Pos)
2722 #define SPI_TXCRCR_TXCRC_13                                                (0x2000U << SPI_TXCRCR_TXCRC_Pos)
2723 #define SPI_TXCRCR_TXCRC_14                                                (0x4000U << SPI_TXCRCR_TXCRC_Pos)
2724 #define SPI_TXCRCR_TXCRC_15                                                (0x8000U << SPI_TXCRCR_TXCRC_Pos)
2725 
2726 /* =====================================================    I2SCFGR    ===================================================== */
2727 #define SPI_I2SCFGR_ASTRTEN_Pos                                            (12UL)   /*!<SPI I2SCFGR: ASTRTEN (Bit 12) */
2728 #define SPI_I2SCFGR_ASTRTEN_Msk                                            (0x1000UL)    /*!< SPI I2SCFGR: ASTRTEN (Bitfield-Mask: 0x01) */
2729 #define SPI_I2SCFGR_ASTRTEN                                                SPI_I2SCFGR_ASTRTEN_Msk
2730 #define SPI_I2SCFGR_I2SMOD_Pos                                             (11UL)   /*!<SPI I2SCFGR: I2SMOD (Bit 11) */
2731 #define SPI_I2SCFGR_I2SMOD_Msk                                             (0x800UL)    /*!< SPI I2SCFGR: I2SMOD (Bitfield-Mask: 0x01) */
2732 #define SPI_I2SCFGR_I2SMOD                                                 SPI_I2SCFGR_I2SMOD_Msk
2733 #define SPI_I2SCFGR_I2SE_Pos                                               (10UL)   /*!<SPI I2SCFGR: I2SE (Bit 10) */
2734 #define SPI_I2SCFGR_I2SE_Msk                                               (0x400UL)    /*!< SPI I2SCFGR: I2SE (Bitfield-Mask: 0x01) */
2735 #define SPI_I2SCFGR_I2SE                                                   SPI_I2SCFGR_I2SE_Msk
2736 #define SPI_I2SCFGR_I2SCFG_Pos                                             (8UL)    /*!<SPI I2SCFGR: I2SCFG (Bit 8) */
2737 #define SPI_I2SCFGR_I2SCFG_Msk                                             (0x300UL)    /*!< SPI I2SCFGR: I2SCFG (Bitfield-Mask: 0x03) */
2738 #define SPI_I2SCFGR_I2SCFG                                                 SPI_I2SCFGR_I2SCFG_Msk
2739 #define SPI_I2SCFGR_I2SCFG_0                                               (0x1U << SPI_I2SCFGR_I2SCFG_Pos)
2740 #define SPI_I2SCFGR_I2SCFG_1                                               (0x2U << SPI_I2SCFGR_I2SCFG_Pos)
2741 #define SPI_I2SCFGR_PCMSYNC_Pos                                            (7UL)    /*!<SPI I2SCFGR: PCMSYNC (Bit 7) */
2742 #define SPI_I2SCFGR_PCMSYNC_Msk                                            (0x80UL)   /*!< SPI I2SCFGR: PCMSYNC (Bitfield-Mask: 0x01) */
2743 #define SPI_I2SCFGR_PCMSYNC                                                SPI_I2SCFGR_PCMSYNC_Msk
2744 #define SPI_I2SCFGR_I2SSTD_Pos                                             (4UL)    /*!<SPI I2SCFGR: I2SSTD (Bit 4) */
2745 #define SPI_I2SCFGR_I2SSTD_Msk                                             (0x30UL)   /*!< SPI I2SCFGR: I2SSTD (Bitfield-Mask: 0x03) */
2746 #define SPI_I2SCFGR_I2SSTD                                                 SPI_I2SCFGR_I2SSTD_Msk
2747 #define SPI_I2SCFGR_I2SSTD_0                                               (0x1U << SPI_I2SCFGR_I2SSTD_Pos)
2748 #define SPI_I2SCFGR_I2SSTD_1                                               (0x2U << SPI_I2SCFGR_I2SSTD_Pos)
2749 #define SPI_I2SCFGR_CKPOL_Pos                                              (3UL)    /*!<SPI I2SCFGR: CKPOL (Bit 3) */
2750 #define SPI_I2SCFGR_CKPOL_Msk                                              (0x8UL)    /*!< SPI I2SCFGR: CKPOL (Bitfield-Mask: 0x01) */
2751 #define SPI_I2SCFGR_CKPOL                                                  SPI_I2SCFGR_CKPOL_Msk
2752 #define SPI_I2SCFGR_DATLEN_Pos                                             (1UL)    /*!<SPI I2SCFGR: DATLEN (Bit 1) */
2753 #define SPI_I2SCFGR_DATLEN_Msk                                             (0x6UL)    /*!< SPI I2SCFGR: DATLEN (Bitfield-Mask: 0x03) */
2754 #define SPI_I2SCFGR_DATLEN                                                 SPI_I2SCFGR_DATLEN_Msk
2755 #define SPI_I2SCFGR_DATLEN_0                                               (0x1U << SPI_I2SCFGR_DATLEN_Pos)
2756 #define SPI_I2SCFGR_DATLEN_1                                               (0x2U << SPI_I2SCFGR_DATLEN_Pos)
2757 #define SPI_I2SCFGR_CHLEN_Pos                                              (0UL)    /*!<SPI I2SCFGR: CHLEN (Bit 0) */
2758 #define SPI_I2SCFGR_CHLEN_Msk                                              (0x1UL)    /*!< SPI I2SCFGR: CHLEN (Bitfield-Mask: 0x01) */
2759 #define SPI_I2SCFGR_CHLEN                                                  SPI_I2SCFGR_CHLEN_Msk
2760 
2761 /* =====================================================    I2SPR    ===================================================== */
2762 #define SPI_I2SPR_MCKOE_Pos                                                (9UL)    /*!<SPI I2SPR: MCKOE (Bit 9) */
2763 #define SPI_I2SPR_MCKOE_Msk                                                (0x200UL)    /*!< SPI I2SPR: MCKOE (Bitfield-Mask: 0x01) */
2764 #define SPI_I2SPR_MCKOE                                                    SPI_I2SPR_MCKOE_Msk
2765 #define SPI_I2SPR_ODD_Pos                                                  (8UL)    /*!<SPI I2SPR: ODD (Bit 8) */
2766 #define SPI_I2SPR_ODD_Msk                                                  (0x100UL)    /*!< SPI I2SPR: ODD (Bitfield-Mask: 0x01) */
2767 #define SPI_I2SPR_ODD                                                      SPI_I2SPR_ODD_Msk
2768 #define SPI_I2SPR_I2SDIV_Pos                                               (0UL)    /*!<SPI I2SPR: I2SDIV (Bit 0) */
2769 #define SPI_I2SPR_I2SDIV_Msk                                               (0xffUL)   /*!< SPI I2SPR: I2SDIV (Bitfield-Mask: 0xff) */
2770 #define SPI_I2SPR_I2SDIV                                                   SPI_I2SPR_I2SDIV_Msk
2771 #define SPI_I2SPR_I2SDIV_0                                                 (0x1U << SPI_I2SPR_I2SDIV_Pos)
2772 #define SPI_I2SPR_I2SDIV_1                                                 (0x2U << SPI_I2SPR_I2SDIV_Pos)
2773 #define SPI_I2SPR_I2SDIV_2                                                 (0x4U << SPI_I2SPR_I2SDIV_Pos)
2774 #define SPI_I2SPR_I2SDIV_3                                                 (0x8U << SPI_I2SPR_I2SDIV_Pos)
2775 #define SPI_I2SPR_I2SDIV_4                                                 (0x10U << SPI_I2SPR_I2SDIV_Pos)
2776 #define SPI_I2SPR_I2SDIV_5                                                 (0x20U << SPI_I2SPR_I2SDIV_Pos)
2777 #define SPI_I2SPR_I2SDIV_6                                                 (0x40U << SPI_I2SPR_I2SDIV_Pos)
2778 #define SPI_I2SPR_I2SDIV_7                                                 (0x80U << SPI_I2SPR_I2SDIV_Pos)
2779 
2780 
2781 /* =========================================================================================================================== */
2782 /*=====================                                       RCC                                       ===================== */
2783 /* =========================================================================================================================== */
2784 
2785 /* =====================================================    CR    ===================================================== */
2786 #define RCC_CR_HSERDY_Pos                                                  (17UL)   /*!<RCC CR: HSERDY (Bit 17) */
2787 #define RCC_CR_HSERDY_Msk                                                  (0x20000UL)    /*!< RCC CR: HSERDY (Bitfield-Mask: 0x01) */
2788 #define RCC_CR_HSERDY                                                      RCC_CR_HSERDY_Msk
2789 #define RCC_CR_HSEON_Pos                                                   (16UL)   /*!<RCC CR: HSEON (Bit 16) */
2790 #define RCC_CR_HSEON_Msk                                                   (0x10000UL)    /*!< RCC CR: HSEON (Bitfield-Mask: 0x01) */
2791 #define RCC_CR_HSEON                                                       RCC_CR_HSEON_Msk
2792 #define RCC_CR_FMRAT_Pos                                                   (15UL)   /*!<RCC CR: FMRAT (Bit 15) */
2793 #define RCC_CR_FMRAT_Msk                                                   (0x8000UL)   /*!< RCC CR: FMRAT (Bitfield-Mask: 0x01) */
2794 #define RCC_CR_FMRAT                                                       RCC_CR_FMRAT_Msk
2795 #define RCC_CR_HSIPLLRDY_Pos                                               (14UL)   /*!<RCC CR: HSIPLLRDY (Bit 14) */
2796 #define RCC_CR_HSIPLLRDY_Msk                                               (0x4000UL)   /*!< RCC CR: HSIPLLRDY (Bitfield-Mask: 0x01) */
2797 #define RCC_CR_HSIPLLRDY                                                   RCC_CR_HSIPLLRDY_Msk
2798 #define RCC_CR_HSIPLLON_Pos                                                (13UL)   /*!<RCC CR: HSIPLLON (Bit 13) */
2799 #define RCC_CR_HSIPLLON_Msk                                                (0x2000UL)   /*!< RCC CR: HSIPLLON (Bitfield-Mask: 0x01) */
2800 #define RCC_CR_HSIPLLON                                                    RCC_CR_HSIPLLON_Msk
2801 #define RCC_CR_HSEPLLBUFON_Pos                                             (12UL)   /*!<RCC CR: HSEPLLBUFON (Bit 12) */
2802 #define RCC_CR_HSEPLLBUFON_Msk                                             (0x1000UL)   /*!< RCC CR: HSEPLLBUFON (Bitfield-Mask: 0x01) */
2803 #define RCC_CR_HSEPLLBUFON                                                 RCC_CR_HSEPLLBUFON_Msk
2804 #define RCC_CR_HSIRDY_Pos                                                  (10UL)   /*!<RCC CR: HSIRDY (Bit 10) */
2805 #define RCC_CR_HSIRDY_Msk                                                  (0x400UL)    /*!< RCC CR: HSIRDY (Bitfield-Mask: 0x01) */
2806 #define RCC_CR_HSIRDY                                                      RCC_CR_HSIRDY_Msk
2807 #define RCC_CR_LOCKDET_NSTOP_Pos                                           (7UL)    /*!<RCC CR: LOCKDET_NSTOP (Bit 7) */
2808 #define RCC_CR_LOCKDET_NSTOP_Msk                                           (0x380UL)    /*!< RCC CR: LOCKDET_NSTOP (Bitfield-Mask: 0x07) */
2809 #define RCC_CR_LOCKDET_NSTOP                                               RCC_CR_LOCKDET_NSTOP_Msk
2810 #define RCC_CR_LOCKDET_NSTOP_0                                             (0x1U << RCC_CR_LOCKDET_NSTOP_Pos)
2811 #define RCC_CR_LOCKDET_NSTOP_1                                             (0x2U << RCC_CR_LOCKDET_NSTOP_Pos)
2812 #define RCC_CR_LOCKDET_NSTOP_2                                             (0x4U << RCC_CR_LOCKDET_NSTOP_Pos)
2813 #define RCC_CR_LSEBYP_Pos                                                  (6UL)    /*!<RCC CR: LSEBYP (Bit 6) */
2814 #define RCC_CR_LSEBYP_Msk                                                  (0x40UL)   /*!< RCC CR: LSEBYP (Bitfield-Mask: 0x01) */
2815 #define RCC_CR_LSEBYP                                                      RCC_CR_LSEBYP_Msk
2816 #define RCC_CR_LSERDY_Pos                                                  (5UL)    /*!<RCC CR: LSERDY (Bit 5) */
2817 #define RCC_CR_LSERDY_Msk                                                  (0x20UL)   /*!< RCC CR: LSERDY (Bitfield-Mask: 0x01) */
2818 #define RCC_CR_LSERDY                                                      RCC_CR_LSERDY_Msk
2819 #define RCC_CR_LSEON_Pos                                                   (4UL)    /*!<RCC CR: LSEON (Bit 4) */
2820 #define RCC_CR_LSEON_Msk                                                   (0x10UL)   /*!< RCC CR: LSEON (Bitfield-Mask: 0x01) */
2821 #define RCC_CR_LSEON                                                       RCC_CR_LSEON_Msk
2822 #define RCC_CR_LSIRDY_Pos                                                  (3UL)    /*!<RCC CR: LSIRDY (Bit 3) */
2823 #define RCC_CR_LSIRDY_Msk                                                  (0x8UL)    /*!< RCC CR: LSIRDY (Bitfield-Mask: 0x01) */
2824 #define RCC_CR_LSIRDY                                                      RCC_CR_LSIRDY_Msk
2825 #define RCC_CR_LSION_Pos                                                   (2UL)    /*!<RCC CR: LSION (Bit 2) */
2826 #define RCC_CR_LSION_Msk                                                   (0x4UL)    /*!< RCC CR: LSION (Bitfield-Mask: 0x01) */
2827 #define RCC_CR_LSION                                                       RCC_CR_LSION_Msk
2828 
2829 /* =====================================================    ICSCR    ===================================================== */
2830 #define RCC_ICSCR_HSITRIM_Pos                                              (24UL)   /*!<RCC ICSCR: HSITRIM (Bit 24) */
2831 #define RCC_ICSCR_HSITRIM_Msk                                              (0x3f000000UL)   /*!< RCC ICSCR: HSITRIM (Bitfield-Mask: 0x3f) */
2832 #define RCC_ICSCR_HSITRIM                                                  RCC_ICSCR_HSITRIM_Msk
2833 #define RCC_ICSCR_HSITRIM_0                                                (0x1U << RCC_ICSCR_HSITRIM_Pos)
2834 #define RCC_ICSCR_HSITRIM_1                                                (0x2U << RCC_ICSCR_HSITRIM_Pos)
2835 #define RCC_ICSCR_HSITRIM_2                                                (0x4U << RCC_ICSCR_HSITRIM_Pos)
2836 #define RCC_ICSCR_HSITRIM_3                                                (0x8U << RCC_ICSCR_HSITRIM_Pos)
2837 #define RCC_ICSCR_HSITRIM_4                                                (0x10U << RCC_ICSCR_HSITRIM_Pos)
2838 #define RCC_ICSCR_HSITRIM_5                                                (0x20U << RCC_ICSCR_HSITRIM_Pos)
2839 #define RCC_ICSCR_LSIBW_Pos                                                (2UL)    /*!<RCC ICSCR: LSIBW (Bit 2) */
2840 #define RCC_ICSCR_LSIBW_Msk                                                (0x3cUL)   /*!< RCC ICSCR: LSIBW (Bitfield-Mask: 0x0f) */
2841 #define RCC_ICSCR_LSIBW                                                    RCC_ICSCR_LSIBW_Msk
2842 #define RCC_ICSCR_LSIBW_0                                                  (0x1U << RCC_ICSCR_LSIBW_Pos)
2843 #define RCC_ICSCR_LSIBW_1                                                  (0x2U << RCC_ICSCR_LSIBW_Pos)
2844 #define RCC_ICSCR_LSIBW_2                                                  (0x4U << RCC_ICSCR_LSIBW_Pos)
2845 #define RCC_ICSCR_LSIBW_3                                                  (0x8U << RCC_ICSCR_LSIBW_Pos)
2846 #define RCC_ICSCR_LSITRIMOK_Pos                                            (1UL)    /*!<RCC ICSCR: LSITRIMOK (Bit 1) */
2847 #define RCC_ICSCR_LSITRIMOK_Msk                                            (0x2UL)    /*!< RCC ICSCR: LSITRIMOK (Bitfield-Mask: 0x01) */
2848 #define RCC_ICSCR_LSITRIMOK                                                RCC_ICSCR_LSITRIMOK_Msk
2849 #define RCC_ICSCR_LSITRIMEN_Pos                                            (0UL)    /*!<RCC ICSCR: LSITRIMEN (Bit 0) */
2850 #define RCC_ICSCR_LSITRIMEN_Msk                                            (0x1UL)    /*!< RCC ICSCR: LSITRIMEN (Bitfield-Mask: 0x01) */
2851 #define RCC_ICSCR_LSITRIMEN                                                RCC_ICSCR_LSITRIMEN_Msk
2852 
2853 /* =====================================================    CFGR    ===================================================== */
2854 #define RCC_CFGR_CCOPRE_Pos                                                (29UL)   /*!<RCC CFGR: CCOPRE (Bit 29) */
2855 #define RCC_CFGR_CCOPRE_Msk                                                (0xe0000000UL)   /*!< RCC CFGR: CCOPRE (Bitfield-Mask: 0x07) */
2856 #define RCC_CFGR_CCOPRE                                                    RCC_CFGR_CCOPRE_Msk
2857 #define RCC_CFGR_CCOPRE_0                                                  (0x1U << RCC_CFGR_CCOPRE_Pos)
2858 #define RCC_CFGR_CCOPRE_1                                                  (0x2U << RCC_CFGR_CCOPRE_Pos)
2859 #define RCC_CFGR_CCOPRE_2                                                  (0x4U << RCC_CFGR_CCOPRE_Pos)
2860 #define RCC_CFGR_MCOSEL_Pos                                                (26UL)   /*!<RCC CFGR: MCOSEL (Bit 26) */
2861 #define RCC_CFGR_MCOSEL_Msk                                                (0x1c000000UL)   /*!< RCC CFGR: MCOSEL (Bitfield-Mask: 0x07) */
2862 #define RCC_CFGR_MCOSEL                                                    RCC_CFGR_MCOSEL_Msk
2863 #define RCC_CFGR_MCOSEL_0                                                  (0x1U << RCC_CFGR_MCOSEL_Pos)
2864 #define RCC_CFGR_MCOSEL_1                                                  (0x2U << RCC_CFGR_MCOSEL_Pos)
2865 #define RCC_CFGR_MCOSEL_2                                                  (0x4U << RCC_CFGR_MCOSEL_Pos)
2866 #define RCC_CFGR_LCOSEL_Pos                                                (24UL)   /*!<RCC CFGR: LCOSEL (Bit 24) */
2867 #define RCC_CFGR_LCOSEL_Msk                                                (0x3000000UL)    /*!< RCC CFGR: LCOSEL (Bitfield-Mask: 0x03) */
2868 #define RCC_CFGR_LCOSEL                                                    RCC_CFGR_LCOSEL_Msk
2869 #define RCC_CFGR_LCOSEL_0                                                  (0x1U << RCC_CFGR_LCOSEL_Pos)
2870 #define RCC_CFGR_LCOSEL_1                                                  (0x2U << RCC_CFGR_LCOSEL_Pos)
2871 #define RCC_CFGR_SPI2I2SCLKSEL_Pos                                         (23UL)   /*!<RCC CFGR: SPI2I2SCLKSEL (Bit 23) */
2872 #define RCC_CFGR_SPI2I2SCLKSEL_Msk                                         (0x800000UL)   /*!< RCC CFGR: SPI2I2SCLKSEL (Bitfield-Mask: 0x01) */
2873 #define RCC_CFGR_SPI2I2SCLKSEL                                             RCC_CFGR_SPI2I2SCLKSEL_Msk
2874 #define RCC_CFGR_SPI3I2SCLKSEL_Pos                                         (22UL)   /*!<RCC CFGR: SPI3I2SCLKSEL (Bit 22) */
2875 #define RCC_CFGR_SPI3I2SCLKSEL_Msk                                         (0x400000UL)   /*!< RCC CFGR: SPI3I2SCLKSEL (Bitfield-Mask: 0x01) */
2876 #define RCC_CFGR_SPI3I2SCLKSEL                                             RCC_CFGR_SPI3I2SCLKSEL_Msk
2877 #define RCC_CFGR_IOBOOSTEN_Pos                                             (17UL)   /*!<RCC CFGR: IOBOOSTEN (Bit 17) */
2878 #define RCC_CFGR_IOBOOSTEN_Msk                                             (0x20000UL)    /*!< RCC CFGR: IOBOOSTEN (Bitfield-Mask: 0x01) */
2879 #define RCC_CFGR_IOBOOSTEN                                                 RCC_CFGR_IOBOOSTEN_Msk
2880 #define RCC_CFGR_CLKSLOWSEL_Pos                                            (15UL)   /*!<RCC CFGR: CLKSLOWSEL (Bit 15) */
2881 #define RCC_CFGR_CLKSLOWSEL_Msk                                            (0x18000UL)    /*!< RCC CFGR: CLKSLOWSEL (Bitfield-Mask: 0x03) */
2882 #define RCC_CFGR_CLKSLOWSEL                                                RCC_CFGR_CLKSLOWSEL_Msk
2883 #define RCC_CFGR_CLKSLOWSEL_0                                              (0x1U << RCC_CFGR_CLKSLOWSEL_Pos)
2884 #define RCC_CFGR_CLKSLOWSEL_1                                              (0x2U << RCC_CFGR_CLKSLOWSEL_Pos)
2885 #define RCC_CFGR_SMPSDIV_Pos                                               (12UL)   /*!<RCC CFGR: SMPSDIV (Bit 12) */
2886 #define RCC_CFGR_SMPSDIV_Msk                                               (0x1000UL)   /*!< RCC CFGR: SMPSDIV (Bitfield-Mask: 0x01) */
2887 #define RCC_CFGR_SMPSDIV                                                   RCC_CFGR_SMPSDIV_Msk
2888 #define RCC_CFGR_ANADIV_Pos                                                (10UL)   /*!<RCC CFGR: ANADIV (Bit 10) */
2889 #define RCC_CFGR_ANADIV_Msk                                                (0xc00UL)    /*!< RCC CFGR: ANADIV (Bitfield-Mask: 0x03) */
2890 #define RCC_CFGR_ANADIV                                                    RCC_CFGR_ANADIV_Msk
2891 #define RCC_CFGR_ANADIV_0                                                  (0x1U << RCC_CFGR_ANADIV_Pos)
2892 #define RCC_CFGR_ANADIV_1                                                  (0x2U << RCC_CFGR_ANADIV_Pos)
2893 #define RCC_CFGR_CLKSYSDIV_Pos                                             (5UL)    /*!<RCC CFGR: CLKSYSDIV (Bit 5) */
2894 #define RCC_CFGR_CLKSYSDIV_Msk                                             (0xe0UL)   /*!< RCC CFGR: CLKSYSDIV (Bitfield-Mask: 0x07) */
2895 #define RCC_CFGR_CLKSYSDIV                                                 RCC_CFGR_CLKSYSDIV_Msk
2896 #define RCC_CFGR_CLKSYSDIV_0                                               (0x1U << RCC_CFGR_CLKSYSDIV_Pos)
2897 #define RCC_CFGR_CLKSYSDIV_1                                               (0x2U << RCC_CFGR_CLKSYSDIV_Pos)
2898 #define RCC_CFGR_CLKSYSDIV_2                                               (0x4U << RCC_CFGR_CLKSYSDIV_Pos)
2899 #define RCC_CFGR_STOPHSI_Pos                                               (2UL)    /*!<RCC CFGR: STOPHSI (Bit 2) */
2900 #define RCC_CFGR_STOPHSI_Msk                                               (0x4UL)    /*!< RCC CFGR: STOPHSI (Bitfield-Mask: 0x01) */
2901 #define RCC_CFGR_STOPHSI                                                   RCC_CFGR_STOPHSI_Msk
2902 #define RCC_CFGR_HSESEL_Pos                                                (1UL)    /*!<RCC CFGR: HSESEL (Bit 1) */
2903 #define RCC_CFGR_HSESEL_Msk                                                (0x2UL)    /*!< RCC CFGR: HSESEL (Bitfield-Mask: 0x01) */
2904 #define RCC_CFGR_HSESEL                                                    RCC_CFGR_HSESEL_Msk
2905 #define RCC_CFGR_SMPSINV_Pos                                               (0UL)    /*!<RCC CFGR: SMPSINV (Bit 0) */
2906 #define RCC_CFGR_SMPSINV_Msk                                               (0x1UL)    /*!< RCC CFGR: SMPSINV (Bitfield-Mask: 0x01) */
2907 #define RCC_CFGR_SMPSINV                                                   RCC_CFGR_SMPSINV_Msk
2908 
2909 /* =====================================================    CSSWCR    ===================================================== */
2910 #define RCC_CSSWCR_HSITRIMSW_Pos                                           (24UL)   /*!<RCC CSSWCR: HSITRIMSW (Bit 24) */
2911 #define RCC_CSSWCR_HSITRIMSW_Msk                                           (0x3f000000UL)   /*!< RCC CSSWCR: HSITRIMSW (Bitfield-Mask: 0x3f) */
2912 #define RCC_CSSWCR_HSITRIMSW                                               RCC_CSSWCR_HSITRIMSW_Msk
2913 #define RCC_CSSWCR_HSITRIMSW_0                                             (0x1U << RCC_CSSWCR_HSITRIMSW_Pos)
2914 #define RCC_CSSWCR_HSITRIMSW_1                                             (0x2U << RCC_CSSWCR_HSITRIMSW_Pos)
2915 #define RCC_CSSWCR_HSITRIMSW_2                                             (0x4U << RCC_CSSWCR_HSITRIMSW_Pos)
2916 #define RCC_CSSWCR_HSITRIMSW_3                                             (0x8U << RCC_CSSWCR_HSITRIMSW_Pos)
2917 #define RCC_CSSWCR_HSITRIMSW_4                                             (0x10U << RCC_CSSWCR_HSITRIMSW_Pos)
2918 #define RCC_CSSWCR_HSITRIMSW_5                                             (0x20U << RCC_CSSWCR_HSITRIMSW_Pos)
2919 #define RCC_CSSWCR_HSISWTRIMEN_Pos                                         (23UL)   /*!<RCC CSSWCR: HSISWTRIMEN (Bit 23) */
2920 #define RCC_CSSWCR_HSISWTRIMEN_Msk                                         (0x800000UL)   /*!< RCC CSSWCR: HSISWTRIMEN (Bitfield-Mask: 0x01) */
2921 #define RCC_CSSWCR_HSISWTRIMEN                                             RCC_CSSWCR_HSISWTRIMEN_Msk
2922 #define RCC_CSSWCR_LSEDRV_Pos                                              (5UL)    /*!<RCC CSSWCR: LSEDRV (Bit 5) */
2923 #define RCC_CSSWCR_LSEDRV_Msk                                              (0x60UL)   /*!< RCC CSSWCR: LSEDRV (Bitfield-Mask: 0x03) */
2924 #define RCC_CSSWCR_LSEDRV                                                  RCC_CSSWCR_LSEDRV_Msk
2925 #define RCC_CSSWCR_LSEDRV_0                                                (0x1U << RCC_CSSWCR_LSEDRV_Pos)
2926 #define RCC_CSSWCR_LSEDRV_1                                                (0x2U << RCC_CSSWCR_LSEDRV_Pos)
2927 #define RCC_CSSWCR_LSISWBW_Pos                                             (1UL)    /*!<RCC CSSWCR: LSISWBW (Bit 1) */
2928 #define RCC_CSSWCR_LSISWBW_Msk                                             (0x1eUL)   /*!< RCC CSSWCR: LSISWBW (Bitfield-Mask: 0x0f) */
2929 #define RCC_CSSWCR_LSISWBW                                                 RCC_CSSWCR_LSISWBW_Msk
2930 #define RCC_CSSWCR_LSISWBW_0                                               (0x1U << RCC_CSSWCR_LSISWBW_Pos)
2931 #define RCC_CSSWCR_LSISWBW_1                                               (0x2U << RCC_CSSWCR_LSISWBW_Pos)
2932 #define RCC_CSSWCR_LSISWBW_2                                               (0x4U << RCC_CSSWCR_LSISWBW_Pos)
2933 #define RCC_CSSWCR_LSISWBW_3                                               (0x8U << RCC_CSSWCR_LSISWBW_Pos)
2934 #define RCC_CSSWCR_LSISWTRIMEN_Pos                                         (0UL)    /*!<RCC CSSWCR: LSISWTRIMEN (Bit 0) */
2935 #define RCC_CSSWCR_LSISWTRIMEN_Msk                                         (0x1UL)    /*!< RCC CSSWCR: LSISWTRIMEN (Bitfield-Mask: 0x01) */
2936 #define RCC_CSSWCR_LSISWTRIMEN                                             RCC_CSSWCR_LSISWTRIMEN_Msk
2937 
2938 /* =====================================================    CIER    ===================================================== */
2939 #define RCC_CIER_WDGRSTIE_Pos                                              (8UL)    /*!<RCC CIER: WDGRSTIE (Bit 8) */
2940 #define RCC_CIER_WDGRSTIE_Msk                                              (0x100UL)    /*!< RCC CIER: WDGRSTIE (Bitfield-Mask: 0x01) */
2941 #define RCC_CIER_WDGRSTIE                                                  RCC_CIER_WDGRSTIE_Msk
2942 #define RCC_CIER_RTCRSTIE_Pos                                              (7UL)    /*!<RCC CIER: RTCRSTIE (Bit 7) */
2943 #define RCC_CIER_RTCRSTIE_Msk                                              (0x80UL)   /*!< RCC CIER: RTCRSTIE (Bitfield-Mask: 0x01) */
2944 #define RCC_CIER_RTCRSTIE                                                  RCC_CIER_RTCRSTIE_Msk
2945 #define RCC_CIER_HSIPLLUNLOCKDETIE_Pos                                     (6UL)    /*!<RCC CIER: HSIPLLUNLOCKDETIE (Bit 6) */
2946 #define RCC_CIER_HSIPLLUNLOCKDETIE_Msk                                     (0x40UL)   /*!< RCC CIER: HSIPLLUNLOCKDETIE (Bitfield-Mask: 0x01) */
2947 #define RCC_CIER_HSIPLLUNLOCKDETIE                                         RCC_CIER_HSIPLLUNLOCKDETIE_Msk
2948 #define RCC_CIER_HSIPLLRDYIE_Pos                                           (5UL)    /*!<RCC CIER: HSIPLLRDYIE (Bit 5) */
2949 #define RCC_CIER_HSIPLLRDYIE_Msk                                           (0x20UL)   /*!< RCC CIER: HSIPLLRDYIE (Bitfield-Mask: 0x01) */
2950 #define RCC_CIER_HSIPLLRDYIE                                               RCC_CIER_HSIPLLRDYIE_Msk
2951 #define RCC_CIER_HSERDYIE_Pos                                              (4UL)    /*!<RCC CIER: HSERDYIE (Bit 4) */
2952 #define RCC_CIER_HSERDYIE_Msk                                              (0x10UL)   /*!< RCC CIER: HSERDYIE (Bitfield-Mask: 0x01) */
2953 #define RCC_CIER_HSERDYIE                                                  RCC_CIER_HSERDYIE_Msk
2954 #define RCC_CIER_HSIRDYIE_Pos                                              (3UL)    /*!<RCC CIER: HSIRDYIE (Bit 3) */
2955 #define RCC_CIER_HSIRDYIE_Msk                                              (0x8UL)    /*!< RCC CIER: HSIRDYIE (Bitfield-Mask: 0x01) */
2956 #define RCC_CIER_HSIRDYIE                                                  RCC_CIER_HSIRDYIE_Msk
2957 #define RCC_CIER_LSERDYIE_Pos                                              (1UL)    /*!<RCC CIER: LSERDYIE (Bit 1) */
2958 #define RCC_CIER_LSERDYIE_Msk                                              (0x2UL)    /*!< RCC CIER: LSERDYIE (Bitfield-Mask: 0x01) */
2959 #define RCC_CIER_LSERDYIE                                                  RCC_CIER_LSERDYIE_Msk
2960 #define RCC_CIER_LSIRDYIE_Pos                                              (0UL)    /*!<RCC CIER: LSIRDYIE (Bit 0) */
2961 #define RCC_CIER_LSIRDYIE_Msk                                              (0x1UL)    /*!< RCC CIER: LSIRDYIE (Bitfield-Mask: 0x01) */
2962 #define RCC_CIER_LSIRDYIE                                                  RCC_CIER_LSIRDYIE_Msk
2963 
2964 /* =====================================================    CIFR    ===================================================== */
2965 #define RCC_CIFR_WDGRSTF_Pos                                               (8UL)    /*!<RCC CIFR: WDGRSTF (Bit 8) */
2966 #define RCC_CIFR_WDGRSTF_Msk                                               (0x100UL)    /*!< RCC CIFR: WDGRSTF (Bitfield-Mask: 0x01) */
2967 #define RCC_CIFR_WDGRSTF                                                   RCC_CIFR_WDGRSTF_Msk
2968 #define RCC_CIFR_RTCRSTF_Pos                                               (7UL)    /*!<RCC CIFR: RTCRSTF (Bit 7) */
2969 #define RCC_CIFR_RTCRSTF_Msk                                               (0x80UL)   /*!< RCC CIFR: RTCRSTF (Bitfield-Mask: 0x01) */
2970 #define RCC_CIFR_RTCRSTF                                                   RCC_CIFR_RTCRSTF_Msk
2971 #define RCC_CIFR_HSIPLLUNLOCKDETF_Pos                                      (6UL)    /*!<RCC CIFR: HSIPLLUNLOCKDETF (Bit 6) */
2972 #define RCC_CIFR_HSIPLLUNLOCKDETF_Msk                                      (0x40UL)   /*!< RCC CIFR: HSIPLLUNLOCKDETF (Bitfield-Mask: 0x01) */
2973 #define RCC_CIFR_HSIPLLUNLOCKDETF                                          RCC_CIFR_HSIPLLUNLOCKDETF_Msk
2974 #define RCC_CIFR_HSIPLLRDYF_Pos                                            (5UL)    /*!<RCC CIFR: HSIPLLRDYF (Bit 5) */
2975 #define RCC_CIFR_HSIPLLRDYF_Msk                                            (0x20UL)   /*!< RCC CIFR: HSIPLLRDYF (Bitfield-Mask: 0x01) */
2976 #define RCC_CIFR_HSIPLLRDYF                                                RCC_CIFR_HSIPLLRDYF_Msk
2977 #define RCC_CIFR_HSERDYF_Pos                                               (4UL)    /*!<RCC CIFR: HSERDYF (Bit 4) */
2978 #define RCC_CIFR_HSERDYF_Msk                                               (0x10UL)   /*!< RCC CIFR: HSERDYF (Bitfield-Mask: 0x01) */
2979 #define RCC_CIFR_HSERDYF                                                   RCC_CIFR_HSERDYF_Msk
2980 #define RCC_CIFR_HSIRDYF_Pos                                               (3UL)    /*!<RCC CIFR: HSIRDYF (Bit 3) */
2981 #define RCC_CIFR_HSIRDYF_Msk                                               (0x8UL)    /*!< RCC CIFR: HSIRDYF (Bitfield-Mask: 0x01) */
2982 #define RCC_CIFR_HSIRDYF                                                   RCC_CIFR_HSIRDYF_Msk
2983 #define RCC_CIFR_LSERDYF_Pos                                               (1UL)    /*!<RCC CIFR: LSERDYF (Bit 1) */
2984 #define RCC_CIFR_LSERDYF_Msk                                               (0x2UL)    /*!< RCC CIFR: LSERDYF (Bitfield-Mask: 0x01) */
2985 #define RCC_CIFR_LSERDYF                                                   RCC_CIFR_LSERDYF_Msk
2986 #define RCC_CIFR_LSIRDYF_Pos                                               (0UL)    /*!<RCC CIFR: LSIRDYF (Bit 0) */
2987 #define RCC_CIFR_LSIRDYF_Msk                                               (0x1UL)    /*!< RCC CIFR: LSIRDYF (Bitfield-Mask: 0x01) */
2988 #define RCC_CIFR_LSIRDYF                                                   RCC_CIFR_LSIRDYF_Msk
2989 
2990 /* =====================================================    CSCMDR    ===================================================== */
2991 #define RCC_CSCMDR_EOFSEQ_IRQ_Pos                                          (7UL)    /*!<RCC CSCMDR: EOFSEQ_IRQ (Bit 7) */
2992 #define RCC_CSCMDR_EOFSEQ_IRQ_Msk                                          (0x80UL)   /*!< RCC CSCMDR: EOFSEQ_IRQ (Bitfield-Mask: 0x01) */
2993 #define RCC_CSCMDR_EOFSEQ_IRQ                                              RCC_CSCMDR_EOFSEQ_IRQ_Msk
2994 #define RCC_CSCMDR_EOFSEQ_IE_Pos                                           (6UL)    /*!<RCC CSCMDR: EOFSEQ_IE (Bit 6) */
2995 #define RCC_CSCMDR_EOFSEQ_IE_Msk                                           (0x40UL)   /*!< RCC CSCMDR: EOFSEQ_IE (Bitfield-Mask: 0x01) */
2996 #define RCC_CSCMDR_EOFSEQ_IE                                               RCC_CSCMDR_EOFSEQ_IE_Msk
2997 #define RCC_CSCMDR_STATUS_Pos                                              (4UL)    /*!<RCC CSCMDR: STATUS (Bit 4) */
2998 #define RCC_CSCMDR_STATUS_Msk                                              (0x30UL)   /*!< RCC CSCMDR: STATUS (Bitfield-Mask: 0x03) */
2999 #define RCC_CSCMDR_STATUS                                                  RCC_CSCMDR_STATUS_Msk
3000 #define RCC_CSCMDR_STATUS_0                                                (0x1U << RCC_CSCMDR_STATUS_Pos)
3001 #define RCC_CSCMDR_STATUS_1                                                (0x2U << RCC_CSCMDR_STATUS_Pos)
3002 #define RCC_CSCMDR_CLKSYSDIV_REQ_Pos                                       (1UL)    /*!<RCC CSCMDR: CLKSYSDIV_REQ (Bit 1) */
3003 #define RCC_CSCMDR_CLKSYSDIV_REQ_Msk                                       (0xeUL)    /*!< RCC CSCMDR: CLKSYSDIV_REQ (Bitfield-Mask: 0x07) */
3004 #define RCC_CSCMDR_CLKSYSDIV_REQ                                           RCC_CSCMDR_CLKSYSDIV_REQ_Msk
3005 #define RCC_CSCMDR_CLKSYSDIV_REQ_0                                         (0x1U << RCC_CSCMDR_CLKSYSDIV_REQ_Pos)
3006 #define RCC_CSCMDR_CLKSYSDIV_REQ_1                                         (0x2U << RCC_CSCMDR_CLKSYSDIV_REQ_Pos)
3007 #define RCC_CSCMDR_CLKSYSDIV_REQ_2                                         (0x4U << RCC_CSCMDR_CLKSYSDIV_REQ_Pos)
3008 #define RCC_CSCMDR_REQUEST_Pos                                             (0UL)    /*!<RCC CSCMDR: REQUEST (Bit 0) */
3009 #define RCC_CSCMDR_REQUEST_Msk                                             (0x1UL)    /*!< RCC CSCMDR: REQUEST (Bitfield-Mask: 0x01) */
3010 #define RCC_CSCMDR_REQUEST                                                 RCC_CSCMDR_REQUEST_Msk
3011 
3012 /* =====================================================    AHBRSTR    ===================================================== */
3013 #define RCC_AHBRSTR_RNGRST_Pos                                             (18UL)   /*!<RCC AHBRSTR: RNGRST (Bit 18) */
3014 #define RCC_AHBRSTR_RNGRST_Msk                                             (0x40000UL)    /*!< RCC AHBRSTR: RNGRST (Bitfield-Mask: 0x01) */
3015 #define RCC_AHBRSTR_RNGRST                                                 RCC_AHBRSTR_RNGRST_Msk
3016 #define RCC_AHBRSTR_PKARST_Pos                                             (16UL)   /*!<RCC AHBRSTR: PKARST (Bit 16) */
3017 #define RCC_AHBRSTR_PKARST_Msk                                             (0x10000UL)    /*!< RCC AHBRSTR: PKARST (Bitfield-Mask: 0x01) */
3018 #define RCC_AHBRSTR_PKARST                                                 RCC_AHBRSTR_PKARST_Msk
3019 #define RCC_AHBRSTR_CRCRST_Pos                                             (12UL)   /*!<RCC AHBRSTR: CRCRST (Bit 12) */
3020 #define RCC_AHBRSTR_CRCRST_Msk                                             (0x1000UL)   /*!< RCC AHBRSTR: CRCRST (Bitfield-Mask: 0x01) */
3021 #define RCC_AHBRSTR_CRCRST                                                 RCC_AHBRSTR_CRCRST_Msk
3022 #define RCC_AHBRSTR_GPIOBRST_Pos                                           (3UL)    /*!<RCC AHBRSTR: GPIOBRST (Bit 3) */
3023 #define RCC_AHBRSTR_GPIOBRST_Msk                                           (0x8UL)    /*!< RCC AHBRSTR: GPIOBRST (Bitfield-Mask: 0x01) */
3024 #define RCC_AHBRSTR_GPIOBRST                                               RCC_AHBRSTR_GPIOBRST_Msk
3025 #define RCC_AHBRSTR_GPIOARST_Pos                                           (2UL)    /*!<RCC AHBRSTR: GPIOARST (Bit 2) */
3026 #define RCC_AHBRSTR_GPIOARST_Msk                                           (0x4UL)    /*!< RCC AHBRSTR: GPIOARST (Bitfield-Mask: 0x01) */
3027 #define RCC_AHBRSTR_GPIOARST                                               RCC_AHBRSTR_GPIOARST_Msk
3028 #define RCC_AHBRSTR_DMARST_Pos                                             (0UL)    /*!<RCC AHBRSTR: DMARST (Bit 0) */
3029 #define RCC_AHBRSTR_DMARST_Msk                                             (0x1UL)    /*!< RCC AHBRSTR: DMARST (Bitfield-Mask: 0x01) */
3030 #define RCC_AHBRSTR_DMARST                                                 RCC_AHBRSTR_DMARST_Msk
3031 
3032 /* =====================================================    APB0RSTR    ===================================================== */
3033 #define RCC_APB0RSTR_WDGRST_Pos                                            (14UL)   /*!<RCC APB0RSTR: WDGRST (Bit 14) */
3034 #define RCC_APB0RSTR_WDGRST_Msk                                            (0x4000UL)   /*!< RCC APB0RSTR: WDGRST (Bitfield-Mask: 0x01) */
3035 #define RCC_APB0RSTR_WDGRST                                                RCC_APB0RSTR_WDGRST_Msk
3036 #define RCC_APB0RSTR_RTCRST_Pos                                            (12UL)   /*!<RCC APB0RSTR: RTCRST (Bit 12) */
3037 #define RCC_APB0RSTR_RTCRST_Msk                                            (0x1000UL)   /*!< RCC APB0RSTR: RTCRST (Bitfield-Mask: 0x01) */
3038 #define RCC_APB0RSTR_RTCRST                                                RCC_APB0RSTR_RTCRST_Msk
3039 #define RCC_APB0RSTR_SYSCFGRST_Pos                                         (8UL)    /*!<RCC APB0RSTR: SYSCFGRST (Bit 8) */
3040 #define RCC_APB0RSTR_SYSCFGRST_Msk                                         (0x100UL)    /*!< RCC APB0RSTR: SYSCFGRST (Bitfield-Mask: 0x01) */
3041 #define RCC_APB0RSTR_SYSCFGRST                                             RCC_APB0RSTR_SYSCFGRST_Msk
3042 #define RCC_APB0RSTR_TIM1RST_Pos                                           (0UL)    /*!<RCC APB0RSTR: TIM1RST (Bit 0) */
3043 #define RCC_APB0RSTR_TIM1RST_Msk                                           (0x1UL)    /*!< RCC APB0RSTR: TIM1RST (Bitfield-Mask: 0x01) */
3044 #define RCC_APB0RSTR_TIM1RST                                               RCC_APB0RSTR_TIM1RST_Msk
3045 
3046 /* =====================================================    APB1RSTR    ===================================================== */
3047 #define RCC_APB1RSTR_I2C2RST_Pos                                           (23UL)   /*!<RCC APB1RSTR: I2C2RST (Bit 23) */
3048 #define RCC_APB1RSTR_I2C2RST_Msk                                           (0x800000UL)   /*!< RCC APB1RSTR: I2C2RST (Bitfield-Mask: 0x01) */
3049 #define RCC_APB1RSTR_I2C2RST                                               RCC_APB1RSTR_I2C2RST_Msk
3050 #define RCC_APB1RSTR_I2C1RST_Pos                                           (21UL)   /*!<RCC APB1RSTR: I2C1RST (Bit 21) */
3051 #define RCC_APB1RSTR_I2C1RST_Msk                                           (0x200000UL)   /*!< RCC APB1RSTR: I2C1RST (Bitfield-Mask: 0x01) */
3052 #define RCC_APB1RSTR_I2C1RST                                               RCC_APB1RSTR_I2C1RST_Msk
3053 #define RCC_APB1RSTR_SPI3RST_Pos                                           (14UL)   /*!<RCC APB1RSTR: SPI3RST (Bit 14) */
3054 #define RCC_APB1RSTR_SPI3RST_Msk                                           (0x4000UL)   /*!< RCC APB1RSTR: SPI3RST (Bitfield-Mask: 0x01) */
3055 #define RCC_APB1RSTR_SPI3RST                                               RCC_APB1RSTR_SPI3RST_Msk
3056 #define RCC_APB1RSTR_SPI2RST_Pos                                           (12UL)   /*!<RCC APB1RSTR: SPI2RST (Bit 12) */
3057 #define RCC_APB1RSTR_SPI2RST_Msk                                           (0x1000UL)   /*!< RCC APB1RSTR: SPI2RST (Bitfield-Mask: 0x01) */
3058 #define RCC_APB1RSTR_SPI2RST                                               RCC_APB1RSTR_SPI2RST_Msk
3059 #define RCC_APB1RSTR_USARTRST_Pos                                          (10UL)   /*!<RCC APB1RSTR: USARTRST (Bit 10) */
3060 #define RCC_APB1RSTR_USARTRST_Msk                                          (0x400UL)    /*!< RCC APB1RSTR: USARTRST (Bitfield-Mask: 0x01) */
3061 #define RCC_APB1RSTR_USARTRST                                              RCC_APB1RSTR_USARTRST_Msk
3062 #define RCC_APB1RSTR_LPUARTRST_Pos                                         (8UL)    /*!<RCC APB1RSTR: LPUARTRST (Bit 8) */
3063 #define RCC_APB1RSTR_LPUARTRST_Msk                                         (0x100UL)    /*!< RCC APB1RSTR: LPUARTRST (Bitfield-Mask: 0x01) */
3064 #define RCC_APB1RSTR_LPUARTRST                                             RCC_APB1RSTR_LPUARTRST_Msk
3065 #define RCC_APB1RSTR_ADCRST_Pos                                            (4UL)    /*!<RCC APB1RSTR: ADCRST (Bit 4) */
3066 #define RCC_APB1RSTR_ADCRST_Msk                                            (0x10UL)   /*!< RCC APB1RSTR: ADCRST (Bitfield-Mask: 0x01) */
3067 #define RCC_APB1RSTR_ADCRST                                                RCC_APB1RSTR_ADCRST_Msk
3068 #define RCC_APB1RSTR_SPI1RST_Pos                                           (0UL)    /*!<RCC APB1RSTR: SPI1RST (Bit 0) */
3069 #define RCC_APB1RSTR_SPI1RST_Msk                                           (0x1UL)    /*!< RCC APB1RSTR: SPI1RST (Bitfield-Mask: 0x01) */
3070 #define RCC_APB1RSTR_SPI1RST                                               RCC_APB1RSTR_SPI1RST_Msk
3071 
3072 /* =====================================================    APB2RSTR    ===================================================== */
3073 #define RCC_APB2RSTR_MRBLERST_Pos                                          (0UL)    /*!<RCC APB2RSTR: MRBLERST (Bit 0) */
3074 #define RCC_APB2RSTR_MRBLERST_Msk                                          (0x1UL)    /*!< RCC APB2RSTR: MRBLERST (Bitfield-Mask: 0x01) */
3075 #define RCC_APB2RSTR_MRBLERST                                              RCC_APB2RSTR_MRBLERST_Msk
3076 
3077 /* =====================================================    AHBENR    ===================================================== */
3078 #define RCC_AHBENR_RNGEN_Pos                                               (18UL)   /*!<RCC AHBENR: RNGEN (Bit 18) */
3079 #define RCC_AHBENR_RNGEN_Msk                                               (0x40000UL)    /*!< RCC AHBENR: RNGEN (Bitfield-Mask: 0x01) */
3080 #define RCC_AHBENR_RNGEN                                                   RCC_AHBENR_RNGEN_Msk
3081 #define RCC_AHBENR_PKAEN_Pos                                               (16UL)   /*!<RCC AHBENR: PKAEN (Bit 16) */
3082 #define RCC_AHBENR_PKAEN_Msk                                               (0x10000UL)    /*!< RCC AHBENR: PKAEN (Bitfield-Mask: 0x01) */
3083 #define RCC_AHBENR_PKAEN                                                   RCC_AHBENR_PKAEN_Msk
3084 #define RCC_AHBENR_CRCEN_Pos                                               (12UL)   /*!<RCC AHBENR: CRCEN (Bit 12) */
3085 #define RCC_AHBENR_CRCEN_Msk                                               (0x1000UL)   /*!< RCC AHBENR: CRCEN (Bitfield-Mask: 0x01) */
3086 #define RCC_AHBENR_CRCEN                                                   RCC_AHBENR_CRCEN_Msk
3087 #define RCC_AHBENR_GPIOBEN_Pos                                             (3UL)    /*!<RCC AHBENR: GPIOBEN (Bit 3) */
3088 #define RCC_AHBENR_GPIOBEN_Msk                                             (0x8UL)    /*!< RCC AHBENR: GPIOBEN (Bitfield-Mask: 0x01) */
3089 #define RCC_AHBENR_GPIOBEN                                                 RCC_AHBENR_GPIOBEN_Msk
3090 #define RCC_AHBENR_GPIOAEN_Pos                                             (2UL)    /*!<RCC AHBENR: GPIOAEN (Bit 2) */
3091 #define RCC_AHBENR_GPIOAEN_Msk                                             (0x4UL)    /*!< RCC AHBENR: GPIOAEN (Bitfield-Mask: 0x01) */
3092 #define RCC_AHBENR_GPIOAEN                                                 RCC_AHBENR_GPIOAEN_Msk
3093 #define RCC_AHBENR_DMAEN_Pos                                               (0UL)    /*!<RCC AHBENR: DMAEN (Bit 0) */
3094 #define RCC_AHBENR_DMAEN_Msk                                               (0x1UL)    /*!< RCC AHBENR: DMAEN (Bitfield-Mask: 0x01) */
3095 #define RCC_AHBENR_DMAEN                                                   RCC_AHBENR_DMAEN_Msk
3096 
3097 /* =====================================================    APB0ENR    ===================================================== */
3098 #define RCC_APB0ENR_WDGEN_Pos                                              (14UL)   /*!<RCC APB0ENR: WDGEN (Bit 14) */
3099 #define RCC_APB0ENR_WDGEN_Msk                                              (0x4000UL)   /*!< RCC APB0ENR: WDGEN (Bitfield-Mask: 0x01) */
3100 #define RCC_APB0ENR_WDGEN                                                  RCC_APB0ENR_WDGEN_Msk
3101 #define RCC_APB0ENR_RTCEN_Pos                                              (12UL)   /*!<RCC APB0ENR: RTCEN (Bit 12) */
3102 #define RCC_APB0ENR_RTCEN_Msk                                              (0x1000UL)   /*!< RCC APB0ENR: RTCEN (Bitfield-Mask: 0x01) */
3103 #define RCC_APB0ENR_RTCEN                                                  RCC_APB0ENR_RTCEN_Msk
3104 #define RCC_APB0ENR_SYSCFGEN_Pos                                           (8UL)    /*!<RCC APB0ENR: SYSCFGEN (Bit 8) */
3105 #define RCC_APB0ENR_SYSCFGEN_Msk                                           (0x100UL)    /*!< RCC APB0ENR: SYSCFGEN (Bitfield-Mask: 0x01) */
3106 #define RCC_APB0ENR_SYSCFGEN                                               RCC_APB0ENR_SYSCFGEN_Msk
3107 #define RCC_APB0ENR_TIM1EN_Pos                                             (0UL)    /*!<RCC APB0ENR: TIM1EN (Bit 0) */
3108 #define RCC_APB0ENR_TIM1EN_Msk                                             (0x1UL)    /*!< RCC APB0ENR: TIM1EN (Bitfield-Mask: 0x01) */
3109 #define RCC_APB0ENR_TIM1EN                                                 RCC_APB0ENR_TIM1EN_Msk
3110 
3111 /* =====================================================    APB1ENR    ===================================================== */
3112 #define RCC_APB1ENR_I2C2EN_Pos                                             (23UL)   /*!<RCC APB1ENR: I2C2EN (Bit 23) */
3113 #define RCC_APB1ENR_I2C2EN_Msk                                             (0x800000UL)   /*!< RCC APB1ENR: I2C2EN (Bitfield-Mask: 0x01) */
3114 #define RCC_APB1ENR_I2C2EN                                                 RCC_APB1ENR_I2C2EN_Msk
3115 #define RCC_APB1ENR_I2C1EN_Pos                                             (21UL)   /*!<RCC APB1ENR: I2C1EN (Bit 21) */
3116 #define RCC_APB1ENR_I2C1EN_Msk                                             (0x200000UL)   /*!< RCC APB1ENR: I2C1EN (Bitfield-Mask: 0x01) */
3117 #define RCC_APB1ENR_I2C1EN                                                 RCC_APB1ENR_I2C1EN_Msk
3118 #define RCC_APB1ENR_SPI3EN_Pos                                             (14UL)   /*!<RCC APB1ENR: SPI3EN (Bit 14) */
3119 #define RCC_APB1ENR_SPI3EN_Msk                                             (0x4000UL)   /*!< RCC APB1ENR: SPI3EN (Bitfield-Mask: 0x01) */
3120 #define RCC_APB1ENR_SPI3EN                                                 RCC_APB1ENR_SPI3EN_Msk
3121 #define RCC_APB1ENR_SPI2EN_Pos                                             (12UL)   /*!<RCC APB1ENR: SPI2EN (Bit 12) */
3122 #define RCC_APB1ENR_SPI2EN_Msk                                             (0x1000UL)   /*!< RCC APB1ENR: SPI2EN (Bitfield-Mask: 0x01) */
3123 #define RCC_APB1ENR_SPI2EN                                                 RCC_APB1ENR_SPI2EN_Msk
3124 #define RCC_APB1ENR_USARTEN_Pos                                            (10UL)   /*!<RCC APB1ENR: USARTEN (Bit 10) */
3125 #define RCC_APB1ENR_USARTEN_Msk                                            (0x400UL)    /*!< RCC APB1ENR: USARTEN (Bitfield-Mask: 0x01) */
3126 #define RCC_APB1ENR_USARTEN                                                RCC_APB1ENR_USARTEN_Msk
3127 #define RCC_APB1ENR_LPUARTEN_Pos                                           (8UL)    /*!<RCC APB1ENR: LPUARTEN (Bit 8) */
3128 #define RCC_APB1ENR_LPUARTEN_Msk                                           (0x100UL)    /*!< RCC APB1ENR: LPUARTEN (Bitfield-Mask: 0x01) */
3129 #define RCC_APB1ENR_LPUARTEN                                               RCC_APB1ENR_LPUARTEN_Msk
3130 #define RCC_APB1ENR_ADCANAEN_Pos                                           (5UL)    /*!<RCC APB1ENR: ADCANAEN (Bit 5) */
3131 #define RCC_APB1ENR_ADCANAEN_Msk                                           (0x20UL)   /*!< RCC APB1ENR: ADCANAEN (Bitfield-Mask: 0x01) */
3132 #define RCC_APB1ENR_ADCANAEN                                               RCC_APB1ENR_ADCANAEN_Msk
3133 #define RCC_APB1ENR_ADCDIGEN_Pos                                           (4UL)    /*!<RCC APB1ENR: ADCDIGEN (Bit 4) */
3134 #define RCC_APB1ENR_ADCDIGEN_Msk                                           (0x10UL)   /*!< RCC APB1ENR: ADCDIGEN (Bitfield-Mask: 0x01) */
3135 #define RCC_APB1ENR_ADCDIGEN                                               RCC_APB1ENR_ADCDIGEN_Msk
3136 #define RCC_APB1ENR_SPI1EN_Pos                                             (0UL)    /*!<RCC APB1ENR: SPI1EN (Bit 0) */
3137 #define RCC_APB1ENR_SPI1EN_Msk                                             (0x1UL)    /*!< RCC APB1ENR: SPI1EN (Bitfield-Mask: 0x01) */
3138 #define RCC_APB1ENR_SPI1EN                                                 RCC_APB1ENR_SPI1EN_Msk
3139 
3140 /* =====================================================    APB2ENR    ===================================================== */
3141 #define RCC_APB2ENR_CLKBLEDIV_Pos                                          (1UL)    /*!<RCC APB2ENR: CLKBLEDIV (Bit 1) */
3142 #define RCC_APB2ENR_CLKBLEDIV_Msk                                          (0x6UL)    /*!< RCC APB2ENR: CLKBLEDIV (Bitfield-Mask: 0x03) */
3143 #define RCC_APB2ENR_CLKBLEDIV                                              RCC_APB2ENR_CLKBLEDIV_Msk
3144 #define RCC_APB2ENR_CLKBLEDIV_0                                            (0x1U << RCC_APB2ENR_CLKBLEDIV_Pos)
3145 #define RCC_APB2ENR_CLKBLEDIV_1                                            (0x2U << RCC_APB2ENR_CLKBLEDIV_Pos)
3146 #define RCC_APB2ENR_MRBLEEN_Pos                                            (0UL)    /*!<RCC APB2ENR: MRBLEEN (Bit 0) */
3147 #define RCC_APB2ENR_MRBLEEN_Msk                                            (0x1UL)    /*!< RCC APB2ENR: MRBLEEN (Bitfield-Mask: 0x01) */
3148 #define RCC_APB2ENR_MRBLEEN                                                RCC_APB2ENR_MRBLEEN_Msk
3149 
3150 /* =====================================================    CSR    ===================================================== */
3151 #define RCC_CSR_LOCKUPRSTF_Pos                                             (30UL)   /*!<RCC CSR: LOCKUPRSTF (Bit 30) */
3152 #define RCC_CSR_LOCKUPRSTF_Msk                                             (0x40000000UL)   /*!< RCC CSR: LOCKUPRSTF (Bitfield-Mask: 0x01) */
3153 #define RCC_CSR_LOCKUPRSTF                                                 RCC_CSR_LOCKUPRSTF_Msk
3154 #define RCC_CSR_WDGRSTF_Pos                                                (29UL)   /*!<RCC CSR: WDGRSTF (Bit 29) */
3155 #define RCC_CSR_WDGRSTF_Msk                                                (0x20000000UL)   /*!< RCC CSR: WDGRSTF (Bitfield-Mask: 0x01) */
3156 #define RCC_CSR_WDGRSTF                                                    RCC_CSR_WDGRSTF_Msk
3157 #define RCC_CSR_SFTRSTF_Pos                                                (28UL)   /*!<RCC CSR: SFTRSTF (Bit 28) */
3158 #define RCC_CSR_SFTRSTF_Msk                                                (0x10000000UL)   /*!< RCC CSR: SFTRSTF (Bitfield-Mask: 0x01) */
3159 #define RCC_CSR_SFTRSTF                                                    RCC_CSR_SFTRSTF_Msk
3160 #define RCC_CSR_PORRSTF_Pos                                                (27UL)   /*!<RCC CSR: PORRSTF (Bit 27) */
3161 #define RCC_CSR_PORRSTF_Msk                                                (0x8000000UL)    /*!< RCC CSR: PORRSTF (Bitfield-Mask: 0x01) */
3162 #define RCC_CSR_PORRSTF                                                    RCC_CSR_PORRSTF_Msk
3163 #define RCC_CSR_PADRSTF_Pos                                                (26UL)   /*!<RCC CSR: PADRSTF (Bit 26) */
3164 #define RCC_CSR_PADRSTF_Msk                                                (0x4000000UL)    /*!< RCC CSR: PADRSTF (Bitfield-Mask: 0x01) */
3165 #define RCC_CSR_PADRSTF                                                    RCC_CSR_PADRSTF_Msk
3166 #define RCC_CSR_RMVF_Pos                                                   (23UL)   /*!<RCC CSR: RMVF (Bit 23) */
3167 #define RCC_CSR_RMVF_Msk                                                   (0x800000UL)   /*!< RCC CSR: RMVF (Bitfield-Mask: 0x01) */
3168 #define RCC_CSR_RMVF                                                       RCC_CSR_RMVF_Msk
3169 
3170 /* =====================================================    RFSWHSECR    ===================================================== */
3171 #define RCC_RFSWHSECR_SWXOTUNE_Pos                                         (8UL)    /*!<RCC RFSWHSECR: SWXOTUNE (Bit 8) */
3172 #define RCC_RFSWHSECR_SWXOTUNE_Msk                                         (0x3f00UL)   /*!< RCC RFSWHSECR: SWXOTUNE (Bitfield-Mask: 0x3f) */
3173 #define RCC_RFSWHSECR_SWXOTUNE                                             RCC_RFSWHSECR_SWXOTUNE_Msk
3174 #define RCC_RFSWHSECR_SWXOTUNE_0                                           (0x1U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3175 #define RCC_RFSWHSECR_SWXOTUNE_1                                           (0x2U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3176 #define RCC_RFSWHSECR_SWXOTUNE_2                                           (0x4U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3177 #define RCC_RFSWHSECR_SWXOTUNE_3                                           (0x8U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3178 #define RCC_RFSWHSECR_SWXOTUNE_4                                           (0x10U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3179 #define RCC_RFSWHSECR_SWXOTUNE_5                                           (0x20U << RCC_RFSWHSECR_SWXOTUNE_Pos)
3180 #define RCC_RFSWHSECR_SWXOTUNEEN_Pos                                       (7UL)    /*!<RCC RFSWHSECR: SWXOTUNEEN (Bit 7) */
3181 #define RCC_RFSWHSECR_SWXOTUNEEN_Msk                                       (0x80UL)   /*!< RCC RFSWHSECR: SWXOTUNEEN (Bitfield-Mask: 0x01) */
3182 #define RCC_RFSWHSECR_SWXOTUNEEN                                           RCC_RFSWHSECR_SWXOTUNEEN_Msk
3183 #define RCC_RFSWHSECR_GMC_Pos                                              (4UL)    /*!<RCC RFSWHSECR: GMC (Bit 4) */
3184 #define RCC_RFSWHSECR_GMC_Msk                                              (0x70UL)   /*!< RCC RFSWHSECR: GMC (Bitfield-Mask: 0x07) */
3185 #define RCC_RFSWHSECR_GMC                                                  RCC_RFSWHSECR_GMC_Msk
3186 #define RCC_RFSWHSECR_GMC_0                                                (0x1U << RCC_RFSWHSECR_GMC_Pos)
3187 #define RCC_RFSWHSECR_GMC_1                                                (0x2U << RCC_RFSWHSECR_GMC_Pos)
3188 #define RCC_RFSWHSECR_GMC_2                                                (0x4U << RCC_RFSWHSECR_GMC_Pos)
3189 #define RCC_RFSWHSECR_SATRG_Pos                                            (3UL)    /*!<RCC RFSWHSECR: SATRG (Bit 3) */
3190 #define RCC_RFSWHSECR_SATRG_Msk                                            (0x8UL)    /*!< RCC RFSWHSECR: SATRG (Bitfield-Mask: 0x01) */
3191 #define RCC_RFSWHSECR_SATRG                                                RCC_RFSWHSECR_SATRG_Msk
3192 
3193 /* =====================================================    RFHSECR    ===================================================== */
3194 #define RCC_RFHSECR_XOTUNE_Pos                                             (0UL)    /*!<RCC RFHSECR: XOTUNE (Bit 0) */
3195 #define RCC_RFHSECR_XOTUNE_Msk                                             (0x3fUL)   /*!< RCC RFHSECR: XOTUNE (Bitfield-Mask: 0x3f) */
3196 #define RCC_RFHSECR_XOTUNE                                                 RCC_RFHSECR_XOTUNE_Msk
3197 #define RCC_RFHSECR_XOTUNE_0                                               (0x1U << RCC_RFHSECR_XOTUNE_Pos)
3198 #define RCC_RFHSECR_XOTUNE_1                                               (0x2U << RCC_RFHSECR_XOTUNE_Pos)
3199 #define RCC_RFHSECR_XOTUNE_2                                               (0x4U << RCC_RFHSECR_XOTUNE_Pos)
3200 #define RCC_RFHSECR_XOTUNE_3                                               (0x8U << RCC_RFHSECR_XOTUNE_Pos)
3201 #define RCC_RFHSECR_XOTUNE_4                                               (0x10U << RCC_RFHSECR_XOTUNE_Pos)
3202 #define RCC_RFHSECR_XOTUNE_5                                               (0x20U << RCC_RFHSECR_XOTUNE_Pos)
3203 
3204 
3205 /* =========================================================================================================================== */
3206 /*=====================                                       PWR                                       ===================== */
3207 /* =========================================================================================================================== */
3208 
3209 /* =====================================================    CR1    ===================================================== */
3210 #define PWR_CR1_APC_Pos                                                    (4UL)    /*!<PWR CR1: APC (Bit 4) */
3211 #define PWR_CR1_APC_Msk                                                    (0x10UL)   /*!< PWR CR1: APC (Bitfield-Mask: 0x01) */
3212 #define PWR_CR1_APC                                                        PWR_CR1_APC_Msk
3213 #define PWR_CR1_ENSDNBOR_Pos                                               (1UL)    /*!<PWR CR1: ENSDNBOR (Bit 1) */
3214 #define PWR_CR1_ENSDNBOR_Msk                                               (0x2UL)    /*!< PWR CR1: ENSDNBOR (Bitfield-Mask: 0x01) */
3215 #define PWR_CR1_ENSDNBOR                                                   PWR_CR1_ENSDNBOR_Msk
3216 #define PWR_CR1_LPMS_Pos                                                   (0UL)    /*!<PWR CR1: LPMS (Bit 0) */
3217 #define PWR_CR1_LPMS_Msk                                                   (0x1UL)    /*!< PWR CR1: LPMS (Bitfield-Mask: 0x01) */
3218 #define PWR_CR1_LPMS                                                       PWR_CR1_LPMS_Msk
3219 
3220 /* =====================================================    CR2    ===================================================== */
3221 #define PWR_CR2_LSILPMUFEN_Pos                                             (10UL)   /*!<PWR CR2: LSILPMUFEN (Bit 10) */
3222 #define PWR_CR2_LSILPMUFEN_Msk                                             (0x400UL)    /*!< PWR CR2: LSILPMUFEN (Bitfield-Mask: 0x01) */
3223 #define PWR_CR2_LSILPMUFEN                                                 PWR_CR2_LSILPMUFEN_Msk
3224 #define PWR_CR2_ENTS_Pos                                                   (9UL)    /*!<PWR CR2: ENTS (Bit 9) */
3225 #define PWR_CR2_ENTS_Msk                                                   (0x200UL)    /*!< PWR CR2: ENTS (Bitfield-Mask: 0x01) */
3226 #define PWR_CR2_ENTS                                                       PWR_CR2_ENTS_Msk
3227 #define PWR_CR2_SCALEMR_Pos                                                (8UL)    /*!<PWR CR2: SCALEMR (Bit 8) */
3228 #define PWR_CR2_SCALEMR_Msk                                                (0x100UL)    /*!< PWR CR2: SCALEMR (Bitfield-Mask: 0x01) */
3229 #define PWR_CR2_SCALEMR                                                    PWR_CR2_SCALEMR_Msk
3230 #define PWR_CR2_RAMRET3_Pos                                                (7UL)    /*!<PWR CR2: RAMRET3 (Bit 7) */
3231 #define PWR_CR2_RAMRET3_Msk                                                (0x80UL)   /*!< PWR CR2: RAMRET3 (Bitfield-Mask: 0x01) */
3232 #define PWR_CR2_RAMRET3                                                    PWR_CR2_RAMRET3_Msk
3233 #define PWR_CR2_RAMRET2_Pos                                                (6UL)    /*!<PWR CR2: RAMRET2 (Bit 6) */
3234 #define PWR_CR2_RAMRET2_Msk                                                (0x40UL)   /*!< PWR CR2: RAMRET2 (Bitfield-Mask: 0x01) */
3235 #define PWR_CR2_RAMRET2                                                    PWR_CR2_RAMRET2_Msk
3236 #define PWR_CR2_RAMRET1_Pos                                                (5UL)    /*!<PWR CR2: RAMRET1 (Bit 5) */
3237 #define PWR_CR2_RAMRET1_Msk                                                (0x20UL)   /*!< PWR CR2: RAMRET1 (Bitfield-Mask: 0x01) */
3238 #define PWR_CR2_RAMRET1                                                    PWR_CR2_RAMRET1_Msk
3239 #define PWR_CR2_PVDLS_Pos                                                  (1UL)    /*!<PWR CR2: PVDLS (Bit 1) */
3240 #define PWR_CR2_PVDLS_Msk                                                  (0xeUL)    /*!< PWR CR2: PVDLS (Bitfield-Mask: 0x07) */
3241 #define PWR_CR2_PVDLS                                                      PWR_CR2_PVDLS_Msk
3242 #define PWR_CR2_PVDLS_0                                                    (0x1U << PWR_CR2_PVDLS_Pos)
3243 #define PWR_CR2_PVDLS_1                                                    (0x2U << PWR_CR2_PVDLS_Pos)
3244 #define PWR_CR2_PVDLS_2                                                    (0x4U << PWR_CR2_PVDLS_Pos)
3245 #define PWR_CR2_PVDE_Pos                                                   (0UL)    /*!<PWR CR2: PVDE (Bit 0) */
3246 #define PWR_CR2_PVDE_Msk                                                   (0x1UL)    /*!< PWR CR2: PVDE (Bitfield-Mask: 0x01) */
3247 #define PWR_CR2_PVDE                                                       PWR_CR2_PVDE_Msk
3248 
3249 /* =====================================================    CR3    ===================================================== */
3250 #define PWR_CR3_EIWL_Pos                                                   (15UL)   /*!<PWR CR3: EIWL (Bit 15) */
3251 #define PWR_CR3_EIWL_Msk                                                   (0x8000UL)   /*!< PWR CR3: EIWL (Bitfield-Mask: 0x01) */
3252 #define PWR_CR3_EIWL                                                       PWR_CR3_EIWL_Msk
3253 #define PWR_CR3_EWBLEHCPU_Pos                                              (13UL)   /*!<PWR CR3: EWBLEHCPU (Bit 13) */
3254 #define PWR_CR3_EWBLEHCPU_Msk                                              (0x2000UL)   /*!< PWR CR3: EWBLEHCPU (Bitfield-Mask: 0x01) */
3255 #define PWR_CR3_EWBLEHCPU                                                  PWR_CR3_EWBLEHCPU_Msk
3256 #define PWR_CR3_EWBLE_Pos                                                  (12UL)   /*!<PWR CR3: EWBLE (Bit 12) */
3257 #define PWR_CR3_EWBLE_Msk                                                  (0x1000UL)   /*!< PWR CR3: EWBLE (Bitfield-Mask: 0x01) */
3258 #define PWR_CR3_EWBLE                                                      PWR_CR3_EWBLE_Msk
3259 #define PWR_CR3_EWU11_Pos                                                  (11UL)   /*!<PWR CR3: EWU11 (Bit 11) */
3260 #define PWR_CR3_EWU11_Msk                                                  (0x800UL)    /*!< PWR CR3: EWU11 (Bitfield-Mask: 0x01) */
3261 #define PWR_CR3_EWU11                                                      PWR_CR3_EWU11_Msk
3262 #define PWR_CR3_EWU10_Pos                                                  (10UL)   /*!<PWR CR3: EWU10 (Bit 10) */
3263 #define PWR_CR3_EWU10_Msk                                                  (0x400UL)    /*!< PWR CR3: EWU10 (Bitfield-Mask: 0x01) */
3264 #define PWR_CR3_EWU10                                                      PWR_CR3_EWU10_Msk
3265 #define PWR_CR3_EWU9_Pos                                                   (9UL)    /*!<PWR CR3: EWU9 (Bit 9) */
3266 #define PWR_CR3_EWU9_Msk                                                   (0x200UL)    /*!< PWR CR3: EWU9 (Bitfield-Mask: 0x01) */
3267 #define PWR_CR3_EWU9                                                       PWR_CR3_EWU9_Msk
3268 #define PWR_CR3_EWU8_Pos                                                   (8UL)    /*!<PWR CR3: EWU8 (Bit 8) */
3269 #define PWR_CR3_EWU8_Msk                                                   (0x100UL)    /*!< PWR CR3: EWU8 (Bitfield-Mask: 0x01) */
3270 #define PWR_CR3_EWU8                                                       PWR_CR3_EWU8_Msk
3271 #define PWR_CR3_EWU7_Pos                                                   (7UL)    /*!<PWR CR3: EWU7 (Bit 7) */
3272 #define PWR_CR3_EWU7_Msk                                                   (0x80UL)   /*!< PWR CR3: EWU7 (Bitfield-Mask: 0x01) */
3273 #define PWR_CR3_EWU7                                                       PWR_CR3_EWU7_Msk
3274 #define PWR_CR3_EWU6_Pos                                                   (6UL)    /*!<PWR CR3: EWU6 (Bit 6) */
3275 #define PWR_CR3_EWU6_Msk                                                   (0x40UL)   /*!< PWR CR3: EWU6 (Bitfield-Mask: 0x01) */
3276 #define PWR_CR3_EWU6                                                       PWR_CR3_EWU6_Msk
3277 #define PWR_CR3_EWU5_Pos                                                   (5UL)    /*!<PWR CR3: EWU5 (Bit 5) */
3278 #define PWR_CR3_EWU5_Msk                                                   (0x20UL)   /*!< PWR CR3: EWU5 (Bitfield-Mask: 0x01) */
3279 #define PWR_CR3_EWU5                                                       PWR_CR3_EWU5_Msk
3280 #define PWR_CR3_EWU4_Pos                                                   (4UL)    /*!<PWR CR3: EWU4 (Bit 4) */
3281 #define PWR_CR3_EWU4_Msk                                                   (0x10UL)   /*!< PWR CR3: EWU4 (Bitfield-Mask: 0x01) */
3282 #define PWR_CR3_EWU4                                                       PWR_CR3_EWU4_Msk
3283 #define PWR_CR3_EWU3_Pos                                                   (3UL)    /*!<PWR CR3: EWU3 (Bit 3) */
3284 #define PWR_CR3_EWU3_Msk                                                   (0x8UL)    /*!< PWR CR3: EWU3 (Bitfield-Mask: 0x01) */
3285 #define PWR_CR3_EWU3                                                       PWR_CR3_EWU3_Msk
3286 #define PWR_CR3_EWU2_Pos                                                   (2UL)    /*!<PWR CR3: EWU2 (Bit 2) */
3287 #define PWR_CR3_EWU2_Msk                                                   (0x4UL)    /*!< PWR CR3: EWU2 (Bitfield-Mask: 0x01) */
3288 #define PWR_CR3_EWU2                                                       PWR_CR3_EWU2_Msk
3289 #define PWR_CR3_EWU1_Pos                                                   (1UL)    /*!<PWR CR3: EWU1 (Bit 1) */
3290 #define PWR_CR3_EWU1_Msk                                                   (0x2UL)    /*!< PWR CR3: EWU1 (Bitfield-Mask: 0x01) */
3291 #define PWR_CR3_EWU1                                                       PWR_CR3_EWU1_Msk
3292 #define PWR_CR3_EWU0_Pos                                                   (0UL)    /*!<PWR CR3: EWU0 (Bit 0) */
3293 #define PWR_CR3_EWU0_Msk                                                   (0x1UL)    /*!< PWR CR3: EWU0 (Bitfield-Mask: 0x01) */
3294 #define PWR_CR3_EWU0                                                       PWR_CR3_EWU0_Msk
3295 
3296 /* =====================================================    CR4    ===================================================== */
3297 #define PWR_CR4_WUP11_Pos                                                  (11UL)   /*!<PWR CR4: WUP11 (Bit 11) */
3298 #define PWR_CR4_WUP11_Msk                                                  (0x800UL)    /*!< PWR CR4: WUP11 (Bitfield-Mask: 0x01) */
3299 #define PWR_CR4_WUP11                                                      PWR_CR4_WUP11_Msk
3300 #define PWR_CR4_WUP10_Pos                                                  (10UL)   /*!<PWR CR4: WUP10 (Bit 10) */
3301 #define PWR_CR4_WUP10_Msk                                                  (0x400UL)    /*!< PWR CR4: WUP10 (Bitfield-Mask: 0x01) */
3302 #define PWR_CR4_WUP10                                                      PWR_CR4_WUP10_Msk
3303 #define PWR_CR4_WUP9_Pos                                                   (9UL)    /*!<PWR CR4: WUP9 (Bit 9) */
3304 #define PWR_CR4_WUP9_Msk                                                   (0x200UL)    /*!< PWR CR4: WUP9 (Bitfield-Mask: 0x01) */
3305 #define PWR_CR4_WUP9                                                       PWR_CR4_WUP9_Msk
3306 #define PWR_CR4_WUP8_Pos                                                   (8UL)    /*!<PWR CR4: WUP8 (Bit 8) */
3307 #define PWR_CR4_WUP8_Msk                                                   (0x100UL)    /*!< PWR CR4: WUP8 (Bitfield-Mask: 0x01) */
3308 #define PWR_CR4_WUP8                                                       PWR_CR4_WUP8_Msk
3309 #define PWR_CR4_WUP7_Pos                                                   (7UL)    /*!<PWR CR4: WUP7 (Bit 7) */
3310 #define PWR_CR4_WUP7_Msk                                                   (0x80UL)   /*!< PWR CR4: WUP7 (Bitfield-Mask: 0x01) */
3311 #define PWR_CR4_WUP7                                                       PWR_CR4_WUP7_Msk
3312 #define PWR_CR4_WUP6_Pos                                                   (6UL)    /*!<PWR CR4: WUP6 (Bit 6) */
3313 #define PWR_CR4_WUP6_Msk                                                   (0x40UL)   /*!< PWR CR4: WUP6 (Bitfield-Mask: 0x01) */
3314 #define PWR_CR4_WUP6                                                       PWR_CR4_WUP6_Msk
3315 #define PWR_CR4_WUP5_Pos                                                   (5UL)    /*!<PWR CR4: WUP5 (Bit 5) */
3316 #define PWR_CR4_WUP5_Msk                                                   (0x20UL)   /*!< PWR CR4: WUP5 (Bitfield-Mask: 0x01) */
3317 #define PWR_CR4_WUP5                                                       PWR_CR4_WUP5_Msk
3318 #define PWR_CR4_WUP4_Pos                                                   (4UL)    /*!<PWR CR4: WUP4 (Bit 4) */
3319 #define PWR_CR4_WUP4_Msk                                                   (0x10UL)   /*!< PWR CR4: WUP4 (Bitfield-Mask: 0x01) */
3320 #define PWR_CR4_WUP4                                                       PWR_CR4_WUP4_Msk
3321 #define PWR_CR4_WUP3_Pos                                                   (3UL)    /*!<PWR CR4: WUP3 (Bit 3) */
3322 #define PWR_CR4_WUP3_Msk                                                   (0x8UL)    /*!< PWR CR4: WUP3 (Bitfield-Mask: 0x01) */
3323 #define PWR_CR4_WUP3                                                       PWR_CR4_WUP3_Msk
3324 #define PWR_CR4_WUP2_Pos                                                   (2UL)    /*!<PWR CR4: WUP2 (Bit 2) */
3325 #define PWR_CR4_WUP2_Msk                                                   (0x4UL)    /*!< PWR CR4: WUP2 (Bitfield-Mask: 0x01) */
3326 #define PWR_CR4_WUP2                                                       PWR_CR4_WUP2_Msk
3327 #define PWR_CR4_WUP1_Pos                                                   (1UL)    /*!<PWR CR4: WUP1 (Bit 1) */
3328 #define PWR_CR4_WUP1_Msk                                                   (0x2UL)    /*!< PWR CR4: WUP1 (Bitfield-Mask: 0x01) */
3329 #define PWR_CR4_WUP1                                                       PWR_CR4_WUP1_Msk
3330 #define PWR_CR4_WUP0_Pos                                                   (0UL)    /*!<PWR CR4: WUP0 (Bit 0) */
3331 #define PWR_CR4_WUP0_Msk                                                   (0x1UL)    /*!< PWR CR4: WUP0 (Bitfield-Mask: 0x01) */
3332 #define PWR_CR4_WUP0                                                       PWR_CR4_WUP0_Msk
3333 
3334 /* =====================================================    SR1    ===================================================== */
3335 #define PWR_SR1_IWUF_Pos                                                   (15UL)   /*!<PWR SR1: IWUF (Bit 15) */
3336 #define PWR_SR1_IWUF_Msk                                                   (0x8000UL)   /*!< PWR SR1: IWUF (Bitfield-Mask: 0x01) */
3337 #define PWR_SR1_IWUF                                                       PWR_SR1_IWUF_Msk
3338 #define PWR_SR1_WBLEHCPUF_Pos                                              (13UL)   /*!<PWR SR1: WBLEHCPUF (Bit 13) */
3339 #define PWR_SR1_WBLEHCPUF_Msk                                              (0x2000UL)   /*!< PWR SR1: WBLEHCPUF (Bitfield-Mask: 0x01) */
3340 #define PWR_SR1_WBLEHCPUF                                                  PWR_SR1_WBLEHCPUF_Msk
3341 #define PWR_SR1_WBLEF_Pos                                                  (12UL)   /*!<PWR SR1: WBLEF (Bit 12) */
3342 #define PWR_SR1_WBLEF_Msk                                                  (0x1000UL)   /*!< PWR SR1: WBLEF (Bitfield-Mask: 0x01) */
3343 #define PWR_SR1_WBLEF                                                      PWR_SR1_WBLEF_Msk
3344 #define PWR_SR1_WUF11_Pos                                                  (11UL)   /*!<PWR SR1: WUF11 (Bit 11) */
3345 #define PWR_SR1_WUF11_Msk                                                  (0x800UL)    /*!< PWR SR1: WUF11 (Bitfield-Mask: 0x01) */
3346 #define PWR_SR1_WUF11                                                      PWR_SR1_WUF11_Msk
3347 #define PWR_SR1_WUF10_Pos                                                  (10UL)   /*!<PWR SR1: WUF10 (Bit 10) */
3348 #define PWR_SR1_WUF10_Msk                                                  (0x400UL)    /*!< PWR SR1: WUF10 (Bitfield-Mask: 0x01) */
3349 #define PWR_SR1_WUF10                                                      PWR_SR1_WUF10_Msk
3350 #define PWR_SR1_WUF9_Pos                                                   (9UL)    /*!<PWR SR1: WUF9 (Bit 9) */
3351 #define PWR_SR1_WUF9_Msk                                                   (0x200UL)    /*!< PWR SR1: WUF9 (Bitfield-Mask: 0x01) */
3352 #define PWR_SR1_WUF9                                                       PWR_SR1_WUF9_Msk
3353 #define PWR_SR1_WUF8_Pos                                                   (8UL)    /*!<PWR SR1: WUF8 (Bit 8) */
3354 #define PWR_SR1_WUF8_Msk                                                   (0x100UL)    /*!< PWR SR1: WUF8 (Bitfield-Mask: 0x01) */
3355 #define PWR_SR1_WUF8                                                       PWR_SR1_WUF8_Msk
3356 #define PWR_SR1_WUF7_Pos                                                   (7UL)    /*!<PWR SR1: WUF7 (Bit 7) */
3357 #define PWR_SR1_WUF7_Msk                                                   (0x80UL)   /*!< PWR SR1: WUF7 (Bitfield-Mask: 0x01) */
3358 #define PWR_SR1_WUF7                                                       PWR_SR1_WUF7_Msk
3359 #define PWR_SR1_WUF6_Pos                                                   (6UL)    /*!<PWR SR1: WUF6 (Bit 6) */
3360 #define PWR_SR1_WUF6_Msk                                                   (0x40UL)   /*!< PWR SR1: WUF6 (Bitfield-Mask: 0x01) */
3361 #define PWR_SR1_WUF6                                                       PWR_SR1_WUF6_Msk
3362 #define PWR_SR1_WUF5_Pos                                                   (5UL)    /*!<PWR SR1: WUF5 (Bit 5) */
3363 #define PWR_SR1_WUF5_Msk                                                   (0x20UL)   /*!< PWR SR1: WUF5 (Bitfield-Mask: 0x01) */
3364 #define PWR_SR1_WUF5                                                       PWR_SR1_WUF5_Msk
3365 #define PWR_SR1_WUF4_Pos                                                   (4UL)    /*!<PWR SR1: WUF4 (Bit 4) */
3366 #define PWR_SR1_WUF4_Msk                                                   (0x10UL)   /*!< PWR SR1: WUF4 (Bitfield-Mask: 0x01) */
3367 #define PWR_SR1_WUF4                                                       PWR_SR1_WUF4_Msk
3368 #define PWR_SR1_WUF3_Pos                                                   (3UL)    /*!<PWR SR1: WUF3 (Bit 3) */
3369 #define PWR_SR1_WUF3_Msk                                                   (0x8UL)    /*!< PWR SR1: WUF3 (Bitfield-Mask: 0x01) */
3370 #define PWR_SR1_WUF3                                                       PWR_SR1_WUF3_Msk
3371 #define PWR_SR1_WUF2_Pos                                                   (2UL)    /*!<PWR SR1: WUF2 (Bit 2) */
3372 #define PWR_SR1_WUF2_Msk                                                   (0x4UL)    /*!< PWR SR1: WUF2 (Bitfield-Mask: 0x01) */
3373 #define PWR_SR1_WUF2                                                       PWR_SR1_WUF2_Msk
3374 #define PWR_SR1_WUF1_Pos                                                   (1UL)    /*!<PWR SR1: WUF1 (Bit 1) */
3375 #define PWR_SR1_WUF1_Msk                                                   (0x2UL)    /*!< PWR SR1: WUF1 (Bitfield-Mask: 0x01) */
3376 #define PWR_SR1_WUF1                                                       PWR_SR1_WUF1_Msk
3377 #define PWR_SR1_WUF0_Pos                                                   (0UL)    /*!<PWR SR1: WUF0 (Bit 0) */
3378 #define PWR_SR1_WUF0_Msk                                                   (0x1UL)    /*!< PWR SR1: WUF0 (Bitfield-Mask: 0x01) */
3379 #define PWR_SR1_WUF0                                                       PWR_SR1_WUF0_Msk
3380 
3381 /* =====================================================    SR2    ===================================================== */
3382 #define PWR_SR2_IOBOOTVAL_Pos                                              (12UL)   /*!<PWR SR2: IOBOOTVAL (Bit 12) */
3383 #define PWR_SR2_IOBOOTVAL_Msk                                              (0xf000UL)   /*!< PWR SR2: IOBOOTVAL (Bitfield-Mask: 0x0f) */
3384 #define PWR_SR2_IOBOOTVAL                                                  PWR_SR2_IOBOOTVAL_Msk
3385 #define PWR_SR2_IOBOOTVAL_0                                                (0x1U << PWR_SR2_IOBOOTVAL_Pos)
3386 #define PWR_SR2_IOBOOTVAL_1                                                (0x2U << PWR_SR2_IOBOOTVAL_Pos)
3387 #define PWR_SR2_IOBOOTVAL_2                                                (0x4U << PWR_SR2_IOBOOTVAL_Pos)
3388 #define PWR_SR2_IOBOOTVAL_3                                                (0x8U << PWR_SR2_IOBOOTVAL_Pos)
3389 #define PWR_SR2_PVDO_Pos                                                   (11UL)   /*!<PWR SR2: PVDO (Bit 11) */
3390 #define PWR_SR2_PVDO_Msk                                                   (0x800UL)    /*!< PWR SR2: PVDO (Bitfield-Mask: 0x01) */
3391 #define PWR_SR2_PVDO                                                       PWR_SR2_PVDO_Msk
3392 #define PWR_SR2_REGMS_Pos                                                  (9UL)    /*!<PWR SR2: REGMS (Bit 9) */
3393 #define PWR_SR2_REGMS_Msk                                                  (0x200UL)    /*!< PWR SR2: REGMS (Bitfield-Mask: 0x01) */
3394 #define PWR_SR2_REGMS                                                      PWR_SR2_REGMS_Msk
3395 #define PWR_SR2_REGLPS_Pos                                                 (8UL)    /*!<PWR SR2: REGLPS (Bit 8) */
3396 #define PWR_SR2_REGLPS_Msk                                                 (0x100UL)    /*!< PWR SR2: REGLPS (Bitfield-Mask: 0x01) */
3397 #define PWR_SR2_REGLPS                                                     PWR_SR2_REGLPS_Msk
3398 #define PWR_SR2_SMPSRDY_Pos                                                (2UL)    /*!<PWR SR2: SMPSRDY (Bit 2) */
3399 #define PWR_SR2_SMPSRDY_Msk                                                (0x4UL)    /*!< PWR SR2: SMPSRDY (Bitfield-Mask: 0x01) */
3400 #define PWR_SR2_SMPSRDY                                                    PWR_SR2_SMPSRDY_Msk
3401 #define PWR_SR2_SMPSENR_Pos                                                (1UL)    /*!<PWR SR2: SMPSENR (Bit 1) */
3402 #define PWR_SR2_SMPSENR_Msk                                                (0x2UL)    /*!< PWR SR2: SMPSENR (Bitfield-Mask: 0x01) */
3403 #define PWR_SR2_SMPSENR                                                    PWR_SR2_SMPSENR_Msk
3404 #define PWR_SR2_SMPSBYPR_Pos                                               (0UL)    /*!<PWR SR2: SMPSBYPR (Bit 0) */
3405 #define PWR_SR2_SMPSBYPR_Msk                                               (0x1UL)    /*!< PWR SR2: SMPSBYPR (Bitfield-Mask: 0x01) */
3406 #define PWR_SR2_SMPSBYPR                                                   PWR_SR2_SMPSBYPR_Msk
3407 
3408 /* =====================================================    CR5    ===================================================== */
3409 #define PWR_CR5_CLKDETR_DISABLE_Pos                                        (12UL)   /*!<PWR CR5: CLKDETR_DISABLE (Bit 12) */
3410 #define PWR_CR5_CLKDETR_DISABLE_Msk                                        (0x1000UL)   /*!< PWR CR5: CLKDETR_DISABLE (Bitfield-Mask: 0x01) */
3411 #define PWR_CR5_CLKDETR_DISABLE                                            PWR_CR5_CLKDETR_DISABLE_Msk
3412 #define PWR_CR5_SMPS_ENA_DCM_Pos                                           (11UL)   /*!<PWR CR5: SMPS_ENA_DCM (Bit 11) */
3413 #define PWR_CR5_SMPS_ENA_DCM_Msk                                           (0x800UL)    /*!< PWR CR5: SMPS_ENA_DCM (Bitfield-Mask: 0x01) */
3414 #define PWR_CR5_SMPS_ENA_DCM                                               PWR_CR5_SMPS_ENA_DCM_Msk
3415 #define PWR_CR5_NOSMPS_Pos                                                 (10UL)   /*!<PWR CR5: NOSMPS (Bit 10) */
3416 #define PWR_CR5_NOSMPS_Msk                                                 (0x400UL)    /*!< PWR CR5: NOSMPS (Bitfield-Mask: 0x01) */
3417 #define PWR_CR5_NOSMPS                                                     PWR_CR5_NOSMPS_Msk
3418 #define PWR_CR5_SMPSFBYP_Pos                                               (9UL)    /*!<PWR CR5: SMPSFBYP (Bit 9) */
3419 #define PWR_CR5_SMPSFBYP_Msk                                               (0x200UL)    /*!< PWR CR5: SMPSFBYP (Bitfield-Mask: 0x01) */
3420 #define PWR_CR5_SMPSFBYP                                                   PWR_CR5_SMPSFBYP_Msk
3421 #define PWR_CR5_SMPSLPOPEN_Pos                                             (8UL)    /*!<PWR CR5: SMPSLPOPEN (Bit 8) */
3422 #define PWR_CR5_SMPSLPOPEN_Msk                                             (0x100UL)    /*!< PWR CR5: SMPSLPOPEN (Bitfield-Mask: 0x01) */
3423 #define PWR_CR5_SMPSLPOPEN                                                 PWR_CR5_SMPSLPOPEN_Msk
3424 #define PWR_CR5_SMPSFRDY_Pos                                               (7UL)    /*!<PWR CR5: SMPSFRDY (Bit 7) */
3425 #define PWR_CR5_SMPSFRDY_Msk                                               (0x80UL)   /*!< PWR CR5: SMPSFRDY (Bitfield-Mask: 0x01) */
3426 #define PWR_CR5_SMPSFRDY                                                   PWR_CR5_SMPSFRDY_Msk
3427 #define PWR_CR5_SMPSBOMSEL_Pos                                             (4UL)    /*!<PWR CR5: SMPSBOMSEL (Bit 4) */
3428 #define PWR_CR5_SMPSBOMSEL_Msk                                             (0x30UL)   /*!< PWR CR5: SMPSBOMSEL (Bitfield-Mask: 0x03) */
3429 #define PWR_CR5_SMPSBOMSEL                                                 PWR_CR5_SMPSBOMSEL_Msk
3430 #define PWR_CR5_SMPSBOMSEL_0                                               (0x1U << PWR_CR5_SMPSBOMSEL_Pos)
3431 #define PWR_CR5_SMPSBOMSEL_1                                               (0x2U << PWR_CR5_SMPSBOMSEL_Pos)
3432 #define PWR_CR5_SMPSLVL_Pos                                                (0UL)    /*!<PWR CR5: SMPSLVL (Bit 0) */
3433 #define PWR_CR5_SMPSLVL_Msk                                                (0xfUL)    /*!< PWR CR5: SMPSLVL (Bitfield-Mask: 0x0f) */
3434 #define PWR_CR5_SMPSLVL                                                    PWR_CR5_SMPSLVL_Msk
3435 #define PWR_CR5_SMPSLVL_0                                                  (0x1U << PWR_CR5_SMPSLVL_Pos)
3436 #define PWR_CR5_SMPSLVL_1                                                  (0x2U << PWR_CR5_SMPSLVL_Pos)
3437 #define PWR_CR5_SMPSLVL_2                                                  (0x4U << PWR_CR5_SMPSLVL_Pos)
3438 #define PWR_CR5_SMPSLVL_3                                                  (0x8U << PWR_CR5_SMPSLVL_Pos)
3439 
3440 /* =====================================================    PUCRA    ===================================================== */
3441 #define PWR_PUCRA_PA15_Pos                                                 (15UL)   /*!<PWR PUCRA: PA15 (Bit 15) */
3442 #define PWR_PUCRA_PA15_Msk                                                 (0x8000UL)   /*!< PWR PUCRA: PA15 (Bitfield-Mask: 0x01) */
3443 #define PWR_PUCRA_PA15                                                     PWR_PUCRA_PA15_Msk
3444 #define PWR_PUCRA_PA14_Pos                                                 (14UL)   /*!<PWR PUCRA: PA14 (Bit 14) */
3445 #define PWR_PUCRA_PA14_Msk                                                 (0x4000UL)   /*!< PWR PUCRA: PA14 (Bitfield-Mask: 0x01) */
3446 #define PWR_PUCRA_PA14                                                     PWR_PUCRA_PA14_Msk
3447 #define PWR_PUCRA_PA13_Pos                                                 (13UL)   /*!<PWR PUCRA: PA13 (Bit 13) */
3448 #define PWR_PUCRA_PA13_Msk                                                 (0x2000UL)   /*!< PWR PUCRA: PA13 (Bitfield-Mask: 0x01) */
3449 #define PWR_PUCRA_PA13                                                     PWR_PUCRA_PA13_Msk
3450 #define PWR_PUCRA_PA12_Pos                                                 (12UL)   /*!<PWR PUCRA: PA12 (Bit 12) */
3451 #define PWR_PUCRA_PA12_Msk                                                 (0x1000UL)   /*!< PWR PUCRA: PA12 (Bitfield-Mask: 0x01) */
3452 #define PWR_PUCRA_PA12                                                     PWR_PUCRA_PA12_Msk
3453 #define PWR_PUCRA_PA11_Pos                                                 (11UL)   /*!<PWR PUCRA: PA11 (Bit 11) */
3454 #define PWR_PUCRA_PA11_Msk                                                 (0x800UL)    /*!< PWR PUCRA: PA11 (Bitfield-Mask: 0x01) */
3455 #define PWR_PUCRA_PA11                                                     PWR_PUCRA_PA11_Msk
3456 #define PWR_PUCRA_PA10_Pos                                                 (10UL)   /*!<PWR PUCRA: PA10 (Bit 10) */
3457 #define PWR_PUCRA_PA10_Msk                                                 (0x400UL)    /*!< PWR PUCRA: PA10 (Bitfield-Mask: 0x01) */
3458 #define PWR_PUCRA_PA10                                                     PWR_PUCRA_PA10_Msk
3459 #define PWR_PUCRA_PA9_Pos                                                  (9UL)    /*!<PWR PUCRA: PA9 (Bit 9) */
3460 #define PWR_PUCRA_PA9_Msk                                                  (0x200UL)    /*!< PWR PUCRA: PA9 (Bitfield-Mask: 0x01) */
3461 #define PWR_PUCRA_PA9                                                      PWR_PUCRA_PA9_Msk
3462 #define PWR_PUCRA_PA8_Pos                                                  (8UL)    /*!<PWR PUCRA: PA8 (Bit 8) */
3463 #define PWR_PUCRA_PA8_Msk                                                  (0x100UL)    /*!< PWR PUCRA: PA8 (Bitfield-Mask: 0x01) */
3464 #define PWR_PUCRA_PA8                                                      PWR_PUCRA_PA8_Msk
3465 #define PWR_PUCRA_PA7_Pos                                                  (7UL)    /*!<PWR PUCRA: PA7 (Bit 7) */
3466 #define PWR_PUCRA_PA7_Msk                                                  (0x80UL)   /*!< PWR PUCRA: PA7 (Bitfield-Mask: 0x01) */
3467 #define PWR_PUCRA_PA7                                                      PWR_PUCRA_PA7_Msk
3468 #define PWR_PUCRA_PA6_Pos                                                  (6UL)    /*!<PWR PUCRA: PA6 (Bit 6) */
3469 #define PWR_PUCRA_PA6_Msk                                                  (0x40UL)   /*!< PWR PUCRA: PA6 (Bitfield-Mask: 0x01) */
3470 #define PWR_PUCRA_PA6                                                      PWR_PUCRA_PA6_Msk
3471 #define PWR_PUCRA_PA5_Pos                                                  (5UL)    /*!<PWR PUCRA: PA5 (Bit 5) */
3472 #define PWR_PUCRA_PA5_Msk                                                  (0x20UL)   /*!< PWR PUCRA: PA5 (Bitfield-Mask: 0x01) */
3473 #define PWR_PUCRA_PA5                                                      PWR_PUCRA_PA5_Msk
3474 #define PWR_PUCRA_PA4_Pos                                                  (4UL)    /*!<PWR PUCRA: PA4 (Bit 4) */
3475 #define PWR_PUCRA_PA4_Msk                                                  (0x10UL)   /*!< PWR PUCRA: PA4 (Bitfield-Mask: 0x01) */
3476 #define PWR_PUCRA_PA4                                                      PWR_PUCRA_PA4_Msk
3477 #define PWR_PUCRA_PA3_Pos                                                  (3UL)    /*!<PWR PUCRA: PA3 (Bit 3) */
3478 #define PWR_PUCRA_PA3_Msk                                                  (0x8UL)    /*!< PWR PUCRA: PA3 (Bitfield-Mask: 0x01) */
3479 #define PWR_PUCRA_PA3                                                      PWR_PUCRA_PA3_Msk
3480 #define PWR_PUCRA_PA2_Pos                                                  (2UL)    /*!<PWR PUCRA: PA2 (Bit 2) */
3481 #define PWR_PUCRA_PA2_Msk                                                  (0x4UL)    /*!< PWR PUCRA: PA2 (Bitfield-Mask: 0x01) */
3482 #define PWR_PUCRA_PA2                                                      PWR_PUCRA_PA2_Msk
3483 #define PWR_PUCRA_PA1_Pos                                                  (1UL)    /*!<PWR PUCRA: PA1 (Bit 1) */
3484 #define PWR_PUCRA_PA1_Msk                                                  (0x2UL)    /*!< PWR PUCRA: PA1 (Bitfield-Mask: 0x01) */
3485 #define PWR_PUCRA_PA1                                                      PWR_PUCRA_PA1_Msk
3486 #define PWR_PUCRA_PA0_Pos                                                  (0UL)    /*!<PWR PUCRA: PA0 (Bit 0) */
3487 #define PWR_PUCRA_PA0_Msk                                                  (0x1UL)    /*!< PWR PUCRA: PA0 (Bitfield-Mask: 0x01) */
3488 #define PWR_PUCRA_PA0                                                      PWR_PUCRA_PA0_Msk
3489 
3490 /* =====================================================    PDCRA    ===================================================== */
3491 #define PWR_PDCRA_PA15_Pos                                                 (15UL)   /*!<PWR PDCRA: PA15 (Bit 15) */
3492 #define PWR_PDCRA_PA15_Msk                                                 (0x8000UL)   /*!< PWR PDCRA: PA15 (Bitfield-Mask: 0x01) */
3493 #define PWR_PDCRA_PA15                                                     PWR_PDCRA_PA15_Msk
3494 #define PWR_PDCRA_PA14_Pos                                                 (14UL)   /*!<PWR PDCRA: PA14 (Bit 14) */
3495 #define PWR_PDCRA_PA14_Msk                                                 (0x4000UL)   /*!< PWR PDCRA: PA14 (Bitfield-Mask: 0x01) */
3496 #define PWR_PDCRA_PA14                                                     PWR_PDCRA_PA14_Msk
3497 #define PWR_PDCRA_PA13_Pos                                                 (13UL)   /*!<PWR PDCRA: PA13 (Bit 13) */
3498 #define PWR_PDCRA_PA13_Msk                                                 (0x2000UL)   /*!< PWR PDCRA: PA13 (Bitfield-Mask: 0x01) */
3499 #define PWR_PDCRA_PA13                                                     PWR_PDCRA_PA13_Msk
3500 #define PWR_PDCRA_PA12_Pos                                                 (12UL)   /*!<PWR PDCRA: PA12 (Bit 12) */
3501 #define PWR_PDCRA_PA12_Msk                                                 (0x1000UL)   /*!< PWR PDCRA: PA12 (Bitfield-Mask: 0x01) */
3502 #define PWR_PDCRA_PA12                                                     PWR_PDCRA_PA12_Msk
3503 #define PWR_PDCRA_PA11_Pos                                                 (11UL)   /*!<PWR PDCRA: PA11 (Bit 11) */
3504 #define PWR_PDCRA_PA11_Msk                                                 (0x800UL)    /*!< PWR PDCRA: PA11 (Bitfield-Mask: 0x01) */
3505 #define PWR_PDCRA_PA11                                                     PWR_PDCRA_PA11_Msk
3506 #define PWR_PDCRA_PA10_Pos                                                 (10UL)   /*!<PWR PDCRA: PA10 (Bit 10) */
3507 #define PWR_PDCRA_PA10_Msk                                                 (0x400UL)    /*!< PWR PDCRA: PA10 (Bitfield-Mask: 0x01) */
3508 #define PWR_PDCRA_PA10                                                     PWR_PDCRA_PA10_Msk
3509 #define PWR_PDCRA_PA9_Pos                                                  (9UL)    /*!<PWR PDCRA: PA9 (Bit 9) */
3510 #define PWR_PDCRA_PA9_Msk                                                  (0x200UL)    /*!< PWR PDCRA: PA9 (Bitfield-Mask: 0x01) */
3511 #define PWR_PDCRA_PA9                                                      PWR_PDCRA_PA9_Msk
3512 #define PWR_PDCRA_PA8_Pos                                                  (8UL)    /*!<PWR PDCRA: PA8 (Bit 8) */
3513 #define PWR_PDCRA_PA8_Msk                                                  (0x100UL)    /*!< PWR PDCRA: PA8 (Bitfield-Mask: 0x01) */
3514 #define PWR_PDCRA_PA8                                                      PWR_PDCRA_PA8_Msk
3515 #define PWR_PDCRA_PA7_Pos                                                  (7UL)    /*!<PWR PDCRA: PA7 (Bit 7) */
3516 #define PWR_PDCRA_PA7_Msk                                                  (0x80UL)   /*!< PWR PDCRA: PA7 (Bitfield-Mask: 0x01) */
3517 #define PWR_PDCRA_PA7                                                      PWR_PDCRA_PA7_Msk
3518 #define PWR_PDCRA_PA6_Pos                                                  (6UL)    /*!<PWR PDCRA: PA6 (Bit 6) */
3519 #define PWR_PDCRA_PA6_Msk                                                  (0x40UL)   /*!< PWR PDCRA: PA6 (Bitfield-Mask: 0x01) */
3520 #define PWR_PDCRA_PA6                                                      PWR_PDCRA_PA6_Msk
3521 #define PWR_PDCRA_PA5_Pos                                                  (5UL)    /*!<PWR PDCRA: PA5 (Bit 5) */
3522 #define PWR_PDCRA_PA5_Msk                                                  (0x20UL)   /*!< PWR PDCRA: PA5 (Bitfield-Mask: 0x01) */
3523 #define PWR_PDCRA_PA5                                                      PWR_PDCRA_PA5_Msk
3524 #define PWR_PDCRA_PA4_Pos                                                  (4UL)    /*!<PWR PDCRA: PA4 (Bit 4) */
3525 #define PWR_PDCRA_PA4_Msk                                                  (0x10UL)   /*!< PWR PDCRA: PA4 (Bitfield-Mask: 0x01) */
3526 #define PWR_PDCRA_PA4                                                      PWR_PDCRA_PA4_Msk
3527 #define PWR_PDCRA_PA3_Pos                                                  (3UL)    /*!<PWR PDCRA: PA3 (Bit 3) */
3528 #define PWR_PDCRA_PA3_Msk                                                  (0x8UL)    /*!< PWR PDCRA: PA3 (Bitfield-Mask: 0x01) */
3529 #define PWR_PDCRA_PA3                                                      PWR_PDCRA_PA3_Msk
3530 #define PWR_PDCRA_PA2_Pos                                                  (2UL)    /*!<PWR PDCRA: PA2 (Bit 2) */
3531 #define PWR_PDCRA_PA2_Msk                                                  (0x4UL)    /*!< PWR PDCRA: PA2 (Bitfield-Mask: 0x01) */
3532 #define PWR_PDCRA_PA2                                                      PWR_PDCRA_PA2_Msk
3533 #define PWR_PDCRA_PA1_Pos                                                  (1UL)    /*!<PWR PDCRA: PA1 (Bit 1) */
3534 #define PWR_PDCRA_PA1_Msk                                                  (0x2UL)    /*!< PWR PDCRA: PA1 (Bitfield-Mask: 0x01) */
3535 #define PWR_PDCRA_PA1                                                      PWR_PDCRA_PA1_Msk
3536 #define PWR_PDCRA_PA0_Pos                                                  (0UL)    /*!<PWR PDCRA: PA0 (Bit 0) */
3537 #define PWR_PDCRA_PA0_Msk                                                  (0x1UL)    /*!< PWR PDCRA: PA0 (Bitfield-Mask: 0x01) */
3538 #define PWR_PDCRA_PA0                                                      PWR_PDCRA_PA0_Msk
3539 
3540 /* =====================================================    PUCRB    ===================================================== */
3541 #define PWR_PUCRB_PB15_Pos                                                 (15UL)   /*!<PWR PUCRB: PB15 (Bit 15) */
3542 #define PWR_PUCRB_PB15_Msk                                                 (0x8000UL)   /*!< PWR PUCRB: PB15 (Bitfield-Mask: 0x01) */
3543 #define PWR_PUCRB_PB15                                                     PWR_PUCRB_PB15_Msk
3544 #define PWR_PUCRB_PB14_Pos                                                 (14UL)   /*!<PWR PUCRB: PB14 (Bit 14) */
3545 #define PWR_PUCRB_PB14_Msk                                                 (0x4000UL)   /*!< PWR PUCRB: PB14 (Bitfield-Mask: 0x01) */
3546 #define PWR_PUCRB_PB14                                                     PWR_PUCRB_PB14_Msk
3547 #define PWR_PUCRB_PB13_Pos                                                 (13UL)   /*!<PWR PUCRB: PB13 (Bit 13) */
3548 #define PWR_PUCRB_PB13_Msk                                                 (0x2000UL)   /*!< PWR PUCRB: PB13 (Bitfield-Mask: 0x01) */
3549 #define PWR_PUCRB_PB13                                                     PWR_PUCRB_PB13_Msk
3550 #define PWR_PUCRB_PB12_Pos                                                 (12UL)   /*!<PWR PUCRB: PB12 (Bit 12) */
3551 #define PWR_PUCRB_PB12_Msk                                                 (0x1000UL)   /*!< PWR PUCRB: PB12 (Bitfield-Mask: 0x01) */
3552 #define PWR_PUCRB_PB12                                                     PWR_PUCRB_PB12_Msk
3553 #define PWR_PUCRB_PB11_Pos                                                 (11UL)   /*!<PWR PUCRB: PB11 (Bit 11) */
3554 #define PWR_PUCRB_PB11_Msk                                                 (0x800UL)    /*!< PWR PUCRB: PB11 (Bitfield-Mask: 0x01) */
3555 #define PWR_PUCRB_PB11                                                     PWR_PUCRB_PB11_Msk
3556 #define PWR_PUCRB_PB10_Pos                                                 (10UL)   /*!<PWR PUCRB: PB10 (Bit 10) */
3557 #define PWR_PUCRB_PB10_Msk                                                 (0x400UL)    /*!< PWR PUCRB: PB10 (Bitfield-Mask: 0x01) */
3558 #define PWR_PUCRB_PB10                                                     PWR_PUCRB_PB10_Msk
3559 #define PWR_PUCRB_PB9_Pos                                                  (9UL)    /*!<PWR PUCRB: PB9 (Bit 9) */
3560 #define PWR_PUCRB_PB9_Msk                                                  (0x200UL)    /*!< PWR PUCRB: PB9 (Bitfield-Mask: 0x01) */
3561 #define PWR_PUCRB_PB9                                                      PWR_PUCRB_PB9_Msk
3562 #define PWR_PUCRB_PB8_Pos                                                  (8UL)    /*!<PWR PUCRB: PB8 (Bit 8) */
3563 #define PWR_PUCRB_PB8_Msk                                                  (0x100UL)    /*!< PWR PUCRB: PB8 (Bitfield-Mask: 0x01) */
3564 #define PWR_PUCRB_PB8                                                      PWR_PUCRB_PB8_Msk
3565 #define PWR_PUCRB_PB7_Pos                                                  (7UL)    /*!<PWR PUCRB: PB7 (Bit 7) */
3566 #define PWR_PUCRB_PB7_Msk                                                  (0x80UL)   /*!< PWR PUCRB: PB7 (Bitfield-Mask: 0x01) */
3567 #define PWR_PUCRB_PB7                                                      PWR_PUCRB_PB7_Msk
3568 #define PWR_PUCRB_PB6_Pos                                                  (6UL)    /*!<PWR PUCRB: PB6 (Bit 6) */
3569 #define PWR_PUCRB_PB6_Msk                                                  (0x40UL)   /*!< PWR PUCRB: PB6 (Bitfield-Mask: 0x01) */
3570 #define PWR_PUCRB_PB6                                                      PWR_PUCRB_PB6_Msk
3571 #define PWR_PUCRB_PB5_Pos                                                  (5UL)    /*!<PWR PUCRB: PB5 (Bit 5) */
3572 #define PWR_PUCRB_PB5_Msk                                                  (0x20UL)   /*!< PWR PUCRB: PB5 (Bitfield-Mask: 0x01) */
3573 #define PWR_PUCRB_PB5                                                      PWR_PUCRB_PB5_Msk
3574 #define PWR_PUCRB_PB4_Pos                                                  (4UL)    /*!<PWR PUCRB: PB4 (Bit 4) */
3575 #define PWR_PUCRB_PB4_Msk                                                  (0x10UL)   /*!< PWR PUCRB: PB4 (Bitfield-Mask: 0x01) */
3576 #define PWR_PUCRB_PB4                                                      PWR_PUCRB_PB4_Msk
3577 #define PWR_PUCRB_PB3_Pos                                                  (3UL)    /*!<PWR PUCRB: PB3 (Bit 3) */
3578 #define PWR_PUCRB_PB3_Msk                                                  (0x8UL)    /*!< PWR PUCRB: PB3 (Bitfield-Mask: 0x01) */
3579 #define PWR_PUCRB_PB3                                                      PWR_PUCRB_PB3_Msk
3580 #define PWR_PUCRB_PB2_Pos                                                  (2UL)    /*!<PWR PUCRB: PB2 (Bit 2) */
3581 #define PWR_PUCRB_PB2_Msk                                                  (0x4UL)    /*!< PWR PUCRB: PB2 (Bitfield-Mask: 0x01) */
3582 #define PWR_PUCRB_PB2                                                      PWR_PUCRB_PB2_Msk
3583 #define PWR_PUCRB_PB1_Pos                                                  (1UL)    /*!<PWR PUCRB: PB1 (Bit 1) */
3584 #define PWR_PUCRB_PB1_Msk                                                  (0x2UL)    /*!< PWR PUCRB: PB1 (Bitfield-Mask: 0x01) */
3585 #define PWR_PUCRB_PB1                                                      PWR_PUCRB_PB1_Msk
3586 #define PWR_PUCRB_PB0_Pos                                                  (0UL)    /*!<PWR PUCRB: PB0 (Bit 0) */
3587 #define PWR_PUCRB_PB0_Msk                                                  (0x1UL)    /*!< PWR PUCRB: PB0 (Bitfield-Mask: 0x01) */
3588 #define PWR_PUCRB_PB0                                                      PWR_PUCRB_PB0_Msk
3589 
3590 /* =====================================================    PDCRB    ===================================================== */
3591 #define PWR_PDCRB_PB15_Pos                                                 (15UL)   /*!<PWR PDCRB: PB15 (Bit 15) */
3592 #define PWR_PDCRB_PB15_Msk                                                 (0x8000UL)   /*!< PWR PDCRB: PB15 (Bitfield-Mask: 0x01) */
3593 #define PWR_PDCRB_PB15                                                     PWR_PDCRB_PB15_Msk
3594 #define PWR_PDCRB_PB14_Pos                                                 (14UL)   /*!<PWR PDCRB: PB14 (Bit 14) */
3595 #define PWR_PDCRB_PB14_Msk                                                 (0x4000UL)   /*!< PWR PDCRB: PB14 (Bitfield-Mask: 0x01) */
3596 #define PWR_PDCRB_PB14                                                     PWR_PDCRB_PB14_Msk
3597 #define PWR_PDCRB_PB13_Pos                                                 (13UL)   /*!<PWR PDCRB: PB13 (Bit 13) */
3598 #define PWR_PDCRB_PB13_Msk                                                 (0x2000UL)   /*!< PWR PDCRB: PB13 (Bitfield-Mask: 0x01) */
3599 #define PWR_PDCRB_PB13                                                     PWR_PDCRB_PB13_Msk
3600 #define PWR_PDCRB_PB12_Pos                                                 (12UL)   /*!<PWR PDCRB: PB12 (Bit 12) */
3601 #define PWR_PDCRB_PB12_Msk                                                 (0x1000UL)   /*!< PWR PDCRB: PB12 (Bitfield-Mask: 0x01) */
3602 #define PWR_PDCRB_PB12                                                     PWR_PDCRB_PB12_Msk
3603 #define PWR_PDCRB_PB11_Pos                                                 (11UL)   /*!<PWR PDCRB: PB11 (Bit 11) */
3604 #define PWR_PDCRB_PB11_Msk                                                 (0x800UL)    /*!< PWR PDCRB: PB11 (Bitfield-Mask: 0x01) */
3605 #define PWR_PDCRB_PB11                                                     PWR_PDCRB_PB11_Msk
3606 #define PWR_PDCRB_PB10_Pos                                                 (10UL)   /*!<PWR PDCRB: PB10 (Bit 10) */
3607 #define PWR_PDCRB_PB10_Msk                                                 (0x400UL)    /*!< PWR PDCRB: PB10 (Bitfield-Mask: 0x01) */
3608 #define PWR_PDCRB_PB10                                                     PWR_PDCRB_PB10_Msk
3609 #define PWR_PDCRB_PB9_Pos                                                  (9UL)    /*!<PWR PDCRB: PB9 (Bit 9) */
3610 #define PWR_PDCRB_PB9_Msk                                                  (0x200UL)    /*!< PWR PDCRB: PB9 (Bitfield-Mask: 0x01) */
3611 #define PWR_PDCRB_PB9                                                      PWR_PDCRB_PB9_Msk
3612 #define PWR_PDCRB_PB8_Pos                                                  (8UL)    /*!<PWR PDCRB: PB8 (Bit 8) */
3613 #define PWR_PDCRB_PB8_Msk                                                  (0x100UL)    /*!< PWR PDCRB: PB8 (Bitfield-Mask: 0x01) */
3614 #define PWR_PDCRB_PB8                                                      PWR_PDCRB_PB8_Msk
3615 #define PWR_PDCRB_PB7_Pos                                                  (7UL)    /*!<PWR PDCRB: PB7 (Bit 7) */
3616 #define PWR_PDCRB_PB7_Msk                                                  (0x80UL)   /*!< PWR PDCRB: PB7 (Bitfield-Mask: 0x01) */
3617 #define PWR_PDCRB_PB7                                                      PWR_PDCRB_PB7_Msk
3618 #define PWR_PDCRB_PB6_Pos                                                  (6UL)    /*!<PWR PDCRB: PB6 (Bit 6) */
3619 #define PWR_PDCRB_PB6_Msk                                                  (0x40UL)   /*!< PWR PDCRB: PB6 (Bitfield-Mask: 0x01) */
3620 #define PWR_PDCRB_PB6                                                      PWR_PDCRB_PB6_Msk
3621 #define PWR_PDCRB_PB5_Pos                                                  (5UL)    /*!<PWR PDCRB: PB5 (Bit 5) */
3622 #define PWR_PDCRB_PB5_Msk                                                  (0x20UL)   /*!< PWR PDCRB: PB5 (Bitfield-Mask: 0x01) */
3623 #define PWR_PDCRB_PB5                                                      PWR_PDCRB_PB5_Msk
3624 #define PWR_PDCRB_PB4_Pos                                                  (4UL)    /*!<PWR PDCRB: PB4 (Bit 4) */
3625 #define PWR_PDCRB_PB4_Msk                                                  (0x10UL)   /*!< PWR PDCRB: PB4 (Bitfield-Mask: 0x01) */
3626 #define PWR_PDCRB_PB4                                                      PWR_PDCRB_PB4_Msk
3627 #define PWR_PDCRB_PB3_Pos                                                  (3UL)    /*!<PWR PDCRB: PB3 (Bit 3) */
3628 #define PWR_PDCRB_PB3_Msk                                                  (0x8UL)    /*!< PWR PDCRB: PB3 (Bitfield-Mask: 0x01) */
3629 #define PWR_PDCRB_PB3                                                      PWR_PDCRB_PB3_Msk
3630 #define PWR_PDCRB_PB2_Pos                                                  (2UL)    /*!<PWR PDCRB: PB2 (Bit 2) */
3631 #define PWR_PDCRB_PB2_Msk                                                  (0x4UL)    /*!< PWR PDCRB: PB2 (Bitfield-Mask: 0x01) */
3632 #define PWR_PDCRB_PB2                                                      PWR_PDCRB_PB2_Msk
3633 #define PWR_PDCRB_PB1_Pos                                                  (1UL)    /*!<PWR PDCRB: PB1 (Bit 1) */
3634 #define PWR_PDCRB_PB1_Msk                                                  (0x2UL)    /*!< PWR PDCRB: PB1 (Bitfield-Mask: 0x01) */
3635 #define PWR_PDCRB_PB1                                                      PWR_PDCRB_PB1_Msk
3636 #define PWR_PDCRB_PB0_Pos                                                  (0UL)    /*!<PWR PDCRB: PB0 (Bit 0) */
3637 #define PWR_PDCRB_PB0_Msk                                                  (0x1UL)    /*!< PWR PDCRB: PB0 (Bitfield-Mask: 0x01) */
3638 #define PWR_PDCRB_PB0                                                      PWR_PDCRB_PB0_Msk
3639 
3640 /* =====================================================    CR6    ===================================================== */
3641 #define PWR_CR6_EWU27_Pos                                                  (15UL)   /*!<PWR CR6: EWU27 (Bit 15) */
3642 #define PWR_CR6_EWU27_Msk                                                  (0x8000UL)   /*!< PWR CR6: EWU27 (Bitfield-Mask: 0x01) */
3643 #define PWR_CR6_EWU27                                                      PWR_CR6_EWU27_Msk
3644 #define PWR_CR6_EWU26_Pos                                                  (14UL)   /*!<PWR CR6: EWU26 (Bit 14) */
3645 #define PWR_CR6_EWU26_Msk                                                  (0x4000UL)   /*!< PWR CR6: EWU26 (Bitfield-Mask: 0x01) */
3646 #define PWR_CR6_EWU26                                                      PWR_CR6_EWU26_Msk
3647 #define PWR_CR6_EWU25_Pos                                                  (13UL)   /*!<PWR CR6: EWU25 (Bit 13) */
3648 #define PWR_CR6_EWU25_Msk                                                  (0x2000UL)   /*!< PWR CR6: EWU25 (Bitfield-Mask: 0x01) */
3649 #define PWR_CR6_EWU25                                                      PWR_CR6_EWU25_Msk
3650 #define PWR_CR6_EWU24_Pos                                                  (12UL)   /*!<PWR CR6: EWU24 (Bit 12) */
3651 #define PWR_CR6_EWU24_Msk                                                  (0x1000UL)   /*!< PWR CR6: EWU24 (Bitfield-Mask: 0x01) */
3652 #define PWR_CR6_EWU24                                                      PWR_CR6_EWU24_Msk
3653 #define PWR_CR6_EWU23_Pos                                                  (11UL)   /*!<PWR CR6: EWU23 (Bit 11) */
3654 #define PWR_CR6_EWU23_Msk                                                  (0x800UL)    /*!< PWR CR6: EWU23 (Bitfield-Mask: 0x01) */
3655 #define PWR_CR6_EWU23                                                      PWR_CR6_EWU23_Msk
3656 #define PWR_CR6_EWU22_Pos                                                  (10UL)   /*!<PWR CR6: EWU22 (Bit 10) */
3657 #define PWR_CR6_EWU22_Msk                                                  (0x400UL)    /*!< PWR CR6: EWU22 (Bitfield-Mask: 0x01) */
3658 #define PWR_CR6_EWU22                                                      PWR_CR6_EWU22_Msk
3659 #define PWR_CR6_EWU21_Pos                                                  (9UL)    /*!<PWR CR6: EWU21 (Bit 9) */
3660 #define PWR_CR6_EWU21_Msk                                                  (0x200UL)    /*!< PWR CR6: EWU21 (Bitfield-Mask: 0x01) */
3661 #define PWR_CR6_EWU21                                                      PWR_CR6_EWU21_Msk
3662 #define PWR_CR6_EWU20_Pos                                                  (8UL)    /*!<PWR CR6: EWU20 (Bit 8) */
3663 #define PWR_CR6_EWU20_Msk                                                  (0x100UL)    /*!< PWR CR6: EWU20 (Bitfield-Mask: 0x01) */
3664 #define PWR_CR6_EWU20                                                      PWR_CR6_EWU20_Msk
3665 #define PWR_CR6_EWU19_Pos                                                  (7UL)    /*!<PWR CR6: EWU19 (Bit 7) */
3666 #define PWR_CR6_EWU19_Msk                                                  (0x80UL)   /*!< PWR CR6: EWU19 (Bitfield-Mask: 0x01) */
3667 #define PWR_CR6_EWU19                                                      PWR_CR6_EWU19_Msk
3668 #define PWR_CR6_EWU18_Pos                                                  (6UL)    /*!<PWR CR6: EWU18 (Bit 6) */
3669 #define PWR_CR6_EWU18_Msk                                                  (0x40UL)   /*!< PWR CR6: EWU18 (Bitfield-Mask: 0x01) */
3670 #define PWR_CR6_EWU18                                                      PWR_CR6_EWU18_Msk
3671 #define PWR_CR6_EWU17_Pos                                                  (5UL)    /*!<PWR CR6: EWU17 (Bit 5) */
3672 #define PWR_CR6_EWU17_Msk                                                  (0x20UL)   /*!< PWR CR6: EWU17 (Bitfield-Mask: 0x01) */
3673 #define PWR_CR6_EWU17                                                      PWR_CR6_EWU17_Msk
3674 #define PWR_CR6_EWU16_Pos                                                  (4UL)    /*!<PWR CR6: EWU16 (Bit 4) */
3675 #define PWR_CR6_EWU16_Msk                                                  (0x10UL)   /*!< PWR CR6: EWU16 (Bitfield-Mask: 0x01) */
3676 #define PWR_CR6_EWU16                                                      PWR_CR6_EWU16_Msk
3677 #define PWR_CR6_EWU15_Pos                                                  (3UL)    /*!<PWR CR6: EWU15 (Bit 3) */
3678 #define PWR_CR6_EWU15_Msk                                                  (0x8UL)    /*!< PWR CR6: EWU15 (Bitfield-Mask: 0x01) */
3679 #define PWR_CR6_EWU15                                                      PWR_CR6_EWU15_Msk
3680 #define PWR_CR6_EWU14_Pos                                                  (2UL)    /*!<PWR CR6: EWU14 (Bit 2) */
3681 #define PWR_CR6_EWU14_Msk                                                  (0x4UL)    /*!< PWR CR6: EWU14 (Bitfield-Mask: 0x01) */
3682 #define PWR_CR6_EWU14                                                      PWR_CR6_EWU14_Msk
3683 #define PWR_CR6_EWU13_Pos                                                  (1UL)    /*!<PWR CR6: EWU13 (Bit 1) */
3684 #define PWR_CR6_EWU13_Msk                                                  (0x2UL)    /*!< PWR CR6: EWU13 (Bitfield-Mask: 0x01) */
3685 #define PWR_CR6_EWU13                                                      PWR_CR6_EWU13_Msk
3686 #define PWR_CR6_EWU12_Pos                                                  (0UL)    /*!<PWR CR6: EWU12 (Bit 0) */
3687 #define PWR_CR6_EWU12_Msk                                                  (0x1UL)    /*!< PWR CR6: EWU12 (Bitfield-Mask: 0x01) */
3688 #define PWR_CR6_EWU12                                                      PWR_CR6_EWU12_Msk
3689 
3690 /* =====================================================    CR7    ===================================================== */
3691 #define PWR_CR7_WUP27_Pos                                                  (15UL)   /*!<PWR CR7: WUP27 (Bit 15) */
3692 #define PWR_CR7_WUP27_Msk                                                  (0x8000UL)   /*!< PWR CR7: WUP27 (Bitfield-Mask: 0x01) */
3693 #define PWR_CR7_WUP27                                                      PWR_CR7_WUP27_Msk
3694 #define PWR_CR7_WUP26_Pos                                                  (14UL)   /*!<PWR CR7: WUP26 (Bit 14) */
3695 #define PWR_CR7_WUP26_Msk                                                  (0x4000UL)   /*!< PWR CR7: WUP26 (Bitfield-Mask: 0x01) */
3696 #define PWR_CR7_WUP26                                                      PWR_CR7_WUP26_Msk
3697 #define PWR_CR7_WUP25_Pos                                                  (13UL)   /*!<PWR CR7: WUP25 (Bit 13) */
3698 #define PWR_CR7_WUP25_Msk                                                  (0x2000UL)   /*!< PWR CR7: WUP25 (Bitfield-Mask: 0x01) */
3699 #define PWR_CR7_WUP25                                                      PWR_CR7_WUP25_Msk
3700 #define PWR_CR7_WUP24_Pos                                                  (12UL)   /*!<PWR CR7: WUP24 (Bit 12) */
3701 #define PWR_CR7_WUP24_Msk                                                  (0x1000UL)   /*!< PWR CR7: WUP24 (Bitfield-Mask: 0x01) */
3702 #define PWR_CR7_WUP24                                                      PWR_CR7_WUP24_Msk
3703 #define PWR_CR7_WUP23_Pos                                                  (11UL)   /*!<PWR CR7: WUP23 (Bit 11) */
3704 #define PWR_CR7_WUP23_Msk                                                  (0x800UL)    /*!< PWR CR7: WUP23 (Bitfield-Mask: 0x01) */
3705 #define PWR_CR7_WUP23                                                      PWR_CR7_WUP23_Msk
3706 #define PWR_CR7_WUP22_Pos                                                  (10UL)   /*!<PWR CR7: WUP22 (Bit 10) */
3707 #define PWR_CR7_WUP22_Msk                                                  (0x400UL)    /*!< PWR CR7: WUP22 (Bitfield-Mask: 0x01) */
3708 #define PWR_CR7_WUP22                                                      PWR_CR7_WUP22_Msk
3709 #define PWR_CR7_WUP21_Pos                                                  (9UL)    /*!<PWR CR7: WUP21 (Bit 9) */
3710 #define PWR_CR7_WUP21_Msk                                                  (0x200UL)    /*!< PWR CR7: WUP21 (Bitfield-Mask: 0x01) */
3711 #define PWR_CR7_WUP21                                                      PWR_CR7_WUP21_Msk
3712 #define PWR_CR7_WUP20_Pos                                                  (8UL)    /*!<PWR CR7: WUP20 (Bit 8) */
3713 #define PWR_CR7_WUP20_Msk                                                  (0x100UL)    /*!< PWR CR7: WUP20 (Bitfield-Mask: 0x01) */
3714 #define PWR_CR7_WUP20                                                      PWR_CR7_WUP20_Msk
3715 #define PWR_CR7_WUP19_Pos                                                  (7UL)    /*!<PWR CR7: WUP19 (Bit 7) */
3716 #define PWR_CR7_WUP19_Msk                                                  (0x80UL)   /*!< PWR CR7: WUP19 (Bitfield-Mask: 0x01) */
3717 #define PWR_CR7_WUP19                                                      PWR_CR7_WUP19_Msk
3718 #define PWR_CR7_WUP18_Pos                                                  (6UL)    /*!<PWR CR7: WUP18 (Bit 6) */
3719 #define PWR_CR7_WUP18_Msk                                                  (0x40UL)   /*!< PWR CR7: WUP18 (Bitfield-Mask: 0x01) */
3720 #define PWR_CR7_WUP18                                                      PWR_CR7_WUP18_Msk
3721 #define PWR_CR7_WUP17_Pos                                                  (5UL)    /*!<PWR CR7: WUP17 (Bit 5) */
3722 #define PWR_CR7_WUP17_Msk                                                  (0x20UL)   /*!< PWR CR7: WUP17 (Bitfield-Mask: 0x01) */
3723 #define PWR_CR7_WUP17                                                      PWR_CR7_WUP17_Msk
3724 #define PWR_CR7_WUP16_Pos                                                  (4UL)    /*!<PWR CR7: WUP16 (Bit 4) */
3725 #define PWR_CR7_WUP16_Msk                                                  (0x10UL)   /*!< PWR CR7: WUP16 (Bitfield-Mask: 0x01) */
3726 #define PWR_CR7_WUP16                                                      PWR_CR7_WUP16_Msk
3727 #define PWR_CR7_WUP15_Pos                                                  (3UL)    /*!<PWR CR7: WUP15 (Bit 3) */
3728 #define PWR_CR7_WUP15_Msk                                                  (0x8UL)    /*!< PWR CR7: WUP15 (Bitfield-Mask: 0x01) */
3729 #define PWR_CR7_WUP15                                                      PWR_CR7_WUP15_Msk
3730 #define PWR_CR7_WUP14_Pos                                                  (2UL)    /*!<PWR CR7: WUP14 (Bit 2) */
3731 #define PWR_CR7_WUP14_Msk                                                  (0x4UL)    /*!< PWR CR7: WUP14 (Bitfield-Mask: 0x01) */
3732 #define PWR_CR7_WUP14                                                      PWR_CR7_WUP14_Msk
3733 #define PWR_CR7_WUP13_Pos                                                  (1UL)    /*!<PWR CR7: WUP13 (Bit 1) */
3734 #define PWR_CR7_WUP13_Msk                                                  (0x2UL)    /*!< PWR CR7: WUP13 (Bitfield-Mask: 0x01) */
3735 #define PWR_CR7_WUP13                                                      PWR_CR7_WUP13_Msk
3736 #define PWR_CR7_WUP12_Pos                                                  (0UL)    /*!<PWR CR7: WUP12 (Bit 0) */
3737 #define PWR_CR7_WUP12_Msk                                                  (0x1UL)    /*!< PWR CR7: WUP12 (Bitfield-Mask: 0x01) */
3738 #define PWR_CR7_WUP12                                                      PWR_CR7_WUP12_Msk
3739 
3740 /* =====================================================    SR3    ===================================================== */
3741 #define PWR_SR3_WUF27_Pos                                                  (15UL)   /*!<PWR SR3: WUF27 (Bit 15) */
3742 #define PWR_SR3_WUF27_Msk                                                  (0x8000UL)   /*!< PWR SR3: WUF27 (Bitfield-Mask: 0x01) */
3743 #define PWR_SR3_WUF27                                                      PWR_SR3_WUF27_Msk
3744 #define PWR_SR3_WUF26_Pos                                                  (14UL)   /*!<PWR SR3: WUF26 (Bit 14) */
3745 #define PWR_SR3_WUF26_Msk                                                  (0x4000UL)   /*!< PWR SR3: WUF26 (Bitfield-Mask: 0x01) */
3746 #define PWR_SR3_WUF26                                                      PWR_SR3_WUF26_Msk
3747 #define PWR_SR3_WUF25_Pos                                                  (13UL)   /*!<PWR SR3: WUF25 (Bit 13) */
3748 #define PWR_SR3_WUF25_Msk                                                  (0x2000UL)   /*!< PWR SR3: WUF25 (Bitfield-Mask: 0x01) */
3749 #define PWR_SR3_WUF25                                                      PWR_SR3_WUF25_Msk
3750 #define PWR_SR3_WUF24_Pos                                                  (12UL)   /*!<PWR SR3: WUF24 (Bit 12) */
3751 #define PWR_SR3_WUF24_Msk                                                  (0x1000UL)   /*!< PWR SR3: WUF24 (Bitfield-Mask: 0x01) */
3752 #define PWR_SR3_WUF24                                                      PWR_SR3_WUF24_Msk
3753 #define PWR_SR3_WUF23_Pos                                                  (11UL)   /*!<PWR SR3: WUF23 (Bit 11) */
3754 #define PWR_SR3_WUF23_Msk                                                  (0x800UL)    /*!< PWR SR3: WUF23 (Bitfield-Mask: 0x01) */
3755 #define PWR_SR3_WUF23                                                      PWR_SR3_WUF23_Msk
3756 #define PWR_SR3_WUF22_Pos                                                  (10UL)   /*!<PWR SR3: WUF22 (Bit 10) */
3757 #define PWR_SR3_WUF22_Msk                                                  (0x400UL)    /*!< PWR SR3: WUF22 (Bitfield-Mask: 0x01) */
3758 #define PWR_SR3_WUF22                                                      PWR_SR3_WUF22_Msk
3759 #define PWR_SR3_WUF21_Pos                                                  (9UL)    /*!<PWR SR3: WUF21 (Bit 9) */
3760 #define PWR_SR3_WUF21_Msk                                                  (0x200UL)    /*!< PWR SR3: WUF21 (Bitfield-Mask: 0x01) */
3761 #define PWR_SR3_WUF21                                                      PWR_SR3_WUF21_Msk
3762 #define PWR_SR3_WUF20_Pos                                                  (8UL)    /*!<PWR SR3: WUF20 (Bit 8) */
3763 #define PWR_SR3_WUF20_Msk                                                  (0x100UL)    /*!< PWR SR3: WUF20 (Bitfield-Mask: 0x01) */
3764 #define PWR_SR3_WUF20                                                      PWR_SR3_WUF20_Msk
3765 #define PWR_SR3_WUF19_Pos                                                  (7UL)    /*!<PWR SR3: WUF19 (Bit 7) */
3766 #define PWR_SR3_WUF19_Msk                                                  (0x80UL)   /*!< PWR SR3: WUF19 (Bitfield-Mask: 0x01) */
3767 #define PWR_SR3_WUF19                                                      PWR_SR3_WUF19_Msk
3768 #define PWR_SR3_WUF18_Pos                                                  (6UL)    /*!<PWR SR3: WUF18 (Bit 6) */
3769 #define PWR_SR3_WUF18_Msk                                                  (0x40UL)   /*!< PWR SR3: WUF18 (Bitfield-Mask: 0x01) */
3770 #define PWR_SR3_WUF18                                                      PWR_SR3_WUF18_Msk
3771 #define PWR_SR3_WUF17_Pos                                                  (5UL)    /*!<PWR SR3: WUF17 (Bit 5) */
3772 #define PWR_SR3_WUF17_Msk                                                  (0x20UL)   /*!< PWR SR3: WUF17 (Bitfield-Mask: 0x01) */
3773 #define PWR_SR3_WUF17                                                      PWR_SR3_WUF17_Msk
3774 #define PWR_SR3_WUF16_Pos                                                  (4UL)    /*!<PWR SR3: WUF16 (Bit 4) */
3775 #define PWR_SR3_WUF16_Msk                                                  (0x10UL)   /*!< PWR SR3: WUF16 (Bitfield-Mask: 0x01) */
3776 #define PWR_SR3_WUF16                                                      PWR_SR3_WUF16_Msk
3777 #define PWR_SR3_WUF15_Pos                                                  (3UL)    /*!<PWR SR3: WUF15 (Bit 3) */
3778 #define PWR_SR3_WUF15_Msk                                                  (0x8UL)    /*!< PWR SR3: WUF15 (Bitfield-Mask: 0x01) */
3779 #define PWR_SR3_WUF15                                                      PWR_SR3_WUF15_Msk
3780 #define PWR_SR3_WUF14_Pos                                                  (2UL)    /*!<PWR SR3: WUF14 (Bit 2) */
3781 #define PWR_SR3_WUF14_Msk                                                  (0x4UL)    /*!< PWR SR3: WUF14 (Bitfield-Mask: 0x01) */
3782 #define PWR_SR3_WUF14                                                      PWR_SR3_WUF14_Msk
3783 #define PWR_SR3_WUF13_Pos                                                  (1UL)    /*!<PWR SR3: WUF13 (Bit 1) */
3784 #define PWR_SR3_WUF13_Msk                                                  (0x2UL)    /*!< PWR SR3: WUF13 (Bitfield-Mask: 0x01) */
3785 #define PWR_SR3_WUF13                                                      PWR_SR3_WUF13_Msk
3786 #define PWR_SR3_WUF12_Pos                                                  (0UL)    /*!<PWR SR3: WUF12 (Bit 0) */
3787 #define PWR_SR3_WUF12_Msk                                                  (0x1UL)    /*!< PWR SR3: WUF12 (Bitfield-Mask: 0x01) */
3788 #define PWR_SR3_WUF12                                                      PWR_SR3_WUF12_Msk
3789 
3790 /* =====================================================    IOxCFG    ===================================================== */
3791 #define PWR_IOxCFG_IOCFG7_Pos                                              (14UL)   /*!<PWR IOxCFG: IOCFG7 (Bit 14) */
3792 #define PWR_IOxCFG_IOCFG7_Msk                                              (0xc000UL)   /*!< PWR IOxCFG: IOCFG7 (Bitfield-Mask: 0x03) */
3793 #define PWR_IOxCFG_IOCFG7                                                  PWR_IOxCFG_IOCFG7_Msk
3794 #define PWR_IOxCFG_IOCFG7_0                                                (0x1U << PWR_IOxCFG_IOCFG7_Pos)
3795 #define PWR_IOxCFG_IOCFG7_1                                                (0x2U << PWR_IOxCFG_IOCFG7_Pos)
3796 #define PWR_IOxCFG_IOCFG6_Pos                                              (12UL)   /*!<PWR IOxCFG: IOCFG6 (Bit 12) */
3797 #define PWR_IOxCFG_IOCFG6_Msk                                              (0x3000UL)   /*!< PWR IOxCFG: IOCFG6 (Bitfield-Mask: 0x03) */
3798 #define PWR_IOxCFG_IOCFG6                                                  PWR_IOxCFG_IOCFG6_Msk
3799 #define PWR_IOxCFG_IOCFG6_0                                                (0x1U << PWR_IOxCFG_IOCFG6_Pos)
3800 #define PWR_IOxCFG_IOCFG6_1                                                (0x2U << PWR_IOxCFG_IOCFG6_Pos)
3801 #define PWR_IOxCFG_IOCFG5_Pos                                              (10UL)   /*!<PWR IOxCFG: IOCFG5 (Bit 10) */
3802 #define PWR_IOxCFG_IOCFG5_Msk                                              (0xc00UL)    /*!< PWR IOxCFG: IOCFG5 (Bitfield-Mask: 0x03) */
3803 #define PWR_IOxCFG_IOCFG5                                                  PWR_IOxCFG_IOCFG5_Msk
3804 #define PWR_IOxCFG_IOCFG5_0                                                (0x1U << PWR_IOxCFG_IOCFG5_Pos)
3805 #define PWR_IOxCFG_IOCFG5_1                                                (0x2U << PWR_IOxCFG_IOCFG5_Pos)
3806 #define PWR_IOxCFG_IOCFG4_Pos                                              (8UL)    /*!<PWR IOxCFG: IOCFG4 (Bit 8) */
3807 #define PWR_IOxCFG_IOCFG4_Msk                                              (0x300UL)    /*!< PWR IOxCFG: IOCFG4 (Bitfield-Mask: 0x03) */
3808 #define PWR_IOxCFG_IOCFG4                                                  PWR_IOxCFG_IOCFG4_Msk
3809 #define PWR_IOxCFG_IOCFG4_0                                                (0x1U << PWR_IOxCFG_IOCFG4_Pos)
3810 #define PWR_IOxCFG_IOCFG4_1                                                (0x2U << PWR_IOxCFG_IOCFG4_Pos)
3811 #define PWR_IOxCFG_IOCFG3_Pos                                              (6UL)    /*!<PWR IOxCFG: IOCFG3 (Bit 6) */
3812 #define PWR_IOxCFG_IOCFG3_Msk                                              (0xc0UL)   /*!< PWR IOxCFG: IOCFG3 (Bitfield-Mask: 0x03) */
3813 #define PWR_IOxCFG_IOCFG3                                                  PWR_IOxCFG_IOCFG3_Msk
3814 #define PWR_IOxCFG_IOCFG3_0                                                (0x1U << PWR_IOxCFG_IOCFG3_Pos)
3815 #define PWR_IOxCFG_IOCFG3_1                                                (0x2U << PWR_IOxCFG_IOCFG3_Pos)
3816 #define PWR_IOxCFG_IOCFG2_Pos                                              (4UL)    /*!<PWR IOxCFG: IOCFG2 (Bit 4) */
3817 #define PWR_IOxCFG_IOCFG2_Msk                                              (0x30UL)   /*!< PWR IOxCFG: IOCFG2 (Bitfield-Mask: 0x03) */
3818 #define PWR_IOxCFG_IOCFG2                                                  PWR_IOxCFG_IOCFG2_Msk
3819 #define PWR_IOxCFG_IOCFG2_0                                                (0x1U << PWR_IOxCFG_IOCFG2_Pos)
3820 #define PWR_IOxCFG_IOCFG2_1                                                (0x2U << PWR_IOxCFG_IOCFG2_Pos)
3821 #define PWR_IOxCFG_IOCFG1_Pos                                              (2UL)    /*!<PWR IOxCFG: IOCFG1 (Bit 2) */
3822 #define PWR_IOxCFG_IOCFG1_Msk                                              (0xcUL)    /*!< PWR IOxCFG: IOCFG1 (Bitfield-Mask: 0x03) */
3823 #define PWR_IOxCFG_IOCFG1                                                  PWR_IOxCFG_IOCFG1_Msk
3824 #define PWR_IOxCFG_IOCFG1_0                                                (0x1U << PWR_IOxCFG_IOCFG1_Pos)
3825 #define PWR_IOxCFG_IOCFG1_1                                                (0x2U << PWR_IOxCFG_IOCFG1_Pos)
3826 #define PWR_IOxCFG_IOCFG0_Pos                                              (0UL)    /*!<PWR IOxCFG: IOCFG0 (Bit 0) */
3827 #define PWR_IOxCFG_IOCFG0_Msk                                              (0x3UL)    /*!< PWR IOxCFG: IOCFG0 (Bitfield-Mask: 0x03) */
3828 #define PWR_IOxCFG_IOCFG0                                                  PWR_IOxCFG_IOCFG0_Msk
3829 #define PWR_IOxCFG_IOCFG0_0                                                (0x1U << PWR_IOxCFG_IOCFG0_Pos)
3830 #define PWR_IOxCFG_IOCFG0_1                                                (0x2U << PWR_IOxCFG_IOCFG0_Pos)
3831 
3832 /* =====================================================    DBGR    ===================================================== */
3833 #define PWR_DBGR_DEEPSTOP2_Pos                                             (0UL)    /*!<PWR DBGR: DEEPSTOP2 (Bit 0) */
3834 #define PWR_DBGR_DEEPSTOP2_Msk                                             (0x1UL)    /*!< PWR DBGR: DEEPSTOP2 (Bitfield-Mask: 0x01) */
3835 #define PWR_DBGR_DEEPSTOP2                                                 PWR_DBGR_DEEPSTOP2_Msk
3836 
3837 /* =====================================================    EXTSRR    ===================================================== */
3838 #define PWR_EXTSRR_RFPHASEF_Pos                                            (10UL)   /*!<PWR EXTSRR: RFPHASEF (Bit 10) */
3839 #define PWR_EXTSRR_RFPHASEF_Msk                                            (0x400UL)    /*!< PWR EXTSRR: RFPHASEF (Bitfield-Mask: 0x01) */
3840 #define PWR_EXTSRR_RFPHASEF                                                PWR_EXTSRR_RFPHASEF_Msk
3841 #define PWR_EXTSRR_DEEPSTOPF_Pos                                           (9UL)    /*!<PWR EXTSRR: DEEPSTOPF (Bit 9) */
3842 #define PWR_EXTSRR_DEEPSTOPF_Msk                                           (0x200UL)    /*!< PWR EXTSRR: DEEPSTOPF (Bitfield-Mask: 0x01) */
3843 #define PWR_EXTSRR_DEEPSTOPF                                               PWR_EXTSRR_DEEPSTOPF_Msk
3844 
3845 /* =====================================================    DBGSMPS    ===================================================== */
3846 #define PWR_DBGSMPS_TEST_OL_Pos                                            (11UL)   /*!<PWR DBGSMPS: TEST_OL (Bit 11) */
3847 #define PWR_DBGSMPS_TEST_OL_Msk                                            (0x800UL)    /*!< PWR DBGSMPS: TEST_OL (Bitfield-Mask: 0x01) */
3848 #define PWR_DBGSMPS_TEST_OL                                                PWR_DBGSMPS_TEST_OL_Msk
3849 #define PWR_DBGSMPS_DIS_BIG_MOS_Pos                                        (10UL)   /*!<PWR DBGSMPS: DIS_BIG_MOS (Bit 10) */
3850 #define PWR_DBGSMPS_DIS_BIG_MOS_Msk                                        (0x400UL)    /*!< PWR DBGSMPS: DIS_BIG_MOS (Bitfield-Mask: 0x01) */
3851 #define PWR_DBGSMPS_DIS_BIG_MOS                                            PWR_DBGSMPS_DIS_BIG_MOS_Msk
3852 #define PWR_DBGSMPS_CTLRES_RAMP_Pos                                        (9UL)    /*!<PWR DBGSMPS: CTLRES_RAMP (Bit 9) */
3853 #define PWR_DBGSMPS_CTLRES_RAMP_Msk                                        (0x200UL)    /*!< PWR DBGSMPS: CTLRES_RAMP (Bitfield-Mask: 0x01) */
3854 #define PWR_DBGSMPS_CTLRES_RAMP                                            PWR_DBGSMPS_CTLRES_RAMP_Msk
3855 #define PWR_DBGSMPS_TESTILIM_Pos                                           (8UL)    /*!<PWR DBGSMPS: TESTILIM (Bit 8) */
3856 #define PWR_DBGSMPS_TESTILIM_Msk                                           (0x100UL)    /*!< PWR DBGSMPS: TESTILIM (Bitfield-Mask: 0x01) */
3857 #define PWR_DBGSMPS_TESTILIM                                               PWR_DBGSMPS_TESTILIM_Msk
3858 #define PWR_DBGSMPS_NO_STUP_Pos                                            (7UL)    /*!<PWR DBGSMPS: NO_STUP (Bit 7) */
3859 #define PWR_DBGSMPS_NO_STUP_Msk                                            (0x80UL)   /*!< PWR DBGSMPS: NO_STUP (Bitfield-Mask: 0x01) */
3860 #define PWR_DBGSMPS_NO_STUP                                                PWR_DBGSMPS_NO_STUP_Msk
3861 #define PWR_DBGSMPS_HOT_STUP_Pos                                           (6UL)    /*!<PWR DBGSMPS: HOT_STUP (Bit 6) */
3862 #define PWR_DBGSMPS_HOT_STUP_Msk                                           (0x40UL)   /*!< PWR DBGSMPS: HOT_STUP (Bitfield-Mask: 0x01) */
3863 #define PWR_DBGSMPS_HOT_STUP                                               PWR_DBGSMPS_HOT_STUP_Msk
3864 #define PWR_DBGSMPS_TESTKEL_Pos                                            (4UL)    /*!<PWR DBGSMPS: TESTKEL (Bit 4) */
3865 #define PWR_DBGSMPS_TESTKEL_Msk                                            (0x30UL)   /*!< PWR DBGSMPS: TESTKEL (Bitfield-Mask: 0x03) */
3866 #define PWR_DBGSMPS_TESTKEL                                                PWR_DBGSMPS_TESTKEL_Msk
3867 #define PWR_DBGSMPS_TESTKEL_0                                              (0x1U << PWR_DBGSMPS_TESTKEL_Pos)
3868 #define PWR_DBGSMPS_TESTKEL_1                                              (0x2U << PWR_DBGSMPS_TESTKEL_Pos)
3869 #define PWR_DBGSMPS_TESTDIG_Pos                                            (0UL)    /*!<PWR DBGSMPS: TESTDIG (Bit 0) */
3870 #define PWR_DBGSMPS_TESTDIG_Msk                                            (0xfUL)    /*!< PWR DBGSMPS: TESTDIG (Bitfield-Mask: 0x0f) */
3871 #define PWR_DBGSMPS_TESTDIG                                                PWR_DBGSMPS_TESTDIG_Msk
3872 #define PWR_DBGSMPS_TESTDIG_0                                              (0x1U << PWR_DBGSMPS_TESTDIG_Pos)
3873 #define PWR_DBGSMPS_TESTDIG_1                                              (0x2U << PWR_DBGSMPS_TESTDIG_Pos)
3874 #define PWR_DBGSMPS_TESTDIG_2                                              (0x4U << PWR_DBGSMPS_TESTDIG_Pos)
3875 #define PWR_DBGSMPS_TESTDIG_3                                              (0x8U << PWR_DBGSMPS_TESTDIG_Pos)
3876 
3877 /* =====================================================    TRIMR    ===================================================== */
3878 #define PWR_TRIMR_RAM_SIZE_Pos                                             (12UL)   /*!<PWR TRIMR: RAM_SIZE (Bit 12) */
3879 #define PWR_TRIMR_RAM_SIZE_Msk                                             (0x3000UL)   /*!< PWR TRIMR: RAM_SIZE (Bitfield-Mask: 0x03) */
3880 #define PWR_TRIMR_RAM_SIZE                                                 PWR_TRIMR_RAM_SIZE_Msk
3881 #define PWR_TRIMR_RAM_SIZE_0                                               (0x1U << PWR_TRIMR_RAM_SIZE_Pos)
3882 #define PWR_TRIMR_RAM_SIZE_1                                               (0x2U << PWR_TRIMR_RAM_SIZE_Pos)
3883 #define PWR_TRIMR_SMPS_TRIM_Pos                                            (8UL)    /*!<PWR TRIMR: SMPS_TRIM (Bit 8) */
3884 #define PWR_TRIMR_SMPS_TRIM_Msk                                            (0x700UL)    /*!< PWR TRIMR: SMPS_TRIM (Bitfield-Mask: 0x07) */
3885 #define PWR_TRIMR_SMPS_TRIM                                                PWR_TRIMR_SMPS_TRIM_Msk
3886 #define PWR_TRIMR_SMPS_TRIM_0                                              (0x1U << PWR_TRIMR_SMPS_TRIM_Pos)
3887 #define PWR_TRIMR_SMPS_TRIM_1                                              (0x2U << PWR_TRIMR_SMPS_TRIM_Pos)
3888 #define PWR_TRIMR_SMPS_TRIM_2                                              (0x4U << PWR_TRIMR_SMPS_TRIM_Pos)
3889 #define PWR_TRIMR_TRIM_MR_Pos                                              (4UL)    /*!<PWR TRIMR: TRIM_MR (Bit 4) */
3890 #define PWR_TRIMR_TRIM_MR_Msk                                              (0xf0UL)   /*!< PWR TRIMR: TRIM_MR (Bitfield-Mask: 0x0f) */
3891 #define PWR_TRIMR_TRIM_MR                                                  PWR_TRIMR_TRIM_MR_Msk
3892 #define PWR_TRIMR_TRIM_MR_0                                                (0x1U << PWR_TRIMR_TRIM_MR_Pos)
3893 #define PWR_TRIMR_TRIM_MR_1                                                (0x2U << PWR_TRIMR_TRIM_MR_Pos)
3894 #define PWR_TRIMR_TRIM_MR_2                                                (0x4U << PWR_TRIMR_TRIM_MR_Pos)
3895 #define PWR_TRIMR_TRIM_MR_3                                                (0x8U << PWR_TRIMR_TRIM_MR_Pos)
3896 #define PWR_TRIMR_TRIM_LSI_LPMU_Pos                                        (0UL)    /*!<PWR TRIMR: TRIM_LSI_LPMU (Bit 0) */
3897 #define PWR_TRIMR_TRIM_LSI_LPMU_Msk                                        (0xfUL)    /*!< PWR TRIMR: TRIM_LSI_LPMU (Bitfield-Mask: 0x0f) */
3898 #define PWR_TRIMR_TRIM_LSI_LPMU                                            PWR_TRIMR_TRIM_LSI_LPMU_Msk
3899 #define PWR_TRIMR_TRIM_LSI_LPMU_0                                          (0x1U << PWR_TRIMR_TRIM_LSI_LPMU_Pos)
3900 #define PWR_TRIMR_TRIM_LSI_LPMU_1                                          (0x2U << PWR_TRIMR_TRIM_LSI_LPMU_Pos)
3901 #define PWR_TRIMR_TRIM_LSI_LPMU_2                                          (0x4U << PWR_TRIMR_TRIM_LSI_LPMU_Pos)
3902 #define PWR_TRIMR_TRIM_LSI_LPMU_3                                          (0x8U << PWR_TRIMR_TRIM_LSI_LPMU_Pos)
3903 
3904 /* =====================================================    ENGTRIM    ===================================================== */
3905 #define PWR_ENGTRIM_SMPS_TRIM_Pos                                          (11UL)   /*!<PWR ENGTRIM: SMPS_TRIM (Bit 11) */
3906 #define PWR_ENGTRIM_SMPS_TRIM_Msk                                          (0x3800UL)   /*!< PWR ENGTRIM: SMPS_TRIM (Bitfield-Mask: 0x07) */
3907 #define PWR_ENGTRIM_SMPS_TRIM                                              PWR_ENGTRIM_SMPS_TRIM_Msk
3908 #define PWR_ENGTRIM_SMPS_TRIM_0                                            (0x1U << PWR_ENGTRIM_SMPS_TRIM_Pos)
3909 #define PWR_ENGTRIM_SMPS_TRIM_1                                            (0x2U << PWR_ENGTRIM_SMPS_TRIM_Pos)
3910 #define PWR_ENGTRIM_SMPS_TRIM_2                                            (0x4U << PWR_ENGTRIM_SMPS_TRIM_Pos)
3911 #define PWR_ENGTRIM_SMPSTRIMEN_Pos                                         (10UL)   /*!<PWR ENGTRIM: SMPSTRIMEN (Bit 10) */
3912 #define PWR_ENGTRIM_SMPSTRIMEN_Msk                                         (0x400UL)    /*!< PWR ENGTRIM: SMPSTRIMEN (Bitfield-Mask: 0x01) */
3913 #define PWR_ENGTRIM_SMPSTRIMEN                                             PWR_ENGTRIM_SMPSTRIMEN_Msk
3914 #define PWR_ENGTRIM_TRIM_MR_Pos                                            (6UL)    /*!<PWR ENGTRIM: TRIM_MR (Bit 6) */
3915 #define PWR_ENGTRIM_TRIM_MR_Msk                                            (0x3c0UL)    /*!< PWR ENGTRIM: TRIM_MR (Bitfield-Mask: 0x0f) */
3916 #define PWR_ENGTRIM_TRIM_MR                                                PWR_ENGTRIM_TRIM_MR_Msk
3917 #define PWR_ENGTRIM_TRIM_MR_0                                              (0x1U << PWR_ENGTRIM_TRIM_MR_Pos)
3918 #define PWR_ENGTRIM_TRIM_MR_1                                              (0x2U << PWR_ENGTRIM_TRIM_MR_Pos)
3919 #define PWR_ENGTRIM_TRIM_MR_2                                              (0x4U << PWR_ENGTRIM_TRIM_MR_Pos)
3920 #define PWR_ENGTRIM_TRIM_MR_3                                              (0x8U << PWR_ENGTRIM_TRIM_MR_Pos)
3921 #define PWR_ENGTRIM_TRIMMREN_Pos                                           (5UL)    /*!<PWR ENGTRIM: TRIMMREN (Bit 5) */
3922 #define PWR_ENGTRIM_TRIMMREN_Msk                                           (0x20UL)   /*!< PWR ENGTRIM: TRIMMREN (Bitfield-Mask: 0x01) */
3923 #define PWR_ENGTRIM_TRIMMREN                                               PWR_ENGTRIM_TRIMMREN_Msk
3924 #define PWR_ENGTRIM_TRIM_LSI_LPMU_Pos                                      (1UL)    /*!<PWR ENGTRIM: TRIM_LSI_LPMU (Bit 1) */
3925 #define PWR_ENGTRIM_TRIM_LSI_LPMU_Msk                                      (0x1eUL)   /*!< PWR ENGTRIM: TRIM_LSI_LPMU (Bitfield-Mask: 0x0f) */
3926 #define PWR_ENGTRIM_TRIM_LSI_LPMU                                          PWR_ENGTRIM_TRIM_LSI_LPMU_Msk
3927 #define PWR_ENGTRIM_TRIM_LSI_LPMU_0                                        (0x1U << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos)
3928 #define PWR_ENGTRIM_TRIM_LSI_LPMU_1                                        (0x2U << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos)
3929 #define PWR_ENGTRIM_TRIM_LSI_LPMU_2                                        (0x4U << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos)
3930 #define PWR_ENGTRIM_TRIM_LSI_LPMU_3                                        (0x8U << PWR_ENGTRIM_TRIM_LSI_LPMU_Pos)
3931 #define PWR_ENGTRIM_TRIMLSILPMUEN_Pos                                      (0UL)    /*!<PWR ENGTRIM: TRIMLSILPMUEN (Bit 0) */
3932 #define PWR_ENGTRIM_TRIMLSILPMUEN_Msk                                      (0x1UL)    /*!< PWR ENGTRIM: TRIMLSILPMUEN (Bitfield-Mask: 0x01) */
3933 #define PWR_ENGTRIM_TRIMLSILPMUEN                                          PWR_ENGTRIM_TRIMLSILPMUEN_Msk
3934 
3935 /* =====================================================    DBG1    ===================================================== */
3936 #define PWR_DBG1_FLASH_FSM_STATE_Pos                                       (8UL)    /*!<PWR DBG1: FLASH_FSM_STATE (Bit 8) */
3937 #define PWR_DBG1_FLASH_FSM_STATE_Msk                                       (0x700UL)    /*!< PWR DBG1: FLASH_FSM_STATE (Bitfield-Mask: 0x07) */
3938 #define PWR_DBG1_FLASH_FSM_STATE                                           PWR_DBG1_FLASH_FSM_STATE_Msk
3939 #define PWR_DBG1_FLASH_FSM_STATE_0                                         (0x1U << PWR_DBG1_FLASH_FSM_STATE_Pos)
3940 #define PWR_DBG1_FLASH_FSM_STATE_1                                         (0x2U << PWR_DBG1_FLASH_FSM_STATE_Pos)
3941 #define PWR_DBG1_FLASH_FSM_STATE_2                                         (0x4U << PWR_DBG1_FLASH_FSM_STATE_Pos)
3942 #define PWR_DBG1_SMPS_FSM_STATE_Pos                                        (0UL)    /*!<PWR DBG1: SMPS_FSM_STATE (Bit 0) */
3943 #define PWR_DBG1_SMPS_FSM_STATE_Msk                                        (0x7UL)    /*!< PWR DBG1: SMPS_FSM_STATE (Bitfield-Mask: 0x07) */
3944 #define PWR_DBG1_SMPS_FSM_STATE                                            PWR_DBG1_SMPS_FSM_STATE_Msk
3945 #define PWR_DBG1_SMPS_FSM_STATE_0                                          (0x1U << PWR_DBG1_SMPS_FSM_STATE_Pos)
3946 #define PWR_DBG1_SMPS_FSM_STATE_1                                          (0x2U << PWR_DBG1_SMPS_FSM_STATE_Pos)
3947 #define PWR_DBG1_SMPS_FSM_STATE_2                                          (0x4U << PWR_DBG1_SMPS_FSM_STATE_Pos)
3948 
3949 /* =====================================================    DBG2    ===================================================== */
3950 #define PWR_DBG2_RAM_FSM_STATE_Pos                                         (8UL)    /*!<PWR DBG2: RAM_FSM_STATE (Bit 8) */
3951 #define PWR_DBG2_RAM_FSM_STATE_Msk                                         (0x300UL)    /*!< PWR DBG2: RAM_FSM_STATE (Bitfield-Mask: 0x03) */
3952 #define PWR_DBG2_RAM_FSM_STATE                                             PWR_DBG2_RAM_FSM_STATE_Msk
3953 #define PWR_DBG2_RAM_FSM_STATE_0                                           (0x1U << PWR_DBG2_RAM_FSM_STATE_Pos)
3954 #define PWR_DBG2_RAM_FSM_STATE_1                                           (0x2U << PWR_DBG2_RAM_FSM_STATE_Pos)
3955 #define PWR_DBG2_PMU_FSM_STATE_Pos                                         (0UL)    /*!<PWR DBG2: PMU_FSM_STATE (Bit 0) */
3956 #define PWR_DBG2_PMU_FSM_STATE_Msk                                         (0xfUL)    /*!< PWR DBG2: PMU_FSM_STATE (Bitfield-Mask: 0x0f) */
3957 #define PWR_DBG2_PMU_FSM_STATE                                             PWR_DBG2_PMU_FSM_STATE_Msk
3958 #define PWR_DBG2_PMU_FSM_STATE_0                                           (0x1U << PWR_DBG2_PMU_FSM_STATE_Pos)
3959 #define PWR_DBG2_PMU_FSM_STATE_1                                           (0x2U << PWR_DBG2_PMU_FSM_STATE_Pos)
3960 #define PWR_DBG2_PMU_FSM_STATE_2                                           (0x4U << PWR_DBG2_PMU_FSM_STATE_Pos)
3961 #define PWR_DBG2_PMU_FSM_STATE_3                                           (0x8U << PWR_DBG2_PMU_FSM_STATE_Pos)
3962 
3963 
3964 /* =========================================================================================================================== */
3965 /*=====================                                      SYSCFG                                      ===================== */
3966 /* =========================================================================================================================== */
3967 
3968 /* =====================================================    DIE_ID    ===================================================== */
3969 #define SYSCFG_DIE_ID_PRODUCT_Pos                                          (8UL)    /*!<SYSCFG DIE_ID: PRODUCT (Bit 8) */
3970 #define SYSCFG_DIE_ID_PRODUCT_Msk                                          (0xf00UL)    /*!< SYSCFG DIE_ID: PRODUCT (Bitfield-Mask: 0x0f) */
3971 #define SYSCFG_DIE_ID_PRODUCT                                              SYSCFG_DIE_ID_PRODUCT_Msk
3972 #define SYSCFG_DIE_ID_PRODUCT_0                                            (0x1U << SYSCFG_DIE_ID_PRODUCT_Pos)
3973 #define SYSCFG_DIE_ID_PRODUCT_1                                            (0x2U << SYSCFG_DIE_ID_PRODUCT_Pos)
3974 #define SYSCFG_DIE_ID_PRODUCT_2                                            (0x4U << SYSCFG_DIE_ID_PRODUCT_Pos)
3975 #define SYSCFG_DIE_ID_PRODUCT_3                                            (0x8U << SYSCFG_DIE_ID_PRODUCT_Pos)
3976 #define SYSCFG_DIE_ID_VERSION_Pos                                          (4UL)    /*!<SYSCFG DIE_ID: VERSION (Bit 4) */
3977 #define SYSCFG_DIE_ID_VERSION_Msk                                          (0xf0UL)   /*!< SYSCFG DIE_ID: VERSION (Bitfield-Mask: 0x0f) */
3978 #define SYSCFG_DIE_ID_VERSION                                              SYSCFG_DIE_ID_VERSION_Msk
3979 #define SYSCFG_DIE_ID_VERSION_0                                            (0x1U << SYSCFG_DIE_ID_VERSION_Pos)
3980 #define SYSCFG_DIE_ID_VERSION_1                                            (0x2U << SYSCFG_DIE_ID_VERSION_Pos)
3981 #define SYSCFG_DIE_ID_VERSION_2                                            (0x4U << SYSCFG_DIE_ID_VERSION_Pos)
3982 #define SYSCFG_DIE_ID_VERSION_3                                            (0x8U << SYSCFG_DIE_ID_VERSION_Pos)
3983 #define SYSCFG_DIE_ID_REVISION_Pos                                         (0UL)    /*!<SYSCFG DIE_ID: REVISION (Bit 0) */
3984 #define SYSCFG_DIE_ID_REVISION_Msk                                         (0xfUL)    /*!< SYSCFG DIE_ID: REVISION (Bitfield-Mask: 0x0f) */
3985 #define SYSCFG_DIE_ID_REVISION                                             SYSCFG_DIE_ID_REVISION_Msk
3986 #define SYSCFG_DIE_ID_REVISION_0                                           (0x1U << SYSCFG_DIE_ID_REVISION_Pos)
3987 #define SYSCFG_DIE_ID_REVISION_1                                           (0x2U << SYSCFG_DIE_ID_REVISION_Pos)
3988 #define SYSCFG_DIE_ID_REVISION_2                                           (0x4U << SYSCFG_DIE_ID_REVISION_Pos)
3989 #define SYSCFG_DIE_ID_REVISION_3                                           (0x8U << SYSCFG_DIE_ID_REVISION_Pos)
3990 
3991 /* =====================================================    JTAG_ID    ===================================================== */
3992 #define SYSCFG_JTAG_ID_VERSION_NUMBER_Pos                                  (28UL)   /*!<SYSCFG JTAG_ID: VERSION_NUMBER (Bit 28) */
3993 #define SYSCFG_JTAG_ID_VERSION_NUMBER_Msk                                  (0xf0000000UL)   /*!< SYSCFG JTAG_ID: VERSION_NUMBER (Bitfield-Mask: 0x0f) */
3994 #define SYSCFG_JTAG_ID_VERSION_NUMBER                                      SYSCFG_JTAG_ID_VERSION_NUMBER_Msk
3995 #define SYSCFG_JTAG_ID_VERSION_NUMBER_0                                    (0x1U << SYSCFG_JTAG_ID_VERSION_NUMBER_Pos)
3996 #define SYSCFG_JTAG_ID_VERSION_NUMBER_1                                    (0x2U << SYSCFG_JTAG_ID_VERSION_NUMBER_Pos)
3997 #define SYSCFG_JTAG_ID_VERSION_NUMBER_2                                    (0x4U << SYSCFG_JTAG_ID_VERSION_NUMBER_Pos)
3998 #define SYSCFG_JTAG_ID_VERSION_NUMBER_3                                    (0x8U << SYSCFG_JTAG_ID_VERSION_NUMBER_Pos)
3999 #define SYSCFG_JTAG_ID_PART_NUMBER_Pos                                     (12UL)   /*!<SYSCFG JTAG_ID: PART_NUMBER (Bit 12) */
4000 #define SYSCFG_JTAG_ID_PART_NUMBER_Msk                                     (0xffff000UL)    /*!< SYSCFG JTAG_ID: PART_NUMBER (Bitfield-Mask: 0xffff) */
4001 #define SYSCFG_JTAG_ID_PART_NUMBER                                         SYSCFG_JTAG_ID_PART_NUMBER_Msk
4002 #define SYSCFG_JTAG_ID_PART_NUMBER_0                                       (0x1U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4003 #define SYSCFG_JTAG_ID_PART_NUMBER_1                                       (0x2U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4004 #define SYSCFG_JTAG_ID_PART_NUMBER_2                                       (0x4U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4005 #define SYSCFG_JTAG_ID_PART_NUMBER_3                                       (0x8U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4006 #define SYSCFG_JTAG_ID_PART_NUMBER_4                                       (0x10U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4007 #define SYSCFG_JTAG_ID_PART_NUMBER_5                                       (0x20U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4008 #define SYSCFG_JTAG_ID_PART_NUMBER_6                                       (0x40U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4009 #define SYSCFG_JTAG_ID_PART_NUMBER_7                                       (0x80U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4010 #define SYSCFG_JTAG_ID_PART_NUMBER_8                                       (0x100U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4011 #define SYSCFG_JTAG_ID_PART_NUMBER_9                                       (0x200U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4012 #define SYSCFG_JTAG_ID_PART_NUMBER_10                                      (0x400U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4013 #define SYSCFG_JTAG_ID_PART_NUMBER_11                                      (0x800U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4014 #define SYSCFG_JTAG_ID_PART_NUMBER_12                                      (0x1000U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4015 #define SYSCFG_JTAG_ID_PART_NUMBER_13                                      (0x2000U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4016 #define SYSCFG_JTAG_ID_PART_NUMBER_14                                      (0x4000U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4017 #define SYSCFG_JTAG_ID_PART_NUMBER_15                                      (0x8000U << SYSCFG_JTAG_ID_PART_NUMBER_Pos)
4018 #define SYSCFG_JTAG_ID_MANUF_ID_Pos                                        (1UL)    /*!<SYSCFG JTAG_ID: MANUF_ID (Bit 1) */
4019 #define SYSCFG_JTAG_ID_MANUF_ID_Msk                                        (0xffeUL)    /*!< SYSCFG JTAG_ID: MANUF_ID (Bitfield-Mask: 0x7ff) */
4020 #define SYSCFG_JTAG_ID_MANUF_ID                                            SYSCFG_JTAG_ID_MANUF_ID_Msk
4021 #define SYSCFG_JTAG_ID_MANUF_ID_0                                          (0x1U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4022 #define SYSCFG_JTAG_ID_MANUF_ID_1                                          (0x2U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4023 #define SYSCFG_JTAG_ID_MANUF_ID_2                                          (0x4U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4024 #define SYSCFG_JTAG_ID_MANUF_ID_3                                          (0x8U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4025 #define SYSCFG_JTAG_ID_MANUF_ID_4                                          (0x10U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4026 #define SYSCFG_JTAG_ID_MANUF_ID_5                                          (0x20U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4027 #define SYSCFG_JTAG_ID_MANUF_ID_6                                          (0x40U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4028 #define SYSCFG_JTAG_ID_MANUF_ID_7                                          (0x80U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4029 #define SYSCFG_JTAG_ID_MANUF_ID_8                                          (0x100U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4030 #define SYSCFG_JTAG_ID_MANUF_ID_9                                          (0x200U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4031 #define SYSCFG_JTAG_ID_MANUF_ID_10                                         (0x400U << SYSCFG_JTAG_ID_MANUF_ID_Pos)
4032 
4033 /* =====================================================    I2C_FMP_CTRL    ===================================================== */
4034 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB7_FMP_Pos                               (3UL)    /*!<SYSCFG I2C_FMP_CTRL: I2C2_PB7_FMP (Bit 3) */
4035 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB7_FMP_Msk                               (0x8UL)    /*!< SYSCFG I2C_FMP_CTRL: I2C2_PB7_FMP (Bitfield-Mask: 0x01) */
4036 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB7_FMP                                   SYSCFG_I2C_FMP_CTRL_I2C2_PB7_FMP_Msk
4037 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB6_FMP_Pos                               (2UL)    /*!<SYSCFG I2C_FMP_CTRL: I2C2_PB6_FMP (Bit 2) */
4038 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB6_FMP_Msk                               (0x4UL)    /*!< SYSCFG I2C_FMP_CTRL: I2C2_PB6_FMP (Bitfield-Mask: 0x01) */
4039 #define SYSCFG_I2C_FMP_CTRL_I2C2_PB6_FMP                                   SYSCFG_I2C_FMP_CTRL_I2C2_PB6_FMP_Msk
4040 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP_Pos                               (1UL)    /*!<SYSCFG I2C_FMP_CTRL: I2C1_PA1_FMP (Bit 1) */
4041 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP_Msk                               (0x2UL)    /*!< SYSCFG I2C_FMP_CTRL: I2C1_PA1_FMP (Bitfield-Mask: 0x01) */
4042 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP                                   SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP_Msk
4043 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP_Pos                               (0UL)    /*!<SYSCFG I2C_FMP_CTRL: I2C1_PA0_FMP (Bit 0) */
4044 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP_Msk                               (0x1UL)    /*!< SYSCFG I2C_FMP_CTRL: I2C1_PA0_FMP (Bitfield-Mask: 0x01) */
4045 #define SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP                                   SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP_Msk
4046 
4047 /* =====================================================    IO_DTR    ===================================================== */
4048 #define SYSCFG_IO_DTR_PB15_DT_Pos                                          (31UL)   /*!<SYSCFG IO_DTR: PB15_DT (Bit 31) */
4049 #define SYSCFG_IO_DTR_PB15_DT_Msk                                          (0x80000000UL)   /*!< SYSCFG IO_DTR: PB15_DT (Bitfield-Mask: 0x01) */
4050 #define SYSCFG_IO_DTR_PB15_DT                                              SYSCFG_IO_DTR_PB15_DT_Msk
4051 #define SYSCFG_IO_DTR_PB14_DT_Pos                                          (30UL)   /*!<SYSCFG IO_DTR: PB14_DT (Bit 30) */
4052 #define SYSCFG_IO_DTR_PB14_DT_Msk                                          (0x40000000UL)   /*!< SYSCFG IO_DTR: PB14_DT (Bitfield-Mask: 0x01) */
4053 #define SYSCFG_IO_DTR_PB14_DT                                              SYSCFG_IO_DTR_PB14_DT_Msk
4054 #define SYSCFG_IO_DTR_PB13_DT_Pos                                          (29UL)   /*!<SYSCFG IO_DTR: PB13_DT (Bit 29) */
4055 #define SYSCFG_IO_DTR_PB13_DT_Msk                                          (0x20000000UL)   /*!< SYSCFG IO_DTR: PB13_DT (Bitfield-Mask: 0x01) */
4056 #define SYSCFG_IO_DTR_PB13_DT                                              SYSCFG_IO_DTR_PB13_DT_Msk
4057 #define SYSCFG_IO_DTR_PB12_DT_Pos                                          (28UL)   /*!<SYSCFG IO_DTR: PB12_DT (Bit 28) */
4058 #define SYSCFG_IO_DTR_PB12_DT_Msk                                          (0x10000000UL)   /*!< SYSCFG IO_DTR: PB12_DT (Bitfield-Mask: 0x01) */
4059 #define SYSCFG_IO_DTR_PB12_DT                                              SYSCFG_IO_DTR_PB12_DT_Msk
4060 #define SYSCFG_IO_DTR_PB11_DT_Pos                                          (27UL)   /*!<SYSCFG IO_DTR: PB11_DT (Bit 27) */
4061 #define SYSCFG_IO_DTR_PB11_DT_Msk                                          (0x8000000UL)    /*!< SYSCFG IO_DTR: PB11_DT (Bitfield-Mask: 0x01) */
4062 #define SYSCFG_IO_DTR_PB11_DT                                              SYSCFG_IO_DTR_PB11_DT_Msk
4063 #define SYSCFG_IO_DTR_PB10_DT_Pos                                          (26UL)   /*!<SYSCFG IO_DTR: PB10_DT (Bit 26) */
4064 #define SYSCFG_IO_DTR_PB10_DT_Msk                                          (0x4000000UL)    /*!< SYSCFG IO_DTR: PB10_DT (Bitfield-Mask: 0x01) */
4065 #define SYSCFG_IO_DTR_PB10_DT                                              SYSCFG_IO_DTR_PB10_DT_Msk
4066 #define SYSCFG_IO_DTR_PB9_DT_Pos                                           (25UL)   /*!<SYSCFG IO_DTR: PB9_DT (Bit 25) */
4067 #define SYSCFG_IO_DTR_PB9_DT_Msk                                           (0x2000000UL)    /*!< SYSCFG IO_DTR: PB9_DT (Bitfield-Mask: 0x01) */
4068 #define SYSCFG_IO_DTR_PB9_DT                                               SYSCFG_IO_DTR_PB9_DT_Msk
4069 #define SYSCFG_IO_DTR_PB8_DT_Pos                                           (24UL)   /*!<SYSCFG IO_DTR: PB8_DT (Bit 24) */
4070 #define SYSCFG_IO_DTR_PB8_DT_Msk                                           (0x1000000UL)    /*!< SYSCFG IO_DTR: PB8_DT (Bitfield-Mask: 0x01) */
4071 #define SYSCFG_IO_DTR_PB8_DT                                               SYSCFG_IO_DTR_PB8_DT_Msk
4072 #define SYSCFG_IO_DTR_PB7_DT_Pos                                           (23UL)   /*!<SYSCFG IO_DTR: PB7_DT (Bit 23) */
4073 #define SYSCFG_IO_DTR_PB7_DT_Msk                                           (0x800000UL)   /*!< SYSCFG IO_DTR: PB7_DT (Bitfield-Mask: 0x01) */
4074 #define SYSCFG_IO_DTR_PB7_DT                                               SYSCFG_IO_DTR_PB7_DT_Msk
4075 #define SYSCFG_IO_DTR_PB6_DT_Pos                                           (22UL)   /*!<SYSCFG IO_DTR: PB6_DT (Bit 22) */
4076 #define SYSCFG_IO_DTR_PB6_DT_Msk                                           (0x400000UL)   /*!< SYSCFG IO_DTR: PB6_DT (Bitfield-Mask: 0x01) */
4077 #define SYSCFG_IO_DTR_PB6_DT                                               SYSCFG_IO_DTR_PB6_DT_Msk
4078 #define SYSCFG_IO_DTR_PB5_DT_Pos                                           (21UL)   /*!<SYSCFG IO_DTR: PB5_DT (Bit 21) */
4079 #define SYSCFG_IO_DTR_PB5_DT_Msk                                           (0x200000UL)   /*!< SYSCFG IO_DTR: PB5_DT (Bitfield-Mask: 0x01) */
4080 #define SYSCFG_IO_DTR_PB5_DT                                               SYSCFG_IO_DTR_PB5_DT_Msk
4081 #define SYSCFG_IO_DTR_PB4_DT_Pos                                           (20UL)   /*!<SYSCFG IO_DTR: PB4_DT (Bit 20) */
4082 #define SYSCFG_IO_DTR_PB4_DT_Msk                                           (0x100000UL)   /*!< SYSCFG IO_DTR: PB4_DT (Bitfield-Mask: 0x01) */
4083 #define SYSCFG_IO_DTR_PB4_DT                                               SYSCFG_IO_DTR_PB4_DT_Msk
4084 #define SYSCFG_IO_DTR_PB3_DT_Pos                                           (19UL)   /*!<SYSCFG IO_DTR: PB3_DT (Bit 19) */
4085 #define SYSCFG_IO_DTR_PB3_DT_Msk                                           (0x80000UL)    /*!< SYSCFG IO_DTR: PB3_DT (Bitfield-Mask: 0x01) */
4086 #define SYSCFG_IO_DTR_PB3_DT                                               SYSCFG_IO_DTR_PB3_DT_Msk
4087 #define SYSCFG_IO_DTR_PB2_DT_Pos                                           (18UL)   /*!<SYSCFG IO_DTR: PB2_DT (Bit 18) */
4088 #define SYSCFG_IO_DTR_PB2_DT_Msk                                           (0x40000UL)    /*!< SYSCFG IO_DTR: PB2_DT (Bitfield-Mask: 0x01) */
4089 #define SYSCFG_IO_DTR_PB2_DT                                               SYSCFG_IO_DTR_PB2_DT_Msk
4090 #define SYSCFG_IO_DTR_PB1_DT_Pos                                           (17UL)   /*!<SYSCFG IO_DTR: PB1_DT (Bit 17) */
4091 #define SYSCFG_IO_DTR_PB1_DT_Msk                                           (0x20000UL)    /*!< SYSCFG IO_DTR: PB1_DT (Bitfield-Mask: 0x01) */
4092 #define SYSCFG_IO_DTR_PB1_DT                                               SYSCFG_IO_DTR_PB1_DT_Msk
4093 #define SYSCFG_IO_DTR_PB0_DT_Pos                                           (16UL)   /*!<SYSCFG IO_DTR: PB0_DT (Bit 16) */
4094 #define SYSCFG_IO_DTR_PB0_DT_Msk                                           (0x10000UL)    /*!< SYSCFG IO_DTR: PB0_DT (Bitfield-Mask: 0x01) */
4095 #define SYSCFG_IO_DTR_PB0_DT                                               SYSCFG_IO_DTR_PB0_DT_Msk
4096 #define SYSCFG_IO_DTR_PA15_DT_Pos                                          (15UL)   /*!<SYSCFG IO_DTR: PA15_DT (Bit 15) */
4097 #define SYSCFG_IO_DTR_PA15_DT_Msk                                          (0x8000UL)   /*!< SYSCFG IO_DTR: PA15_DT (Bitfield-Mask: 0x01) */
4098 #define SYSCFG_IO_DTR_PA15_DT                                              SYSCFG_IO_DTR_PA15_DT_Msk
4099 #define SYSCFG_IO_DTR_PA14_DT_Pos                                          (14UL)   /*!<SYSCFG IO_DTR: PA14_DT (Bit 14) */
4100 #define SYSCFG_IO_DTR_PA14_DT_Msk                                          (0x4000UL)   /*!< SYSCFG IO_DTR: PA14_DT (Bitfield-Mask: 0x01) */
4101 #define SYSCFG_IO_DTR_PA14_DT                                              SYSCFG_IO_DTR_PA14_DT_Msk
4102 #define SYSCFG_IO_DTR_PA13_DT_Pos                                          (13UL)   /*!<SYSCFG IO_DTR: PA13_DT (Bit 13) */
4103 #define SYSCFG_IO_DTR_PA13_DT_Msk                                          (0x2000UL)   /*!< SYSCFG IO_DTR: PA13_DT (Bitfield-Mask: 0x01) */
4104 #define SYSCFG_IO_DTR_PA13_DT                                              SYSCFG_IO_DTR_PA13_DT_Msk
4105 #define SYSCFG_IO_DTR_PA12_DT_Pos                                          (12UL)   /*!<SYSCFG IO_DTR: PA12_DT (Bit 12) */
4106 #define SYSCFG_IO_DTR_PA12_DT_Msk                                          (0x1000UL)   /*!< SYSCFG IO_DTR: PA12_DT (Bitfield-Mask: 0x01) */
4107 #define SYSCFG_IO_DTR_PA12_DT                                              SYSCFG_IO_DTR_PA12_DT_Msk
4108 #define SYSCFG_IO_DTR_PA11_DT_Pos                                          (11UL)   /*!<SYSCFG IO_DTR: PA11_DT (Bit 11) */
4109 #define SYSCFG_IO_DTR_PA11_DT_Msk                                          (0x800UL)    /*!< SYSCFG IO_DTR: PA11_DT (Bitfield-Mask: 0x01) */
4110 #define SYSCFG_IO_DTR_PA11_DT                                              SYSCFG_IO_DTR_PA11_DT_Msk
4111 #define SYSCFG_IO_DTR_PA10_DT_Pos                                          (10UL)   /*!<SYSCFG IO_DTR: PA10_DT (Bit 10) */
4112 #define SYSCFG_IO_DTR_PA10_DT_Msk                                          (0x400UL)    /*!< SYSCFG IO_DTR: PA10_DT (Bitfield-Mask: 0x01) */
4113 #define SYSCFG_IO_DTR_PA10_DT                                              SYSCFG_IO_DTR_PA10_DT_Msk
4114 #define SYSCFG_IO_DTR_PA9_DT_Pos                                           (9UL)    /*!<SYSCFG IO_DTR: PA9_DT (Bit 9) */
4115 #define SYSCFG_IO_DTR_PA9_DT_Msk                                           (0x200UL)    /*!< SYSCFG IO_DTR: PA9_DT (Bitfield-Mask: 0x01) */
4116 #define SYSCFG_IO_DTR_PA9_DT                                               SYSCFG_IO_DTR_PA9_DT_Msk
4117 #define SYSCFG_IO_DTR_PA8_DT_Pos                                           (8UL)    /*!<SYSCFG IO_DTR: PA8_DT (Bit 8) */
4118 #define SYSCFG_IO_DTR_PA8_DT_Msk                                           (0x100UL)    /*!< SYSCFG IO_DTR: PA8_DT (Bitfield-Mask: 0x01) */
4119 #define SYSCFG_IO_DTR_PA8_DT                                               SYSCFG_IO_DTR_PA8_DT_Msk
4120 #define SYSCFG_IO_DTR_PA7_DT_Pos                                           (7UL)    /*!<SYSCFG IO_DTR: PA7_DT (Bit 7) */
4121 #define SYSCFG_IO_DTR_PA7_DT_Msk                                           (0x80UL)   /*!< SYSCFG IO_DTR: PA7_DT (Bitfield-Mask: 0x01) */
4122 #define SYSCFG_IO_DTR_PA7_DT                                               SYSCFG_IO_DTR_PA7_DT_Msk
4123 #define SYSCFG_IO_DTR_PA6_DT_Pos                                           (6UL)    /*!<SYSCFG IO_DTR: PA6_DT (Bit 6) */
4124 #define SYSCFG_IO_DTR_PA6_DT_Msk                                           (0x40UL)   /*!< SYSCFG IO_DTR: PA6_DT (Bitfield-Mask: 0x01) */
4125 #define SYSCFG_IO_DTR_PA6_DT                                               SYSCFG_IO_DTR_PA6_DT_Msk
4126 #define SYSCFG_IO_DTR_PA5_DT_Pos                                           (5UL)    /*!<SYSCFG IO_DTR: PA5_DT (Bit 5) */
4127 #define SYSCFG_IO_DTR_PA5_DT_Msk                                           (0x20UL)   /*!< SYSCFG IO_DTR: PA5_DT (Bitfield-Mask: 0x01) */
4128 #define SYSCFG_IO_DTR_PA5_DT                                               SYSCFG_IO_DTR_PA5_DT_Msk
4129 #define SYSCFG_IO_DTR_PA4_DT_Pos                                           (4UL)    /*!<SYSCFG IO_DTR: PA4_DT (Bit 4) */
4130 #define SYSCFG_IO_DTR_PA4_DT_Msk                                           (0x10UL)   /*!< SYSCFG IO_DTR: PA4_DT (Bitfield-Mask: 0x01) */
4131 #define SYSCFG_IO_DTR_PA4_DT                                               SYSCFG_IO_DTR_PA4_DT_Msk
4132 #define SYSCFG_IO_DTR_PA3_DT_Pos                                           (3UL)    /*!<SYSCFG IO_DTR: PA3_DT (Bit 3) */
4133 #define SYSCFG_IO_DTR_PA3_DT_Msk                                           (0x8UL)    /*!< SYSCFG IO_DTR: PA3_DT (Bitfield-Mask: 0x01) */
4134 #define SYSCFG_IO_DTR_PA3_DT                                               SYSCFG_IO_DTR_PA3_DT_Msk
4135 #define SYSCFG_IO_DTR_PA2_DT_Pos                                           (2UL)    /*!<SYSCFG IO_DTR: PA2_DT (Bit 2) */
4136 #define SYSCFG_IO_DTR_PA2_DT_Msk                                           (0x4UL)    /*!< SYSCFG IO_DTR: PA2_DT (Bitfield-Mask: 0x01) */
4137 #define SYSCFG_IO_DTR_PA2_DT                                               SYSCFG_IO_DTR_PA2_DT_Msk
4138 #define SYSCFG_IO_DTR_PA1_DT_Pos                                           (1UL)    /*!<SYSCFG IO_DTR: PA1_DT (Bit 1) */
4139 #define SYSCFG_IO_DTR_PA1_DT_Msk                                           (0x2UL)    /*!< SYSCFG IO_DTR: PA1_DT (Bitfield-Mask: 0x01) */
4140 #define SYSCFG_IO_DTR_PA1_DT                                               SYSCFG_IO_DTR_PA1_DT_Msk
4141 #define SYSCFG_IO_DTR_PA0_DT_Pos                                           (0UL)    /*!<SYSCFG IO_DTR: PA0_DT (Bit 0) */
4142 #define SYSCFG_IO_DTR_PA0_DT_Msk                                           (0x1UL)    /*!< SYSCFG IO_DTR: PA0_DT (Bitfield-Mask: 0x01) */
4143 #define SYSCFG_IO_DTR_PA0_DT                                               SYSCFG_IO_DTR_PA0_DT_Msk
4144 
4145 /* =====================================================    IO_IBER    ===================================================== */
4146 #define SYSCFG_IO_IBER_PB15_IBE_Pos                                        (31UL)   /*!<SYSCFG IO_IBER: PB15_IBE (Bit 31) */
4147 #define SYSCFG_IO_IBER_PB15_IBE_Msk                                        (0x80000000UL)   /*!< SYSCFG IO_IBER: PB15_IBE (Bitfield-Mask: 0x01) */
4148 #define SYSCFG_IO_IBER_PB15_IBE                                            SYSCFG_IO_IBER_PB15_IBE_Msk
4149 #define SYSCFG_IO_IBER_PB14_IBE_Pos                                        (30UL)   /*!<SYSCFG IO_IBER: PB14_IBE (Bit 30) */
4150 #define SYSCFG_IO_IBER_PB14_IBE_Msk                                        (0x40000000UL)   /*!< SYSCFG IO_IBER: PB14_IBE (Bitfield-Mask: 0x01) */
4151 #define SYSCFG_IO_IBER_PB14_IBE                                            SYSCFG_IO_IBER_PB14_IBE_Msk
4152 #define SYSCFG_IO_IBER_PB13_IBE_Pos                                        (29UL)   /*!<SYSCFG IO_IBER: PB13_IBE (Bit 29) */
4153 #define SYSCFG_IO_IBER_PB13_IBE_Msk                                        (0x20000000UL)   /*!< SYSCFG IO_IBER: PB13_IBE (Bitfield-Mask: 0x01) */
4154 #define SYSCFG_IO_IBER_PB13_IBE                                            SYSCFG_IO_IBER_PB13_IBE_Msk
4155 #define SYSCFG_IO_IBER_PB12_IBE_Pos                                        (28UL)   /*!<SYSCFG IO_IBER: PB12_IBE (Bit 28) */
4156 #define SYSCFG_IO_IBER_PB12_IBE_Msk                                        (0x10000000UL)   /*!< SYSCFG IO_IBER: PB12_IBE (Bitfield-Mask: 0x01) */
4157 #define SYSCFG_IO_IBER_PB12_IBE                                            SYSCFG_IO_IBER_PB12_IBE_Msk
4158 #define SYSCFG_IO_IBER_PB11_IBE_Pos                                        (27UL)   /*!<SYSCFG IO_IBER: PB11_IBE (Bit 27) */
4159 #define SYSCFG_IO_IBER_PB11_IBE_Msk                                        (0x8000000UL)    /*!< SYSCFG IO_IBER: PB11_IBE (Bitfield-Mask: 0x01) */
4160 #define SYSCFG_IO_IBER_PB11_IBE                                            SYSCFG_IO_IBER_PB11_IBE_Msk
4161 #define SYSCFG_IO_IBER_PB10_IBE_Pos                                        (26UL)   /*!<SYSCFG IO_IBER: PB10_IBE (Bit 26) */
4162 #define SYSCFG_IO_IBER_PB10_IBE_Msk                                        (0x4000000UL)    /*!< SYSCFG IO_IBER: PB10_IBE (Bitfield-Mask: 0x01) */
4163 #define SYSCFG_IO_IBER_PB10_IBE                                            SYSCFG_IO_IBER_PB10_IBE_Msk
4164 #define SYSCFG_IO_IBER_PB9_IBE_Pos                                         (25UL)   /*!<SYSCFG IO_IBER: PB9_IBE (Bit 25) */
4165 #define SYSCFG_IO_IBER_PB9_IBE_Msk                                         (0x2000000UL)    /*!< SYSCFG IO_IBER: PB9_IBE (Bitfield-Mask: 0x01) */
4166 #define SYSCFG_IO_IBER_PB9_IBE                                             SYSCFG_IO_IBER_PB9_IBE_Msk
4167 #define SYSCFG_IO_IBER_PB8_IBE_Pos                                         (24UL)   /*!<SYSCFG IO_IBER: PB8_IBE (Bit 24) */
4168 #define SYSCFG_IO_IBER_PB8_IBE_Msk                                         (0x1000000UL)    /*!< SYSCFG IO_IBER: PB8_IBE (Bitfield-Mask: 0x01) */
4169 #define SYSCFG_IO_IBER_PB8_IBE                                             SYSCFG_IO_IBER_PB8_IBE_Msk
4170 #define SYSCFG_IO_IBER_PB7_IBE_Pos                                         (23UL)   /*!<SYSCFG IO_IBER: PB7_IBE (Bit 23) */
4171 #define SYSCFG_IO_IBER_PB7_IBE_Msk                                         (0x800000UL)   /*!< SYSCFG IO_IBER: PB7_IBE (Bitfield-Mask: 0x01) */
4172 #define SYSCFG_IO_IBER_PB7_IBE                                             SYSCFG_IO_IBER_PB7_IBE_Msk
4173 #define SYSCFG_IO_IBER_PB6_IBE_Pos                                         (22UL)   /*!<SYSCFG IO_IBER: PB6_IBE (Bit 22) */
4174 #define SYSCFG_IO_IBER_PB6_IBE_Msk                                         (0x400000UL)   /*!< SYSCFG IO_IBER: PB6_IBE (Bitfield-Mask: 0x01) */
4175 #define SYSCFG_IO_IBER_PB6_IBE                                             SYSCFG_IO_IBER_PB6_IBE_Msk
4176 #define SYSCFG_IO_IBER_PB5_IBE_Pos                                         (21UL)   /*!<SYSCFG IO_IBER: PB5_IBE (Bit 21) */
4177 #define SYSCFG_IO_IBER_PB5_IBE_Msk                                         (0x200000UL)   /*!< SYSCFG IO_IBER: PB5_IBE (Bitfield-Mask: 0x01) */
4178 #define SYSCFG_IO_IBER_PB5_IBE                                             SYSCFG_IO_IBER_PB5_IBE_Msk
4179 #define SYSCFG_IO_IBER_PB4_IBE_Pos                                         (20UL)   /*!<SYSCFG IO_IBER: PB4_IBE (Bit 20) */
4180 #define SYSCFG_IO_IBER_PB4_IBE_Msk                                         (0x100000UL)   /*!< SYSCFG IO_IBER: PB4_IBE (Bitfield-Mask: 0x01) */
4181 #define SYSCFG_IO_IBER_PB4_IBE                                             SYSCFG_IO_IBER_PB4_IBE_Msk
4182 #define SYSCFG_IO_IBER_PB3_IBE_Pos                                         (19UL)   /*!<SYSCFG IO_IBER: PB3_IBE (Bit 19) */
4183 #define SYSCFG_IO_IBER_PB3_IBE_Msk                                         (0x80000UL)    /*!< SYSCFG IO_IBER: PB3_IBE (Bitfield-Mask: 0x01) */
4184 #define SYSCFG_IO_IBER_PB3_IBE                                             SYSCFG_IO_IBER_PB3_IBE_Msk
4185 #define SYSCFG_IO_IBER_PB2_IBE_Pos                                         (18UL)   /*!<SYSCFG IO_IBER: PB2_IBE (Bit 18) */
4186 #define SYSCFG_IO_IBER_PB2_IBE_Msk                                         (0x40000UL)    /*!< SYSCFG IO_IBER: PB2_IBE (Bitfield-Mask: 0x01) */
4187 #define SYSCFG_IO_IBER_PB2_IBE                                             SYSCFG_IO_IBER_PB2_IBE_Msk
4188 #define SYSCFG_IO_IBER_PB1_IBE_Pos                                         (17UL)   /*!<SYSCFG IO_IBER: PB1_IBE (Bit 17) */
4189 #define SYSCFG_IO_IBER_PB1_IBE_Msk                                         (0x20000UL)    /*!< SYSCFG IO_IBER: PB1_IBE (Bitfield-Mask: 0x01) */
4190 #define SYSCFG_IO_IBER_PB1_IBE                                             SYSCFG_IO_IBER_PB1_IBE_Msk
4191 #define SYSCFG_IO_IBER_PB0_IBE_Pos                                         (16UL)   /*!<SYSCFG IO_IBER: PB0_IBE (Bit 16) */
4192 #define SYSCFG_IO_IBER_PB0_IBE_Msk                                         (0x10000UL)    /*!< SYSCFG IO_IBER: PB0_IBE (Bitfield-Mask: 0x01) */
4193 #define SYSCFG_IO_IBER_PB0_IBE                                             SYSCFG_IO_IBER_PB0_IBE_Msk
4194 #define SYSCFG_IO_IBER_PA15_IBE_Pos                                        (15UL)   /*!<SYSCFG IO_IBER: PA15_IBE (Bit 15) */
4195 #define SYSCFG_IO_IBER_PA15_IBE_Msk                                        (0x8000UL)   /*!< SYSCFG IO_IBER: PA15_IBE (Bitfield-Mask: 0x01) */
4196 #define SYSCFG_IO_IBER_PA15_IBE                                            SYSCFG_IO_IBER_PA15_IBE_Msk
4197 #define SYSCFG_IO_IBER_PA14_IBE_Pos                                        (14UL)   /*!<SYSCFG IO_IBER: PA14_IBE (Bit 14) */
4198 #define SYSCFG_IO_IBER_PA14_IBE_Msk                                        (0x4000UL)   /*!< SYSCFG IO_IBER: PA14_IBE (Bitfield-Mask: 0x01) */
4199 #define SYSCFG_IO_IBER_PA14_IBE                                            SYSCFG_IO_IBER_PA14_IBE_Msk
4200 #define SYSCFG_IO_IBER_PA13_IBE_Pos                                        (13UL)   /*!<SYSCFG IO_IBER: PA13_IBE (Bit 13) */
4201 #define SYSCFG_IO_IBER_PA13_IBE_Msk                                        (0x2000UL)   /*!< SYSCFG IO_IBER: PA13_IBE (Bitfield-Mask: 0x01) */
4202 #define SYSCFG_IO_IBER_PA13_IBE                                            SYSCFG_IO_IBER_PA13_IBE_Msk
4203 #define SYSCFG_IO_IBER_PA12_IBE_Pos                                        (12UL)   /*!<SYSCFG IO_IBER: PA12_IBE (Bit 12) */
4204 #define SYSCFG_IO_IBER_PA12_IBE_Msk                                        (0x1000UL)   /*!< SYSCFG IO_IBER: PA12_IBE (Bitfield-Mask: 0x01) */
4205 #define SYSCFG_IO_IBER_PA12_IBE                                            SYSCFG_IO_IBER_PA12_IBE_Msk
4206 #define SYSCFG_IO_IBER_PA11_IBE_Pos                                        (11UL)   /*!<SYSCFG IO_IBER: PA11_IBE (Bit 11) */
4207 #define SYSCFG_IO_IBER_PA11_IBE_Msk                                        (0x800UL)    /*!< SYSCFG IO_IBER: PA11_IBE (Bitfield-Mask: 0x01) */
4208 #define SYSCFG_IO_IBER_PA11_IBE                                            SYSCFG_IO_IBER_PA11_IBE_Msk
4209 #define SYSCFG_IO_IBER_PA10_IBE_Pos                                        (10UL)   /*!<SYSCFG IO_IBER: PA10_IBE (Bit 10) */
4210 #define SYSCFG_IO_IBER_PA10_IBE_Msk                                        (0x400UL)    /*!< SYSCFG IO_IBER: PA10_IBE (Bitfield-Mask: 0x01) */
4211 #define SYSCFG_IO_IBER_PA10_IBE                                            SYSCFG_IO_IBER_PA10_IBE_Msk
4212 #define SYSCFG_IO_IBER_PA9_IBE_Pos                                         (9UL)    /*!<SYSCFG IO_IBER: PA9_IBE (Bit 9) */
4213 #define SYSCFG_IO_IBER_PA9_IBE_Msk                                         (0x200UL)    /*!< SYSCFG IO_IBER: PA9_IBE (Bitfield-Mask: 0x01) */
4214 #define SYSCFG_IO_IBER_PA9_IBE                                             SYSCFG_IO_IBER_PA9_IBE_Msk
4215 #define SYSCFG_IO_IBER_PA8_IBE_Pos                                         (8UL)    /*!<SYSCFG IO_IBER: PA8_IBE (Bit 8) */
4216 #define SYSCFG_IO_IBER_PA8_IBE_Msk                                         (0x100UL)    /*!< SYSCFG IO_IBER: PA8_IBE (Bitfield-Mask: 0x01) */
4217 #define SYSCFG_IO_IBER_PA8_IBE                                             SYSCFG_IO_IBER_PA8_IBE_Msk
4218 #define SYSCFG_IO_IBER_PA7_IBE_Pos                                         (7UL)    /*!<SYSCFG IO_IBER: PA7_IBE (Bit 7) */
4219 #define SYSCFG_IO_IBER_PA7_IBE_Msk                                         (0x80UL)   /*!< SYSCFG IO_IBER: PA7_IBE (Bitfield-Mask: 0x01) */
4220 #define SYSCFG_IO_IBER_PA7_IBE                                             SYSCFG_IO_IBER_PA7_IBE_Msk
4221 #define SYSCFG_IO_IBER_PA6_IBE_Pos                                         (6UL)    /*!<SYSCFG IO_IBER: PA6_IBE (Bit 6) */
4222 #define SYSCFG_IO_IBER_PA6_IBE_Msk                                         (0x40UL)   /*!< SYSCFG IO_IBER: PA6_IBE (Bitfield-Mask: 0x01) */
4223 #define SYSCFG_IO_IBER_PA6_IBE                                             SYSCFG_IO_IBER_PA6_IBE_Msk
4224 #define SYSCFG_IO_IBER_PA5_IBE_Pos                                         (5UL)    /*!<SYSCFG IO_IBER: PA5_IBE (Bit 5) */
4225 #define SYSCFG_IO_IBER_PA5_IBE_Msk                                         (0x20UL)   /*!< SYSCFG IO_IBER: PA5_IBE (Bitfield-Mask: 0x01) */
4226 #define SYSCFG_IO_IBER_PA5_IBE                                             SYSCFG_IO_IBER_PA5_IBE_Msk
4227 #define SYSCFG_IO_IBER_PA4_IBE_Pos                                         (4UL)    /*!<SYSCFG IO_IBER: PA4_IBE (Bit 4) */
4228 #define SYSCFG_IO_IBER_PA4_IBE_Msk                                         (0x10UL)   /*!< SYSCFG IO_IBER: PA4_IBE (Bitfield-Mask: 0x01) */
4229 #define SYSCFG_IO_IBER_PA4_IBE                                             SYSCFG_IO_IBER_PA4_IBE_Msk
4230 #define SYSCFG_IO_IBER_PA3_IBE_Pos                                         (3UL)    /*!<SYSCFG IO_IBER: PA3_IBE (Bit 3) */
4231 #define SYSCFG_IO_IBER_PA3_IBE_Msk                                         (0x8UL)    /*!< SYSCFG IO_IBER: PA3_IBE (Bitfield-Mask: 0x01) */
4232 #define SYSCFG_IO_IBER_PA3_IBE                                             SYSCFG_IO_IBER_PA3_IBE_Msk
4233 #define SYSCFG_IO_IBER_PA2_IBE_Pos                                         (2UL)    /*!<SYSCFG IO_IBER: PA2_IBE (Bit 2) */
4234 #define SYSCFG_IO_IBER_PA2_IBE_Msk                                         (0x4UL)    /*!< SYSCFG IO_IBER: PA2_IBE (Bitfield-Mask: 0x01) */
4235 #define SYSCFG_IO_IBER_PA2_IBE                                             SYSCFG_IO_IBER_PA2_IBE_Msk
4236 #define SYSCFG_IO_IBER_PA1_IBE_Pos                                         (1UL)    /*!<SYSCFG IO_IBER: PA1_IBE (Bit 1) */
4237 #define SYSCFG_IO_IBER_PA1_IBE_Msk                                         (0x2UL)    /*!< SYSCFG IO_IBER: PA1_IBE (Bitfield-Mask: 0x01) */
4238 #define SYSCFG_IO_IBER_PA1_IBE                                             SYSCFG_IO_IBER_PA1_IBE_Msk
4239 #define SYSCFG_IO_IBER_PA0_IBE_Pos                                         (0UL)    /*!<SYSCFG IO_IBER: PA0_IBE (Bit 0) */
4240 #define SYSCFG_IO_IBER_PA0_IBE_Msk                                         (0x1UL)    /*!< SYSCFG IO_IBER: PA0_IBE (Bitfield-Mask: 0x01) */
4241 #define SYSCFG_IO_IBER_PA0_IBE                                             SYSCFG_IO_IBER_PA0_IBE_Msk
4242 
4243 /* =====================================================    IO_IEVR    ===================================================== */
4244 #define SYSCFG_IO_IEVR_PB15_IEV_Pos                                        (31UL)   /*!<SYSCFG IO_IEVR: PB15_IEV (Bit 31) */
4245 #define SYSCFG_IO_IEVR_PB15_IEV_Msk                                        (0x80000000UL)   /*!< SYSCFG IO_IEVR: PB15_IEV (Bitfield-Mask: 0x01) */
4246 #define SYSCFG_IO_IEVR_PB15_IEV                                            SYSCFG_IO_IEVR_PB15_IEV_Msk
4247 #define SYSCFG_IO_IEVR_PB14_IEV_Pos                                        (30UL)   /*!<SYSCFG IO_IEVR: PB14_IEV (Bit 30) */
4248 #define SYSCFG_IO_IEVR_PB14_IEV_Msk                                        (0x40000000UL)   /*!< SYSCFG IO_IEVR: PB14_IEV (Bitfield-Mask: 0x01) */
4249 #define SYSCFG_IO_IEVR_PB14_IEV                                            SYSCFG_IO_IEVR_PB14_IEV_Msk
4250 #define SYSCFG_IO_IEVR_PB13_IEV_Pos                                        (29UL)   /*!<SYSCFG IO_IEVR: PB13_IEV (Bit 29) */
4251 #define SYSCFG_IO_IEVR_PB13_IEV_Msk                                        (0x20000000UL)   /*!< SYSCFG IO_IEVR: PB13_IEV (Bitfield-Mask: 0x01) */
4252 #define SYSCFG_IO_IEVR_PB13_IEV                                            SYSCFG_IO_IEVR_PB13_IEV_Msk
4253 #define SYSCFG_IO_IEVR_PB12_IEV_Pos                                        (28UL)   /*!<SYSCFG IO_IEVR: PB12_IEV (Bit 28) */
4254 #define SYSCFG_IO_IEVR_PB12_IEV_Msk                                        (0x10000000UL)   /*!< SYSCFG IO_IEVR: PB12_IEV (Bitfield-Mask: 0x01) */
4255 #define SYSCFG_IO_IEVR_PB12_IEV                                            SYSCFG_IO_IEVR_PB12_IEV_Msk
4256 #define SYSCFG_IO_IEVR_PB11_IEV_Pos                                        (27UL)   /*!<SYSCFG IO_IEVR: PB11_IEV (Bit 27) */
4257 #define SYSCFG_IO_IEVR_PB11_IEV_Msk                                        (0x8000000UL)    /*!< SYSCFG IO_IEVR: PB11_IEV (Bitfield-Mask: 0x01) */
4258 #define SYSCFG_IO_IEVR_PB11_IEV                                            SYSCFG_IO_IEVR_PB11_IEV_Msk
4259 #define SYSCFG_IO_IEVR_PB10_IEV_Pos                                        (26UL)   /*!<SYSCFG IO_IEVR: PB10_IEV (Bit 26) */
4260 #define SYSCFG_IO_IEVR_PB10_IEV_Msk                                        (0x4000000UL)    /*!< SYSCFG IO_IEVR: PB10_IEV (Bitfield-Mask: 0x01) */
4261 #define SYSCFG_IO_IEVR_PB10_IEV                                            SYSCFG_IO_IEVR_PB10_IEV_Msk
4262 #define SYSCFG_IO_IEVR_PB9_IEV_Pos                                         (25UL)   /*!<SYSCFG IO_IEVR: PB9_IEV (Bit 25) */
4263 #define SYSCFG_IO_IEVR_PB9_IEV_Msk                                         (0x2000000UL)    /*!< SYSCFG IO_IEVR: PB9_IEV (Bitfield-Mask: 0x01) */
4264 #define SYSCFG_IO_IEVR_PB9_IEV                                             SYSCFG_IO_IEVR_PB9_IEV_Msk
4265 #define SYSCFG_IO_IEVR_PB8_IEV_Pos                                         (24UL)   /*!<SYSCFG IO_IEVR: PB8_IEV (Bit 24) */
4266 #define SYSCFG_IO_IEVR_PB8_IEV_Msk                                         (0x1000000UL)    /*!< SYSCFG IO_IEVR: PB8_IEV (Bitfield-Mask: 0x01) */
4267 #define SYSCFG_IO_IEVR_PB8_IEV                                             SYSCFG_IO_IEVR_PB8_IEV_Msk
4268 #define SYSCFG_IO_IEVR_PB7_IEV_Pos                                         (23UL)   /*!<SYSCFG IO_IEVR: PB7_IEV (Bit 23) */
4269 #define SYSCFG_IO_IEVR_PB7_IEV_Msk                                         (0x800000UL)   /*!< SYSCFG IO_IEVR: PB7_IEV (Bitfield-Mask: 0x01) */
4270 #define SYSCFG_IO_IEVR_PB7_IEV                                             SYSCFG_IO_IEVR_PB7_IEV_Msk
4271 #define SYSCFG_IO_IEVR_PB6_IEV_Pos                                         (22UL)   /*!<SYSCFG IO_IEVR: PB6_IEV (Bit 22) */
4272 #define SYSCFG_IO_IEVR_PB6_IEV_Msk                                         (0x400000UL)   /*!< SYSCFG IO_IEVR: PB6_IEV (Bitfield-Mask: 0x01) */
4273 #define SYSCFG_IO_IEVR_PB6_IEV                                             SYSCFG_IO_IEVR_PB6_IEV_Msk
4274 #define SYSCFG_IO_IEVR_PB5_IEV_Pos                                         (21UL)   /*!<SYSCFG IO_IEVR: PB5_IEV (Bit 21) */
4275 #define SYSCFG_IO_IEVR_PB5_IEV_Msk                                         (0x200000UL)   /*!< SYSCFG IO_IEVR: PB5_IEV (Bitfield-Mask: 0x01) */
4276 #define SYSCFG_IO_IEVR_PB5_IEV                                             SYSCFG_IO_IEVR_PB5_IEV_Msk
4277 #define SYSCFG_IO_IEVR_PB4_IEV_Pos                                         (20UL)   /*!<SYSCFG IO_IEVR: PB4_IEV (Bit 20) */
4278 #define SYSCFG_IO_IEVR_PB4_IEV_Msk                                         (0x100000UL)   /*!< SYSCFG IO_IEVR: PB4_IEV (Bitfield-Mask: 0x01) */
4279 #define SYSCFG_IO_IEVR_PB4_IEV                                             SYSCFG_IO_IEVR_PB4_IEV_Msk
4280 #define SYSCFG_IO_IEVR_PB3_IEV_Pos                                         (19UL)   /*!<SYSCFG IO_IEVR: PB3_IEV (Bit 19) */
4281 #define SYSCFG_IO_IEVR_PB3_IEV_Msk                                         (0x80000UL)    /*!< SYSCFG IO_IEVR: PB3_IEV (Bitfield-Mask: 0x01) */
4282 #define SYSCFG_IO_IEVR_PB3_IEV                                             SYSCFG_IO_IEVR_PB3_IEV_Msk
4283 #define SYSCFG_IO_IEVR_PB2_IEV_Pos                                         (18UL)   /*!<SYSCFG IO_IEVR: PB2_IEV (Bit 18) */
4284 #define SYSCFG_IO_IEVR_PB2_IEV_Msk                                         (0x40000UL)    /*!< SYSCFG IO_IEVR: PB2_IEV (Bitfield-Mask: 0x01) */
4285 #define SYSCFG_IO_IEVR_PB2_IEV                                             SYSCFG_IO_IEVR_PB2_IEV_Msk
4286 #define SYSCFG_IO_IEVR_PB1_IEV_Pos                                         (17UL)   /*!<SYSCFG IO_IEVR: PB1_IEV (Bit 17) */
4287 #define SYSCFG_IO_IEVR_PB1_IEV_Msk                                         (0x20000UL)    /*!< SYSCFG IO_IEVR: PB1_IEV (Bitfield-Mask: 0x01) */
4288 #define SYSCFG_IO_IEVR_PB1_IEV                                             SYSCFG_IO_IEVR_PB1_IEV_Msk
4289 #define SYSCFG_IO_IEVR_PB0_IEV_Pos                                         (16UL)   /*!<SYSCFG IO_IEVR: PB0_IEV (Bit 16) */
4290 #define SYSCFG_IO_IEVR_PB0_IEV_Msk                                         (0x10000UL)    /*!< SYSCFG IO_IEVR: PB0_IEV (Bitfield-Mask: 0x01) */
4291 #define SYSCFG_IO_IEVR_PB0_IEV                                             SYSCFG_IO_IEVR_PB0_IEV_Msk
4292 #define SYSCFG_IO_IEVR_PA15_IEV_Pos                                        (15UL)   /*!<SYSCFG IO_IEVR: PA15_IEV (Bit 15) */
4293 #define SYSCFG_IO_IEVR_PA15_IEV_Msk                                        (0x8000UL)   /*!< SYSCFG IO_IEVR: PA15_IEV (Bitfield-Mask: 0x01) */
4294 #define SYSCFG_IO_IEVR_PA15_IEV                                            SYSCFG_IO_IEVR_PA15_IEV_Msk
4295 #define SYSCFG_IO_IEVR_PA14_IEV_Pos                                        (14UL)   /*!<SYSCFG IO_IEVR: PA14_IEV (Bit 14) */
4296 #define SYSCFG_IO_IEVR_PA14_IEV_Msk                                        (0x4000UL)   /*!< SYSCFG IO_IEVR: PA14_IEV (Bitfield-Mask: 0x01) */
4297 #define SYSCFG_IO_IEVR_PA14_IEV                                            SYSCFG_IO_IEVR_PA14_IEV_Msk
4298 #define SYSCFG_IO_IEVR_PA13_IEV_Pos                                        (13UL)   /*!<SYSCFG IO_IEVR: PA13_IEV (Bit 13) */
4299 #define SYSCFG_IO_IEVR_PA13_IEV_Msk                                        (0x2000UL)   /*!< SYSCFG IO_IEVR: PA13_IEV (Bitfield-Mask: 0x01) */
4300 #define SYSCFG_IO_IEVR_PA13_IEV                                            SYSCFG_IO_IEVR_PA13_IEV_Msk
4301 #define SYSCFG_IO_IEVR_PA12_IEV_Pos                                        (12UL)   /*!<SYSCFG IO_IEVR: PA12_IEV (Bit 12) */
4302 #define SYSCFG_IO_IEVR_PA12_IEV_Msk                                        (0x1000UL)   /*!< SYSCFG IO_IEVR: PA12_IEV (Bitfield-Mask: 0x01) */
4303 #define SYSCFG_IO_IEVR_PA12_IEV                                            SYSCFG_IO_IEVR_PA12_IEV_Msk
4304 #define SYSCFG_IO_IEVR_PA11_IEV_Pos                                        (11UL)   /*!<SYSCFG IO_IEVR: PA11_IEV (Bit 11) */
4305 #define SYSCFG_IO_IEVR_PA11_IEV_Msk                                        (0x800UL)    /*!< SYSCFG IO_IEVR: PA11_IEV (Bitfield-Mask: 0x01) */
4306 #define SYSCFG_IO_IEVR_PA11_IEV                                            SYSCFG_IO_IEVR_PA11_IEV_Msk
4307 #define SYSCFG_IO_IEVR_PA10_IEV_Pos                                        (10UL)   /*!<SYSCFG IO_IEVR: PA10_IEV (Bit 10) */
4308 #define SYSCFG_IO_IEVR_PA10_IEV_Msk                                        (0x400UL)    /*!< SYSCFG IO_IEVR: PA10_IEV (Bitfield-Mask: 0x01) */
4309 #define SYSCFG_IO_IEVR_PA10_IEV                                            SYSCFG_IO_IEVR_PA10_IEV_Msk
4310 #define SYSCFG_IO_IEVR_PA9_IEV_Pos                                         (9UL)    /*!<SYSCFG IO_IEVR: PA9_IEV (Bit 9) */
4311 #define SYSCFG_IO_IEVR_PA9_IEV_Msk                                         (0x200UL)    /*!< SYSCFG IO_IEVR: PA9_IEV (Bitfield-Mask: 0x01) */
4312 #define SYSCFG_IO_IEVR_PA9_IEV                                             SYSCFG_IO_IEVR_PA9_IEV_Msk
4313 #define SYSCFG_IO_IEVR_PA8_IEV_Pos                                         (8UL)    /*!<SYSCFG IO_IEVR: PA8_IEV (Bit 8) */
4314 #define SYSCFG_IO_IEVR_PA8_IEV_Msk                                         (0x100UL)    /*!< SYSCFG IO_IEVR: PA8_IEV (Bitfield-Mask: 0x01) */
4315 #define SYSCFG_IO_IEVR_PA8_IEV                                             SYSCFG_IO_IEVR_PA8_IEV_Msk
4316 #define SYSCFG_IO_IEVR_PA7_IEV_Pos                                         (7UL)    /*!<SYSCFG IO_IEVR: PA7_IEV (Bit 7) */
4317 #define SYSCFG_IO_IEVR_PA7_IEV_Msk                                         (0x80UL)   /*!< SYSCFG IO_IEVR: PA7_IEV (Bitfield-Mask: 0x01) */
4318 #define SYSCFG_IO_IEVR_PA7_IEV                                             SYSCFG_IO_IEVR_PA7_IEV_Msk
4319 #define SYSCFG_IO_IEVR_PA6_IEV_Pos                                         (6UL)    /*!<SYSCFG IO_IEVR: PA6_IEV (Bit 6) */
4320 #define SYSCFG_IO_IEVR_PA6_IEV_Msk                                         (0x40UL)   /*!< SYSCFG IO_IEVR: PA6_IEV (Bitfield-Mask: 0x01) */
4321 #define SYSCFG_IO_IEVR_PA6_IEV                                             SYSCFG_IO_IEVR_PA6_IEV_Msk
4322 #define SYSCFG_IO_IEVR_PA5_IEV_Pos                                         (5UL)    /*!<SYSCFG IO_IEVR: PA5_IEV (Bit 5) */
4323 #define SYSCFG_IO_IEVR_PA5_IEV_Msk                                         (0x20UL)   /*!< SYSCFG IO_IEVR: PA5_IEV (Bitfield-Mask: 0x01) */
4324 #define SYSCFG_IO_IEVR_PA5_IEV                                             SYSCFG_IO_IEVR_PA5_IEV_Msk
4325 #define SYSCFG_IO_IEVR_PA4_IEV_Pos                                         (4UL)    /*!<SYSCFG IO_IEVR: PA4_IEV (Bit 4) */
4326 #define SYSCFG_IO_IEVR_PA4_IEV_Msk                                         (0x10UL)   /*!< SYSCFG IO_IEVR: PA4_IEV (Bitfield-Mask: 0x01) */
4327 #define SYSCFG_IO_IEVR_PA4_IEV                                             SYSCFG_IO_IEVR_PA4_IEV_Msk
4328 #define SYSCFG_IO_IEVR_PA3_IEV_Pos                                         (3UL)    /*!<SYSCFG IO_IEVR: PA3_IEV (Bit 3) */
4329 #define SYSCFG_IO_IEVR_PA3_IEV_Msk                                         (0x8UL)    /*!< SYSCFG IO_IEVR: PA3_IEV (Bitfield-Mask: 0x01) */
4330 #define SYSCFG_IO_IEVR_PA3_IEV                                             SYSCFG_IO_IEVR_PA3_IEV_Msk
4331 #define SYSCFG_IO_IEVR_PA2_IEV_Pos                                         (2UL)    /*!<SYSCFG IO_IEVR: PA2_IEV (Bit 2) */
4332 #define SYSCFG_IO_IEVR_PA2_IEV_Msk                                         (0x4UL)    /*!< SYSCFG IO_IEVR: PA2_IEV (Bitfield-Mask: 0x01) */
4333 #define SYSCFG_IO_IEVR_PA2_IEV                                             SYSCFG_IO_IEVR_PA2_IEV_Msk
4334 #define SYSCFG_IO_IEVR_PA1_IEV_Pos                                         (1UL)    /*!<SYSCFG IO_IEVR: PA1_IEV (Bit 1) */
4335 #define SYSCFG_IO_IEVR_PA1_IEV_Msk                                         (0x2UL)    /*!< SYSCFG IO_IEVR: PA1_IEV (Bitfield-Mask: 0x01) */
4336 #define SYSCFG_IO_IEVR_PA1_IEV                                             SYSCFG_IO_IEVR_PA1_IEV_Msk
4337 #define SYSCFG_IO_IEVR_PA0_IEV_Pos                                         (0UL)    /*!<SYSCFG IO_IEVR: PA0_IEV (Bit 0) */
4338 #define SYSCFG_IO_IEVR_PA0_IEV_Msk                                         (0x1UL)    /*!< SYSCFG IO_IEVR: PA0_IEV (Bitfield-Mask: 0x01) */
4339 #define SYSCFG_IO_IEVR_PA0_IEV                                             SYSCFG_IO_IEVR_PA0_IEV_Msk
4340 
4341 /* =====================================================    IO_IER    ===================================================== */
4342 #define SYSCFG_IO_IER_PB15_IE_Pos                                          (31UL)   /*!<SYSCFG IO_IER: PB15_IE (Bit 31) */
4343 #define SYSCFG_IO_IER_PB15_IE_Msk                                          (0x80000000UL)   /*!< SYSCFG IO_IER: PB15_IE (Bitfield-Mask: 0x01) */
4344 #define SYSCFG_IO_IER_PB15_IE                                              SYSCFG_IO_IER_PB15_IE_Msk
4345 #define SYSCFG_IO_IER_PB14_IE_Pos                                          (30UL)   /*!<SYSCFG IO_IER: PB14_IE (Bit 30) */
4346 #define SYSCFG_IO_IER_PB14_IE_Msk                                          (0x40000000UL)   /*!< SYSCFG IO_IER: PB14_IE (Bitfield-Mask: 0x01) */
4347 #define SYSCFG_IO_IER_PB14_IE                                              SYSCFG_IO_IER_PB14_IE_Msk
4348 #define SYSCFG_IO_IER_PB13_IE_Pos                                          (29UL)   /*!<SYSCFG IO_IER: PB13_IE (Bit 29) */
4349 #define SYSCFG_IO_IER_PB13_IE_Msk                                          (0x20000000UL)   /*!< SYSCFG IO_IER: PB13_IE (Bitfield-Mask: 0x01) */
4350 #define SYSCFG_IO_IER_PB13_IE                                              SYSCFG_IO_IER_PB13_IE_Msk
4351 #define SYSCFG_IO_IER_PB12_IE_Pos                                          (28UL)   /*!<SYSCFG IO_IER: PB12_IE (Bit 28) */
4352 #define SYSCFG_IO_IER_PB12_IE_Msk                                          (0x10000000UL)   /*!< SYSCFG IO_IER: PB12_IE (Bitfield-Mask: 0x01) */
4353 #define SYSCFG_IO_IER_PB12_IE                                              SYSCFG_IO_IER_PB12_IE_Msk
4354 #define SYSCFG_IO_IER_PB11_IE_Pos                                          (27UL)   /*!<SYSCFG IO_IER: PB11_IE (Bit 27) */
4355 #define SYSCFG_IO_IER_PB11_IE_Msk                                          (0x8000000UL)    /*!< SYSCFG IO_IER: PB11_IE (Bitfield-Mask: 0x01) */
4356 #define SYSCFG_IO_IER_PB11_IE                                              SYSCFG_IO_IER_PB11_IE_Msk
4357 #define SYSCFG_IO_IER_PB10_IE_Pos                                          (26UL)   /*!<SYSCFG IO_IER: PB10_IE (Bit 26) */
4358 #define SYSCFG_IO_IER_PB10_IE_Msk                                          (0x4000000UL)    /*!< SYSCFG IO_IER: PB10_IE (Bitfield-Mask: 0x01) */
4359 #define SYSCFG_IO_IER_PB10_IE                                              SYSCFG_IO_IER_PB10_IE_Msk
4360 #define SYSCFG_IO_IER_PB9_IE_Pos                                           (25UL)   /*!<SYSCFG IO_IER: PB9_IE (Bit 25) */
4361 #define SYSCFG_IO_IER_PB9_IE_Msk                                           (0x2000000UL)    /*!< SYSCFG IO_IER: PB9_IE (Bitfield-Mask: 0x01) */
4362 #define SYSCFG_IO_IER_PB9_IE                                               SYSCFG_IO_IER_PB9_IE_Msk
4363 #define SYSCFG_IO_IER_PB8_IE_Pos                                           (24UL)   /*!<SYSCFG IO_IER: PB8_IE (Bit 24) */
4364 #define SYSCFG_IO_IER_PB8_IE_Msk                                           (0x1000000UL)    /*!< SYSCFG IO_IER: PB8_IE (Bitfield-Mask: 0x01) */
4365 #define SYSCFG_IO_IER_PB8_IE                                               SYSCFG_IO_IER_PB8_IE_Msk
4366 #define SYSCFG_IO_IER_PB7_IE_Pos                                           (23UL)   /*!<SYSCFG IO_IER: PB7_IE (Bit 23) */
4367 #define SYSCFG_IO_IER_PB7_IE_Msk                                           (0x800000UL)   /*!< SYSCFG IO_IER: PB7_IE (Bitfield-Mask: 0x01) */
4368 #define SYSCFG_IO_IER_PB7_IE                                               SYSCFG_IO_IER_PB7_IE_Msk
4369 #define SYSCFG_IO_IER_PB6_IE_Pos                                           (22UL)   /*!<SYSCFG IO_IER: PB6_IE (Bit 22) */
4370 #define SYSCFG_IO_IER_PB6_IE_Msk                                           (0x400000UL)   /*!< SYSCFG IO_IER: PB6_IE (Bitfield-Mask: 0x01) */
4371 #define SYSCFG_IO_IER_PB6_IE                                               SYSCFG_IO_IER_PB6_IE_Msk
4372 #define SYSCFG_IO_IER_PB5_IE_Pos                                           (21UL)   /*!<SYSCFG IO_IER: PB5_IE (Bit 21) */
4373 #define SYSCFG_IO_IER_PB5_IE_Msk                                           (0x200000UL)   /*!< SYSCFG IO_IER: PB5_IE (Bitfield-Mask: 0x01) */
4374 #define SYSCFG_IO_IER_PB5_IE                                               SYSCFG_IO_IER_PB5_IE_Msk
4375 #define SYSCFG_IO_IER_PB4_IE_Pos                                           (20UL)   /*!<SYSCFG IO_IER: PB4_IE (Bit 20) */
4376 #define SYSCFG_IO_IER_PB4_IE_Msk                                           (0x100000UL)   /*!< SYSCFG IO_IER: PB4_IE (Bitfield-Mask: 0x01) */
4377 #define SYSCFG_IO_IER_PB4_IE                                               SYSCFG_IO_IER_PB4_IE_Msk
4378 #define SYSCFG_IO_IER_PB3_IE_Pos                                           (19UL)   /*!<SYSCFG IO_IER: PB3_IE (Bit 19) */
4379 #define SYSCFG_IO_IER_PB3_IE_Msk                                           (0x80000UL)    /*!< SYSCFG IO_IER: PB3_IE (Bitfield-Mask: 0x01) */
4380 #define SYSCFG_IO_IER_PB3_IE                                               SYSCFG_IO_IER_PB3_IE_Msk
4381 #define SYSCFG_IO_IER_PB2_IE_Pos                                           (18UL)   /*!<SYSCFG IO_IER: PB2_IE (Bit 18) */
4382 #define SYSCFG_IO_IER_PB2_IE_Msk                                           (0x40000UL)    /*!< SYSCFG IO_IER: PB2_IE (Bitfield-Mask: 0x01) */
4383 #define SYSCFG_IO_IER_PB2_IE                                               SYSCFG_IO_IER_PB2_IE_Msk
4384 #define SYSCFG_IO_IER_PB1_IE_Pos                                           (17UL)   /*!<SYSCFG IO_IER: PB1_IE (Bit 17) */
4385 #define SYSCFG_IO_IER_PB1_IE_Msk                                           (0x20000UL)    /*!< SYSCFG IO_IER: PB1_IE (Bitfield-Mask: 0x01) */
4386 #define SYSCFG_IO_IER_PB1_IE                                               SYSCFG_IO_IER_PB1_IE_Msk
4387 #define SYSCFG_IO_IER_PB0_IE_Pos                                           (16UL)   /*!<SYSCFG IO_IER: PB0_IE (Bit 16) */
4388 #define SYSCFG_IO_IER_PB0_IE_Msk                                           (0x10000UL)    /*!< SYSCFG IO_IER: PB0_IE (Bitfield-Mask: 0x01) */
4389 #define SYSCFG_IO_IER_PB0_IE                                               SYSCFG_IO_IER_PB0_IE_Msk
4390 #define SYSCFG_IO_IER_PA15_IE_Pos                                          (15UL)   /*!<SYSCFG IO_IER: PA15_IE (Bit 15) */
4391 #define SYSCFG_IO_IER_PA15_IE_Msk                                          (0x8000UL)   /*!< SYSCFG IO_IER: PA15_IE (Bitfield-Mask: 0x01) */
4392 #define SYSCFG_IO_IER_PA15_IE                                              SYSCFG_IO_IER_PA15_IE_Msk
4393 #define SYSCFG_IO_IER_PA14_IE_Pos                                          (14UL)   /*!<SYSCFG IO_IER: PA14_IE (Bit 14) */
4394 #define SYSCFG_IO_IER_PA14_IE_Msk                                          (0x4000UL)   /*!< SYSCFG IO_IER: PA14_IE (Bitfield-Mask: 0x01) */
4395 #define SYSCFG_IO_IER_PA14_IE                                              SYSCFG_IO_IER_PA14_IE_Msk
4396 #define SYSCFG_IO_IER_PA13_IE_Pos                                          (13UL)   /*!<SYSCFG IO_IER: PA13_IE (Bit 13) */
4397 #define SYSCFG_IO_IER_PA13_IE_Msk                                          (0x2000UL)   /*!< SYSCFG IO_IER: PA13_IE (Bitfield-Mask: 0x01) */
4398 #define SYSCFG_IO_IER_PA13_IE                                              SYSCFG_IO_IER_PA13_IE_Msk
4399 #define SYSCFG_IO_IER_PA12_IE_Pos                                          (12UL)   /*!<SYSCFG IO_IER: PA12_IE (Bit 12) */
4400 #define SYSCFG_IO_IER_PA12_IE_Msk                                          (0x1000UL)   /*!< SYSCFG IO_IER: PA12_IE (Bitfield-Mask: 0x01) */
4401 #define SYSCFG_IO_IER_PA12_IE                                              SYSCFG_IO_IER_PA12_IE_Msk
4402 #define SYSCFG_IO_IER_PA11_IE_Pos                                          (11UL)   /*!<SYSCFG IO_IER: PA11_IE (Bit 11) */
4403 #define SYSCFG_IO_IER_PA11_IE_Msk                                          (0x800UL)    /*!< SYSCFG IO_IER: PA11_IE (Bitfield-Mask: 0x01) */
4404 #define SYSCFG_IO_IER_PA11_IE                                              SYSCFG_IO_IER_PA11_IE_Msk
4405 #define SYSCFG_IO_IER_PA10_IE_Pos                                          (10UL)   /*!<SYSCFG IO_IER: PA10_IE (Bit 10) */
4406 #define SYSCFG_IO_IER_PA10_IE_Msk                                          (0x400UL)    /*!< SYSCFG IO_IER: PA10_IE (Bitfield-Mask: 0x01) */
4407 #define SYSCFG_IO_IER_PA10_IE                                              SYSCFG_IO_IER_PA10_IE_Msk
4408 #define SYSCFG_IO_IER_PA9_IE_Pos                                           (9UL)    /*!<SYSCFG IO_IER: PA9_IE (Bit 9) */
4409 #define SYSCFG_IO_IER_PA9_IE_Msk                                           (0x200UL)    /*!< SYSCFG IO_IER: PA9_IE (Bitfield-Mask: 0x01) */
4410 #define SYSCFG_IO_IER_PA9_IE                                               SYSCFG_IO_IER_PA9_IE_Msk
4411 #define SYSCFG_IO_IER_PA8_IE_Pos                                           (8UL)    /*!<SYSCFG IO_IER: PA8_IE (Bit 8) */
4412 #define SYSCFG_IO_IER_PA8_IE_Msk                                           (0x100UL)    /*!< SYSCFG IO_IER: PA8_IE (Bitfield-Mask: 0x01) */
4413 #define SYSCFG_IO_IER_PA8_IE                                               SYSCFG_IO_IER_PA8_IE_Msk
4414 #define SYSCFG_IO_IER_PA7_IE_Pos                                           (7UL)    /*!<SYSCFG IO_IER: PA7_IE (Bit 7) */
4415 #define SYSCFG_IO_IER_PA7_IE_Msk                                           (0x80UL)   /*!< SYSCFG IO_IER: PA7_IE (Bitfield-Mask: 0x01) */
4416 #define SYSCFG_IO_IER_PA7_IE                                               SYSCFG_IO_IER_PA7_IE_Msk
4417 #define SYSCFG_IO_IER_PA6_IE_Pos                                           (6UL)    /*!<SYSCFG IO_IER: PA6_IE (Bit 6) */
4418 #define SYSCFG_IO_IER_PA6_IE_Msk                                           (0x40UL)   /*!< SYSCFG IO_IER: PA6_IE (Bitfield-Mask: 0x01) */
4419 #define SYSCFG_IO_IER_PA6_IE                                               SYSCFG_IO_IER_PA6_IE_Msk
4420 #define SYSCFG_IO_IER_PA5_IE_Pos                                           (5UL)    /*!<SYSCFG IO_IER: PA5_IE (Bit 5) */
4421 #define SYSCFG_IO_IER_PA5_IE_Msk                                           (0x20UL)   /*!< SYSCFG IO_IER: PA5_IE (Bitfield-Mask: 0x01) */
4422 #define SYSCFG_IO_IER_PA5_IE                                               SYSCFG_IO_IER_PA5_IE_Msk
4423 #define SYSCFG_IO_IER_PA4_IE_Pos                                           (4UL)    /*!<SYSCFG IO_IER: PA4_IE (Bit 4) */
4424 #define SYSCFG_IO_IER_PA4_IE_Msk                                           (0x10UL)   /*!< SYSCFG IO_IER: PA4_IE (Bitfield-Mask: 0x01) */
4425 #define SYSCFG_IO_IER_PA4_IE                                               SYSCFG_IO_IER_PA4_IE_Msk
4426 #define SYSCFG_IO_IER_PA3_IE_Pos                                           (3UL)    /*!<SYSCFG IO_IER: PA3_IE (Bit 3) */
4427 #define SYSCFG_IO_IER_PA3_IE_Msk                                           (0x8UL)    /*!< SYSCFG IO_IER: PA3_IE (Bitfield-Mask: 0x01) */
4428 #define SYSCFG_IO_IER_PA3_IE                                               SYSCFG_IO_IER_PA3_IE_Msk
4429 #define SYSCFG_IO_IER_PA2_IE_Pos                                           (2UL)    /*!<SYSCFG IO_IER: PA2_IE (Bit 2) */
4430 #define SYSCFG_IO_IER_PA2_IE_Msk                                           (0x4UL)    /*!< SYSCFG IO_IER: PA2_IE (Bitfield-Mask: 0x01) */
4431 #define SYSCFG_IO_IER_PA2_IE                                               SYSCFG_IO_IER_PA2_IE_Msk
4432 #define SYSCFG_IO_IER_PA1_IE_Pos                                           (1UL)    /*!<SYSCFG IO_IER: PA1_IE (Bit 1) */
4433 #define SYSCFG_IO_IER_PA1_IE_Msk                                           (0x2UL)    /*!< SYSCFG IO_IER: PA1_IE (Bitfield-Mask: 0x01) */
4434 #define SYSCFG_IO_IER_PA1_IE                                               SYSCFG_IO_IER_PA1_IE_Msk
4435 #define SYSCFG_IO_IER_PA0_IE_Pos                                           (0UL)    /*!<SYSCFG IO_IER: PA0_IE (Bit 0) */
4436 #define SYSCFG_IO_IER_PA0_IE_Msk                                           (0x1UL)    /*!< SYSCFG IO_IER: PA0_IE (Bitfield-Mask: 0x01) */
4437 #define SYSCFG_IO_IER_PA0_IE                                               SYSCFG_IO_IER_PA0_IE_Msk
4438 
4439 /* =====================================================    IO_ISCR    ===================================================== */
4440 #define SYSCFG_IO_ISCR_PB15_ISC_Pos                                        (31UL)   /*!<SYSCFG IO_ISCR: PB15_ISC (Bit 31) */
4441 #define SYSCFG_IO_ISCR_PB15_ISC_Msk                                        (0x80000000UL)   /*!< SYSCFG IO_ISCR: PB15_ISC (Bitfield-Mask: 0x01) */
4442 #define SYSCFG_IO_ISCR_PB15_ISC                                            SYSCFG_IO_ISCR_PB15_ISC_Msk
4443 #define SYSCFG_IO_ISCR_PB14_ISC_Pos                                        (30UL)   /*!<SYSCFG IO_ISCR: PB14_ISC (Bit 30) */
4444 #define SYSCFG_IO_ISCR_PB14_ISC_Msk                                        (0x40000000UL)   /*!< SYSCFG IO_ISCR: PB14_ISC (Bitfield-Mask: 0x01) */
4445 #define SYSCFG_IO_ISCR_PB14_ISC                                            SYSCFG_IO_ISCR_PB14_ISC_Msk
4446 #define SYSCFG_IO_ISCR_PB13_ISC_Pos                                        (29UL)   /*!<SYSCFG IO_ISCR: PB13_ISC (Bit 29) */
4447 #define SYSCFG_IO_ISCR_PB13_ISC_Msk                                        (0x20000000UL)   /*!< SYSCFG IO_ISCR: PB13_ISC (Bitfield-Mask: 0x01) */
4448 #define SYSCFG_IO_ISCR_PB13_ISC                                            SYSCFG_IO_ISCR_PB13_ISC_Msk
4449 #define SYSCFG_IO_ISCR_PB12_ISC_Pos                                        (28UL)   /*!<SYSCFG IO_ISCR: PB12_ISC (Bit 28) */
4450 #define SYSCFG_IO_ISCR_PB12_ISC_Msk                                        (0x10000000UL)   /*!< SYSCFG IO_ISCR: PB12_ISC (Bitfield-Mask: 0x01) */
4451 #define SYSCFG_IO_ISCR_PB12_ISC                                            SYSCFG_IO_ISCR_PB12_ISC_Msk
4452 #define SYSCFG_IO_ISCR_PB11_ISC_Pos                                        (27UL)   /*!<SYSCFG IO_ISCR: PB11_ISC (Bit 27) */
4453 #define SYSCFG_IO_ISCR_PB11_ISC_Msk                                        (0x8000000UL)    /*!< SYSCFG IO_ISCR: PB11_ISC (Bitfield-Mask: 0x01) */
4454 #define SYSCFG_IO_ISCR_PB11_ISC                                            SYSCFG_IO_ISCR_PB11_ISC_Msk
4455 #define SYSCFG_IO_ISCR_PB10_ISC_Pos                                        (26UL)   /*!<SYSCFG IO_ISCR: PB10_ISC (Bit 26) */
4456 #define SYSCFG_IO_ISCR_PB10_ISC_Msk                                        (0x4000000UL)    /*!< SYSCFG IO_ISCR: PB10_ISC (Bitfield-Mask: 0x01) */
4457 #define SYSCFG_IO_ISCR_PB10_ISC                                            SYSCFG_IO_ISCR_PB10_ISC_Msk
4458 #define SYSCFG_IO_ISCR_PB9_ISC_Pos                                         (25UL)   /*!<SYSCFG IO_ISCR: PB9_ISC (Bit 25) */
4459 #define SYSCFG_IO_ISCR_PB9_ISC_Msk                                         (0x2000000UL)    /*!< SYSCFG IO_ISCR: PB9_ISC (Bitfield-Mask: 0x01) */
4460 #define SYSCFG_IO_ISCR_PB9_ISC                                             SYSCFG_IO_ISCR_PB9_ISC_Msk
4461 #define SYSCFG_IO_ISCR_PB8_ISC_Pos                                         (24UL)   /*!<SYSCFG IO_ISCR: PB8_ISC (Bit 24) */
4462 #define SYSCFG_IO_ISCR_PB8_ISC_Msk                                         (0x1000000UL)    /*!< SYSCFG IO_ISCR: PB8_ISC (Bitfield-Mask: 0x01) */
4463 #define SYSCFG_IO_ISCR_PB8_ISC                                             SYSCFG_IO_ISCR_PB8_ISC_Msk
4464 #define SYSCFG_IO_ISCR_PB7_ISC_Pos                                         (23UL)   /*!<SYSCFG IO_ISCR: PB7_ISC (Bit 23) */
4465 #define SYSCFG_IO_ISCR_PB7_ISC_Msk                                         (0x800000UL)   /*!< SYSCFG IO_ISCR: PB7_ISC (Bitfield-Mask: 0x01) */
4466 #define SYSCFG_IO_ISCR_PB7_ISC                                             SYSCFG_IO_ISCR_PB7_ISC_Msk
4467 #define SYSCFG_IO_ISCR_PB6_ISC_Pos                                         (22UL)   /*!<SYSCFG IO_ISCR: PB6_ISC (Bit 22) */
4468 #define SYSCFG_IO_ISCR_PB6_ISC_Msk                                         (0x400000UL)   /*!< SYSCFG IO_ISCR: PB6_ISC (Bitfield-Mask: 0x01) */
4469 #define SYSCFG_IO_ISCR_PB6_ISC                                             SYSCFG_IO_ISCR_PB6_ISC_Msk
4470 #define SYSCFG_IO_ISCR_PB5_ISC_Pos                                         (21UL)   /*!<SYSCFG IO_ISCR: PB5_ISC (Bit 21) */
4471 #define SYSCFG_IO_ISCR_PB5_ISC_Msk                                         (0x200000UL)   /*!< SYSCFG IO_ISCR: PB5_ISC (Bitfield-Mask: 0x01) */
4472 #define SYSCFG_IO_ISCR_PB5_ISC                                             SYSCFG_IO_ISCR_PB5_ISC_Msk
4473 #define SYSCFG_IO_ISCR_PB4_ISC_Pos                                         (20UL)   /*!<SYSCFG IO_ISCR: PB4_ISC (Bit 20) */
4474 #define SYSCFG_IO_ISCR_PB4_ISC_Msk                                         (0x100000UL)   /*!< SYSCFG IO_ISCR: PB4_ISC (Bitfield-Mask: 0x01) */
4475 #define SYSCFG_IO_ISCR_PB4_ISC                                             SYSCFG_IO_ISCR_PB4_ISC_Msk
4476 #define SYSCFG_IO_ISCR_PB3_ISC_Pos                                         (19UL)   /*!<SYSCFG IO_ISCR: PB3_ISC (Bit 19) */
4477 #define SYSCFG_IO_ISCR_PB3_ISC_Msk                                         (0x80000UL)    /*!< SYSCFG IO_ISCR: PB3_ISC (Bitfield-Mask: 0x01) */
4478 #define SYSCFG_IO_ISCR_PB3_ISC                                             SYSCFG_IO_ISCR_PB3_ISC_Msk
4479 #define SYSCFG_IO_ISCR_PB2_ISC_Pos                                         (18UL)   /*!<SYSCFG IO_ISCR: PB2_ISC (Bit 18) */
4480 #define SYSCFG_IO_ISCR_PB2_ISC_Msk                                         (0x40000UL)    /*!< SYSCFG IO_ISCR: PB2_ISC (Bitfield-Mask: 0x01) */
4481 #define SYSCFG_IO_ISCR_PB2_ISC                                             SYSCFG_IO_ISCR_PB2_ISC_Msk
4482 #define SYSCFG_IO_ISCR_PB1_ISC_Pos                                         (17UL)   /*!<SYSCFG IO_ISCR: PB1_ISC (Bit 17) */
4483 #define SYSCFG_IO_ISCR_PB1_ISC_Msk                                         (0x20000UL)    /*!< SYSCFG IO_ISCR: PB1_ISC (Bitfield-Mask: 0x01) */
4484 #define SYSCFG_IO_ISCR_PB1_ISC                                             SYSCFG_IO_ISCR_PB1_ISC_Msk
4485 #define SYSCFG_IO_ISCR_PB0_ISC_Pos                                         (16UL)   /*!<SYSCFG IO_ISCR: PB0_ISC (Bit 16) */
4486 #define SYSCFG_IO_ISCR_PB0_ISC_Msk                                         (0x10000UL)    /*!< SYSCFG IO_ISCR: PB0_ISC (Bitfield-Mask: 0x01) */
4487 #define SYSCFG_IO_ISCR_PB0_ISC                                             SYSCFG_IO_ISCR_PB0_ISC_Msk
4488 #define SYSCFG_IO_ISCR_PA15_ISC_Pos                                        (15UL)   /*!<SYSCFG IO_ISCR: PA15_ISC (Bit 15) */
4489 #define SYSCFG_IO_ISCR_PA15_ISC_Msk                                        (0x8000UL)   /*!< SYSCFG IO_ISCR: PA15_ISC (Bitfield-Mask: 0x01) */
4490 #define SYSCFG_IO_ISCR_PA15_ISC                                            SYSCFG_IO_ISCR_PA15_ISC_Msk
4491 #define SYSCFG_IO_ISCR_PA14_ISC_Pos                                        (14UL)   /*!<SYSCFG IO_ISCR: PA14_ISC (Bit 14) */
4492 #define SYSCFG_IO_ISCR_PA14_ISC_Msk                                        (0x4000UL)   /*!< SYSCFG IO_ISCR: PA14_ISC (Bitfield-Mask: 0x01) */
4493 #define SYSCFG_IO_ISCR_PA14_ISC                                            SYSCFG_IO_ISCR_PA14_ISC_Msk
4494 #define SYSCFG_IO_ISCR_PA13_ISC_Pos                                        (13UL)   /*!<SYSCFG IO_ISCR: PA13_ISC (Bit 13) */
4495 #define SYSCFG_IO_ISCR_PA13_ISC_Msk                                        (0x2000UL)   /*!< SYSCFG IO_ISCR: PA13_ISC (Bitfield-Mask: 0x01) */
4496 #define SYSCFG_IO_ISCR_PA13_ISC                                            SYSCFG_IO_ISCR_PA13_ISC_Msk
4497 #define SYSCFG_IO_ISCR_PA12_ISC_Pos                                        (12UL)   /*!<SYSCFG IO_ISCR: PA12_ISC (Bit 12) */
4498 #define SYSCFG_IO_ISCR_PA12_ISC_Msk                                        (0x1000UL)   /*!< SYSCFG IO_ISCR: PA12_ISC (Bitfield-Mask: 0x01) */
4499 #define SYSCFG_IO_ISCR_PA12_ISC                                            SYSCFG_IO_ISCR_PA12_ISC_Msk
4500 #define SYSCFG_IO_ISCR_PA11_ISC_Pos                                        (11UL)   /*!<SYSCFG IO_ISCR: PA11_ISC (Bit 11) */
4501 #define SYSCFG_IO_ISCR_PA11_ISC_Msk                                        (0x800UL)    /*!< SYSCFG IO_ISCR: PA11_ISC (Bitfield-Mask: 0x01) */
4502 #define SYSCFG_IO_ISCR_PA11_ISC                                            SYSCFG_IO_ISCR_PA11_ISC_Msk
4503 #define SYSCFG_IO_ISCR_PA10_ISC_Pos                                        (10UL)   /*!<SYSCFG IO_ISCR: PA10_ISC (Bit 10) */
4504 #define SYSCFG_IO_ISCR_PA10_ISC_Msk                                        (0x400UL)    /*!< SYSCFG IO_ISCR: PA10_ISC (Bitfield-Mask: 0x01) */
4505 #define SYSCFG_IO_ISCR_PA10_ISC                                            SYSCFG_IO_ISCR_PA10_ISC_Msk
4506 #define SYSCFG_IO_ISCR_PA9_ISC_Pos                                         (9UL)    /*!<SYSCFG IO_ISCR: PA9_ISC (Bit 9) */
4507 #define SYSCFG_IO_ISCR_PA9_ISC_Msk                                         (0x200UL)    /*!< SYSCFG IO_ISCR: PA9_ISC (Bitfield-Mask: 0x01) */
4508 #define SYSCFG_IO_ISCR_PA9_ISC                                             SYSCFG_IO_ISCR_PA9_ISC_Msk
4509 #define SYSCFG_IO_ISCR_PA8_ISC_Pos                                         (8UL)    /*!<SYSCFG IO_ISCR: PA8_ISC (Bit 8) */
4510 #define SYSCFG_IO_ISCR_PA8_ISC_Msk                                         (0x100UL)    /*!< SYSCFG IO_ISCR: PA8_ISC (Bitfield-Mask: 0x01) */
4511 #define SYSCFG_IO_ISCR_PA8_ISC                                             SYSCFG_IO_ISCR_PA8_ISC_Msk
4512 #define SYSCFG_IO_ISCR_PA7_ISC_Pos                                         (7UL)    /*!<SYSCFG IO_ISCR: PA7_ISC (Bit 7) */
4513 #define SYSCFG_IO_ISCR_PA7_ISC_Msk                                         (0x80UL)   /*!< SYSCFG IO_ISCR: PA7_ISC (Bitfield-Mask: 0x01) */
4514 #define SYSCFG_IO_ISCR_PA7_ISC                                             SYSCFG_IO_ISCR_PA7_ISC_Msk
4515 #define SYSCFG_IO_ISCR_PA6_ISC_Pos                                         (6UL)    /*!<SYSCFG IO_ISCR: PA6_ISC (Bit 6) */
4516 #define SYSCFG_IO_ISCR_PA6_ISC_Msk                                         (0x40UL)   /*!< SYSCFG IO_ISCR: PA6_ISC (Bitfield-Mask: 0x01) */
4517 #define SYSCFG_IO_ISCR_PA6_ISC                                             SYSCFG_IO_ISCR_PA6_ISC_Msk
4518 #define SYSCFG_IO_ISCR_PA5_ISC_Pos                                         (5UL)    /*!<SYSCFG IO_ISCR: PA5_ISC (Bit 5) */
4519 #define SYSCFG_IO_ISCR_PA5_ISC_Msk                                         (0x20UL)   /*!< SYSCFG IO_ISCR: PA5_ISC (Bitfield-Mask: 0x01) */
4520 #define SYSCFG_IO_ISCR_PA5_ISC                                             SYSCFG_IO_ISCR_PA5_ISC_Msk
4521 #define SYSCFG_IO_ISCR_PA4_ISC_Pos                                         (4UL)    /*!<SYSCFG IO_ISCR: PA4_ISC (Bit 4) */
4522 #define SYSCFG_IO_ISCR_PA4_ISC_Msk                                         (0x10UL)   /*!< SYSCFG IO_ISCR: PA4_ISC (Bitfield-Mask: 0x01) */
4523 #define SYSCFG_IO_ISCR_PA4_ISC                                             SYSCFG_IO_ISCR_PA4_ISC_Msk
4524 #define SYSCFG_IO_ISCR_PA3_ISC_Pos                                         (3UL)    /*!<SYSCFG IO_ISCR: PA3_ISC (Bit 3) */
4525 #define SYSCFG_IO_ISCR_PA3_ISC_Msk                                         (0x8UL)    /*!< SYSCFG IO_ISCR: PA3_ISC (Bitfield-Mask: 0x01) */
4526 #define SYSCFG_IO_ISCR_PA3_ISC                                             SYSCFG_IO_ISCR_PA3_ISC_Msk
4527 #define SYSCFG_IO_ISCR_PA2_ISC_Pos                                         (2UL)    /*!<SYSCFG IO_ISCR: PA2_ISC (Bit 2) */
4528 #define SYSCFG_IO_ISCR_PA2_ISC_Msk                                         (0x4UL)    /*!< SYSCFG IO_ISCR: PA2_ISC (Bitfield-Mask: 0x01) */
4529 #define SYSCFG_IO_ISCR_PA2_ISC                                             SYSCFG_IO_ISCR_PA2_ISC_Msk
4530 #define SYSCFG_IO_ISCR_PA1_ISC_Pos                                         (1UL)    /*!<SYSCFG IO_ISCR: PA1_ISC (Bit 1) */
4531 #define SYSCFG_IO_ISCR_PA1_ISC_Msk                                         (0x2UL)    /*!< SYSCFG IO_ISCR: PA1_ISC (Bitfield-Mask: 0x01) */
4532 #define SYSCFG_IO_ISCR_PA1_ISC                                             SYSCFG_IO_ISCR_PA1_ISC_Msk
4533 #define SYSCFG_IO_ISCR_PA0_ISC_Pos                                         (0UL)    /*!<SYSCFG IO_ISCR: PA0_ISC (Bit 0) */
4534 #define SYSCFG_IO_ISCR_PA0_ISC_Msk                                         (0x1UL)    /*!< SYSCFG IO_ISCR: PA0_ISC (Bitfield-Mask: 0x01) */
4535 #define SYSCFG_IO_ISCR_PA0_ISC                                             SYSCFG_IO_ISCR_PA0_ISC_Msk
4536 
4537 /* =====================================================    PWRC_IER    ===================================================== */
4538 #define SYSCFG_PWRC_IER_WKUP_IE_Pos                                        (2UL)    /*!<SYSCFG PWRC_IER: WKUP_IE (Bit 2) */
4539 #define SYSCFG_PWRC_IER_WKUP_IE_Msk                                        (0x4UL)    /*!< SYSCFG PWRC_IER: WKUP_IE (Bitfield-Mask: 0x01) */
4540 #define SYSCFG_PWRC_IER_WKUP_IE                                            SYSCFG_PWRC_IER_WKUP_IE_Msk
4541 #define SYSCFG_PWRC_IER_PVD_IE_Pos                                         (1UL)    /*!<SYSCFG PWRC_IER: PVD_IE (Bit 1) */
4542 #define SYSCFG_PWRC_IER_PVD_IE_Msk                                         (0x2UL)    /*!< SYSCFG PWRC_IER: PVD_IE (Bitfield-Mask: 0x01) */
4543 #define SYSCFG_PWRC_IER_PVD_IE                                             SYSCFG_PWRC_IER_PVD_IE_Msk
4544 
4545 /* =====================================================    PWRC_ISCR    ===================================================== */
4546 #define SYSCFG_PWRC_ISCR_WKUP_ISC_Pos                                      (2UL)    /*!<SYSCFG PWRC_ISCR: WKUP_ISC (Bit 2) */
4547 #define SYSCFG_PWRC_ISCR_WKUP_ISC_Msk                                      (0x4UL)    /*!< SYSCFG PWRC_ISCR: WKUP_ISC (Bitfield-Mask: 0x01) */
4548 #define SYSCFG_PWRC_ISCR_WKUP_ISC                                          SYSCFG_PWRC_ISCR_WKUP_ISC_Msk
4549 #define SYSCFG_PWRC_ISCR_PVD_ISC_Pos                                       (1UL)    /*!<SYSCFG PWRC_ISCR: PVD_ISC (Bit 1) */
4550 #define SYSCFG_PWRC_ISCR_PVD_ISC_Msk                                       (0x2UL)    /*!< SYSCFG PWRC_ISCR: PVD_ISC (Bitfield-Mask: 0x01) */
4551 #define SYSCFG_PWRC_ISCR_PVD_ISC                                           SYSCFG_PWRC_ISCR_PVD_ISC_Msk
4552 
4553 /* =====================================================    BLERXTX_DTR    ===================================================== */
4554 #define SYSCFG_BLERXTX_DTR_RX_DT_Pos                                       (1UL)    /*!<SYSCFG BLERXTX_DTR: RX_DT (Bit 1) */
4555 #define SYSCFG_BLERXTX_DTR_RX_DT_Msk                                       (0x2UL)    /*!< SYSCFG BLERXTX_DTR: RX_DT (Bitfield-Mask: 0x01) */
4556 #define SYSCFG_BLERXTX_DTR_RX_DT                                           SYSCFG_BLERXTX_DTR_RX_DT_Msk
4557 #define SYSCFG_BLERXTX_DTR_TX_DT_Pos                                       (0UL)    /*!<SYSCFG BLERXTX_DTR: TX_DT (Bit 0) */
4558 #define SYSCFG_BLERXTX_DTR_TX_DT_Msk                                       (0x1UL)    /*!< SYSCFG BLERXTX_DTR: TX_DT (Bitfield-Mask: 0x01) */
4559 #define SYSCFG_BLERXTX_DTR_TX_DT                                           SYSCFG_BLERXTX_DTR_TX_DT_Msk
4560 
4561 /* =====================================================    BLERXTX_IBER    ===================================================== */
4562 #define SYSCFG_BLERXTX_IBER_RX_IBE_Pos                                     (1UL)    /*!<SYSCFG BLERXTX_IBER: RX_IBE (Bit 1) */
4563 #define SYSCFG_BLERXTX_IBER_RX_IBE_Msk                                     (0x2UL)    /*!< SYSCFG BLERXTX_IBER: RX_IBE (Bitfield-Mask: 0x01) */
4564 #define SYSCFG_BLERXTX_IBER_RX_IBE                                         SYSCFG_BLERXTX_IBER_RX_IBE_Msk
4565 #define SYSCFG_BLERXTX_IBER_TX_IBE_Pos                                     (0UL)    /*!<SYSCFG BLERXTX_IBER: TX_IBE (Bit 0) */
4566 #define SYSCFG_BLERXTX_IBER_TX_IBE_Msk                                     (0x1UL)    /*!< SYSCFG BLERXTX_IBER: TX_IBE (Bitfield-Mask: 0x01) */
4567 #define SYSCFG_BLERXTX_IBER_TX_IBE                                         SYSCFG_BLERXTX_IBER_TX_IBE_Msk
4568 
4569 /* =====================================================    BLERXTX_IEVR    ===================================================== */
4570 #define SYSCFG_BLERXTX_IEVR_RX_IEV_Pos                                     (1UL)    /*!<SYSCFG BLERXTX_IEVR: RX_IEV (Bit 1) */
4571 #define SYSCFG_BLERXTX_IEVR_RX_IEV_Msk                                     (0x2UL)    /*!< SYSCFG BLERXTX_IEVR: RX_IEV (Bitfield-Mask: 0x01) */
4572 #define SYSCFG_BLERXTX_IEVR_RX_IEV                                         SYSCFG_BLERXTX_IEVR_RX_IEV_Msk
4573 #define SYSCFG_BLERXTX_IEVR_TX_IEV_Pos                                     (0UL)    /*!<SYSCFG BLERXTX_IEVR: TX_IEV (Bit 0) */
4574 #define SYSCFG_BLERXTX_IEVR_TX_IEV_Msk                                     (0x1UL)    /*!< SYSCFG BLERXTX_IEVR: TX_IEV (Bitfield-Mask: 0x01) */
4575 #define SYSCFG_BLERXTX_IEVR_TX_IEV                                         SYSCFG_BLERXTX_IEVR_TX_IEV_Msk
4576 
4577 /* =====================================================    BLERXTX_IER    ===================================================== */
4578 #define SYSCFG_BLERXTX_IER_RX_IE_Pos                                       (1UL)    /*!<SYSCFG BLERXTX_IER: RX_IE (Bit 1) */
4579 #define SYSCFG_BLERXTX_IER_RX_IE_Msk                                       (0x2UL)    /*!< SYSCFG BLERXTX_IER: RX_IE (Bitfield-Mask: 0x01) */
4580 #define SYSCFG_BLERXTX_IER_RX_IE                                           SYSCFG_BLERXTX_IER_RX_IE_Msk
4581 #define SYSCFG_BLERXTX_IER_TX_IE_Pos                                       (0UL)    /*!<SYSCFG BLERXTX_IER: TX_IE (Bit 0) */
4582 #define SYSCFG_BLERXTX_IER_TX_IE_Msk                                       (0x1UL)    /*!< SYSCFG BLERXTX_IER: TX_IE (Bitfield-Mask: 0x01) */
4583 #define SYSCFG_BLERXTX_IER_TX_IE                                           SYSCFG_BLERXTX_IER_TX_IE_Msk
4584 
4585 /* =====================================================    BLERXTX_ISCR    ===================================================== */
4586 #define SYSCFG_BLERXTX_ISCR_RX_ISC_Pos                                     (1UL)    /*!<SYSCFG BLERXTX_ISCR: RX_ISC (Bit 1) */
4587 #define SYSCFG_BLERXTX_ISCR_RX_ISC_Msk                                     (0x2UL)    /*!< SYSCFG BLERXTX_ISCR: RX_ISC (Bitfield-Mask: 0x01) */
4588 #define SYSCFG_BLERXTX_ISCR_RX_ISC                                         SYSCFG_BLERXTX_ISCR_RX_ISC_Msk
4589 #define SYSCFG_BLERXTX_ISCR_TX_ISC_Pos                                     (0UL)    /*!<SYSCFG BLERXTX_ISCR: TX_ISC (Bit 0) */
4590 #define SYSCFG_BLERXTX_ISCR_TX_ISC_Msk                                     (0x1UL)    /*!< SYSCFG BLERXTX_ISCR: TX_ISC (Bitfield-Mask: 0x01) */
4591 #define SYSCFG_BLERXTX_ISCR_TX_ISC                                         SYSCFG_BLERXTX_ISCR_TX_ISC_Msk
4592 
4593 
4594 /* =========================================================================================================================== */
4595 /*=====================                                       RNG                                       ===================== */
4596 /* =========================================================================================================================== */
4597 
4598 /* =====================================================    CR    ===================================================== */
4599 #define RNG_CR_TST_CLK_Pos                                                 (3UL)    /*!<RNG CR: TST_CLK (Bit 3) */
4600 #define RNG_CR_TST_CLK_Msk                                                 (0x8UL)    /*!< RNG CR: TST_CLK (Bitfield-Mask: 0x01) */
4601 #define RNG_CR_TST_CLK                                                     RNG_CR_TST_CLK_Msk
4602 #define RNG_CR_RNG_DIS_Pos                                                 (2UL)    /*!<RNG CR: RNG_DIS (Bit 2) */
4603 #define RNG_CR_RNG_DIS_Msk                                                 (0x4UL)    /*!< RNG CR: RNG_DIS (Bitfield-Mask: 0x01) */
4604 #define RNG_CR_RNG_DIS                                                     RNG_CR_RNG_DIS_Msk
4605 
4606 /* =====================================================    SR    ===================================================== */
4607 #define RNG_SR_FAULT_Pos                                                   (2UL)    /*!<RNG SR: FAULT (Bit 2) */
4608 #define RNG_SR_FAULT_Msk                                                   (0x4UL)    /*!< RNG SR: FAULT (Bitfield-Mask: 0x01) */
4609 #define RNG_SR_FAULT                                                       RNG_SR_FAULT_Msk
4610 #define RNG_SR_REVCLK_Pos                                                  (1UL)    /*!<RNG SR: REVCLK (Bit 1) */
4611 #define RNG_SR_REVCLK_Msk                                                  (0x2UL)    /*!< RNG SR: REVCLK (Bitfield-Mask: 0x01) */
4612 #define RNG_SR_REVCLK                                                      RNG_SR_REVCLK_Msk
4613 #define RNG_SR_RNGRDY_Pos                                                  (0UL)    /*!<RNG SR: RNGRDY (Bit 0) */
4614 #define RNG_SR_RNGRDY_Msk                                                  (0x1UL)    /*!< RNG SR: RNGRDY (Bitfield-Mask: 0x01) */
4615 #define RNG_SR_RNGRDY                                                      RNG_SR_RNGRDY_Msk
4616 
4617 /* =====================================================    VAL    ===================================================== */
4618 #define RNG_VAL_RANDOM_VALUE_Pos                                           (0UL)    /*!<RNG VAL: RANDOM_VALUE (Bit 0) */
4619 #define RNG_VAL_RANDOM_VALUE_Msk                                           (0xffffUL)   /*!< RNG VAL: RANDOM_VALUE (Bitfield-Mask: 0xffff) */
4620 #define RNG_VAL_RANDOM_VALUE                                               RNG_VAL_RANDOM_VALUE_Msk
4621 #define RNG_VAL_RANDOM_VALUE_0                                             (0x1U << RNG_VAL_RANDOM_VALUE_Pos)
4622 #define RNG_VAL_RANDOM_VALUE_1                                             (0x2U << RNG_VAL_RANDOM_VALUE_Pos)
4623 #define RNG_VAL_RANDOM_VALUE_2                                             (0x4U << RNG_VAL_RANDOM_VALUE_Pos)
4624 #define RNG_VAL_RANDOM_VALUE_3                                             (0x8U << RNG_VAL_RANDOM_VALUE_Pos)
4625 #define RNG_VAL_RANDOM_VALUE_4                                             (0x10U << RNG_VAL_RANDOM_VALUE_Pos)
4626 #define RNG_VAL_RANDOM_VALUE_5                                             (0x20U << RNG_VAL_RANDOM_VALUE_Pos)
4627 #define RNG_VAL_RANDOM_VALUE_6                                             (0x40U << RNG_VAL_RANDOM_VALUE_Pos)
4628 #define RNG_VAL_RANDOM_VALUE_7                                             (0x80U << RNG_VAL_RANDOM_VALUE_Pos)
4629 #define RNG_VAL_RANDOM_VALUE_8                                             (0x100U << RNG_VAL_RANDOM_VALUE_Pos)
4630 #define RNG_VAL_RANDOM_VALUE_9                                             (0x200U << RNG_VAL_RANDOM_VALUE_Pos)
4631 #define RNG_VAL_RANDOM_VALUE_10                                            (0x400U << RNG_VAL_RANDOM_VALUE_Pos)
4632 #define RNG_VAL_RANDOM_VALUE_11                                            (0x800U << RNG_VAL_RANDOM_VALUE_Pos)
4633 #define RNG_VAL_RANDOM_VALUE_12                                            (0x1000U << RNG_VAL_RANDOM_VALUE_Pos)
4634 #define RNG_VAL_RANDOM_VALUE_13                                            (0x2000U << RNG_VAL_RANDOM_VALUE_Pos)
4635 #define RNG_VAL_RANDOM_VALUE_14                                            (0x4000U << RNG_VAL_RANDOM_VALUE_Pos)
4636 #define RNG_VAL_RANDOM_VALUE_15                                            (0x8000U << RNG_VAL_RANDOM_VALUE_Pos)
4637 
4638 
4639 /* =========================================================================================================================== */
4640 /*=====================                                       GPIO                                       ===================== */
4641 /* =========================================================================================================================== */
4642 
4643 /* =====================================================    MODER    ===================================================== */
4644 #define GPIO_MODER_MODE15_Pos                                              (30UL)   /*!<GPIO MODER: MODE15 (Bit 30) */
4645 #define GPIO_MODER_MODE15_Msk                                              (0xc0000000UL)   /*!< GPIO MODER: MODE15 (Bitfield-Mask: 0x03) */
4646 #define GPIO_MODER_MODE15                                                  GPIO_MODER_MODE15_Msk
4647 #define GPIO_MODER_MODE15_0                                                (0x1U << GPIO_MODER_MODE15_Pos)
4648 #define GPIO_MODER_MODE15_1                                                (0x2U << GPIO_MODER_MODE15_Pos)
4649 #define GPIO_MODER_MODE14_Pos                                              (28UL)   /*!<GPIO MODER: MODE14 (Bit 28) */
4650 #define GPIO_MODER_MODE14_Msk                                              (0x30000000UL)   /*!< GPIO MODER: MODE14 (Bitfield-Mask: 0x03) */
4651 #define GPIO_MODER_MODE14                                                  GPIO_MODER_MODE14_Msk
4652 #define GPIO_MODER_MODE14_0                                                (0x1U << GPIO_MODER_MODE14_Pos)
4653 #define GPIO_MODER_MODE14_1                                                (0x2U << GPIO_MODER_MODE14_Pos)
4654 #define GPIO_MODER_MODE13_Pos                                              (26UL)   /*!<GPIO MODER: MODE13 (Bit 26) */
4655 #define GPIO_MODER_MODE13_Msk                                              (0xc000000UL)    /*!< GPIO MODER: MODE13 (Bitfield-Mask: 0x03) */
4656 #define GPIO_MODER_MODE13                                                  GPIO_MODER_MODE13_Msk
4657 #define GPIO_MODER_MODE13_0                                                (0x1U << GPIO_MODER_MODE13_Pos)
4658 #define GPIO_MODER_MODE13_1                                                (0x2U << GPIO_MODER_MODE13_Pos)
4659 #define GPIO_MODER_MODE12_Pos                                              (24UL)   /*!<GPIO MODER: MODE12 (Bit 24) */
4660 #define GPIO_MODER_MODE12_Msk                                              (0x3000000UL)    /*!< GPIO MODER: MODE12 (Bitfield-Mask: 0x03) */
4661 #define GPIO_MODER_MODE12                                                  GPIO_MODER_MODE12_Msk
4662 #define GPIO_MODER_MODE12_0                                                (0x1U << GPIO_MODER_MODE12_Pos)
4663 #define GPIO_MODER_MODE12_1                                                (0x2U << GPIO_MODER_MODE12_Pos)
4664 #define GPIO_MODER_MODE11_Pos                                              (22UL)   /*!<GPIO MODER: MODE11 (Bit 22) */
4665 #define GPIO_MODER_MODE11_Msk                                              (0xc00000UL)   /*!< GPIO MODER: MODE11 (Bitfield-Mask: 0x03) */
4666 #define GPIO_MODER_MODE11                                                  GPIO_MODER_MODE11_Msk
4667 #define GPIO_MODER_MODE11_0                                                (0x1U << GPIO_MODER_MODE11_Pos)
4668 #define GPIO_MODER_MODE11_1                                                (0x2U << GPIO_MODER_MODE11_Pos)
4669 #define GPIO_MODER_MODE10_Pos                                              (20UL)   /*!<GPIO MODER: MODE10 (Bit 20) */
4670 #define GPIO_MODER_MODE10_Msk                                              (0x300000UL)   /*!< GPIO MODER: MODE10 (Bitfield-Mask: 0x03) */
4671 #define GPIO_MODER_MODE10                                                  GPIO_MODER_MODE10_Msk
4672 #define GPIO_MODER_MODE10_0                                                (0x1U << GPIO_MODER_MODE10_Pos)
4673 #define GPIO_MODER_MODE10_1                                                (0x2U << GPIO_MODER_MODE10_Pos)
4674 #define GPIO_MODER_MODE9_Pos                                               (18UL)   /*!<GPIO MODER: MODE9 (Bit 18) */
4675 #define GPIO_MODER_MODE9_Msk                                               (0xc0000UL)    /*!< GPIO MODER: MODE9 (Bitfield-Mask: 0x03) */
4676 #define GPIO_MODER_MODE9                                                   GPIO_MODER_MODE9_Msk
4677 #define GPIO_MODER_MODE9_0                                                 (0x1U << GPIO_MODER_MODE9_Pos)
4678 #define GPIO_MODER_MODE9_1                                                 (0x2U << GPIO_MODER_MODE9_Pos)
4679 #define GPIO_MODER_MODE8_Pos                                               (16UL)   /*!<GPIO MODER: MODE8 (Bit 16) */
4680 #define GPIO_MODER_MODE8_Msk                                               (0x30000UL)    /*!< GPIO MODER: MODE8 (Bitfield-Mask: 0x03) */
4681 #define GPIO_MODER_MODE8                                                   GPIO_MODER_MODE8_Msk
4682 #define GPIO_MODER_MODE8_0                                                 (0x1U << GPIO_MODER_MODE8_Pos)
4683 #define GPIO_MODER_MODE8_1                                                 (0x2U << GPIO_MODER_MODE8_Pos)
4684 #define GPIO_MODER_MODE7_Pos                                               (14UL)   /*!<GPIO MODER: MODE7 (Bit 14) */
4685 #define GPIO_MODER_MODE7_Msk                                               (0xc000UL)   /*!< GPIO MODER: MODE7 (Bitfield-Mask: 0x03) */
4686 #define GPIO_MODER_MODE7                                                   GPIO_MODER_MODE7_Msk
4687 #define GPIO_MODER_MODE7_0                                                 (0x1U << GPIO_MODER_MODE7_Pos)
4688 #define GPIO_MODER_MODE7_1                                                 (0x2U << GPIO_MODER_MODE7_Pos)
4689 #define GPIO_MODER_MODE6_Pos                                               (12UL)   /*!<GPIO MODER: MODE6 (Bit 12) */
4690 #define GPIO_MODER_MODE6_Msk                                               (0x3000UL)   /*!< GPIO MODER: MODE6 (Bitfield-Mask: 0x03) */
4691 #define GPIO_MODER_MODE6                                                   GPIO_MODER_MODE6_Msk
4692 #define GPIO_MODER_MODE6_0                                                 (0x1U << GPIO_MODER_MODE6_Pos)
4693 #define GPIO_MODER_MODE6_1                                                 (0x2U << GPIO_MODER_MODE6_Pos)
4694 #define GPIO_MODER_MODE5_Pos                                               (10UL)   /*!<GPIO MODER: MODE5 (Bit 10) */
4695 #define GPIO_MODER_MODE5_Msk                                               (0xc00UL)    /*!< GPIO MODER: MODE5 (Bitfield-Mask: 0x03) */
4696 #define GPIO_MODER_MODE5                                                   GPIO_MODER_MODE5_Msk
4697 #define GPIO_MODER_MODE5_0                                                 (0x1U << GPIO_MODER_MODE5_Pos)
4698 #define GPIO_MODER_MODE5_1                                                 (0x2U << GPIO_MODER_MODE5_Pos)
4699 #define GPIO_MODER_MODE4_Pos                                               (8UL)    /*!<GPIO MODER: MODE4 (Bit 8) */
4700 #define GPIO_MODER_MODE4_Msk                                               (0x300UL)    /*!< GPIO MODER: MODE4 (Bitfield-Mask: 0x03) */
4701 #define GPIO_MODER_MODE4                                                   GPIO_MODER_MODE4_Msk
4702 #define GPIO_MODER_MODE4_0                                                 (0x1U << GPIO_MODER_MODE4_Pos)
4703 #define GPIO_MODER_MODE4_1                                                 (0x2U << GPIO_MODER_MODE4_Pos)
4704 #define GPIO_MODER_MODE3_Pos                                               (6UL)    /*!<GPIO MODER: MODE3 (Bit 6) */
4705 #define GPIO_MODER_MODE3_Msk                                               (0xc0UL)   /*!< GPIO MODER: MODE3 (Bitfield-Mask: 0x03) */
4706 #define GPIO_MODER_MODE3                                                   GPIO_MODER_MODE3_Msk
4707 #define GPIO_MODER_MODE3_0                                                 (0x1U << GPIO_MODER_MODE3_Pos)
4708 #define GPIO_MODER_MODE3_1                                                 (0x2U << GPIO_MODER_MODE3_Pos)
4709 #define GPIO_MODER_MODE2_Pos                                               (4UL)    /*!<GPIO MODER: MODE2 (Bit 4) */
4710 #define GPIO_MODER_MODE2_Msk                                               (0x30UL)   /*!< GPIO MODER: MODE2 (Bitfield-Mask: 0x03) */
4711 #define GPIO_MODER_MODE2                                                   GPIO_MODER_MODE2_Msk
4712 #define GPIO_MODER_MODE2_0                                                 (0x1U << GPIO_MODER_MODE2_Pos)
4713 #define GPIO_MODER_MODE2_1                                                 (0x2U << GPIO_MODER_MODE2_Pos)
4714 #define GPIO_MODER_MODE1_Pos                                               (2UL)    /*!<GPIO MODER: MODE1 (Bit 2) */
4715 #define GPIO_MODER_MODE1_Msk                                               (0xcUL)    /*!< GPIO MODER: MODE1 (Bitfield-Mask: 0x03) */
4716 #define GPIO_MODER_MODE1                                                   GPIO_MODER_MODE1_Msk
4717 #define GPIO_MODER_MODE1_0                                                 (0x1U << GPIO_MODER_MODE1_Pos)
4718 #define GPIO_MODER_MODE1_1                                                 (0x2U << GPIO_MODER_MODE1_Pos)
4719 #define GPIO_MODER_MODE0_Pos                                               (0UL)    /*!<GPIO MODER: MODE0 (Bit 0) */
4720 #define GPIO_MODER_MODE0_Msk                                               (0x3UL)    /*!< GPIO MODER: MODE0 (Bitfield-Mask: 0x03) */
4721 #define GPIO_MODER_MODE0                                                   GPIO_MODER_MODE0_Msk
4722 #define GPIO_MODER_MODE0_0                                                 (0x1U << GPIO_MODER_MODE0_Pos)
4723 #define GPIO_MODER_MODE0_1                                                 (0x2U << GPIO_MODER_MODE0_Pos)
4724 
4725 /* =====================================================    OTYPER    ===================================================== */
4726 #define GPIO_OTYPER_OT15_Pos                                               (15UL)   /*!<GPIO OTYPER: OT15 (Bit 15) */
4727 #define GPIO_OTYPER_OT15_Msk                                               (0x8000UL)   /*!< GPIO OTYPER: OT15 (Bitfield-Mask: 0x01) */
4728 #define GPIO_OTYPER_OT15                                                   GPIO_OTYPER_OT15_Msk
4729 #define GPIO_OTYPER_OT14_Pos                                               (14UL)   /*!<GPIO OTYPER: OT14 (Bit 14) */
4730 #define GPIO_OTYPER_OT14_Msk                                               (0x4000UL)   /*!< GPIO OTYPER: OT14 (Bitfield-Mask: 0x01) */
4731 #define GPIO_OTYPER_OT14                                                   GPIO_OTYPER_OT14_Msk
4732 #define GPIO_OTYPER_OT13_Pos                                               (13UL)   /*!<GPIO OTYPER: OT13 (Bit 13) */
4733 #define GPIO_OTYPER_OT13_Msk                                               (0x2000UL)   /*!< GPIO OTYPER: OT13 (Bitfield-Mask: 0x01) */
4734 #define GPIO_OTYPER_OT13                                                   GPIO_OTYPER_OT13_Msk
4735 #define GPIO_OTYPER_OT12_Pos                                               (12UL)   /*!<GPIO OTYPER: OT12 (Bit 12) */
4736 #define GPIO_OTYPER_OT12_Msk                                               (0x1000UL)   /*!< GPIO OTYPER: OT12 (Bitfield-Mask: 0x01) */
4737 #define GPIO_OTYPER_OT12                                                   GPIO_OTYPER_OT12_Msk
4738 #define GPIO_OTYPER_OT11_Pos                                               (11UL)   /*!<GPIO OTYPER: OT11 (Bit 11) */
4739 #define GPIO_OTYPER_OT11_Msk                                               (0x800UL)    /*!< GPIO OTYPER: OT11 (Bitfield-Mask: 0x01) */
4740 #define GPIO_OTYPER_OT11                                                   GPIO_OTYPER_OT11_Msk
4741 #define GPIO_OTYPER_OT10_Pos                                               (10UL)   /*!<GPIO OTYPER: OT10 (Bit 10) */
4742 #define GPIO_OTYPER_OT10_Msk                                               (0x400UL)    /*!< GPIO OTYPER: OT10 (Bitfield-Mask: 0x01) */
4743 #define GPIO_OTYPER_OT10                                                   GPIO_OTYPER_OT10_Msk
4744 #define GPIO_OTYPER_OT9_Pos                                                (9UL)    /*!<GPIO OTYPER: OT9 (Bit 9) */
4745 #define GPIO_OTYPER_OT9_Msk                                                (0x200UL)    /*!< GPIO OTYPER: OT9 (Bitfield-Mask: 0x01) */
4746 #define GPIO_OTYPER_OT9                                                    GPIO_OTYPER_OT9_Msk
4747 #define GPIO_OTYPER_OT8_Pos                                                (8UL)    /*!<GPIO OTYPER: OT8 (Bit 8) */
4748 #define GPIO_OTYPER_OT8_Msk                                                (0x100UL)    /*!< GPIO OTYPER: OT8 (Bitfield-Mask: 0x01) */
4749 #define GPIO_OTYPER_OT8                                                    GPIO_OTYPER_OT8_Msk
4750 #define GPIO_OTYPER_OT7_Pos                                                (7UL)    /*!<GPIO OTYPER: OT7 (Bit 7) */
4751 #define GPIO_OTYPER_OT7_Msk                                                (0x80UL)   /*!< GPIO OTYPER: OT7 (Bitfield-Mask: 0x01) */
4752 #define GPIO_OTYPER_OT7                                                    GPIO_OTYPER_OT7_Msk
4753 #define GPIO_OTYPER_OT6_Pos                                                (6UL)    /*!<GPIO OTYPER: OT6 (Bit 6) */
4754 #define GPIO_OTYPER_OT6_Msk                                                (0x40UL)   /*!< GPIO OTYPER: OT6 (Bitfield-Mask: 0x01) */
4755 #define GPIO_OTYPER_OT6                                                    GPIO_OTYPER_OT6_Msk
4756 #define GPIO_OTYPER_OT5_Pos                                                (5UL)    /*!<GPIO OTYPER: OT5 (Bit 5) */
4757 #define GPIO_OTYPER_OT5_Msk                                                (0x20UL)   /*!< GPIO OTYPER: OT5 (Bitfield-Mask: 0x01) */
4758 #define GPIO_OTYPER_OT5                                                    GPIO_OTYPER_OT5_Msk
4759 #define GPIO_OTYPER_OT4_Pos                                                (4UL)    /*!<GPIO OTYPER: OT4 (Bit 4) */
4760 #define GPIO_OTYPER_OT4_Msk                                                (0x10UL)   /*!< GPIO OTYPER: OT4 (Bitfield-Mask: 0x01) */
4761 #define GPIO_OTYPER_OT4                                                    GPIO_OTYPER_OT4_Msk
4762 #define GPIO_OTYPER_OT3_Pos                                                (3UL)    /*!<GPIO OTYPER: OT3 (Bit 3) */
4763 #define GPIO_OTYPER_OT3_Msk                                                (0x8UL)    /*!< GPIO OTYPER: OT3 (Bitfield-Mask: 0x01) */
4764 #define GPIO_OTYPER_OT3                                                    GPIO_OTYPER_OT3_Msk
4765 #define GPIO_OTYPER_OT2_Pos                                                (2UL)    /*!<GPIO OTYPER: OT2 (Bit 2) */
4766 #define GPIO_OTYPER_OT2_Msk                                                (0x4UL)    /*!< GPIO OTYPER: OT2 (Bitfield-Mask: 0x01) */
4767 #define GPIO_OTYPER_OT2                                                    GPIO_OTYPER_OT2_Msk
4768 #define GPIO_OTYPER_OT1_Pos                                                (1UL)    /*!<GPIO OTYPER: OT1 (Bit 1) */
4769 #define GPIO_OTYPER_OT1_Msk                                                (0x2UL)    /*!< GPIO OTYPER: OT1 (Bitfield-Mask: 0x01) */
4770 #define GPIO_OTYPER_OT1                                                    GPIO_OTYPER_OT1_Msk
4771 #define GPIO_OTYPER_OT0_Pos                                                (0UL)    /*!<GPIO OTYPER: OT0 (Bit 0) */
4772 #define GPIO_OTYPER_OT0_Msk                                                (0x1UL)    /*!< GPIO OTYPER: OT0 (Bitfield-Mask: 0x01) */
4773 #define GPIO_OTYPER_OT0                                                    GPIO_OTYPER_OT0_Msk
4774 
4775 /* =====================================================    OSPEEDR    ===================================================== */
4776 #define GPIO_OSPEEDR_OSPEED15_Pos                                          (30UL)   /*!<GPIO OSPEEDR: OSPEED15 (Bit 30) */
4777 #define GPIO_OSPEEDR_OSPEED15_Msk                                          (0xc0000000UL)   /*!< GPIO OSPEEDR: OSPEED15 (Bitfield-Mask: 0x03) */
4778 #define GPIO_OSPEEDR_OSPEED15                                              GPIO_OSPEEDR_OSPEED15_Msk
4779 #define GPIO_OSPEEDR_OSPEED15_0                                            (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)
4780 #define GPIO_OSPEEDR_OSPEED15_1                                            (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)
4781 #define GPIO_OSPEEDR_OSPEED14_Pos                                          (28UL)   /*!<GPIO OSPEEDR: OSPEED14 (Bit 28) */
4782 #define GPIO_OSPEEDR_OSPEED14_Msk                                          (0x30000000UL)   /*!< GPIO OSPEEDR: OSPEED14 (Bitfield-Mask: 0x03) */
4783 #define GPIO_OSPEEDR_OSPEED14                                              GPIO_OSPEEDR_OSPEED14_Msk
4784 #define GPIO_OSPEEDR_OSPEED14_0                                            (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)
4785 #define GPIO_OSPEEDR_OSPEED14_1                                            (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)
4786 #define GPIO_OSPEEDR_OSPEED13_Pos                                          (26UL)   /*!<GPIO OSPEEDR: OSPEED13 (Bit 26) */
4787 #define GPIO_OSPEEDR_OSPEED13_Msk                                          (0xc000000UL)    /*!< GPIO OSPEEDR: OSPEED13 (Bitfield-Mask: 0x03) */
4788 #define GPIO_OSPEEDR_OSPEED13                                              GPIO_OSPEEDR_OSPEED13_Msk
4789 #define GPIO_OSPEEDR_OSPEED13_0                                            (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)
4790 #define GPIO_OSPEEDR_OSPEED13_1                                            (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)
4791 #define GPIO_OSPEEDR_OSPEED12_Pos                                          (24UL)   /*!<GPIO OSPEEDR: OSPEED12 (Bit 24) */
4792 #define GPIO_OSPEEDR_OSPEED12_Msk                                          (0x3000000UL)    /*!< GPIO OSPEEDR: OSPEED12 (Bitfield-Mask: 0x03) */
4793 #define GPIO_OSPEEDR_OSPEED12                                              GPIO_OSPEEDR_OSPEED12_Msk
4794 #define GPIO_OSPEEDR_OSPEED12_0                                            (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)
4795 #define GPIO_OSPEEDR_OSPEED12_1                                            (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)
4796 #define GPIO_OSPEEDR_OSPEED11_Pos                                          (22UL)   /*!<GPIO OSPEEDR: OSPEED11 (Bit 22) */
4797 #define GPIO_OSPEEDR_OSPEED11_Msk                                          (0xc00000UL)   /*!< GPIO OSPEEDR: OSPEED11 (Bitfield-Mask: 0x03) */
4798 #define GPIO_OSPEEDR_OSPEED11                                              GPIO_OSPEEDR_OSPEED11_Msk
4799 #define GPIO_OSPEEDR_OSPEED11_0                                            (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)
4800 #define GPIO_OSPEEDR_OSPEED11_1                                            (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)
4801 #define GPIO_OSPEEDR_OSPEED10_Pos                                          (20UL)   /*!<GPIO OSPEEDR: OSPEED10 (Bit 20) */
4802 #define GPIO_OSPEEDR_OSPEED10_Msk                                          (0x300000UL)   /*!< GPIO OSPEEDR: OSPEED10 (Bitfield-Mask: 0x03) */
4803 #define GPIO_OSPEEDR_OSPEED10                                              GPIO_OSPEEDR_OSPEED10_Msk
4804 #define GPIO_OSPEEDR_OSPEED10_0                                            (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)
4805 #define GPIO_OSPEEDR_OSPEED10_1                                            (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)
4806 #define GPIO_OSPEEDR_OSPEED9_Pos                                           (18UL)   /*!<GPIO OSPEEDR: OSPEED9 (Bit 18) */
4807 #define GPIO_OSPEEDR_OSPEED9_Msk                                           (0xc0000UL)    /*!< GPIO OSPEEDR: OSPEED9 (Bitfield-Mask: 0x03) */
4808 #define GPIO_OSPEEDR_OSPEED9                                               GPIO_OSPEEDR_OSPEED9_Msk
4809 #define GPIO_OSPEEDR_OSPEED9_0                                             (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)
4810 #define GPIO_OSPEEDR_OSPEED9_1                                             (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)
4811 #define GPIO_OSPEEDR_OSPEED8_Pos                                           (16UL)   /*!<GPIO OSPEEDR: OSPEED8 (Bit 16) */
4812 #define GPIO_OSPEEDR_OSPEED8_Msk                                           (0x30000UL)    /*!< GPIO OSPEEDR: OSPEED8 (Bitfield-Mask: 0x03) */
4813 #define GPIO_OSPEEDR_OSPEED8                                               GPIO_OSPEEDR_OSPEED8_Msk
4814 #define GPIO_OSPEEDR_OSPEED8_0                                             (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)
4815 #define GPIO_OSPEEDR_OSPEED8_1                                             (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)
4816 #define GPIO_OSPEEDR_OSPEED7_Pos                                           (14UL)   /*!<GPIO OSPEEDR: OSPEED7 (Bit 14) */
4817 #define GPIO_OSPEEDR_OSPEED7_Msk                                           (0xc000UL)   /*!< GPIO OSPEEDR: OSPEED7 (Bitfield-Mask: 0x03) */
4818 #define GPIO_OSPEEDR_OSPEED7                                               GPIO_OSPEEDR_OSPEED7_Msk
4819 #define GPIO_OSPEEDR_OSPEED7_0                                             (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)
4820 #define GPIO_OSPEEDR_OSPEED7_1                                             (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)
4821 #define GPIO_OSPEEDR_OSPEED6_Pos                                           (12UL)   /*!<GPIO OSPEEDR: OSPEED6 (Bit 12) */
4822 #define GPIO_OSPEEDR_OSPEED6_Msk                                           (0x3000UL)   /*!< GPIO OSPEEDR: OSPEED6 (Bitfield-Mask: 0x03) */
4823 #define GPIO_OSPEEDR_OSPEED6                                               GPIO_OSPEEDR_OSPEED6_Msk
4824 #define GPIO_OSPEEDR_OSPEED6_0                                             (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)
4825 #define GPIO_OSPEEDR_OSPEED6_1                                             (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)
4826 #define GPIO_OSPEEDR_OSPEED5_Pos                                           (10UL)   /*!<GPIO OSPEEDR: OSPEED5 (Bit 10) */
4827 #define GPIO_OSPEEDR_OSPEED5_Msk                                           (0xc00UL)    /*!< GPIO OSPEEDR: OSPEED5 (Bitfield-Mask: 0x03) */
4828 #define GPIO_OSPEEDR_OSPEED5                                               GPIO_OSPEEDR_OSPEED5_Msk
4829 #define GPIO_OSPEEDR_OSPEED5_0                                             (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)
4830 #define GPIO_OSPEEDR_OSPEED5_1                                             (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)
4831 #define GPIO_OSPEEDR_OSPEED4_Pos                                           (8UL)    /*!<GPIO OSPEEDR: OSPEED4 (Bit 8) */
4832 #define GPIO_OSPEEDR_OSPEED4_Msk                                           (0x300UL)    /*!< GPIO OSPEEDR: OSPEED4 (Bitfield-Mask: 0x03) */
4833 #define GPIO_OSPEEDR_OSPEED4                                               GPIO_OSPEEDR_OSPEED4_Msk
4834 #define GPIO_OSPEEDR_OSPEED4_0                                             (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)
4835 #define GPIO_OSPEEDR_OSPEED4_1                                             (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)
4836 #define GPIO_OSPEEDR_OSPEED3_Pos                                           (6UL)    /*!<GPIO OSPEEDR: OSPEED3 (Bit 6) */
4837 #define GPIO_OSPEEDR_OSPEED3_Msk                                           (0xc0UL)   /*!< GPIO OSPEEDR: OSPEED3 (Bitfield-Mask: 0x03) */
4838 #define GPIO_OSPEEDR_OSPEED3                                               GPIO_OSPEEDR_OSPEED3_Msk
4839 #define GPIO_OSPEEDR_OSPEED3_0                                             (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)
4840 #define GPIO_OSPEEDR_OSPEED3_1                                             (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)
4841 #define GPIO_OSPEEDR_OSPEED2_Pos                                           (4UL)    /*!<GPIO OSPEEDR: OSPEED2 (Bit 4) */
4842 #define GPIO_OSPEEDR_OSPEED2_Msk                                           (0x30UL)   /*!< GPIO OSPEEDR: OSPEED2 (Bitfield-Mask: 0x03) */
4843 #define GPIO_OSPEEDR_OSPEED2                                               GPIO_OSPEEDR_OSPEED2_Msk
4844 #define GPIO_OSPEEDR_OSPEED2_0                                             (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)
4845 #define GPIO_OSPEEDR_OSPEED2_1                                             (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)
4846 #define GPIO_OSPEEDR_OSPEED1_Pos                                           (2UL)    /*!<GPIO OSPEEDR: OSPEED1 (Bit 2) */
4847 #define GPIO_OSPEEDR_OSPEED1_Msk                                           (0xcUL)    /*!< GPIO OSPEEDR: OSPEED1 (Bitfield-Mask: 0x03) */
4848 #define GPIO_OSPEEDR_OSPEED1                                               GPIO_OSPEEDR_OSPEED1_Msk
4849 #define GPIO_OSPEEDR_OSPEED1_0                                             (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)
4850 #define GPIO_OSPEEDR_OSPEED1_1                                             (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)
4851 #define GPIO_OSPEEDR_OSPEED0_Pos                                           (0UL)    /*!<GPIO OSPEEDR: OSPEED0 (Bit 0) */
4852 #define GPIO_OSPEEDR_OSPEED0_Msk                                           (0x3UL)    /*!< GPIO OSPEEDR: OSPEED0 (Bitfield-Mask: 0x03) */
4853 #define GPIO_OSPEEDR_OSPEED0                                               GPIO_OSPEEDR_OSPEED0_Msk
4854 #define GPIO_OSPEEDR_OSPEED0_0                                             (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)
4855 #define GPIO_OSPEEDR_OSPEED0_1                                             (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)
4856 
4857 /* =====================================================    PUPDR    ===================================================== */
4858 #define GPIO_PUPDR_PUPD15_Pos                                              (30UL)   /*!<GPIO PUPDR: PUPD15 (Bit 30) */
4859 #define GPIO_PUPDR_PUPD15_Msk                                              (0xc0000000UL)   /*!< GPIO PUPDR: PUPD15 (Bitfield-Mask: 0x03) */
4860 #define GPIO_PUPDR_PUPD15                                                  GPIO_PUPDR_PUPD15_Msk
4861 #define GPIO_PUPDR_PUPD15_0                                                (0x1U << GPIO_PUPDR_PUPD15_Pos)
4862 #define GPIO_PUPDR_PUPD15_1                                                (0x2U << GPIO_PUPDR_PUPD15_Pos)
4863 #define GPIO_PUPDR_PUPD14_Pos                                              (28UL)   /*!<GPIO PUPDR: PUPD14 (Bit 28) */
4864 #define GPIO_PUPDR_PUPD14_Msk                                              (0x30000000UL)   /*!< GPIO PUPDR: PUPD14 (Bitfield-Mask: 0x03) */
4865 #define GPIO_PUPDR_PUPD14                                                  GPIO_PUPDR_PUPD14_Msk
4866 #define GPIO_PUPDR_PUPD14_0                                                (0x1U << GPIO_PUPDR_PUPD14_Pos)
4867 #define GPIO_PUPDR_PUPD14_1                                                (0x2U << GPIO_PUPDR_PUPD14_Pos)
4868 #define GPIO_PUPDR_PUPD13_Pos                                              (26UL)   /*!<GPIO PUPDR: PUPD13 (Bit 26) */
4869 #define GPIO_PUPDR_PUPD13_Msk                                              (0xc000000UL)    /*!< GPIO PUPDR: PUPD13 (Bitfield-Mask: 0x03) */
4870 #define GPIO_PUPDR_PUPD13                                                  GPIO_PUPDR_PUPD13_Msk
4871 #define GPIO_PUPDR_PUPD13_0                                                (0x1U << GPIO_PUPDR_PUPD13_Pos)
4872 #define GPIO_PUPDR_PUPD13_1                                                (0x2U << GPIO_PUPDR_PUPD13_Pos)
4873 #define GPIO_PUPDR_PUPD12_Pos                                              (24UL)   /*!<GPIO PUPDR: PUPD12 (Bit 24) */
4874 #define GPIO_PUPDR_PUPD12_Msk                                              (0x3000000UL)    /*!< GPIO PUPDR: PUPD12 (Bitfield-Mask: 0x03) */
4875 #define GPIO_PUPDR_PUPD12                                                  GPIO_PUPDR_PUPD12_Msk
4876 #define GPIO_PUPDR_PUPD12_0                                                (0x1U << GPIO_PUPDR_PUPD12_Pos)
4877 #define GPIO_PUPDR_PUPD12_1                                                (0x2U << GPIO_PUPDR_PUPD12_Pos)
4878 #define GPIO_PUPDR_PUPD11_Pos                                              (22UL)   /*!<GPIO PUPDR: PUPD11 (Bit 22) */
4879 #define GPIO_PUPDR_PUPD11_Msk                                              (0xc00000UL)   /*!< GPIO PUPDR: PUPD11 (Bitfield-Mask: 0x03) */
4880 #define GPIO_PUPDR_PUPD11                                                  GPIO_PUPDR_PUPD11_Msk
4881 #define GPIO_PUPDR_PUPD11_0                                                (0x1U << GPIO_PUPDR_PUPD11_Pos)
4882 #define GPIO_PUPDR_PUPD11_1                                                (0x2U << GPIO_PUPDR_PUPD11_Pos)
4883 #define GPIO_PUPDR_PUPD10_Pos                                              (20UL)   /*!<GPIO PUPDR: PUPD10 (Bit 20) */
4884 #define GPIO_PUPDR_PUPD10_Msk                                              (0x300000UL)   /*!< GPIO PUPDR: PUPD10 (Bitfield-Mask: 0x03) */
4885 #define GPIO_PUPDR_PUPD10                                                  GPIO_PUPDR_PUPD10_Msk
4886 #define GPIO_PUPDR_PUPD10_0                                                (0x1U << GPIO_PUPDR_PUPD10_Pos)
4887 #define GPIO_PUPDR_PUPD10_1                                                (0x2U << GPIO_PUPDR_PUPD10_Pos)
4888 #define GPIO_PUPDR_PUPD9_Pos                                               (18UL)   /*!<GPIO PUPDR: PUPD9 (Bit 18) */
4889 #define GPIO_PUPDR_PUPD9_Msk                                               (0xc0000UL)    /*!< GPIO PUPDR: PUPD9 (Bitfield-Mask: 0x03) */
4890 #define GPIO_PUPDR_PUPD9                                                   GPIO_PUPDR_PUPD9_Msk
4891 #define GPIO_PUPDR_PUPD9_0                                                 (0x1U << GPIO_PUPDR_PUPD9_Pos)
4892 #define GPIO_PUPDR_PUPD9_1                                                 (0x2U << GPIO_PUPDR_PUPD9_Pos)
4893 #define GPIO_PUPDR_PUPD8_Pos                                               (16UL)   /*!<GPIO PUPDR: PUPD8 (Bit 16) */
4894 #define GPIO_PUPDR_PUPD8_Msk                                               (0x30000UL)    /*!< GPIO PUPDR: PUPD8 (Bitfield-Mask: 0x03) */
4895 #define GPIO_PUPDR_PUPD8                                                   GPIO_PUPDR_PUPD8_Msk
4896 #define GPIO_PUPDR_PUPD8_0                                                 (0x1U << GPIO_PUPDR_PUPD8_Pos)
4897 #define GPIO_PUPDR_PUPD8_1                                                 (0x2U << GPIO_PUPDR_PUPD8_Pos)
4898 #define GPIO_PUPDR_PUPD7_Pos                                               (14UL)   /*!<GPIO PUPDR: PUPD7 (Bit 14) */
4899 #define GPIO_PUPDR_PUPD7_Msk                                               (0xc000UL)   /*!< GPIO PUPDR: PUPD7 (Bitfield-Mask: 0x03) */
4900 #define GPIO_PUPDR_PUPD7                                                   GPIO_PUPDR_PUPD7_Msk
4901 #define GPIO_PUPDR_PUPD7_0                                                 (0x1U << GPIO_PUPDR_PUPD7_Pos)
4902 #define GPIO_PUPDR_PUPD7_1                                                 (0x2U << GPIO_PUPDR_PUPD7_Pos)
4903 #define GPIO_PUPDR_PUPD6_Pos                                               (12UL)   /*!<GPIO PUPDR: PUPD6 (Bit 12) */
4904 #define GPIO_PUPDR_PUPD6_Msk                                               (0x3000UL)   /*!< GPIO PUPDR: PUPD6 (Bitfield-Mask: 0x03) */
4905 #define GPIO_PUPDR_PUPD6                                                   GPIO_PUPDR_PUPD6_Msk
4906 #define GPIO_PUPDR_PUPD6_0                                                 (0x1U << GPIO_PUPDR_PUPD6_Pos)
4907 #define GPIO_PUPDR_PUPD6_1                                                 (0x2U << GPIO_PUPDR_PUPD6_Pos)
4908 #define GPIO_PUPDR_PUPD5_Pos                                               (10UL)   /*!<GPIO PUPDR: PUPD5 (Bit 10) */
4909 #define GPIO_PUPDR_PUPD5_Msk                                               (0xc00UL)    /*!< GPIO PUPDR: PUPD5 (Bitfield-Mask: 0x03) */
4910 #define GPIO_PUPDR_PUPD5                                                   GPIO_PUPDR_PUPD5_Msk
4911 #define GPIO_PUPDR_PUPD5_0                                                 (0x1U << GPIO_PUPDR_PUPD5_Pos)
4912 #define GPIO_PUPDR_PUPD5_1                                                 (0x2U << GPIO_PUPDR_PUPD5_Pos)
4913 #define GPIO_PUPDR_PUPD4_Pos                                               (8UL)    /*!<GPIO PUPDR: PUPD4 (Bit 8) */
4914 #define GPIO_PUPDR_PUPD4_Msk                                               (0x300UL)    /*!< GPIO PUPDR: PUPD4 (Bitfield-Mask: 0x03) */
4915 #define GPIO_PUPDR_PUPD4                                                   GPIO_PUPDR_PUPD4_Msk
4916 #define GPIO_PUPDR_PUPD4_0                                                 (0x1U << GPIO_PUPDR_PUPD4_Pos)
4917 #define GPIO_PUPDR_PUPD4_1                                                 (0x2U << GPIO_PUPDR_PUPD4_Pos)
4918 #define GPIO_PUPDR_PUPD3_Pos                                               (6UL)    /*!<GPIO PUPDR: PUPD3 (Bit 6) */
4919 #define GPIO_PUPDR_PUPD3_Msk                                               (0xc0UL)   /*!< GPIO PUPDR: PUPD3 (Bitfield-Mask: 0x03) */
4920 #define GPIO_PUPDR_PUPD3                                                   GPIO_PUPDR_PUPD3_Msk
4921 #define GPIO_PUPDR_PUPD3_0                                                 (0x1U << GPIO_PUPDR_PUPD3_Pos)
4922 #define GPIO_PUPDR_PUPD3_1                                                 (0x2U << GPIO_PUPDR_PUPD3_Pos)
4923 #define GPIO_PUPDR_PUPD2_Pos                                               (4UL)    /*!<GPIO PUPDR: PUPD2 (Bit 4) */
4924 #define GPIO_PUPDR_PUPD2_Msk                                               (0x30UL)   /*!< GPIO PUPDR: PUPD2 (Bitfield-Mask: 0x03) */
4925 #define GPIO_PUPDR_PUPD2                                                   GPIO_PUPDR_PUPD2_Msk
4926 #define GPIO_PUPDR_PUPD2_0                                                 (0x1U << GPIO_PUPDR_PUPD2_Pos)
4927 #define GPIO_PUPDR_PUPD2_1                                                 (0x2U << GPIO_PUPDR_PUPD2_Pos)
4928 #define GPIO_PUPDR_PUPD1_Pos                                               (2UL)    /*!<GPIO PUPDR: PUPD1 (Bit 2) */
4929 #define GPIO_PUPDR_PUPD1_Msk                                               (0xcUL)    /*!< GPIO PUPDR: PUPD1 (Bitfield-Mask: 0x03) */
4930 #define GPIO_PUPDR_PUPD1                                                   GPIO_PUPDR_PUPD1_Msk
4931 #define GPIO_PUPDR_PUPD1_0                                                 (0x1U << GPIO_PUPDR_PUPD1_Pos)
4932 #define GPIO_PUPDR_PUPD1_1                                                 (0x2U << GPIO_PUPDR_PUPD1_Pos)
4933 #define GPIO_PUPDR_PUPD0_Pos                                               (0UL)    /*!<GPIO PUPDR: PUPD0 (Bit 0) */
4934 #define GPIO_PUPDR_PUPD0_Msk                                               (0x3UL)    /*!< GPIO PUPDR: PUPD0 (Bitfield-Mask: 0x03) */
4935 #define GPIO_PUPDR_PUPD0                                                   GPIO_PUPDR_PUPD0_Msk
4936 #define GPIO_PUPDR_PUPD0_0                                                 (0x1U << GPIO_PUPDR_PUPD0_Pos)
4937 #define GPIO_PUPDR_PUPD0_1                                                 (0x2U << GPIO_PUPDR_PUPD0_Pos)
4938 
4939 /* =====================================================    IDR    ===================================================== */
4940 #define GPIO_IDR_ID15_Pos                                                  (15UL)   /*!<GPIO IDR: ID15 (Bit 15) */
4941 #define GPIO_IDR_ID15_Msk                                                  (0x8000UL)   /*!< GPIO IDR: ID15 (Bitfield-Mask: 0x01) */
4942 #define GPIO_IDR_ID15                                                      GPIO_IDR_ID15_Msk
4943 #define GPIO_IDR_ID14_Pos                                                  (14UL)   /*!<GPIO IDR: ID14 (Bit 14) */
4944 #define GPIO_IDR_ID14_Msk                                                  (0x4000UL)   /*!< GPIO IDR: ID14 (Bitfield-Mask: 0x01) */
4945 #define GPIO_IDR_ID14                                                      GPIO_IDR_ID14_Msk
4946 #define GPIO_IDR_ID13_Pos                                                  (13UL)   /*!<GPIO IDR: ID13 (Bit 13) */
4947 #define GPIO_IDR_ID13_Msk                                                  (0x2000UL)   /*!< GPIO IDR: ID13 (Bitfield-Mask: 0x01) */
4948 #define GPIO_IDR_ID13                                                      GPIO_IDR_ID13_Msk
4949 #define GPIO_IDR_ID12_Pos                                                  (12UL)   /*!<GPIO IDR: ID12 (Bit 12) */
4950 #define GPIO_IDR_ID12_Msk                                                  (0x1000UL)   /*!< GPIO IDR: ID12 (Bitfield-Mask: 0x01) */
4951 #define GPIO_IDR_ID12                                                      GPIO_IDR_ID12_Msk
4952 #define GPIO_IDR_ID11_Pos                                                  (11UL)   /*!<GPIO IDR: ID11 (Bit 11) */
4953 #define GPIO_IDR_ID11_Msk                                                  (0x800UL)    /*!< GPIO IDR: ID11 (Bitfield-Mask: 0x01) */
4954 #define GPIO_IDR_ID11                                                      GPIO_IDR_ID11_Msk
4955 #define GPIO_IDR_ID10_Pos                                                  (10UL)   /*!<GPIO IDR: ID10 (Bit 10) */
4956 #define GPIO_IDR_ID10_Msk                                                  (0x400UL)    /*!< GPIO IDR: ID10 (Bitfield-Mask: 0x01) */
4957 #define GPIO_IDR_ID10                                                      GPIO_IDR_ID10_Msk
4958 #define GPIO_IDR_ID9_Pos                                                   (9UL)    /*!<GPIO IDR: ID9 (Bit 9) */
4959 #define GPIO_IDR_ID9_Msk                                                   (0x200UL)    /*!< GPIO IDR: ID9 (Bitfield-Mask: 0x01) */
4960 #define GPIO_IDR_ID9                                                       GPIO_IDR_ID9_Msk
4961 #define GPIO_IDR_ID8_Pos                                                   (8UL)    /*!<GPIO IDR: ID8 (Bit 8) */
4962 #define GPIO_IDR_ID8_Msk                                                   (0x100UL)    /*!< GPIO IDR: ID8 (Bitfield-Mask: 0x01) */
4963 #define GPIO_IDR_ID8                                                       GPIO_IDR_ID8_Msk
4964 #define GPIO_IDR_ID7_Pos                                                   (7UL)    /*!<GPIO IDR: ID7 (Bit 7) */
4965 #define GPIO_IDR_ID7_Msk                                                   (0x80UL)   /*!< GPIO IDR: ID7 (Bitfield-Mask: 0x01) */
4966 #define GPIO_IDR_ID7                                                       GPIO_IDR_ID7_Msk
4967 #define GPIO_IDR_ID6_Pos                                                   (6UL)    /*!<GPIO IDR: ID6 (Bit 6) */
4968 #define GPIO_IDR_ID6_Msk                                                   (0x40UL)   /*!< GPIO IDR: ID6 (Bitfield-Mask: 0x01) */
4969 #define GPIO_IDR_ID6                                                       GPIO_IDR_ID6_Msk
4970 #define GPIO_IDR_ID5_Pos                                                   (5UL)    /*!<GPIO IDR: ID5 (Bit 5) */
4971 #define GPIO_IDR_ID5_Msk                                                   (0x20UL)   /*!< GPIO IDR: ID5 (Bitfield-Mask: 0x01) */
4972 #define GPIO_IDR_ID5                                                       GPIO_IDR_ID5_Msk
4973 #define GPIO_IDR_ID4_Pos                                                   (4UL)    /*!<GPIO IDR: ID4 (Bit 4) */
4974 #define GPIO_IDR_ID4_Msk                                                   (0x10UL)   /*!< GPIO IDR: ID4 (Bitfield-Mask: 0x01) */
4975 #define GPIO_IDR_ID4                                                       GPIO_IDR_ID4_Msk
4976 #define GPIO_IDR_ID3_Pos                                                   (3UL)    /*!<GPIO IDR: ID3 (Bit 3) */
4977 #define GPIO_IDR_ID3_Msk                                                   (0x8UL)    /*!< GPIO IDR: ID3 (Bitfield-Mask: 0x01) */
4978 #define GPIO_IDR_ID3                                                       GPIO_IDR_ID3_Msk
4979 #define GPIO_IDR_ID2_Pos                                                   (2UL)    /*!<GPIO IDR: ID2 (Bit 2) */
4980 #define GPIO_IDR_ID2_Msk                                                   (0x4UL)    /*!< GPIO IDR: ID2 (Bitfield-Mask: 0x01) */
4981 #define GPIO_IDR_ID2                                                       GPIO_IDR_ID2_Msk
4982 #define GPIO_IDR_ID1_Pos                                                   (1UL)    /*!<GPIO IDR: ID1 (Bit 1) */
4983 #define GPIO_IDR_ID1_Msk                                                   (0x2UL)    /*!< GPIO IDR: ID1 (Bitfield-Mask: 0x01) */
4984 #define GPIO_IDR_ID1                                                       GPIO_IDR_ID1_Msk
4985 #define GPIO_IDR_ID0_Pos                                                   (0UL)    /*!<GPIO IDR: ID0 (Bit 0) */
4986 #define GPIO_IDR_ID0_Msk                                                   (0x1UL)    /*!< GPIO IDR: ID0 (Bitfield-Mask: 0x01) */
4987 #define GPIO_IDR_ID0                                                       GPIO_IDR_ID0_Msk
4988 
4989 /* =====================================================    ODR    ===================================================== */
4990 #define GPIO_ODR_OD15_Pos                                                  (15UL)   /*!<GPIO ODR: OD15 (Bit 15) */
4991 #define GPIO_ODR_OD15_Msk                                                  (0x8000UL)   /*!< GPIO ODR: OD15 (Bitfield-Mask: 0x01) */
4992 #define GPIO_ODR_OD15                                                      GPIO_ODR_OD15_Msk
4993 #define GPIO_ODR_OD14_Pos                                                  (14UL)   /*!<GPIO ODR: OD14 (Bit 14) */
4994 #define GPIO_ODR_OD14_Msk                                                  (0x4000UL)   /*!< GPIO ODR: OD14 (Bitfield-Mask: 0x01) */
4995 #define GPIO_ODR_OD14                                                      GPIO_ODR_OD14_Msk
4996 #define GPIO_ODR_OD13_Pos                                                  (13UL)   /*!<GPIO ODR: OD13 (Bit 13) */
4997 #define GPIO_ODR_OD13_Msk                                                  (0x2000UL)   /*!< GPIO ODR: OD13 (Bitfield-Mask: 0x01) */
4998 #define GPIO_ODR_OD13                                                      GPIO_ODR_OD13_Msk
4999 #define GPIO_ODR_OD12_Pos                                                  (12UL)   /*!<GPIO ODR: OD12 (Bit 12) */
5000 #define GPIO_ODR_OD12_Msk                                                  (0x1000UL)   /*!< GPIO ODR: OD12 (Bitfield-Mask: 0x01) */
5001 #define GPIO_ODR_OD12                                                      GPIO_ODR_OD12_Msk
5002 #define GPIO_ODR_OD11_Pos                                                  (11UL)   /*!<GPIO ODR: OD11 (Bit 11) */
5003 #define GPIO_ODR_OD11_Msk                                                  (0x800UL)    /*!< GPIO ODR: OD11 (Bitfield-Mask: 0x01) */
5004 #define GPIO_ODR_OD11                                                      GPIO_ODR_OD11_Msk
5005 #define GPIO_ODR_OD10_Pos                                                  (10UL)   /*!<GPIO ODR: OD10 (Bit 10) */
5006 #define GPIO_ODR_OD10_Msk                                                  (0x400UL)    /*!< GPIO ODR: OD10 (Bitfield-Mask: 0x01) */
5007 #define GPIO_ODR_OD10                                                      GPIO_ODR_OD10_Msk
5008 #define GPIO_ODR_OD9_Pos                                                   (9UL)    /*!<GPIO ODR: OD9 (Bit 9) */
5009 #define GPIO_ODR_OD9_Msk                                                   (0x200UL)    /*!< GPIO ODR: OD9 (Bitfield-Mask: 0x01) */
5010 #define GPIO_ODR_OD9                                                       GPIO_ODR_OD9_Msk
5011 #define GPIO_ODR_OD8_Pos                                                   (8UL)    /*!<GPIO ODR: OD8 (Bit 8) */
5012 #define GPIO_ODR_OD8_Msk                                                   (0x100UL)    /*!< GPIO ODR: OD8 (Bitfield-Mask: 0x01) */
5013 #define GPIO_ODR_OD8                                                       GPIO_ODR_OD8_Msk
5014 #define GPIO_ODR_OD7_Pos                                                   (7UL)    /*!<GPIO ODR: OD7 (Bit 7) */
5015 #define GPIO_ODR_OD7_Msk                                                   (0x80UL)   /*!< GPIO ODR: OD7 (Bitfield-Mask: 0x01) */
5016 #define GPIO_ODR_OD7                                                       GPIO_ODR_OD7_Msk
5017 #define GPIO_ODR_OD6_Pos                                                   (6UL)    /*!<GPIO ODR: OD6 (Bit 6) */
5018 #define GPIO_ODR_OD6_Msk                                                   (0x40UL)   /*!< GPIO ODR: OD6 (Bitfield-Mask: 0x01) */
5019 #define GPIO_ODR_OD6                                                       GPIO_ODR_OD6_Msk
5020 #define GPIO_ODR_OD5_Pos                                                   (5UL)    /*!<GPIO ODR: OD5 (Bit 5) */
5021 #define GPIO_ODR_OD5_Msk                                                   (0x20UL)   /*!< GPIO ODR: OD5 (Bitfield-Mask: 0x01) */
5022 #define GPIO_ODR_OD5                                                       GPIO_ODR_OD5_Msk
5023 #define GPIO_ODR_OD4_Pos                                                   (4UL)    /*!<GPIO ODR: OD4 (Bit 4) */
5024 #define GPIO_ODR_OD4_Msk                                                   (0x10UL)   /*!< GPIO ODR: OD4 (Bitfield-Mask: 0x01) */
5025 #define GPIO_ODR_OD4                                                       GPIO_ODR_OD4_Msk
5026 #define GPIO_ODR_OD3_Pos                                                   (3UL)    /*!<GPIO ODR: OD3 (Bit 3) */
5027 #define GPIO_ODR_OD3_Msk                                                   (0x8UL)    /*!< GPIO ODR: OD3 (Bitfield-Mask: 0x01) */
5028 #define GPIO_ODR_OD3                                                       GPIO_ODR_OD3_Msk
5029 #define GPIO_ODR_OD2_Pos                                                   (2UL)    /*!<GPIO ODR: OD2 (Bit 2) */
5030 #define GPIO_ODR_OD2_Msk                                                   (0x4UL)    /*!< GPIO ODR: OD2 (Bitfield-Mask: 0x01) */
5031 #define GPIO_ODR_OD2                                                       GPIO_ODR_OD2_Msk
5032 #define GPIO_ODR_OD1_Pos                                                   (1UL)    /*!<GPIO ODR: OD1 (Bit 1) */
5033 #define GPIO_ODR_OD1_Msk                                                   (0x2UL)    /*!< GPIO ODR: OD1 (Bitfield-Mask: 0x01) */
5034 #define GPIO_ODR_OD1                                                       GPIO_ODR_OD1_Msk
5035 #define GPIO_ODR_OD0_Pos                                                   (0UL)    /*!<GPIO ODR: OD0 (Bit 0) */
5036 #define GPIO_ODR_OD0_Msk                                                   (0x1UL)    /*!< GPIO ODR: OD0 (Bitfield-Mask: 0x01) */
5037 #define GPIO_ODR_OD0                                                       GPIO_ODR_OD0_Msk
5038 
5039 /* =====================================================    BSRR    ===================================================== */
5040 #define GPIO_BSRR_BR15_Pos                                                 (31UL)   /*!<GPIO BSRR: BR15 (Bit 31) */
5041 #define GPIO_BSRR_BR15_Msk                                                 (0x80000000UL)   /*!< GPIO BSRR: BR15 (Bitfield-Mask: 0x01) */
5042 #define GPIO_BSRR_BR15                                                     GPIO_BSRR_BR15_Msk
5043 #define GPIO_BSRR_BR14_Pos                                                 (30UL)   /*!<GPIO BSRR: BR14 (Bit 30) */
5044 #define GPIO_BSRR_BR14_Msk                                                 (0x40000000UL)   /*!< GPIO BSRR: BR14 (Bitfield-Mask: 0x01) */
5045 #define GPIO_BSRR_BR14                                                     GPIO_BSRR_BR14_Msk
5046 #define GPIO_BSRR_BR13_Pos                                                 (29UL)   /*!<GPIO BSRR: BR13 (Bit 29) */
5047 #define GPIO_BSRR_BR13_Msk                                                 (0x20000000UL)   /*!< GPIO BSRR: BR13 (Bitfield-Mask: 0x01) */
5048 #define GPIO_BSRR_BR13                                                     GPIO_BSRR_BR13_Msk
5049 #define GPIO_BSRR_BR12_Pos                                                 (28UL)   /*!<GPIO BSRR: BR12 (Bit 28) */
5050 #define GPIO_BSRR_BR12_Msk                                                 (0x10000000UL)   /*!< GPIO BSRR: BR12 (Bitfield-Mask: 0x01) */
5051 #define GPIO_BSRR_BR12                                                     GPIO_BSRR_BR12_Msk
5052 #define GPIO_BSRR_BR11_Pos                                                 (27UL)   /*!<GPIO BSRR: BR11 (Bit 27) */
5053 #define GPIO_BSRR_BR11_Msk                                                 (0x8000000UL)    /*!< GPIO BSRR: BR11 (Bitfield-Mask: 0x01) */
5054 #define GPIO_BSRR_BR11                                                     GPIO_BSRR_BR11_Msk
5055 #define GPIO_BSRR_BR10_Pos                                                 (26UL)   /*!<GPIO BSRR: BR10 (Bit 26) */
5056 #define GPIO_BSRR_BR10_Msk                                                 (0x4000000UL)    /*!< GPIO BSRR: BR10 (Bitfield-Mask: 0x01) */
5057 #define GPIO_BSRR_BR10                                                     GPIO_BSRR_BR10_Msk
5058 #define GPIO_BSRR_BR9_Pos                                                  (25UL)   /*!<GPIO BSRR: BR9 (Bit 25) */
5059 #define GPIO_BSRR_BR9_Msk                                                  (0x2000000UL)    /*!< GPIO BSRR: BR9 (Bitfield-Mask: 0x01) */
5060 #define GPIO_BSRR_BR9                                                      GPIO_BSRR_BR9_Msk
5061 #define GPIO_BSRR_BR8_Pos                                                  (24UL)   /*!<GPIO BSRR: BR8 (Bit 24) */
5062 #define GPIO_BSRR_BR8_Msk                                                  (0x1000000UL)    /*!< GPIO BSRR: BR8 (Bitfield-Mask: 0x01) */
5063 #define GPIO_BSRR_BR8                                                      GPIO_BSRR_BR8_Msk
5064 #define GPIO_BSRR_BR7_Pos                                                  (23UL)   /*!<GPIO BSRR: BR7 (Bit 23) */
5065 #define GPIO_BSRR_BR7_Msk                                                  (0x800000UL)   /*!< GPIO BSRR: BR7 (Bitfield-Mask: 0x01) */
5066 #define GPIO_BSRR_BR7                                                      GPIO_BSRR_BR7_Msk
5067 #define GPIO_BSRR_BR6_Pos                                                  (22UL)   /*!<GPIO BSRR: BR6 (Bit 22) */
5068 #define GPIO_BSRR_BR6_Msk                                                  (0x400000UL)   /*!< GPIO BSRR: BR6 (Bitfield-Mask: 0x01) */
5069 #define GPIO_BSRR_BR6                                                      GPIO_BSRR_BR6_Msk
5070 #define GPIO_BSRR_BR5_Pos                                                  (21UL)   /*!<GPIO BSRR: BR5 (Bit 21) */
5071 #define GPIO_BSRR_BR5_Msk                                                  (0x200000UL)   /*!< GPIO BSRR: BR5 (Bitfield-Mask: 0x01) */
5072 #define GPIO_BSRR_BR5                                                      GPIO_BSRR_BR5_Msk
5073 #define GPIO_BSRR_BR4_Pos                                                  (20UL)   /*!<GPIO BSRR: BR4 (Bit 20) */
5074 #define GPIO_BSRR_BR4_Msk                                                  (0x100000UL)   /*!< GPIO BSRR: BR4 (Bitfield-Mask: 0x01) */
5075 #define GPIO_BSRR_BR4                                                      GPIO_BSRR_BR4_Msk
5076 #define GPIO_BSRR_BR3_Pos                                                  (19UL)   /*!<GPIO BSRR: BR3 (Bit 19) */
5077 #define GPIO_BSRR_BR3_Msk                                                  (0x80000UL)    /*!< GPIO BSRR: BR3 (Bitfield-Mask: 0x01) */
5078 #define GPIO_BSRR_BR3                                                      GPIO_BSRR_BR3_Msk
5079 #define GPIO_BSRR_BR2_Pos                                                  (18UL)   /*!<GPIO BSRR: BR2 (Bit 18) */
5080 #define GPIO_BSRR_BR2_Msk                                                  (0x40000UL)    /*!< GPIO BSRR: BR2 (Bitfield-Mask: 0x01) */
5081 #define GPIO_BSRR_BR2                                                      GPIO_BSRR_BR2_Msk
5082 #define GPIO_BSRR_BR1_Pos                                                  (17UL)   /*!<GPIO BSRR: BR1 (Bit 17) */
5083 #define GPIO_BSRR_BR1_Msk                                                  (0x20000UL)    /*!< GPIO BSRR: BR1 (Bitfield-Mask: 0x01) */
5084 #define GPIO_BSRR_BR1                                                      GPIO_BSRR_BR1_Msk
5085 #define GPIO_BSRR_BR0_Pos                                                  (16UL)   /*!<GPIO BSRR: BR0 (Bit 16) */
5086 #define GPIO_BSRR_BR0_Msk                                                  (0x10000UL)    /*!< GPIO BSRR: BR0 (Bitfield-Mask: 0x01) */
5087 #define GPIO_BSRR_BR0                                                      GPIO_BSRR_BR0_Msk
5088 #define GPIO_BSRR_BS15_Pos                                                 (15UL)   /*!<GPIO BSRR: BS15 (Bit 15) */
5089 #define GPIO_BSRR_BS15_Msk                                                 (0x8000UL)   /*!< GPIO BSRR: BS15 (Bitfield-Mask: 0x01) */
5090 #define GPIO_BSRR_BS15                                                     GPIO_BSRR_BS15_Msk
5091 #define GPIO_BSRR_BS14_Pos                                                 (14UL)   /*!<GPIO BSRR: BS14 (Bit 14) */
5092 #define GPIO_BSRR_BS14_Msk                                                 (0x4000UL)   /*!< GPIO BSRR: BS14 (Bitfield-Mask: 0x01) */
5093 #define GPIO_BSRR_BS14                                                     GPIO_BSRR_BS14_Msk
5094 #define GPIO_BSRR_BS13_Pos                                                 (13UL)   /*!<GPIO BSRR: BS13 (Bit 13) */
5095 #define GPIO_BSRR_BS13_Msk                                                 (0x2000UL)   /*!< GPIO BSRR: BS13 (Bitfield-Mask: 0x01) */
5096 #define GPIO_BSRR_BS13                                                     GPIO_BSRR_BS13_Msk
5097 #define GPIO_BSRR_BS12_Pos                                                 (12UL)   /*!<GPIO BSRR: BS12 (Bit 12) */
5098 #define GPIO_BSRR_BS12_Msk                                                 (0x1000UL)   /*!< GPIO BSRR: BS12 (Bitfield-Mask: 0x01) */
5099 #define GPIO_BSRR_BS12                                                     GPIO_BSRR_BS12_Msk
5100 #define GPIO_BSRR_BS11_Pos                                                 (11UL)   /*!<GPIO BSRR: BS11 (Bit 11) */
5101 #define GPIO_BSRR_BS11_Msk                                                 (0x800UL)    /*!< GPIO BSRR: BS11 (Bitfield-Mask: 0x01) */
5102 #define GPIO_BSRR_BS11                                                     GPIO_BSRR_BS11_Msk
5103 #define GPIO_BSRR_BS10_Pos                                                 (10UL)   /*!<GPIO BSRR: BS10 (Bit 10) */
5104 #define GPIO_BSRR_BS10_Msk                                                 (0x400UL)    /*!< GPIO BSRR: BS10 (Bitfield-Mask: 0x01) */
5105 #define GPIO_BSRR_BS10                                                     GPIO_BSRR_BS10_Msk
5106 #define GPIO_BSRR_BS9_Pos                                                  (9UL)    /*!<GPIO BSRR: BS9 (Bit 9) */
5107 #define GPIO_BSRR_BS9_Msk                                                  (0x200UL)    /*!< GPIO BSRR: BS9 (Bitfield-Mask: 0x01) */
5108 #define GPIO_BSRR_BS9                                                      GPIO_BSRR_BS9_Msk
5109 #define GPIO_BSRR_BS8_Pos                                                  (8UL)    /*!<GPIO BSRR: BS8 (Bit 8) */
5110 #define GPIO_BSRR_BS8_Msk                                                  (0x100UL)    /*!< GPIO BSRR: BS8 (Bitfield-Mask: 0x01) */
5111 #define GPIO_BSRR_BS8                                                      GPIO_BSRR_BS8_Msk
5112 #define GPIO_BSRR_BS7_Pos                                                  (7UL)    /*!<GPIO BSRR: BS7 (Bit 7) */
5113 #define GPIO_BSRR_BS7_Msk                                                  (0x80UL)   /*!< GPIO BSRR: BS7 (Bitfield-Mask: 0x01) */
5114 #define GPIO_BSRR_BS7                                                      GPIO_BSRR_BS7_Msk
5115 #define GPIO_BSRR_BS6_Pos                                                  (6UL)    /*!<GPIO BSRR: BS6 (Bit 6) */
5116 #define GPIO_BSRR_BS6_Msk                                                  (0x40UL)   /*!< GPIO BSRR: BS6 (Bitfield-Mask: 0x01) */
5117 #define GPIO_BSRR_BS6                                                      GPIO_BSRR_BS6_Msk
5118 #define GPIO_BSRR_BS5_Pos                                                  (5UL)    /*!<GPIO BSRR: BS5 (Bit 5) */
5119 #define GPIO_BSRR_BS5_Msk                                                  (0x20UL)   /*!< GPIO BSRR: BS5 (Bitfield-Mask: 0x01) */
5120 #define GPIO_BSRR_BS5                                                      GPIO_BSRR_BS5_Msk
5121 #define GPIO_BSRR_BS4_Pos                                                  (4UL)    /*!<GPIO BSRR: BS4 (Bit 4) */
5122 #define GPIO_BSRR_BS4_Msk                                                  (0x10UL)   /*!< GPIO BSRR: BS4 (Bitfield-Mask: 0x01) */
5123 #define GPIO_BSRR_BS4                                                      GPIO_BSRR_BS4_Msk
5124 #define GPIO_BSRR_BS3_Pos                                                  (3UL)    /*!<GPIO BSRR: BS3 (Bit 3) */
5125 #define GPIO_BSRR_BS3_Msk                                                  (0x8UL)    /*!< GPIO BSRR: BS3 (Bitfield-Mask: 0x01) */
5126 #define GPIO_BSRR_BS3                                                      GPIO_BSRR_BS3_Msk
5127 #define GPIO_BSRR_BS2_Pos                                                  (2UL)    /*!<GPIO BSRR: BS2 (Bit 2) */
5128 #define GPIO_BSRR_BS2_Msk                                                  (0x4UL)    /*!< GPIO BSRR: BS2 (Bitfield-Mask: 0x01) */
5129 #define GPIO_BSRR_BS2                                                      GPIO_BSRR_BS2_Msk
5130 #define GPIO_BSRR_BS1_Pos                                                  (1UL)    /*!<GPIO BSRR: BS1 (Bit 1) */
5131 #define GPIO_BSRR_BS1_Msk                                                  (0x2UL)    /*!< GPIO BSRR: BS1 (Bitfield-Mask: 0x01) */
5132 #define GPIO_BSRR_BS1                                                      GPIO_BSRR_BS1_Msk
5133 #define GPIO_BSRR_BS0_Pos                                                  (0UL)    /*!<GPIO BSRR: BS0 (Bit 0) */
5134 #define GPIO_BSRR_BS0_Msk                                                  (0x1UL)    /*!< GPIO BSRR: BS0 (Bitfield-Mask: 0x01) */
5135 #define GPIO_BSRR_BS0                                                      GPIO_BSRR_BS0_Msk
5136 
5137 /* =====================================================    LCKR    ===================================================== */
5138 #define GPIO_LCKR_LCKK_Pos                                                 (16UL)   /*!<GPIO LCKR: LCKK (Bit 16) */
5139 #define GPIO_LCKR_LCKK_Msk                                                 (0x10000UL)    /*!< GPIO LCKR: LCKK (Bitfield-Mask: 0x01) */
5140 #define GPIO_LCKR_LCKK                                                     GPIO_LCKR_LCKK_Msk
5141 #define GPIO_LCKR_LCK15_Pos                                                (15UL)   /*!<GPIO LCKR: LCK15 (Bit 15) */
5142 #define GPIO_LCKR_LCK15_Msk                                                (0x8000UL)   /*!< GPIO LCKR: LCK15 (Bitfield-Mask: 0x01) */
5143 #define GPIO_LCKR_LCK15                                                    GPIO_LCKR_LCK15_Msk
5144 #define GPIO_LCKR_LCK14_Pos                                                (14UL)   /*!<GPIO LCKR: LCK14 (Bit 14) */
5145 #define GPIO_LCKR_LCK14_Msk                                                (0x4000UL)   /*!< GPIO LCKR: LCK14 (Bitfield-Mask: 0x01) */
5146 #define GPIO_LCKR_LCK14                                                    GPIO_LCKR_LCK14_Msk
5147 #define GPIO_LCKR_LCK13_Pos                                                (13UL)   /*!<GPIO LCKR: LCK13 (Bit 13) */
5148 #define GPIO_LCKR_LCK13_Msk                                                (0x2000UL)   /*!< GPIO LCKR: LCK13 (Bitfield-Mask: 0x01) */
5149 #define GPIO_LCKR_LCK13                                                    GPIO_LCKR_LCK13_Msk
5150 #define GPIO_LCKR_LCK12_Pos                                                (12UL)   /*!<GPIO LCKR: LCK12 (Bit 12) */
5151 #define GPIO_LCKR_LCK12_Msk                                                (0x1000UL)   /*!< GPIO LCKR: LCK12 (Bitfield-Mask: 0x01) */
5152 #define GPIO_LCKR_LCK12                                                    GPIO_LCKR_LCK12_Msk
5153 #define GPIO_LCKR_LCK11_Pos                                                (11UL)   /*!<GPIO LCKR: LCK11 (Bit 11) */
5154 #define GPIO_LCKR_LCK11_Msk                                                (0x800UL)    /*!< GPIO LCKR: LCK11 (Bitfield-Mask: 0x01) */
5155 #define GPIO_LCKR_LCK11                                                    GPIO_LCKR_LCK11_Msk
5156 #define GPIO_LCKR_LCK10_Pos                                                (10UL)   /*!<GPIO LCKR: LCK10 (Bit 10) */
5157 #define GPIO_LCKR_LCK10_Msk                                                (0x400UL)    /*!< GPIO LCKR: LCK10 (Bitfield-Mask: 0x01) */
5158 #define GPIO_LCKR_LCK10                                                    GPIO_LCKR_LCK10_Msk
5159 #define GPIO_LCKR_LCK9_Pos                                                 (9UL)    /*!<GPIO LCKR: LCK9 (Bit 9) */
5160 #define GPIO_LCKR_LCK9_Msk                                                 (0x200UL)    /*!< GPIO LCKR: LCK9 (Bitfield-Mask: 0x01) */
5161 #define GPIO_LCKR_LCK9                                                     GPIO_LCKR_LCK9_Msk
5162 #define GPIO_LCKR_LCK8_Pos                                                 (8UL)    /*!<GPIO LCKR: LCK8 (Bit 8) */
5163 #define GPIO_LCKR_LCK8_Msk                                                 (0x100UL)    /*!< GPIO LCKR: LCK8 (Bitfield-Mask: 0x01) */
5164 #define GPIO_LCKR_LCK8                                                     GPIO_LCKR_LCK8_Msk
5165 #define GPIO_LCKR_LCK7_Pos                                                 (7UL)    /*!<GPIO LCKR: LCK7 (Bit 7) */
5166 #define GPIO_LCKR_LCK7_Msk                                                 (0x80UL)   /*!< GPIO LCKR: LCK7 (Bitfield-Mask: 0x01) */
5167 #define GPIO_LCKR_LCK7                                                     GPIO_LCKR_LCK7_Msk
5168 #define GPIO_LCKR_LCK6_Pos                                                 (6UL)    /*!<GPIO LCKR: LCK6 (Bit 6) */
5169 #define GPIO_LCKR_LCK6_Msk                                                 (0x40UL)   /*!< GPIO LCKR: LCK6 (Bitfield-Mask: 0x01) */
5170 #define GPIO_LCKR_LCK6                                                     GPIO_LCKR_LCK6_Msk
5171 #define GPIO_LCKR_LCK5_Pos                                                 (5UL)    /*!<GPIO LCKR: LCK5 (Bit 5) */
5172 #define GPIO_LCKR_LCK5_Msk                                                 (0x20UL)   /*!< GPIO LCKR: LCK5 (Bitfield-Mask: 0x01) */
5173 #define GPIO_LCKR_LCK5                                                     GPIO_LCKR_LCK5_Msk
5174 #define GPIO_LCKR_LCK4_Pos                                                 (4UL)    /*!<GPIO LCKR: LCK4 (Bit 4) */
5175 #define GPIO_LCKR_LCK4_Msk                                                 (0x10UL)   /*!< GPIO LCKR: LCK4 (Bitfield-Mask: 0x01) */
5176 #define GPIO_LCKR_LCK4                                                     GPIO_LCKR_LCK4_Msk
5177 #define GPIO_LCKR_LCK3_Pos                                                 (3UL)    /*!<GPIO LCKR: LCK3 (Bit 3) */
5178 #define GPIO_LCKR_LCK3_Msk                                                 (0x8UL)    /*!< GPIO LCKR: LCK3 (Bitfield-Mask: 0x01) */
5179 #define GPIO_LCKR_LCK3                                                     GPIO_LCKR_LCK3_Msk
5180 #define GPIO_LCKR_LCK2_Pos                                                 (2UL)    /*!<GPIO LCKR: LCK2 (Bit 2) */
5181 #define GPIO_LCKR_LCK2_Msk                                                 (0x4UL)    /*!< GPIO LCKR: LCK2 (Bitfield-Mask: 0x01) */
5182 #define GPIO_LCKR_LCK2                                                     GPIO_LCKR_LCK2_Msk
5183 #define GPIO_LCKR_LCK1_Pos                                                 (1UL)    /*!<GPIO LCKR: LCK1 (Bit 1) */
5184 #define GPIO_LCKR_LCK1_Msk                                                 (0x2UL)    /*!< GPIO LCKR: LCK1 (Bitfield-Mask: 0x01) */
5185 #define GPIO_LCKR_LCK1                                                     GPIO_LCKR_LCK1_Msk
5186 #define GPIO_LCKR_LCK0_Pos                                                 (0UL)    /*!<GPIO LCKR: LCK0 (Bit 0) */
5187 #define GPIO_LCKR_LCK0_Msk                                                 (0x1UL)    /*!< GPIO LCKR: LCK0 (Bitfield-Mask: 0x01) */
5188 #define GPIO_LCKR_LCK0                                                     GPIO_LCKR_LCK0_Msk
5189 
5190 /* =====================================================    AFRL    ===================================================== */
5191 #define GPIO_AFRL_AFSEL7_Pos                                               (28UL)   /*!<GPIO AFRL: AFSEL7 (Bit 28) */
5192 #define GPIO_AFRL_AFSEL7_Msk                                               (0xf0000000UL)   /*!< GPIO AFRL: AFSEL7 (Bitfield-Mask: 0x0f) */
5193 #define GPIO_AFRL_AFSEL7                                                   GPIO_AFRL_AFSEL7_Msk
5194 #define GPIO_AFRL_AFSEL7_0                                                 (0x1U << GPIO_AFRL_AFSEL7_Pos)
5195 #define GPIO_AFRL_AFSEL7_1                                                 (0x2U << GPIO_AFRL_AFSEL7_Pos)
5196 #define GPIO_AFRL_AFSEL7_2                                                 (0x4U << GPIO_AFRL_AFSEL7_Pos)
5197 #define GPIO_AFRL_AFSEL7_3                                                 (0x8U << GPIO_AFRL_AFSEL7_Pos)
5198 #define GPIO_AFRL_AFSEL6_Pos                                               (24UL)   /*!<GPIO AFRL: AFSEL6 (Bit 24) */
5199 #define GPIO_AFRL_AFSEL6_Msk                                               (0xf000000UL)    /*!< GPIO AFRL: AFSEL6 (Bitfield-Mask: 0x0f) */
5200 #define GPIO_AFRL_AFSEL6                                                   GPIO_AFRL_AFSEL6_Msk
5201 #define GPIO_AFRL_AFSEL6_0                                                 (0x1U << GPIO_AFRL_AFSEL6_Pos)
5202 #define GPIO_AFRL_AFSEL6_1                                                 (0x2U << GPIO_AFRL_AFSEL6_Pos)
5203 #define GPIO_AFRL_AFSEL6_2                                                 (0x4U << GPIO_AFRL_AFSEL6_Pos)
5204 #define GPIO_AFRL_AFSEL6_3                                                 (0x8U << GPIO_AFRL_AFSEL6_Pos)
5205 #define GPIO_AFRL_AFSEL5_Pos                                               (20UL)   /*!<GPIO AFRL: AFSEL5 (Bit 20) */
5206 #define GPIO_AFRL_AFSEL5_Msk                                               (0xf00000UL)   /*!< GPIO AFRL: AFSEL5 (Bitfield-Mask: 0x0f) */
5207 #define GPIO_AFRL_AFSEL5                                                   GPIO_AFRL_AFSEL5_Msk
5208 #define GPIO_AFRL_AFSEL5_0                                                 (0x1U << GPIO_AFRL_AFSEL5_Pos)
5209 #define GPIO_AFRL_AFSEL5_1                                                 (0x2U << GPIO_AFRL_AFSEL5_Pos)
5210 #define GPIO_AFRL_AFSEL5_2                                                 (0x4U << GPIO_AFRL_AFSEL5_Pos)
5211 #define GPIO_AFRL_AFSEL5_3                                                 (0x8U << GPIO_AFRL_AFSEL5_Pos)
5212 #define GPIO_AFRL_AFSEL4_Pos                                               (16UL)   /*!<GPIO AFRL: AFSEL4 (Bit 16) */
5213 #define GPIO_AFRL_AFSEL4_Msk                                               (0xf0000UL)    /*!< GPIO AFRL: AFSEL4 (Bitfield-Mask: 0x0f) */
5214 #define GPIO_AFRL_AFSEL4                                                   GPIO_AFRL_AFSEL4_Msk
5215 #define GPIO_AFRL_AFSEL4_0                                                 (0x1U << GPIO_AFRL_AFSEL4_Pos)
5216 #define GPIO_AFRL_AFSEL4_1                                                 (0x2U << GPIO_AFRL_AFSEL4_Pos)
5217 #define GPIO_AFRL_AFSEL4_2                                                 (0x4U << GPIO_AFRL_AFSEL4_Pos)
5218 #define GPIO_AFRL_AFSEL4_3                                                 (0x8U << GPIO_AFRL_AFSEL4_Pos)
5219 #define GPIO_AFRL_AFSEL3_Pos                                               (12UL)   /*!<GPIO AFRL: AFSEL3 (Bit 12) */
5220 #define GPIO_AFRL_AFSEL3_Msk                                               (0xf000UL)   /*!< GPIO AFRL: AFSEL3 (Bitfield-Mask: 0x0f) */
5221 #define GPIO_AFRL_AFSEL3                                                   GPIO_AFRL_AFSEL3_Msk
5222 #define GPIO_AFRL_AFSEL3_0                                                 (0x1U << GPIO_AFRL_AFSEL3_Pos)
5223 #define GPIO_AFRL_AFSEL3_1                                                 (0x2U << GPIO_AFRL_AFSEL3_Pos)
5224 #define GPIO_AFRL_AFSEL3_2                                                 (0x4U << GPIO_AFRL_AFSEL3_Pos)
5225 #define GPIO_AFRL_AFSEL3_3                                                 (0x8U << GPIO_AFRL_AFSEL3_Pos)
5226 #define GPIO_AFRL_AFSEL2_Pos                                               (8UL)    /*!<GPIO AFRL: AFSEL2 (Bit 8) */
5227 #define GPIO_AFRL_AFSEL2_Msk                                               (0xf00UL)    /*!< GPIO AFRL: AFSEL2 (Bitfield-Mask: 0x0f) */
5228 #define GPIO_AFRL_AFSEL2                                                   GPIO_AFRL_AFSEL2_Msk
5229 #define GPIO_AFRL_AFSEL2_0                                                 (0x1U << GPIO_AFRL_AFSEL2_Pos)
5230 #define GPIO_AFRL_AFSEL2_1                                                 (0x2U << GPIO_AFRL_AFSEL2_Pos)
5231 #define GPIO_AFRL_AFSEL2_2                                                 (0x4U << GPIO_AFRL_AFSEL2_Pos)
5232 #define GPIO_AFRL_AFSEL2_3                                                 (0x8U << GPIO_AFRL_AFSEL2_Pos)
5233 #define GPIO_AFRL_AFSEL1_Pos                                               (4UL)    /*!<GPIO AFRL: AFSEL1 (Bit 4) */
5234 #define GPIO_AFRL_AFSEL1_Msk                                               (0xf0UL)   /*!< GPIO AFRL: AFSEL1 (Bitfield-Mask: 0x0f) */
5235 #define GPIO_AFRL_AFSEL1                                                   GPIO_AFRL_AFSEL1_Msk
5236 #define GPIO_AFRL_AFSEL1_0                                                 (0x1U << GPIO_AFRL_AFSEL1_Pos)
5237 #define GPIO_AFRL_AFSEL1_1                                                 (0x2U << GPIO_AFRL_AFSEL1_Pos)
5238 #define GPIO_AFRL_AFSEL1_2                                                 (0x4U << GPIO_AFRL_AFSEL1_Pos)
5239 #define GPIO_AFRL_AFSEL1_3                                                 (0x8U << GPIO_AFRL_AFSEL1_Pos)
5240 #define GPIO_AFRL_AFSEL0_Pos                                               (0UL)    /*!<GPIO AFRL: AFSEL0 (Bit 0) */
5241 #define GPIO_AFRL_AFSEL0_Msk                                               (0xfUL)    /*!< GPIO AFRL: AFSEL0 (Bitfield-Mask: 0x0f) */
5242 #define GPIO_AFRL_AFSEL0                                                   GPIO_AFRL_AFSEL0_Msk
5243 #define GPIO_AFRL_AFSEL0_0                                                 (0x1U << GPIO_AFRL_AFSEL0_Pos)
5244 #define GPIO_AFRL_AFSEL0_1                                                 (0x2U << GPIO_AFRL_AFSEL0_Pos)
5245 #define GPIO_AFRL_AFSEL0_2                                                 (0x4U << GPIO_AFRL_AFSEL0_Pos)
5246 #define GPIO_AFRL_AFSEL0_3                                                 (0x8U << GPIO_AFRL_AFSEL0_Pos)
5247 
5248 /* =====================================================    AFRH    ===================================================== */
5249 #define GPIO_AFRH_AFSEL15_Pos                                              (28UL)   /*!<GPIO AFRH: AFSEL15 (Bit 28) */
5250 #define GPIO_AFRH_AFSEL15_Msk                                              (0xf0000000UL)   /*!< GPIO AFRH: AFSEL15 (Bitfield-Mask: 0x0f) */
5251 #define GPIO_AFRH_AFSEL15                                                  GPIO_AFRH_AFSEL15_Msk
5252 #define GPIO_AFRH_AFSEL15_0                                                (0x1U << GPIO_AFRH_AFSEL15_Pos)
5253 #define GPIO_AFRH_AFSEL15_1                                                (0x2U << GPIO_AFRH_AFSEL15_Pos)
5254 #define GPIO_AFRH_AFSEL15_2                                                (0x4U << GPIO_AFRH_AFSEL15_Pos)
5255 #define GPIO_AFRH_AFSEL15_3                                                (0x8U << GPIO_AFRH_AFSEL15_Pos)
5256 #define GPIO_AFRH_AFSEL14_Pos                                              (24UL)   /*!<GPIO AFRH: AFSEL14 (Bit 24) */
5257 #define GPIO_AFRH_AFSEL14_Msk                                              (0xf000000UL)    /*!< GPIO AFRH: AFSEL14 (Bitfield-Mask: 0x0f) */
5258 #define GPIO_AFRH_AFSEL14                                                  GPIO_AFRH_AFSEL14_Msk
5259 #define GPIO_AFRH_AFSEL14_0                                                (0x1U << GPIO_AFRH_AFSEL14_Pos)
5260 #define GPIO_AFRH_AFSEL14_1                                                (0x2U << GPIO_AFRH_AFSEL14_Pos)
5261 #define GPIO_AFRH_AFSEL14_2                                                (0x4U << GPIO_AFRH_AFSEL14_Pos)
5262 #define GPIO_AFRH_AFSEL14_3                                                (0x8U << GPIO_AFRH_AFSEL14_Pos)
5263 #define GPIO_AFRH_AFSEL13_Pos                                              (20UL)   /*!<GPIO AFRH: AFSEL13 (Bit 20) */
5264 #define GPIO_AFRH_AFSEL13_Msk                                              (0xf00000UL)   /*!< GPIO AFRH: AFSEL13 (Bitfield-Mask: 0x0f) */
5265 #define GPIO_AFRH_AFSEL13                                                  GPIO_AFRH_AFSEL13_Msk
5266 #define GPIO_AFRH_AFSEL13_0                                                (0x1U << GPIO_AFRH_AFSEL13_Pos)
5267 #define GPIO_AFRH_AFSEL13_1                                                (0x2U << GPIO_AFRH_AFSEL13_Pos)
5268 #define GPIO_AFRH_AFSEL13_2                                                (0x4U << GPIO_AFRH_AFSEL13_Pos)
5269 #define GPIO_AFRH_AFSEL13_3                                                (0x8U << GPIO_AFRH_AFSEL13_Pos)
5270 #define GPIO_AFRH_AFSEL12_Pos                                              (16UL)   /*!<GPIO AFRH: AFSEL12 (Bit 16) */
5271 #define GPIO_AFRH_AFSEL12_Msk                                              (0xf0000UL)    /*!< GPIO AFRH: AFSEL12 (Bitfield-Mask: 0x0f) */
5272 #define GPIO_AFRH_AFSEL12                                                  GPIO_AFRH_AFSEL12_Msk
5273 #define GPIO_AFRH_AFSEL12_0                                                (0x1U << GPIO_AFRH_AFSEL12_Pos)
5274 #define GPIO_AFRH_AFSEL12_1                                                (0x2U << GPIO_AFRH_AFSEL12_Pos)
5275 #define GPIO_AFRH_AFSEL12_2                                                (0x4U << GPIO_AFRH_AFSEL12_Pos)
5276 #define GPIO_AFRH_AFSEL12_3                                                (0x8U << GPIO_AFRH_AFSEL12_Pos)
5277 #define GPIO_AFRH_AFSEL11_Pos                                              (12UL)   /*!<GPIO AFRH: AFSEL11 (Bit 12) */
5278 #define GPIO_AFRH_AFSEL11_Msk                                              (0xf000UL)   /*!< GPIO AFRH: AFSEL11 (Bitfield-Mask: 0x0f) */
5279 #define GPIO_AFRH_AFSEL11                                                  GPIO_AFRH_AFSEL11_Msk
5280 #define GPIO_AFRH_AFSEL11_0                                                (0x1U << GPIO_AFRH_AFSEL11_Pos)
5281 #define GPIO_AFRH_AFSEL11_1                                                (0x2U << GPIO_AFRH_AFSEL11_Pos)
5282 #define GPIO_AFRH_AFSEL11_2                                                (0x4U << GPIO_AFRH_AFSEL11_Pos)
5283 #define GPIO_AFRH_AFSEL11_3                                                (0x8U << GPIO_AFRH_AFSEL11_Pos)
5284 #define GPIO_AFRH_AFSEL10_Pos                                              (8UL)    /*!<GPIO AFRH: AFSEL10 (Bit 8) */
5285 #define GPIO_AFRH_AFSEL10_Msk                                              (0xf00UL)    /*!< GPIO AFRH: AFSEL10 (Bitfield-Mask: 0x0f) */
5286 #define GPIO_AFRH_AFSEL10                                                  GPIO_AFRH_AFSEL10_Msk
5287 #define GPIO_AFRH_AFSEL10_0                                                (0x1U << GPIO_AFRH_AFSEL10_Pos)
5288 #define GPIO_AFRH_AFSEL10_1                                                (0x2U << GPIO_AFRH_AFSEL10_Pos)
5289 #define GPIO_AFRH_AFSEL10_2                                                (0x4U << GPIO_AFRH_AFSEL10_Pos)
5290 #define GPIO_AFRH_AFSEL10_3                                                (0x8U << GPIO_AFRH_AFSEL10_Pos)
5291 #define GPIO_AFRH_AFSEL9_Pos                                               (4UL)    /*!<GPIO AFRH: AFSEL9 (Bit 4) */
5292 #define GPIO_AFRH_AFSEL9_Msk                                               (0xf0UL)   /*!< GPIO AFRH: AFSEL9 (Bitfield-Mask: 0x0f) */
5293 #define GPIO_AFRH_AFSEL9                                                   GPIO_AFRH_AFSEL9_Msk
5294 #define GPIO_AFRH_AFSEL9_0                                                 (0x1U << GPIO_AFRH_AFSEL9_Pos)
5295 #define GPIO_AFRH_AFSEL9_1                                                 (0x2U << GPIO_AFRH_AFSEL9_Pos)
5296 #define GPIO_AFRH_AFSEL9_2                                                 (0x4U << GPIO_AFRH_AFSEL9_Pos)
5297 #define GPIO_AFRH_AFSEL9_3                                                 (0x8U << GPIO_AFRH_AFSEL9_Pos)
5298 #define GPIO_AFRH_AFSEL8_Pos                                               (0UL)    /*!<GPIO AFRH: AFSEL8 (Bit 0) */
5299 #define GPIO_AFRH_AFSEL8_Msk                                               (0xfUL)    /*!< GPIO AFRH: AFSEL8 (Bitfield-Mask: 0x0f) */
5300 #define GPIO_AFRH_AFSEL8                                                   GPIO_AFRH_AFSEL8_Msk
5301 #define GPIO_AFRH_AFSEL8_0                                                 (0x1U << GPIO_AFRH_AFSEL8_Pos)
5302 #define GPIO_AFRH_AFSEL8_1                                                 (0x2U << GPIO_AFRH_AFSEL8_Pos)
5303 #define GPIO_AFRH_AFSEL8_2                                                 (0x4U << GPIO_AFRH_AFSEL8_Pos)
5304 #define GPIO_AFRH_AFSEL8_3                                                 (0x8U << GPIO_AFRH_AFSEL8_Pos)
5305 
5306 /* =====================================================    BRR    ===================================================== */
5307 #define GPIO_BRR_BR15_Pos                                                  (15UL)   /*!<GPIO BRR: BR15 (Bit 15) */
5308 #define GPIO_BRR_BR15_Msk                                                  (0x8000UL)   /*!< GPIO BRR: BR15 (Bitfield-Mask: 0x01) */
5309 #define GPIO_BRR_BR15                                                      GPIO_BRR_BR15_Msk
5310 #define GPIO_BRR_BR14_Pos                                                  (14UL)   /*!<GPIO BRR: BR14 (Bit 14) */
5311 #define GPIO_BRR_BR14_Msk                                                  (0x4000UL)   /*!< GPIO BRR: BR14 (Bitfield-Mask: 0x01) */
5312 #define GPIO_BRR_BR14                                                      GPIO_BRR_BR14_Msk
5313 #define GPIO_BRR_BR13_Pos                                                  (13UL)   /*!<GPIO BRR: BR13 (Bit 13) */
5314 #define GPIO_BRR_BR13_Msk                                                  (0x2000UL)   /*!< GPIO BRR: BR13 (Bitfield-Mask: 0x01) */
5315 #define GPIO_BRR_BR13                                                      GPIO_BRR_BR13_Msk
5316 #define GPIO_BRR_BR12_Pos                                                  (12UL)   /*!<GPIO BRR: BR12 (Bit 12) */
5317 #define GPIO_BRR_BR12_Msk                                                  (0x1000UL)   /*!< GPIO BRR: BR12 (Bitfield-Mask: 0x01) */
5318 #define GPIO_BRR_BR12                                                      GPIO_BRR_BR12_Msk
5319 #define GPIO_BRR_BR11_Pos                                                  (11UL)   /*!<GPIO BRR: BR11 (Bit 11) */
5320 #define GPIO_BRR_BR11_Msk                                                  (0x800UL)    /*!< GPIO BRR: BR11 (Bitfield-Mask: 0x01) */
5321 #define GPIO_BRR_BR11                                                      GPIO_BRR_BR11_Msk
5322 #define GPIO_BRR_BR10_Pos                                                  (10UL)   /*!<GPIO BRR: BR10 (Bit 10) */
5323 #define GPIO_BRR_BR10_Msk                                                  (0x400UL)    /*!< GPIO BRR: BR10 (Bitfield-Mask: 0x01) */
5324 #define GPIO_BRR_BR10                                                      GPIO_BRR_BR10_Msk
5325 #define GPIO_BRR_BR9_Pos                                                   (9UL)    /*!<GPIO BRR: BR9 (Bit 9) */
5326 #define GPIO_BRR_BR9_Msk                                                   (0x200UL)    /*!< GPIO BRR: BR9 (Bitfield-Mask: 0x01) */
5327 #define GPIO_BRR_BR9                                                       GPIO_BRR_BR9_Msk
5328 #define GPIO_BRR_BR8_Pos                                                   (8UL)    /*!<GPIO BRR: BR8 (Bit 8) */
5329 #define GPIO_BRR_BR8_Msk                                                   (0x100UL)    /*!< GPIO BRR: BR8 (Bitfield-Mask: 0x01) */
5330 #define GPIO_BRR_BR8                                                       GPIO_BRR_BR8_Msk
5331 #define GPIO_BRR_BR7_Pos                                                   (7UL)    /*!<GPIO BRR: BR7 (Bit 7) */
5332 #define GPIO_BRR_BR7_Msk                                                   (0x80UL)   /*!< GPIO BRR: BR7 (Bitfield-Mask: 0x01) */
5333 #define GPIO_BRR_BR7                                                       GPIO_BRR_BR7_Msk
5334 #define GPIO_BRR_BR6_Pos                                                   (6UL)    /*!<GPIO BRR: BR6 (Bit 6) */
5335 #define GPIO_BRR_BR6_Msk                                                   (0x40UL)   /*!< GPIO BRR: BR6 (Bitfield-Mask: 0x01) */
5336 #define GPIO_BRR_BR6                                                       GPIO_BRR_BR6_Msk
5337 #define GPIO_BRR_BR5_Pos                                                   (5UL)    /*!<GPIO BRR: BR5 (Bit 5) */
5338 #define GPIO_BRR_BR5_Msk                                                   (0x20UL)   /*!< GPIO BRR: BR5 (Bitfield-Mask: 0x01) */
5339 #define GPIO_BRR_BR5                                                       GPIO_BRR_BR5_Msk
5340 #define GPIO_BRR_BR4_Pos                                                   (4UL)    /*!<GPIO BRR: BR4 (Bit 4) */
5341 #define GPIO_BRR_BR4_Msk                                                   (0x10UL)   /*!< GPIO BRR: BR4 (Bitfield-Mask: 0x01) */
5342 #define GPIO_BRR_BR4                                                       GPIO_BRR_BR4_Msk
5343 #define GPIO_BRR_BR3_Pos                                                   (3UL)    /*!<GPIO BRR: BR3 (Bit 3) */
5344 #define GPIO_BRR_BR3_Msk                                                   (0x8UL)    /*!< GPIO BRR: BR3 (Bitfield-Mask: 0x01) */
5345 #define GPIO_BRR_BR3                                                       GPIO_BRR_BR3_Msk
5346 #define GPIO_BRR_BR2_Pos                                                   (2UL)    /*!<GPIO BRR: BR2 (Bit 2) */
5347 #define GPIO_BRR_BR2_Msk                                                   (0x4UL)    /*!< GPIO BRR: BR2 (Bitfield-Mask: 0x01) */
5348 #define GPIO_BRR_BR2                                                       GPIO_BRR_BR2_Msk
5349 #define GPIO_BRR_BR1_Pos                                                   (1UL)    /*!<GPIO BRR: BR1 (Bit 1) */
5350 #define GPIO_BRR_BR1_Msk                                                   (0x2UL)    /*!< GPIO BRR: BR1 (Bitfield-Mask: 0x01) */
5351 #define GPIO_BRR_BR1                                                       GPIO_BRR_BR1_Msk
5352 #define GPIO_BRR_BR0_Pos                                                   (0UL)    /*!<GPIO BRR: BR0 (Bit 0) */
5353 #define GPIO_BRR_BR0_Msk                                                   (0x1UL)    /*!< GPIO BRR: BR0 (Bitfield-Mask: 0x01) */
5354 #define GPIO_BRR_BR0                                                       GPIO_BRR_BR0_Msk
5355 
5356 
5357 /* =========================================================================================================================== */
5358 /*=====================                                       TIM                                       ===================== */
5359 /* =========================================================================================================================== */
5360 
5361 /* =====================================================    CR1    ===================================================== */
5362 #define TIM_CR1_UIFREMAP_Pos                                               (11UL)   /*!<TIM CR1: UIFREMAP (Bit 11) */
5363 #define TIM_CR1_UIFREMAP_Msk                                               (0x800UL)    /*!< TIM CR1: UIFREMAP (Bitfield-Mask: 0x01) */
5364 #define TIM_CR1_UIFREMAP                                                   TIM_CR1_UIFREMAP_Msk
5365 #define TIM_CR1_CKD_Pos                                                    (8UL)    /*!<TIM CR1: CKD (Bit 8) */
5366 #define TIM_CR1_CKD_Msk                                                    (0x300UL)    /*!< TIM CR1: CKD (Bitfield-Mask: 0x03) */
5367 #define TIM_CR1_CKD                                                        TIM_CR1_CKD_Msk
5368 #define TIM_CR1_CKD_0                                                      (0x1U << TIM_CR1_CKD_Pos)
5369 #define TIM_CR1_CKD_1                                                      (0x2U << TIM_CR1_CKD_Pos)
5370 #define TIM_CR1_ARPE_Pos                                                   (7UL)    /*!<TIM CR1: ARPE (Bit 7) */
5371 #define TIM_CR1_ARPE_Msk                                                   (0x80UL)   /*!< TIM CR1: ARPE (Bitfield-Mask: 0x01) */
5372 #define TIM_CR1_ARPE                                                       TIM_CR1_ARPE_Msk
5373 #define TIM_CR1_CMS_Pos                                                    (5UL)    /*!<TIM CR1: CMS (Bit 5) */
5374 #define TIM_CR1_CMS_Msk                                                    (0x60UL)   /*!< TIM CR1: CMS (Bitfield-Mask: 0x03) */
5375 #define TIM_CR1_CMS                                                        TIM_CR1_CMS_Msk
5376 #define TIM_CR1_CMS_0                                                      (0x1U << TIM_CR1_CMS_Pos)
5377 #define TIM_CR1_CMS_1                                                      (0x2U << TIM_CR1_CMS_Pos)
5378 #define TIM_CR1_DIR_Pos                                                    (4UL)    /*!<TIM CR1: DIR (Bit 4) */
5379 #define TIM_CR1_DIR_Msk                                                    (0x10UL)   /*!< TIM CR1: DIR (Bitfield-Mask: 0x01) */
5380 #define TIM_CR1_DIR                                                        TIM_CR1_DIR_Msk
5381 #define TIM_CR1_OPM_Pos                                                    (3UL)    /*!<TIM CR1: OPM (Bit 3) */
5382 #define TIM_CR1_OPM_Msk                                                    (0x8UL)    /*!< TIM CR1: OPM (Bitfield-Mask: 0x01) */
5383 #define TIM_CR1_OPM                                                        TIM_CR1_OPM_Msk
5384 #define TIM_CR1_URS_Pos                                                    (2UL)    /*!<TIM CR1: URS (Bit 2) */
5385 #define TIM_CR1_URS_Msk                                                    (0x4UL)    /*!< TIM CR1: URS (Bitfield-Mask: 0x01) */
5386 #define TIM_CR1_URS                                                        TIM_CR1_URS_Msk
5387 #define TIM_CR1_UDIS_Pos                                                   (1UL)    /*!<TIM CR1: UDIS (Bit 1) */
5388 #define TIM_CR1_UDIS_Msk                                                   (0x2UL)    /*!< TIM CR1: UDIS (Bitfield-Mask: 0x01) */
5389 #define TIM_CR1_UDIS                                                       TIM_CR1_UDIS_Msk
5390 #define TIM_CR1_CEN_Pos                                                    (0UL)    /*!<TIM CR1: CEN (Bit 0) */
5391 #define TIM_CR1_CEN_Msk                                                    (0x1UL)    /*!< TIM CR1: CEN (Bitfield-Mask: 0x01) */
5392 #define TIM_CR1_CEN                                                        TIM_CR1_CEN_Msk
5393 
5394 /* =====================================================    CR2    ===================================================== */
5395 #define TIM_CR2_OIS6_Pos                                                   (18UL)   /*!<TIM CR2: OIS6 (Bit 18) */
5396 #define TIM_CR2_OIS6_Msk                                                   (0x40000UL)    /*!< TIM CR2: OIS6 (Bitfield-Mask: 0x01) */
5397 #define TIM_CR2_OIS6                                                       TIM_CR2_OIS6_Msk
5398 #define TIM_CR2_OIS5_Pos                                                   (16UL)   /*!<TIM CR2: OIS5 (Bit 16) */
5399 #define TIM_CR2_OIS5_Msk                                                   (0x10000UL)    /*!< TIM CR2: OIS5 (Bitfield-Mask: 0x01) */
5400 #define TIM_CR2_OIS5                                                       TIM_CR2_OIS5_Msk
5401 #define TIM_CR2_OIS4_Pos                                                   (14UL)   /*!<TIM CR2: OIS4 (Bit 14) */
5402 #define TIM_CR2_OIS4_Msk                                                   (0x4000UL)   /*!< TIM CR2: OIS4 (Bitfield-Mask: 0x01) */
5403 #define TIM_CR2_OIS4                                                       TIM_CR2_OIS4_Msk
5404 #define TIM_CR2_OIS3N_Pos                                                  (13UL)   /*!<TIM CR2: OIS3N (Bit 13) */
5405 #define TIM_CR2_OIS3N_Msk                                                  (0x2000UL)   /*!< TIM CR2: OIS3N (Bitfield-Mask: 0x01) */
5406 #define TIM_CR2_OIS3N                                                      TIM_CR2_OIS3N_Msk
5407 #define TIM_CR2_OIS3_Pos                                                   (12UL)   /*!<TIM CR2: OIS3 (Bit 12) */
5408 #define TIM_CR2_OIS3_Msk                                                   (0x1000UL)   /*!< TIM CR2: OIS3 (Bitfield-Mask: 0x01) */
5409 #define TIM_CR2_OIS3                                                       TIM_CR2_OIS3_Msk
5410 #define TIM_CR2_OIS2N_Pos                                                  (11UL)   /*!<TIM CR2: OIS2N (Bit 11) */
5411 #define TIM_CR2_OIS2N_Msk                                                  (0x800UL)    /*!< TIM CR2: OIS2N (Bitfield-Mask: 0x01) */
5412 #define TIM_CR2_OIS2N                                                      TIM_CR2_OIS2N_Msk
5413 #define TIM_CR2_OIS2_Pos                                                   (10UL)   /*!<TIM CR2: OIS2 (Bit 10) */
5414 #define TIM_CR2_OIS2_Msk                                                   (0x400UL)    /*!< TIM CR2: OIS2 (Bitfield-Mask: 0x01) */
5415 #define TIM_CR2_OIS2                                                       TIM_CR2_OIS2_Msk
5416 #define TIM_CR2_OIS1N_Pos                                                  (9UL)    /*!<TIM CR2: OIS1N (Bit 9) */
5417 #define TIM_CR2_OIS1N_Msk                                                  (0x200UL)    /*!< TIM CR2: OIS1N (Bitfield-Mask: 0x01) */
5418 #define TIM_CR2_OIS1N                                                      TIM_CR2_OIS1N_Msk
5419 #define TIM_CR2_OIS1_Pos                                                   (8UL)    /*!<TIM CR2: OIS1 (Bit 8) */
5420 #define TIM_CR2_OIS1_Msk                                                   (0x100UL)    /*!< TIM CR2: OIS1 (Bitfield-Mask: 0x01) */
5421 #define TIM_CR2_OIS1                                                       TIM_CR2_OIS1_Msk
5422 #define TIM_CR2_TI1S_Pos                                                   (7UL)    /*!<TIM CR2: TI1S (Bit 7) */
5423 #define TIM_CR2_TI1S_Msk                                                   (0x80UL)   /*!< TIM CR2: TI1S (Bitfield-Mask: 0x01) */
5424 #define TIM_CR2_TI1S                                                       TIM_CR2_TI1S_Msk
5425 #define TIM_CR2_CCUS_Pos                                                   (2UL)    /*!<TIM CR2: CCUS (Bit 2) */
5426 #define TIM_CR2_CCUS_Msk                                                   (0x4UL)    /*!< TIM CR2: CCUS (Bitfield-Mask: 0x01) */
5427 #define TIM_CR2_CCUS                                                       TIM_CR2_CCUS_Msk
5428 #define TIM_CR2_CCPC_Pos                                                   (0UL)    /*!<TIM CR2: CCPC (Bit 0) */
5429 #define TIM_CR2_CCPC_Msk                                                   (0x1UL)    /*!< TIM CR2: CCPC (Bitfield-Mask: 0x01) */
5430 #define TIM_CR2_CCPC                                                       TIM_CR2_CCPC_Msk
5431 
5432 /* =====================================================    SMCR    ===================================================== */
5433 #define TIM_SMCR_ETP_Pos                                                   (15UL)   /*!<TIM SMCR: ETP (Bit 15) */
5434 #define TIM_SMCR_ETP_Msk                                                   (0x8000UL)   /*!< TIM SMCR: ETP (Bitfield-Mask: 0x01) */
5435 #define TIM_SMCR_ETP                                                       TIM_SMCR_ETP_Msk
5436 #define TIM_SMCR_ECE_Pos                                                   (14UL)   /*!<TIM SMCR: ECE (Bit 14) */
5437 #define TIM_SMCR_ECE_Msk                                                   (0x4000UL)   /*!< TIM SMCR: ECE (Bitfield-Mask: 0x01) */
5438 #define TIM_SMCR_ECE                                                       TIM_SMCR_ECE_Msk
5439 #define TIM_SMCR_ETPS_Pos                                                  (12UL)   /*!<TIM SMCR: ETPS (Bit 12) */
5440 #define TIM_SMCR_ETPS_Msk                                                  (0x3000UL)   /*!< TIM SMCR: ETPS (Bitfield-Mask: 0x03) */
5441 #define TIM_SMCR_ETPS                                                      TIM_SMCR_ETPS_Msk
5442 #define TIM_SMCR_ETPS_0                                                    (0x1U << TIM_SMCR_ETPS_Pos)
5443 #define TIM_SMCR_ETPS_1                                                    (0x2U << TIM_SMCR_ETPS_Pos)
5444 #define TIM_SMCR_ETF_Pos                                                   (8UL)    /*!<TIM SMCR: ETF (Bit 8) */
5445 #define TIM_SMCR_ETF_Msk                                                   (0xf00UL)    /*!< TIM SMCR: ETF (Bitfield-Mask: 0x0f) */
5446 #define TIM_SMCR_ETF                                                       TIM_SMCR_ETF_Msk
5447 #define TIM_SMCR_ETF_0                                                     (0x1U << TIM_SMCR_ETF_Pos)
5448 #define TIM_SMCR_ETF_1                                                     (0x2U << TIM_SMCR_ETF_Pos)
5449 #define TIM_SMCR_ETF_2                                                     (0x4U << TIM_SMCR_ETF_Pos)
5450 #define TIM_SMCR_ETF_3                                                     (0x8U << TIM_SMCR_ETF_Pos)
5451 #define TIM_SMCR_TS_Pos                                                    (4UL)    /*!<TIM SMCR: TS (Bit 4) */
5452 #define TIM_SMCR_TS_Msk                                                    (0x70UL)   /*!< TIM SMCR: TS (Bitfield-Mask: 0x07) */
5453 #define TIM_SMCR_TS                                                        TIM_SMCR_TS_Msk
5454 #define TIM_SMCR_TS_0                                                      (0x1U << TIM_SMCR_TS_Pos)
5455 #define TIM_SMCR_TS_1                                                      (0x2U << TIM_SMCR_TS_Pos)
5456 #define TIM_SMCR_TS_2                                                      (0x4U << TIM_SMCR_TS_Pos)
5457 #define TIM_SMCR_OCCS_Pos                                                  (3UL)    /*!<TIM SMCR: OCCS (Bit 3) */
5458 #define TIM_SMCR_OCCS_Msk                                                  (0x8UL)    /*!< TIM SMCR: OCCS (Bitfield-Mask: 0x01) */
5459 #define TIM_SMCR_OCCS                                                      TIM_SMCR_OCCS_Msk
5460 #define TIM_SMCR_SMS_Pos                                                   (0UL)    /*!<TIM SMCR: SMS (Bit 0) */
5461 #define TIM_SMCR_SMS_Msk                                                   (0x10007UL)    /*!< TIM SMCR: SMS (Bitfield-Mask: 0x10007) */
5462 #define TIM_SMCR_SMS                                                       TIM_SMCR_SMS_Msk
5463 #define TIM_SMCR_SMS_0                                                     (0x1U << TIM_SMCR_SMS_Pos)
5464 #define TIM_SMCR_SMS_1                                                     (0x2U << TIM_SMCR_SMS_Pos)
5465 #define TIM_SMCR_SMS_2                                                     (0x4U << TIM_SMCR_SMS_Pos)
5466 #define TIM_SMCR_SMS_3                                                     (0x10000U << TIM_SMCR_SMS_Pos)
5467 
5468 /* =====================================================    DIER    ===================================================== */
5469 #define TIM_DIER_BIE_Pos                                                   (7UL)    /*!<TIM DIER: BIE (Bit 7) */
5470 #define TIM_DIER_BIE_Msk                                                   (0x80UL)   /*!< TIM DIER: BIE (Bitfield-Mask: 0x01) */
5471 #define TIM_DIER_BIE                                                       TIM_DIER_BIE_Msk
5472 #define TIM_DIER_TIE_Pos                                                   (6UL)    /*!<TIM DIER: TIE (Bit 6) */
5473 #define TIM_DIER_TIE_Msk                                                   (0x40UL)   /*!< TIM DIER: TIE (Bitfield-Mask: 0x01) */
5474 #define TIM_DIER_TIE                                                       TIM_DIER_TIE_Msk
5475 #define TIM_DIER_COMIE_Pos                                                 (5UL)    /*!<TIM DIER: COMIE (Bit 5) */
5476 #define TIM_DIER_COMIE_Msk                                                 (0x20UL)   /*!< TIM DIER: COMIE (Bitfield-Mask: 0x01) */
5477 #define TIM_DIER_COMIE                                                     TIM_DIER_COMIE_Msk
5478 #define TIM_DIER_CC4IE_Pos                                                 (4UL)    /*!<TIM DIER: CC4IE (Bit 4) */
5479 #define TIM_DIER_CC4IE_Msk                                                 (0x10UL)   /*!< TIM DIER: CC4IE (Bitfield-Mask: 0x01) */
5480 #define TIM_DIER_CC4IE                                                     TIM_DIER_CC4IE_Msk
5481 #define TIM_DIER_CC3IE_Pos                                                 (3UL)    /*!<TIM DIER: CC3IE (Bit 3) */
5482 #define TIM_DIER_CC3IE_Msk                                                 (0x8UL)    /*!< TIM DIER: CC3IE (Bitfield-Mask: 0x01) */
5483 #define TIM_DIER_CC3IE                                                     TIM_DIER_CC3IE_Msk
5484 #define TIM_DIER_CC2IE_Pos                                                 (2UL)    /*!<TIM DIER: CC2IE (Bit 2) */
5485 #define TIM_DIER_CC2IE_Msk                                                 (0x4UL)    /*!< TIM DIER: CC2IE (Bitfield-Mask: 0x01) */
5486 #define TIM_DIER_CC2IE                                                     TIM_DIER_CC2IE_Msk
5487 #define TIM_DIER_CC1IE_Pos                                                 (1UL)    /*!<TIM DIER: CC1IE (Bit 1) */
5488 #define TIM_DIER_CC1IE_Msk                                                 (0x2UL)    /*!< TIM DIER: CC1IE (Bitfield-Mask: 0x01) */
5489 #define TIM_DIER_CC1IE                                                     TIM_DIER_CC1IE_Msk
5490 #define TIM_DIER_UIE_Pos                                                   (0UL)    /*!<TIM DIER: UIE (Bit 0) */
5491 #define TIM_DIER_UIE_Msk                                                   (0x1UL)    /*!< TIM DIER: UIE (Bitfield-Mask: 0x01) */
5492 #define TIM_DIER_UIE                                                       TIM_DIER_UIE_Msk
5493 
5494 /* =====================================================    SR    ===================================================== */
5495 #define TIM_SR_CC6IF_Pos                                                   (17UL)   /*!<TIM SR: CC6IF (Bit 17) */
5496 #define TIM_SR_CC6IF_Msk                                                   (0x20000UL)    /*!< TIM SR: CC6IF (Bitfield-Mask: 0x01) */
5497 #define TIM_SR_CC6IF                                                       TIM_SR_CC6IF_Msk
5498 #define TIM_SR_CC5IF_Pos                                                   (16UL)   /*!<TIM SR: CC5IF (Bit 16) */
5499 #define TIM_SR_CC5IF_Msk                                                   (0x10000UL)    /*!< TIM SR: CC5IF (Bitfield-Mask: 0x01) */
5500 #define TIM_SR_CC5IF                                                       TIM_SR_CC5IF_Msk
5501 #define TIM_SR_CC4OF_Pos                                                   (12UL)   /*!<TIM SR: CC4OF (Bit 12) */
5502 #define TIM_SR_CC4OF_Msk                                                   (0x1000UL)   /*!< TIM SR: CC4OF (Bitfield-Mask: 0x01) */
5503 #define TIM_SR_CC4OF                                                       TIM_SR_CC4OF_Msk
5504 #define TIM_SR_CC3OF_Pos                                                   (11UL)   /*!<TIM SR: CC3OF (Bit 11) */
5505 #define TIM_SR_CC3OF_Msk                                                   (0x800UL)    /*!< TIM SR: CC3OF (Bitfield-Mask: 0x01) */
5506 #define TIM_SR_CC3OF                                                       TIM_SR_CC3OF_Msk
5507 #define TIM_SR_CC2OF_Pos                                                   (10UL)   /*!<TIM SR: CC2OF (Bit 10) */
5508 #define TIM_SR_CC2OF_Msk                                                   (0x400UL)    /*!< TIM SR: CC2OF (Bitfield-Mask: 0x01) */
5509 #define TIM_SR_CC2OF                                                       TIM_SR_CC2OF_Msk
5510 #define TIM_SR_CC1OF_Pos                                                   (9UL)    /*!<TIM SR: CC1OF (Bit 9) */
5511 #define TIM_SR_CC1OF_Msk                                                   (0x200UL)    /*!< TIM SR: CC1OF (Bitfield-Mask: 0x01) */
5512 #define TIM_SR_CC1OF                                                       TIM_SR_CC1OF_Msk
5513 #define TIM_SR_B2IF_Pos                                                    (8UL)    /*!<TIM SR: B2IF (Bit 8) */
5514 #define TIM_SR_B2IF_Msk                                                    (0x100UL)    /*!< TIM SR: B2IF (Bitfield-Mask: 0x01) */
5515 #define TIM_SR_B2IF                                                        TIM_SR_B2IF_Msk
5516 #define TIM_SR_BIF_Pos                                                     (7UL)    /*!<TIM SR: BIF (Bit 7) */
5517 #define TIM_SR_BIF_Msk                                                     (0x80UL)   /*!< TIM SR: BIF (Bitfield-Mask: 0x01) */
5518 #define TIM_SR_BIF                                                         TIM_SR_BIF_Msk
5519 #define TIM_SR_TIF_Pos                                                     (6UL)    /*!<TIM SR: TIF (Bit 6) */
5520 #define TIM_SR_TIF_Msk                                                     (0x40UL)   /*!< TIM SR: TIF (Bitfield-Mask: 0x01) */
5521 #define TIM_SR_TIF                                                         TIM_SR_TIF_Msk
5522 #define TIM_SR_COMIF_Pos                                                   (5UL)    /*!<TIM SR: COMIF (Bit 5) */
5523 #define TIM_SR_COMIF_Msk                                                   (0x20UL)   /*!< TIM SR: COMIF (Bitfield-Mask: 0x01) */
5524 #define TIM_SR_COMIF                                                       TIM_SR_COMIF_Msk
5525 #define TIM_SR_CC4IF_Pos                                                   (4UL)    /*!<TIM SR: CC4IF (Bit 4) */
5526 #define TIM_SR_CC4IF_Msk                                                   (0x10UL)   /*!< TIM SR: CC4IF (Bitfield-Mask: 0x01) */
5527 #define TIM_SR_CC4IF                                                       TIM_SR_CC4IF_Msk
5528 #define TIM_SR_CC3IF_Pos                                                   (3UL)    /*!<TIM SR: CC3IF (Bit 3) */
5529 #define TIM_SR_CC3IF_Msk                                                   (0x8UL)    /*!< TIM SR: CC3IF (Bitfield-Mask: 0x01) */
5530 #define TIM_SR_CC3IF                                                       TIM_SR_CC3IF_Msk
5531 #define TIM_SR_CC2IF_Pos                                                   (2UL)    /*!<TIM SR: CC2IF (Bit 2) */
5532 #define TIM_SR_CC2IF_Msk                                                   (0x4UL)    /*!< TIM SR: CC2IF (Bitfield-Mask: 0x01) */
5533 #define TIM_SR_CC2IF                                                       TIM_SR_CC2IF_Msk
5534 #define TIM_SR_CC1IF_Pos                                                   (1UL)    /*!<TIM SR: CC1IF (Bit 1) */
5535 #define TIM_SR_CC1IF_Msk                                                   (0x2UL)    /*!< TIM SR: CC1IF (Bitfield-Mask: 0x01) */
5536 #define TIM_SR_CC1IF                                                       TIM_SR_CC1IF_Msk
5537 #define TIM_SR_UIF_Pos                                                     (0UL)    /*!<TIM SR: UIF (Bit 0) */
5538 #define TIM_SR_UIF_Msk                                                     (0x1UL)    /*!< TIM SR: UIF (Bitfield-Mask: 0x01) */
5539 #define TIM_SR_UIF                                                         TIM_SR_UIF_Msk
5540 
5541 /* =====================================================    EGR    ===================================================== */
5542 #define TIM_EGR_B2G_Pos                                                    (8UL)    /*!<TIM EGR: B2G (Bit 8) */
5543 #define TIM_EGR_B2G_Msk                                                    (0x100UL)    /*!< TIM EGR: B2G (Bitfield-Mask: 0x01) */
5544 #define TIM_EGR_B2G                                                        TIM_EGR_B2G_Msk
5545 #define TIM_EGR_BG_Pos                                                     (7UL)    /*!<TIM EGR: BG (Bit 7) */
5546 #define TIM_EGR_BG_Msk                                                     (0x80UL)   /*!< TIM EGR: BG (Bitfield-Mask: 0x01) */
5547 #define TIM_EGR_BG                                                         TIM_EGR_BG_Msk
5548 #define TIM_EGR_TG_Pos                                                     (6UL)    /*!<TIM EGR: TG (Bit 6) */
5549 #define TIM_EGR_TG_Msk                                                     (0x40UL)   /*!< TIM EGR: TG (Bitfield-Mask: 0x01) */
5550 #define TIM_EGR_TG                                                         TIM_EGR_TG_Msk
5551 #define TIM_EGR_COMG_Pos                                                   (5UL)    /*!<TIM EGR: COMG (Bit 5) */
5552 #define TIM_EGR_COMG_Msk                                                   (0x20UL)   /*!< TIM EGR: COMG (Bitfield-Mask: 0x01) */
5553 #define TIM_EGR_COMG                                                       TIM_EGR_COMG_Msk
5554 #define TIM_EGR_CC4G_Pos                                                   (4UL)    /*!<TIM EGR: CC4G (Bit 4) */
5555 #define TIM_EGR_CC4G_Msk                                                   (0x10UL)   /*!< TIM EGR: CC4G (Bitfield-Mask: 0x01) */
5556 #define TIM_EGR_CC4G                                                       TIM_EGR_CC4G_Msk
5557 #define TIM_EGR_CC3G_Pos                                                   (3UL)    /*!<TIM EGR: CC3G (Bit 3) */
5558 #define TIM_EGR_CC3G_Msk                                                   (0x8UL)    /*!< TIM EGR: CC3G (Bitfield-Mask: 0x01) */
5559 #define TIM_EGR_CC3G                                                       TIM_EGR_CC3G_Msk
5560 #define TIM_EGR_CC2G_Pos                                                   (2UL)    /*!<TIM EGR: CC2G (Bit 2) */
5561 #define TIM_EGR_CC2G_Msk                                                   (0x4UL)    /*!< TIM EGR: CC2G (Bitfield-Mask: 0x01) */
5562 #define TIM_EGR_CC2G                                                       TIM_EGR_CC2G_Msk
5563 #define TIM_EGR_CC1G_Pos                                                   (1UL)    /*!<TIM EGR: CC1G (Bit 1) */
5564 #define TIM_EGR_CC1G_Msk                                                   (0x2UL)    /*!< TIM EGR: CC1G (Bitfield-Mask: 0x01) */
5565 #define TIM_EGR_CC1G                                                       TIM_EGR_CC1G_Msk
5566 #define TIM_EGR_UG_Pos                                                     (0UL)    /*!<TIM EGR: UG (Bit 0) */
5567 #define TIM_EGR_UG_Msk                                                     (0x1UL)    /*!< TIM EGR: UG (Bitfield-Mask: 0x01) */
5568 #define TIM_EGR_UG                                                         TIM_EGR_UG_Msk
5569 
5570 /* =====================================================    CCMR1    ===================================================== */
5571 #define TIM_CCMR1_OC2CE_Pos                                                (15UL)   /*!<TIM CCMR1: OC2CE (Bit 15) */
5572 #define TIM_CCMR1_OC2CE_Msk                                                (0x8000UL)   /*!< TIM CCMR1: OC2CE (Bitfield-Mask: 0x01) */
5573 #define TIM_CCMR1_OC2CE                                                    TIM_CCMR1_OC2CE_Msk
5574 #define TIM_CCMR1_OC2M_Pos                                                 (12UL)   /*!<TIM CCMR1: OC2M (Bit 12) */
5575 #define TIM_CCMR1_OC2M_Msk                                                 (0x1007000UL)    /*!< TIM CCMR1: OC2M (Bitfield-Mask: 0x1007) */
5576 #define TIM_CCMR1_OC2M                                                     TIM_CCMR1_OC2M_Msk
5577 #define TIM_CCMR1_OC2M_0                                                   (0x1U << TIM_CCMR1_OC2M_Pos)
5578 #define TIM_CCMR1_OC2M_1                                                   (0x2U << TIM_CCMR1_OC2M_Pos)
5579 #define TIM_CCMR1_OC2M_2                                                   (0x4U << TIM_CCMR1_OC2M_Pos)
5580 #define TIM_CCMR1_OC2M_3                                                   (0x1000U << TIM_CCMR1_OC2M_Pos)
5581 #define TIM_CCMR1_OC2PE_Pos                                                (11UL)   /*!<TIM CCMR1: OC2PE (Bit 11) */
5582 #define TIM_CCMR1_OC2PE_Msk                                                (0x800UL)    /*!< TIM CCMR1: OC2PE (Bitfield-Mask: 0x01) */
5583 #define TIM_CCMR1_OC2PE                                                    TIM_CCMR1_OC2PE_Msk
5584 #define TIM_CCMR1_OC2FE_Pos                                                (10UL)   /*!<TIM CCMR1: OC2FE (Bit 10) */
5585 #define TIM_CCMR1_OC2FE_Msk                                                (0x400UL)    /*!< TIM CCMR1: OC2FE (Bitfield-Mask: 0x01) */
5586 #define TIM_CCMR1_OC2FE                                                    TIM_CCMR1_OC2FE_Msk
5587 #define TIM_CCMR1_CC2S_Pos                                                 (8UL)    /*!<TIM CCMR1: CC2S (Bit 8) */
5588 #define TIM_CCMR1_CC2S_Msk                                                 (0x300UL)    /*!< TIM CCMR1: CC2S (Bitfield-Mask: 0x03) */
5589 #define TIM_CCMR1_CC2S                                                     TIM_CCMR1_CC2S_Msk
5590 #define TIM_CCMR1_CC2S_0                                                   (0x1U << TIM_CCMR1_CC2S_Pos)
5591 #define TIM_CCMR1_CC2S_1                                                   (0x2U << TIM_CCMR1_CC2S_Pos)
5592 #define TIM_CCMR1_OC1CE_Pos                                                (7UL)    /*!<TIM CCMR1: OC1CE (Bit 7) */
5593 #define TIM_CCMR1_OC1CE_Msk                                                (0x80UL)   /*!< TIM CCMR1: OC1CE (Bitfield-Mask: 0x01) */
5594 #define TIM_CCMR1_OC1CE                                                    TIM_CCMR1_OC1CE_Msk
5595 #define TIM_CCMR1_OC1M_Pos                                                 (4UL)    /*!<TIM CCMR1: OC1M (Bit 4) */
5596 #define TIM_CCMR1_OC1M_Msk                                                 (0x10070UL)    /*!< TIM CCMR1: OC1M (Bitfield-Mask: 0x1007) */
5597 #define TIM_CCMR1_OC1M                                                     TIM_CCMR1_OC1M_Msk
5598 #define TIM_CCMR1_OC1M_0                                                   (0x1U << TIM_CCMR1_OC1M_Pos)
5599 #define TIM_CCMR1_OC1M_1                                                   (0x2U << TIM_CCMR1_OC1M_Pos)
5600 #define TIM_CCMR1_OC1M_2                                                   (0x4U << TIM_CCMR1_OC1M_Pos)
5601 #define TIM_CCMR1_OC1M_3                                                   (0x1000U << TIM_CCMR1_OC1M_Pos)
5602 #define TIM_CCMR1_OC1PE_Pos                                                (3UL)    /*!<TIM CCMR1: OC1PE (Bit 3) */
5603 #define TIM_CCMR1_OC1PE_Msk                                                (0x8UL)    /*!< TIM CCMR1: OC1PE (Bitfield-Mask: 0x01) */
5604 #define TIM_CCMR1_OC1PE                                                    TIM_CCMR1_OC1PE_Msk
5605 #define TIM_CCMR1_OC1FE_Pos                                                (2UL)    /*!<TIM CCMR1: OC1FE (Bit 2) */
5606 #define TIM_CCMR1_OC1FE_Msk                                                (0x4UL)    /*!< TIM CCMR1: OC1FE (Bitfield-Mask: 0x01) */
5607 #define TIM_CCMR1_OC1FE                                                    TIM_CCMR1_OC1FE_Msk
5608 #define TIM_CCMR1_CC1S_Pos                                                 (0UL)    /*!<TIM CCMR1: CC1S (Bit 0) */
5609 #define TIM_CCMR1_CC1S_Msk                                                 (0x3UL)    /*!< TIM CCMR1: CC1S (Bitfield-Mask: 0x03) */
5610 #define TIM_CCMR1_CC1S                                                     TIM_CCMR1_CC1S_Msk
5611 #define TIM_CCMR1_CC1S_0                                                   (0x1U << TIM_CCMR1_CC1S_Pos)
5612 #define TIM_CCMR1_CC1S_1                                                   (0x2U << TIM_CCMR1_CC1S_Pos)
5613 
5614 /* =====================================================    CCMR1    ===================================================== */
5615 #define TIM_CCMR1_IC2F_Pos                                                 (12UL)   /*!<TIM CCMR1: IC2F (Bit 12) */
5616 #define TIM_CCMR1_IC2F_Msk                                                 (0xf000UL)   /*!< TIM CCMR1: IC2F (Bitfield-Mask: 0x0f) */
5617 #define TIM_CCMR1_IC2F                                                     TIM_CCMR1_IC2F_Msk
5618 #define TIM_CCMR1_IC2F_0                                                   (0x1U << TIM_CCMR1_IC2F_Pos)
5619 #define TIM_CCMR1_IC2F_1                                                   (0x2U << TIM_CCMR1_IC2F_Pos)
5620 #define TIM_CCMR1_IC2F_2                                                   (0x4U << TIM_CCMR1_IC2F_Pos)
5621 #define TIM_CCMR1_IC2F_3                                                   (0x8U << TIM_CCMR1_IC2F_Pos)
5622 #define TIM_CCMR1_IC2PSC_Pos                                               (10UL)   /*!<TIM CCMR1: IC2PSC (Bit 10) */
5623 #define TIM_CCMR1_IC2PSC_Msk                                               (0xc00UL)    /*!< TIM CCMR1: IC2PSC (Bitfield-Mask: 0x03) */
5624 #define TIM_CCMR1_IC2PSC                                                   TIM_CCMR1_IC2PSC_Msk
5625 #define TIM_CCMR1_IC2PSC_0                                                 (0x1U << TIM_CCMR1_IC2PSC_Pos)
5626 #define TIM_CCMR1_IC2PSC_1                                                 (0x2U << TIM_CCMR1_IC2PSC_Pos)
5627 #define TIM_CCMR1_IC1F_Pos                                                 (4UL)    /*!<TIM CCMR1: IC1F (Bit 4) */
5628 #define TIM_CCMR1_IC1F_Msk                                                 (0xf0UL)   /*!< TIM CCMR1: IC1F (Bitfield-Mask: 0x0f) */
5629 #define TIM_CCMR1_IC1F                                                     TIM_CCMR1_IC1F_Msk
5630 #define TIM_CCMR1_IC1F_0                                                   (0x1U << TIM_CCMR1_IC1F_Pos)
5631 #define TIM_CCMR1_IC1F_1                                                   (0x2U << TIM_CCMR1_IC1F_Pos)
5632 #define TIM_CCMR1_IC1F_2                                                   (0x4U << TIM_CCMR1_IC1F_Pos)
5633 #define TIM_CCMR1_IC1F_3                                                   (0x8U << TIM_CCMR1_IC1F_Pos)
5634 #define TIM_CCMR1_IC1PSC_Pos                                               (2UL)    /*!<TIM CCMR1: IC1PSC (Bit 2) */
5635 #define TIM_CCMR1_IC1PSC_Msk                                               (0xcUL)    /*!< TIM CCMR1: IC1PSC (Bitfield-Mask: 0x03) */
5636 #define TIM_CCMR1_IC1PSC                                                   TIM_CCMR1_IC1PSC_Msk
5637 #define TIM_CCMR1_IC1PSC_0                                                 (0x1U << TIM_CCMR1_IC1PSC_Pos)
5638 #define TIM_CCMR1_IC1PSC_1                                                 (0x2U << TIM_CCMR1_IC1PSC_Pos)
5639 
5640 /* =====================================================    CCMR2    ===================================================== */
5641 #define TIM_CCMR2_OC4CE_Pos                                                (15UL)   /*!<TIM CCMR2: OC4CE (Bit 15) */
5642 #define TIM_CCMR2_OC4CE_Msk                                                (0x8000UL)   /*!< TIM CCMR2: OC4CE (Bitfield-Mask: 0x01) */
5643 #define TIM_CCMR2_OC4CE                                                    TIM_CCMR2_OC4CE_Msk
5644 #define TIM_CCMR2_OC4M_Pos                                                 (12UL)   /*!<TIM CCMR2: OC4M (Bit 12) */
5645 #define TIM_CCMR2_OC4M_Msk                                                 (0x1007000UL)    /*!< TIM CCMR2: OC4M (Bitfield-Mask: 0x1007) */
5646 #define TIM_CCMR2_OC4M                                                     TIM_CCMR2_OC4M_Msk
5647 #define TIM_CCMR2_OC4M_0                                                   (0x1U << TIM_CCMR2_OC4M_Pos)
5648 #define TIM_CCMR2_OC4M_1                                                   (0x2U << TIM_CCMR2_OC4M_Pos)
5649 #define TIM_CCMR2_OC4M_2                                                   (0x4U << TIM_CCMR2_OC4M_Pos)
5650 #define TIM_CCMR2_OC4M_3                                                   (0x1000U << TIM_CCMR2_OC4M_Pos)
5651 #define TIM_CCMR2_OC4PE_Pos                                                (11UL)   /*!<TIM CCMR2: OC4PE (Bit 11) */
5652 #define TIM_CCMR2_OC4PE_Msk                                                (0x800UL)    /*!< TIM CCMR2: OC4PE (Bitfield-Mask: 0x01) */
5653 #define TIM_CCMR2_OC4PE                                                    TIM_CCMR2_OC4PE_Msk
5654 #define TIM_CCMR2_OC4FE_Pos                                                (10UL)   /*!<TIM CCMR2: OC4FE (Bit 10) */
5655 #define TIM_CCMR2_OC4FE_Msk                                                (0x400UL)    /*!< TIM CCMR2: OC4FE (Bitfield-Mask: 0x01) */
5656 #define TIM_CCMR2_OC4FE                                                    TIM_CCMR2_OC4FE_Msk
5657 #define TIM_CCMR2_CC4S_Pos                                                 (8UL)    /*!<TIM CCMR2: CC4S (Bit 8) */
5658 #define TIM_CCMR2_CC4S_Msk                                                 (0x300UL)    /*!< TIM CCMR2: CC4S (Bitfield-Mask: 0x03) */
5659 #define TIM_CCMR2_CC4S                                                     TIM_CCMR2_CC4S_Msk
5660 #define TIM_CCMR2_CC4S_0                                                   (0x1U << TIM_CCMR2_CC4S_Pos)
5661 #define TIM_CCMR2_CC4S_1                                                   (0x2U << TIM_CCMR2_CC4S_Pos)
5662 #define TIM_CCMR2_OC3CE_Pos                                                (7UL)    /*!<TIM CCMR2: OC3CE (Bit 7) */
5663 #define TIM_CCMR2_OC3CE_Msk                                                (0x80UL)   /*!< TIM CCMR2: OC3CE (Bitfield-Mask: 0x01) */
5664 #define TIM_CCMR2_OC3CE                                                    TIM_CCMR2_OC3CE_Msk
5665 #define TIM_CCMR2_OC3M_Pos                                                 (4UL)    /*!<TIM CCMR2: OC3M (Bit 4) */
5666 #define TIM_CCMR2_OC3M_Msk                                                 (0x10070UL)    /*!< TIM CCMR2: OC3M (Bitfield-Mask: 0x1007) */
5667 #define TIM_CCMR2_OC3M                                                     TIM_CCMR2_OC3M_Msk
5668 #define TIM_CCMR2_OC3M_0                                                   (0x1U << TIM_CCMR2_OC3M_Pos)
5669 #define TIM_CCMR2_OC3M_1                                                   (0x2U << TIM_CCMR2_OC3M_Pos)
5670 #define TIM_CCMR2_OC3M_2                                                   (0x4U << TIM_CCMR2_OC3M_Pos)
5671 #define TIM_CCMR2_OC3M_3                                                   (0x1000U << TIM_CCMR2_OC3M_Pos)
5672 #define TIM_CCMR2_OC3PE_Pos                                                (3UL)    /*!<TIM CCMR2: OC3PE (Bit 3) */
5673 #define TIM_CCMR2_OC3PE_Msk                                                (0x8UL)    /*!< TIM CCMR2: OC3PE (Bitfield-Mask: 0x01) */
5674 #define TIM_CCMR2_OC3PE                                                    TIM_CCMR2_OC3PE_Msk
5675 #define TIM_CCMR2_OC3FE_Pos                                                (2UL)    /*!<TIM CCMR2: OC3FE (Bit 2) */
5676 #define TIM_CCMR2_OC3FE_Msk                                                (0x4UL)    /*!< TIM CCMR2: OC3FE (Bitfield-Mask: 0x01) */
5677 #define TIM_CCMR2_OC3FE                                                    TIM_CCMR2_OC3FE_Msk
5678 #define TIM_CCMR2_CC3S_Pos                                                 (0UL)    /*!<TIM CCMR2: CC3S (Bit 0) */
5679 #define TIM_CCMR2_CC3S_Msk                                                 (0x3UL)    /*!< TIM CCMR2: CC3S (Bitfield-Mask: 0x03) */
5680 #define TIM_CCMR2_CC3S                                                     TIM_CCMR2_CC3S_Msk
5681 #define TIM_CCMR2_CC3S_0                                                   (0x1U << TIM_CCMR2_CC3S_Pos)
5682 #define TIM_CCMR2_CC3S_1                                                   (0x2U << TIM_CCMR2_CC3S_Pos)
5683 
5684 /* =====================================================    CCMR2    ===================================================== */
5685 #define TIM_CCMR2_IC4F_Pos                                                 (12UL)   /*!<TIM CCMR2: IC4F (Bit 12) */
5686 #define TIM_CCMR2_IC4F_Msk                                                 (0xf000UL)   /*!< TIM CCMR2: IC4F (Bitfield-Mask: 0x0f) */
5687 #define TIM_CCMR2_IC4F                                                     TIM_CCMR2_IC4F_Msk
5688 #define TIM_CCMR2_IC4F_0                                                   (0x1U << TIM_CCMR2_IC4F_Pos)
5689 #define TIM_CCMR2_IC4F_1                                                   (0x2U << TIM_CCMR2_IC4F_Pos)
5690 #define TIM_CCMR2_IC4F_2                                                   (0x4U << TIM_CCMR2_IC4F_Pos)
5691 #define TIM_CCMR2_IC4F_3                                                   (0x8U << TIM_CCMR2_IC4F_Pos)
5692 #define TIM_CCMR2_IC4PSC_Pos                                               (10UL)   /*!<TIM CCMR2: IC4PSC (Bit 10) */
5693 #define TIM_CCMR2_IC4PSC_Msk                                               (0xc00UL)    /*!< TIM CCMR2: IC4PSC (Bitfield-Mask: 0x03) */
5694 #define TIM_CCMR2_IC4PSC                                                   TIM_CCMR2_IC4PSC_Msk
5695 #define TIM_CCMR2_IC4PSC_0                                                 (0x1U << TIM_CCMR2_IC4PSC_Pos)
5696 #define TIM_CCMR2_IC4PSC_1                                                 (0x2U << TIM_CCMR2_IC4PSC_Pos)
5697 #define TIM_CCMR2_IC3F_Pos                                                 (4UL)    /*!<TIM CCMR2: IC3F (Bit 4) */
5698 #define TIM_CCMR2_IC3F_Msk                                                 (0xf0UL)   /*!< TIM CCMR2: IC3F (Bitfield-Mask: 0x0f) */
5699 #define TIM_CCMR2_IC3F                                                     TIM_CCMR2_IC3F_Msk
5700 #define TIM_CCMR2_IC3F_0                                                   (0x1U << TIM_CCMR2_IC3F_Pos)
5701 #define TIM_CCMR2_IC3F_1                                                   (0x2U << TIM_CCMR2_IC3F_Pos)
5702 #define TIM_CCMR2_IC3F_2                                                   (0x4U << TIM_CCMR2_IC3F_Pos)
5703 #define TIM_CCMR2_IC3F_3                                                   (0x8U << TIM_CCMR2_IC3F_Pos)
5704 #define TIM_CCMR2_IC3PSC_Pos                                               (2UL)    /*!<TIM CCMR2: IC3PSC (Bit 2) */
5705 #define TIM_CCMR2_IC3PSC_Msk                                               (0xcUL)    /*!< TIM CCMR2: IC3PSC (Bitfield-Mask: 0x03) */
5706 #define TIM_CCMR2_IC3PSC                                                   TIM_CCMR2_IC3PSC_Msk
5707 #define TIM_CCMR2_IC3PSC_0                                                 (0x1U << TIM_CCMR2_IC3PSC_Pos)
5708 #define TIM_CCMR2_IC3PSC_1                                                 (0x2U << TIM_CCMR2_IC3PSC_Pos)
5709 
5710 /* =====================================================    CCER    ===================================================== */
5711 #define TIM_CCER_CC6P_Pos                                                  (21UL)   /*!<TIM CCER: CC6P (Bit 21) */
5712 #define TIM_CCER_CC6P_Msk                                                  (0x200000UL)   /*!< TIM CCER: CC6P (Bitfield-Mask: 0x01) */
5713 #define TIM_CCER_CC6P                                                      TIM_CCER_CC6P_Msk
5714 #define TIM_CCER_CC6E_Pos                                                  (20UL)   /*!<TIM CCER: CC6E (Bit 20) */
5715 #define TIM_CCER_CC6E_Msk                                                  (0x100000UL)   /*!< TIM CCER: CC6E (Bitfield-Mask: 0x01) */
5716 #define TIM_CCER_CC6E                                                      TIM_CCER_CC6E_Msk
5717 #define TIM_CCER_CC5P_Pos                                                  (17UL)   /*!<TIM CCER: CC5P (Bit 17) */
5718 #define TIM_CCER_CC5P_Msk                                                  (0x20000UL)    /*!< TIM CCER: CC5P (Bitfield-Mask: 0x01) */
5719 #define TIM_CCER_CC5P                                                      TIM_CCER_CC5P_Msk
5720 #define TIM_CCER_CC5E_Pos                                                  (16UL)   /*!<TIM CCER: CC5E (Bit 16) */
5721 #define TIM_CCER_CC5E_Msk                                                  (0x10000UL)    /*!< TIM CCER: CC5E (Bitfield-Mask: 0x01) */
5722 #define TIM_CCER_CC5E                                                      TIM_CCER_CC5E_Msk
5723 #define TIM_CCER_CC4NP_Pos                                                 (15UL)   /*!<TIM CCER: CC4NP (Bit 15) */
5724 #define TIM_CCER_CC4NP_Msk                                                 (0x8000UL)   /*!< TIM CCER: CC4NP (Bitfield-Mask: 0x01) */
5725 #define TIM_CCER_CC4NP                                                     TIM_CCER_CC4NP_Msk
5726 #define TIM_CCER_CC4NE_Pos                                                 (14UL)   /*!<TIM CCER: CC4NE (Bit 14) */
5727 #define TIM_CCER_CC4NE_Msk                                                 (0x4000UL)   /*!< TIM CCER: CC4NE (Bitfield-Mask: 0x01) */
5728 #define TIM_CCER_CC4NE                                                     TIM_CCER_CC4NE_Msk
5729 #define TIM_CCER_CC4P_Pos                                                  (13UL)   /*!<TIM CCER: CC4P (Bit 13) */
5730 #define TIM_CCER_CC4P_Msk                                                  (0x2000UL)   /*!< TIM CCER: CC4P (Bitfield-Mask: 0x01) */
5731 #define TIM_CCER_CC4P                                                      TIM_CCER_CC4P_Msk
5732 #define TIM_CCER_CC4E_Pos                                                  (12UL)   /*!<TIM CCER: CC4E (Bit 12) */
5733 #define TIM_CCER_CC4E_Msk                                                  (0x1000UL)   /*!< TIM CCER: CC4E (Bitfield-Mask: 0x01) */
5734 #define TIM_CCER_CC4E                                                      TIM_CCER_CC4E_Msk
5735 #define TIM_CCER_CC3NP_Pos                                                 (11UL)   /*!<TIM CCER: CC3NP (Bit 11) */
5736 #define TIM_CCER_CC3NP_Msk                                                 (0x800UL)    /*!< TIM CCER: CC3NP (Bitfield-Mask: 0x01) */
5737 #define TIM_CCER_CC3NP                                                     TIM_CCER_CC3NP_Msk
5738 #define TIM_CCER_CC3NE_Pos                                                 (10UL)   /*!<TIM CCER: CC3NE (Bit 10) */
5739 #define TIM_CCER_CC3NE_Msk                                                 (0x400UL)    /*!< TIM CCER: CC3NE (Bitfield-Mask: 0x01) */
5740 #define TIM_CCER_CC3NE                                                     TIM_CCER_CC3NE_Msk
5741 #define TIM_CCER_CC3P_Pos                                                  (9UL)    /*!<TIM CCER: CC3P (Bit 9) */
5742 #define TIM_CCER_CC3P_Msk                                                  (0x200UL)    /*!< TIM CCER: CC3P (Bitfield-Mask: 0x01) */
5743 #define TIM_CCER_CC3P                                                      TIM_CCER_CC3P_Msk
5744 #define TIM_CCER_CC3E_Pos                                                  (8UL)    /*!<TIM CCER: CC3E (Bit 8) */
5745 #define TIM_CCER_CC3E_Msk                                                  (0x100UL)    /*!< TIM CCER: CC3E (Bitfield-Mask: 0x01) */
5746 #define TIM_CCER_CC3E                                                      TIM_CCER_CC3E_Msk
5747 #define TIM_CCER_CC2NP_Pos                                                 (7UL)    /*!<TIM CCER: CC2NP (Bit 7) */
5748 #define TIM_CCER_CC2NP_Msk                                                 (0x80UL)   /*!< TIM CCER: CC2NP (Bitfield-Mask: 0x01) */
5749 #define TIM_CCER_CC2NP                                                     TIM_CCER_CC2NP_Msk
5750 #define TIM_CCER_CC2NE_Pos                                                 (6UL)    /*!<TIM CCER: CC2NE (Bit 6) */
5751 #define TIM_CCER_CC2NE_Msk                                                 (0x40UL)   /*!< TIM CCER: CC2NE (Bitfield-Mask: 0x01) */
5752 #define TIM_CCER_CC2NE                                                     TIM_CCER_CC2NE_Msk
5753 #define TIM_CCER_CC2P_Pos                                                  (5UL)    /*!<TIM CCER: CC2P (Bit 5) */
5754 #define TIM_CCER_CC2P_Msk                                                  (0x20UL)   /*!< TIM CCER: CC2P (Bitfield-Mask: 0x01) */
5755 #define TIM_CCER_CC2P                                                      TIM_CCER_CC2P_Msk
5756 #define TIM_CCER_CC2E_Pos                                                  (4UL)    /*!<TIM CCER: CC2E (Bit 4) */
5757 #define TIM_CCER_CC2E_Msk                                                  (0x10UL)   /*!< TIM CCER: CC2E (Bitfield-Mask: 0x01) */
5758 #define TIM_CCER_CC2E                                                      TIM_CCER_CC2E_Msk
5759 #define TIM_CCER_CC1NP_Pos                                                 (3UL)    /*!<TIM CCER: CC1NP (Bit 3) */
5760 #define TIM_CCER_CC1NP_Msk                                                 (0x8UL)    /*!< TIM CCER: CC1NP (Bitfield-Mask: 0x01) */
5761 #define TIM_CCER_CC1NP                                                     TIM_CCER_CC1NP_Msk
5762 #define TIM_CCER_CC1NE_Pos                                                 (2UL)    /*!<TIM CCER: CC1NE (Bit 2) */
5763 #define TIM_CCER_CC1NE_Msk                                                 (0x4UL)    /*!< TIM CCER: CC1NE (Bitfield-Mask: 0x01) */
5764 #define TIM_CCER_CC1NE                                                     TIM_CCER_CC1NE_Msk
5765 #define TIM_CCER_CC1P_Pos                                                  (1UL)    /*!<TIM CCER: CC1P (Bit 1) */
5766 #define TIM_CCER_CC1P_Msk                                                  (0x2UL)    /*!< TIM CCER: CC1P (Bitfield-Mask: 0x01) */
5767 #define TIM_CCER_CC1P                                                      TIM_CCER_CC1P_Msk
5768 #define TIM_CCER_CC1E_Pos                                                  (0UL)    /*!<TIM CCER: CC1E (Bit 0) */
5769 #define TIM_CCER_CC1E_Msk                                                  (0x1UL)    /*!< TIM CCER: CC1E (Bitfield-Mask: 0x01) */
5770 #define TIM_CCER_CC1E                                                      TIM_CCER_CC1E_Msk
5771 
5772 /* =====================================================    CNT    ===================================================== */
5773 #define TIM_CNT_UIFCPY_Pos                                                 (31UL)   /*!<TIM CNT: UIFCPY (Bit 31) */
5774 #define TIM_CNT_UIFCPY_Msk                                                 (0x80000000UL)   /*!< TIM CNT: UIFCPY (Bitfield-Mask: 0x01) */
5775 #define TIM_CNT_UIFCPY                                                     TIM_CNT_UIFCPY_Msk
5776 #define TIM_CNT_CNT_Pos                                                    (0UL)    /*!<TIM CNT: CNT (Bit 0) */
5777 #define TIM_CNT_CNT_Msk                                                    (0xffffUL)   /*!< TIM CNT: CNT (Bitfield-Mask: 0xffff) */
5778 #define TIM_CNT_CNT                                                        TIM_CNT_CNT_Msk
5779 #define TIM_CNT_CNT_0                                                      (0x1U << TIM_CNT_CNT_Pos)
5780 #define TIM_CNT_CNT_1                                                      (0x2U << TIM_CNT_CNT_Pos)
5781 #define TIM_CNT_CNT_2                                                      (0x4U << TIM_CNT_CNT_Pos)
5782 #define TIM_CNT_CNT_3                                                      (0x8U << TIM_CNT_CNT_Pos)
5783 #define TIM_CNT_CNT_4                                                      (0x10U << TIM_CNT_CNT_Pos)
5784 #define TIM_CNT_CNT_5                                                      (0x20U << TIM_CNT_CNT_Pos)
5785 #define TIM_CNT_CNT_6                                                      (0x40U << TIM_CNT_CNT_Pos)
5786 #define TIM_CNT_CNT_7                                                      (0x80U << TIM_CNT_CNT_Pos)
5787 #define TIM_CNT_CNT_8                                                      (0x100U << TIM_CNT_CNT_Pos)
5788 #define TIM_CNT_CNT_9                                                      (0x200U << TIM_CNT_CNT_Pos)
5789 #define TIM_CNT_CNT_10                                                     (0x400U << TIM_CNT_CNT_Pos)
5790 #define TIM_CNT_CNT_11                                                     (0x800U << TIM_CNT_CNT_Pos)
5791 #define TIM_CNT_CNT_12                                                     (0x1000U << TIM_CNT_CNT_Pos)
5792 #define TIM_CNT_CNT_13                                                     (0x2000U << TIM_CNT_CNT_Pos)
5793 #define TIM_CNT_CNT_14                                                     (0x4000U << TIM_CNT_CNT_Pos)
5794 #define TIM_CNT_CNT_15                                                     (0x8000U << TIM_CNT_CNT_Pos)
5795 
5796 /* =====================================================    PSC    ===================================================== */
5797 #define TIM_PSC_PSC_Pos                                                    (0UL)    /*!<TIM PSC: PSC (Bit 0) */
5798 #define TIM_PSC_PSC_Msk                                                    (0xffffUL)   /*!< TIM PSC: PSC (Bitfield-Mask: 0xffff) */
5799 #define TIM_PSC_PSC                                                        TIM_PSC_PSC_Msk
5800 #define TIM_PSC_PSC_0                                                      (0x1U << TIM_PSC_PSC_Pos)
5801 #define TIM_PSC_PSC_1                                                      (0x2U << TIM_PSC_PSC_Pos)
5802 #define TIM_PSC_PSC_2                                                      (0x4U << TIM_PSC_PSC_Pos)
5803 #define TIM_PSC_PSC_3                                                      (0x8U << TIM_PSC_PSC_Pos)
5804 #define TIM_PSC_PSC_4                                                      (0x10U << TIM_PSC_PSC_Pos)
5805 #define TIM_PSC_PSC_5                                                      (0x20U << TIM_PSC_PSC_Pos)
5806 #define TIM_PSC_PSC_6                                                      (0x40U << TIM_PSC_PSC_Pos)
5807 #define TIM_PSC_PSC_7                                                      (0x80U << TIM_PSC_PSC_Pos)
5808 #define TIM_PSC_PSC_8                                                      (0x100U << TIM_PSC_PSC_Pos)
5809 #define TIM_PSC_PSC_9                                                      (0x200U << TIM_PSC_PSC_Pos)
5810 #define TIM_PSC_PSC_10                                                     (0x400U << TIM_PSC_PSC_Pos)
5811 #define TIM_PSC_PSC_11                                                     (0x800U << TIM_PSC_PSC_Pos)
5812 #define TIM_PSC_PSC_12                                                     (0x1000U << TIM_PSC_PSC_Pos)
5813 #define TIM_PSC_PSC_13                                                     (0x2000U << TIM_PSC_PSC_Pos)
5814 #define TIM_PSC_PSC_14                                                     (0x4000U << TIM_PSC_PSC_Pos)
5815 #define TIM_PSC_PSC_15                                                     (0x8000U << TIM_PSC_PSC_Pos)
5816 
5817 /* =====================================================    ARR    ===================================================== */
5818 #define TIM_ARR_ARR_Pos                                                    (0UL)    /*!<TIM ARR: ARR (Bit 0) */
5819 #define TIM_ARR_ARR_Msk                                                    (0xffffUL)   /*!< TIM ARR: ARR (Bitfield-Mask: 0xffff) */
5820 #define TIM_ARR_ARR                                                        TIM_ARR_ARR_Msk
5821 #define TIM_ARR_ARR_0                                                      (0x1U << TIM_ARR_ARR_Pos)
5822 #define TIM_ARR_ARR_1                                                      (0x2U << TIM_ARR_ARR_Pos)
5823 #define TIM_ARR_ARR_2                                                      (0x4U << TIM_ARR_ARR_Pos)
5824 #define TIM_ARR_ARR_3                                                      (0x8U << TIM_ARR_ARR_Pos)
5825 #define TIM_ARR_ARR_4                                                      (0x10U << TIM_ARR_ARR_Pos)
5826 #define TIM_ARR_ARR_5                                                      (0x20U << TIM_ARR_ARR_Pos)
5827 #define TIM_ARR_ARR_6                                                      (0x40U << TIM_ARR_ARR_Pos)
5828 #define TIM_ARR_ARR_7                                                      (0x80U << TIM_ARR_ARR_Pos)
5829 #define TIM_ARR_ARR_8                                                      (0x100U << TIM_ARR_ARR_Pos)
5830 #define TIM_ARR_ARR_9                                                      (0x200U << TIM_ARR_ARR_Pos)
5831 #define TIM_ARR_ARR_10                                                     (0x400U << TIM_ARR_ARR_Pos)
5832 #define TIM_ARR_ARR_11                                                     (0x800U << TIM_ARR_ARR_Pos)
5833 #define TIM_ARR_ARR_12                                                     (0x1000U << TIM_ARR_ARR_Pos)
5834 #define TIM_ARR_ARR_13                                                     (0x2000U << TIM_ARR_ARR_Pos)
5835 #define TIM_ARR_ARR_14                                                     (0x4000U << TIM_ARR_ARR_Pos)
5836 #define TIM_ARR_ARR_15                                                     (0x8000U << TIM_ARR_ARR_Pos)
5837 
5838 /* =====================================================    RCR    ===================================================== */
5839 #define TIM_RCR_REP_Pos                                                    (0UL)    /*!<TIM RCR: REP (Bit 0) */
5840 #define TIM_RCR_REP_Msk                                                    (0xffffUL)   /*!< TIM RCR: REP (Bitfield-Mask: 0xffff) */
5841 #define TIM_RCR_REP                                                        TIM_RCR_REP_Msk
5842 #define TIM_RCR_REP_0                                                      (0x1U << TIM_RCR_REP_Pos)
5843 #define TIM_RCR_REP_1                                                      (0x2U << TIM_RCR_REP_Pos)
5844 #define TIM_RCR_REP_2                                                      (0x4U << TIM_RCR_REP_Pos)
5845 #define TIM_RCR_REP_3                                                      (0x8U << TIM_RCR_REP_Pos)
5846 #define TIM_RCR_REP_4                                                      (0x10U << TIM_RCR_REP_Pos)
5847 #define TIM_RCR_REP_5                                                      (0x20U << TIM_RCR_REP_Pos)
5848 #define TIM_RCR_REP_6                                                      (0x40U << TIM_RCR_REP_Pos)
5849 #define TIM_RCR_REP_7                                                      (0x80U << TIM_RCR_REP_Pos)
5850 #define TIM_RCR_REP_8                                                      (0x100U << TIM_RCR_REP_Pos)
5851 #define TIM_RCR_REP_9                                                      (0x200U << TIM_RCR_REP_Pos)
5852 #define TIM_RCR_REP_10                                                     (0x400U << TIM_RCR_REP_Pos)
5853 #define TIM_RCR_REP_11                                                     (0x800U << TIM_RCR_REP_Pos)
5854 #define TIM_RCR_REP_12                                                     (0x1000U << TIM_RCR_REP_Pos)
5855 #define TIM_RCR_REP_13                                                     (0x2000U << TIM_RCR_REP_Pos)
5856 #define TIM_RCR_REP_14                                                     (0x4000U << TIM_RCR_REP_Pos)
5857 #define TIM_RCR_REP_15                                                     (0x8000U << TIM_RCR_REP_Pos)
5858 
5859 /* =====================================================    CCR1    ===================================================== */
5860 #define TIM_CCR1_CCR1_Pos                                                  (0UL)    /*!<TIM CCR1: CCR1 (Bit 0) */
5861 #define TIM_CCR1_CCR1_Msk                                                  (0xffffUL)   /*!< TIM CCR1: CCR1 (Bitfield-Mask: 0xffff) */
5862 #define TIM_CCR1_CCR1                                                      TIM_CCR1_CCR1_Msk
5863 #define TIM_CCR1_CCR1_0                                                    (0x1U << TIM_CCR1_CCR1_Pos)
5864 #define TIM_CCR1_CCR1_1                                                    (0x2U << TIM_CCR1_CCR1_Pos)
5865 #define TIM_CCR1_CCR1_2                                                    (0x4U << TIM_CCR1_CCR1_Pos)
5866 #define TIM_CCR1_CCR1_3                                                    (0x8U << TIM_CCR1_CCR1_Pos)
5867 #define TIM_CCR1_CCR1_4                                                    (0x10U << TIM_CCR1_CCR1_Pos)
5868 #define TIM_CCR1_CCR1_5                                                    (0x20U << TIM_CCR1_CCR1_Pos)
5869 #define TIM_CCR1_CCR1_6                                                    (0x40U << TIM_CCR1_CCR1_Pos)
5870 #define TIM_CCR1_CCR1_7                                                    (0x80U << TIM_CCR1_CCR1_Pos)
5871 #define TIM_CCR1_CCR1_8                                                    (0x100U << TIM_CCR1_CCR1_Pos)
5872 #define TIM_CCR1_CCR1_9                                                    (0x200U << TIM_CCR1_CCR1_Pos)
5873 #define TIM_CCR1_CCR1_10                                                   (0x400U << TIM_CCR1_CCR1_Pos)
5874 #define TIM_CCR1_CCR1_11                                                   (0x800U << TIM_CCR1_CCR1_Pos)
5875 #define TIM_CCR1_CCR1_12                                                   (0x1000U << TIM_CCR1_CCR1_Pos)
5876 #define TIM_CCR1_CCR1_13                                                   (0x2000U << TIM_CCR1_CCR1_Pos)
5877 #define TIM_CCR1_CCR1_14                                                   (0x4000U << TIM_CCR1_CCR1_Pos)
5878 #define TIM_CCR1_CCR1_15                                                   (0x8000U << TIM_CCR1_CCR1_Pos)
5879 
5880 /* =====================================================    CCR2    ===================================================== */
5881 #define TIM_CCR2_CCR2_Pos                                                  (0UL)    /*!<TIM CCR2: CCR2 (Bit 0) */
5882 #define TIM_CCR2_CCR2_Msk                                                  (0xffffUL)   /*!< TIM CCR2: CCR2 (Bitfield-Mask: 0xffff) */
5883 #define TIM_CCR2_CCR2                                                      TIM_CCR2_CCR2_Msk
5884 #define TIM_CCR2_CCR2_0                                                    (0x1U << TIM_CCR2_CCR2_Pos)
5885 #define TIM_CCR2_CCR2_1                                                    (0x2U << TIM_CCR2_CCR2_Pos)
5886 #define TIM_CCR2_CCR2_2                                                    (0x4U << TIM_CCR2_CCR2_Pos)
5887 #define TIM_CCR2_CCR2_3                                                    (0x8U << TIM_CCR2_CCR2_Pos)
5888 #define TIM_CCR2_CCR2_4                                                    (0x10U << TIM_CCR2_CCR2_Pos)
5889 #define TIM_CCR2_CCR2_5                                                    (0x20U << TIM_CCR2_CCR2_Pos)
5890 #define TIM_CCR2_CCR2_6                                                    (0x40U << TIM_CCR2_CCR2_Pos)
5891 #define TIM_CCR2_CCR2_7                                                    (0x80U << TIM_CCR2_CCR2_Pos)
5892 #define TIM_CCR2_CCR2_8                                                    (0x100U << TIM_CCR2_CCR2_Pos)
5893 #define TIM_CCR2_CCR2_9                                                    (0x200U << TIM_CCR2_CCR2_Pos)
5894 #define TIM_CCR2_CCR2_10                                                   (0x400U << TIM_CCR2_CCR2_Pos)
5895 #define TIM_CCR2_CCR2_11                                                   (0x800U << TIM_CCR2_CCR2_Pos)
5896 #define TIM_CCR2_CCR2_12                                                   (0x1000U << TIM_CCR2_CCR2_Pos)
5897 #define TIM_CCR2_CCR2_13                                                   (0x2000U << TIM_CCR2_CCR2_Pos)
5898 #define TIM_CCR2_CCR2_14                                                   (0x4000U << TIM_CCR2_CCR2_Pos)
5899 #define TIM_CCR2_CCR2_15                                                   (0x8000U << TIM_CCR2_CCR2_Pos)
5900 
5901 /* =====================================================    CCR3    ===================================================== */
5902 #define TIM_CCR3_CCR3_Pos                                                  (0UL)    /*!<TIM CCR3: CCR3 (Bit 0) */
5903 #define TIM_CCR3_CCR3_Msk                                                  (0xffffUL)   /*!< TIM CCR3: CCR3 (Bitfield-Mask: 0xffff) */
5904 #define TIM_CCR3_CCR3                                                      TIM_CCR3_CCR3_Msk
5905 #define TIM_CCR3_CCR3_0                                                    (0x1U << TIM_CCR3_CCR3_Pos)
5906 #define TIM_CCR3_CCR3_1                                                    (0x2U << TIM_CCR3_CCR3_Pos)
5907 #define TIM_CCR3_CCR3_2                                                    (0x4U << TIM_CCR3_CCR3_Pos)
5908 #define TIM_CCR3_CCR3_3                                                    (0x8U << TIM_CCR3_CCR3_Pos)
5909 #define TIM_CCR3_CCR3_4                                                    (0x10U << TIM_CCR3_CCR3_Pos)
5910 #define TIM_CCR3_CCR3_5                                                    (0x20U << TIM_CCR3_CCR3_Pos)
5911 #define TIM_CCR3_CCR3_6                                                    (0x40U << TIM_CCR3_CCR3_Pos)
5912 #define TIM_CCR3_CCR3_7                                                    (0x80U << TIM_CCR3_CCR3_Pos)
5913 #define TIM_CCR3_CCR3_8                                                    (0x100U << TIM_CCR3_CCR3_Pos)
5914 #define TIM_CCR3_CCR3_9                                                    (0x200U << TIM_CCR3_CCR3_Pos)
5915 #define TIM_CCR3_CCR3_10                                                   (0x400U << TIM_CCR3_CCR3_Pos)
5916 #define TIM_CCR3_CCR3_11                                                   (0x800U << TIM_CCR3_CCR3_Pos)
5917 #define TIM_CCR3_CCR3_12                                                   (0x1000U << TIM_CCR3_CCR3_Pos)
5918 #define TIM_CCR3_CCR3_13                                                   (0x2000U << TIM_CCR3_CCR3_Pos)
5919 #define TIM_CCR3_CCR3_14                                                   (0x4000U << TIM_CCR3_CCR3_Pos)
5920 #define TIM_CCR3_CCR3_15                                                   (0x8000U << TIM_CCR3_CCR3_Pos)
5921 
5922 /* =====================================================    CCR4    ===================================================== */
5923 #define TIM_CCR4_CCR4_Pos                                                  (0UL)    /*!<TIM CCR4: CCR4 (Bit 0) */
5924 #define TIM_CCR4_CCR4_Msk                                                  (0xffffUL)   /*!< TIM CCR4: CCR4 (Bitfield-Mask: 0xffff) */
5925 #define TIM_CCR4_CCR4                                                      TIM_CCR4_CCR4_Msk
5926 #define TIM_CCR4_CCR4_0                                                    (0x1U << TIM_CCR4_CCR4_Pos)
5927 #define TIM_CCR4_CCR4_1                                                    (0x2U << TIM_CCR4_CCR4_Pos)
5928 #define TIM_CCR4_CCR4_2                                                    (0x4U << TIM_CCR4_CCR4_Pos)
5929 #define TIM_CCR4_CCR4_3                                                    (0x8U << TIM_CCR4_CCR4_Pos)
5930 #define TIM_CCR4_CCR4_4                                                    (0x10U << TIM_CCR4_CCR4_Pos)
5931 #define TIM_CCR4_CCR4_5                                                    (0x20U << TIM_CCR4_CCR4_Pos)
5932 #define TIM_CCR4_CCR4_6                                                    (0x40U << TIM_CCR4_CCR4_Pos)
5933 #define TIM_CCR4_CCR4_7                                                    (0x80U << TIM_CCR4_CCR4_Pos)
5934 #define TIM_CCR4_CCR4_8                                                    (0x100U << TIM_CCR4_CCR4_Pos)
5935 #define TIM_CCR4_CCR4_9                                                    (0x200U << TIM_CCR4_CCR4_Pos)
5936 #define TIM_CCR4_CCR4_10                                                   (0x400U << TIM_CCR4_CCR4_Pos)
5937 #define TIM_CCR4_CCR4_11                                                   (0x800U << TIM_CCR4_CCR4_Pos)
5938 #define TIM_CCR4_CCR4_12                                                   (0x1000U << TIM_CCR4_CCR4_Pos)
5939 #define TIM_CCR4_CCR4_13                                                   (0x2000U << TIM_CCR4_CCR4_Pos)
5940 #define TIM_CCR4_CCR4_14                                                   (0x4000U << TIM_CCR4_CCR4_Pos)
5941 #define TIM_CCR4_CCR4_15                                                   (0x8000U << TIM_CCR4_CCR4_Pos)
5942 
5943 /* =====================================================    BDTR    ===================================================== */
5944 #define TIM_BDTR_BK2P_Pos                                                  (25UL)   /*!<TIM BDTR: BK2P (Bit 25) */
5945 #define TIM_BDTR_BK2P_Msk                                                  (0x2000000UL)    /*!< TIM BDTR: BK2P (Bitfield-Mask: 0x01) */
5946 #define TIM_BDTR_BK2P                                                      TIM_BDTR_BK2P_Msk
5947 #define TIM_BDTR_BK2E_Pos                                                  (24UL)   /*!<TIM BDTR: BK2E (Bit 24) */
5948 #define TIM_BDTR_BK2E_Msk                                                  (0x1000000UL)    /*!< TIM BDTR: BK2E (Bitfield-Mask: 0x01) */
5949 #define TIM_BDTR_BK2E                                                      TIM_BDTR_BK2E_Msk
5950 #define TIM_BDTR_BK2F_Pos                                                  (20UL)   /*!<TIM BDTR: BK2F (Bit 20) */
5951 #define TIM_BDTR_BK2F_Msk                                                  (0xf00000UL)   /*!< TIM BDTR: BK2F (Bitfield-Mask: 0x0f) */
5952 #define TIM_BDTR_BK2F                                                      TIM_BDTR_BK2F_Msk
5953 #define TIM_BDTR_BK2F_0                                                    (0x1U << TIM_BDTR_BK2F_Pos)
5954 #define TIM_BDTR_BK2F_1                                                    (0x2U << TIM_BDTR_BK2F_Pos)
5955 #define TIM_BDTR_BK2F_2                                                    (0x4U << TIM_BDTR_BK2F_Pos)
5956 #define TIM_BDTR_BK2F_3                                                    (0x8U << TIM_BDTR_BK2F_Pos)
5957 #define TIM_BDTR_BKF_Pos                                                   (16UL)   /*!<TIM BDTR: BKF (Bit 16) */
5958 #define TIM_BDTR_BKF_Msk                                                   (0xf0000UL)    /*!< TIM BDTR: BKF (Bitfield-Mask: 0x0f) */
5959 #define TIM_BDTR_BKF                                                       TIM_BDTR_BKF_Msk
5960 #define TIM_BDTR_BKF_0                                                     (0x1U << TIM_BDTR_BKF_Pos)
5961 #define TIM_BDTR_BKF_1                                                     (0x2U << TIM_BDTR_BKF_Pos)
5962 #define TIM_BDTR_BKF_2                                                     (0x4U << TIM_BDTR_BKF_Pos)
5963 #define TIM_BDTR_BKF_3                                                     (0x8U << TIM_BDTR_BKF_Pos)
5964 #define TIM_BDTR_MOE_Pos                                                   (15UL)   /*!<TIM BDTR: MOE (Bit 15) */
5965 #define TIM_BDTR_MOE_Msk                                                   (0x8000UL)   /*!< TIM BDTR: MOE (Bitfield-Mask: 0x01) */
5966 #define TIM_BDTR_MOE                                                       TIM_BDTR_MOE_Msk
5967 #define TIM_BDTR_AOE_Pos                                                   (14UL)   /*!<TIM BDTR: AOE (Bit 14) */
5968 #define TIM_BDTR_AOE_Msk                                                   (0x4000UL)   /*!< TIM BDTR: AOE (Bitfield-Mask: 0x01) */
5969 #define TIM_BDTR_AOE                                                       TIM_BDTR_AOE_Msk
5970 #define TIM_BDTR_BKP_Pos                                                   (13UL)   /*!<TIM BDTR: BKP (Bit 13) */
5971 #define TIM_BDTR_BKP_Msk                                                   (0x2000UL)   /*!< TIM BDTR: BKP (Bitfield-Mask: 0x01) */
5972 #define TIM_BDTR_BKP                                                       TIM_BDTR_BKP_Msk
5973 #define TIM_BDTR_BKE_Pos                                                   (12UL)   /*!<TIM BDTR: BKE (Bit 12) */
5974 #define TIM_BDTR_BKE_Msk                                                   (0x1000UL)   /*!< TIM BDTR: BKE (Bitfield-Mask: 0x01) */
5975 #define TIM_BDTR_BKE                                                       TIM_BDTR_BKE_Msk
5976 #define TIM_BDTR_OSSR_Pos                                                  (11UL)   /*!<TIM BDTR: OSSR (Bit 11) */
5977 #define TIM_BDTR_OSSR_Msk                                                  (0x800UL)    /*!< TIM BDTR: OSSR (Bitfield-Mask: 0x01) */
5978 #define TIM_BDTR_OSSR                                                      TIM_BDTR_OSSR_Msk
5979 #define TIM_BDTR_OSSI_Pos                                                  (10UL)   /*!<TIM BDTR: OSSI (Bit 10) */
5980 #define TIM_BDTR_OSSI_Msk                                                  (0x400UL)    /*!< TIM BDTR: OSSI (Bitfield-Mask: 0x01) */
5981 #define TIM_BDTR_OSSI                                                      TIM_BDTR_OSSI_Msk
5982 #define TIM_BDTR_LOCK_Pos                                                  (8UL)    /*!<TIM BDTR: LOCK (Bit 8) */
5983 #define TIM_BDTR_LOCK_Msk                                                  (0x300UL)    /*!< TIM BDTR: LOCK (Bitfield-Mask: 0x03) */
5984 #define TIM_BDTR_LOCK                                                      TIM_BDTR_LOCK_Msk
5985 #define TIM_BDTR_LOCK_0                                                    (0x1U << TIM_BDTR_LOCK_Pos)
5986 #define TIM_BDTR_LOCK_1                                                    (0x2U << TIM_BDTR_LOCK_Pos)
5987 #define TIM_BDTR_DTG_Pos                                                   (0UL)    /*!<TIM BDTR: DTG (Bit 0) */
5988 #define TIM_BDTR_DTG_Msk                                                   (0xffUL)   /*!< TIM BDTR: DTG (Bitfield-Mask: 0xff) */
5989 #define TIM_BDTR_DTG                                                       TIM_BDTR_DTG_Msk
5990 #define TIM_BDTR_DTG_0                                                     (0x1U << TIM_BDTR_DTG_Pos)
5991 #define TIM_BDTR_DTG_1                                                     (0x2U << TIM_BDTR_DTG_Pos)
5992 #define TIM_BDTR_DTG_2                                                     (0x4U << TIM_BDTR_DTG_Pos)
5993 #define TIM_BDTR_DTG_3                                                     (0x8U << TIM_BDTR_DTG_Pos)
5994 #define TIM_BDTR_DTG_4                                                     (0x10U << TIM_BDTR_DTG_Pos)
5995 #define TIM_BDTR_DTG_5                                                     (0x20U << TIM_BDTR_DTG_Pos)
5996 #define TIM_BDTR_DTG_6                                                     (0x40U << TIM_BDTR_DTG_Pos)
5997 #define TIM_BDTR_DTG_7                                                     (0x80U << TIM_BDTR_DTG_Pos)
5998 
5999 /* =====================================================    CCMR3    ===================================================== */
6000 #define TIM_CCMR3_OC6CE_Pos                                                (15UL)   /*!<TIM CCMR3: OC6CE (Bit 15) */
6001 #define TIM_CCMR3_OC6CE_Msk                                                (0x8000UL)   /*!< TIM CCMR3: OC6CE (Bitfield-Mask: 0x01) */
6002 #define TIM_CCMR3_OC6CE                                                    TIM_CCMR3_OC6CE_Msk
6003 #define TIM_CCMR3_OC6M_Pos                                                 (12UL)   /*!<TIM CCMR3: OC6M (Bit 12) */
6004 #define TIM_CCMR3_OC6M_Msk                                                 (0x1007000UL)    /*!< TIM CCMR3: OC6M (Bitfield-Mask: 0x1007) */
6005 #define TIM_CCMR3_OC6M                                                     TIM_CCMR3_OC6M_Msk
6006 #define TIM_CCMR3_OC6M_0                                                   (0x1U << TIM_CCMR3_OC6M_Pos)
6007 #define TIM_CCMR3_OC6M_1                                                   (0x2U << TIM_CCMR3_OC6M_Pos)
6008 #define TIM_CCMR3_OC6M_2                                                   (0x4U << TIM_CCMR3_OC6M_Pos)
6009 #define TIM_CCMR3_OC6M_3                                                   (0x1000U << TIM_CCMR3_OC6M_Pos)
6010 #define TIM_CCMR3_OC6PE_Pos                                                (11UL)   /*!<TIM CCMR3: OC6PE (Bit 11) */
6011 #define TIM_CCMR3_OC6PE_Msk                                                (0x800UL)    /*!< TIM CCMR3: OC6PE (Bitfield-Mask: 0x01) */
6012 #define TIM_CCMR3_OC6PE                                                    TIM_CCMR3_OC6PE_Msk
6013 #define TIM_CCMR3_OC6FE_Pos                                                (10UL)   /*!<TIM CCMR3: OC6FE (Bit 10) */
6014 #define TIM_CCMR3_OC6FE_Msk                                                (0x400UL)    /*!< TIM CCMR3: OC6FE (Bitfield-Mask: 0x01) */
6015 #define TIM_CCMR3_OC6FE                                                    TIM_CCMR3_OC6FE_Msk
6016 #define TIM_CCMR3_OC5CE_Pos                                                (7UL)    /*!<TIM CCMR3: OC5CE (Bit 7) */
6017 #define TIM_CCMR3_OC5CE_Msk                                                (0x80UL)   /*!< TIM CCMR3: OC5CE (Bitfield-Mask: 0x01) */
6018 #define TIM_CCMR3_OC5CE                                                    TIM_CCMR3_OC5CE_Msk
6019 #define TIM_CCMR3_OC5M_Pos                                                 (4UL)    /*!<TIM CCMR3: OC5M (Bit 4) */
6020 #define TIM_CCMR3_OC5M_Msk                                                 (0x10070UL)    /*!< TIM CCMR3: OC5M (Bitfield-Mask: 0x1007) */
6021 #define TIM_CCMR3_OC5M                                                     TIM_CCMR3_OC5M_Msk
6022 #define TIM_CCMR3_OC5M_0                                                   (0x1U << TIM_CCMR3_OC5M_Pos)
6023 #define TIM_CCMR3_OC5M_1                                                   (0x2U << TIM_CCMR3_OC5M_Pos)
6024 #define TIM_CCMR3_OC5M_2                                                   (0x4U << TIM_CCMR3_OC5M_Pos)
6025 #define TIM_CCMR3_OC5M_3                                                   (0x1000U << TIM_CCMR3_OC5M_Pos)
6026 #define TIM_CCMR3_OC5PE_Pos                                                (3UL)    /*!<TIM CCMR3: OC5PE (Bit 3) */
6027 #define TIM_CCMR3_OC5PE_Msk                                                (0x8UL)    /*!< TIM CCMR3: OC5PE (Bitfield-Mask: 0x01) */
6028 #define TIM_CCMR3_OC5PE                                                    TIM_CCMR3_OC5PE_Msk
6029 #define TIM_CCMR3_OC5FE_Pos                                                (2UL)    /*!<TIM CCMR3: OC5FE (Bit 2) */
6030 #define TIM_CCMR3_OC5FE_Msk                                                (0x4UL)    /*!< TIM CCMR3: OC5FE (Bitfield-Mask: 0x01) */
6031 #define TIM_CCMR3_OC5FE                                                    TIM_CCMR3_OC5FE_Msk
6032 
6033 /* =====================================================    CCR5    ===================================================== */
6034 #define TIM_CCR5_GC5C3_Pos                                                 (31UL)   /*!<TIM CCR5: GC5C3 (Bit 31) */
6035 #define TIM_CCR5_GC5C3_Msk                                                 (0x80000000UL)   /*!< TIM CCR5: GC5C3 (Bitfield-Mask: 0x01) */
6036 #define TIM_CCR5_GC5C3                                                     TIM_CCR5_GC5C3_Msk
6037 #define TIM_CCR5_GC5C2_Pos                                                 (30UL)   /*!<TIM CCR5: GC5C2 (Bit 30) */
6038 #define TIM_CCR5_GC5C2_Msk                                                 (0x40000000UL)   /*!< TIM CCR5: GC5C2 (Bitfield-Mask: 0x01) */
6039 #define TIM_CCR5_GC5C2                                                     TIM_CCR5_GC5C2_Msk
6040 #define TIM_CCR5_GC5C1_Pos                                                 (29UL)   /*!<TIM CCR5: GC5C1 (Bit 29) */
6041 #define TIM_CCR5_GC5C1_Msk                                                 (0x20000000UL)   /*!< TIM CCR5: GC5C1 (Bitfield-Mask: 0x01) */
6042 #define TIM_CCR5_GC5C1                                                     TIM_CCR5_GC5C1_Msk
6043 #define TIM_CCR5_CCR5_Pos                                                  (0UL)    /*!<TIM CCR5: CCR5 (Bit 0) */
6044 #define TIM_CCR5_CCR5_Msk                                                  (0xffffUL)   /*!< TIM CCR5: CCR5 (Bitfield-Mask: 0xffff) */
6045 #define TIM_CCR5_CCR5                                                      TIM_CCR5_CCR5_Msk
6046 #define TIM_CCR5_CCR5_0                                                    (0x1U << TIM_CCR5_CCR5_Pos)
6047 #define TIM_CCR5_CCR5_1                                                    (0x2U << TIM_CCR5_CCR5_Pos)
6048 #define TIM_CCR5_CCR5_2                                                    (0x4U << TIM_CCR5_CCR5_Pos)
6049 #define TIM_CCR5_CCR5_3                                                    (0x8U << TIM_CCR5_CCR5_Pos)
6050 #define TIM_CCR5_CCR5_4                                                    (0x10U << TIM_CCR5_CCR5_Pos)
6051 #define TIM_CCR5_CCR5_5                                                    (0x20U << TIM_CCR5_CCR5_Pos)
6052 #define TIM_CCR5_CCR5_6                                                    (0x40U << TIM_CCR5_CCR5_Pos)
6053 #define TIM_CCR5_CCR5_7                                                    (0x80U << TIM_CCR5_CCR5_Pos)
6054 #define TIM_CCR5_CCR5_8                                                    (0x100U << TIM_CCR5_CCR5_Pos)
6055 #define TIM_CCR5_CCR5_9                                                    (0x200U << TIM_CCR5_CCR5_Pos)
6056 #define TIM_CCR5_CCR5_10                                                   (0x400U << TIM_CCR5_CCR5_Pos)
6057 #define TIM_CCR5_CCR5_11                                                   (0x800U << TIM_CCR5_CCR5_Pos)
6058 #define TIM_CCR5_CCR5_12                                                   (0x1000U << TIM_CCR5_CCR5_Pos)
6059 #define TIM_CCR5_CCR5_13                                                   (0x2000U << TIM_CCR5_CCR5_Pos)
6060 #define TIM_CCR5_CCR5_14                                                   (0x4000U << TIM_CCR5_CCR5_Pos)
6061 #define TIM_CCR5_CCR5_15                                                   (0x8000U << TIM_CCR5_CCR5_Pos)
6062 
6063 /* =====================================================    CCR6    ===================================================== */
6064 #define TIM_CCR6_CCR6_Pos                                                  (0UL)    /*!<TIM CCR6: CCR6 (Bit 0) */
6065 #define TIM_CCR6_CCR6_Msk                                                  (0xffffUL)   /*!< TIM CCR6: CCR6 (Bitfield-Mask: 0xffff) */
6066 #define TIM_CCR6_CCR6                                                      TIM_CCR6_CCR6_Msk
6067 #define TIM_CCR6_CCR6_0                                                    (0x1U << TIM_CCR6_CCR6_Pos)
6068 #define TIM_CCR6_CCR6_1                                                    (0x2U << TIM_CCR6_CCR6_Pos)
6069 #define TIM_CCR6_CCR6_2                                                    (0x4U << TIM_CCR6_CCR6_Pos)
6070 #define TIM_CCR6_CCR6_3                                                    (0x8U << TIM_CCR6_CCR6_Pos)
6071 #define TIM_CCR6_CCR6_4                                                    (0x10U << TIM_CCR6_CCR6_Pos)
6072 #define TIM_CCR6_CCR6_5                                                    (0x20U << TIM_CCR6_CCR6_Pos)
6073 #define TIM_CCR6_CCR6_6                                                    (0x40U << TIM_CCR6_CCR6_Pos)
6074 #define TIM_CCR6_CCR6_7                                                    (0x80U << TIM_CCR6_CCR6_Pos)
6075 #define TIM_CCR6_CCR6_8                                                    (0x100U << TIM_CCR6_CCR6_Pos)
6076 #define TIM_CCR6_CCR6_9                                                    (0x200U << TIM_CCR6_CCR6_Pos)
6077 #define TIM_CCR6_CCR6_10                                                   (0x400U << TIM_CCR6_CCR6_Pos)
6078 #define TIM_CCR6_CCR6_11                                                   (0x800U << TIM_CCR6_CCR6_Pos)
6079 #define TIM_CCR6_CCR6_12                                                   (0x1000U << TIM_CCR6_CCR6_Pos)
6080 #define TIM_CCR6_CCR6_13                                                   (0x2000U << TIM_CCR6_CCR6_Pos)
6081 #define TIM_CCR6_CCR6_14                                                   (0x4000U << TIM_CCR6_CCR6_Pos)
6082 #define TIM_CCR6_CCR6_15                                                   (0x8000U << TIM_CCR6_CCR6_Pos)
6083 
6084 /* =====================================================    AF1    ===================================================== */
6085 #define TIM_AF1_BKCMP2P_Pos                                                (11UL)   /*!<TIM AF1: BKCMP2P (Bit 11) */
6086 #define TIM_AF1_BKCMP2P_Msk                                                (0x800UL)    /*!< TIM AF1: BKCMP2P (Bitfield-Mask: 0x01) */
6087 #define TIM_AF1_BKCMP2P                                                    TIM_AF1_BKCMP2P_Msk
6088 #define TIM_AF1_BKCMP1P_Pos                                                (10UL)   /*!<TIM AF1: BKCMP1P (Bit 10) */
6089 #define TIM_AF1_BKCMP1P_Msk                                                (0x400UL)    /*!< TIM AF1: BKCMP1P (Bitfield-Mask: 0x01) */
6090 #define TIM_AF1_BKCMP1P                                                    TIM_AF1_BKCMP1P_Msk
6091 #define TIM_AF1_BKINP_Pos                                                  (9UL)    /*!<TIM AF1: BKINP (Bit 9) */
6092 #define TIM_AF1_BKINP_Msk                                                  (0x200UL)    /*!< TIM AF1: BKINP (Bitfield-Mask: 0x01) */
6093 #define TIM_AF1_BKINP                                                      TIM_AF1_BKINP_Msk
6094 #define TIM_AF1_BKCMP2E_Pos                                                (2UL)    /*!<TIM AF1: BKCMP2E (Bit 2) */
6095 #define TIM_AF1_BKCMP2E_Msk                                                (0x4UL)    /*!< TIM AF1: BKCMP2E (Bitfield-Mask: 0x01) */
6096 #define TIM_AF1_BKCMP2E                                                    TIM_AF1_BKCMP2E_Msk
6097 #define TIM_AF1_BKCMP1E_Pos                                                (1UL)    /*!<TIM AF1: BKCMP1E (Bit 1) */
6098 #define TIM_AF1_BKCMP1E_Msk                                                (0x2UL)    /*!< TIM AF1: BKCMP1E (Bitfield-Mask: 0x01) */
6099 #define TIM_AF1_BKCMP1E                                                    TIM_AF1_BKCMP1E_Msk
6100 #define TIM_AF1_BKINE_Pos                                                  (0UL)    /*!<TIM AF1: BKINE (Bit 0) */
6101 #define TIM_AF1_BKINE_Msk                                                  (0x1UL)    /*!< TIM AF1: BKINE (Bitfield-Mask: 0x01) */
6102 #define TIM_AF1_BKINE                                                      TIM_AF1_BKINE_Msk
6103 
6104 /* =====================================================    AF2    ===================================================== */
6105 #define TIM_AF2_BK2CMP2P_Pos                                               (11UL)   /*!<TIM AF2: BK2CMP2P (Bit 11) */
6106 #define TIM_AF2_BK2CMP2P_Msk                                               (0x800UL)    /*!< TIM AF2: BK2CMP2P (Bitfield-Mask: 0x01) */
6107 #define TIM_AF2_BK2CMP2P                                                   TIM_AF2_BK2CMP2P_Msk
6108 #define TIM_AF2_BK2CMP1P_Pos                                               (10UL)   /*!<TIM AF2: BK2CMP1P (Bit 10) */
6109 #define TIM_AF2_BK2CMP1P_Msk                                               (0x400UL)    /*!< TIM AF2: BK2CMP1P (Bitfield-Mask: 0x01) */
6110 #define TIM_AF2_BK2CMP1P                                                   TIM_AF2_BK2CMP1P_Msk
6111 #define TIM_AF2_BK2INP_Pos                                                 (9UL)    /*!<TIM AF2: BK2INP (Bit 9) */
6112 #define TIM_AF2_BK2INP_Msk                                                 (0x200UL)    /*!< TIM AF2: BK2INP (Bitfield-Mask: 0x01) */
6113 #define TIM_AF2_BK2INP                                                     TIM_AF2_BK2INP_Msk
6114 #define TIM_AF2_BK2CMP2E_Pos                                               (2UL)    /*!<TIM AF2: BK2CMP2E (Bit 2) */
6115 #define TIM_AF2_BK2CMP2E_Msk                                               (0x4UL)    /*!< TIM AF2: BK2CMP2E (Bitfield-Mask: 0x01) */
6116 #define TIM_AF2_BK2CMP2E                                                   TIM_AF2_BK2CMP2E_Msk
6117 #define TIM_AF2_BK2CMP1E_Pos                                               (1UL)    /*!<TIM AF2: BK2CMP1E (Bit 1) */
6118 #define TIM_AF2_BK2CMP1E_Msk                                               (0x2UL)    /*!< TIM AF2: BK2CMP1E (Bitfield-Mask: 0x01) */
6119 #define TIM_AF2_BK2CMP1E                                                   TIM_AF2_BK2CMP1E_Msk
6120 #define TIM_AF2_BK2INE_Pos                                                 (0UL)    /*!<TIM AF2: BK2INE (Bit 0) */
6121 #define TIM_AF2_BK2INE_Msk                                                 (0x1UL)    /*!< TIM AF2: BK2INE (Bitfield-Mask: 0x01) */
6122 #define TIM_AF2_BK2INE                                                     TIM_AF2_BK2INE_Msk
6123 
6124 
6125 /* =========================================================================================================================== */
6126 /*=====================                                      USART                                      ===================== */
6127 /* =========================================================================================================================== */
6128 
6129 /* =====================================================    CR1    ===================================================== */
6130 #define USART_CR1_RXFFIE_Pos                                               (31UL)   /*!<USART CR1: RXFFIE (Bit 31) */
6131 #define USART_CR1_RXFFIE_Msk                                               (0x80000000UL)   /*!< USART CR1: RXFFIE (Bitfield-Mask: 0x01) */
6132 #define USART_CR1_RXFFIE                                                   USART_CR1_RXFFIE_Msk
6133 #define USART_CR1_TXFEIE_Pos                                               (30UL)   /*!<USART CR1: TXFEIE (Bit 30) */
6134 #define USART_CR1_TXFEIE_Msk                                               (0x40000000UL)   /*!< USART CR1: TXFEIE (Bitfield-Mask: 0x01) */
6135 #define USART_CR1_TXFEIE                                                   USART_CR1_TXFEIE_Msk
6136 #define USART_CR1_FIFOEN_Pos                                               (29UL)   /*!<USART CR1: FIFOEN (Bit 29) */
6137 #define USART_CR1_FIFOEN_Msk                                               (0x20000000UL)   /*!< USART CR1: FIFOEN (Bitfield-Mask: 0x01) */
6138 #define USART_CR1_FIFOEN                                                   USART_CR1_FIFOEN_Msk
6139 #define USART_CR1_M1_Pos                                                   (28U)
6140 #define USART_CR1_M1_Msk                                                   (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
6141 #define USART_CR1_M1                                                       USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
6142 #define USART_CR1_EOBIE_Pos                                                (27UL)   /*!<USART CR1: EOBIE (Bit 27) */
6143 #define USART_CR1_EOBIE_Msk                                                (0x8000000UL)    /*!< USART CR1: EOBIE (Bitfield-Mask: 0x01) */
6144 #define USART_CR1_EOBIE                                                    USART_CR1_EOBIE_Msk
6145 #define USART_CR1_RTOIE_Pos                                                (26UL)   /*!<USART CR1: RTOIE (Bit 26) */
6146 #define USART_CR1_RTOIE_Msk                                                (0x4000000UL)    /*!< USART CR1: RTOIE (Bitfield-Mask: 0x01) */
6147 #define USART_CR1_RTOIE                                                    USART_CR1_RTOIE_Msk
6148 #define USART_CR1_DEAT_Pos                                                 (21UL)   /*!<USART CR1: DEAT (Bit 21) */
6149 #define USART_CR1_DEAT_Msk                                                 (0x3e00000UL)    /*!< USART CR1: DEAT (Bitfield-Mask: 0x1f) */
6150 #define USART_CR1_DEAT                                                     USART_CR1_DEAT_Msk
6151 #define USART_CR1_DEAT_0                                                   (0x1U << USART_CR1_DEAT_Pos)
6152 #define USART_CR1_DEAT_1                                                   (0x2U << USART_CR1_DEAT_Pos)
6153 #define USART_CR1_DEAT_2                                                   (0x4U << USART_CR1_DEAT_Pos)
6154 #define USART_CR1_DEAT_3                                                   (0x8U << USART_CR1_DEAT_Pos)
6155 #define USART_CR1_DEAT_4                                                   (0x10U << USART_CR1_DEAT_Pos)
6156 #define USART_CR1_DEDT_Pos                                                 (16UL)   /*!<USART CR1: DEDT (Bit 16) */
6157 #define USART_CR1_DEDT_Msk                                                 (0x1f0000UL)   /*!< USART CR1: DEDT (Bitfield-Mask: 0x1f) */
6158 #define USART_CR1_DEDT                                                     USART_CR1_DEDT_Msk
6159 #define USART_CR1_DEDT_0                                                   (0x1U << USART_CR1_DEDT_Pos)
6160 #define USART_CR1_DEDT_1                                                   (0x2U << USART_CR1_DEDT_Pos)
6161 #define USART_CR1_DEDT_2                                                   (0x4U << USART_CR1_DEDT_Pos)
6162 #define USART_CR1_DEDT_3                                                   (0x8U << USART_CR1_DEDT_Pos)
6163 #define USART_CR1_DEDT_4                                                   (0x10U << USART_CR1_DEDT_Pos)
6164 #define USART_CR1_OVER8_Pos                                                (15UL)   /*!<USART CR1: OVER8 (Bit 15) */
6165 #define USART_CR1_OVER8_Msk                                                (0x8000UL)   /*!< USART CR1: OVER8 (Bitfield-Mask: 0x01) */
6166 #define USART_CR1_OVER8                                                    USART_CR1_OVER8_Msk
6167 #define USART_CR1_CMIE_Pos                                                 (14UL)   /*!<USART CR1: CMIE (Bit 14) */
6168 #define USART_CR1_CMIE_Msk                                                 (0x4000UL)   /*!< USART CR1: CMIE (Bitfield-Mask: 0x01) */
6169 #define USART_CR1_CMIE                                                     USART_CR1_CMIE_Msk
6170 #define USART_CR1_MME_Pos                                                  (13UL)   /*!<USART CR1: MME (Bit 13) */
6171 #define USART_CR1_MME_Msk                                                  (0x2000UL)   /*!< USART CR1: MME (Bitfield-Mask: 0x01) */
6172 #define USART_CR1_MME                                                      USART_CR1_MME_Msk
6173 #define USART_CR1_M_Pos                                                    (12U)
6174 #define USART_CR1_M_Msk                                                    (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
6175 #define USART_CR1_M                                                        USART_CR1_M_Msk                         /*!< Word length */
6176 #define USART_CR1_M0_Pos                                                   (12U)
6177 #define USART_CR1_M0_Msk                                                   (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
6178 #define USART_CR1_M0                                                       USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
6179 #define USART_CR1_WAKE_Pos                                                 (11UL)   /*!<USART CR1: WAKE (Bit 11) */
6180 #define USART_CR1_WAKE_Msk                                                 (0x800UL)    /*!< USART CR1: WAKE (Bitfield-Mask: 0x01) */
6181 #define USART_CR1_WAKE                                                     USART_CR1_WAKE_Msk
6182 #define USART_CR1_PCE_Pos                                                  (10UL)   /*!<USART CR1: PCE (Bit 10) */
6183 #define USART_CR1_PCE_Msk                                                  (0x400UL)    /*!< USART CR1: PCE (Bitfield-Mask: 0x01) */
6184 #define USART_CR1_PCE                                                      USART_CR1_PCE_Msk
6185 #define USART_CR1_PS_Pos                                                   (9UL)    /*!<USART CR1: PS (Bit 9) */
6186 #define USART_CR1_PS_Msk                                                   (0x200UL)    /*!< USART CR1: PS (Bitfield-Mask: 0x01) */
6187 #define USART_CR1_PS                                                       USART_CR1_PS_Msk
6188 #define USART_CR1_PEIE_Pos                                                 (8UL)    /*!<USART CR1: PEIE (Bit 8) */
6189 #define USART_CR1_PEIE_Msk                                                 (0x100UL)    /*!< USART CR1: PEIE (Bitfield-Mask: 0x01) */
6190 #define USART_CR1_PEIE                                                     USART_CR1_PEIE_Msk
6191 #define USART_CR1_TXEIE_TXFNFIE_Pos                                        (7UL)    /*!<USART CR1: TXEIE_TXFNFIE (Bit 7) */
6192 #define USART_CR1_TXEIE_TXFNFIE_Msk                                        (0x80UL)   /*!< USART CR1: TXEIE_TXFNFIE (Bitfield-Mask: 0x01) */
6193 #define USART_CR1_TXEIE_TXFNFIE                                            USART_CR1_TXEIE_TXFNFIE_Msk
6194 #define USART_CR1_TCIE_Pos                                                 (6UL)    /*!<USART CR1: TCIE (Bit 6) */
6195 #define USART_CR1_TCIE_Msk                                                 (0x40UL)   /*!< USART CR1: TCIE (Bitfield-Mask: 0x01) */
6196 #define USART_CR1_TCIE                                                     USART_CR1_TCIE_Msk
6197 #define USART_CR1_RXNEIE_RXFNEIE_Pos                                       (5UL)    /*!<USART CR1: RXNEIE_RXFNEIE (Bit 5) */
6198 #define USART_CR1_RXNEIE_RXFNEIE_Msk                                       (0x20UL)   /*!< USART CR1: RXNEIE_RXFNEIE (Bitfield-Mask: 0x01) */
6199 #define USART_CR1_RXNEIE_RXFNEIE                                           USART_CR1_RXNEIE_RXFNEIE_Msk
6200 #define USART_CR1_IDLEIE_Pos                                               (4UL)    /*!<USART CR1: IDLEIE (Bit 4) */
6201 #define USART_CR1_IDLEIE_Msk                                               (0x10UL)   /*!< USART CR1: IDLEIE (Bitfield-Mask: 0x01) */
6202 #define USART_CR1_IDLEIE                                                   USART_CR1_IDLEIE_Msk
6203 #define USART_CR1_TE_Pos                                                   (3UL)    /*!<USART CR1: TE (Bit 3) */
6204 #define USART_CR1_TE_Msk                                                   (0x8UL)    /*!< USART CR1: TE (Bitfield-Mask: 0x01) */
6205 #define USART_CR1_TE                                                       USART_CR1_TE_Msk
6206 #define USART_CR1_RE_Pos                                                   (2UL)    /*!<USART CR1: RE (Bit 2) */
6207 #define USART_CR1_RE_Msk                                                   (0x4UL)    /*!< USART CR1: RE (Bitfield-Mask: 0x01) */
6208 #define USART_CR1_RE                                                       USART_CR1_RE_Msk
6209 #define USART_CR1_UE_Pos                                                   (0UL)    /*!<USART CR1: UE (Bit 0) */
6210 #define USART_CR1_UE_Msk                                                   (0x1UL)    /*!< USART CR1: UE (Bitfield-Mask: 0x01) */
6211 #define USART_CR1_UE                                                       USART_CR1_UE_Msk
6212 
6213 /* =====================================================    CR2    ===================================================== */
6214 #define USART_CR2_ADD_Pos                                                  (24UL)   /*!<USART CR2: ADD (Bit 24) */
6215 #define USART_CR2_ADD_Msk                                                  (0xff000000UL)   /*!< USART CR2: ADD (Bitfield-Mask: 0xff) */
6216 #define USART_CR2_ADD                                                      USART_CR2_ADD_Msk
6217 #define USART_CR2_ADD_0                                                    (0x1U << USART_CR2_ADD_Pos)
6218 #define USART_CR2_ADD_1                                                    (0x2U << USART_CR2_ADD_Pos)
6219 #define USART_CR2_ADD_2                                                    (0x4U << USART_CR2_ADD_Pos)
6220 #define USART_CR2_ADD_3                                                    (0x8U << USART_CR2_ADD_Pos)
6221 #define USART_CR2_ADD_4                                                    (0x10U << USART_CR2_ADD_Pos)
6222 #define USART_CR2_ADD_5                                                    (0x20U << USART_CR2_ADD_Pos)
6223 #define USART_CR2_ADD_6                                                    (0x40U << USART_CR2_ADD_Pos)
6224 #define USART_CR2_ADD_7                                                    (0x80U << USART_CR2_ADD_Pos)
6225 #define USART_CR2_RTOEN_Pos                                                (23UL)   /*!<USART CR2: RTOEN (Bit 23) */
6226 #define USART_CR2_RTOEN_Msk                                                (0x800000UL)   /*!< USART CR2: RTOEN (Bitfield-Mask: 0x01) */
6227 #define USART_CR2_RTOEN                                                    USART_CR2_RTOEN_Msk
6228 #define USART_CR2_ABRMODE_Pos                                              (21UL)   /*!<USART CR2: ABRMODE (Bit 21) */
6229 #define USART_CR2_ABRMODE_Msk                                              (0x600000UL)   /*!< USART CR2: ABRMODE (Bitfield-Mask: 0x03) */
6230 #define USART_CR2_ABRMODE                                                  USART_CR2_ABRMODE_Msk
6231 #define USART_CR2_ABRMODE_0                                                (0x1U << USART_CR2_ABRMODE_Pos)
6232 #define USART_CR2_ABRMODE_1                                                (0x2U << USART_CR2_ABRMODE_Pos)
6233 #define USART_CR2_ABREN_Pos                                                (20UL)   /*!<USART CR2: ABREN (Bit 20) */
6234 #define USART_CR2_ABREN_Msk                                                (0x100000UL)   /*!< USART CR2: ABREN (Bitfield-Mask: 0x01) */
6235 #define USART_CR2_ABREN                                                    USART_CR2_ABREN_Msk
6236 #define USART_CR2_MSBFIRST_Pos                                             (19UL)   /*!<USART CR2: MSBFIRST (Bit 19) */
6237 #define USART_CR2_MSBFIRST_Msk                                             (0x80000UL)    /*!< USART CR2: MSBFIRST (Bitfield-Mask: 0x01) */
6238 #define USART_CR2_MSBFIRST                                                 USART_CR2_MSBFIRST_Msk
6239 #define USART_CR2_DATAINV_Pos                                              (18UL)   /*!<USART CR2: DATAINV (Bit 18) */
6240 #define USART_CR2_DATAINV_Msk                                              (0x40000UL)    /*!< USART CR2: DATAINV (Bitfield-Mask: 0x01) */
6241 #define USART_CR2_DATAINV                                                  USART_CR2_DATAINV_Msk
6242 #define USART_CR2_TXINV_Pos                                                (17UL)   /*!<USART CR2: TXINV (Bit 17) */
6243 #define USART_CR2_TXINV_Msk                                                (0x20000UL)    /*!< USART CR2: TXINV (Bitfield-Mask: 0x01) */
6244 #define USART_CR2_TXINV                                                    USART_CR2_TXINV_Msk
6245 #define USART_CR2_RXINV_Pos                                                (16UL)   /*!<USART CR2: RXINV (Bit 16) */
6246 #define USART_CR2_RXINV_Msk                                                (0x10000UL)    /*!< USART CR2: RXINV (Bitfield-Mask: 0x01) */
6247 #define USART_CR2_RXINV                                                    USART_CR2_RXINV_Msk
6248 #define USART_CR2_SWAP_Pos                                                 (15UL)   /*!<USART CR2: SWAP (Bit 15) */
6249 #define USART_CR2_SWAP_Msk                                                 (0x8000UL)   /*!< USART CR2: SWAP (Bitfield-Mask: 0x01) */
6250 #define USART_CR2_SWAP                                                     USART_CR2_SWAP_Msk
6251 #define USART_CR2_LINEN_Pos                                                (14UL)   /*!<USART CR2: LINEN (Bit 14) */
6252 #define USART_CR2_LINEN_Msk                                                (0x4000UL)   /*!< USART CR2: LINEN (Bitfield-Mask: 0x01) */
6253 #define USART_CR2_LINEN                                                    USART_CR2_LINEN_Msk
6254 #define USART_CR2_STOP_Pos                                                 (12UL)   /*!<USART CR2: STOP (Bit 12) */
6255 #define USART_CR2_STOP_Msk                                                 (0x3000UL)   /*!< USART CR2: STOP (Bitfield-Mask: 0x03) */
6256 #define USART_CR2_STOP                                                     USART_CR2_STOP_Msk
6257 #define USART_CR2_STOP_0                                                   (0x1U << USART_CR2_STOP_Pos)
6258 #define USART_CR2_STOP_1                                                   (0x2U << USART_CR2_STOP_Pos)
6259 #define USART_CR2_CLKEN_Pos                                                (11UL)   /*!<USART CR2: CLKEN (Bit 11) */
6260 #define USART_CR2_CLKEN_Msk                                                (0x800UL)    /*!< USART CR2: CLKEN (Bitfield-Mask: 0x01) */
6261 #define USART_CR2_CLKEN                                                    USART_CR2_CLKEN_Msk
6262 #define USART_CR2_CPOL_Pos                                                 (10UL)   /*!<USART CR2: CPOL (Bit 10) */
6263 #define USART_CR2_CPOL_Msk                                                 (0x400UL)    /*!< USART CR2: CPOL (Bitfield-Mask: 0x01) */
6264 #define USART_CR2_CPOL                                                     USART_CR2_CPOL_Msk
6265 #define USART_CR2_CPHA_Pos                                                 (9UL)    /*!<USART CR2: CPHA (Bit 9) */
6266 #define USART_CR2_CPHA_Msk                                                 (0x200UL)    /*!< USART CR2: CPHA (Bitfield-Mask: 0x01) */
6267 #define USART_CR2_CPHA                                                     USART_CR2_CPHA_Msk
6268 #define USART_CR2_LBCL_Pos                                                 (8UL)    /*!<USART CR2: LBCL (Bit 8) */
6269 #define USART_CR2_LBCL_Msk                                                 (0x100UL)    /*!< USART CR2: LBCL (Bitfield-Mask: 0x01) */
6270 #define USART_CR2_LBCL                                                     USART_CR2_LBCL_Msk
6271 #define USART_CR2_LBDIE_Pos                                                (6UL)    /*!<USART CR2: LBDIE (Bit 6) */
6272 #define USART_CR2_LBDIE_Msk                                                (0x40UL)   /*!< USART CR2: LBDIE (Bitfield-Mask: 0x01) */
6273 #define USART_CR2_LBDIE                                                    USART_CR2_LBDIE_Msk
6274 #define USART_CR2_LBDL_Pos                                                 (5UL)    /*!<USART CR2: LBDL (Bit 5) */
6275 #define USART_CR2_LBDL_Msk                                                 (0x20UL)   /*!< USART CR2: LBDL (Bitfield-Mask: 0x01) */
6276 #define USART_CR2_LBDL                                                     USART_CR2_LBDL_Msk
6277 #define USART_CR2_ADDM7_Pos                                                (4UL)    /*!<USART CR2: ADDM7 (Bit 4) */
6278 #define USART_CR2_ADDM7_Msk                                                (0x10UL)   /*!< USART CR2: ADDM7 (Bitfield-Mask: 0x01) */
6279 #define USART_CR2_ADDM7                                                    USART_CR2_ADDM7_Msk
6280 #define USART_CR2_DIS_NSS_Pos                                              (3UL)    /*!<USART CR2: DIS_NSS (Bit 3) */
6281 #define USART_CR2_DIS_NSS_Msk                                              (0x8UL)    /*!< USART CR2: DIS_NSS (Bitfield-Mask: 0x01) */
6282 #define USART_CR2_DIS_NSS                                                  USART_CR2_DIS_NSS_Msk
6283 #define USART_CR2_SLVEN_Pos                                                (0UL)    /*!<USART CR2: SLVEN (Bit 0) */
6284 #define USART_CR2_SLVEN_Msk                                                (0x1UL)    /*!< USART CR2: SLVEN (Bitfield-Mask: 0x01) */
6285 #define USART_CR2_SLVEN                                                    USART_CR2_SLVEN_Msk
6286 
6287 /* =====================================================    CR3    ===================================================== */
6288 #define USART_CR3_TXFTCFG_Pos                                              (29UL)   /*!<USART CR3: TXFTCFG (Bit 29) */
6289 #define USART_CR3_TXFTCFG_Msk                                              (0xe0000000UL)   /*!< USART CR3: TXFTCFG (Bitfield-Mask: 0x07) */
6290 #define USART_CR3_TXFTCFG                                                  USART_CR3_TXFTCFG_Msk
6291 #define USART_CR3_TXFTCFG_0                                                (0x1U << USART_CR3_TXFTCFG_Pos)
6292 #define USART_CR3_TXFTCFG_1                                                (0x2U << USART_CR3_TXFTCFG_Pos)
6293 #define USART_CR3_TXFTCFG_2                                                (0x4U << USART_CR3_TXFTCFG_Pos)
6294 #define USART_CR3_RXFTIE_Pos                                               (28UL)   /*!<USART CR3: RXFTIE (Bit 28) */
6295 #define USART_CR3_RXFTIE_Msk                                               (0x10000000UL)   /*!< USART CR3: RXFTIE (Bitfield-Mask: 0x01) */
6296 #define USART_CR3_RXFTIE                                                   USART_CR3_RXFTIE_Msk
6297 #define USART_CR3_RXFTCFG_Pos                                              (25UL)   /*!<USART CR3: RXFTCFG (Bit 25) */
6298 #define USART_CR3_RXFTCFG_Msk                                              (0xe000000UL)    /*!< USART CR3: RXFTCFG (Bitfield-Mask: 0x07) */
6299 #define USART_CR3_RXFTCFG                                                  USART_CR3_RXFTCFG_Msk
6300 #define USART_CR3_RXFTCFG_0                                                (0x1U << USART_CR3_RXFTCFG_Pos)
6301 #define USART_CR3_RXFTCFG_1                                                (0x2U << USART_CR3_RXFTCFG_Pos)
6302 #define USART_CR3_RXFTCFG_2                                                (0x4U << USART_CR3_RXFTCFG_Pos)
6303 #define USART_CR3_TCBGTIE_Pos                                              (24UL)   /*!<USART CR3: TCBGTIE (Bit 24) */
6304 #define USART_CR3_TCBGTIE_Msk                                              (0x1000000UL)    /*!< USART CR3: TCBGTIE (Bitfield-Mask: 0x01) */
6305 #define USART_CR3_TCBGTIE                                                  USART_CR3_TCBGTIE_Msk
6306 #define USART_CR3_TXFTIE_Pos                                               (23UL)   /*!<USART CR3: TXFTIE (Bit 23) */
6307 #define USART_CR3_TXFTIE_Msk                                               (0x800000UL)   /*!< USART CR3: TXFTIE (Bitfield-Mask: 0x01) */
6308 #define USART_CR3_TXFTIE                                                   USART_CR3_TXFTIE_Msk
6309 #define USART_CR3_SCARCNT_Pos                                              (17UL)   /*!<USART CR3: SCARCNT (Bit 17) */
6310 #define USART_CR3_SCARCNT_Msk                                              (0xe0000UL)    /*!< USART CR3: SCARCNT (Bitfield-Mask: 0x07) */
6311 #define USART_CR3_SCARCNT                                                  USART_CR3_SCARCNT_Msk
6312 #define USART_CR3_SCARCNT_0                                                (0x1U << USART_CR3_SCARCNT_Pos)
6313 #define USART_CR3_SCARCNT_1                                                (0x2U << USART_CR3_SCARCNT_Pos)
6314 #define USART_CR3_SCARCNT_2                                                (0x4U << USART_CR3_SCARCNT_Pos)
6315 #define USART_CR3_DEP_Pos                                                  (15UL)   /*!<USART CR3: DEP (Bit 15) */
6316 #define USART_CR3_DEP_Msk                                                  (0x8000UL)   /*!< USART CR3: DEP (Bitfield-Mask: 0x01) */
6317 #define USART_CR3_DEP                                                      USART_CR3_DEP_Msk
6318 #define USART_CR3_DEM_Pos                                                  (14UL)   /*!<USART CR3: DEM (Bit 14) */
6319 #define USART_CR3_DEM_Msk                                                  (0x4000UL)   /*!< USART CR3: DEM (Bitfield-Mask: 0x01) */
6320 #define USART_CR3_DEM                                                      USART_CR3_DEM_Msk
6321 #define USART_CR3_DDRE_Pos                                                 (13UL)   /*!<USART CR3: DDRE (Bit 13) */
6322 #define USART_CR3_DDRE_Msk                                                 (0x2000UL)   /*!< USART CR3: DDRE (Bitfield-Mask: 0x01) */
6323 #define USART_CR3_DDRE                                                     USART_CR3_DDRE_Msk
6324 #define USART_CR3_OVRDIS_Pos                                               (12UL)   /*!<USART CR3: OVRDIS (Bit 12) */
6325 #define USART_CR3_OVRDIS_Msk                                               (0x1000UL)   /*!< USART CR3: OVRDIS (Bitfield-Mask: 0x01) */
6326 #define USART_CR3_OVRDIS                                                   USART_CR3_OVRDIS_Msk
6327 #define USART_CR3_ONEBIT_Pos                                               (11UL)   /*!<USART CR3: ONEBIT (Bit 11) */
6328 #define USART_CR3_ONEBIT_Msk                                               (0x800UL)    /*!< USART CR3: ONEBIT (Bitfield-Mask: 0x01) */
6329 #define USART_CR3_ONEBIT                                                   USART_CR3_ONEBIT_Msk
6330 #define USART_CR3_CTSIE_Pos                                                (10UL)   /*!<USART CR3: CTSIE (Bit 10) */
6331 #define USART_CR3_CTSIE_Msk                                                (0x400UL)    /*!< USART CR3: CTSIE (Bitfield-Mask: 0x01) */
6332 #define USART_CR3_CTSIE                                                    USART_CR3_CTSIE_Msk
6333 #define USART_CR3_CTSE_Pos                                                 (9UL)    /*!<USART CR3: CTSE (Bit 9) */
6334 #define USART_CR3_CTSE_Msk                                                 (0x200UL)    /*!< USART CR3: CTSE (Bitfield-Mask: 0x01) */
6335 #define USART_CR3_CTSE                                                     USART_CR3_CTSE_Msk
6336 #define USART_CR3_RTSE_Pos                                                 (8UL)    /*!<USART CR3: RTSE (Bit 8) */
6337 #define USART_CR3_RTSE_Msk                                                 (0x100UL)    /*!< USART CR3: RTSE (Bitfield-Mask: 0x01) */
6338 #define USART_CR3_RTSE                                                     USART_CR3_RTSE_Msk
6339 #define USART_CR3_DMAT_Pos                                                 (7UL)    /*!<USART CR3: DMAT (Bit 7) */
6340 #define USART_CR3_DMAT_Msk                                                 (0x80UL)   /*!< USART CR3: DMAT (Bitfield-Mask: 0x01) */
6341 #define USART_CR3_DMAT                                                     USART_CR3_DMAT_Msk
6342 #define USART_CR3_DMAR_Pos                                                 (6UL)    /*!<USART CR3: DMAR (Bit 6) */
6343 #define USART_CR3_DMAR_Msk                                                 (0x40UL)   /*!< USART CR3: DMAR (Bitfield-Mask: 0x01) */
6344 #define USART_CR3_DMAR                                                     USART_CR3_DMAR_Msk
6345 #define USART_CR3_SCEN_Pos                                                 (5UL)    /*!<USART CR3: SCEN (Bit 5) */
6346 #define USART_CR3_SCEN_Msk                                                 (0x20UL)   /*!< USART CR3: SCEN (Bitfield-Mask: 0x01) */
6347 #define USART_CR3_SCEN                                                     USART_CR3_SCEN_Msk
6348 #define USART_CR3_NACK_Pos                                                 (4UL)    /*!<USART CR3: NACK (Bit 4) */
6349 #define USART_CR3_NACK_Msk                                                 (0x10UL)   /*!< USART CR3: NACK (Bitfield-Mask: 0x01) */
6350 #define USART_CR3_NACK                                                     USART_CR3_NACK_Msk
6351 #define USART_CR3_HDSEL_Pos                                                (3UL)    /*!<USART CR3: HDSEL (Bit 3) */
6352 #define USART_CR3_HDSEL_Msk                                                (0x8UL)    /*!< USART CR3: HDSEL (Bitfield-Mask: 0x01) */
6353 #define USART_CR3_HDSEL                                                    USART_CR3_HDSEL_Msk
6354 #define USART_CR3_IRLP_Pos                                                 (2UL)    /*!<USART CR3: IRLP (Bit 2) */
6355 #define USART_CR3_IRLP_Msk                                                 (0x4UL)    /*!< USART CR3: IRLP (Bitfield-Mask: 0x01) */
6356 #define USART_CR3_IRLP                                                     USART_CR3_IRLP_Msk
6357 #define USART_CR3_IREN_Pos                                                 (1UL)    /*!<USART CR3: IREN (Bit 1) */
6358 #define USART_CR3_IREN_Msk                                                 (0x2UL)    /*!< USART CR3: IREN (Bitfield-Mask: 0x01) */
6359 #define USART_CR3_IREN                                                     USART_CR3_IREN_Msk
6360 #define USART_CR3_EIE_Pos                                                  (0UL)    /*!<USART CR3: EIE (Bit 0) */
6361 #define USART_CR3_EIE_Msk                                                  (0x1UL)    /*!< USART CR3: EIE (Bitfield-Mask: 0x01) */
6362 #define USART_CR3_EIE                                                      USART_CR3_EIE_Msk
6363 
6364 /* =====================================================    BRR    ===================================================== */
6365 #define USART_BRR_BRR_Pos                                                  (0UL)    /*!<USART BRR: BRR (Bit 0) */
6366 #define USART_BRR_BRR_Msk                                                  (0xfffffUL)    /*!< USART BRR: BRR (Bitfield-Mask: 0xfffff) */
6367 #define USART_BRR_BRR                                                      USART_BRR_BRR_Msk
6368 #define USART_BRR_BRR_0                                                    (0x1U << USART_BRR_BRR_Pos)
6369 #define USART_BRR_BRR_1                                                    (0x2U << USART_BRR_BRR_Pos)
6370 #define USART_BRR_BRR_2                                                    (0x4U << USART_BRR_BRR_Pos)
6371 #define USART_BRR_BRR_3                                                    (0x8U << USART_BRR_BRR_Pos)
6372 #define USART_BRR_BRR_4                                                    (0x10U << USART_BRR_BRR_Pos)
6373 #define USART_BRR_BRR_5                                                    (0x20U << USART_BRR_BRR_Pos)
6374 #define USART_BRR_BRR_6                                                    (0x40U << USART_BRR_BRR_Pos)
6375 #define USART_BRR_BRR_7                                                    (0x80U << USART_BRR_BRR_Pos)
6376 #define USART_BRR_BRR_8                                                    (0x100U << USART_BRR_BRR_Pos)
6377 #define USART_BRR_BRR_9                                                    (0x200U << USART_BRR_BRR_Pos)
6378 #define USART_BRR_BRR_10                                                   (0x400U << USART_BRR_BRR_Pos)
6379 #define USART_BRR_BRR_11                                                   (0x800U << USART_BRR_BRR_Pos)
6380 #define USART_BRR_BRR_12                                                   (0x1000U << USART_BRR_BRR_Pos)
6381 #define USART_BRR_BRR_13                                                   (0x2000U << USART_BRR_BRR_Pos)
6382 #define USART_BRR_BRR_14                                                   (0x4000U << USART_BRR_BRR_Pos)
6383 #define USART_BRR_BRR_15                                                   (0x8000U << USART_BRR_BRR_Pos)
6384 #define USART_BRR_BRR_16                                                   (0x10000U << USART_BRR_BRR_Pos)
6385 #define USART_BRR_BRR_17                                                   (0x20000U << USART_BRR_BRR_Pos)
6386 #define USART_BRR_BRR_18                                                   (0x40000U << USART_BRR_BRR_Pos)
6387 #define USART_BRR_BRR_19                                                   (0x80000U << USART_BRR_BRR_Pos)
6388 
6389 /* =====================================================    GTPR    ===================================================== */
6390 #define USART_GTPR_GT_Pos                                                  (8UL)    /*!<USART GTPR: GT (Bit 8) */
6391 #define USART_GTPR_GT_Msk                                                  (0xff00UL)   /*!< USART GTPR: GT (Bitfield-Mask: 0xff) */
6392 #define USART_GTPR_GT                                                      USART_GTPR_GT_Msk
6393 #define USART_GTPR_GT_0                                                    (0x1U << USART_GTPR_GT_Pos)
6394 #define USART_GTPR_GT_1                                                    (0x2U << USART_GTPR_GT_Pos)
6395 #define USART_GTPR_GT_2                                                    (0x4U << USART_GTPR_GT_Pos)
6396 #define USART_GTPR_GT_3                                                    (0x8U << USART_GTPR_GT_Pos)
6397 #define USART_GTPR_GT_4                                                    (0x10U << USART_GTPR_GT_Pos)
6398 #define USART_GTPR_GT_5                                                    (0x20U << USART_GTPR_GT_Pos)
6399 #define USART_GTPR_GT_6                                                    (0x40U << USART_GTPR_GT_Pos)
6400 #define USART_GTPR_GT_7                                                    (0x80U << USART_GTPR_GT_Pos)
6401 #define USART_GTPR_PSC_Pos                                                 (0UL)    /*!<USART GTPR: PSC (Bit 0) */
6402 #define USART_GTPR_PSC_Msk                                                 (0xffUL)   /*!< USART GTPR: PSC (Bitfield-Mask: 0xff) */
6403 #define USART_GTPR_PSC                                                     USART_GTPR_PSC_Msk
6404 #define USART_GTPR_PSC_0                                                   (0x1U << USART_GTPR_PSC_Pos)
6405 #define USART_GTPR_PSC_1                                                   (0x2U << USART_GTPR_PSC_Pos)
6406 #define USART_GTPR_PSC_2                                                   (0x4U << USART_GTPR_PSC_Pos)
6407 #define USART_GTPR_PSC_3                                                   (0x8U << USART_GTPR_PSC_Pos)
6408 #define USART_GTPR_PSC_4                                                   (0x10U << USART_GTPR_PSC_Pos)
6409 #define USART_GTPR_PSC_5                                                   (0x20U << USART_GTPR_PSC_Pos)
6410 #define USART_GTPR_PSC_6                                                   (0x40U << USART_GTPR_PSC_Pos)
6411 #define USART_GTPR_PSC_7                                                   (0x80U << USART_GTPR_PSC_Pos)
6412 
6413 /* =====================================================    RTOR    ===================================================== */
6414 #define USART_RTOR_BLEN_Pos                                                (24UL)   /*!<USART RTOR: BLEN (Bit 24) */
6415 #define USART_RTOR_BLEN_Msk                                                (0xff000000UL)   /*!< USART RTOR: BLEN (Bitfield-Mask: 0xff) */
6416 #define USART_RTOR_BLEN                                                    USART_RTOR_BLEN_Msk
6417 #define USART_RTOR_BLEN_0                                                  (0x1U << USART_RTOR_BLEN_Pos)
6418 #define USART_RTOR_BLEN_1                                                  (0x2U << USART_RTOR_BLEN_Pos)
6419 #define USART_RTOR_BLEN_2                                                  (0x4U << USART_RTOR_BLEN_Pos)
6420 #define USART_RTOR_BLEN_3                                                  (0x8U << USART_RTOR_BLEN_Pos)
6421 #define USART_RTOR_BLEN_4                                                  (0x10U << USART_RTOR_BLEN_Pos)
6422 #define USART_RTOR_BLEN_5                                                  (0x20U << USART_RTOR_BLEN_Pos)
6423 #define USART_RTOR_BLEN_6                                                  (0x40U << USART_RTOR_BLEN_Pos)
6424 #define USART_RTOR_BLEN_7                                                  (0x80U << USART_RTOR_BLEN_Pos)
6425 #define USART_RTOR_RTO_Pos                                                 (0UL)    /*!<USART RTOR: RTO (Bit 0) */
6426 #define USART_RTOR_RTO_Msk                                                 (0xffffffUL)   /*!< USART RTOR: RTO (Bitfield-Mask: 0xffffff) */
6427 #define USART_RTOR_RTO                                                     USART_RTOR_RTO_Msk
6428 #define USART_RTOR_RTO_0                                                   (0x1U << USART_RTOR_RTO_Pos)
6429 #define USART_RTOR_RTO_1                                                   (0x2U << USART_RTOR_RTO_Pos)
6430 #define USART_RTOR_RTO_2                                                   (0x4U << USART_RTOR_RTO_Pos)
6431 #define USART_RTOR_RTO_3                                                   (0x8U << USART_RTOR_RTO_Pos)
6432 #define USART_RTOR_RTO_4                                                   (0x10U << USART_RTOR_RTO_Pos)
6433 #define USART_RTOR_RTO_5                                                   (0x20U << USART_RTOR_RTO_Pos)
6434 #define USART_RTOR_RTO_6                                                   (0x40U << USART_RTOR_RTO_Pos)
6435 #define USART_RTOR_RTO_7                                                   (0x80U << USART_RTOR_RTO_Pos)
6436 #define USART_RTOR_RTO_8                                                   (0x100U << USART_RTOR_RTO_Pos)
6437 #define USART_RTOR_RTO_9                                                   (0x200U << USART_RTOR_RTO_Pos)
6438 #define USART_RTOR_RTO_10                                                  (0x400U << USART_RTOR_RTO_Pos)
6439 #define USART_RTOR_RTO_11                                                  (0x800U << USART_RTOR_RTO_Pos)
6440 #define USART_RTOR_RTO_12                                                  (0x1000U << USART_RTOR_RTO_Pos)
6441 #define USART_RTOR_RTO_13                                                  (0x2000U << USART_RTOR_RTO_Pos)
6442 #define USART_RTOR_RTO_14                                                  (0x4000U << USART_RTOR_RTO_Pos)
6443 #define USART_RTOR_RTO_15                                                  (0x8000U << USART_RTOR_RTO_Pos)
6444 #define USART_RTOR_RTO_16                                                  (0x10000U << USART_RTOR_RTO_Pos)
6445 #define USART_RTOR_RTO_17                                                  (0x20000U << USART_RTOR_RTO_Pos)
6446 #define USART_RTOR_RTO_18                                                  (0x40000U << USART_RTOR_RTO_Pos)
6447 #define USART_RTOR_RTO_19                                                  (0x80000U << USART_RTOR_RTO_Pos)
6448 #define USART_RTOR_RTO_20                                                  (0x100000U << USART_RTOR_RTO_Pos)
6449 #define USART_RTOR_RTO_21                                                  (0x200000U << USART_RTOR_RTO_Pos)
6450 #define USART_RTOR_RTO_22                                                  (0x400000U << USART_RTOR_RTO_Pos)
6451 #define USART_RTOR_RTO_23                                                  (0x800000U << USART_RTOR_RTO_Pos)
6452 
6453 /* =====================================================    RQR    ===================================================== */
6454 #define USART_RQR_TXFRQ_Pos                                                (4UL)    /*!<USART RQR: TXFRQ (Bit 4) */
6455 #define USART_RQR_TXFRQ_Msk                                                (0x10UL)   /*!< USART RQR: TXFRQ (Bitfield-Mask: 0x01) */
6456 #define USART_RQR_TXFRQ                                                    USART_RQR_TXFRQ_Msk
6457 #define USART_RQR_RXFRQ_Pos                                                (3UL)    /*!<USART RQR: RXFRQ (Bit 3) */
6458 #define USART_RQR_RXFRQ_Msk                                                (0x8UL)    /*!< USART RQR: RXFRQ (Bitfield-Mask: 0x01) */
6459 #define USART_RQR_RXFRQ                                                    USART_RQR_RXFRQ_Msk
6460 #define USART_RQR_MMRQ_Pos                                                 (2UL)    /*!<USART RQR: MMRQ (Bit 2) */
6461 #define USART_RQR_MMRQ_Msk                                                 (0x4UL)    /*!< USART RQR: MMRQ (Bitfield-Mask: 0x01) */
6462 #define USART_RQR_MMRQ                                                     USART_RQR_MMRQ_Msk
6463 #define USART_RQR_SBKRQ_Pos                                                (1UL)    /*!<USART RQR: SBKRQ (Bit 1) */
6464 #define USART_RQR_SBKRQ_Msk                                                (0x2UL)    /*!< USART RQR: SBKRQ (Bitfield-Mask: 0x01) */
6465 #define USART_RQR_SBKRQ                                                    USART_RQR_SBKRQ_Msk
6466 #define USART_RQR_ABRRQ_Pos                                                (0UL)    /*!<USART RQR: ABRRQ (Bit 0) */
6467 #define USART_RQR_ABRRQ_Msk                                                (0x1UL)    /*!< USART RQR: ABRRQ (Bitfield-Mask: 0x01) */
6468 #define USART_RQR_ABRRQ                                                    USART_RQR_ABRRQ_Msk
6469 
6470 /* =====================================================    ISR    ===================================================== */
6471 #define USART_ISR_TXFT_Pos                                                 (27UL)   /*!<USART ISR: TXFT (Bit 27) */
6472 #define USART_ISR_TXFT_Msk                                                 (0x8000000UL)    /*!< USART ISR: TXFT (Bitfield-Mask: 0x01) */
6473 #define USART_ISR_TXFT                                                     USART_ISR_TXFT_Msk
6474 #define USART_ISR_RXFT_Pos                                                 (26UL)   /*!<USART ISR: RXFT (Bit 26) */
6475 #define USART_ISR_RXFT_Msk                                                 (0x4000000UL)    /*!< USART ISR: RXFT (Bitfield-Mask: 0x01) */
6476 #define USART_ISR_RXFT                                                     USART_ISR_RXFT_Msk
6477 #define USART_ISR_TCBGT_Pos                                                (25UL)   /*!<USART ISR: TCBGT (Bit 25) */
6478 #define USART_ISR_TCBGT_Msk                                                (0x2000000UL)    /*!< USART ISR: TCBGT (Bitfield-Mask: 0x01) */
6479 #define USART_ISR_TCBGT                                                    USART_ISR_TCBGT_Msk
6480 #define USART_ISR_RXFF_Pos                                                 (24UL)   /*!<USART ISR: RXFF (Bit 24) */
6481 #define USART_ISR_RXFF_Msk                                                 (0x1000000UL)    /*!< USART ISR: RXFF (Bitfield-Mask: 0x01) */
6482 #define USART_ISR_RXFF                                                     USART_ISR_RXFF_Msk
6483 #define USART_ISR_TXFE_Pos                                                 (23UL)   /*!<USART ISR: TXFE (Bit 23) */
6484 #define USART_ISR_TXFE_Msk                                                 (0x800000UL)   /*!< USART ISR: TXFE (Bitfield-Mask: 0x01) */
6485 #define USART_ISR_TXFE                                                     USART_ISR_TXFE_Msk
6486 #define USART_ISR_REACK_Pos                                                (22UL)   /*!<USART ISR: REACK (Bit 22) */
6487 #define USART_ISR_REACK_Msk                                                (0x400000UL)   /*!< USART ISR: REACK (Bitfield-Mask: 0x01) */
6488 #define USART_ISR_REACK                                                    USART_ISR_REACK_Msk
6489 #define USART_ISR_TEACK_Pos                                                (21UL)   /*!<USART ISR: TEACK (Bit 21) */
6490 #define USART_ISR_TEACK_Msk                                                (0x200000UL)   /*!< USART ISR: TEACK (Bitfield-Mask: 0x01) */
6491 #define USART_ISR_TEACK                                                    USART_ISR_TEACK_Msk
6492 #define USART_ISR_RWU_Pos                                                  (19UL)   /*!<USART ISR: RWU (Bit 19) */
6493 #define USART_ISR_RWU_Msk                                                  (0x80000UL)    /*!< USART ISR: RWU (Bitfield-Mask: 0x01) */
6494 #define USART_ISR_RWU                                                      USART_ISR_RWU_Msk
6495 #define USART_ISR_SBKF_Pos                                                 (18UL)   /*!<USART ISR: SBKF (Bit 18) */
6496 #define USART_ISR_SBKF_Msk                                                 (0x40000UL)    /*!< USART ISR: SBKF (Bitfield-Mask: 0x01) */
6497 #define USART_ISR_SBKF                                                     USART_ISR_SBKF_Msk
6498 #define USART_ISR_CMF_Pos                                                  (17UL)   /*!<USART ISR: CMF (Bit 17) */
6499 #define USART_ISR_CMF_Msk                                                  (0x20000UL)    /*!< USART ISR: CMF (Bitfield-Mask: 0x01) */
6500 #define USART_ISR_CMF                                                      USART_ISR_CMF_Msk
6501 #define USART_ISR_BUSY_Pos                                                 (16UL)   /*!<USART ISR: BUSY (Bit 16) */
6502 #define USART_ISR_BUSY_Msk                                                 (0x10000UL)    /*!< USART ISR: BUSY (Bitfield-Mask: 0x01) */
6503 #define USART_ISR_BUSY                                                     USART_ISR_BUSY_Msk
6504 #define USART_ISR_ABRF_Pos                                                 (15UL)   /*!<USART ISR: ABRF (Bit 15) */
6505 #define USART_ISR_ABRF_Msk                                                 (0x8000UL)   /*!< USART ISR: ABRF (Bitfield-Mask: 0x01) */
6506 #define USART_ISR_ABRF                                                     USART_ISR_ABRF_Msk
6507 #define USART_ISR_ABRE_Pos                                                 (14UL)   /*!<USART ISR: ABRE (Bit 14) */
6508 #define USART_ISR_ABRE_Msk                                                 (0x4000UL)   /*!< USART ISR: ABRE (Bitfield-Mask: 0x01) */
6509 #define USART_ISR_ABRE                                                     USART_ISR_ABRE_Msk
6510 #define USART_ISR_UDR_Pos                                                  (13UL)   /*!<USART ISR: UDR (Bit 13) */
6511 #define USART_ISR_UDR_Msk                                                  (0x2000UL)   /*!< USART ISR: UDR (Bitfield-Mask: 0x01) */
6512 #define USART_ISR_UDR                                                      USART_ISR_UDR_Msk
6513 #define USART_ISR_EOBF_Pos                                                 (12UL)   /*!<USART ISR: EOBF (Bit 12) */
6514 #define USART_ISR_EOBF_Msk                                                 (0x1000UL)   /*!< USART ISR: EOBF (Bitfield-Mask: 0x01) */
6515 #define USART_ISR_EOBF                                                     USART_ISR_EOBF_Msk
6516 #define USART_ISR_RTOF_Pos                                                 (11UL)   /*!<USART ISR: RTOF (Bit 11) */
6517 #define USART_ISR_RTOF_Msk                                                 (0x800UL)    /*!< USART ISR: RTOF (Bitfield-Mask: 0x01) */
6518 #define USART_ISR_RTOF                                                     USART_ISR_RTOF_Msk
6519 #define USART_ISR_CTS_Pos                                                  (10UL)   /*!<USART ISR: CTS (Bit 10) */
6520 #define USART_ISR_CTS_Msk                                                  (0x400UL)    /*!< USART ISR: CTS (Bitfield-Mask: 0x01) */
6521 #define USART_ISR_CTS                                                      USART_ISR_CTS_Msk
6522 #define USART_ISR_CTSIF_Pos                                                (9UL)    /*!<USART ISR: CTSIF (Bit 9) */
6523 #define USART_ISR_CTSIF_Msk                                                (0x200UL)    /*!< USART ISR: CTSIF (Bitfield-Mask: 0x01) */
6524 #define USART_ISR_CTSIF                                                    USART_ISR_CTSIF_Msk
6525 #define USART_ISR_LBDF_Pos                                                 (8UL)    /*!<USART ISR: LBDF (Bit 8) */
6526 #define USART_ISR_LBDF_Msk                                                 (0x100UL)    /*!< USART ISR: LBDF (Bitfield-Mask: 0x01) */
6527 #define USART_ISR_LBDF                                                     USART_ISR_LBDF_Msk
6528 #define USART_ISR_TXE_TXFNF_Pos                                            (7UL)    /*!<USART ISR: TXE_TXFNF (Bit 7) */
6529 #define USART_ISR_TXE_TXFNF_Msk                                            (0x80UL)   /*!< USART ISR: TXE_TXFNF (Bitfield-Mask: 0x01) */
6530 #define USART_ISR_TXE_TXFNF                                                USART_ISR_TXE_TXFNF_Msk
6531 #define USART_ISR_TC_Pos                                                   (6UL)    /*!<USART ISR: TC (Bit 6) */
6532 #define USART_ISR_TC_Msk                                                   (0x40UL)   /*!< USART ISR: TC (Bitfield-Mask: 0x01) */
6533 #define USART_ISR_TC                                                       USART_ISR_TC_Msk
6534 #define USART_ISR_RXNE_RXFNE_Pos                                           (5UL)    /*!<USART ISR: RXNE_RXFNE (Bit 5) */
6535 #define USART_ISR_RXNE_RXFNE_Msk                                           (0x20UL)   /*!< USART ISR: RXNE_RXFNE (Bitfield-Mask: 0x01) */
6536 #define USART_ISR_RXNE_RXFNE                                               USART_ISR_RXNE_RXFNE_Msk
6537 #define USART_ISR_IDLE_Pos                                                 (4UL)    /*!<USART ISR: IDLE (Bit 4) */
6538 #define USART_ISR_IDLE_Msk                                                 (0x10UL)   /*!< USART ISR: IDLE (Bitfield-Mask: 0x01) */
6539 #define USART_ISR_IDLE                                                     USART_ISR_IDLE_Msk
6540 #define USART_ISR_ORE_Pos                                                  (3UL)    /*!<USART ISR: ORE (Bit 3) */
6541 #define USART_ISR_ORE_Msk                                                  (0x8UL)    /*!< USART ISR: ORE (Bitfield-Mask: 0x01) */
6542 #define USART_ISR_ORE                                                      USART_ISR_ORE_Msk
6543 #define USART_ISR_NE_Pos                                                   (2UL)    /*!<USART ISR: NE (Bit 2) */
6544 #define USART_ISR_NE_Msk                                                   (0x4UL)    /*!< USART ISR: NE (Bitfield-Mask: 0x01) */
6545 #define USART_ISR_NE                                                       USART_ISR_NE_Msk
6546 #define USART_ISR_FE_Pos                                                   (1UL)    /*!<USART ISR: FE (Bit 1) */
6547 #define USART_ISR_FE_Msk                                                   (0x2UL)    /*!< USART ISR: FE (Bitfield-Mask: 0x01) */
6548 #define USART_ISR_FE                                                       USART_ISR_FE_Msk
6549 #define USART_ISR_PE_Pos                                                   (0UL)    /*!<USART ISR: PE (Bit 0) */
6550 #define USART_ISR_PE_Msk                                                   (0x1UL)    /*!< USART ISR: PE (Bitfield-Mask: 0x01) */
6551 #define USART_ISR_PE                                                       USART_ISR_PE_Msk
6552 
6553 /* =====================================================    ICR    ===================================================== */
6554 #define USART_ICR_CMCF_Pos                                                 (17UL)   /*!<USART ICR: CMCF (Bit 17) */
6555 #define USART_ICR_CMCF_Msk                                                 (0x20000UL)    /*!< USART ICR: CMCF (Bitfield-Mask: 0x01) */
6556 #define USART_ICR_CMCF                                                     USART_ICR_CMCF_Msk
6557 #define USART_ICR_UDRCF_Pos                                                (13UL)   /*!<USART ICR: UDRCF (Bit 13) */
6558 #define USART_ICR_UDRCF_Msk                                                (0x2000UL)   /*!< USART ICR: UDRCF (Bitfield-Mask: 0x01) */
6559 #define USART_ICR_UDRCF                                                    USART_ICR_UDRCF_Msk
6560 #define USART_ICR_EOBCF_Pos                                                (12UL)   /*!<USART ICR: EOBCF (Bit 12) */
6561 #define USART_ICR_EOBCF_Msk                                                (0x1000UL)   /*!< USART ICR: EOBCF (Bitfield-Mask: 0x01) */
6562 #define USART_ICR_EOBCF                                                    USART_ICR_EOBCF_Msk
6563 #define USART_ICR_RTOCF_Pos                                                (11UL)   /*!<USART ICR: RTOCF (Bit 11) */
6564 #define USART_ICR_RTOCF_Msk                                                (0x800UL)    /*!< USART ICR: RTOCF (Bitfield-Mask: 0x01) */
6565 #define USART_ICR_RTOCF                                                    USART_ICR_RTOCF_Msk
6566 #define USART_ICR_CTSCF_Pos                                                (9UL)    /*!<USART ICR: CTSCF (Bit 9) */
6567 #define USART_ICR_CTSCF_Msk                                                (0x200UL)    /*!< USART ICR: CTSCF (Bitfield-Mask: 0x01) */
6568 #define USART_ICR_CTSCF                                                    USART_ICR_CTSCF_Msk
6569 #define USART_ICR_LBDCF_Pos                                                (8UL)    /*!<USART ICR: LBDCF (Bit 8) */
6570 #define USART_ICR_LBDCF_Msk                                                (0x100UL)    /*!< USART ICR: LBDCF (Bitfield-Mask: 0x01) */
6571 #define USART_ICR_LBDCF                                                    USART_ICR_LBDCF_Msk
6572 #define USART_ICR_TCBGTCF_Pos                                              (7UL)    /*!<USART ICR: TCBGTCF (Bit 7) */
6573 #define USART_ICR_TCBGTCF_Msk                                              (0x80UL)   /*!< USART ICR: TCBGTCF (Bitfield-Mask: 0x01) */
6574 #define USART_ICR_TCBGTCF                                                  USART_ICR_TCBGTCF_Msk
6575 #define USART_ICR_TCCF_Pos                                                 (6UL)    /*!<USART ICR: TCCF (Bit 6) */
6576 #define USART_ICR_TCCF_Msk                                                 (0x40UL)   /*!< USART ICR: TCCF (Bitfield-Mask: 0x01) */
6577 #define USART_ICR_TCCF                                                     USART_ICR_TCCF_Msk
6578 #define USART_ICR_TXFECF_Pos                                               (5UL)    /*!<USART ICR: TXFECF (Bit 5) */
6579 #define USART_ICR_TXFECF_Msk                                               (0x20UL)   /*!< USART ICR: TXFECF (Bitfield-Mask: 0x01) */
6580 #define USART_ICR_TXFECF                                                   USART_ICR_TXFECF_Msk
6581 #define USART_ICR_IDLECF_Pos                                               (4UL)    /*!<USART ICR: IDLECF (Bit 4) */
6582 #define USART_ICR_IDLECF_Msk                                               (0x10UL)   /*!< USART ICR: IDLECF (Bitfield-Mask: 0x01) */
6583 #define USART_ICR_IDLECF                                                   USART_ICR_IDLECF_Msk
6584 #define USART_ICR_ORECF_Pos                                                (3UL)    /*!<USART ICR: ORECF (Bit 3) */
6585 #define USART_ICR_ORECF_Msk                                                (0x8UL)    /*!< USART ICR: ORECF (Bitfield-Mask: 0x01) */
6586 #define USART_ICR_ORECF                                                    USART_ICR_ORECF_Msk
6587 #define USART_ICR_NECF_Pos                                                 (2UL)    /*!<USART ICR: NECF (Bit 2) */
6588 #define USART_ICR_NECF_Msk                                                 (0x4UL)    /*!< USART ICR: NECF (Bitfield-Mask: 0x01) */
6589 #define USART_ICR_NECF                                                     USART_ICR_NECF_Msk
6590 #define USART_ICR_FECF_Pos                                                 (1UL)    /*!<USART ICR: FECF (Bit 1) */
6591 #define USART_ICR_FECF_Msk                                                 (0x2UL)    /*!< USART ICR: FECF (Bitfield-Mask: 0x01) */
6592 #define USART_ICR_FECF                                                     USART_ICR_FECF_Msk
6593 #define USART_ICR_PECF_Pos                                                 (0UL)    /*!<USART ICR: PECF (Bit 0) */
6594 #define USART_ICR_PECF_Msk                                                 (0x1UL)    /*!< USART ICR: PECF (Bitfield-Mask: 0x01) */
6595 #define USART_ICR_PECF                                                     USART_ICR_PECF_Msk
6596 
6597 /* =====================================================    RDR    ===================================================== */
6598 #define USART_RDR_RDR_Pos                                                  (0UL)    /*!<USART RDR: RDR (Bit 0) */
6599 #define USART_RDR_RDR_Msk                                                  (0x1ffUL)    /*!< USART RDR: RDR (Bitfield-Mask: 0x1ff) */
6600 #define USART_RDR_RDR                                                      USART_RDR_RDR_Msk
6601 #define USART_RDR_RDR_0                                                    (0x1U << USART_RDR_RDR_Pos)
6602 #define USART_RDR_RDR_1                                                    (0x2U << USART_RDR_RDR_Pos)
6603 #define USART_RDR_RDR_2                                                    (0x4U << USART_RDR_RDR_Pos)
6604 #define USART_RDR_RDR_3                                                    (0x8U << USART_RDR_RDR_Pos)
6605 #define USART_RDR_RDR_4                                                    (0x10U << USART_RDR_RDR_Pos)
6606 #define USART_RDR_RDR_5                                                    (0x20U << USART_RDR_RDR_Pos)
6607 #define USART_RDR_RDR_6                                                    (0x40U << USART_RDR_RDR_Pos)
6608 #define USART_RDR_RDR_7                                                    (0x80U << USART_RDR_RDR_Pos)
6609 #define USART_RDR_RDR_8                                                    (0x100U << USART_RDR_RDR_Pos)
6610 
6611 /* =====================================================    TDR    ===================================================== */
6612 #define USART_TDR_TDR_Pos                                                  (0UL)    /*!<USART TDR: TDR (Bit 0) */
6613 #define USART_TDR_TDR_Msk                                                  (0x1ffUL)    /*!< USART TDR: TDR (Bitfield-Mask: 0x1ff) */
6614 #define USART_TDR_TDR                                                      USART_TDR_TDR_Msk
6615 #define USART_TDR_TDR_0                                                    (0x1U << USART_TDR_TDR_Pos)
6616 #define USART_TDR_TDR_1                                                    (0x2U << USART_TDR_TDR_Pos)
6617 #define USART_TDR_TDR_2                                                    (0x4U << USART_TDR_TDR_Pos)
6618 #define USART_TDR_TDR_3                                                    (0x8U << USART_TDR_TDR_Pos)
6619 #define USART_TDR_TDR_4                                                    (0x10U << USART_TDR_TDR_Pos)
6620 #define USART_TDR_TDR_5                                                    (0x20U << USART_TDR_TDR_Pos)
6621 #define USART_TDR_TDR_6                                                    (0x40U << USART_TDR_TDR_Pos)
6622 #define USART_TDR_TDR_7                                                    (0x80U << USART_TDR_TDR_Pos)
6623 #define USART_TDR_TDR_8                                                    (0x100U << USART_TDR_TDR_Pos)
6624 
6625 /* =====================================================    PRESC    ===================================================== */
6626 #define USART_PRESC_PRESCALER_Pos                                          (0UL)    /*!<USART PRESC: PRESCALER (Bit 0) */
6627 #define USART_PRESC_PRESCALER_Msk                                          (0xfUL)    /*!< USART PRESC: PRESCALER (Bitfield-Mask: 0x0f) */
6628 #define USART_PRESC_PRESCALER                                              USART_PRESC_PRESCALER_Msk
6629 #define USART_PRESC_PRESCALER_0                                            (0x1U << USART_PRESC_PRESCALER_Pos)
6630 #define USART_PRESC_PRESCALER_1                                            (0x2U << USART_PRESC_PRESCALER_Pos)
6631 #define USART_PRESC_PRESCALER_2                                            (0x4U << USART_PRESC_PRESCALER_Pos)
6632 #define USART_PRESC_PRESCALER_3                                            (0x8U << USART_PRESC_PRESCALER_Pos)
6633 
6634 
6635 /* =========================================================================================================================== */
6636 /*=====================                                       RTC                                       ===================== */
6637 /* =========================================================================================================================== */
6638 
6639 /* =====================================================    TR    ===================================================== */
6640 #define RTC_TR_PM_Pos                                                      (22UL)   /*!<RTC TR: PM (Bit 22) */
6641 #define RTC_TR_PM_Msk                                                      (0x400000UL)   /*!< RTC TR: PM (Bitfield-Mask: 0x01) */
6642 #define RTC_TR_PM                                                          RTC_TR_PM_Msk
6643 #define RTC_TR_HT_Pos                                                      (20UL)   /*!<RTC TR: HT (Bit 20) */
6644 #define RTC_TR_HT_Msk                                                      (0x300000UL)   /*!< RTC TR: HT (Bitfield-Mask: 0x03) */
6645 #define RTC_TR_HT                                                          RTC_TR_HT_Msk
6646 #define RTC_TR_HT_0                                                        (0x1U << RTC_TR_HT_Pos)
6647 #define RTC_TR_HT_1                                                        (0x2U << RTC_TR_HT_Pos)
6648 #define RTC_TR_HU_Pos                                                      (16UL)   /*!<RTC TR: HU (Bit 16) */
6649 #define RTC_TR_HU_Msk                                                      (0xf0000UL)    /*!< RTC TR: HU (Bitfield-Mask: 0x0f) */
6650 #define RTC_TR_HU                                                          RTC_TR_HU_Msk
6651 #define RTC_TR_HU_0                                                        (0x1U << RTC_TR_HU_Pos)
6652 #define RTC_TR_HU_1                                                        (0x2U << RTC_TR_HU_Pos)
6653 #define RTC_TR_HU_2                                                        (0x4U << RTC_TR_HU_Pos)
6654 #define RTC_TR_HU_3                                                        (0x8U << RTC_TR_HU_Pos)
6655 #define RTC_TR_MNT_Pos                                                     (12UL)   /*!<RTC TR: MNT (Bit 12) */
6656 #define RTC_TR_MNT_Msk                                                     (0x7000UL)   /*!< RTC TR: MNT (Bitfield-Mask: 0x07) */
6657 #define RTC_TR_MNT                                                         RTC_TR_MNT_Msk
6658 #define RTC_TR_MNT_0                                                       (0x1U << RTC_TR_MNT_Pos)
6659 #define RTC_TR_MNT_1                                                       (0x2U << RTC_TR_MNT_Pos)
6660 #define RTC_TR_MNT_2                                                       (0x4U << RTC_TR_MNT_Pos)
6661 #define RTC_TR_MNU_Pos                                                     (8UL)    /*!<RTC TR: MNU (Bit 8) */
6662 #define RTC_TR_MNU_Msk                                                     (0xf00UL)    /*!< RTC TR: MNU (Bitfield-Mask: 0x0f) */
6663 #define RTC_TR_MNU                                                         RTC_TR_MNU_Msk
6664 #define RTC_TR_MNU_0                                                       (0x1U << RTC_TR_MNU_Pos)
6665 #define RTC_TR_MNU_1                                                       (0x2U << RTC_TR_MNU_Pos)
6666 #define RTC_TR_MNU_2                                                       (0x4U << RTC_TR_MNU_Pos)
6667 #define RTC_TR_MNU_3                                                       (0x8U << RTC_TR_MNU_Pos)
6668 #define RTC_TR_ST_Pos                                                      (4UL)    /*!<RTC TR: ST (Bit 4) */
6669 #define RTC_TR_ST_Msk                                                      (0x70UL)   /*!< RTC TR: ST (Bitfield-Mask: 0x07) */
6670 #define RTC_TR_ST                                                          RTC_TR_ST_Msk
6671 #define RTC_TR_ST_0                                                        (0x1U << RTC_TR_ST_Pos)
6672 #define RTC_TR_ST_1                                                        (0x2U << RTC_TR_ST_Pos)
6673 #define RTC_TR_ST_2                                                        (0x4U << RTC_TR_ST_Pos)
6674 #define RTC_TR_SU_Pos                                                      (0UL)    /*!<RTC TR: SU (Bit 0) */
6675 #define RTC_TR_SU_Msk                                                      (0xfUL)    /*!< RTC TR: SU (Bitfield-Mask: 0x0f) */
6676 #define RTC_TR_SU                                                          RTC_TR_SU_Msk
6677 #define RTC_TR_SU_0                                                        (0x1U << RTC_TR_SU_Pos)
6678 #define RTC_TR_SU_1                                                        (0x2U << RTC_TR_SU_Pos)
6679 #define RTC_TR_SU_2                                                        (0x4U << RTC_TR_SU_Pos)
6680 #define RTC_TR_SU_3                                                        (0x8U << RTC_TR_SU_Pos)
6681 
6682 /* =====================================================    DR    ===================================================== */
6683 #define RTC_DR_YT_Pos                                                      (20UL)   /*!<RTC DR: YT (Bit 20) */
6684 #define RTC_DR_YT_Msk                                                      (0xf00000UL)   /*!< RTC DR: YT (Bitfield-Mask: 0x0f) */
6685 #define RTC_DR_YT                                                          RTC_DR_YT_Msk
6686 #define RTC_DR_YT_0                                                        (0x1U << RTC_DR_YT_Pos)
6687 #define RTC_DR_YT_1                                                        (0x2U << RTC_DR_YT_Pos)
6688 #define RTC_DR_YT_2                                                        (0x4U << RTC_DR_YT_Pos)
6689 #define RTC_DR_YT_3                                                        (0x8U << RTC_DR_YT_Pos)
6690 #define RTC_DR_YU_Pos                                                      (16UL)   /*!<RTC DR: YU (Bit 16) */
6691 #define RTC_DR_YU_Msk                                                      (0xf0000UL)    /*!< RTC DR: YU (Bitfield-Mask: 0x0f) */
6692 #define RTC_DR_YU                                                          RTC_DR_YU_Msk
6693 #define RTC_DR_YU_0                                                        (0x1U << RTC_DR_YU_Pos)
6694 #define RTC_DR_YU_1                                                        (0x2U << RTC_DR_YU_Pos)
6695 #define RTC_DR_YU_2                                                        (0x4U << RTC_DR_YU_Pos)
6696 #define RTC_DR_YU_3                                                        (0x8U << RTC_DR_YU_Pos)
6697 #define RTC_DR_WDU_Pos                                                     (13UL)   /*!<RTC DR: WDU (Bit 13) */
6698 #define RTC_DR_WDU_Msk                                                     (0xe000UL)   /*!< RTC DR: WDU (Bitfield-Mask: 0x07) */
6699 #define RTC_DR_WDU                                                         RTC_DR_WDU_Msk
6700 #define RTC_DR_WDU_0                                                       (0x1U << RTC_DR_WDU_Pos)
6701 #define RTC_DR_WDU_1                                                       (0x2U << RTC_DR_WDU_Pos)
6702 #define RTC_DR_WDU_2                                                       (0x4U << RTC_DR_WDU_Pos)
6703 #define RTC_DR_MT_Pos                                                      (12UL)   /*!<RTC DR: MT (Bit 12) */
6704 #define RTC_DR_MT_Msk                                                      (0x1000UL)   /*!< RTC DR: MT (Bitfield-Mask: 0x01) */
6705 #define RTC_DR_MT                                                          RTC_DR_MT_Msk
6706 #define RTC_DR_MU_Pos                                                      (8UL)    /*!<RTC DR: MU (Bit 8) */
6707 #define RTC_DR_MU_Msk                                                      (0xf00UL)    /*!< RTC DR: MU (Bitfield-Mask: 0x0f) */
6708 #define RTC_DR_MU                                                          RTC_DR_MU_Msk
6709 #define RTC_DR_MU_0                                                        (0x1U << RTC_DR_MU_Pos)
6710 #define RTC_DR_MU_1                                                        (0x2U << RTC_DR_MU_Pos)
6711 #define RTC_DR_MU_2                                                        (0x4U << RTC_DR_MU_Pos)
6712 #define RTC_DR_MU_3                                                        (0x8U << RTC_DR_MU_Pos)
6713 #define RTC_DR_DT_Pos                                                      (4UL)    /*!<RTC DR: DT (Bit 4) */
6714 #define RTC_DR_DT_Msk                                                      (0x30UL)   /*!< RTC DR: DT (Bitfield-Mask: 0x03) */
6715 #define RTC_DR_DT                                                          RTC_DR_DT_Msk
6716 #define RTC_DR_DT_0                                                        (0x1U << RTC_DR_DT_Pos)
6717 #define RTC_DR_DT_1                                                        (0x2U << RTC_DR_DT_Pos)
6718 #define RTC_DR_DU_Pos                                                      (0UL)    /*!<RTC DR: DU (Bit 0) */
6719 #define RTC_DR_DU_Msk                                                      (0xfUL)    /*!< RTC DR: DU (Bitfield-Mask: 0x0f) */
6720 #define RTC_DR_DU                                                          RTC_DR_DU_Msk
6721 #define RTC_DR_DU_0                                                        (0x1U << RTC_DR_DU_Pos)
6722 #define RTC_DR_DU_1                                                        (0x2U << RTC_DR_DU_Pos)
6723 #define RTC_DR_DU_2                                                        (0x4U << RTC_DR_DU_Pos)
6724 #define RTC_DR_DU_3                                                        (0x8U << RTC_DR_DU_Pos)
6725 
6726 /* =====================================================    CR    ===================================================== */
6727 #define RTC_CR_COE_Pos                                                     (23UL)   /*!<RTC CR: COE (Bit 23) */
6728 #define RTC_CR_COE_Msk                                                     (0x800000UL)   /*!< RTC CR: COE (Bitfield-Mask: 0x01) */
6729 #define RTC_CR_COE                                                         RTC_CR_COE_Msk
6730 #define RTC_CR_OSEL_Pos                                                    (21UL)   /*!<RTC CR: OSEL (Bit 21) */
6731 #define RTC_CR_OSEL_Msk                                                    (0x600000UL)   /*!< RTC CR: OSEL (Bitfield-Mask: 0x03) */
6732 #define RTC_CR_OSEL                                                        RTC_CR_OSEL_Msk
6733 #define RTC_CR_OSEL_0                                                      (0x1U << RTC_CR_OSEL_Pos)
6734 #define RTC_CR_OSEL_1                                                      (0x2U << RTC_CR_OSEL_Pos)
6735 #define RTC_CR_POL_Pos                                                     (20UL)   /*!<RTC CR: POL (Bit 20) */
6736 #define RTC_CR_POL_Msk                                                     (0x100000UL)   /*!< RTC CR: POL (Bitfield-Mask: 0x01) */
6737 #define RTC_CR_POL                                                         RTC_CR_POL_Msk
6738 #define RTC_CR_COSEL_Pos                                                   (19UL)   /*!<RTC CR: COSEL (Bit 19) */
6739 #define RTC_CR_COSEL_Msk                                                   (0x80000UL)    /*!< RTC CR: COSEL (Bitfield-Mask: 0x01) */
6740 #define RTC_CR_COSEL                                                       RTC_CR_COSEL_Msk
6741 #define RTC_CR_BKP_Pos                                                     (18UL)   /*!<RTC CR: BKP (Bit 18) */
6742 #define RTC_CR_BKP_Msk                                                     (0x40000UL)    /*!< RTC CR: BKP (Bitfield-Mask: 0x01) */
6743 #define RTC_CR_BKP                                                         RTC_CR_BKP_Msk
6744 #define RTC_CR_SUB1H_Pos                                                   (17UL)   /*!<RTC CR: SUB1H (Bit 17) */
6745 #define RTC_CR_SUB1H_Msk                                                   (0x20000UL)    /*!< RTC CR: SUB1H (Bitfield-Mask: 0x01) */
6746 #define RTC_CR_SUB1H                                                       RTC_CR_SUB1H_Msk
6747 #define RTC_CR_ADD1H_Pos                                                   (16UL)   /*!<RTC CR: ADD1H (Bit 16) */
6748 #define RTC_CR_ADD1H_Msk                                                   (0x10000UL)    /*!< RTC CR: ADD1H (Bitfield-Mask: 0x01) */
6749 #define RTC_CR_ADD1H                                                       RTC_CR_ADD1H_Msk
6750 #define RTC_CR_WUTIE_Pos                                                   (14UL)   /*!<RTC CR: WUTIE (Bit 14) */
6751 #define RTC_CR_WUTIE_Msk                                                   (0x4000UL)   /*!< RTC CR: WUTIE (Bitfield-Mask: 0x01) */
6752 #define RTC_CR_WUTIE                                                       RTC_CR_WUTIE_Msk
6753 #define RTC_CR_ALRAIE_Pos                                                  (12UL)   /*!<RTC CR: ALRAIE (Bit 12) */
6754 #define RTC_CR_ALRAIE_Msk                                                  (0x1000UL)   /*!< RTC CR: ALRAIE (Bitfield-Mask: 0x01) */
6755 #define RTC_CR_ALRAIE                                                      RTC_CR_ALRAIE_Msk
6756 #define RTC_CR_WUTE_Pos                                                    (10UL)   /*!<RTC CR: WUTE (Bit 10) */
6757 #define RTC_CR_WUTE_Msk                                                    (0x400UL)    /*!< RTC CR: WUTE (Bitfield-Mask: 0x01) */
6758 #define RTC_CR_WUTE                                                        RTC_CR_WUTE_Msk
6759 #define RTC_CR_ALRAE_Pos                                                   (8UL)    /*!<RTC CR: ALRAE (Bit 8) */
6760 #define RTC_CR_ALRAE_Msk                                                   (0x100UL)    /*!< RTC CR: ALRAE (Bitfield-Mask: 0x01) */
6761 #define RTC_CR_ALRAE                                                       RTC_CR_ALRAE_Msk
6762 #define RTC_CR_FMT_Pos                                                     (6UL)    /*!<RTC CR: FMT (Bit 6) */
6763 #define RTC_CR_FMT_Msk                                                     (0x40UL)   /*!< RTC CR: FMT (Bitfield-Mask: 0x01) */
6764 #define RTC_CR_FMT                                                         RTC_CR_FMT_Msk
6765 #define RTC_CR_BYPSHAD_Pos                                                 (5UL)    /*!<RTC CR: BYPSHAD (Bit 5) */
6766 #define RTC_CR_BYPSHAD_Msk                                                 (0x20UL)   /*!< RTC CR: BYPSHAD (Bitfield-Mask: 0x01) */
6767 #define RTC_CR_BYPSHAD                                                     RTC_CR_BYPSHAD_Msk
6768 #define RTC_CR_WUCKSEL_Pos                                                 (0UL)    /*!<RTC CR: WUCKSEL (Bit 0) */
6769 #define RTC_CR_WUCKSEL_Msk                                                 (0x7UL)    /*!< RTC CR: WUCKSEL (Bitfield-Mask: 0x07) */
6770 #define RTC_CR_WUCKSEL                                                     RTC_CR_WUCKSEL_Msk
6771 #define RTC_CR_WUCKSEL_0                                                   (0x1U << RTC_CR_WUCKSEL_Pos)
6772 #define RTC_CR_WUCKSEL_1                                                   (0x2U << RTC_CR_WUCKSEL_Pos)
6773 #define RTC_CR_WUCKSEL_2                                                   (0x4U << RTC_CR_WUCKSEL_Pos)
6774 
6775 /* =====================================================    ISR    ===================================================== */
6776 #define RTC_ISR_RECALPF_Pos                                                (16UL)   /*!<RTC ISR: RECALPF (Bit 16) */
6777 #define RTC_ISR_RECALPF_Msk                                                (0x10000UL)    /*!< RTC ISR: RECALPF (Bitfield-Mask: 0x01) */
6778 #define RTC_ISR_RECALPF                                                    RTC_ISR_RECALPF_Msk
6779 #define RTC_ISR_WUTF_Pos                                                   (10UL)   /*!<RTC ISR: WUTF (Bit 10) */
6780 #define RTC_ISR_WUTF_Msk                                                   (0x400UL)    /*!< RTC ISR: WUTF (Bitfield-Mask: 0x01) */
6781 #define RTC_ISR_WUTF                                                       RTC_ISR_WUTF_Msk
6782 #define RTC_ISR_ALRAF_Pos                                                  (8UL)    /*!<RTC ISR: ALRAF (Bit 8) */
6783 #define RTC_ISR_ALRAF_Msk                                                  (0x100UL)    /*!< RTC ISR: ALRAF (Bitfield-Mask: 0x01) */
6784 #define RTC_ISR_ALRAF                                                      RTC_ISR_ALRAF_Msk
6785 #define RTC_ISR_INIT_Pos                                                   (7UL)    /*!<RTC ISR: INIT (Bit 7) */
6786 #define RTC_ISR_INIT_Msk                                                   (0x80UL)   /*!< RTC ISR: INIT (Bitfield-Mask: 0x01) */
6787 #define RTC_ISR_INIT                                                       RTC_ISR_INIT_Msk
6788 #define RTC_ISR_INITF_Pos                                                  (6UL)    /*!<RTC ISR: INITF (Bit 6) */
6789 #define RTC_ISR_INITF_Msk                                                  (0x40UL)   /*!< RTC ISR: INITF (Bitfield-Mask: 0x01) */
6790 #define RTC_ISR_INITF                                                      RTC_ISR_INITF_Msk
6791 #define RTC_ISR_RSF_Pos                                                    (5UL)    /*!<RTC ISR: RSF (Bit 5) */
6792 #define RTC_ISR_RSF_Msk                                                    (0x20UL)   /*!< RTC ISR: RSF (Bitfield-Mask: 0x01) */
6793 #define RTC_ISR_RSF                                                        RTC_ISR_RSF_Msk
6794 #define RTC_ISR_INITS_Pos                                                  (4UL)    /*!<RTC ISR: INITS (Bit 4) */
6795 #define RTC_ISR_INITS_Msk                                                  (0x10UL)   /*!< RTC ISR: INITS (Bitfield-Mask: 0x01) */
6796 #define RTC_ISR_INITS                                                      RTC_ISR_INITS_Msk
6797 #define RTC_ISR_SHPF_Pos                                                   (3UL)    /*!<RTC ISR: SHPF (Bit 3) */
6798 #define RTC_ISR_SHPF_Msk                                                   (0x8UL)    /*!< RTC ISR: SHPF (Bitfield-Mask: 0x01) */
6799 #define RTC_ISR_SHPF                                                       RTC_ISR_SHPF_Msk
6800 #define RTC_ISR_WUTWF_Pos                                                  (2UL)    /*!<RTC ISR: WUTWF (Bit 2) */
6801 #define RTC_ISR_WUTWF_Msk                                                  (0x4UL)    /*!< RTC ISR: WUTWF (Bitfield-Mask: 0x01) */
6802 #define RTC_ISR_WUTWF                                                      RTC_ISR_WUTWF_Msk
6803 #define RTC_ISR_ALRAWF_Pos                                                 (0UL)    /*!<RTC ISR: ALRAWF (Bit 0) */
6804 #define RTC_ISR_ALRAWF_Msk                                                 (0x1UL)    /*!< RTC ISR: ALRAWF (Bitfield-Mask: 0x01) */
6805 #define RTC_ISR_ALRAWF                                                     RTC_ISR_ALRAWF_Msk
6806 
6807 /* =====================================================    PRER    ===================================================== */
6808 #define RTC_PRER_PREDIV_A_Pos                                              (16UL)   /*!<RTC PRER: PREDIV_A (Bit 16) */
6809 #define RTC_PRER_PREDIV_A_Msk                                              (0x7f0000UL)   /*!< RTC PRER: PREDIV_A (Bitfield-Mask: 0x7f) */
6810 #define RTC_PRER_PREDIV_A                                                  RTC_PRER_PREDIV_A_Msk
6811 #define RTC_PRER_PREDIV_A_0                                                (0x1U << RTC_PRER_PREDIV_A_Pos)
6812 #define RTC_PRER_PREDIV_A_1                                                (0x2U << RTC_PRER_PREDIV_A_Pos)
6813 #define RTC_PRER_PREDIV_A_2                                                (0x4U << RTC_PRER_PREDIV_A_Pos)
6814 #define RTC_PRER_PREDIV_A_3                                                (0x8U << RTC_PRER_PREDIV_A_Pos)
6815 #define RTC_PRER_PREDIV_A_4                                                (0x10U << RTC_PRER_PREDIV_A_Pos)
6816 #define RTC_PRER_PREDIV_A_5                                                (0x20U << RTC_PRER_PREDIV_A_Pos)
6817 #define RTC_PRER_PREDIV_A_6                                                (0x40U << RTC_PRER_PREDIV_A_Pos)
6818 #define RTC_PRER_PREDIV_S_Pos                                              (0UL)    /*!<RTC PRER: PREDIV_S (Bit 0) */
6819 #define RTC_PRER_PREDIV_S_Msk                                              (0x7fffUL)   /*!< RTC PRER: PREDIV_S (Bitfield-Mask: 0x7fff) */
6820 #define RTC_PRER_PREDIV_S                                                  RTC_PRER_PREDIV_S_Msk
6821 #define RTC_PRER_PREDIV_S_0                                                (0x1U << RTC_PRER_PREDIV_S_Pos)
6822 #define RTC_PRER_PREDIV_S_1                                                (0x2U << RTC_PRER_PREDIV_S_Pos)
6823 #define RTC_PRER_PREDIV_S_2                                                (0x4U << RTC_PRER_PREDIV_S_Pos)
6824 #define RTC_PRER_PREDIV_S_3                                                (0x8U << RTC_PRER_PREDIV_S_Pos)
6825 #define RTC_PRER_PREDIV_S_4                                                (0x10U << RTC_PRER_PREDIV_S_Pos)
6826 #define RTC_PRER_PREDIV_S_5                                                (0x20U << RTC_PRER_PREDIV_S_Pos)
6827 #define RTC_PRER_PREDIV_S_6                                                (0x40U << RTC_PRER_PREDIV_S_Pos)
6828 #define RTC_PRER_PREDIV_S_7                                                (0x80U << RTC_PRER_PREDIV_S_Pos)
6829 #define RTC_PRER_PREDIV_S_8                                                (0x100U << RTC_PRER_PREDIV_S_Pos)
6830 #define RTC_PRER_PREDIV_S_9                                                (0x200U << RTC_PRER_PREDIV_S_Pos)
6831 #define RTC_PRER_PREDIV_S_10                                               (0x400U << RTC_PRER_PREDIV_S_Pos)
6832 #define RTC_PRER_PREDIV_S_11                                               (0x800U << RTC_PRER_PREDIV_S_Pos)
6833 #define RTC_PRER_PREDIV_S_12                                               (0x1000U << RTC_PRER_PREDIV_S_Pos)
6834 #define RTC_PRER_PREDIV_S_13                                               (0x2000U << RTC_PRER_PREDIV_S_Pos)
6835 #define RTC_PRER_PREDIV_S_14                                               (0x4000U << RTC_PRER_PREDIV_S_Pos)
6836 
6837 /* =====================================================    WUTR    ===================================================== */
6838 #define RTC_WUTR_WUT_Pos                                                   (0UL)    /*!<RTC WUTR: WUT (Bit 0) */
6839 #define RTC_WUTR_WUT_Msk                                                   (0xffffUL)   /*!< RTC WUTR: WUT (Bitfield-Mask: 0xffff) */
6840 #define RTC_WUTR_WUT                                                       RTC_WUTR_WUT_Msk
6841 #define RTC_WUTR_WUT_0                                                     (0x1U << RTC_WUTR_WUT_Pos)
6842 #define RTC_WUTR_WUT_1                                                     (0x2U << RTC_WUTR_WUT_Pos)
6843 #define RTC_WUTR_WUT_2                                                     (0x4U << RTC_WUTR_WUT_Pos)
6844 #define RTC_WUTR_WUT_3                                                     (0x8U << RTC_WUTR_WUT_Pos)
6845 #define RTC_WUTR_WUT_4                                                     (0x10U << RTC_WUTR_WUT_Pos)
6846 #define RTC_WUTR_WUT_5                                                     (0x20U << RTC_WUTR_WUT_Pos)
6847 #define RTC_WUTR_WUT_6                                                     (0x40U << RTC_WUTR_WUT_Pos)
6848 #define RTC_WUTR_WUT_7                                                     (0x80U << RTC_WUTR_WUT_Pos)
6849 #define RTC_WUTR_WUT_8                                                     (0x100U << RTC_WUTR_WUT_Pos)
6850 #define RTC_WUTR_WUT_9                                                     (0x200U << RTC_WUTR_WUT_Pos)
6851 #define RTC_WUTR_WUT_10                                                    (0x400U << RTC_WUTR_WUT_Pos)
6852 #define RTC_WUTR_WUT_11                                                    (0x800U << RTC_WUTR_WUT_Pos)
6853 #define RTC_WUTR_WUT_12                                                    (0x1000U << RTC_WUTR_WUT_Pos)
6854 #define RTC_WUTR_WUT_13                                                    (0x2000U << RTC_WUTR_WUT_Pos)
6855 #define RTC_WUTR_WUT_14                                                    (0x4000U << RTC_WUTR_WUT_Pos)
6856 #define RTC_WUTR_WUT_15                                                    (0x8000U << RTC_WUTR_WUT_Pos)
6857 
6858 /* =====================================================    ALRMAR    ===================================================== */
6859 #define RTC_ALRMAR_MSK4_Pos                                                (31UL)   /*!<RTC ALRMAR: MSK4 (Bit 31) */
6860 #define RTC_ALRMAR_MSK4_Msk                                                (0x80000000UL)   /*!< RTC ALRMAR: MSK4 (Bitfield-Mask: 0x01) */
6861 #define RTC_ALRMAR_MSK4                                                    RTC_ALRMAR_MSK4_Msk
6862 #define RTC_ALRMAR_WDSEL_Pos                                               (30UL)   /*!<RTC ALRMAR: WDSEL (Bit 30) */
6863 #define RTC_ALRMAR_WDSEL_Msk                                               (0x40000000UL)   /*!< RTC ALRMAR: WDSEL (Bitfield-Mask: 0x01) */
6864 #define RTC_ALRMAR_WDSEL                                                   RTC_ALRMAR_WDSEL_Msk
6865 #define RTC_ALRMAR_DT_Pos                                                  (28UL)   /*!<RTC ALRMAR: DT (Bit 28) */
6866 #define RTC_ALRMAR_DT_Msk                                                  (0x30000000UL)   /*!< RTC ALRMAR: DT (Bitfield-Mask: 0x03) */
6867 #define RTC_ALRMAR_DT                                                      RTC_ALRMAR_DT_Msk
6868 #define RTC_ALRMAR_DT_0                                                    (0x1U << RTC_ALRMAR_DT_Pos)
6869 #define RTC_ALRMAR_DT_1                                                    (0x2U << RTC_ALRMAR_DT_Pos)
6870 #define RTC_ALRMAR_DU_Pos                                                  (24UL)   /*!<RTC ALRMAR: DU (Bit 24) */
6871 #define RTC_ALRMAR_DU_Msk                                                  (0xf000000UL)    /*!< RTC ALRMAR: DU (Bitfield-Mask: 0x0f) */
6872 #define RTC_ALRMAR_DU                                                      RTC_ALRMAR_DU_Msk
6873 #define RTC_ALRMAR_DU_0                                                    (0x1U << RTC_ALRMAR_DU_Pos)
6874 #define RTC_ALRMAR_DU_1                                                    (0x2U << RTC_ALRMAR_DU_Pos)
6875 #define RTC_ALRMAR_DU_2                                                    (0x4U << RTC_ALRMAR_DU_Pos)
6876 #define RTC_ALRMAR_DU_3                                                    (0x8U << RTC_ALRMAR_DU_Pos)
6877 #define RTC_ALRMAR_MSK3_Pos                                                (23UL)   /*!<RTC ALRMAR: MSK3 (Bit 23) */
6878 #define RTC_ALRMAR_MSK3_Msk                                                (0x800000UL)   /*!< RTC ALRMAR: MSK3 (Bitfield-Mask: 0x01) */
6879 #define RTC_ALRMAR_MSK3                                                    RTC_ALRMAR_MSK3_Msk
6880 #define RTC_ALRMAR_PM_Pos                                                  (22UL)   /*!<RTC ALRMAR: PM (Bit 22) */
6881 #define RTC_ALRMAR_PM_Msk                                                  (0x400000UL)   /*!< RTC ALRMAR: PM (Bitfield-Mask: 0x01) */
6882 #define RTC_ALRMAR_PM                                                      RTC_ALRMAR_PM_Msk
6883 #define RTC_ALRMAR_HT_Pos                                                  (20UL)   /*!<RTC ALRMAR: HT (Bit 20) */
6884 #define RTC_ALRMAR_HT_Msk                                                  (0x300000UL)   /*!< RTC ALRMAR: HT (Bitfield-Mask: 0x03) */
6885 #define RTC_ALRMAR_HT                                                      RTC_ALRMAR_HT_Msk
6886 #define RTC_ALRMAR_HT_0                                                    (0x1U << RTC_ALRMAR_HT_Pos)
6887 #define RTC_ALRMAR_HT_1                                                    (0x2U << RTC_ALRMAR_HT_Pos)
6888 #define RTC_ALRMAR_HU_Pos                                                  (16UL)   /*!<RTC ALRMAR: HU (Bit 16) */
6889 #define RTC_ALRMAR_HU_Msk                                                  (0xf0000UL)    /*!< RTC ALRMAR: HU (Bitfield-Mask: 0x0f) */
6890 #define RTC_ALRMAR_HU                                                      RTC_ALRMAR_HU_Msk
6891 #define RTC_ALRMAR_HU_0                                                    (0x1U << RTC_ALRMAR_HU_Pos)
6892 #define RTC_ALRMAR_HU_1                                                    (0x2U << RTC_ALRMAR_HU_Pos)
6893 #define RTC_ALRMAR_HU_2                                                    (0x4U << RTC_ALRMAR_HU_Pos)
6894 #define RTC_ALRMAR_HU_3                                                    (0x8U << RTC_ALRMAR_HU_Pos)
6895 #define RTC_ALRMAR_MSK2_Pos                                                (15UL)   /*!<RTC ALRMAR: MSK2 (Bit 15) */
6896 #define RTC_ALRMAR_MSK2_Msk                                                (0x8000UL)   /*!< RTC ALRMAR: MSK2 (Bitfield-Mask: 0x01) */
6897 #define RTC_ALRMAR_MSK2                                                    RTC_ALRMAR_MSK2_Msk
6898 #define RTC_ALRMAR_MNT_Pos                                                 (12UL)   /*!<RTC ALRMAR: MNT (Bit 12) */
6899 #define RTC_ALRMAR_MNT_Msk                                                 (0x7000UL)   /*!< RTC ALRMAR: MNT (Bitfield-Mask: 0x07) */
6900 #define RTC_ALRMAR_MNT                                                     RTC_ALRMAR_MNT_Msk
6901 #define RTC_ALRMAR_MNT_0                                                   (0x1U << RTC_ALRMAR_MNT_Pos)
6902 #define RTC_ALRMAR_MNT_1                                                   (0x2U << RTC_ALRMAR_MNT_Pos)
6903 #define RTC_ALRMAR_MNT_2                                                   (0x4U << RTC_ALRMAR_MNT_Pos)
6904 #define RTC_ALRMAR_MNU_Pos                                                 (8UL)    /*!<RTC ALRMAR: MNU (Bit 8) */
6905 #define RTC_ALRMAR_MNU_Msk                                                 (0xf00UL)    /*!< RTC ALRMAR: MNU (Bitfield-Mask: 0x0f) */
6906 #define RTC_ALRMAR_MNU                                                     RTC_ALRMAR_MNU_Msk
6907 #define RTC_ALRMAR_MNU_0                                                   (0x1U << RTC_ALRMAR_MNU_Pos)
6908 #define RTC_ALRMAR_MNU_1                                                   (0x2U << RTC_ALRMAR_MNU_Pos)
6909 #define RTC_ALRMAR_MNU_2                                                   (0x4U << RTC_ALRMAR_MNU_Pos)
6910 #define RTC_ALRMAR_MNU_3                                                   (0x8U << RTC_ALRMAR_MNU_Pos)
6911 #define RTC_ALRMAR_MSK1_Pos                                                (7UL)    /*!<RTC ALRMAR: MSK1 (Bit 7) */
6912 #define RTC_ALRMAR_MSK1_Msk                                                (0x80UL)   /*!< RTC ALRMAR: MSK1 (Bitfield-Mask: 0x01) */
6913 #define RTC_ALRMAR_MSK1                                                    RTC_ALRMAR_MSK1_Msk
6914 #define RTC_ALRMAR_ST_Pos                                                  (4UL)    /*!<RTC ALRMAR: ST (Bit 4) */
6915 #define RTC_ALRMAR_ST_Msk                                                  (0x70UL)   /*!< RTC ALRMAR: ST (Bitfield-Mask: 0x07) */
6916 #define RTC_ALRMAR_ST                                                      RTC_ALRMAR_ST_Msk
6917 #define RTC_ALRMAR_ST_0                                                    (0x1U << RTC_ALRMAR_ST_Pos)
6918 #define RTC_ALRMAR_ST_1                                                    (0x2U << RTC_ALRMAR_ST_Pos)
6919 #define RTC_ALRMAR_ST_2                                                    (0x4U << RTC_ALRMAR_ST_Pos)
6920 #define RTC_ALRMAR_SU_Pos                                                  (0UL)    /*!<RTC ALRMAR: SU (Bit 0) */
6921 #define RTC_ALRMAR_SU_Msk                                                  (0xfUL)    /*!< RTC ALRMAR: SU (Bitfield-Mask: 0x0f) */
6922 #define RTC_ALRMAR_SU                                                      RTC_ALRMAR_SU_Msk
6923 #define RTC_ALRMAR_SU_0                                                    (0x1U << RTC_ALRMAR_SU_Pos)
6924 #define RTC_ALRMAR_SU_1                                                    (0x2U << RTC_ALRMAR_SU_Pos)
6925 #define RTC_ALRMAR_SU_2                                                    (0x4U << RTC_ALRMAR_SU_Pos)
6926 #define RTC_ALRMAR_SU_3                                                    (0x8U << RTC_ALRMAR_SU_Pos)
6927 
6928 /* =====================================================    WPR    ===================================================== */
6929 #define RTC_WPR_KEY_Pos                                                    (0UL)    /*!<RTC WPR: KEY (Bit 0) */
6930 #define RTC_WPR_KEY_Msk                                                    (0xffUL)   /*!< RTC WPR: KEY (Bitfield-Mask: 0xff) */
6931 #define RTC_WPR_KEY                                                        RTC_WPR_KEY_Msk
6932 #define RTC_WPR_KEY_0                                                      (0x1U << RTC_WPR_KEY_Pos)
6933 #define RTC_WPR_KEY_1                                                      (0x2U << RTC_WPR_KEY_Pos)
6934 #define RTC_WPR_KEY_2                                                      (0x4U << RTC_WPR_KEY_Pos)
6935 #define RTC_WPR_KEY_3                                                      (0x8U << RTC_WPR_KEY_Pos)
6936 #define RTC_WPR_KEY_4                                                      (0x10U << RTC_WPR_KEY_Pos)
6937 #define RTC_WPR_KEY_5                                                      (0x20U << RTC_WPR_KEY_Pos)
6938 #define RTC_WPR_KEY_6                                                      (0x40U << RTC_WPR_KEY_Pos)
6939 #define RTC_WPR_KEY_7                                                      (0x80U << RTC_WPR_KEY_Pos)
6940 
6941 /* =====================================================    SSR    ===================================================== */
6942 #define RTC_SSR_SS_Pos                                                     (0UL)    /*!<RTC SSR: SS (Bit 0) */
6943 #define RTC_SSR_SS_Msk                                                     (0xffffUL)   /*!< RTC SSR: SS (Bitfield-Mask: 0xffff) */
6944 #define RTC_SSR_SS                                                         RTC_SSR_SS_Msk
6945 #define RTC_SSR_SS_0                                                       (0x1U << RTC_SSR_SS_Pos)
6946 #define RTC_SSR_SS_1                                                       (0x2U << RTC_SSR_SS_Pos)
6947 #define RTC_SSR_SS_2                                                       (0x4U << RTC_SSR_SS_Pos)
6948 #define RTC_SSR_SS_3                                                       (0x8U << RTC_SSR_SS_Pos)
6949 #define RTC_SSR_SS_4                                                       (0x10U << RTC_SSR_SS_Pos)
6950 #define RTC_SSR_SS_5                                                       (0x20U << RTC_SSR_SS_Pos)
6951 #define RTC_SSR_SS_6                                                       (0x40U << RTC_SSR_SS_Pos)
6952 #define RTC_SSR_SS_7                                                       (0x80U << RTC_SSR_SS_Pos)
6953 #define RTC_SSR_SS_8                                                       (0x100U << RTC_SSR_SS_Pos)
6954 #define RTC_SSR_SS_9                                                       (0x200U << RTC_SSR_SS_Pos)
6955 #define RTC_SSR_SS_10                                                      (0x400U << RTC_SSR_SS_Pos)
6956 #define RTC_SSR_SS_11                                                      (0x800U << RTC_SSR_SS_Pos)
6957 #define RTC_SSR_SS_12                                                      (0x1000U << RTC_SSR_SS_Pos)
6958 #define RTC_SSR_SS_13                                                      (0x2000U << RTC_SSR_SS_Pos)
6959 #define RTC_SSR_SS_14                                                      (0x4000U << RTC_SSR_SS_Pos)
6960 #define RTC_SSR_SS_15                                                      (0x8000U << RTC_SSR_SS_Pos)
6961 
6962 /* =====================================================    SHIFTR    ===================================================== */
6963 #define RTC_SHIFTR_ADD1S_Pos                                               (31UL)   /*!<RTC SHIFTR: ADD1S (Bit 31) */
6964 #define RTC_SHIFTR_ADD1S_Msk                                               (0x80000000UL)   /*!< RTC SHIFTR: ADD1S (Bitfield-Mask: 0x01) */
6965 #define RTC_SHIFTR_ADD1S                                                   RTC_SHIFTR_ADD1S_Msk
6966 #define RTC_SHIFTR_SUBFS_Pos                                               (0UL)    /*!<RTC SHIFTR: SUBFS (Bit 0) */
6967 #define RTC_SHIFTR_SUBFS_Msk                                               (0x7fffUL)   /*!< RTC SHIFTR: SUBFS (Bitfield-Mask: 0x7fff) */
6968 #define RTC_SHIFTR_SUBFS                                                   RTC_SHIFTR_SUBFS_Msk
6969 #define RTC_SHIFTR_SUBFS_0                                                 (0x1U << RTC_SHIFTR_SUBFS_Pos)
6970 #define RTC_SHIFTR_SUBFS_1                                                 (0x2U << RTC_SHIFTR_SUBFS_Pos)
6971 #define RTC_SHIFTR_SUBFS_2                                                 (0x4U << RTC_SHIFTR_SUBFS_Pos)
6972 #define RTC_SHIFTR_SUBFS_3                                                 (0x8U << RTC_SHIFTR_SUBFS_Pos)
6973 #define RTC_SHIFTR_SUBFS_4                                                 (0x10U << RTC_SHIFTR_SUBFS_Pos)
6974 #define RTC_SHIFTR_SUBFS_5                                                 (0x20U << RTC_SHIFTR_SUBFS_Pos)
6975 #define RTC_SHIFTR_SUBFS_6                                                 (0x40U << RTC_SHIFTR_SUBFS_Pos)
6976 #define RTC_SHIFTR_SUBFS_7                                                 (0x80U << RTC_SHIFTR_SUBFS_Pos)
6977 #define RTC_SHIFTR_SUBFS_8                                                 (0x100U << RTC_SHIFTR_SUBFS_Pos)
6978 #define RTC_SHIFTR_SUBFS_9                                                 (0x200U << RTC_SHIFTR_SUBFS_Pos)
6979 #define RTC_SHIFTR_SUBFS_10                                                (0x400U << RTC_SHIFTR_SUBFS_Pos)
6980 #define RTC_SHIFTR_SUBFS_11                                                (0x800U << RTC_SHIFTR_SUBFS_Pos)
6981 #define RTC_SHIFTR_SUBFS_12                                                (0x1000U << RTC_SHIFTR_SUBFS_Pos)
6982 #define RTC_SHIFTR_SUBFS_13                                                (0x2000U << RTC_SHIFTR_SUBFS_Pos)
6983 #define RTC_SHIFTR_SUBFS_14                                                (0x4000U << RTC_SHIFTR_SUBFS_Pos)
6984 
6985 /* =====================================================    CALR    ===================================================== */
6986 #define RTC_CALR_CALP_Pos                                                  (15UL)   /*!<RTC CALR: CALP (Bit 15) */
6987 #define RTC_CALR_CALP_Msk                                                  (0x8000UL)   /*!< RTC CALR: CALP (Bitfield-Mask: 0x01) */
6988 #define RTC_CALR_CALP                                                      RTC_CALR_CALP_Msk
6989 #define RTC_CALR_CALW8_Pos                                                 (14UL)   /*!<RTC CALR: CALW8 (Bit 14) */
6990 #define RTC_CALR_CALW8_Msk                                                 (0x4000UL)   /*!< RTC CALR: CALW8 (Bitfield-Mask: 0x01) */
6991 #define RTC_CALR_CALW8                                                     RTC_CALR_CALW8_Msk
6992 #define RTC_CALR_CALW16_Pos                                                (13UL)   /*!<RTC CALR: CALW16 (Bit 13) */
6993 #define RTC_CALR_CALW16_Msk                                                (0x2000UL)   /*!< RTC CALR: CALW16 (Bitfield-Mask: 0x01) */
6994 #define RTC_CALR_CALW16                                                    RTC_CALR_CALW16_Msk
6995 #define RTC_CALR_CALM_Pos                                                  (0UL)    /*!<RTC CALR: CALM (Bit 0) */
6996 #define RTC_CALR_CALM_Msk                                                  (0x1ffUL)    /*!< RTC CALR: CALM (Bitfield-Mask: 0x1ff) */
6997 #define RTC_CALR_CALM                                                      RTC_CALR_CALM_Msk
6998 #define RTC_CALR_CALM_0                                                    (0x1U << RTC_CALR_CALM_Pos)
6999 #define RTC_CALR_CALM_1                                                    (0x2U << RTC_CALR_CALM_Pos)
7000 #define RTC_CALR_CALM_2                                                    (0x4U << RTC_CALR_CALM_Pos)
7001 #define RTC_CALR_CALM_3                                                    (0x8U << RTC_CALR_CALM_Pos)
7002 #define RTC_CALR_CALM_4                                                    (0x10U << RTC_CALR_CALM_Pos)
7003 #define RTC_CALR_CALM_5                                                    (0x20U << RTC_CALR_CALM_Pos)
7004 #define RTC_CALR_CALM_6                                                    (0x40U << RTC_CALR_CALM_Pos)
7005 #define RTC_CALR_CALM_7                                                    (0x80U << RTC_CALR_CALM_Pos)
7006 #define RTC_CALR_CALM_8                                                    (0x100U << RTC_CALR_CALM_Pos)
7007 
7008 /* =====================================================    ALRMASSR    ===================================================== */
7009 #define RTC_ALRMASSR_MASKSS_Pos                                            (24UL)   /*!<RTC ALRMASSR: MASKSS (Bit 24) */
7010 #define RTC_ALRMASSR_MASKSS_Msk                                            (0xf000000UL)    /*!< RTC ALRMASSR: MASKSS (Bitfield-Mask: 0x0f) */
7011 #define RTC_ALRMASSR_MASKSS                                                RTC_ALRMASSR_MASKSS_Msk
7012 #define RTC_ALRMASSR_MASKSS_0                                              (0x1U << RTC_ALRMASSR_MASKSS_Pos)
7013 #define RTC_ALRMASSR_MASKSS_1                                              (0x2U << RTC_ALRMASSR_MASKSS_Pos)
7014 #define RTC_ALRMASSR_MASKSS_2                                              (0x4U << RTC_ALRMASSR_MASKSS_Pos)
7015 #define RTC_ALRMASSR_MASKSS_3                                              (0x8U << RTC_ALRMASSR_MASKSS_Pos)
7016 #define RTC_ALRMASSR_SS_Pos                                                (0UL)    /*!<RTC ALRMASSR: SS (Bit 0) */
7017 #define RTC_ALRMASSR_SS_Msk                                                (0x7fffUL)   /*!< RTC ALRMASSR: SS (Bitfield-Mask: 0x7fff) */
7018 #define RTC_ALRMASSR_SS                                                    RTC_ALRMASSR_SS_Msk
7019 #define RTC_ALRMASSR_SS_0                                                  (0x1U << RTC_ALRMASSR_SS_Pos)
7020 #define RTC_ALRMASSR_SS_1                                                  (0x2U << RTC_ALRMASSR_SS_Pos)
7021 #define RTC_ALRMASSR_SS_2                                                  (0x4U << RTC_ALRMASSR_SS_Pos)
7022 #define RTC_ALRMASSR_SS_3                                                  (0x8U << RTC_ALRMASSR_SS_Pos)
7023 #define RTC_ALRMASSR_SS_4                                                  (0x10U << RTC_ALRMASSR_SS_Pos)
7024 #define RTC_ALRMASSR_SS_5                                                  (0x20U << RTC_ALRMASSR_SS_Pos)
7025 #define RTC_ALRMASSR_SS_6                                                  (0x40U << RTC_ALRMASSR_SS_Pos)
7026 #define RTC_ALRMASSR_SS_7                                                  (0x80U << RTC_ALRMASSR_SS_Pos)
7027 #define RTC_ALRMASSR_SS_8                                                  (0x100U << RTC_ALRMASSR_SS_Pos)
7028 #define RTC_ALRMASSR_SS_9                                                  (0x200U << RTC_ALRMASSR_SS_Pos)
7029 #define RTC_ALRMASSR_SS_10                                                 (0x400U << RTC_ALRMASSR_SS_Pos)
7030 #define RTC_ALRMASSR_SS_11                                                 (0x800U << RTC_ALRMASSR_SS_Pos)
7031 #define RTC_ALRMASSR_SS_12                                                 (0x1000U << RTC_ALRMASSR_SS_Pos)
7032 #define RTC_ALRMASSR_SS_13                                                 (0x2000U << RTC_ALRMASSR_SS_Pos)
7033 #define RTC_ALRMASSR_SS_14                                                 (0x4000U << RTC_ALRMASSR_SS_Pos)
7034 
7035 /* =====================================================    BKP0R    ===================================================== */
7036 #define RTC_BKP0R_BKP_Pos                                                  (0UL)    /*!<RTC BKP0R: BKP (Bit 0) */
7037 #define RTC_BKP0R_BKP_Msk                                                  (0xffffffffUL)   /*!< RTC BKP0R: BKP (Bitfield-Mask: 0xffffffff) */
7038 #define RTC_BKP0R_BKP                                                      RTC_BKP0R_BKP_Msk
7039 #define RTC_BKP0R_BKP_0                                                    (0x1U << RTC_BKP0R_BKP_Pos)
7040 #define RTC_BKP0R_BKP_1                                                    (0x2U << RTC_BKP0R_BKP_Pos)
7041 #define RTC_BKP0R_BKP_2                                                    (0x4U << RTC_BKP0R_BKP_Pos)
7042 #define RTC_BKP0R_BKP_3                                                    (0x8U << RTC_BKP0R_BKP_Pos)
7043 #define RTC_BKP0R_BKP_4                                                    (0x10U << RTC_BKP0R_BKP_Pos)
7044 #define RTC_BKP0R_BKP_5                                                    (0x20U << RTC_BKP0R_BKP_Pos)
7045 #define RTC_BKP0R_BKP_6                                                    (0x40U << RTC_BKP0R_BKP_Pos)
7046 #define RTC_BKP0R_BKP_7                                                    (0x80U << RTC_BKP0R_BKP_Pos)
7047 #define RTC_BKP0R_BKP_8                                                    (0x100U << RTC_BKP0R_BKP_Pos)
7048 #define RTC_BKP0R_BKP_9                                                    (0x200U << RTC_BKP0R_BKP_Pos)
7049 #define RTC_BKP0R_BKP_10                                                   (0x400U << RTC_BKP0R_BKP_Pos)
7050 #define RTC_BKP0R_BKP_11                                                   (0x800U << RTC_BKP0R_BKP_Pos)
7051 #define RTC_BKP0R_BKP_12                                                   (0x1000U << RTC_BKP0R_BKP_Pos)
7052 #define RTC_BKP0R_BKP_13                                                   (0x2000U << RTC_BKP0R_BKP_Pos)
7053 #define RTC_BKP0R_BKP_14                                                   (0x4000U << RTC_BKP0R_BKP_Pos)
7054 #define RTC_BKP0R_BKP_15                                                   (0x8000U << RTC_BKP0R_BKP_Pos)
7055 #define RTC_BKP0R_BKP_16                                                   (0x10000U << RTC_BKP0R_BKP_Pos)
7056 #define RTC_BKP0R_BKP_17                                                   (0x20000U << RTC_BKP0R_BKP_Pos)
7057 #define RTC_BKP0R_BKP_18                                                   (0x40000U << RTC_BKP0R_BKP_Pos)
7058 #define RTC_BKP0R_BKP_19                                                   (0x80000U << RTC_BKP0R_BKP_Pos)
7059 #define RTC_BKP0R_BKP_20                                                   (0x100000U << RTC_BKP0R_BKP_Pos)
7060 #define RTC_BKP0R_BKP_21                                                   (0x200000U << RTC_BKP0R_BKP_Pos)
7061 #define RTC_BKP0R_BKP_22                                                   (0x400000U << RTC_BKP0R_BKP_Pos)
7062 #define RTC_BKP0R_BKP_23                                                   (0x800000U << RTC_BKP0R_BKP_Pos)
7063 #define RTC_BKP0R_BKP_24                                                   (0x1000000U << RTC_BKP0R_BKP_Pos)
7064 #define RTC_BKP0R_BKP_25                                                   (0x2000000U << RTC_BKP0R_BKP_Pos)
7065 #define RTC_BKP0R_BKP_26                                                   (0x4000000U << RTC_BKP0R_BKP_Pos)
7066 #define RTC_BKP0R_BKP_27                                                   (0x8000000U << RTC_BKP0R_BKP_Pos)
7067 #define RTC_BKP0R_BKP_28                                                   (0x10000000U << RTC_BKP0R_BKP_Pos)
7068 #define RTC_BKP0R_BKP_29                                                   (0x20000000U << RTC_BKP0R_BKP_Pos)
7069 #define RTC_BKP0R_BKP_30                                                   (0x40000000U << RTC_BKP0R_BKP_Pos)
7070 #define RTC_BKP0R_BKP_31                                                   (0x80000000UL << RTC_BKP0R_BKP_Pos)
7071 
7072 /* =====================================================    BKP1R    ===================================================== */
7073 #define RTC_BKP1R_BKP_Pos                                                  (0UL)    /*!<RTC BKP1R: BKP (Bit 0) */
7074 #define RTC_BKP1R_BKP_Msk                                                  (0xffffffffUL)   /*!< RTC BKP1R: BKP (Bitfield-Mask: 0xffffffff) */
7075 #define RTC_BKP1R_BKP                                                      RTC_BKP1R_BKP_Msk
7076 #define RTC_BKP1R_BKP_0                                                    (0x1U << RTC_BKP1R_BKP_Pos)
7077 #define RTC_BKP1R_BKP_1                                                    (0x2U << RTC_BKP1R_BKP_Pos)
7078 #define RTC_BKP1R_BKP_2                                                    (0x4U << RTC_BKP1R_BKP_Pos)
7079 #define RTC_BKP1R_BKP_3                                                    (0x8U << RTC_BKP1R_BKP_Pos)
7080 #define RTC_BKP1R_BKP_4                                                    (0x10U << RTC_BKP1R_BKP_Pos)
7081 #define RTC_BKP1R_BKP_5                                                    (0x20U << RTC_BKP1R_BKP_Pos)
7082 #define RTC_BKP1R_BKP_6                                                    (0x40U << RTC_BKP1R_BKP_Pos)
7083 #define RTC_BKP1R_BKP_7                                                    (0x80U << RTC_BKP1R_BKP_Pos)
7084 #define RTC_BKP1R_BKP_8                                                    (0x100U << RTC_BKP1R_BKP_Pos)
7085 #define RTC_BKP1R_BKP_9                                                    (0x200U << RTC_BKP1R_BKP_Pos)
7086 #define RTC_BKP1R_BKP_10                                                   (0x400U << RTC_BKP1R_BKP_Pos)
7087 #define RTC_BKP1R_BKP_11                                                   (0x800U << RTC_BKP1R_BKP_Pos)
7088 #define RTC_BKP1R_BKP_12                                                   (0x1000U << RTC_BKP1R_BKP_Pos)
7089 #define RTC_BKP1R_BKP_13                                                   (0x2000U << RTC_BKP1R_BKP_Pos)
7090 #define RTC_BKP1R_BKP_14                                                   (0x4000U << RTC_BKP1R_BKP_Pos)
7091 #define RTC_BKP1R_BKP_15                                                   (0x8000U << RTC_BKP1R_BKP_Pos)
7092 #define RTC_BKP1R_BKP_16                                                   (0x10000U << RTC_BKP1R_BKP_Pos)
7093 #define RTC_BKP1R_BKP_17                                                   (0x20000U << RTC_BKP1R_BKP_Pos)
7094 #define RTC_BKP1R_BKP_18                                                   (0x40000U << RTC_BKP1R_BKP_Pos)
7095 #define RTC_BKP1R_BKP_19                                                   (0x80000U << RTC_BKP1R_BKP_Pos)
7096 #define RTC_BKP1R_BKP_20                                                   (0x100000U << RTC_BKP1R_BKP_Pos)
7097 #define RTC_BKP1R_BKP_21                                                   (0x200000U << RTC_BKP1R_BKP_Pos)
7098 #define RTC_BKP1R_BKP_22                                                   (0x400000U << RTC_BKP1R_BKP_Pos)
7099 #define RTC_BKP1R_BKP_23                                                   (0x800000U << RTC_BKP1R_BKP_Pos)
7100 #define RTC_BKP1R_BKP_24                                                   (0x1000000U << RTC_BKP1R_BKP_Pos)
7101 #define RTC_BKP1R_BKP_25                                                   (0x2000000U << RTC_BKP1R_BKP_Pos)
7102 #define RTC_BKP1R_BKP_26                                                   (0x4000000U << RTC_BKP1R_BKP_Pos)
7103 #define RTC_BKP1R_BKP_27                                                   (0x8000000U << RTC_BKP1R_BKP_Pos)
7104 #define RTC_BKP1R_BKP_28                                                   (0x10000000U << RTC_BKP1R_BKP_Pos)
7105 #define RTC_BKP1R_BKP_29                                                   (0x20000000U << RTC_BKP1R_BKP_Pos)
7106 #define RTC_BKP1R_BKP_30                                                   (0x40000000U << RTC_BKP1R_BKP_Pos)
7107 #define RTC_BKP1R_BKP_31                                                   (0x80000000UL << RTC_BKP1R_BKP_Pos)
7108 
7109 /******************** Number of backup registers ******************************/
7110 #define RTC_BKP_NUMBER                 (2U)
7111 
7112 /* =========================================================================================================================== */
7113 /* ================                                            PKA                                            ================ */
7114 /* =========================================================================================================================== */
7115 
7116 /* =====================================================    CSR    ===================================================== */
7117 #define PKA_CSR_SFT_RST_Pos                                                (7UL)    /*!<PKA CSR: SFT_RST (Bit 7) */
7118 #define PKA_CSR_SFT_RST_Msk                                                (0x80UL)   /*!< PKA CSR: SFT_RST (Bitfield-Mask: 0x01) */
7119 #define PKA_CSR_SFT_RST                                                    PKA_CSR_SFT_RST_Msk
7120 #define PKA_CSR_READY_Pos                                                  (1UL)    /*!<PKA CSR: READY (Bit 1) */
7121 #define PKA_CSR_READY_Msk                                                  (0x2UL)    /*!< PKA CSR: READY (Bitfield-Mask: 0x01) */
7122 #define PKA_CSR_READY                                                      PKA_CSR_READY_Msk
7123 #define PKA_CSR_GO_Pos                                                     (0UL)    /*!<PKA CSR: GO (Bit 0) */
7124 #define PKA_CSR_GO_Msk                                                     (0x1UL)    /*!< PKA CSR: GO (Bitfield-Mask: 0x01) */
7125 #define PKA_CSR_GO                                                         PKA_CSR_GO_Msk
7126 
7127 /* =====================================================    ISR    ===================================================== */
7128 #define PKA_ISR_ADD_ERR_Pos                                                (3UL)    /*!<PKA ISR: ADD_ERR (Bit 3) */
7129 #define PKA_ISR_ADD_ERR_Msk                                                (0x8UL)    /*!< PKA ISR: ADD_ERR (Bitfield-Mask: 0x01) */
7130 #define PKA_ISR_ADD_ERR                                                    PKA_ISR_ADD_ERR_Msk
7131 #define PKA_ISR_RAM_ERR_Pos                                                (2UL)    /*!<PKA ISR: RAM_ERR (Bit 2) */
7132 #define PKA_ISR_RAM_ERR_Msk                                                (0x4UL)    /*!< PKA ISR: RAM_ERR (Bitfield-Mask: 0x01) */
7133 #define PKA_ISR_RAM_ERR                                                    PKA_ISR_RAM_ERR_Msk
7134 #define PKA_ISR_PROC_END_Pos                                               (0UL)    /*!<PKA ISR: PROC_END (Bit 0) */
7135 #define PKA_ISR_PROC_END_Msk                                               (0x1UL)    /*!< PKA ISR: PROC_END (Bitfield-Mask: 0x01) */
7136 #define PKA_ISR_PROC_END                                                   PKA_ISR_PROC_END_Msk
7137 
7138 /* =====================================================    IEN    ===================================================== */
7139 #define PKA_IEN_ADDERR_EN_Pos                                              (3UL)    /*!<PKA IEN: ADDERR_EN (Bit 3) */
7140 #define PKA_IEN_ADDERR_EN_Msk                                              (0x8UL)    /*!< PKA IEN: ADDERR_EN (Bitfield-Mask: 0x01) */
7141 #define PKA_IEN_ADDERR_EN                                                  PKA_IEN_ADDERR_EN_Msk
7142 #define PKA_IEN_RAMERR_EN_Pos                                              (2UL)    /*!<PKA IEN: RAMERR_EN (Bit 2) */
7143 #define PKA_IEN_RAMERR_EN_Msk                                              (0x4UL)    /*!< PKA IEN: RAMERR_EN (Bitfield-Mask: 0x01) */
7144 #define PKA_IEN_RAMERR_EN                                                  PKA_IEN_RAMERR_EN_Msk
7145 #define PKA_IEN_READY_EN_Pos                                               (0UL)    /*!<PKA IEN: READY_EN (Bit 0) */
7146 #define PKA_IEN_READY_EN_Msk                                               (0x1UL)    /*!< PKA IEN: READY_EN (Bitfield-Mask: 0x01) */
7147 #define PKA_IEN_READY_EN                                                   PKA_IEN_READY_EN_Msk
7148 
7149 
7150 /* =========================================================================================================================== */
7151 /*=====================                                       ADC                                       ===================== */
7152 /* =========================================================================================================================== */
7153 #define ADC_SUPPORT_AUDIO_FEATURES
7154 
7155 /* =====================================================    VERSION_ID    ===================================================== */
7156 #define ADC_VERSION_ID_VERSION_ID_Pos                                      (0UL)    /*!<ADC VERSION_ID: VERSION_ID (Bit 0) */
7157 #define ADC_VERSION_ID_VERSION_ID_Msk                                      (0xffUL)   /*!< ADC VERSION_ID: VERSION_ID (Bitfield-Mask: 0xff) */
7158 #define ADC_VERSION_ID_VERSION_ID                                          ADC_VERSION_ID_VERSION_ID_Msk
7159 #define ADC_VERSION_ID_VERSION_ID_0                                        (0x1U << ADC_VERSION_ID_VERSION_ID_Pos)
7160 #define ADC_VERSION_ID_VERSION_ID_1                                        (0x2U << ADC_VERSION_ID_VERSION_ID_Pos)
7161 #define ADC_VERSION_ID_VERSION_ID_2                                        (0x4U << ADC_VERSION_ID_VERSION_ID_Pos)
7162 #define ADC_VERSION_ID_VERSION_ID_3                                        (0x8U << ADC_VERSION_ID_VERSION_ID_Pos)
7163 #define ADC_VERSION_ID_VERSION_ID_4                                        (0x10U << ADC_VERSION_ID_VERSION_ID_Pos)
7164 #define ADC_VERSION_ID_VERSION_ID_5                                        (0x20U << ADC_VERSION_ID_VERSION_ID_Pos)
7165 #define ADC_VERSION_ID_VERSION_ID_6                                        (0x40U << ADC_VERSION_ID_VERSION_ID_Pos)
7166 #define ADC_VERSION_ID_VERSION_ID_7                                        (0x80U << ADC_VERSION_ID_VERSION_ID_Pos)
7167 
7168 /* =====================================================    CONF    ===================================================== */
7169 #define ADC_CONF_VBIAS_PRECH_FORCE_Pos                                     (20UL)   /*!<ADC CONF: VBIAS_PRECH_FORCE (Bit 20) */
7170 #define ADC_CONF_VBIAS_PRECH_FORCE_Msk                                     (0x100000UL)   /*!< ADC CONF: VBIAS_PRECH_FORCE (Bitfield-Mask: 0x01) */
7171 #define ADC_CONF_VBIAS_PRECH_FORCE                                         ADC_CONF_VBIAS_PRECH_FORCE_Msk
7172 #define ADC_CONF_ADC_CONT_1V2_Pos                                          (19UL)   /*!<ADC CONF: ADC_CONT_1V2 (Bit 19) */
7173 #define ADC_CONF_ADC_CONT_1V2_Msk                                          (0x80000UL)    /*!< ADC CONF: ADC_CONT_1V2 (Bitfield-Mask: 0x01) */
7174 #define ADC_CONF_ADC_CONT_1V2                                              ADC_CONF_ADC_CONT_1V2_Msk
7175 #define ADC_CONF_BIT_INVERT_DIFF_Pos                                       (18UL)   /*!<ADC CONF: BIT_INVERT_DIFF (Bit 18) */
7176 #define ADC_CONF_BIT_INVERT_DIFF_Msk                                       (0x40000UL)    /*!< ADC CONF: BIT_INVERT_DIFF (Bitfield-Mask: 0x01) */
7177 #define ADC_CONF_BIT_INVERT_DIFF                                           ADC_CONF_BIT_INVERT_DIFF_Msk
7178 #define ADC_CONF_BIT_INVERT_SN_Pos                                         (17UL)   /*!<ADC CONF: BIT_INVERT_SN (Bit 17) */
7179 #define ADC_CONF_BIT_INVERT_SN_Msk                                         (0x20000UL)    /*!< ADC CONF: BIT_INVERT_SN (Bitfield-Mask: 0x01) */
7180 #define ADC_CONF_BIT_INVERT_SN                                             ADC_CONF_BIT_INVERT_SN_Msk
7181 #define ADC_CONF_OVR_DF_CFG_Pos                                            (16UL)   /*!<ADC CONF: OVR_DF_CFG (Bit 16) */
7182 #define ADC_CONF_OVR_DF_CFG_Msk                                            (0x10000UL)    /*!< ADC CONF: OVR_DF_CFG (Bitfield-Mask: 0x01) */
7183 #define ADC_CONF_OVR_DF_CFG                                                ADC_CONF_OVR_DF_CFG_Msk
7184 #define ADC_CONF_OVR_DS_CFG_Pos                                            (15UL)   /*!<ADC CONF: OVR_DS_CFG (Bit 15) */
7185 #define ADC_CONF_OVR_DS_CFG_Msk                                            (0x8000UL)   /*!< ADC CONF: OVR_DS_CFG (Bitfield-Mask: 0x01) */
7186 #define ADC_CONF_OVR_DS_CFG                                                ADC_CONF_OVR_DS_CFG_Msk
7187 #define ADC_CONF_DMA_DF_ENA_Pos                                            (14UL)   /*!<ADC CONF: DMA_DF_ENA (Bit 14) */
7188 #define ADC_CONF_DMA_DF_ENA_Msk                                            (0x4000UL)   /*!< ADC CONF: DMA_DF_ENA (Bitfield-Mask: 0x01) */
7189 #define ADC_CONF_DMA_DF_ENA                                                ADC_CONF_DMA_DF_ENA_Msk
7190 #define ADC_CONF_DMA_DS_ENA_Pos                                            (13UL)   /*!<ADC CONF: DMA_DS_ENA (Bit 13) */
7191 #define ADC_CONF_DMA_DS_ENA_Msk                                            (0x2000UL)   /*!< ADC CONF: DMA_DS_ENA (Bitfield-Mask: 0x01) */
7192 #define ADC_CONF_DMA_DS_ENA                                                ADC_CONF_DMA_DS_ENA_Msk
7193 #define ADC_CONF_SAMPLE_RATE_Pos                                           (11UL)   /*!<ADC CONF: SAMPLE_RATE (Bit 11) */
7194 #define ADC_CONF_SAMPLE_RATE_Msk                                           (0x1800UL)   /*!< ADC CONF: SAMPLE_RATE (Bitfield-Mask: 0x03) */
7195 #define ADC_CONF_SAMPLE_RATE                                               ADC_CONF_SAMPLE_RATE_Msk
7196 #define ADC_CONF_SAMPLE_RATE_0                                             (0x1U << ADC_CONF_SAMPLE_RATE_Pos)
7197 #define ADC_CONF_SAMPLE_RATE_1                                             (0x2U << ADC_CONF_SAMPLE_RATE_Pos)
7198 #define ADC_CONF_OP_MODE_Pos                                               (7UL)    /*!<ADC CONF: OP_MODE (Bit 7) */
7199 #define ADC_CONF_OP_MODE_Msk                                               (0x180UL)    /*!< ADC CONF: OP_MODE (Bitfield-Mask: 0x03) */
7200 #define ADC_CONF_OP_MODE                                                   ADC_CONF_OP_MODE_Msk
7201 #define ADC_CONF_OP_MODE_0                                                 (0x1U << ADC_CONF_OP_MODE_Pos)
7202 #define ADC_CONF_OP_MODE_1                                                 (0x2U << ADC_CONF_OP_MODE_Pos)
7203 #define ADC_CONF_SMPS_SYNCHRO_ENA_Pos                                      (6UL)    /*!<ADC CONF: SMPS_SYNCHRO_ENA (Bit 6) */
7204 #define ADC_CONF_SMPS_SYNCHRO_ENA_Msk                                      (0x40UL)   /*!< ADC CONF: SMPS_SYNCHRO_ENA (Bitfield-Mask: 0x01) */
7205 #define ADC_CONF_SMPS_SYNCHRO_ENA                                          ADC_CONF_SMPS_SYNCHRO_ENA_Msk
7206 #define ADC_CONF_SEQ_LEN_Pos                                               (2UL)    /*!<ADC CONF: SEQ_LEN (Bit 2) */
7207 #define ADC_CONF_SEQ_LEN_Msk                                               (0x3cUL)   /*!< ADC CONF: SEQ_LEN (Bitfield-Mask: 0x0f) */
7208 #define ADC_CONF_SEQ_LEN                                                   ADC_CONF_SEQ_LEN_Msk
7209 #define ADC_CONF_SEQ_LEN_0                                                 (0x1U << ADC_CONF_SEQ_LEN_Pos)
7210 #define ADC_CONF_SEQ_LEN_1                                                 (0x2U << ADC_CONF_SEQ_LEN_Pos)
7211 #define ADC_CONF_SEQ_LEN_2                                                 (0x4U << ADC_CONF_SEQ_LEN_Pos)
7212 #define ADC_CONF_SEQ_LEN_3                                                 (0x8U << ADC_CONF_SEQ_LEN_Pos)
7213 #define ADC_CONF_SEQUENCE_Pos                                              (1UL)    /*!<ADC CONF: SEQUENCE (Bit 1) */
7214 #define ADC_CONF_SEQUENCE_Msk                                              (0x2UL)    /*!< ADC CONF: SEQUENCE (Bitfield-Mask: 0x01) */
7215 #define ADC_CONF_SEQUENCE                                                  ADC_CONF_SEQUENCE_Msk
7216 #define ADC_CONF_CONT_Pos                                                  (0UL)    /*!<ADC CONF: CONT (Bit 0) */
7217 #define ADC_CONF_CONT_Msk                                                  (0x1UL)    /*!< ADC CONF: CONT (Bitfield-Mask: 0x01) */
7218 #define ADC_CONF_CONT                                                      ADC_CONF_CONT_Msk
7219 
7220 /* =====================================================    CTRL    ===================================================== */
7221 #define ADC_CTRL_ADC_LDO_ENA_Pos                                           (5UL)    /*!<ADC CTRL: ADC_LDO_ENA (Bit 5) */
7222 #define ADC_CTRL_ADC_LDO_ENA_Msk                                           (0x20UL)   /*!< ADC CTRL: ADC_LDO_ENA (Bitfield-Mask: 0x01) */
7223 #define ADC_CTRL_ADC_LDO_ENA                                               ADC_CTRL_ADC_LDO_ENA_Msk
7224 #define ADC_CTRL_DIG_AUD_MODE_Pos                                          (3UL)    /*!<ADC CTRL: DIG_AUD_MODE (Bit 3) */
7225 #define ADC_CTRL_DIG_AUD_MODE_Msk                                          (0x8UL)    /*!< ADC CTRL: DIG_AUD_MODE (Bitfield-Mask: 0x01) */
7226 #define ADC_CTRL_DIG_AUD_MODE                                              ADC_CTRL_DIG_AUD_MODE_Msk
7227 #define ADC_CTRL_STOP_OP_MODE_Pos                                          (2UL)    /*!<ADC CTRL: STOP_OP_MODE (Bit 2) */
7228 #define ADC_CTRL_STOP_OP_MODE_Msk                                          (0x4UL)    /*!< ADC CTRL: STOP_OP_MODE (Bitfield-Mask: 0x01) */
7229 #define ADC_CTRL_STOP_OP_MODE                                              ADC_CTRL_STOP_OP_MODE_Msk
7230 #define ADC_CTRL_START_CONV_Pos                                            (1UL)    /*!<ADC CTRL: START_CONV (Bit 1) */
7231 #define ADC_CTRL_START_CONV_Msk                                            (0x2UL)    /*!< ADC CTRL: START_CONV (Bitfield-Mask: 0x01) */
7232 #define ADC_CTRL_START_CONV                                                ADC_CTRL_START_CONV_Msk
7233 #define ADC_CTRL_ADC_ON_OFF_Pos                                            (0UL)    /*!<ADC CTRL: ADC_ON_OFF (Bit 0) */
7234 #define ADC_CTRL_ADC_ON_OFF_Msk                                            (0x1UL)    /*!< ADC CTRL: ADC_ON_OFF (Bitfield-Mask: 0x01) */
7235 #define ADC_CTRL_ADC_ON_OFF                                                ADC_CTRL_ADC_ON_OFF_Msk
7236 
7237 /* =====================================================    OCM_CTRL    ===================================================== */
7238 #define ADC_OCM_CTRL_OCM_ENA_Pos                                           (1UL)    /*!<ADC OCM_CTRL: OCM_ENA (Bit 1) */
7239 #define ADC_OCM_CTRL_OCM_ENA_Msk                                           (0x2UL)    /*!< ADC OCM_CTRL: OCM_ENA (Bitfield-Mask: 0x01) */
7240 #define ADC_OCM_CTRL_OCM_ENA                                               ADC_OCM_CTRL_OCM_ENA_Msk
7241 #define ADC_OCM_CTRL_OCM_SRC_Pos                                           (0UL)    /*!<ADC OCM_CTRL: OCM_SRC (Bit 0) */
7242 #define ADC_OCM_CTRL_OCM_SRC_Msk                                           (0x1UL)    /*!< ADC OCM_CTRL: OCM_SRC (Bitfield-Mask: 0x01) */
7243 #define ADC_OCM_CTRL_OCM_SRC                                               ADC_OCM_CTRL_OCM_SRC_Msk
7244 
7245 /* =====================================================    PGA_CONF    ===================================================== */
7246 #define ADC_PGA_CONF_PGA_BIAS_Pos                                          (4UL)    /*!<ADC PGA_CONF: PGA_BIAS (Bit 4) */
7247 #define ADC_PGA_CONF_PGA_BIAS_Msk                                          (0x70UL)   /*!< ADC PGA_CONF: PGA_BIAS (Bitfield-Mask: 0x07) */
7248 #define ADC_PGA_CONF_PGA_BIAS                                              ADC_PGA_CONF_PGA_BIAS_Msk
7249 #define ADC_PGA_CONF_PGA_BIAS_0                                            (0x1U << ADC_PGA_CONF_PGA_BIAS_Pos)
7250 #define ADC_PGA_CONF_PGA_BIAS_1                                            (0x2U << ADC_PGA_CONF_PGA_BIAS_Pos)
7251 #define ADC_PGA_CONF_PGA_BIAS_2                                            (0x4U << ADC_PGA_CONF_PGA_BIAS_Pos)
7252 #define ADC_PGA_CONF_PGA_GAIN_Pos                                          (0UL)    /*!<ADC PGA_CONF: PGA_GAIN (Bit 0) */
7253 #define ADC_PGA_CONF_PGA_GAIN_Msk                                          (0xfUL)    /*!< ADC PGA_CONF: PGA_GAIN (Bitfield-Mask: 0x0f) */
7254 #define ADC_PGA_CONF_PGA_GAIN                                              ADC_PGA_CONF_PGA_GAIN_Msk
7255 #define ADC_PGA_CONF_PGA_GAIN_0                                            (0x1U << ADC_PGA_CONF_PGA_GAIN_Pos)
7256 #define ADC_PGA_CONF_PGA_GAIN_1                                            (0x2U << ADC_PGA_CONF_PGA_GAIN_Pos)
7257 #define ADC_PGA_CONF_PGA_GAIN_2                                            (0x4U << ADC_PGA_CONF_PGA_GAIN_Pos)
7258 #define ADC_PGA_CONF_PGA_GAIN_3                                            (0x8U << ADC_PGA_CONF_PGA_GAIN_Pos)
7259 
7260 /* =====================================================    SWITCH    ===================================================== */
7261 #define ADC_SWITCH_SE_VIN_7_Pos                                            (14UL)   /*!<ADC SWITCH: SE_VIN_7 (Bit 14) */
7262 #define ADC_SWITCH_SE_VIN_7_Msk                                            (0xc000UL)   /*!< ADC SWITCH: SE_VIN_7 (Bitfield-Mask: 0x03) */
7263 #define ADC_SWITCH_SE_VIN_7                                                ADC_SWITCH_SE_VIN_7_Msk
7264 #define ADC_SWITCH_SE_VIN_7_0                                              (0x1U << ADC_SWITCH_SE_VIN_7_Pos)
7265 #define ADC_SWITCH_SE_VIN_7_1                                              (0x2U << ADC_SWITCH_SE_VIN_7_Pos)
7266 #define ADC_SWITCH_SE_VIN_6_Pos                                            (12UL)   /*!<ADC SWITCH: SE_VIN_6 (Bit 12) */
7267 #define ADC_SWITCH_SE_VIN_6_Msk                                            (0x3000UL)   /*!< ADC SWITCH: SE_VIN_6 (Bitfield-Mask: 0x03) */
7268 #define ADC_SWITCH_SE_VIN_6                                                ADC_SWITCH_SE_VIN_6_Msk
7269 #define ADC_SWITCH_SE_VIN_6_0                                              (0x1U << ADC_SWITCH_SE_VIN_6_Pos)
7270 #define ADC_SWITCH_SE_VIN_6_1                                              (0x2U << ADC_SWITCH_SE_VIN_6_Pos)
7271 #define ADC_SWITCH_SE_VIN_5_Pos                                            (10UL)   /*!<ADC SWITCH: SE_VIN_5 (Bit 10) */
7272 #define ADC_SWITCH_SE_VIN_5_Msk                                            (0xc00UL)    /*!< ADC SWITCH: SE_VIN_5 (Bitfield-Mask: 0x03) */
7273 #define ADC_SWITCH_SE_VIN_5                                                ADC_SWITCH_SE_VIN_5_Msk
7274 #define ADC_SWITCH_SE_VIN_5_0                                              (0x1U << ADC_SWITCH_SE_VIN_5_Pos)
7275 #define ADC_SWITCH_SE_VIN_5_1                                              (0x2U << ADC_SWITCH_SE_VIN_5_Pos)
7276 #define ADC_SWITCH_SE_VIN_4_Pos                                            (8UL)    /*!<ADC SWITCH: SE_VIN_4 (Bit 8) */
7277 #define ADC_SWITCH_SE_VIN_4_Msk                                            (0x300UL)    /*!< ADC SWITCH: SE_VIN_4 (Bitfield-Mask: 0x03) */
7278 #define ADC_SWITCH_SE_VIN_4                                                ADC_SWITCH_SE_VIN_4_Msk
7279 #define ADC_SWITCH_SE_VIN_4_0                                              (0x1U << ADC_SWITCH_SE_VIN_4_Pos)
7280 #define ADC_SWITCH_SE_VIN_4_1                                              (0x2U << ADC_SWITCH_SE_VIN_4_Pos)
7281 #define ADC_SWITCH_SE_VIN_3_Pos                                            (6UL)    /*!<ADC SWITCH: SE_VIN_3 (Bit 6) */
7282 #define ADC_SWITCH_SE_VIN_3_Msk                                            (0xc0UL)   /*!< ADC SWITCH: SE_VIN_3 (Bitfield-Mask: 0x03) */
7283 #define ADC_SWITCH_SE_VIN_3                                                ADC_SWITCH_SE_VIN_3_Msk
7284 #define ADC_SWITCH_SE_VIN_3_0                                              (0x1U << ADC_SWITCH_SE_VIN_3_Pos)
7285 #define ADC_SWITCH_SE_VIN_3_1                                              (0x2U << ADC_SWITCH_SE_VIN_3_Pos)
7286 #define ADC_SWITCH_SE_VIN_2_Pos                                            (4UL)    /*!<ADC SWITCH: SE_VIN_2 (Bit 4) */
7287 #define ADC_SWITCH_SE_VIN_2_Msk                                            (0x30UL)   /*!< ADC SWITCH: SE_VIN_2 (Bitfield-Mask: 0x03) */
7288 #define ADC_SWITCH_SE_VIN_2                                                ADC_SWITCH_SE_VIN_2_Msk
7289 #define ADC_SWITCH_SE_VIN_2_0                                              (0x1U << ADC_SWITCH_SE_VIN_2_Pos)
7290 #define ADC_SWITCH_SE_VIN_2_1                                              (0x2U << ADC_SWITCH_SE_VIN_2_Pos)
7291 #define ADC_SWITCH_SE_VIN_1_Pos                                            (2UL)    /*!<ADC SWITCH: SE_VIN_1 (Bit 2) */
7292 #define ADC_SWITCH_SE_VIN_1_Msk                                            (0xcUL)    /*!< ADC SWITCH: SE_VIN_1 (Bitfield-Mask: 0x03) */
7293 #define ADC_SWITCH_SE_VIN_1                                                ADC_SWITCH_SE_VIN_1_Msk
7294 #define ADC_SWITCH_SE_VIN_1_0                                              (0x1U << ADC_SWITCH_SE_VIN_1_Pos)
7295 #define ADC_SWITCH_SE_VIN_1_1                                              (0x2U << ADC_SWITCH_SE_VIN_1_Pos)
7296 #define ADC_SWITCH_SE_VIN_0_Pos                                            (0UL)    /*!<ADC SWITCH: SE_VIN_0 (Bit 0) */
7297 #define ADC_SWITCH_SE_VIN_0_Msk                                            (0x3UL)    /*!< ADC SWITCH: SE_VIN_0 (Bitfield-Mask: 0x03) */
7298 #define ADC_SWITCH_SE_VIN_0                                                ADC_SWITCH_SE_VIN_0_Msk
7299 #define ADC_SWITCH_SE_VIN_0_0                                              (0x1U << ADC_SWITCH_SE_VIN_0_Pos)
7300 #define ADC_SWITCH_SE_VIN_0_1                                              (0x2U << ADC_SWITCH_SE_VIN_0_Pos)
7301 
7302 /* =====================================================    DF_CONF    ===================================================== */
7303 #define ADC_DF_CONF_DF_HALF_D_EN_Pos                                       (17UL)   /*!<ADC DF_CONF: DF_HALF_D_EN (Bit 17) */
7304 #define ADC_DF_CONF_DF_HALF_D_EN_Msk                                       (0x20000UL)    /*!< ADC DF_CONF: DF_HALF_D_EN (Bitfield-Mask: 0x01) */
7305 #define ADC_DF_CONF_DF_HALF_D_EN                                           ADC_DF_CONF_DF_HALF_D_EN_Msk
7306 #define ADC_DF_CONF_DF_HPF_EN_Pos                                          (16UL)   /*!<ADC DF_CONF: DF_HPF_EN (Bit 16) */
7307 #define ADC_DF_CONF_DF_HPF_EN_Msk                                          (0x10000UL)    /*!< ADC DF_CONF: DF_HPF_EN (Bitfield-Mask: 0x01) */
7308 #define ADC_DF_CONF_DF_HPF_EN                                              ADC_DF_CONF_DF_HPF_EN_Msk
7309 #define ADC_DF_CONF_DF_MICROL_RN_Pos                                       (15UL)   /*!<ADC DF_CONF: DF_MICROL_RN (Bit 15) */
7310 #define ADC_DF_CONF_DF_MICROL_RN_Msk                                       (0x8000UL)   /*!< ADC DF_CONF: DF_MICROL_RN (Bitfield-Mask: 0x01) */
7311 #define ADC_DF_CONF_DF_MICROL_RN                                           ADC_DF_CONF_DF_MICROL_RN_Msk
7312 #define ADC_DF_CONF_PDM_RATE_Pos                                           (11UL)   /*!<ADC DF_CONF: PDM_RATE (Bit 11) */
7313 #define ADC_DF_CONF_PDM_RATE_Msk                                           (0x7800UL)   /*!< ADC DF_CONF: PDM_RATE (Bitfield-Mask: 0x0f) */
7314 #define ADC_DF_CONF_PDM_RATE                                               ADC_DF_CONF_PDM_RATE_Msk
7315 #define ADC_DF_CONF_PDM_RATE_0                                             (0x1U << ADC_DF_CONF_PDM_RATE_Pos)
7316 #define ADC_DF_CONF_PDM_RATE_1                                             (0x2U << ADC_DF_CONF_PDM_RATE_Pos)
7317 #define ADC_DF_CONF_PDM_RATE_2                                             (0x4U << ADC_DF_CONF_PDM_RATE_Pos)
7318 #define ADC_DF_CONF_PDM_RATE_3                                             (0x8U << ADC_DF_CONF_PDM_RATE_Pos)
7319 #define ADC_DF_CONF_DF_O_S2U_Pos                                           (10UL)   /*!<ADC DF_CONF: DF_O_S2U (Bit 10) */
7320 #define ADC_DF_CONF_DF_O_S2U_Msk                                           (0x400UL)    /*!< ADC DF_CONF: DF_O_S2U (Bitfield-Mask: 0x01) */
7321 #define ADC_DF_CONF_DF_O_S2U                                               ADC_DF_CONF_DF_O_S2U_Msk
7322 #define ADC_DF_CONF_DF_I_U2S_Pos                                           (9UL)    /*!<ADC DF_CONF: DF_I_U2S (Bit 9) */
7323 #define ADC_DF_CONF_DF_I_U2S_Msk                                           (0x200UL)    /*!< ADC DF_CONF: DF_I_U2S (Bitfield-Mask: 0x01) */
7324 #define ADC_DF_CONF_DF_I_U2S                                               ADC_DF_CONF_DF_I_U2S_Msk
7325 #define ADC_DF_CONF_DF_ITP1P2_Pos                                          (8UL)    /*!<ADC DF_CONF: DF_ITP1P2 (Bit 8) */
7326 #define ADC_DF_CONF_DF_ITP1P2_Msk                                          (0x100UL)    /*!< ADC DF_CONF: DF_ITP1P2 (Bitfield-Mask: 0x01) */
7327 #define ADC_DF_CONF_DF_ITP1P2                                              ADC_DF_CONF_DF_ITP1P2_Msk
7328 #define ADC_DF_CONF_DF_CIC_DHF_Pos                                         (7UL)    /*!<ADC DF_CONF: DF_CIC_DHF (Bit 7) */
7329 #define ADC_DF_CONF_DF_CIC_DHF_Msk                                         (0x80UL)   /*!< ADC DF_CONF: DF_CIC_DHF (Bitfield-Mask: 0x01) */
7330 #define ADC_DF_CONF_DF_CIC_DHF                                             ADC_DF_CONF_DF_CIC_DHF_Msk
7331 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos                                  (0UL)    /*!<ADC DF_CONF: DF_CIC_DEC_FACTOR (Bit 0) */
7332 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_Msk                                  (0x7fUL)   /*!< ADC DF_CONF: DF_CIC_DEC_FACTOR (Bitfield-Mask: 0x7f) */
7333 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR                                      ADC_DF_CONF_DF_CIC_DEC_FACTOR_Msk
7334 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_0                                    (0x1U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7335 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_1                                    (0x2U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7336 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_2                                    (0x4U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7337 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_3                                    (0x8U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7338 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_4                                    (0x10U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7339 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_5                                    (0x20U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7340 #define ADC_DF_CONF_DF_CIC_DEC_FACTOR_6                                    (0x40U << ADC_DF_CONF_DF_CIC_DEC_FACTOR_Pos)
7341 
7342 /* =====================================================    DS_CONF    ===================================================== */
7343 #define ADC_DS_CONF_DS_WIDTH_Pos                                           (3UL)    /*!<ADC DS_CONF: DS_WIDTH (Bit 3) */
7344 #define ADC_DS_CONF_DS_WIDTH_Msk                                           (0x38UL)   /*!< ADC DS_CONF: DS_WIDTH (Bitfield-Mask: 0x07) */
7345 #define ADC_DS_CONF_DS_WIDTH                                               ADC_DS_CONF_DS_WIDTH_Msk
7346 #define ADC_DS_CONF_DS_WIDTH_0                                             (0x1U << ADC_DS_CONF_DS_WIDTH_Pos)
7347 #define ADC_DS_CONF_DS_WIDTH_1                                             (0x2U << ADC_DS_CONF_DS_WIDTH_Pos)
7348 #define ADC_DS_CONF_DS_WIDTH_2                                             (0x4U << ADC_DS_CONF_DS_WIDTH_Pos)
7349 #define ADC_DS_CONF_DS_RATIO_Pos                                           (0UL)    /*!<ADC DS_CONF: DS_RATIO (Bit 0) */
7350 #define ADC_DS_CONF_DS_RATIO_Msk                                           (0x7UL)    /*!< ADC DS_CONF: DS_RATIO (Bitfield-Mask: 0x07) */
7351 #define ADC_DS_CONF_DS_RATIO                                               ADC_DS_CONF_DS_RATIO_Msk
7352 #define ADC_DS_CONF_DS_RATIO_0                                             (0x1U << ADC_DS_CONF_DS_RATIO_Pos)
7353 #define ADC_DS_CONF_DS_RATIO_1                                             (0x2U << ADC_DS_CONF_DS_RATIO_Pos)
7354 #define ADC_DS_CONF_DS_RATIO_2                                             (0x4U << ADC_DS_CONF_DS_RATIO_Pos)
7355 
7356 /* =====================================================    SEQ_1    ===================================================== */
7357 #define ADC_SEQ_1_SEQ7_Pos                                                 (28UL)   /*!<ADC SEQ_1: SEQ7 (Bit 28) */
7358 #define ADC_SEQ_1_SEQ7_Msk                                                 (0xf0000000UL)   /*!< ADC SEQ_1: SEQ7 (Bitfield-Mask: 0x0f) */
7359 #define ADC_SEQ_1_SEQ7                                                     ADC_SEQ_1_SEQ7_Msk
7360 #define ADC_SEQ_1_SEQ7_0                                                   (0x1U << ADC_SEQ_1_SEQ7_Pos)
7361 #define ADC_SEQ_1_SEQ7_1                                                   (0x2U << ADC_SEQ_1_SEQ7_Pos)
7362 #define ADC_SEQ_1_SEQ7_2                                                   (0x4U << ADC_SEQ_1_SEQ7_Pos)
7363 #define ADC_SEQ_1_SEQ7_3                                                   (0x8U << ADC_SEQ_1_SEQ7_Pos)
7364 #define ADC_SEQ_1_SEQ6_Pos                                                 (24UL)   /*!<ADC SEQ_1: SEQ6 (Bit 24) */
7365 #define ADC_SEQ_1_SEQ6_Msk                                                 (0xf000000UL)    /*!< ADC SEQ_1: SEQ6 (Bitfield-Mask: 0x0f) */
7366 #define ADC_SEQ_1_SEQ6                                                     ADC_SEQ_1_SEQ6_Msk
7367 #define ADC_SEQ_1_SEQ6_0                                                   (0x1U << ADC_SEQ_1_SEQ6_Pos)
7368 #define ADC_SEQ_1_SEQ6_1                                                   (0x2U << ADC_SEQ_1_SEQ6_Pos)
7369 #define ADC_SEQ_1_SEQ6_2                                                   (0x4U << ADC_SEQ_1_SEQ6_Pos)
7370 #define ADC_SEQ_1_SEQ6_3                                                   (0x8U << ADC_SEQ_1_SEQ6_Pos)
7371 #define ADC_SEQ_1_SEQ5_Pos                                                 (20UL)   /*!<ADC SEQ_1: SEQ5 (Bit 20) */
7372 #define ADC_SEQ_1_SEQ5_Msk                                                 (0xf00000UL)   /*!< ADC SEQ_1: SEQ5 (Bitfield-Mask: 0x0f) */
7373 #define ADC_SEQ_1_SEQ5                                                     ADC_SEQ_1_SEQ5_Msk
7374 #define ADC_SEQ_1_SEQ5_0                                                   (0x1U << ADC_SEQ_1_SEQ5_Pos)
7375 #define ADC_SEQ_1_SEQ5_1                                                   (0x2U << ADC_SEQ_1_SEQ5_Pos)
7376 #define ADC_SEQ_1_SEQ5_2                                                   (0x4U << ADC_SEQ_1_SEQ5_Pos)
7377 #define ADC_SEQ_1_SEQ5_3                                                   (0x8U << ADC_SEQ_1_SEQ5_Pos)
7378 #define ADC_SEQ_1_SEQ4_Pos                                                 (16UL)   /*!<ADC SEQ_1: SEQ4 (Bit 16) */
7379 #define ADC_SEQ_1_SEQ4_Msk                                                 (0xf0000UL)    /*!< ADC SEQ_1: SEQ4 (Bitfield-Mask: 0x0f) */
7380 #define ADC_SEQ_1_SEQ4                                                     ADC_SEQ_1_SEQ4_Msk
7381 #define ADC_SEQ_1_SEQ4_0                                                   (0x1U << ADC_SEQ_1_SEQ4_Pos)
7382 #define ADC_SEQ_1_SEQ4_1                                                   (0x2U << ADC_SEQ_1_SEQ4_Pos)
7383 #define ADC_SEQ_1_SEQ4_2                                                   (0x4U << ADC_SEQ_1_SEQ4_Pos)
7384 #define ADC_SEQ_1_SEQ4_3                                                   (0x8U << ADC_SEQ_1_SEQ4_Pos)
7385 #define ADC_SEQ_1_SEQ3_Pos                                                 (12UL)   /*!<ADC SEQ_1: SEQ3 (Bit 12) */
7386 #define ADC_SEQ_1_SEQ3_Msk                                                 (0xf000UL)   /*!< ADC SEQ_1: SEQ3 (Bitfield-Mask: 0x0f) */
7387 #define ADC_SEQ_1_SEQ3                                                     ADC_SEQ_1_SEQ3_Msk
7388 #define ADC_SEQ_1_SEQ3_0                                                   (0x1U << ADC_SEQ_1_SEQ3_Pos)
7389 #define ADC_SEQ_1_SEQ3_1                                                   (0x2U << ADC_SEQ_1_SEQ3_Pos)
7390 #define ADC_SEQ_1_SEQ3_2                                                   (0x4U << ADC_SEQ_1_SEQ3_Pos)
7391 #define ADC_SEQ_1_SEQ3_3                                                   (0x8U << ADC_SEQ_1_SEQ3_Pos)
7392 #define ADC_SEQ_1_SEQ2_Pos                                                 (8UL)    /*!<ADC SEQ_1: SEQ2 (Bit 8) */
7393 #define ADC_SEQ_1_SEQ2_Msk                                                 (0xf00UL)    /*!< ADC SEQ_1: SEQ2 (Bitfield-Mask: 0x0f) */
7394 #define ADC_SEQ_1_SEQ2                                                     ADC_SEQ_1_SEQ2_Msk
7395 #define ADC_SEQ_1_SEQ2_0                                                   (0x1U << ADC_SEQ_1_SEQ2_Pos)
7396 #define ADC_SEQ_1_SEQ2_1                                                   (0x2U << ADC_SEQ_1_SEQ2_Pos)
7397 #define ADC_SEQ_1_SEQ2_2                                                   (0x4U << ADC_SEQ_1_SEQ2_Pos)
7398 #define ADC_SEQ_1_SEQ2_3                                                   (0x8U << ADC_SEQ_1_SEQ2_Pos)
7399 #define ADC_SEQ_1_SEQ1_Pos                                                 (4UL)    /*!<ADC SEQ_1: SEQ1 (Bit 4) */
7400 #define ADC_SEQ_1_SEQ1_Msk                                                 (0xf0UL)   /*!< ADC SEQ_1: SEQ1 (Bitfield-Mask: 0x0f) */
7401 #define ADC_SEQ_1_SEQ1                                                     ADC_SEQ_1_SEQ1_Msk
7402 #define ADC_SEQ_1_SEQ1_0                                                   (0x1U << ADC_SEQ_1_SEQ1_Pos)
7403 #define ADC_SEQ_1_SEQ1_1                                                   (0x2U << ADC_SEQ_1_SEQ1_Pos)
7404 #define ADC_SEQ_1_SEQ1_2                                                   (0x4U << ADC_SEQ_1_SEQ1_Pos)
7405 #define ADC_SEQ_1_SEQ1_3                                                   (0x8U << ADC_SEQ_1_SEQ1_Pos)
7406 #define ADC_SEQ_1_SEQ0_Pos                                                 (0UL)    /*!<ADC SEQ_1: SEQ0 (Bit 0) */
7407 #define ADC_SEQ_1_SEQ0_Msk                                                 (0xfUL)    /*!< ADC SEQ_1: SEQ0 (Bitfield-Mask: 0x0f) */
7408 #define ADC_SEQ_1_SEQ0                                                     ADC_SEQ_1_SEQ0_Msk
7409 #define ADC_SEQ_1_SEQ0_0                                                   (0x1U << ADC_SEQ_1_SEQ0_Pos)
7410 #define ADC_SEQ_1_SEQ0_1                                                   (0x2U << ADC_SEQ_1_SEQ0_Pos)
7411 #define ADC_SEQ_1_SEQ0_2                                                   (0x4U << ADC_SEQ_1_SEQ0_Pos)
7412 #define ADC_SEQ_1_SEQ0_3                                                   (0x8U << ADC_SEQ_1_SEQ0_Pos)
7413 
7414 /* =====================================================    SEQ_2    ===================================================== */
7415 #define ADC_SEQ_2_SEQ15_Pos                                                (28UL)   /*!<ADC SEQ_2: SEQ15 (Bit 28) */
7416 #define ADC_SEQ_2_SEQ15_Msk                                                (0xf0000000UL)   /*!< ADC SEQ_2: SEQ15 (Bitfield-Mask: 0x0f) */
7417 #define ADC_SEQ_2_SEQ15                                                    ADC_SEQ_2_SEQ15_Msk
7418 #define ADC_SEQ_2_SEQ15_0                                                  (0x1U << ADC_SEQ_2_SEQ15_Pos)
7419 #define ADC_SEQ_2_SEQ15_1                                                  (0x2U << ADC_SEQ_2_SEQ15_Pos)
7420 #define ADC_SEQ_2_SEQ15_2                                                  (0x4U << ADC_SEQ_2_SEQ15_Pos)
7421 #define ADC_SEQ_2_SEQ15_3                                                  (0x8U << ADC_SEQ_2_SEQ15_Pos)
7422 #define ADC_SEQ_2_SEQ14_Pos                                                (24UL)   /*!<ADC SEQ_2: SEQ14 (Bit 24) */
7423 #define ADC_SEQ_2_SEQ14_Msk                                                (0xf000000UL)    /*!< ADC SEQ_2: SEQ14 (Bitfield-Mask: 0x0f) */
7424 #define ADC_SEQ_2_SEQ14                                                    ADC_SEQ_2_SEQ14_Msk
7425 #define ADC_SEQ_2_SEQ14_0                                                  (0x1U << ADC_SEQ_2_SEQ14_Pos)
7426 #define ADC_SEQ_2_SEQ14_1                                                  (0x2U << ADC_SEQ_2_SEQ14_Pos)
7427 #define ADC_SEQ_2_SEQ14_2                                                  (0x4U << ADC_SEQ_2_SEQ14_Pos)
7428 #define ADC_SEQ_2_SEQ14_3                                                  (0x8U << ADC_SEQ_2_SEQ14_Pos)
7429 #define ADC_SEQ_2_SEQ13_Pos                                                (20UL)   /*!<ADC SEQ_2: SEQ13 (Bit 20) */
7430 #define ADC_SEQ_2_SEQ13_Msk                                                (0xf00000UL)   /*!< ADC SEQ_2: SEQ13 (Bitfield-Mask: 0x0f) */
7431 #define ADC_SEQ_2_SEQ13                                                    ADC_SEQ_2_SEQ13_Msk
7432 #define ADC_SEQ_2_SEQ13_0                                                  (0x1U << ADC_SEQ_2_SEQ13_Pos)
7433 #define ADC_SEQ_2_SEQ13_1                                                  (0x2U << ADC_SEQ_2_SEQ13_Pos)
7434 #define ADC_SEQ_2_SEQ13_2                                                  (0x4U << ADC_SEQ_2_SEQ13_Pos)
7435 #define ADC_SEQ_2_SEQ13_3                                                  (0x8U << ADC_SEQ_2_SEQ13_Pos)
7436 #define ADC_SEQ_2_SEQ12_Pos                                                (16UL)   /*!<ADC SEQ_2: SEQ12 (Bit 16) */
7437 #define ADC_SEQ_2_SEQ12_Msk                                                (0xf0000UL)    /*!< ADC SEQ_2: SEQ12 (Bitfield-Mask: 0x0f) */
7438 #define ADC_SEQ_2_SEQ12                                                    ADC_SEQ_2_SEQ12_Msk
7439 #define ADC_SEQ_2_SEQ12_0                                                  (0x1U << ADC_SEQ_2_SEQ12_Pos)
7440 #define ADC_SEQ_2_SEQ12_1                                                  (0x2U << ADC_SEQ_2_SEQ12_Pos)
7441 #define ADC_SEQ_2_SEQ12_2                                                  (0x4U << ADC_SEQ_2_SEQ12_Pos)
7442 #define ADC_SEQ_2_SEQ12_3                                                  (0x8U << ADC_SEQ_2_SEQ12_Pos)
7443 #define ADC_SEQ_2_SEQ11_Pos                                                (12UL)   /*!<ADC SEQ_2: SEQ11 (Bit 12) */
7444 #define ADC_SEQ_2_SEQ11_Msk                                                (0xf000UL)   /*!< ADC SEQ_2: SEQ11 (Bitfield-Mask: 0x0f) */
7445 #define ADC_SEQ_2_SEQ11                                                    ADC_SEQ_2_SEQ11_Msk
7446 #define ADC_SEQ_2_SEQ11_0                                                  (0x1U << ADC_SEQ_2_SEQ11_Pos)
7447 #define ADC_SEQ_2_SEQ11_1                                                  (0x2U << ADC_SEQ_2_SEQ11_Pos)
7448 #define ADC_SEQ_2_SEQ11_2                                                  (0x4U << ADC_SEQ_2_SEQ11_Pos)
7449 #define ADC_SEQ_2_SEQ11_3                                                  (0x8U << ADC_SEQ_2_SEQ11_Pos)
7450 #define ADC_SEQ_2_SEQ10_Pos                                                (8UL)    /*!<ADC SEQ_2: SEQ10 (Bit 8) */
7451 #define ADC_SEQ_2_SEQ10_Msk                                                (0xf00UL)    /*!< ADC SEQ_2: SEQ10 (Bitfield-Mask: 0x0f) */
7452 #define ADC_SEQ_2_SEQ10                                                    ADC_SEQ_2_SEQ10_Msk
7453 #define ADC_SEQ_2_SEQ10_0                                                  (0x1U << ADC_SEQ_2_SEQ10_Pos)
7454 #define ADC_SEQ_2_SEQ10_1                                                  (0x2U << ADC_SEQ_2_SEQ10_Pos)
7455 #define ADC_SEQ_2_SEQ10_2                                                  (0x4U << ADC_SEQ_2_SEQ10_Pos)
7456 #define ADC_SEQ_2_SEQ10_3                                                  (0x8U << ADC_SEQ_2_SEQ10_Pos)
7457 #define ADC_SEQ_2_SEQ9_Pos                                                 (4UL)    /*!<ADC SEQ_2: SEQ9 (Bit 4) */
7458 #define ADC_SEQ_2_SEQ9_Msk                                                 (0xf0UL)   /*!< ADC SEQ_2: SEQ9 (Bitfield-Mask: 0x0f) */
7459 #define ADC_SEQ_2_SEQ9                                                     ADC_SEQ_2_SEQ9_Msk
7460 #define ADC_SEQ_2_SEQ9_0                                                   (0x1U << ADC_SEQ_2_SEQ9_Pos)
7461 #define ADC_SEQ_2_SEQ9_1                                                   (0x2U << ADC_SEQ_2_SEQ9_Pos)
7462 #define ADC_SEQ_2_SEQ9_2                                                   (0x4U << ADC_SEQ_2_SEQ9_Pos)
7463 #define ADC_SEQ_2_SEQ9_3                                                   (0x8U << ADC_SEQ_2_SEQ9_Pos)
7464 #define ADC_SEQ_2_SEQ8_Pos                                                 (0UL)    /*!<ADC SEQ_2: SEQ8 (Bit 0) */
7465 #define ADC_SEQ_2_SEQ8_Msk                                                 (0xfUL)    /*!< ADC SEQ_2: SEQ8 (Bitfield-Mask: 0x0f) */
7466 #define ADC_SEQ_2_SEQ8                                                     ADC_SEQ_2_SEQ8_Msk
7467 #define ADC_SEQ_2_SEQ8_0                                                   (0x1U << ADC_SEQ_2_SEQ8_Pos)
7468 #define ADC_SEQ_2_SEQ8_1                                                   (0x2U << ADC_SEQ_2_SEQ8_Pos)
7469 #define ADC_SEQ_2_SEQ8_2                                                   (0x4U << ADC_SEQ_2_SEQ8_Pos)
7470 #define ADC_SEQ_2_SEQ8_3                                                   (0x8U << ADC_SEQ_2_SEQ8_Pos)
7471 
7472 /* =====================================================    COMP_1    ===================================================== */
7473 #define ADC_COMP_1_OFFSET1_Pos                                             (12UL)   /*!<ADC COMP_1: OFFSET1 (Bit 12) */
7474 #define ADC_COMP_1_OFFSET1_Msk                                             (0x7f000UL)    /*!< ADC COMP_1: OFFSET1 (Bitfield-Mask: 0x7f) */
7475 #define ADC_COMP_1_OFFSET1                                                 ADC_COMP_1_OFFSET1_Msk
7476 #define ADC_COMP_1_OFFSET1_0                                               (0x1U << ADC_COMP_1_OFFSET1_Pos)
7477 #define ADC_COMP_1_OFFSET1_1                                               (0x2U << ADC_COMP_1_OFFSET1_Pos)
7478 #define ADC_COMP_1_OFFSET1_2                                               (0x4U << ADC_COMP_1_OFFSET1_Pos)
7479 #define ADC_COMP_1_OFFSET1_3                                               (0x8U << ADC_COMP_1_OFFSET1_Pos)
7480 #define ADC_COMP_1_OFFSET1_4                                               (0x10U << ADC_COMP_1_OFFSET1_Pos)
7481 #define ADC_COMP_1_OFFSET1_5                                               (0x20U << ADC_COMP_1_OFFSET1_Pos)
7482 #define ADC_COMP_1_OFFSET1_6                                               (0x40U << ADC_COMP_1_OFFSET1_Pos)
7483 #define ADC_COMP_1_GAIN1_Pos                                               (0UL)    /*!<ADC COMP_1: GAIN1 (Bit 0) */
7484 #define ADC_COMP_1_GAIN1_Msk                                               (0xfffUL)    /*!< ADC COMP_1: GAIN1 (Bitfield-Mask: 0xfff) */
7485 #define ADC_COMP_1_GAIN1                                                   ADC_COMP_1_GAIN1_Msk
7486 #define ADC_COMP_1_GAIN1_0                                                 (0x1U << ADC_COMP_1_GAIN1_Pos)
7487 #define ADC_COMP_1_GAIN1_1                                                 (0x2U << ADC_COMP_1_GAIN1_Pos)
7488 #define ADC_COMP_1_GAIN1_2                                                 (0x4U << ADC_COMP_1_GAIN1_Pos)
7489 #define ADC_COMP_1_GAIN1_3                                                 (0x8U << ADC_COMP_1_GAIN1_Pos)
7490 #define ADC_COMP_1_GAIN1_4                                                 (0x10U << ADC_COMP_1_GAIN1_Pos)
7491 #define ADC_COMP_1_GAIN1_5                                                 (0x20U << ADC_COMP_1_GAIN1_Pos)
7492 #define ADC_COMP_1_GAIN1_6                                                 (0x40U << ADC_COMP_1_GAIN1_Pos)
7493 #define ADC_COMP_1_GAIN1_7                                                 (0x80U << ADC_COMP_1_GAIN1_Pos)
7494 #define ADC_COMP_1_GAIN1_8                                                 (0x100U << ADC_COMP_1_GAIN1_Pos)
7495 #define ADC_COMP_1_GAIN1_9                                                 (0x200U << ADC_COMP_1_GAIN1_Pos)
7496 #define ADC_COMP_1_GAIN1_10                                                (0x400U << ADC_COMP_1_GAIN1_Pos)
7497 #define ADC_COMP_1_GAIN1_11                                                (0x800U << ADC_COMP_1_GAIN1_Pos)
7498 
7499 /* =====================================================    COMP_2    ===================================================== */
7500 #define ADC_COMP_2_OFFSET2_Pos                                             (12UL)   /*!<ADC COMP_2: OFFSET2 (Bit 12) */
7501 #define ADC_COMP_2_OFFSET2_Msk                                             (0x7f000UL)    /*!< ADC COMP_2: OFFSET2 (Bitfield-Mask: 0x7f) */
7502 #define ADC_COMP_2_OFFSET2                                                 ADC_COMP_2_OFFSET2_Msk
7503 #define ADC_COMP_2_OFFSET2_0                                               (0x1U << ADC_COMP_2_OFFSET2_Pos)
7504 #define ADC_COMP_2_OFFSET2_1                                               (0x2U << ADC_COMP_2_OFFSET2_Pos)
7505 #define ADC_COMP_2_OFFSET2_2                                               (0x4U << ADC_COMP_2_OFFSET2_Pos)
7506 #define ADC_COMP_2_OFFSET2_3                                               (0x8U << ADC_COMP_2_OFFSET2_Pos)
7507 #define ADC_COMP_2_OFFSET2_4                                               (0x10U << ADC_COMP_2_OFFSET2_Pos)
7508 #define ADC_COMP_2_OFFSET2_5                                               (0x20U << ADC_COMP_2_OFFSET2_Pos)
7509 #define ADC_COMP_2_OFFSET2_6                                               (0x40U << ADC_COMP_2_OFFSET2_Pos)
7510 #define ADC_COMP_2_GAIN2_Pos                                               (0UL)    /*!<ADC COMP_2: GAIN2 (Bit 0) */
7511 #define ADC_COMP_2_GAIN2_Msk                                               (0xfffUL)    /*!< ADC COMP_2: GAIN2 (Bitfield-Mask: 0xfff) */
7512 #define ADC_COMP_2_GAIN2                                                   ADC_COMP_2_GAIN2_Msk
7513 #define ADC_COMP_2_GAIN2_0                                                 (0x1U << ADC_COMP_2_GAIN2_Pos)
7514 #define ADC_COMP_2_GAIN2_1                                                 (0x2U << ADC_COMP_2_GAIN2_Pos)
7515 #define ADC_COMP_2_GAIN2_2                                                 (0x4U << ADC_COMP_2_GAIN2_Pos)
7516 #define ADC_COMP_2_GAIN2_3                                                 (0x8U << ADC_COMP_2_GAIN2_Pos)
7517 #define ADC_COMP_2_GAIN2_4                                                 (0x10U << ADC_COMP_2_GAIN2_Pos)
7518 #define ADC_COMP_2_GAIN2_5                                                 (0x20U << ADC_COMP_2_GAIN2_Pos)
7519 #define ADC_COMP_2_GAIN2_6                                                 (0x40U << ADC_COMP_2_GAIN2_Pos)
7520 #define ADC_COMP_2_GAIN2_7                                                 (0x80U << ADC_COMP_2_GAIN2_Pos)
7521 #define ADC_COMP_2_GAIN2_8                                                 (0x100U << ADC_COMP_2_GAIN2_Pos)
7522 #define ADC_COMP_2_GAIN2_9                                                 (0x200U << ADC_COMP_2_GAIN2_Pos)
7523 #define ADC_COMP_2_GAIN2_10                                                (0x400U << ADC_COMP_2_GAIN2_Pos)
7524 #define ADC_COMP_2_GAIN2_11                                                (0x800U << ADC_COMP_2_GAIN2_Pos)
7525 
7526 /* =====================================================    COMP_3    ===================================================== */
7527 #define ADC_COMP_3_OFFSET3_Pos                                             (12UL)   /*!<ADC COMP_3: OFFSET3 (Bit 12) */
7528 #define ADC_COMP_3_OFFSET3_Msk                                             (0x7f000UL)    /*!< ADC COMP_3: OFFSET3 (Bitfield-Mask: 0x7f) */
7529 #define ADC_COMP_3_OFFSET3                                                 ADC_COMP_3_OFFSET3_Msk
7530 #define ADC_COMP_3_OFFSET3_0                                               (0x1U << ADC_COMP_3_OFFSET3_Pos)
7531 #define ADC_COMP_3_OFFSET3_1                                               (0x2U << ADC_COMP_3_OFFSET3_Pos)
7532 #define ADC_COMP_3_OFFSET3_2                                               (0x4U << ADC_COMP_3_OFFSET3_Pos)
7533 #define ADC_COMP_3_OFFSET3_3                                               (0x8U << ADC_COMP_3_OFFSET3_Pos)
7534 #define ADC_COMP_3_OFFSET3_4                                               (0x10U << ADC_COMP_3_OFFSET3_Pos)
7535 #define ADC_COMP_3_OFFSET3_5                                               (0x20U << ADC_COMP_3_OFFSET3_Pos)
7536 #define ADC_COMP_3_OFFSET3_6                                               (0x40U << ADC_COMP_3_OFFSET3_Pos)
7537 #define ADC_COMP_3_GAIN3_Pos                                               (0UL)    /*!<ADC COMP_3: GAIN3 (Bit 0) */
7538 #define ADC_COMP_3_GAIN3_Msk                                               (0xfffUL)    /*!< ADC COMP_3: GAIN3 (Bitfield-Mask: 0xfff) */
7539 #define ADC_COMP_3_GAIN3                                                   ADC_COMP_3_GAIN3_Msk
7540 #define ADC_COMP_3_GAIN3_0                                                 (0x1U << ADC_COMP_3_GAIN3_Pos)
7541 #define ADC_COMP_3_GAIN3_1                                                 (0x2U << ADC_COMP_3_GAIN3_Pos)
7542 #define ADC_COMP_3_GAIN3_2                                                 (0x4U << ADC_COMP_3_GAIN3_Pos)
7543 #define ADC_COMP_3_GAIN3_3                                                 (0x8U << ADC_COMP_3_GAIN3_Pos)
7544 #define ADC_COMP_3_GAIN3_4                                                 (0x10U << ADC_COMP_3_GAIN3_Pos)
7545 #define ADC_COMP_3_GAIN3_5                                                 (0x20U << ADC_COMP_3_GAIN3_Pos)
7546 #define ADC_COMP_3_GAIN3_6                                                 (0x40U << ADC_COMP_3_GAIN3_Pos)
7547 #define ADC_COMP_3_GAIN3_7                                                 (0x80U << ADC_COMP_3_GAIN3_Pos)
7548 #define ADC_COMP_3_GAIN3_8                                                 (0x100U << ADC_COMP_3_GAIN3_Pos)
7549 #define ADC_COMP_3_GAIN3_9                                                 (0x200U << ADC_COMP_3_GAIN3_Pos)
7550 #define ADC_COMP_3_GAIN3_10                                                (0x400U << ADC_COMP_3_GAIN3_Pos)
7551 #define ADC_COMP_3_GAIN3_11                                                (0x800U << ADC_COMP_3_GAIN3_Pos)
7552 
7553 /* =====================================================    COMP_4    ===================================================== */
7554 #define ADC_COMP_4_OFFSET4_Pos                                             (12UL)   /*!<ADC COMP_4: OFFSET4 (Bit 12) */
7555 #define ADC_COMP_4_OFFSET4_Msk                                             (0x7f000UL)    /*!< ADC COMP_4: OFFSET4 (Bitfield-Mask: 0x7f) */
7556 #define ADC_COMP_4_OFFSET4                                                 ADC_COMP_4_OFFSET4_Msk
7557 #define ADC_COMP_4_OFFSET4_0                                               (0x1U << ADC_COMP_4_OFFSET4_Pos)
7558 #define ADC_COMP_4_OFFSET4_1                                               (0x2U << ADC_COMP_4_OFFSET4_Pos)
7559 #define ADC_COMP_4_OFFSET4_2                                               (0x4U << ADC_COMP_4_OFFSET4_Pos)
7560 #define ADC_COMP_4_OFFSET4_3                                               (0x8U << ADC_COMP_4_OFFSET4_Pos)
7561 #define ADC_COMP_4_OFFSET4_4                                               (0x10U << ADC_COMP_4_OFFSET4_Pos)
7562 #define ADC_COMP_4_OFFSET4_5                                               (0x20U << ADC_COMP_4_OFFSET4_Pos)
7563 #define ADC_COMP_4_OFFSET4_6                                               (0x40U << ADC_COMP_4_OFFSET4_Pos)
7564 #define ADC_COMP_4_GAIN4_Pos                                               (0UL)    /*!<ADC COMP_4: GAIN4 (Bit 0) */
7565 #define ADC_COMP_4_GAIN4_Msk                                               (0xfffUL)    /*!< ADC COMP_4: GAIN4 (Bitfield-Mask: 0xfff) */
7566 #define ADC_COMP_4_GAIN4                                                   ADC_COMP_4_GAIN4_Msk
7567 #define ADC_COMP_4_GAIN4_0                                                 (0x1U << ADC_COMP_4_GAIN4_Pos)
7568 #define ADC_COMP_4_GAIN4_1                                                 (0x2U << ADC_COMP_4_GAIN4_Pos)
7569 #define ADC_COMP_4_GAIN4_2                                                 (0x4U << ADC_COMP_4_GAIN4_Pos)
7570 #define ADC_COMP_4_GAIN4_3                                                 (0x8U << ADC_COMP_4_GAIN4_Pos)
7571 #define ADC_COMP_4_GAIN4_4                                                 (0x10U << ADC_COMP_4_GAIN4_Pos)
7572 #define ADC_COMP_4_GAIN4_5                                                 (0x20U << ADC_COMP_4_GAIN4_Pos)
7573 #define ADC_COMP_4_GAIN4_6                                                 (0x40U << ADC_COMP_4_GAIN4_Pos)
7574 #define ADC_COMP_4_GAIN4_7                                                 (0x80U << ADC_COMP_4_GAIN4_Pos)
7575 #define ADC_COMP_4_GAIN4_8                                                 (0x100U << ADC_COMP_4_GAIN4_Pos)
7576 #define ADC_COMP_4_GAIN4_9                                                 (0x200U << ADC_COMP_4_GAIN4_Pos)
7577 #define ADC_COMP_4_GAIN4_10                                                (0x400U << ADC_COMP_4_GAIN4_Pos)
7578 #define ADC_COMP_4_GAIN4_11                                                (0x800U << ADC_COMP_4_GAIN4_Pos)
7579 
7580 /* =====================================================    COMP_SEL    ===================================================== */
7581 #define ADC_COMP_SEL_OFFSET_GAIN8_Pos                                      (16UL)   /*!<ADC COMP_SEL: OFFSET_GAIN8 (Bit 16) */
7582 #define ADC_COMP_SEL_OFFSET_GAIN8_Msk                                      (0x30000UL)    /*!< ADC COMP_SEL: OFFSET_GAIN8 (Bitfield-Mask: 0x03) */
7583 #define ADC_COMP_SEL_OFFSET_GAIN8                                          ADC_COMP_SEL_OFFSET_GAIN8_Msk
7584 #define ADC_COMP_SEL_OFFSET_GAIN8_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN8_Pos)
7585 #define ADC_COMP_SEL_OFFSET_GAIN8_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN8_Pos)
7586 #define ADC_COMP_SEL_OFFSET_GAIN7_Pos                                      (14UL)   /*!<ADC COMP_SEL: OFFSET_GAIN7 (Bit 14) */
7587 #define ADC_COMP_SEL_OFFSET_GAIN7_Msk                                      (0xc000UL)   /*!< ADC COMP_SEL: OFFSET_GAIN7 (Bitfield-Mask: 0x03) */
7588 #define ADC_COMP_SEL_OFFSET_GAIN7                                          ADC_COMP_SEL_OFFSET_GAIN7_Msk
7589 #define ADC_COMP_SEL_OFFSET_GAIN7_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN7_Pos)
7590 #define ADC_COMP_SEL_OFFSET_GAIN7_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN7_Pos)
7591 #define ADC_COMP_SEL_OFFSET_GAIN6_Pos                                      (12UL)   /*!<ADC COMP_SEL: OFFSET_GAIN6 (Bit 12) */
7592 #define ADC_COMP_SEL_OFFSET_GAIN6_Msk                                      (0x3000UL)   /*!< ADC COMP_SEL: OFFSET_GAIN6 (Bitfield-Mask: 0x03) */
7593 #define ADC_COMP_SEL_OFFSET_GAIN6                                          ADC_COMP_SEL_OFFSET_GAIN6_Msk
7594 #define ADC_COMP_SEL_OFFSET_GAIN6_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN6_Pos)
7595 #define ADC_COMP_SEL_OFFSET_GAIN6_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN6_Pos)
7596 #define ADC_COMP_SEL_OFFSET_GAIN5_Pos                                      (10UL)   /*!<ADC COMP_SEL: OFFSET_GAIN5 (Bit 10) */
7597 #define ADC_COMP_SEL_OFFSET_GAIN5_Msk                                      (0xc00UL)    /*!< ADC COMP_SEL: OFFSET_GAIN5 (Bitfield-Mask: 0x03) */
7598 #define ADC_COMP_SEL_OFFSET_GAIN5                                          ADC_COMP_SEL_OFFSET_GAIN5_Msk
7599 #define ADC_COMP_SEL_OFFSET_GAIN5_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN5_Pos)
7600 #define ADC_COMP_SEL_OFFSET_GAIN5_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN5_Pos)
7601 #define ADC_COMP_SEL_OFFSET_GAIN4_Pos                                      (8UL)    /*!<ADC COMP_SEL: OFFSET_GAIN4 (Bit 8) */
7602 #define ADC_COMP_SEL_OFFSET_GAIN4_Msk                                      (0x300UL)    /*!< ADC COMP_SEL: OFFSET_GAIN4 (Bitfield-Mask: 0x03) */
7603 #define ADC_COMP_SEL_OFFSET_GAIN4                                          ADC_COMP_SEL_OFFSET_GAIN4_Msk
7604 #define ADC_COMP_SEL_OFFSET_GAIN4_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN4_Pos)
7605 #define ADC_COMP_SEL_OFFSET_GAIN4_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN4_Pos)
7606 #define ADC_COMP_SEL_OFFSET_GAIN3_Pos                                      (6UL)    /*!<ADC COMP_SEL: OFFSET_GAIN3 (Bit 6) */
7607 #define ADC_COMP_SEL_OFFSET_GAIN3_Msk                                      (0xc0UL)   /*!< ADC COMP_SEL: OFFSET_GAIN3 (Bitfield-Mask: 0x03) */
7608 #define ADC_COMP_SEL_OFFSET_GAIN3                                          ADC_COMP_SEL_OFFSET_GAIN3_Msk
7609 #define ADC_COMP_SEL_OFFSET_GAIN3_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN3_Pos)
7610 #define ADC_COMP_SEL_OFFSET_GAIN3_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN3_Pos)
7611 #define ADC_COMP_SEL_OFFSET_GAIN2_Pos                                      (4UL)    /*!<ADC COMP_SEL: OFFSET_GAIN2 (Bit 4) */
7612 #define ADC_COMP_SEL_OFFSET_GAIN2_Msk                                      (0x30UL)   /*!< ADC COMP_SEL: OFFSET_GAIN2 (Bitfield-Mask: 0x03) */
7613 #define ADC_COMP_SEL_OFFSET_GAIN2                                          ADC_COMP_SEL_OFFSET_GAIN2_Msk
7614 #define ADC_COMP_SEL_OFFSET_GAIN2_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN2_Pos)
7615 #define ADC_COMP_SEL_OFFSET_GAIN2_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN2_Pos)
7616 #define ADC_COMP_SEL_OFFSET_GAIN1_Pos                                      (2UL)    /*!<ADC COMP_SEL: OFFSET_GAIN1 (Bit 2) */
7617 #define ADC_COMP_SEL_OFFSET_GAIN1_Msk                                      (0xcUL)    /*!< ADC COMP_SEL: OFFSET_GAIN1 (Bitfield-Mask: 0x03) */
7618 #define ADC_COMP_SEL_OFFSET_GAIN1                                          ADC_COMP_SEL_OFFSET_GAIN1_Msk
7619 #define ADC_COMP_SEL_OFFSET_GAIN1_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN1_Pos)
7620 #define ADC_COMP_SEL_OFFSET_GAIN1_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN1_Pos)
7621 #define ADC_COMP_SEL_OFFSET_GAIN0_Pos                                      (0UL)    /*!<ADC COMP_SEL: OFFSET_GAIN0 (Bit 0) */
7622 #define ADC_COMP_SEL_OFFSET_GAIN0_Msk                                      (0x3UL)    /*!< ADC COMP_SEL: OFFSET_GAIN0 (Bitfield-Mask: 0x03) */
7623 #define ADC_COMP_SEL_OFFSET_GAIN0                                          ADC_COMP_SEL_OFFSET_GAIN0_Msk
7624 #define ADC_COMP_SEL_OFFSET_GAIN0_0                                        (0x1U << ADC_COMP_SEL_OFFSET_GAIN0_Pos)
7625 #define ADC_COMP_SEL_OFFSET_GAIN0_1                                        (0x2U << ADC_COMP_SEL_OFFSET_GAIN0_Pos)
7626 
7627 /* =====================================================    WD_TH    ===================================================== */
7628 #define ADC_WD_TH_WD_HT_Pos                                                (16UL)   /*!<ADC WD_TH: WD_HT (Bit 16) */
7629 #define ADC_WD_TH_WD_HT_Msk                                                (0xfff0000UL)    /*!< ADC WD_TH: WD_HT (Bitfield-Mask: 0xfff) */
7630 #define ADC_WD_TH_WD_HT                                                    ADC_WD_TH_WD_HT_Msk
7631 #define ADC_WD_TH_WD_HT_0                                                  (0x1U << ADC_WD_TH_WD_HT_Pos)
7632 #define ADC_WD_TH_WD_HT_1                                                  (0x2U << ADC_WD_TH_WD_HT_Pos)
7633 #define ADC_WD_TH_WD_HT_2                                                  (0x4U << ADC_WD_TH_WD_HT_Pos)
7634 #define ADC_WD_TH_WD_HT_3                                                  (0x8U << ADC_WD_TH_WD_HT_Pos)
7635 #define ADC_WD_TH_WD_HT_4                                                  (0x10U << ADC_WD_TH_WD_HT_Pos)
7636 #define ADC_WD_TH_WD_HT_5                                                  (0x20U << ADC_WD_TH_WD_HT_Pos)
7637 #define ADC_WD_TH_WD_HT_6                                                  (0x40U << ADC_WD_TH_WD_HT_Pos)
7638 #define ADC_WD_TH_WD_HT_7                                                  (0x80U << ADC_WD_TH_WD_HT_Pos)
7639 #define ADC_WD_TH_WD_HT_8                                                  (0x100U << ADC_WD_TH_WD_HT_Pos)
7640 #define ADC_WD_TH_WD_HT_9                                                  (0x200U << ADC_WD_TH_WD_HT_Pos)
7641 #define ADC_WD_TH_WD_HT_10                                                 (0x400U << ADC_WD_TH_WD_HT_Pos)
7642 #define ADC_WD_TH_WD_HT_11                                                 (0x800U << ADC_WD_TH_WD_HT_Pos)
7643 #define ADC_WD_TH_WD_LT_Pos                                                (0UL)    /*!<ADC WD_TH: WD_LT (Bit 0) */
7644 #define ADC_WD_TH_WD_LT_Msk                                                (0xfffUL)    /*!< ADC WD_TH: WD_LT (Bitfield-Mask: 0xfff) */
7645 #define ADC_WD_TH_WD_LT                                                    ADC_WD_TH_WD_LT_Msk
7646 #define ADC_WD_TH_WD_LT_0                                                  (0x1U << ADC_WD_TH_WD_LT_Pos)
7647 #define ADC_WD_TH_WD_LT_1                                                  (0x2U << ADC_WD_TH_WD_LT_Pos)
7648 #define ADC_WD_TH_WD_LT_2                                                  (0x4U << ADC_WD_TH_WD_LT_Pos)
7649 #define ADC_WD_TH_WD_LT_3                                                  (0x8U << ADC_WD_TH_WD_LT_Pos)
7650 #define ADC_WD_TH_WD_LT_4                                                  (0x10U << ADC_WD_TH_WD_LT_Pos)
7651 #define ADC_WD_TH_WD_LT_5                                                  (0x20U << ADC_WD_TH_WD_LT_Pos)
7652 #define ADC_WD_TH_WD_LT_6                                                  (0x40U << ADC_WD_TH_WD_LT_Pos)
7653 #define ADC_WD_TH_WD_LT_7                                                  (0x80U << ADC_WD_TH_WD_LT_Pos)
7654 #define ADC_WD_TH_WD_LT_8                                                  (0x100U << ADC_WD_TH_WD_LT_Pos)
7655 #define ADC_WD_TH_WD_LT_9                                                  (0x200U << ADC_WD_TH_WD_LT_Pos)
7656 #define ADC_WD_TH_WD_LT_10                                                 (0x400U << ADC_WD_TH_WD_LT_Pos)
7657 #define ADC_WD_TH_WD_LT_11                                                 (0x800U << ADC_WD_TH_WD_LT_Pos)
7658 
7659 /* =====================================================    WD_CONF    ===================================================== */
7660 #define ADC_WD_CONF_AWD_CHX_Pos                                            (0UL)    /*!<ADC WD_CONF: AWD_CHX (Bit 0) */
7661 #define ADC_WD_CONF_AWD_CHX_Msk                                            (0xffffUL)   /*!< ADC WD_CONF: AWD_CHX (Bitfield-Mask: 0xffff) */
7662 #define ADC_WD_CONF_AWD_CHX                                                ADC_WD_CONF_AWD_CHX_Msk
7663 #define ADC_WD_CONF_AWD_CHX_0                                              (0x1U << ADC_WD_CONF_AWD_CHX_Pos)
7664 #define ADC_WD_CONF_AWD_CHX_1                                              (0x2U << ADC_WD_CONF_AWD_CHX_Pos)
7665 #define ADC_WD_CONF_AWD_CHX_2                                              (0x4U << ADC_WD_CONF_AWD_CHX_Pos)
7666 #define ADC_WD_CONF_AWD_CHX_3                                              (0x8U << ADC_WD_CONF_AWD_CHX_Pos)
7667 #define ADC_WD_CONF_AWD_CHX_4                                              (0x10U << ADC_WD_CONF_AWD_CHX_Pos)
7668 #define ADC_WD_CONF_AWD_CHX_5                                              (0x20U << ADC_WD_CONF_AWD_CHX_Pos)
7669 #define ADC_WD_CONF_AWD_CHX_6                                              (0x40U << ADC_WD_CONF_AWD_CHX_Pos)
7670 #define ADC_WD_CONF_AWD_CHX_7                                              (0x80U << ADC_WD_CONF_AWD_CHX_Pos)
7671 #define ADC_WD_CONF_AWD_CHX_8                                              (0x100U << ADC_WD_CONF_AWD_CHX_Pos)
7672 #define ADC_WD_CONF_AWD_CHX_9                                              (0x200U << ADC_WD_CONF_AWD_CHX_Pos)
7673 #define ADC_WD_CONF_AWD_CHX_10                                             (0x400U << ADC_WD_CONF_AWD_CHX_Pos)
7674 #define ADC_WD_CONF_AWD_CHX_11                                             (0x800U << ADC_WD_CONF_AWD_CHX_Pos)
7675 #define ADC_WD_CONF_AWD_CHX_12                                             (0x1000U << ADC_WD_CONF_AWD_CHX_Pos)
7676 #define ADC_WD_CONF_AWD_CHX_13                                             (0x2000U << ADC_WD_CONF_AWD_CHX_Pos)
7677 #define ADC_WD_CONF_AWD_CHX_14                                             (0x4000U << ADC_WD_CONF_AWD_CHX_Pos)
7678 #define ADC_WD_CONF_AWD_CHX_15                                             (0x8000U << ADC_WD_CONF_AWD_CHX_Pos)
7679 
7680 /* =====================================================    DS_DATAOUT    ===================================================== */
7681 #define ADC_DS_DATAOUT_DS_DATA_Pos                                         (0UL)    /*!<ADC DS_DATAOUT: DS_DATA (Bit 0) */
7682 #define ADC_DS_DATAOUT_DS_DATA_Msk                                         (0xffffUL)   /*!< ADC DS_DATAOUT: DS_DATA (Bitfield-Mask: 0xffff) */
7683 #define ADC_DS_DATAOUT_DS_DATA                                             ADC_DS_DATAOUT_DS_DATA_Msk
7684 #define ADC_DS_DATAOUT_DS_DATA_0                                           (0x1U << ADC_DS_DATAOUT_DS_DATA_Pos)
7685 #define ADC_DS_DATAOUT_DS_DATA_1                                           (0x2U << ADC_DS_DATAOUT_DS_DATA_Pos)
7686 #define ADC_DS_DATAOUT_DS_DATA_2                                           (0x4U << ADC_DS_DATAOUT_DS_DATA_Pos)
7687 #define ADC_DS_DATAOUT_DS_DATA_3                                           (0x8U << ADC_DS_DATAOUT_DS_DATA_Pos)
7688 #define ADC_DS_DATAOUT_DS_DATA_4                                           (0x10U << ADC_DS_DATAOUT_DS_DATA_Pos)
7689 #define ADC_DS_DATAOUT_DS_DATA_5                                           (0x20U << ADC_DS_DATAOUT_DS_DATA_Pos)
7690 #define ADC_DS_DATAOUT_DS_DATA_6                                           (0x40U << ADC_DS_DATAOUT_DS_DATA_Pos)
7691 #define ADC_DS_DATAOUT_DS_DATA_7                                           (0x80U << ADC_DS_DATAOUT_DS_DATA_Pos)
7692 #define ADC_DS_DATAOUT_DS_DATA_8                                           (0x100U << ADC_DS_DATAOUT_DS_DATA_Pos)
7693 #define ADC_DS_DATAOUT_DS_DATA_9                                           (0x200U << ADC_DS_DATAOUT_DS_DATA_Pos)
7694 #define ADC_DS_DATAOUT_DS_DATA_10                                          (0x400U << ADC_DS_DATAOUT_DS_DATA_Pos)
7695 #define ADC_DS_DATAOUT_DS_DATA_11                                          (0x800U << ADC_DS_DATAOUT_DS_DATA_Pos)
7696 #define ADC_DS_DATAOUT_DS_DATA_12                                          (0x1000U << ADC_DS_DATAOUT_DS_DATA_Pos)
7697 #define ADC_DS_DATAOUT_DS_DATA_13                                          (0x2000U << ADC_DS_DATAOUT_DS_DATA_Pos)
7698 #define ADC_DS_DATAOUT_DS_DATA_14                                          (0x4000U << ADC_DS_DATAOUT_DS_DATA_Pos)
7699 #define ADC_DS_DATAOUT_DS_DATA_15                                          (0x8000U << ADC_DS_DATAOUT_DS_DATA_Pos)
7700 
7701 /* =====================================================    DF_DATAOUT    ===================================================== */
7702 #define ADC_DF_DATAOUT_DF_DATA_Pos                                         (0UL)    /*!<ADC DF_DATAOUT: DF_DATA (Bit 0) */
7703 #define ADC_DF_DATAOUT_DF_DATA_Msk                                         (0xffffUL)   /*!< ADC DF_DATAOUT: DF_DATA (Bitfield-Mask: 0xffff) */
7704 #define ADC_DF_DATAOUT_DF_DATA                                             ADC_DF_DATAOUT_DF_DATA_Msk
7705 #define ADC_DF_DATAOUT_DF_DATA_0                                           (0x1U << ADC_DF_DATAOUT_DF_DATA_Pos)
7706 #define ADC_DF_DATAOUT_DF_DATA_1                                           (0x2U << ADC_DF_DATAOUT_DF_DATA_Pos)
7707 #define ADC_DF_DATAOUT_DF_DATA_2                                           (0x4U << ADC_DF_DATAOUT_DF_DATA_Pos)
7708 #define ADC_DF_DATAOUT_DF_DATA_3                                           (0x8U << ADC_DF_DATAOUT_DF_DATA_Pos)
7709 #define ADC_DF_DATAOUT_DF_DATA_4                                           (0x10U << ADC_DF_DATAOUT_DF_DATA_Pos)
7710 #define ADC_DF_DATAOUT_DF_DATA_5                                           (0x20U << ADC_DF_DATAOUT_DF_DATA_Pos)
7711 #define ADC_DF_DATAOUT_DF_DATA_6                                           (0x40U << ADC_DF_DATAOUT_DF_DATA_Pos)
7712 #define ADC_DF_DATAOUT_DF_DATA_7                                           (0x80U << ADC_DF_DATAOUT_DF_DATA_Pos)
7713 #define ADC_DF_DATAOUT_DF_DATA_8                                           (0x100U << ADC_DF_DATAOUT_DF_DATA_Pos)
7714 #define ADC_DF_DATAOUT_DF_DATA_9                                           (0x200U << ADC_DF_DATAOUT_DF_DATA_Pos)
7715 #define ADC_DF_DATAOUT_DF_DATA_10                                          (0x400U << ADC_DF_DATAOUT_DF_DATA_Pos)
7716 #define ADC_DF_DATAOUT_DF_DATA_11                                          (0x800U << ADC_DF_DATAOUT_DF_DATA_Pos)
7717 #define ADC_DF_DATAOUT_DF_DATA_12                                          (0x1000U << ADC_DF_DATAOUT_DF_DATA_Pos)
7718 #define ADC_DF_DATAOUT_DF_DATA_13                                          (0x2000U << ADC_DF_DATAOUT_DF_DATA_Pos)
7719 #define ADC_DF_DATAOUT_DF_DATA_14                                          (0x4000U << ADC_DF_DATAOUT_DF_DATA_Pos)
7720 #define ADC_DF_DATAOUT_DF_DATA_15                                          (0x8000U << ADC_DF_DATAOUT_DF_DATA_Pos)
7721 
7722 /* =====================================================    IRQ_STATUS    ===================================================== */
7723 #define ADC_IRQ_STATUS_DF_OVRFL_IRQ_Pos                                    (7UL)    /*!<ADC IRQ_STATUS: DF_OVRFL_IRQ (Bit 7) */
7724 #define ADC_IRQ_STATUS_DF_OVRFL_IRQ_Msk                                    (0x80UL)   /*!< ADC IRQ_STATUS: DF_OVRFL_IRQ (Bitfield-Mask: 0x01) */
7725 #define ADC_IRQ_STATUS_DF_OVRFL_IRQ                                        ADC_IRQ_STATUS_DF_OVRFL_IRQ_Msk
7726 #define ADC_IRQ_STATUS_OVR_DF_IRQ_Pos                                      (6UL)    /*!<ADC IRQ_STATUS: OVR_DF_IRQ (Bit 6) */
7727 #define ADC_IRQ_STATUS_OVR_DF_IRQ_Msk                                      (0x40UL)   /*!< ADC IRQ_STATUS: OVR_DF_IRQ (Bitfield-Mask: 0x01) */
7728 #define ADC_IRQ_STATUS_OVR_DF_IRQ                                          ADC_IRQ_STATUS_OVR_DF_IRQ_Msk
7729 #define ADC_IRQ_STATUS_OVR_DS_IRQ_Pos                                      (5UL)    /*!<ADC IRQ_STATUS: OVR_DS_IRQ (Bit 5) */
7730 #define ADC_IRQ_STATUS_OVR_DS_IRQ_Msk                                      (0x20UL)   /*!< ADC IRQ_STATUS: OVR_DS_IRQ (Bitfield-Mask: 0x01) */
7731 #define ADC_IRQ_STATUS_OVR_DS_IRQ                                          ADC_IRQ_STATUS_OVR_DS_IRQ_Msk
7732 #define ADC_IRQ_STATUS_AWD_IRQ_Pos                                         (4UL)    /*!<ADC IRQ_STATUS: AWD_IRQ (Bit 4) */
7733 #define ADC_IRQ_STATUS_AWD_IRQ_Msk                                         (0x10UL)   /*!< ADC IRQ_STATUS: AWD_IRQ (Bitfield-Mask: 0x01) */
7734 #define ADC_IRQ_STATUS_AWD_IRQ                                             ADC_IRQ_STATUS_AWD_IRQ_Msk
7735 #define ADC_IRQ_STATUS_EOS_IRQ_Pos                                         (3UL)    /*!<ADC IRQ_STATUS: EOS_IRQ (Bit 3) */
7736 #define ADC_IRQ_STATUS_EOS_IRQ_Msk                                         (0x8UL)    /*!< ADC IRQ_STATUS: EOS_IRQ (Bitfield-Mask: 0x01) */
7737 #define ADC_IRQ_STATUS_EOS_IRQ                                             ADC_IRQ_STATUS_EOS_IRQ_Msk
7738 #define ADC_IRQ_STATUS_EODF_IRQ_Pos                                        (2UL)    /*!<ADC IRQ_STATUS: EODF_IRQ (Bit 2) */
7739 #define ADC_IRQ_STATUS_EODF_IRQ_Msk                                        (0x4UL)    /*!< ADC IRQ_STATUS: EODF_IRQ (Bitfield-Mask: 0x01) */
7740 #define ADC_IRQ_STATUS_EODF_IRQ                                            ADC_IRQ_STATUS_EODF_IRQ_Msk
7741 #define ADC_IRQ_STATUS_EODS_IRQ_Pos                                        (1UL)    /*!<ADC IRQ_STATUS: EODS_IRQ (Bit 1) */
7742 #define ADC_IRQ_STATUS_EODS_IRQ_Msk                                        (0x2UL)    /*!< ADC IRQ_STATUS: EODS_IRQ (Bitfield-Mask: 0x01) */
7743 #define ADC_IRQ_STATUS_EODS_IRQ                                            ADC_IRQ_STATUS_EODS_IRQ_Msk
7744 #define ADC_IRQ_STATUS_EOC_IRQ_Pos                                         (0UL)    /*!<ADC IRQ_STATUS: EOC_IRQ (Bit 0) */
7745 #define ADC_IRQ_STATUS_EOC_IRQ_Msk                                         (0x1UL)    /*!< ADC IRQ_STATUS: EOC_IRQ (Bitfield-Mask: 0x01) */
7746 #define ADC_IRQ_STATUS_EOC_IRQ                                             ADC_IRQ_STATUS_EOC_IRQ_Msk
7747 
7748 /* =====================================================    IRQ_ENABLE    ===================================================== */
7749 #define ADC_IRQ_ENABLE_DF_OVRFL_IRQ_ENA_Pos                                (7UL)    /*!<ADC IRQ_ENABLE: DF_OVRFL_IRQ_ENA (Bit 7) */
7750 #define ADC_IRQ_ENABLE_DF_OVRFL_IRQ_ENA_Msk                                (0x80UL)   /*!< ADC IRQ_ENABLE: DF_OVRFL_IRQ_ENA (Bitfield-Mask: 0x01) */
7751 #define ADC_IRQ_ENABLE_DF_OVRFL_IRQ_ENA                                    ADC_IRQ_ENABLE_DF_OVRFL_IRQ_ENA_Msk
7752 #define ADC_IRQ_ENABLE_OVR_DF_IRQ_ENA_Pos                                  (6UL)    /*!<ADC IRQ_ENABLE: OVR_DF_IRQ_ENA (Bit 6) */
7753 #define ADC_IRQ_ENABLE_OVR_DF_IRQ_ENA_Msk                                  (0x40UL)   /*!< ADC IRQ_ENABLE: OVR_DF_IRQ_ENA (Bitfield-Mask: 0x01) */
7754 #define ADC_IRQ_ENABLE_OVR_DF_IRQ_ENA                                      ADC_IRQ_ENABLE_OVR_DF_IRQ_ENA_Msk
7755 #define ADC_IRQ_ENABLE_OVR_DS_IRQ_ENA_Pos                                  (5UL)    /*!<ADC IRQ_ENABLE: OVR_DS_IRQ_ENA (Bit 5) */
7756 #define ADC_IRQ_ENABLE_OVR_DS_IRQ_ENA_Msk                                  (0x20UL)   /*!< ADC IRQ_ENABLE: OVR_DS_IRQ_ENA (Bitfield-Mask: 0x01) */
7757 #define ADC_IRQ_ENABLE_OVR_DS_IRQ_ENA                                      ADC_IRQ_ENABLE_OVR_DS_IRQ_ENA_Msk
7758 #define ADC_IRQ_ENABLE_AWD_IRQ_ENA_Pos                                     (4UL)    /*!<ADC IRQ_ENABLE: AWD_IRQ_ENA (Bit 4) */
7759 #define ADC_IRQ_ENABLE_AWD_IRQ_ENA_Msk                                     (0x10UL)   /*!< ADC IRQ_ENABLE: AWD_IRQ_ENA (Bitfield-Mask: 0x01) */
7760 #define ADC_IRQ_ENABLE_AWD_IRQ_ENA                                         ADC_IRQ_ENABLE_AWD_IRQ_ENA_Msk
7761 #define ADC_IRQ_ENABLE_EOS_IRQ_ENA_Pos                                     (3UL)    /*!<ADC IRQ_ENABLE: EOS_IRQ_ENA (Bit 3) */
7762 #define ADC_IRQ_ENABLE_EOS_IRQ_ENA_Msk                                     (0x8UL)    /*!< ADC IRQ_ENABLE: EOS_IRQ_ENA (Bitfield-Mask: 0x01) */
7763 #define ADC_IRQ_ENABLE_EOS_IRQ_ENA                                         ADC_IRQ_ENABLE_EOS_IRQ_ENA_Msk
7764 #define ADC_IRQ_ENABLE_EODF_IRQ_ENA_Pos                                    (2UL)    /*!<ADC IRQ_ENABLE: EODF_IRQ_ENA (Bit 2) */
7765 #define ADC_IRQ_ENABLE_EODF_IRQ_ENA_Msk                                    (0x4UL)    /*!< ADC IRQ_ENABLE: EODF_IRQ_ENA (Bitfield-Mask: 0x01) */
7766 #define ADC_IRQ_ENABLE_EODF_IRQ_ENA                                        ADC_IRQ_ENABLE_EODF_IRQ_ENA_Msk
7767 #define ADC_IRQ_ENABLE_EODS_IRQ_ENA_Pos                                    (1UL)    /*!<ADC IRQ_ENABLE: EODS_IRQ_ENA (Bit 1) */
7768 #define ADC_IRQ_ENABLE_EODS_IRQ_ENA_Msk                                    (0x2UL)    /*!< ADC IRQ_ENABLE: EODS_IRQ_ENA (Bitfield-Mask: 0x01) */
7769 #define ADC_IRQ_ENABLE_EODS_IRQ_ENA                                        ADC_IRQ_ENABLE_EODS_IRQ_ENA_Msk
7770 #define ADC_IRQ_ENABLE_EOC_IRQ_ENA_Pos                                     (0UL)    /*!<ADC IRQ_ENABLE: EOC_IRQ_ENA (Bit 0) */
7771 #define ADC_IRQ_ENABLE_EOC_IRQ_ENA_Msk                                     (0x1UL)    /*!< ADC IRQ_ENABLE: EOC_IRQ_ENA (Bitfield-Mask: 0x01) */
7772 #define ADC_IRQ_ENABLE_EOC_IRQ_ENA                                         ADC_IRQ_ENABLE_EOC_IRQ_ENA_Msk
7773 
7774 /* =====================================================    TIMER_CONF    ===================================================== */
7775 #define ADC_TIMER_CONF_PRECH_DELAY_SEL_Pos                                 (16UL)   /*!<ADC TIMER_CONF: PRECH_DELAY_SEL (Bit 16) */
7776 #define ADC_TIMER_CONF_PRECH_DELAY_SEL_Msk                                 (0x10000UL)    /*!< ADC TIMER_CONF: PRECH_DELAY_SEL (Bitfield-Mask: 0x01) */
7777 #define ADC_TIMER_CONF_PRECH_DELAY_SEL                                     ADC_TIMER_CONF_PRECH_DELAY_SEL_Msk
7778 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos                               (8UL)    /*!<ADC TIMER_CONF: VBIAS_PRECH_DELAY (Bit 8) */
7779 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Msk                               (0xff00UL)   /*!< ADC TIMER_CONF: VBIAS_PRECH_DELAY (Bitfield-Mask: 0xff) */
7780 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY                                   ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Msk
7781 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_0                                 (0x1U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7782 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_1                                 (0x2U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7783 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_2                                 (0x4U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7784 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_3                                 (0x8U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7785 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_4                                 (0x10U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7786 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_5                                 (0x20U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7787 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_6                                 (0x40U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7788 #define ADC_TIMER_CONF_VBIAS_PRECH_DELAY_7                                 (0x80U << ADC_TIMER_CONF_VBIAS_PRECH_DELAY_Pos)
7789 #define ADC_TIMER_CONF_ADC_LDO_DELAY_Pos                                   (0UL)    /*!<ADC TIMER_CONF: ADC_LDO_DELAY (Bit 0) */
7790 #define ADC_TIMER_CONF_ADC_LDO_DELAY_Msk                                   (0xffUL)   /*!< ADC TIMER_CONF: ADC_LDO_DELAY (Bitfield-Mask: 0xff) */
7791 #define ADC_TIMER_CONF_ADC_LDO_DELAY                                       ADC_TIMER_CONF_ADC_LDO_DELAY_Msk
7792 #define ADC_TIMER_CONF_ADC_LDO_DELAY_0                                     (0x1U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7793 #define ADC_TIMER_CONF_ADC_LDO_DELAY_1                                     (0x2U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7794 #define ADC_TIMER_CONF_ADC_LDO_DELAY_2                                     (0x4U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7795 #define ADC_TIMER_CONF_ADC_LDO_DELAY_3                                     (0x8U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7796 #define ADC_TIMER_CONF_ADC_LDO_DELAY_4                                     (0x10U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7797 #define ADC_TIMER_CONF_ADC_LDO_DELAY_5                                     (0x20U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7798 #define ADC_TIMER_CONF_ADC_LDO_DELAY_6                                     (0x40U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7799 #define ADC_TIMER_CONF_ADC_LDO_DELAY_7                                     (0x80U << ADC_TIMER_CONF_ADC_LDO_DELAY_Pos)
7800 
7801 
7802 /* =========================================================================================================================== */
7803 /* ================                                     BLUE                                                  ================ */
7804 /* =========================================================================================================================== */
7805 
7806 
7807 /* ===============================================   CONTROLLERVERNUMREG   =============================================== */
7808 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos                             (0UL)   /*!< BLUE CONTROLLERVERNUMREG: SUBVERNUM (Bit 0) */
7809 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Msk                             (0x000000ffUL)  /*!< BLUE CONTROLLERVERNUMREG: SUBVERNUM (Bitfield-Mask: 0xff) */
7810 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM                                 BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Msk
7811 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_0                               (0x01 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000001 */
7812 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_1                               (0x02 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000002 */
7813 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_2                               (0x04 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000004 */
7814 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_3                               (0x08 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000008 */
7815 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_4                               (0x10 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000010 */
7816 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_5                               (0x20 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000020 */
7817 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_6                               (0x40 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000040 */
7818 #define BLUE_CONTROLLERVERNUMREG_SUBVERNUM_7                               (0x80 << BLUE_CONTROLLERVERNUMREG_SUBVERNUM_Pos)   /*!<0x00000080 */
7819 #define BLUE_CONTROLLERVERNUMREG_VERNUM_Pos                                (8UL)   /*!< BLUE CONTROLLERVERNUMREG: VERNUM (Bit 8) */
7820 #define BLUE_CONTROLLERVERNUMREG_VERNUM_Msk                                (0x0000ff00UL)  /*!< BLUE CONTROLLERVERNUMREG: VERNUM (Bitfield-Mask: 0xff) */
7821 #define BLUE_CONTROLLERVERNUMREG_VERNUM                                    BLUE_CONTROLLERVERNUMREG_VERNUM_Msk
7822 #define BLUE_CONTROLLERVERNUMREG_VERNUM_0                                  (0x01 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00000100 */
7823 #define BLUE_CONTROLLERVERNUMREG_VERNUM_1                                  (0x02 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00000200 */
7824 #define BLUE_CONTROLLERVERNUMREG_VERNUM_2                                  (0x04 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00000400 */
7825 #define BLUE_CONTROLLERVERNUMREG_VERNUM_3                                  (0x08 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00000800 */
7826 #define BLUE_CONTROLLERVERNUMREG_VERNUM_4                                  (0x10 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00001000 */
7827 #define BLUE_CONTROLLERVERNUMREG_VERNUM_5                                  (0x20 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00002000 */
7828 #define BLUE_CONTROLLERVERNUMREG_VERNUM_6                                  (0x40 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00004000 */
7829 #define BLUE_CONTROLLERVERNUMREG_VERNUM_7                                  (0x80 << BLUE_CONTROLLERVERNUMREG_VERNUM_Pos)   /*!<0x00008000 */
7830 #define BLUE_CONTROLLERVERNUMREG_TYP_Pos                                   (16UL)   /*!< BLUE CONTROLLERVERNUMREG: TYP (Bit 16) */
7831 #define BLUE_CONTROLLERVERNUMREG_TYP_Msk                                   (0x00ff0000UL)  /*!< BLUE CONTROLLERVERNUMREG: TYP (Bitfield-Mask: 0xff) */
7832 #define BLUE_CONTROLLERVERNUMREG_TYP                                       BLUE_CONTROLLERVERNUMREG_TYP_Msk
7833 #define BLUE_CONTROLLERVERNUMREG_TYP_0                                     (0x01 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00010000 */
7834 #define BLUE_CONTROLLERVERNUMREG_TYP_1                                     (0x02 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00020000 */
7835 #define BLUE_CONTROLLERVERNUMREG_TYP_2                                     (0x04 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00040000 */
7836 #define BLUE_CONTROLLERVERNUMREG_TYP_3                                     (0x08 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00080000 */
7837 #define BLUE_CONTROLLERVERNUMREG_TYP_4                                     (0x10 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00100000 */
7838 #define BLUE_CONTROLLERVERNUMREG_TYP_5                                     (0x20 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00200000 */
7839 #define BLUE_CONTROLLERVERNUMREG_TYP_6                                     (0x40 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00400000 */
7840 #define BLUE_CONTROLLERVERNUMREG_TYP_7                                     (0x80 << BLUE_CONTROLLERVERNUMREG_TYP_Pos)   /*!<0x00800000 */
7841 
7842 /* ===============================================   INTERRUPT1REG   =============================================== */
7843 
7844 #define BLUE_INTERRUPT1REG_ADDPOINTERROR_Pos                               (4UL)   /*!< BLUE INTERRUPT1REG: ADDPOINTERROR (Bit 4) */
7845 #define BLUE_INTERRUPT1REG_ADDPOINTERROR_Msk                               (0x00000010UL)  /*!< BLUE INTERRUPT1REG: ADDPOINTERROR (Bitfield-Mask: 0x1) */
7846 #define BLUE_INTERRUPT1REG_ADDPOINTERROR                                   BLUE_INTERRUPT1REG_ADDPOINTERROR_Msk
7847 #define BLUE_INTERRUPT1REG_RXOVERFLOWERROR_Pos                             (5UL)   /*!< BLUE INTERRUPT1REG: RXOVERFLOWERROR (Bit 5) */
7848 #define BLUE_INTERRUPT1REG_RXOVERFLOWERROR_Msk                             (0x00000020UL)  /*!< BLUE INTERRUPT1REG: RXOVERFLOWERROR (Bitfield-Mask: 0x1) */
7849 #define BLUE_INTERRUPT1REG_RXOVERFLOWERROR                                 BLUE_INTERRUPT1REG_RXOVERFLOWERROR_Msk
7850 #define BLUE_INTERRUPT1REG_SEQDONE_Pos                                     (7UL)   /*!< BLUE INTERRUPT1REG: SEQDONE (Bit 7) */
7851 #define BLUE_INTERRUPT1REG_SEQDONE_Msk                                     (0x00000080UL)  /*!< BLUE INTERRUPT1REG: SEQDONE (Bitfield-Mask: 0x1) */
7852 #define BLUE_INTERRUPT1REG_SEQDONE                                         BLUE_INTERRUPT1REG_SEQDONE_Msk
7853 #define BLUE_INTERRUPT1REG_TXERROR_0_Pos                                   (8UL)   /*!< BLUE INTERRUPT1REG: TXERROR_0 (Bit 8) */
7854 #define BLUE_INTERRUPT1REG_TXERROR_0_Msk                                   (0x00000100UL)  /*!< BLUE INTERRUPT1REG: TXERROR_0 (Bitfield-Mask: 0x1) */
7855 #define BLUE_INTERRUPT1REG_TXERROR_0                                       BLUE_INTERRUPT1REG_TXERROR_0_Msk
7856 #define BLUE_INTERRUPT1REG_TXERROR_1_Pos                                   (9UL)   /*!< BLUE INTERRUPT1REG: TXERROR_1 (Bit 9) */
7857 #define BLUE_INTERRUPT1REG_TXERROR_1_Msk                                   (0x00000200UL)  /*!< BLUE INTERRUPT1REG: TXERROR_1 (Bitfield-Mask: 0x1) */
7858 #define BLUE_INTERRUPT1REG_TXERROR_1                                       BLUE_INTERRUPT1REG_TXERROR_1_Msk
7859 #define BLUE_INTERRUPT1REG_TXERROR_2_Pos                                   (10UL)   /*!< BLUE INTERRUPT1REG: TXERROR_2 (Bit 10) */
7860 #define BLUE_INTERRUPT1REG_TXERROR_2_Msk                                   (0x00000400UL)  /*!< BLUE INTERRUPT1REG: TXERROR_2 (Bitfield-Mask: 0x1) */
7861 #define BLUE_INTERRUPT1REG_TXERROR_2                                       BLUE_INTERRUPT1REG_TXERROR_2_Msk
7862 #define BLUE_INTERRUPT1REG_TXERROR_3_Pos                                   (11UL)   /*!< BLUE INTERRUPT1REG: TXERROR_3 (Bit 11) */
7863 #define BLUE_INTERRUPT1REG_TXERROR_3_Msk                                   (0x00000800UL)  /*!< BLUE INTERRUPT1REG: TXERROR_3 (Bitfield-Mask: 0x1) */
7864 #define BLUE_INTERRUPT1REG_TXERROR_3                                       BLUE_INTERRUPT1REG_TXERROR_3_Msk
7865 #define BLUE_INTERRUPT1REG_TXERROR_4_Pos                                   (12UL)   /*!< BLUE INTERRUPT1REG: TXERROR_4 (Bit 12) */
7866 #define BLUE_INTERRUPT1REG_TXERROR_4_Msk                                   (0x00001000UL)  /*!< BLUE INTERRUPT1REG: TXERROR_4 (Bitfield-Mask: 0x1) */
7867 #define BLUE_INTERRUPT1REG_TXERROR_4                                       BLUE_INTERRUPT1REG_TXERROR_4_Msk
7868 #define BLUE_INTERRUPT1REG_ENCERROR_Pos                                    (13UL)   /*!< BLUE INTERRUPT1REG: ENCERROR (Bit 13) */
7869 #define BLUE_INTERRUPT1REG_ENCERROR_Msk                                    (0x00002000UL)  /*!< BLUE INTERRUPT1REG: ENCERROR (Bitfield-Mask: 0x1) */
7870 #define BLUE_INTERRUPT1REG_ENCERROR                                        BLUE_INTERRUPT1REG_ENCERROR_Msk
7871 #define BLUE_INTERRUPT1REG_ALLTABLEREADYERROR_Pos                          (14UL)   /*!< BLUE INTERRUPT1REG: ALLTABLEREADYERROR (Bit 14) */
7872 #define BLUE_INTERRUPT1REG_ALLTABLEREADYERROR_Msk                          (0x00004000UL)  /*!< BLUE INTERRUPT1REG: ALLTABLEREADYERROR (Bitfield-Mask: 0x1) */
7873 #define BLUE_INTERRUPT1REG_ALLTABLEREADYERROR                              BLUE_INTERRUPT1REG_ALLTABLEREADYERROR_Msk
7874 #define BLUE_INTERRUPT1REG_TXDATAREADYERROR_Pos                            (15UL)   /*!< BLUE INTERRUPT1REG: TXDATAREADYERROR (Bit 15) */
7875 #define BLUE_INTERRUPT1REG_TXDATAREADYERROR_Msk                            (0x00008000UL)  /*!< BLUE INTERRUPT1REG: TXDATAREADYERROR (Bitfield-Mask: 0x1) */
7876 #define BLUE_INTERRUPT1REG_TXDATAREADYERROR                                BLUE_INTERRUPT1REG_TXDATAREADYERROR_Msk
7877 #define BLUE_INTERRUPT1REG_NOACTIVELERROR_Pos                              (16UL)   /*!< BLUE INTERRUPT1REG: NOACTIVELERROR (Bit 16) */
7878 #define BLUE_INTERRUPT1REG_NOACTIVELERROR_Msk                              (0x00010000UL)  /*!< BLUE INTERRUPT1REG: NOACTIVELERROR (Bitfield-Mask: 0x1) */
7879 #define BLUE_INTERRUPT1REG_NOACTIVELERROR                                  BLUE_INTERRUPT1REG_NOACTIVELERROR_Msk
7880 #define BLUE_INTERRUPT1REG_INITDELAYERROR_Pos                              (17UL)   /*!< BLUE INTERRUPT1REG: INITDELAYERROR (Bit 17) */
7881 #define BLUE_INTERRUPT1REG_INITDELAYERROR_Msk                              (0x00020000UL)  /*!< BLUE INTERRUPT1REG: INITDELAYERROR (Bitfield-Mask: 0x1) */
7882 #define BLUE_INTERRUPT1REG_INITDELAYERROR                                  BLUE_INTERRUPT1REG_INITDELAYERROR_Msk
7883 #define BLUE_INTERRUPT1REG_RCVLENGTHERROR_Pos                              (18UL)   /*!< BLUE INTERRUPT1REG: RCVLENGTHERROR (Bit 18) */
7884 #define BLUE_INTERRUPT1REG_RCVLENGTHERROR_Msk                              (0x00040000UL)  /*!< BLUE INTERRUPT1REG: RCVLENGTHERROR (Bitfield-Mask: 0x1) */
7885 #define BLUE_INTERRUPT1REG_RCVLENGTHERROR                                  BLUE_INTERRUPT1REG_RCVLENGTHERROR_Msk
7886 #define BLUE_INTERRUPT1REG_SEMATIMEOUTERROR_Pos                            (19UL)   /*!< BLUE INTERRUPT1REG: SEMATIMEOUTERROR (Bit 19) */
7887 #define BLUE_INTERRUPT1REG_SEMATIMEOUTERROR_Msk                            (0x00080000UL)  /*!< BLUE INTERRUPT1REG: SEMATIMEOUTERROR (Bitfield-Mask: 0x1) */
7888 #define BLUE_INTERRUPT1REG_SEMATIMEOUTERROR                                BLUE_INTERRUPT1REG_SEMATIMEOUTERROR_Msk
7889 #define BLUE_INTERRUPT1REG_SEMAWASPREEMPT_Pos                              (20UL)   /*!< BLUE INTERRUPT1REG: SEMAWASPREEMPT (Bit 20) */
7890 #define BLUE_INTERRUPT1REG_SEMAWASPREEMPT_Msk                              (0x00100000UL)  /*!< BLUE INTERRUPT1REG: SEMAWASPREEMPT (Bitfield-Mask: 0x1) */
7891 #define BLUE_INTERRUPT1REG_SEMAWASPREEMPT                                  BLUE_INTERRUPT1REG_SEMAWASPREEMPT_Msk
7892 #define BLUE_INTERRUPT1REG_TXRXSKIP_Pos                                    (21UL)   /*!< BLUE INTERRUPT1REG: TXRXSKIP (Bit 21) */
7893 #define BLUE_INTERRUPT1REG_TXRXSKIP_Msk                                    (0x00200000UL)  /*!< BLUE INTERRUPT1REG: TXRXSKIP (Bitfield-Mask: 0x1) */
7894 #define BLUE_INTERRUPT1REG_TXRXSKIP                                        BLUE_INTERRUPT1REG_TXRXSKIP_Msk
7895 #define BLUE_INTERRUPT1REG_ACTIVE2ERROR_Pos                                (22UL)   /*!< BLUE INTERRUPT1REG: ACTIVE2ERROR (Bit 22) */
7896 #define BLUE_INTERRUPT1REG_ACTIVE2ERROR_Msk                                (0x00400000UL)  /*!< BLUE INTERRUPT1REG: ACTIVE2ERROR (Bitfield-Mask: 0x1) */
7897 #define BLUE_INTERRUPT1REG_ACTIVE2ERROR                                    BLUE_INTERRUPT1REG_ACTIVE2ERROR_Msk
7898 #define BLUE_INTERRUPT1REG_CONFIGERROR_Pos                                 (23UL)   /*!< BLUE INTERRUPT1REG: CONFIGERROR (Bit 23) */
7899 #define BLUE_INTERRUPT1REG_CONFIGERROR_Msk                                 (0x00800000UL)  /*!< BLUE INTERRUPT1REG: CONFIGERROR (Bitfield-Mask: 0x1) */
7900 #define BLUE_INTERRUPT1REG_CONFIGERROR                                     BLUE_INTERRUPT1REG_CONFIGERROR_Msk
7901 #define BLUE_INTERRUPT1REG_TXOK_Pos                                        (24UL)   /*!< BLUE INTERRUPT1REG: TXOK (Bit 24) */
7902 #define BLUE_INTERRUPT1REG_TXOK_Msk                                        (0x01000000UL)  /*!< BLUE INTERRUPT1REG: TXOK (Bitfield-Mask: 0x1) */
7903 #define BLUE_INTERRUPT1REG_TXOK                                            BLUE_INTERRUPT1REG_TXOK_Msk
7904 #define BLUE_INTERRUPT1REG_DONE_Pos                                        (25UL)   /*!< BLUE INTERRUPT1REG: DONE (Bit 25) */
7905 #define BLUE_INTERRUPT1REG_DONE_Msk                                        (0x02000000UL)  /*!< BLUE INTERRUPT1REG: DONE (Bitfield-Mask: 0x1) */
7906 #define BLUE_INTERRUPT1REG_DONE                                            BLUE_INTERRUPT1REG_DONE_Msk
7907 #define BLUE_INTERRUPT1REG_RCVTIMEOUT_Pos                                  (26UL)   /*!< BLUE INTERRUPT1REG: RCVTIMEOUT (Bit 26) */
7908 #define BLUE_INTERRUPT1REG_RCVTIMEOUT_Msk                                  (0x04000000UL)  /*!< BLUE INTERRUPT1REG: RCVTIMEOUT (Bitfield-Mask: 0x1) */
7909 #define BLUE_INTERRUPT1REG_RCVTIMEOUT                                      BLUE_INTERRUPT1REG_RCVTIMEOUT_Msk
7910 #define BLUE_INTERRUPT1REG_RCVNOMD_Pos                                     (27UL)   /*!< BLUE INTERRUPT1REG: RCVNOMD (Bit 27) */
7911 #define BLUE_INTERRUPT1REG_RCVNOMD_Msk                                     (0x08000000UL)  /*!< BLUE INTERRUPT1REG: RCVNOMD (Bitfield-Mask: 0x1) */
7912 #define BLUE_INTERRUPT1REG_RCVNOMD                                         BLUE_INTERRUPT1REG_RCVNOMD_Msk
7913 #define BLUE_INTERRUPT1REG_RCVCMD_Pos                                      (28UL)   /*!< BLUE INTERRUPT1REG: RCVCMD (Bit 28) */
7914 #define BLUE_INTERRUPT1REG_RCVCMD_Msk                                      (0x10000000UL)  /*!< BLUE INTERRUPT1REG: RCVCMD (Bitfield-Mask: 0x1) */
7915 #define BLUE_INTERRUPT1REG_RCVCMD                                          BLUE_INTERRUPT1REG_RCVCMD_Msk
7916 #define BLUE_INTERRUPT1REG_TIMECAPTURETRIG_Pos                             (29UL)   /*!< BLUE INTERRUPT1REG: TIMECAPTURETRIG (Bit 29) */
7917 #define BLUE_INTERRUPT1REG_TIMECAPTURETRIG_Msk                             (0x20000000UL)  /*!< BLUE INTERRUPT1REG: TIMECAPTURETRIG (Bitfield-Mask: 0x1) */
7918 #define BLUE_INTERRUPT1REG_TIMECAPTURETRIG                                 BLUE_INTERRUPT1REG_TIMECAPTURETRIG_Msk
7919 #define BLUE_INTERRUPT1REG_RCVCRCERR_Pos                                   (30UL)   /*!< BLUE INTERRUPT1REG: RCVCRCERR (Bit 30) */
7920 #define BLUE_INTERRUPT1REG_RCVCRCERR_Msk                                   (0x40000000UL)  /*!< BLUE INTERRUPT1REG: RCVCRCERR (Bitfield-Mask: 0x1) */
7921 #define BLUE_INTERRUPT1REG_RCVCRCERR                                       BLUE_INTERRUPT1REG_RCVCRCERR_Msk
7922 #define BLUE_INTERRUPT1REG_RCVOK_Pos                                       (31UL)   /*!< BLUE INTERRUPT1REG: RCVOK (Bit 31) */
7923 #define BLUE_INTERRUPT1REG_RCVOK_Msk                                       (0x80000000UL)  /*!< BLUE INTERRUPT1REG: RCVOK (Bitfield-Mask: 0x1) */
7924 #define BLUE_INTERRUPT1REG_RCVOK                                           BLUE_INTERRUPT1REG_RCVOK_Msk
7925 #define BLUE_INTERRUPT1REG_ALL_Pos                                         (0UL)
7926 //#define BLUE_INTERRUPT1REG_ALL_Msk                                         (0xffffffffUL)
7927 #define BLUE_INTERRUPT1REG_ALL_Msk                                         (BLUE_INTERRUPT1REG_ADDPOINTERROR |\
7928                                                                             BLUE_INTERRUPT1REG_RXOVERFLOWERROR |\
7929                                                                             BLUE_INTERRUPT1REG_SEQDONE |\
7930                                                                             BLUE_INTERRUPT1REG_TXERROR_0 |\
7931                                                                             BLUE_INTERRUPT1REG_TXERROR_1 |\
7932                                                                             BLUE_INTERRUPT1REG_TXERROR_2 |\
7933                                                                             BLUE_INTERRUPT1REG_TXERROR_3 |\
7934                                                                             BLUE_INTERRUPT1REG_TXERROR_4 |\
7935                                                                             BLUE_INTERRUPT1REG_ENCERROR |\
7936                                                                             BLUE_INTERRUPT1REG_ALLTABLEREADYERROR |\
7937                                                                             BLUE_INTERRUPT1REG_TXDATAREADYERROR |\
7938                                                                             BLUE_INTERRUPT1REG_NOACTIVELERROR |\
7939                                                                             BLUE_INTERRUPT1REG_INITDELAYERROR |\
7940                                                                             BLUE_INTERRUPT1REG_RCVLENGTHERROR |\
7941                                                                             BLUE_INTERRUPT1REG_SEMATIMEOUTERROR |\
7942                                                                             BLUE_INTERRUPT1REG_SEMAWASPREEMPT |\
7943                                                                             BLUE_INTERRUPT1REG_TXRXSKIP |\
7944                                                                             BLUE_INTERRUPT1REG_ACTIVE2ERROR |\
7945                                                                             BLUE_INTERRUPT1REG_CONFIGERROR |\
7946                                                                             BLUE_INTERRUPT1REG_TXOK |\
7947                                                                             BLUE_INTERRUPT1REG_DONE |\
7948                                                                             BLUE_INTERRUPT1REG_RCVTIMEOUT |\
7949                                                                             BLUE_INTERRUPT1REG_RCVNOMD |\
7950                                                                             BLUE_INTERRUPT1REG_RCVCMD |\
7951                                                                             BLUE_INTERRUPT1REG_TIMECAPTURETRIG | BLUE_INTERRUPT1REG_RCVCRCERR | BLUE_INTERRUPT1REG_RCVOK )
7952 #define BLUE_INTERRUPT1REG_ALL                                             BLUE_INTERRUPT1REG_ALL_Msk
7953 
7954 /* ===============================================   INTERRUPT2REG   =============================================== */
7955 #define BLUE_INTERRUPT2REG_AESMANENCINT_Pos                                (0UL)   /*!< BLUE INTERRUPT2REG: AESMANENCINT (Bit 0) */
7956 #define BLUE_INTERRUPT2REG_AESMANENCINT_Msk                                (0x00000001UL)  /*!< BLUE INTERRUPT2REG: AESMANENCINT (Bitfield-Mask: 0x1) */
7957 #define BLUE_INTERRUPT2REG_AESMANENCINT                                    BLUE_INTERRUPT2REG_AESMANENCINT_Msk
7958 #define BLUE_INTERRUPT2REG_AESLEPRIVINT_Pos                                (1UL)   /*!< BLUE INTERRUPT2REG: AESLEPRIVINT (Bit 1) */
7959 #define BLUE_INTERRUPT2REG_AESLEPRIVINT_Msk                                (0x00000002UL)  /*!< BLUE INTERRUPT2REG: AESLEPRIVINT (Bitfield-Mask: 0x1) */
7960 #define BLUE_INTERRUPT2REG_AESLEPRIVINT                                    BLUE_INTERRUPT2REG_AESLEPRIVINT_Msk
7961 
7962 /* ===============================================   TIMEOUTDESTREG   =============================================== */
7963 #define BLUE_TIMEOUTDESTREG_DESTINATION_Pos                                (0UL)   /*!< BLUE TIMEOUTDESTREG: DESTINATION (Bit 0) */
7964 #define BLUE_TIMEOUTDESTREG_DESTINATION_Msk                                (0x00000003UL)  /*!< BLUE TIMEOUTDESTREG: DESTINATION (Bitfield-Mask: 0x3) */
7965 #define BLUE_TIMEOUTDESTREG_DESTINATION                                    BLUE_TIMEOUTDESTREG_DESTINATION_Msk
7966 #define BLUE_TIMEOUTDESTREG_DESTINATION_0                                  (0x1 << BLUE_TIMEOUTDESTREG_DESTINATION_Pos)   /*!<0x00000001 */
7967 #define BLUE_TIMEOUTDESTREG_DESTINATION_1                                  (0x2 << BLUE_TIMEOUTDESTREG_DESTINATION_Pos)   /*!<0x00000002 */
7968 
7969 /* ===============================================   TIMEOUTREG   =============================================== */
7970 #define BLUE_TIMEOUTREG_TIMEOUT_Pos                                        (0UL)   /*!< BLUE TIMEOUTREG: TIMEOUT (Bit 0) */
7971 #define BLUE_TIMEOUTREG_TIMEOUT_Msk                                        (0xffffffffUL)  /*!< BLUE TIMEOUTREG: TIMEOUT (Bitfield-Mask: 0xffffffffL) */
7972 #define BLUE_TIMEOUTREG_TIMEOUT                                            BLUE_TIMEOUTREG_TIMEOUT_Msk
7973 #define BLUE_TIMEOUTREG_TIMEOUT_0                                          (0x00000001 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000001 */
7974 #define BLUE_TIMEOUTREG_TIMEOUT_1                                          (0x00000002 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000002 */
7975 #define BLUE_TIMEOUTREG_TIMEOUT_2                                          (0x00000004 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000004 */
7976 #define BLUE_TIMEOUTREG_TIMEOUT_3                                          (0x00000008 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000008 */
7977 #define BLUE_TIMEOUTREG_TIMEOUT_4                                          (0x00000010 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000010 */
7978 #define BLUE_TIMEOUTREG_TIMEOUT_5                                          (0x00000020 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000020 */
7979 #define BLUE_TIMEOUTREG_TIMEOUT_6                                          (0x00000040 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000040 */
7980 #define BLUE_TIMEOUTREG_TIMEOUT_7                                          (0x00000080 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000080 */
7981 #define BLUE_TIMEOUTREG_TIMEOUT_8                                          (0x00000100 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000100 */
7982 #define BLUE_TIMEOUTREG_TIMEOUT_9                                          (0x00000200 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000200 */
7983 #define BLUE_TIMEOUTREG_TIMEOUT_10                                         (0x00000400 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000400 */
7984 #define BLUE_TIMEOUTREG_TIMEOUT_11                                         (0x00000800 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00000800 */
7985 #define BLUE_TIMEOUTREG_TIMEOUT_12                                         (0x00001000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00001000 */
7986 #define BLUE_TIMEOUTREG_TIMEOUT_13                                         (0x00002000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00002000 */
7987 #define BLUE_TIMEOUTREG_TIMEOUT_14                                         (0x00004000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00004000 */
7988 #define BLUE_TIMEOUTREG_TIMEOUT_15                                         (0x00008000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00008000 */
7989 #define BLUE_TIMEOUTREG_TIMEOUT_16                                         (0x00010000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00010000 */
7990 #define BLUE_TIMEOUTREG_TIMEOUT_17                                         (0x00020000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00020000 */
7991 #define BLUE_TIMEOUTREG_TIMEOUT_18                                         (0x00040000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00040000 */
7992 #define BLUE_TIMEOUTREG_TIMEOUT_19                                         (0x00080000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00080000 */
7993 #define BLUE_TIMEOUTREG_TIMEOUT_20                                         (0x00100000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00100000 */
7994 #define BLUE_TIMEOUTREG_TIMEOUT_21                                         (0x00200000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00200000 */
7995 #define BLUE_TIMEOUTREG_TIMEOUT_22                                         (0x00400000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00400000 */
7996 #define BLUE_TIMEOUTREG_TIMEOUT_23                                         (0x00800000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x00800000 */
7997 #define BLUE_TIMEOUTREG_TIMEOUT_24                                         (0x01000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x01000000 */
7998 #define BLUE_TIMEOUTREG_TIMEOUT_25                                         (0x02000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x02000000 */
7999 #define BLUE_TIMEOUTREG_TIMEOUT_26                                         (0x04000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x04000000 */
8000 #define BLUE_TIMEOUTREG_TIMEOUT_27                                         (0x08000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x08000000 */
8001 #define BLUE_TIMEOUTREG_TIMEOUT_28                                         (0x10000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x10000000 */
8002 #define BLUE_TIMEOUTREG_TIMEOUT_29                                         (0x20000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x20000000 */
8003 #define BLUE_TIMEOUTREG_TIMEOUT_30                                         (0x40000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x40000000 */
8004 #define BLUE_TIMEOUTREG_TIMEOUT_31                                         (0x80000000 << BLUE_TIMEOUTREG_TIMEOUT_Pos)   /*!<0x80000000 */
8005 
8006 /* ===============================================   TIMERCAPTUREREG   =============================================== */
8007 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos                              (0UL)   /*!< BLUE TIMERCAPTUREREG: TIMERCAPTURE (Bit 0) */
8008 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Msk                              (0xffffffffUL)  /*!< BLUE TIMERCAPTUREREG: TIMERCAPTURE (Bitfield-Mask: 0xffffffffL) */
8009 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE                                  BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Msk
8010 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_0                                (0x00000001 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000001 */
8011 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_1                                (0x00000002 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000002 */
8012 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_2                                (0x00000004 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000004 */
8013 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_3                                (0x00000008 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000008 */
8014 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_4                                (0x00000010 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000010 */
8015 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_5                                (0x00000020 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000020 */
8016 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_6                                (0x00000040 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000040 */
8017 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_7                                (0x00000080 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000080 */
8018 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_8                                (0x00000100 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000100 */
8019 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_9                                (0x00000200 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000200 */
8020 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_10                               (0x00000400 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000400 */
8021 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_11                               (0x00000800 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00000800 */
8022 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_12                               (0x00001000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00001000 */
8023 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_13                               (0x00002000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00002000 */
8024 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_14                               (0x00004000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00004000 */
8025 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_15                               (0x00008000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00008000 */
8026 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_16                               (0x00010000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00010000 */
8027 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_17                               (0x00020000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00020000 */
8028 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_18                               (0x00040000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00040000 */
8029 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_19                               (0x00080000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00080000 */
8030 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_20                               (0x00100000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00100000 */
8031 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_21                               (0x00200000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00200000 */
8032 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_22                               (0x00400000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00400000 */
8033 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_23                               (0x00800000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x00800000 */
8034 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_24                               (0x01000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x01000000 */
8035 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_25                               (0x02000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x02000000 */
8036 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_26                               (0x04000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x04000000 */
8037 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_27                               (0x08000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x08000000 */
8038 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_28                               (0x10000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x10000000 */
8039 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_29                               (0x20000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x20000000 */
8040 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_30                               (0x40000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x40000000 */
8041 #define BLUE_TIMERCAPTUREREG_TIMERCAPTURE_31                               (0x80000000 << BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos)   /*!<0x80000000 */
8042 
8043 /* ===============================================   CMDREG   =============================================== */
8044 #define BLUE_CMDREG_TXRXSKIP_Pos                                           (0UL)   /*!< BLUE CMDREG: TXRXSKIP (Bit 0) */
8045 #define BLUE_CMDREG_TXRXSKIP_Msk                                           (0x00000001UL)  /*!< BLUE CMDREG: TXRXSKIP (Bitfield-Mask: 0x1) */
8046 #define BLUE_CMDREG_TXRXSKIP                                               BLUE_CMDREG_TXRXSKIP_Msk
8047 #define BLUE_CMDREG_LOCKAHBWRITEBACKEN_Pos                                 (1UL)   /*!< BLUE CMDREG: LOCKAHBWRITEBACKEN (Bit 1) */
8048 #define BLUE_CMDREG_LOCKAHBWRITEBACKEN_Msk                                 (0x00000002UL)  /*!< BLUE CMDREG: LOCKAHBWRITEBACKEN (Bitfield-Mask: 0x1) */
8049 #define BLUE_CMDREG_LOCKAHBWRITEBACKEN                                     BLUE_CMDREG_LOCKAHBWRITEBACKEN_Msk
8050 #define BLUE_CMDREG_LOCKAHBFIRSTINITEN_Pos                                 (2UL)   /*!< BLUE CMDREG: LOCKAHBFIRSTINITEN (Bit 2) */
8051 #define BLUE_CMDREG_LOCKAHBFIRSTINITEN_Msk                                 (0x00000004UL)  /*!< BLUE CMDREG: LOCKAHBFIRSTINITEN (Bitfield-Mask: 0x1) */
8052 #define BLUE_CMDREG_LOCKAHBFIRSTINITEN                                     BLUE_CMDREG_LOCKAHBFIRSTINITEN_Msk
8053 #define BLUE_CMDREG_CLEARSEMAREQ_Pos                                       (3UL)   /*!< BLUE CMDREG: CLEARSEMAREQ (Bit 3) */
8054 #define BLUE_CMDREG_CLEARSEMAREQ_Msk                                       (0x00000008UL)  /*!< BLUE CMDREG: CLEARSEMAREQ (Bitfield-Mask: 0x1) */
8055 #define BLUE_CMDREG_CLEARSEMAREQ                                           BLUE_CMDREG_CLEARSEMAREQ_Msk
8056 
8057 /* ===============================================   STATUSREG   =============================================== */
8058 #define BLUE_STATUSREG_AESONFLYBUSY_Pos                                    (0UL)   /*!< BLUE STATUSREG: AESONFLYBUSY (Bit 0) */
8059 #define BLUE_STATUSREG_AESONFLYBUSY_Msk                                    (0x00000001UL)  /*!< BLUE STATUSREG: AESONFLYBUSY (Bitfield-Mask: 0x1) */
8060 #define BLUE_STATUSREG_AESONFLYBUSY                                        BLUE_STATUSREG_AESONFLYBUSY_Msk
8061 #define BLUE_STATUSREG_NOT_SUPPORTED_FEATURE_Pos                           (3UL)   /*!< BLUE STATUSREG: NOT_SUPPORTED_FEATURE (Bit 3) */
8062 #define BLUE_STATUSREG_NOT_SUPPORTED_FEATURE_Msk                           (0x00000008UL)  /*!< BLUE STATUSREG: NOT_SUPPORTED_FEATURE (Bitfield-Mask: 0x1) */
8063 #define BLUE_STATUSREG_NOT_SUPPORTED_FEATURE                               BLUE_STATUSREG_NOT_SUPPORTED_FEATURE_Msk
8064 #define BLUE_STATUSREG_ADDPOINTERROR_Pos                                   (4UL)   /*!< BLUE STATUSREG: ADDPOINTERROR (Bit 4) */
8065 #define BLUE_STATUSREG_ADDPOINTERROR_Msk                                   (0x00000010UL)  /*!< BLUE STATUSREG: ADDPOINTERROR (Bitfield-Mask: 0x1) */
8066 #define BLUE_STATUSREG_ADDPOINTERROR                                       BLUE_STATUSREG_ADDPOINTERROR_Msk
8067 #define BLUE_STATUSREG_RXOVERFLOWERROR_Pos                                 (5UL)   /*!< BLUE STATUSREG: RXOVERFLOWERROR (Bit 5) */
8068 #define BLUE_STATUSREG_RXOVERFLOWERROR_Msk                                 (0x00000020UL)  /*!< BLUE STATUSREG: RXOVERFLOWERROR (Bitfield-Mask: 0x1) */
8069 #define BLUE_STATUSREG_RXOVERFLOWERROR                                     BLUE_STATUSREG_RXOVERFLOWERROR_Msk
8070 #define BLUE_STATUSREG_PREVTRANSMIT_Pos                                    (6UL)   /*!< BLUE STATUSREG: PREVTRANSMIT (Bit 6) */
8071 #define BLUE_STATUSREG_PREVTRANSMIT_Msk                                    (0x00000040UL)  /*!< BLUE STATUSREG: PREVTRANSMIT (Bitfield-Mask: 0x1) */
8072 #define BLUE_STATUSREG_PREVTRANSMIT                                        BLUE_STATUSREG_PREVTRANSMIT_Msk
8073 #define BLUE_STATUSREG_SEQDONE_Pos                                         (7UL)   /*!< BLUE STATUSREG: SEQDONE (Bit 7) */
8074 #define BLUE_STATUSREG_SEQDONE_Msk                                         (0x00000080UL)  /*!< BLUE STATUSREG: SEQDONE (Bitfield-Mask: 0x1) */
8075 #define BLUE_STATUSREG_SEQDONE                                             BLUE_STATUSREG_SEQDONE_Msk
8076 #define BLUE_STATUSREG_TXERROR_0_Pos                                       (8UL)   /*!< BLUE STATUSREG: TXERROR_0 (Bit 8) */
8077 #define BLUE_STATUSREG_TXERROR_0_Msk                                       (0x00000100UL)  /*!< BLUE STATUSREG: TXERROR_0 (Bitfield-Mask: 0x1) */
8078 #define BLUE_STATUSREG_TXERROR_0                                           BLUE_STATUSREG_TXERROR_0_Msk
8079 #define BLUE_STATUSREG_TXERROR_1_Pos                                       (9UL)   /*!< BLUE STATUSREG: TXERROR_1 (Bit 9) */
8080 #define BLUE_STATUSREG_TXERROR_1_Msk                                       (0x00000200UL)  /*!< BLUE STATUSREG: TXERROR_1 (Bitfield-Mask: 0x1) */
8081 #define BLUE_STATUSREG_TXERROR_1                                           BLUE_STATUSREG_TXERROR_1_Msk
8082 #define BLUE_STATUSREG_TXERROR_2_Pos                                       (10UL)   /*!< BLUE STATUSREG: TXERROR_2 (Bit 10) */
8083 #define BLUE_STATUSREG_TXERROR_2_Msk                                       (0x00000400UL)  /*!< BLUE STATUSREG: TXERROR_2 (Bitfield-Mask: 0x1) */
8084 #define BLUE_STATUSREG_TXERROR_2                                           BLUE_STATUSREG_TXERROR_2_Msk
8085 #define BLUE_STATUSREG_TXERROR_3_Pos                                       (11UL)   /*!< BLUE STATUSREG: TXERROR_3 (Bit 11) */
8086 #define BLUE_STATUSREG_TXERROR_3_Msk                                       (0x00000800UL)  /*!< BLUE STATUSREG: TXERROR_3 (Bitfield-Mask: 0x1) */
8087 #define BLUE_STATUSREG_TXERROR_3                                           BLUE_STATUSREG_TXERROR_3_Msk
8088 #define BLUE_STATUSREG_TXERROR_4_Pos                                       (12UL)   /*!< BLUE STATUSREG: TXERROR_4 (Bit 12) */
8089 #define BLUE_STATUSREG_TXERROR_4_Msk                                       (0x00001000UL)  /*!< BLUE STATUSREG: TXERROR_4 (Bitfield-Mask: 0x1) */
8090 #define BLUE_STATUSREG_TXERROR_4                                           BLUE_STATUSREG_TXERROR_4_Msk
8091 #define BLUE_STATUSREG_ENCERROR_Pos                                        (13UL)   /*!< BLUE STATUSREG: ENCERROR (Bit 13) */
8092 #define BLUE_STATUSREG_ENCERROR_Msk                                        (0x00002000UL)  /*!< BLUE STATUSREG: ENCERROR (Bitfield-Mask: 0x1) */
8093 #define BLUE_STATUSREG_ENCERROR                                            BLUE_STATUSREG_ENCERROR_Msk
8094 #define BLUE_STATUSREG_ALLTABLEREADYERROR_Pos                              (14UL)   /*!< BLUE STATUSREG: ALLTABLEREADYERROR (Bit 14) */
8095 #define BLUE_STATUSREG_ALLTABLEREADYERROR_Msk                              (0x00004000UL)  /*!< BLUE STATUSREG: ALLTABLEREADYERROR (Bitfield-Mask: 0x1) */
8096 #define BLUE_STATUSREG_ALLTABLEREADYERROR                                  BLUE_STATUSREG_ALLTABLEREADYERROR_Msk
8097 #define BLUE_STATUSREG_TXDATAREADYERROR_Pos                                (15UL)   /*!< BLUE STATUSREG: TXDATAREADYERROR (Bit 15) */
8098 #define BLUE_STATUSREG_TXDATAREADYERROR_Msk                                (0x00008000UL)  /*!< BLUE STATUSREG: TXDATAREADYERROR (Bitfield-Mask: 0x1) */
8099 #define BLUE_STATUSREG_TXDATAREADYERROR                                    BLUE_STATUSREG_TXDATAREADYERROR_Msk
8100 #define BLUE_STATUSREG_NOACTIVELERROR_Pos                                  (16UL)   /*!< BLUE STATUSREG: NOACTIVELERROR (Bit 16) */
8101 #define BLUE_STATUSREG_NOACTIVELERROR_Msk                                  (0x00010000UL)  /*!< BLUE STATUSREG: NOACTIVELERROR (Bitfield-Mask: 0x1) */
8102 #define BLUE_STATUSREG_NOACTIVELERROR                                      BLUE_STATUSREG_NOACTIVELERROR_Msk
8103 #define BLUE_STATUSREG_INITDELAYERROR_Pos                                  (17UL)   /*!< BLUE STATUSREG: INITDELAYERROR (Bit 17) */
8104 #define BLUE_STATUSREG_INITDELAYERROR_Msk                                  (0x00020000UL)  /*!< BLUE STATUSREG: INITDELAYERROR (Bitfield-Mask: 0x1) */
8105 #define BLUE_STATUSREG_INITDELAYERROR                                      BLUE_STATUSREG_INITDELAYERROR_Msk
8106 #define BLUE_STATUSREG_RCVLENGTHERROR_Pos                                  (18UL)   /*!< BLUE STATUSREG: RCVLENGTHERROR (Bit 18) */
8107 #define BLUE_STATUSREG_RCVLENGTHERROR_Msk                                  (0x00040000UL)  /*!< BLUE STATUSREG: RCVLENGTHERROR (Bitfield-Mask: 0x1) */
8108 #define BLUE_STATUSREG_RCVLENGTHERROR                                      BLUE_STATUSREG_RCVLENGTHERROR_Msk
8109 #define BLUE_STATUSREG_SEMATIMEOUTERROR_Pos                                (19UL)   /*!< BLUE STATUSREG: SEMATIMEOUTERROR (Bit 19) */
8110 #define BLUE_STATUSREG_SEMATIMEOUTERROR_Msk                                (0x00080000UL)  /*!< BLUE STATUSREG: SEMATIMEOUTERROR (Bitfield-Mask: 0x1) */
8111 #define BLUE_STATUSREG_SEMATIMEOUTERROR                                    BLUE_STATUSREG_SEMATIMEOUTERROR_Msk
8112 #define BLUE_STATUSREG_SEMAWASPREEMPT_Pos                                  (20UL)   /*!< BLUE STATUSREG: SEMAWASPREEMPT (Bit 20) */
8113 #define BLUE_STATUSREG_SEMAWASPREEMPT_Msk                                  (0x00100000UL)  /*!< BLUE STATUSREG: SEMAWASPREEMPT (Bitfield-Mask: 0x1) */
8114 #define BLUE_STATUSREG_SEMAWASPREEMPT                                      BLUE_STATUSREG_SEMAWASPREEMPT_Msk
8115 #define BLUE_STATUSREG_TXRXSKIP_Pos                                        (21UL)   /*!< BLUE STATUSREG: TXRXSKIP (Bit 21) */
8116 #define BLUE_STATUSREG_TXRXSKIP_Msk                                        (0x00200000UL)  /*!< BLUE STATUSREG: TXRXSKIP (Bitfield-Mask: 0x1) */
8117 #define BLUE_STATUSREG_TXRXSKIP                                            BLUE_STATUSREG_TXRXSKIP_Msk
8118 #define BLUE_STATUSREG_ACTIVE2ERROR_Pos                                    (22UL)   /*!< BLUE STATUSREG: ACTIVE2ERROR (Bit 22) */
8119 #define BLUE_STATUSREG_ACTIVE2ERROR_Msk                                    (0x00400000UL)  /*!< BLUE STATUSREG: ACTIVE2ERROR (Bitfield-Mask: 0x1) */
8120 #define BLUE_STATUSREG_ACTIVE2ERROR                                        BLUE_STATUSREG_ACTIVE2ERROR_Msk
8121 #define BLUE_STATUSREG_CONFIGERROR_Pos                                     (23UL)   /*!< BLUE STATUSREG: CONFIGERROR (Bit 23) */
8122 #define BLUE_STATUSREG_CONFIGERROR_Msk                                     (0x00800000UL)  /*!< BLUE STATUSREG: CONFIGERROR (Bitfield-Mask: 0x1) */
8123 #define BLUE_STATUSREG_CONFIGERROR                                         BLUE_STATUSREG_CONFIGERROR_Msk
8124 #define BLUE_STATUSREG_TXOK_Pos                                            (24UL)   /*!< BLUE STATUSREG: TXOK (Bit 24) */
8125 #define BLUE_STATUSREG_TXOK_Msk                                            (0x01000000UL)  /*!< BLUE STATUSREG: TXOK (Bitfield-Mask: 0x1) */
8126 #define BLUE_STATUSREG_TXOK                                                BLUE_STATUSREG_TXOK_Msk
8127 #define BLUE_STATUSREG_DONE_Pos                                            (25UL)   /*!< BLUE STATUSREG: DONE (Bit 25) */
8128 #define BLUE_STATUSREG_DONE_Msk                                            (0x02000000UL)  /*!< BLUE STATUSREG: DONE (Bitfield-Mask: 0x1) */
8129 #define BLUE_STATUSREG_DONE                                                BLUE_STATUSREG_DONE_Msk
8130 #define BLUE_STATUSREG_RCVTIMEOUT_Pos                                      (26UL)   /*!< BLUE STATUSREG: RCVTIMEOUT (Bit 26) */
8131 #define BLUE_STATUSREG_RCVTIMEOUT_Msk                                      (0x04000000UL)  /*!< BLUE STATUSREG: RCVTIMEOUT (Bitfield-Mask: 0x1) */
8132 #define BLUE_STATUSREG_RCVTIMEOUT                                          BLUE_STATUSREG_RCVTIMEOUT_Msk
8133 #define BLUE_STATUSREG_RCVNOMD_Pos                                         (27UL)   /*!< BLUE STATUSREG: RCVNOMD (Bit 27) */
8134 #define BLUE_STATUSREG_RCVNOMD_Msk                                         (0x08000000UL)  /*!< BLUE STATUSREG: RCVNOMD (Bitfield-Mask: 0x1) */
8135 #define BLUE_STATUSREG_RCVNOMD                                             BLUE_STATUSREG_RCVNOMD_Msk
8136 #define BLUE_STATUSREG_RCVCMD_Pos                                          (28UL)   /*!< BLUE STATUSREG: RCVCMD (Bit 28) */
8137 #define BLUE_STATUSREG_RCVCMD_Msk                                          (0x10000000UL)  /*!< BLUE STATUSREG: RCVCMD (Bitfield-Mask: 0x1) */
8138 #define BLUE_STATUSREG_RCVCMD                                              BLUE_STATUSREG_RCVCMD_Msk
8139 #define BLUE_STATUSREG_TIMECAPTURETRIG_Pos                                 (29UL)   /*!< BLUE STATUSREG: TIMECAPTURETRIG (Bit 29) */
8140 #define BLUE_STATUSREG_TIMECAPTURETRIG_Msk                                 (0x20000000UL)  /*!< BLUE STATUSREG: TIMECAPTURETRIG (Bitfield-Mask: 0x1) */
8141 #define BLUE_STATUSREG_TIMECAPTURETRIG                                     BLUE_STATUSREG_TIMECAPTURETRIG_Msk
8142 #define BLUE_STATUSREG_RCVCRCERR_Pos                                       (30UL)   /*!< BLUE STATUSREG: RCVCRCERR (Bit 30) */
8143 #define BLUE_STATUSREG_RCVCRCERR_Msk                                       (0x40000000UL)  /*!< BLUE STATUSREG: RCVCRCERR (Bitfield-Mask: 0x1) */
8144 #define BLUE_STATUSREG_RCVCRCERR                                           BLUE_STATUSREG_RCVCRCERR_Msk
8145 #define BLUE_STATUSREG_RCVOK_Pos                                           (31UL)   /*!< BLUE STATUSREG: RCVOK (Bit 31) */
8146 #define BLUE_STATUSREG_RCVOK_Msk                                           (0x80000000UL)  /*!< BLUE STATUSREG: RCVOK (Bitfield-Mask: 0x1) */
8147 #define BLUE_STATUSREG_RCVOK                                               BLUE_STATUSREG_RCVOK_Msk
8148 
8149 /* ===============================================   INTERRUPT1ENABLEREG   =============================================== */
8150 #define BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR_Pos                         (4UL)   /*!< BLUE INTERRUPT1ENABLEREG: ADDPOINTERROR (Bit 4) */
8151 #define BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR_Msk                         (0x00000010UL)  /*!< BLUE INTERRUPT1ENABLEREG: ADDPOINTERROR (Bitfield-Mask: 0x1) */
8152 #define BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR                             BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR_Msk
8153 #define BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR_Pos                       (5UL)   /*!< BLUE INTERRUPT1ENABLEREG: RXOVERFLOWERROR (Bit 5) */
8154 #define BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR_Msk                       (0x00000020UL)  /*!< BLUE INTERRUPT1ENABLEREG: RXOVERFLOWERROR (Bitfield-Mask: 0x1) */
8155 #define BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR                           BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR_Msk
8156 #define BLUE_INTERRUPT1ENABLEREG_SEQDONE_Pos                               (7UL)   /*!< BLUE INTERRUPT1ENABLEREG: SEQDONE (Bit 7) */
8157 #define BLUE_INTERRUPT1ENABLEREG_SEQDONE_Msk                               (0x00000080UL)  /*!< BLUE INTERRUPT1ENABLEREG: SEQDONE (Bitfield-Mask: 0x1) */
8158 #define BLUE_INTERRUPT1ENABLEREG_SEQDONE                                   BLUE_INTERRUPT1ENABLEREG_SEQDONE_Msk
8159 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_0_Pos                             (8UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_0 (Bit 8) */
8160 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_0_Msk                             (0x00000100UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_0 (Bitfield-Mask: 0x1) */
8161 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_0                                 BLUE_INTERRUPT1ENABLEREG_TXERROR_0_Msk
8162 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_1_Pos                             (9UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_1 (Bit 9) */
8163 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_1_Msk                             (0x00000200UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_1 (Bitfield-Mask: 0x1) */
8164 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_1                                 BLUE_INTERRUPT1ENABLEREG_TXERROR_1_Msk
8165 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_2_Pos                             (10UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_2 (Bit 10) */
8166 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_2_Msk                             (0x00000400UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_2 (Bitfield-Mask: 0x1) */
8167 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_2                                 BLUE_INTERRUPT1ENABLEREG_TXERROR_2_Msk
8168 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_3_Pos                             (11UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_3 (Bit 11) */
8169 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_3_Msk                             (0x00000800UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_3 (Bitfield-Mask: 0x1) */
8170 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_3                                 BLUE_INTERRUPT1ENABLEREG_TXERROR_3_Msk
8171 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_4_Pos                             (12UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_4 (Bit 12) */
8172 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_4_Msk                             (0x00001000UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXERROR_4 (Bitfield-Mask: 0x1) */
8173 #define BLUE_INTERRUPT1ENABLEREG_TXERROR_4                                 BLUE_INTERRUPT1ENABLEREG_TXERROR_4_Msk
8174 #define BLUE_INTERRUPT1ENABLEREG_ENCERROR_Pos                              (13UL)   /*!< BLUE INTERRUPT1ENABLEREG: ENCERROR (Bit 13) */
8175 #define BLUE_INTERRUPT1ENABLEREG_ENCERROR_Msk                              (0x00002000UL)  /*!< BLUE INTERRUPT1ENABLEREG: ENCERROR (Bitfield-Mask: 0x1) */
8176 #define BLUE_INTERRUPT1ENABLEREG_ENCERROR                                  BLUE_INTERRUPT1ENABLEREG_ENCERROR_Msk
8177 #define BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR_Pos                    (14UL)   /*!< BLUE INTERRUPT1ENABLEREG: ALLTABLEREADYERROR (Bit 14) */
8178 #define BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR_Msk                    (0x00004000UL)  /*!< BLUE INTERRUPT1ENABLEREG: ALLTABLEREADYERROR (Bitfield-Mask: 0x1) */
8179 #define BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR                        BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR_Msk
8180 #define BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR_Pos                      (15UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXDATAREADYERROR (Bit 15) */
8181 #define BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR_Msk                      (0x00008000UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXDATAREADYERROR (Bitfield-Mask: 0x1) */
8182 #define BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR                          BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR_Msk
8183 #define BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR_Pos                        (16UL)   /*!< BLUE INTERRUPT1ENABLEREG: NOACTIVELERROR (Bit 16) */
8184 #define BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR_Msk                        (0x00010000UL)  /*!< BLUE INTERRUPT1ENABLEREG: NOACTIVELERROR (Bitfield-Mask: 0x1) */
8185 #define BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR                            BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR_Msk
8186 #define BLUE_INTERRUPT1ENABLEREG_INITDELAYERROR_Pos                        (17UL)   /*!< BLUE INTERRUPT1ENABLEREG: INITDELAYERROR (Bit 17) */
8187 #define BLUE_INTERRUPT1ENABLEREG_INITDELAYERROR_Msk                        (0x00020000UL)  /*!< BLUE INTERRUPT1ENABLEREG: INITDELAYERROR (Bitfield-Mask: 0x1) */
8188 #define BLUE_INTERRUPT1ENABLEREG_INITDELAYERROR                            BLUE_INTERRUPT1ENABLEREG_INITDELAYERROR_Msk
8189 #define BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR_Pos                        (18UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVLENGTHERROR (Bit 18) */
8190 #define BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR_Msk                        (0x00040000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVLENGTHERROR (Bitfield-Mask: 0x1) */
8191 #define BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR                            BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR_Msk
8192 #define BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR_Pos                      (19UL)   /*!< BLUE INTERRUPT1ENABLEREG: SEMATIMEOUTERROR (Bit 19) */
8193 #define BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR_Msk                      (0x00080000UL)  /*!< BLUE INTERRUPT1ENABLEREG: SEMATIMEOUTERROR (Bitfield-Mask: 0x1) */
8194 #define BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR                          BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR_Msk
8195 #define BLUE_INTERRUPT1ENABLEREG_SEMAWASPREEMPT_Pos                        (20UL)   /*!< BLUE INTERRUPT1ENABLEREG: SEMAWASPREEMPT (Bit 20) */
8196 #define BLUE_INTERRUPT1ENABLEREG_SEMAWASPREEMPT_Msk                        (0x00100000UL)  /*!< BLUE INTERRUPT1ENABLEREG: SEMAWASPREEMPT (Bitfield-Mask: 0x1) */
8197 #define BLUE_INTERRUPT1ENABLEREG_SEMAWASPREEMPT                            BLUE_INTERRUPT1ENABLEREG_SEMAWASPREEMPT_Msk
8198 #define BLUE_INTERRUPT1ENABLEREG_TXRXSKIP_Pos                              (21UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXRXSKIP (Bit 21) */
8199 #define BLUE_INTERRUPT1ENABLEREG_TXRXSKIP_Msk                              (0x00200000UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXRXSKIP (Bitfield-Mask: 0x1) */
8200 #define BLUE_INTERRUPT1ENABLEREG_TXRXSKIP                                  BLUE_INTERRUPT1ENABLEREG_TXRXSKIP_Msk
8201 #define BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR_Pos                          (22UL)   /*!< BLUE INTERRUPT1ENABLEREG: ACTIVE2ERROR (Bit 22) */
8202 #define BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR_Msk                          (0x00400000UL)  /*!< BLUE INTERRUPT1ENABLEREG: ACTIVE2ERROR (Bitfield-Mask: 0x1) */
8203 #define BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR                              BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR_Msk
8204 #define BLUE_INTERRUPT1ENABLEREG_CONFIGERROR_Pos                           (23UL)   /*!< BLUE INTERRUPT1ENABLEREG: CONFIGERROR (Bit 23) */
8205 #define BLUE_INTERRUPT1ENABLEREG_CONFIGERROR_Msk                           (0x00800000UL)  /*!< BLUE INTERRUPT1ENABLEREG: CONFIGERROR (Bitfield-Mask: 0x1) */
8206 #define BLUE_INTERRUPT1ENABLEREG_CONFIGERROR                               BLUE_INTERRUPT1ENABLEREG_CONFIGERROR_Msk
8207 #define BLUE_INTERRUPT1ENABLEREG_TXOK_Pos                                  (24UL)   /*!< BLUE INTERRUPT1ENABLEREG: TXOK (Bit 24) */
8208 #define BLUE_INTERRUPT1ENABLEREG_TXOK_Msk                                  (0x01000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: TXOK (Bitfield-Mask: 0x1) */
8209 #define BLUE_INTERRUPT1ENABLEREG_TXOK                                      BLUE_INTERRUPT1ENABLEREG_TXOK_Msk
8210 #define BLUE_INTERRUPT1ENABLEREG_DONE_Pos                                  (25UL)   /*!< BLUE INTERRUPT1ENABLEREG: DONE (Bit 25) */
8211 #define BLUE_INTERRUPT1ENABLEREG_DONE_Msk                                  (0x02000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: DONE (Bitfield-Mask: 0x1) */
8212 #define BLUE_INTERRUPT1ENABLEREG_DONE                                      BLUE_INTERRUPT1ENABLEREG_DONE_Msk
8213 #define BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT_Pos                            (26UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVTIMEOUT (Bit 26) */
8214 #define BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT_Msk                            (0x04000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVTIMEOUT (Bitfield-Mask: 0x1) */
8215 #define BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT                                BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT_Msk
8216 #define BLUE_INTERRUPT1ENABLEREG_RCVNOMD_Pos                               (27UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVNOMD (Bit 27) */
8217 #define BLUE_INTERRUPT1ENABLEREG_RCVNOMD_Msk                               (0x08000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVNOMD (Bitfield-Mask: 0x1) */
8218 #define BLUE_INTERRUPT1ENABLEREG_RCVNOMD                                   BLUE_INTERRUPT1ENABLEREG_RCVNOMD_Msk
8219 #define BLUE_INTERRUPT1ENABLEREG_RCVCMD_Pos                                (28UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVCMD (Bit 28) */
8220 #define BLUE_INTERRUPT1ENABLEREG_RCVCMD_Msk                                (0x10000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVCMD (Bitfield-Mask: 0x1) */
8221 #define BLUE_INTERRUPT1ENABLEREG_RCVCMD                                    BLUE_INTERRUPT1ENABLEREG_RCVCMD_Msk
8222 #define BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG_Pos                       (29UL)   /*!< BLUE INTERRUPT1ENABLEREG: TIMECAPTURETRIG (Bit 29) */
8223 #define BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG_Msk                       (0x20000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: TIMECAPTURETRIG (Bitfield-Mask: 0x1) */
8224 #define BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG                           BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG_Msk
8225 #define BLUE_INTERRUPT1ENABLEREG_RCVCRCERR_Pos                             (30UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVCRCERR (Bit 30) */
8226 #define BLUE_INTERRUPT1ENABLEREG_RCVCRCERR_Msk                             (0x40000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVCRCERR (Bitfield-Mask: 0x1) */
8227 #define BLUE_INTERRUPT1ENABLEREG_RCVCRCERR                                 BLUE_INTERRUPT1ENABLEREG_RCVCRCERR_Msk
8228 #define BLUE_INTERRUPT1ENABLEREG_RCVOK_Pos                                 (31UL)   /*!< BLUE INTERRUPT1ENABLEREG: RCVOK (Bit 31) */
8229 #define BLUE_INTERRUPT1ENABLEREG_RCVOK_Msk                                 (0x80000000UL)  /*!< BLUE INTERRUPT1ENABLEREG: RCVOK (Bitfield-Mask: 0x1) */
8230 #define BLUE_INTERRUPT1ENABLEREG_RCVOK                                     BLUE_INTERRUPT1ENABLEREG_RCVOK_Msk
8231 
8232 /* ===============================================   INTERRUPT1LATENCYREG   =============================================== */
8233 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos                    (0UL)   /*!< BLUE INTERRUPT1LATENCYREG: INTERRUPT1LATENCY (Bit 0) */
8234 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Msk                    (0x000000ffUL)  /*!< BLUE INTERRUPT1LATENCYREG: INTERRUPT1LATENCY (Bitfield-Mask: 0xff) */
8235 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY                        BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Msk
8236 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_0                      (0x01 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000001 */
8237 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_1                      (0x02 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000002 */
8238 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_2                      (0x04 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000004 */
8239 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_3                      (0x08 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000008 */
8240 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_4                      (0x10 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000010 */
8241 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_5                      (0x20 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000020 */
8242 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_6                      (0x40 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000040 */
8243 #define BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_7                      (0x80 << BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos)   /*!<0x00000080 */
8244 
8245 /* ===============================================   MANAESKEY0REG   =============================================== */
8246 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos                              (0UL)   /*!< BLUE MANAESKEY0REG: MANAESKEY_31_0 (Bit 0) */
8247 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_Msk                              (0xffffffffUL)  /*!< BLUE MANAESKEY0REG: MANAESKEY_31_0 (Bitfield-Mask: 0xffffffffL) */
8248 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0                                  BLUE_MANAESKEY0REG_MANAESKEY_31_0_Msk
8249 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_0                                (0x00000001 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000001 */
8250 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_1                                (0x00000002 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000002 */
8251 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_2                                (0x00000004 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000004 */
8252 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_3                                (0x00000008 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000008 */
8253 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_4                                (0x00000010 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000010 */
8254 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_5                                (0x00000020 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000020 */
8255 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_6                                (0x00000040 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000040 */
8256 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_7                                (0x00000080 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000080 */
8257 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_8                                (0x00000100 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000100 */
8258 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_9                                (0x00000200 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000200 */
8259 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_10                               (0x00000400 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000400 */
8260 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_11                               (0x00000800 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00000800 */
8261 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_12                               (0x00001000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00001000 */
8262 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_13                               (0x00002000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00002000 */
8263 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_14                               (0x00004000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00004000 */
8264 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_15                               (0x00008000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00008000 */
8265 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_16                               (0x00010000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00010000 */
8266 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_17                               (0x00020000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00020000 */
8267 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_18                               (0x00040000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00040000 */
8268 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_19                               (0x00080000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00080000 */
8269 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_20                               (0x00100000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00100000 */
8270 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_21                               (0x00200000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00200000 */
8271 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_22                               (0x00400000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00400000 */
8272 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_23                               (0x00800000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x00800000 */
8273 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_24                               (0x01000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x01000000 */
8274 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_25                               (0x02000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x02000000 */
8275 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_26                               (0x04000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x04000000 */
8276 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_27                               (0x08000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x08000000 */
8277 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_28                               (0x10000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x10000000 */
8278 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_29                               (0x20000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x20000000 */
8279 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_30                               (0x40000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x40000000 */
8280 #define BLUE_MANAESKEY0REG_MANAESKEY_31_0_31                               (0x80000000 << BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos)   /*!<0x80000000 */
8281 
8282 /* ===============================================   MANAESKEY1REG   =============================================== */
8283 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos                             (0UL)   /*!< BLUE MANAESKEY1REG: MANAESKEY_63_32 (Bit 0) */
8284 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_Msk                             (0xffffffffUL)  /*!< BLUE MANAESKEY1REG: MANAESKEY_63_32 (Bitfield-Mask: 0xffffffffL) */
8285 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32                                 BLUE_MANAESKEY1REG_MANAESKEY_63_32_Msk
8286 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_0                               (0x00000001 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000001 */
8287 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_1                               (0x00000002 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000002 */
8288 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_2                               (0x00000004 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000004 */
8289 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_3                               (0x00000008 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000008 */
8290 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_4                               (0x00000010 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000010 */
8291 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_5                               (0x00000020 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000020 */
8292 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_6                               (0x00000040 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000040 */
8293 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_7                               (0x00000080 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000080 */
8294 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_8                               (0x00000100 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000100 */
8295 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_9                               (0x00000200 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000200 */
8296 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_10                              (0x00000400 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000400 */
8297 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_11                              (0x00000800 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00000800 */
8298 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_12                              (0x00001000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00001000 */
8299 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_13                              (0x00002000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00002000 */
8300 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_14                              (0x00004000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00004000 */
8301 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_15                              (0x00008000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00008000 */
8302 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_16                              (0x00010000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00010000 */
8303 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_17                              (0x00020000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00020000 */
8304 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_18                              (0x00040000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00040000 */
8305 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_19                              (0x00080000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00080000 */
8306 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_20                              (0x00100000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00100000 */
8307 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_21                              (0x00200000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00200000 */
8308 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_22                              (0x00400000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00400000 */
8309 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_23                              (0x00800000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x00800000 */
8310 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_24                              (0x01000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x01000000 */
8311 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_25                              (0x02000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x02000000 */
8312 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_26                              (0x04000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x04000000 */
8313 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_27                              (0x08000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x08000000 */
8314 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_28                              (0x10000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x10000000 */
8315 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_29                              (0x20000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x20000000 */
8316 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_30                              (0x40000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x40000000 */
8317 #define BLUE_MANAESKEY1REG_MANAESKEY_63_32_31                              (0x80000000 << BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos)   /*!<0x80000000 */
8318 
8319 /* ===============================================   MANAESKEY2REG   =============================================== */
8320 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos                             (0UL)   /*!< BLUE MANAESKEY2REG: MANAESKEY_95_64 (Bit 0) */
8321 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_Msk                             (0xffffffffUL)  /*!< BLUE MANAESKEY2REG: MANAESKEY_95_64 (Bitfield-Mask: 0xffffffffL) */
8322 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64                                 BLUE_MANAESKEY2REG_MANAESKEY_95_64_Msk
8323 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_0                               (0x00000001 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000001 */
8324 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_1                               (0x00000002 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000002 */
8325 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_2                               (0x00000004 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000004 */
8326 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_3                               (0x00000008 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000008 */
8327 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_4                               (0x00000010 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000010 */
8328 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_5                               (0x00000020 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000020 */
8329 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_6                               (0x00000040 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000040 */
8330 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_7                               (0x00000080 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000080 */
8331 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_8                               (0x00000100 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000100 */
8332 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_9                               (0x00000200 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000200 */
8333 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_10                              (0x00000400 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000400 */
8334 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_11                              (0x00000800 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00000800 */
8335 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_12                              (0x00001000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00001000 */
8336 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_13                              (0x00002000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00002000 */
8337 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_14                              (0x00004000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00004000 */
8338 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_15                              (0x00008000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00008000 */
8339 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_16                              (0x00010000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00010000 */
8340 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_17                              (0x00020000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00020000 */
8341 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_18                              (0x00040000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00040000 */
8342 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_19                              (0x00080000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00080000 */
8343 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_20                              (0x00100000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00100000 */
8344 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_21                              (0x00200000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00200000 */
8345 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_22                              (0x00400000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00400000 */
8346 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_23                              (0x00800000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x00800000 */
8347 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_24                              (0x01000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x01000000 */
8348 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_25                              (0x02000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x02000000 */
8349 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_26                              (0x04000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x04000000 */
8350 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_27                              (0x08000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x08000000 */
8351 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_28                              (0x10000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x10000000 */
8352 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_29                              (0x20000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x20000000 */
8353 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_30                              (0x40000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x40000000 */
8354 #define BLUE_MANAESKEY2REG_MANAESKEY_95_64_31                              (0x80000000 << BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos)   /*!<0x80000000 */
8355 
8356 /* ===============================================   MANAESKEY3REG   =============================================== */
8357 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos                            (0UL)   /*!< BLUE MANAESKEY3REG: MANAESKEY_127_96 (Bit 0) */
8358 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_Msk                            (0xffffffffUL)  /*!< BLUE MANAESKEY3REG: MANAESKEY_127_96 (Bitfield-Mask: 0xffffffffL) */
8359 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96                                BLUE_MANAESKEY3REG_MANAESKEY_127_96_Msk
8360 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_0                              (0x00000001 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000001 */
8361 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_1                              (0x00000002 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000002 */
8362 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_2                              (0x00000004 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000004 */
8363 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_3                              (0x00000008 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000008 */
8364 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_4                              (0x00000010 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000010 */
8365 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_5                              (0x00000020 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000020 */
8366 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_6                              (0x00000040 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000040 */
8367 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_7                              (0x00000080 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000080 */
8368 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_8                              (0x00000100 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000100 */
8369 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_9                              (0x00000200 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000200 */
8370 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_10                             (0x00000400 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000400 */
8371 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_11                             (0x00000800 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00000800 */
8372 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_12                             (0x00001000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00001000 */
8373 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_13                             (0x00002000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00002000 */
8374 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_14                             (0x00004000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00004000 */
8375 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_15                             (0x00008000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00008000 */
8376 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_16                             (0x00010000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00010000 */
8377 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_17                             (0x00020000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00020000 */
8378 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_18                             (0x00040000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00040000 */
8379 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_19                             (0x00080000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00080000 */
8380 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_20                             (0x00100000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00100000 */
8381 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_21                             (0x00200000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00200000 */
8382 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_22                             (0x00400000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00400000 */
8383 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_23                             (0x00800000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x00800000 */
8384 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_24                             (0x01000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x01000000 */
8385 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_25                             (0x02000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x02000000 */
8386 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_26                             (0x04000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x04000000 */
8387 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_27                             (0x08000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x08000000 */
8388 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_28                             (0x10000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x10000000 */
8389 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_29                             (0x20000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x20000000 */
8390 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_30                             (0x40000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x40000000 */
8391 #define BLUE_MANAESKEY3REG_MANAESKEY_127_96_31                             (0x80000000 << BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos)   /*!<0x80000000 */
8392 
8393 /* ===============================================   MANAESCLEARTEXT0REG   =============================================== */
8394 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos                        (0UL)   /*!< BLUE MANAESCLEARTEXT0REG: AES_CLEAR_31_0 (Bit 0) */
8395 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Msk                        (0xffffffffUL)  /*!< BLUE MANAESCLEARTEXT0REG: AES_CLEAR_31_0 (Bitfield-Mask: 0xffffffffL) */
8396 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0                            BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Msk
8397 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_0                          (0x00000001 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000001 */
8398 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_1                          (0x00000002 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000002 */
8399 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_2                          (0x00000004 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000004 */
8400 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_3                          (0x00000008 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000008 */
8401 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_4                          (0x00000010 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000010 */
8402 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_5                          (0x00000020 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000020 */
8403 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_6                          (0x00000040 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000040 */
8404 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_7                          (0x00000080 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000080 */
8405 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_8                          (0x00000100 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000100 */
8406 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_9                          (0x00000200 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000200 */
8407 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_10                         (0x00000400 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000400 */
8408 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_11                         (0x00000800 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00000800 */
8409 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_12                         (0x00001000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00001000 */
8410 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_13                         (0x00002000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00002000 */
8411 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_14                         (0x00004000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00004000 */
8412 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_15                         (0x00008000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00008000 */
8413 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_16                         (0x00010000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00010000 */
8414 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_17                         (0x00020000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00020000 */
8415 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_18                         (0x00040000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00040000 */
8416 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_19                         (0x00080000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00080000 */
8417 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_20                         (0x00100000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00100000 */
8418 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_21                         (0x00200000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00200000 */
8419 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_22                         (0x00400000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00400000 */
8420 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_23                         (0x00800000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x00800000 */
8421 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_24                         (0x01000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x01000000 */
8422 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_25                         (0x02000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x02000000 */
8423 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_26                         (0x04000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x04000000 */
8424 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_27                         (0x08000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x08000000 */
8425 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_28                         (0x10000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x10000000 */
8426 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_29                         (0x20000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x20000000 */
8427 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_30                         (0x40000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x40000000 */
8428 #define BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_31                         (0x80000000 << BLUE_MANAESCLEARTEXT0REG_AES_CLEAR_31_0_Pos)   /*!<0x80000000 */
8429 
8430 /* ===============================================   MANAESCLEARTEXT1REG   =============================================== */
8431 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos                       (0UL)   /*!< BLUE MANAESCLEARTEXT1REG: AES_CLEAR_63_32 (Bit 0) */
8432 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Msk                       (0xffffffffUL)  /*!< BLUE MANAESCLEARTEXT1REG: AES_CLEAR_63_32 (Bitfield-Mask: 0xffffffffL) */
8433 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32                           BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Msk
8434 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_0                         (0x00000001 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000001 */
8435 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_1                         (0x00000002 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000002 */
8436 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_2                         (0x00000004 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000004 */
8437 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_3                         (0x00000008 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000008 */
8438 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_4                         (0x00000010 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000010 */
8439 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_5                         (0x00000020 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000020 */
8440 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_6                         (0x00000040 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000040 */
8441 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_7                         (0x00000080 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000080 */
8442 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_8                         (0x00000100 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000100 */
8443 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_9                         (0x00000200 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000200 */
8444 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_10                        (0x00000400 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000400 */
8445 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_11                        (0x00000800 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00000800 */
8446 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_12                        (0x00001000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00001000 */
8447 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_13                        (0x00002000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00002000 */
8448 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_14                        (0x00004000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00004000 */
8449 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_15                        (0x00008000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00008000 */
8450 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_16                        (0x00010000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00010000 */
8451 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_17                        (0x00020000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00020000 */
8452 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_18                        (0x00040000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00040000 */
8453 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_19                        (0x00080000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00080000 */
8454 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_20                        (0x00100000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00100000 */
8455 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_21                        (0x00200000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00200000 */
8456 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_22                        (0x00400000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00400000 */
8457 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_23                        (0x00800000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x00800000 */
8458 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_24                        (0x01000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x01000000 */
8459 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_25                        (0x02000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x02000000 */
8460 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_26                        (0x04000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x04000000 */
8461 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_27                        (0x08000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x08000000 */
8462 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_28                        (0x10000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x10000000 */
8463 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_29                        (0x20000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x20000000 */
8464 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_30                        (0x40000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x40000000 */
8465 #define BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_31                        (0x80000000 << BLUE_MANAESCLEARTEXT1REG_AES_CLEAR_63_32_Pos)   /*!<0x80000000 */
8466 
8467 /* ===============================================   MANAESCLEARTEXT2REG   =============================================== */
8468 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos                       (0UL)   /*!< BLUE MANAESCLEARTEXT2REG: AES_CLEAR_95_64 (Bit 0) */
8469 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Msk                       (0xffffffffUL)  /*!< BLUE MANAESCLEARTEXT2REG: AES_CLEAR_95_64 (Bitfield-Mask: 0xffffffffL) */
8470 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64                           BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Msk
8471 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_0                         (0x00000001 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000001 */
8472 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_1                         (0x00000002 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000002 */
8473 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_2                         (0x00000004 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000004 */
8474 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_3                         (0x00000008 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000008 */
8475 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_4                         (0x00000010 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000010 */
8476 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_5                         (0x00000020 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000020 */
8477 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_6                         (0x00000040 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000040 */
8478 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_7                         (0x00000080 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000080 */
8479 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_8                         (0x00000100 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000100 */
8480 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_9                         (0x00000200 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000200 */
8481 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_10                        (0x00000400 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000400 */
8482 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_11                        (0x00000800 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00000800 */
8483 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_12                        (0x00001000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00001000 */
8484 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_13                        (0x00002000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00002000 */
8485 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_14                        (0x00004000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00004000 */
8486 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_15                        (0x00008000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00008000 */
8487 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_16                        (0x00010000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00010000 */
8488 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_17                        (0x00020000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00020000 */
8489 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_18                        (0x00040000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00040000 */
8490 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_19                        (0x00080000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00080000 */
8491 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_20                        (0x00100000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00100000 */
8492 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_21                        (0x00200000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00200000 */
8493 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_22                        (0x00400000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00400000 */
8494 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_23                        (0x00800000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x00800000 */
8495 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_24                        (0x01000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x01000000 */
8496 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_25                        (0x02000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x02000000 */
8497 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_26                        (0x04000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x04000000 */
8498 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_27                        (0x08000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x08000000 */
8499 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_28                        (0x10000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x10000000 */
8500 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_29                        (0x20000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x20000000 */
8501 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_30                        (0x40000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x40000000 */
8502 #define BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_31                        (0x80000000 << BLUE_MANAESCLEARTEXT2REG_AES_CLEAR_95_64_Pos)   /*!<0x80000000 */
8503 
8504 /* ===============================================   MANAESCLEARTEXT3REG   =============================================== */
8505 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos                      (0UL)   /*!< BLUE MANAESCLEARTEXT3REG: AES_CLEAR_127_96 (Bit 0) */
8506 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Msk                      (0xffffffffUL)  /*!< BLUE MANAESCLEARTEXT3REG: AES_CLEAR_127_96 (Bitfield-Mask: 0xffffffffL) */
8507 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96                          BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Msk
8508 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_0                        (0x00000001 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000001 */
8509 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_1                        (0x00000002 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000002 */
8510 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_2                        (0x00000004 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000004 */
8511 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_3                        (0x00000008 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000008 */
8512 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_4                        (0x00000010 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000010 */
8513 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_5                        (0x00000020 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000020 */
8514 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_6                        (0x00000040 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000040 */
8515 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_7                        (0x00000080 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000080 */
8516 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_8                        (0x00000100 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000100 */
8517 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_9                        (0x00000200 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000200 */
8518 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_10                       (0x00000400 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000400 */
8519 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_11                       (0x00000800 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00000800 */
8520 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_12                       (0x00001000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00001000 */
8521 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_13                       (0x00002000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00002000 */
8522 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_14                       (0x00004000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00004000 */
8523 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_15                       (0x00008000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00008000 */
8524 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_16                       (0x00010000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00010000 */
8525 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_17                       (0x00020000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00020000 */
8526 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_18                       (0x00040000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00040000 */
8527 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_19                       (0x00080000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00080000 */
8528 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_20                       (0x00100000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00100000 */
8529 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_21                       (0x00200000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00200000 */
8530 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_22                       (0x00400000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00400000 */
8531 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_23                       (0x00800000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x00800000 */
8532 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_24                       (0x01000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x01000000 */
8533 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_25                       (0x02000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x02000000 */
8534 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_26                       (0x04000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x04000000 */
8535 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_27                       (0x08000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x08000000 */
8536 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_28                       (0x10000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x10000000 */
8537 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_29                       (0x20000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x20000000 */
8538 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_30                       (0x40000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x40000000 */
8539 #define BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_31                       (0x80000000 << BLUE_MANAESCLEARTEXT3REG_AES_CLEAR_127_96_Pos)   /*!<0x80000000 */
8540 
8541 /* ===============================================   MANAESCIPHERTEXT0REG   =============================================== */
8542 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos                      (0UL)   /*!< BLUE MANAESCIPHERTEXT0REG: AES_CIPHER_31_0 (Bit 0) */
8543 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Msk                      (0xffffffffUL)  /*!< BLUE MANAESCIPHERTEXT0REG: AES_CIPHER_31_0 (Bitfield-Mask: 0xffffffffL) */
8544 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0                          BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Msk
8545 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_0                        (0x00000001 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000001 */
8546 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_1                        (0x00000002 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000002 */
8547 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_2                        (0x00000004 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000004 */
8548 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_3                        (0x00000008 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000008 */
8549 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_4                        (0x00000010 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000010 */
8550 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_5                        (0x00000020 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000020 */
8551 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_6                        (0x00000040 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000040 */
8552 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_7                        (0x00000080 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000080 */
8553 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_8                        (0x00000100 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000100 */
8554 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_9                        (0x00000200 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000200 */
8555 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_10                       (0x00000400 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000400 */
8556 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_11                       (0x00000800 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00000800 */
8557 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_12                       (0x00001000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00001000 */
8558 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_13                       (0x00002000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00002000 */
8559 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_14                       (0x00004000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00004000 */
8560 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_15                       (0x00008000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00008000 */
8561 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_16                       (0x00010000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00010000 */
8562 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_17                       (0x00020000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00020000 */
8563 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_18                       (0x00040000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00040000 */
8564 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_19                       (0x00080000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00080000 */
8565 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_20                       (0x00100000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00100000 */
8566 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_21                       (0x00200000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00200000 */
8567 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_22                       (0x00400000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00400000 */
8568 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_23                       (0x00800000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x00800000 */
8569 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_24                       (0x01000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x01000000 */
8570 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_25                       (0x02000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x02000000 */
8571 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_26                       (0x04000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x04000000 */
8572 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_27                       (0x08000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x08000000 */
8573 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_28                       (0x10000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x10000000 */
8574 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_29                       (0x20000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x20000000 */
8575 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_30                       (0x40000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x40000000 */
8576 #define BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_31                       (0x80000000 << BLUE_MANAESCIPHERTEXT0REG_AES_CIPHER_31_0_Pos)   /*!<0x80000000 */
8577 
8578 /* ===============================================   MANAESCIPHERTEXT1REG   =============================================== */
8579 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos                     (0UL)   /*!< BLUE MANAESCIPHERTEXT1REG: AES_CIPHER_63_32 (Bit 0) */
8580 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Msk                     (0xffffffffUL)  /*!< BLUE MANAESCIPHERTEXT1REG: AES_CIPHER_63_32 (Bitfield-Mask: 0xffffffffL) */
8581 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32                         BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Msk
8582 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_0                       (0x00000001 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000001 */
8583 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_1                       (0x00000002 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000002 */
8584 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_2                       (0x00000004 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000004 */
8585 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_3                       (0x00000008 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000008 */
8586 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_4                       (0x00000010 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000010 */
8587 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_5                       (0x00000020 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000020 */
8588 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_6                       (0x00000040 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000040 */
8589 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_7                       (0x00000080 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000080 */
8590 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_8                       (0x00000100 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000100 */
8591 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_9                       (0x00000200 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000200 */
8592 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_10                      (0x00000400 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000400 */
8593 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_11                      (0x00000800 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00000800 */
8594 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_12                      (0x00001000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00001000 */
8595 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_13                      (0x00002000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00002000 */
8596 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_14                      (0x00004000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00004000 */
8597 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_15                      (0x00008000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00008000 */
8598 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_16                      (0x00010000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00010000 */
8599 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_17                      (0x00020000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00020000 */
8600 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_18                      (0x00040000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00040000 */
8601 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_19                      (0x00080000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00080000 */
8602 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_20                      (0x00100000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00100000 */
8603 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_21                      (0x00200000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00200000 */
8604 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_22                      (0x00400000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00400000 */
8605 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_23                      (0x00800000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x00800000 */
8606 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_24                      (0x01000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x01000000 */
8607 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_25                      (0x02000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x02000000 */
8608 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_26                      (0x04000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x04000000 */
8609 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_27                      (0x08000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x08000000 */
8610 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_28                      (0x10000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x10000000 */
8611 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_29                      (0x20000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x20000000 */
8612 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_30                      (0x40000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x40000000 */
8613 #define BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_31                      (0x80000000 << BLUE_MANAESCIPHERTEXT1REG_AES_CIPHER_63_32_Pos)   /*!<0x80000000 */
8614 
8615 /* ===============================================   MANAESCIPHERTEXT2REG   =============================================== */
8616 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos                     (0UL)   /*!< BLUE MANAESCIPHERTEXT2REG: AES_CIPHER_95_64 (Bit 0) */
8617 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Msk                     (0xffffffffUL)  /*!< BLUE MANAESCIPHERTEXT2REG: AES_CIPHER_95_64 (Bitfield-Mask: 0xffffffffL) */
8618 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64                         BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Msk
8619 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_0                       (0x00000001 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000001 */
8620 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_1                       (0x00000002 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000002 */
8621 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_2                       (0x00000004 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000004 */
8622 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_3                       (0x00000008 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000008 */
8623 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_4                       (0x00000010 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000010 */
8624 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_5                       (0x00000020 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000020 */
8625 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_6                       (0x00000040 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000040 */
8626 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_7                       (0x00000080 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000080 */
8627 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_8                       (0x00000100 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000100 */
8628 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_9                       (0x00000200 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000200 */
8629 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_10                      (0x00000400 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000400 */
8630 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_11                      (0x00000800 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00000800 */
8631 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_12                      (0x00001000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00001000 */
8632 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_13                      (0x00002000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00002000 */
8633 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_14                      (0x00004000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00004000 */
8634 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_15                      (0x00008000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00008000 */
8635 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_16                      (0x00010000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00010000 */
8636 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_17                      (0x00020000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00020000 */
8637 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_18                      (0x00040000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00040000 */
8638 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_19                      (0x00080000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00080000 */
8639 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_20                      (0x00100000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00100000 */
8640 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_21                      (0x00200000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00200000 */
8641 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_22                      (0x00400000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00400000 */
8642 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_23                      (0x00800000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x00800000 */
8643 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_24                      (0x01000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x01000000 */
8644 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_25                      (0x02000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x02000000 */
8645 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_26                      (0x04000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x04000000 */
8646 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_27                      (0x08000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x08000000 */
8647 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_28                      (0x10000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x10000000 */
8648 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_29                      (0x20000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x20000000 */
8649 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_30                      (0x40000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x40000000 */
8650 #define BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_31                      (0x80000000 << BLUE_MANAESCIPHERTEXT2REG_AES_CIPHER_95_64_Pos)   /*!<0x80000000 */
8651 
8652 /* ===============================================   MANAESCIPHERTEXT3REG   =============================================== */
8653 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos                    (0UL)   /*!< BLUE MANAESCIPHERTEXT3REG: AES_CIPHER_127_96 (Bit 0) */
8654 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Msk                    (0xffffffffUL)  /*!< BLUE MANAESCIPHERTEXT3REG: AES_CIPHER_127_96 (Bitfield-Mask: 0xffffffffL) */
8655 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96                        BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Msk
8656 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_0                      (0x00000001 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000001 */
8657 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_1                      (0x00000002 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000002 */
8658 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_2                      (0x00000004 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000004 */
8659 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_3                      (0x00000008 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000008 */
8660 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_4                      (0x00000010 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000010 */
8661 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_5                      (0x00000020 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000020 */
8662 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_6                      (0x00000040 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000040 */
8663 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_7                      (0x00000080 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000080 */
8664 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_8                      (0x00000100 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000100 */
8665 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_9                      (0x00000200 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000200 */
8666 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_10                     (0x00000400 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000400 */
8667 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_11                     (0x00000800 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00000800 */
8668 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_12                     (0x00001000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00001000 */
8669 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_13                     (0x00002000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00002000 */
8670 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_14                     (0x00004000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00004000 */
8671 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_15                     (0x00008000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00008000 */
8672 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_16                     (0x00010000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00010000 */
8673 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_17                     (0x00020000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00020000 */
8674 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_18                     (0x00040000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00040000 */
8675 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_19                     (0x00080000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00080000 */
8676 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_20                     (0x00100000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00100000 */
8677 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_21                     (0x00200000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00200000 */
8678 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_22                     (0x00400000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00400000 */
8679 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_23                     (0x00800000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x00800000 */
8680 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_24                     (0x01000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x01000000 */
8681 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_25                     (0x02000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x02000000 */
8682 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_26                     (0x04000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x04000000 */
8683 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_27                     (0x08000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x08000000 */
8684 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_28                     (0x10000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x10000000 */
8685 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_29                     (0x20000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x20000000 */
8686 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_30                     (0x40000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x40000000 */
8687 #define BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_31                     (0x80000000 << BLUE_MANAESCIPHERTEXT3REG_AES_CIPHER_127_96_Pos)   /*!<0x80000000 */
8688 
8689 /* ===============================================   MANAESCMDREG   =============================================== */
8690 #define BLUE_MANAESCMDREG_START_Pos                                        (0UL)   /*!< BLUE MANAESCMDREG: START (Bit 0) */
8691 #define BLUE_MANAESCMDREG_START_Msk                                        (0x00000001UL)  /*!< BLUE MANAESCMDREG: START (Bitfield-Mask: 0x1) */
8692 #define BLUE_MANAESCMDREG_START                                            BLUE_MANAESCMDREG_START_Msk
8693 #define BLUE_MANAESCMDREG_INTENA_Pos                                       (1UL)   /*!< BLUE MANAESCMDREG: INTENA (Bit 1) */
8694 #define BLUE_MANAESCMDREG_INTENA_Msk                                       (0x00000002UL)  /*!< BLUE MANAESCMDREG: INTENA (Bitfield-Mask: 0x1) */
8695 #define BLUE_MANAESCMDREG_INTENA                                           BLUE_MANAESCMDREG_INTENA_Msk
8696 
8697 /* ===============================================   MANAESSTATREG   =============================================== */
8698 #define BLUE_MANAESSTATREG_BUSY_Pos                                        (0UL)   /*!< BLUE MANAESSTATREG: BUSY (Bit 0) */
8699 #define BLUE_MANAESSTATREG_BUSY_Msk                                        (0x00000001UL)  /*!< BLUE MANAESSTATREG: BUSY (Bitfield-Mask: 0x1) */
8700 #define BLUE_MANAESSTATREG_BUSY                                            BLUE_MANAESSTATREG_BUSY_Msk
8701 
8702 /* ===============================================   AESLEPRIVPOINTERREG   =============================================== */
8703 #define BLUE_AESLEPRIVPOINTERREG_POINTER_Pos                               (0UL)   /*!< BLUE AESLEPRIVPOINTERREG: POINTER (Bit 0) */
8704 #define BLUE_AESLEPRIVPOINTERREG_POINTER_Msk                               (0x00ffffffUL)  /*!< BLUE AESLEPRIVPOINTERREG: POINTER (Bitfield-Mask: 0xffffff) */
8705 #define BLUE_AESLEPRIVPOINTERREG_POINTER                                   BLUE_AESLEPRIVPOINTERREG_POINTER_Msk
8706 #define BLUE_AESLEPRIVPOINTERREG_POINTER_0                                 (0x000001 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000001 */
8707 #define BLUE_AESLEPRIVPOINTERREG_POINTER_1                                 (0x000002 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000002 */
8708 #define BLUE_AESLEPRIVPOINTERREG_POINTER_2                                 (0x000004 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000004 */
8709 #define BLUE_AESLEPRIVPOINTERREG_POINTER_3                                 (0x000008 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000008 */
8710 #define BLUE_AESLEPRIVPOINTERREG_POINTER_4                                 (0x000010 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000010 */
8711 #define BLUE_AESLEPRIVPOINTERREG_POINTER_5                                 (0x000020 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000020 */
8712 #define BLUE_AESLEPRIVPOINTERREG_POINTER_6                                 (0x000040 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000040 */
8713 #define BLUE_AESLEPRIVPOINTERREG_POINTER_7                                 (0x000080 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000080 */
8714 #define BLUE_AESLEPRIVPOINTERREG_POINTER_8                                 (0x000100 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000100 */
8715 #define BLUE_AESLEPRIVPOINTERREG_POINTER_9                                 (0x000200 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000200 */
8716 #define BLUE_AESLEPRIVPOINTERREG_POINTER_10                                (0x000400 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000400 */
8717 #define BLUE_AESLEPRIVPOINTERREG_POINTER_11                                (0x000800 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00000800 */
8718 #define BLUE_AESLEPRIVPOINTERREG_POINTER_12                                (0x001000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00001000 */
8719 #define BLUE_AESLEPRIVPOINTERREG_POINTER_13                                (0x002000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00002000 */
8720 #define BLUE_AESLEPRIVPOINTERREG_POINTER_14                                (0x004000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00004000 */
8721 #define BLUE_AESLEPRIVPOINTERREG_POINTER_15                                (0x008000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00008000 */
8722 #define BLUE_AESLEPRIVPOINTERREG_POINTER_16                                (0x010000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00010000 */
8723 #define BLUE_AESLEPRIVPOINTERREG_POINTER_17                                (0x020000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00020000 */
8724 #define BLUE_AESLEPRIVPOINTERREG_POINTER_18                                (0x040000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00040000 */
8725 #define BLUE_AESLEPRIVPOINTERREG_POINTER_19                                (0x080000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00080000 */
8726 #define BLUE_AESLEPRIVPOINTERREG_POINTER_20                                (0x100000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00100000 */
8727 #define BLUE_AESLEPRIVPOINTERREG_POINTER_21                                (0x200000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00200000 */
8728 #define BLUE_AESLEPRIVPOINTERREG_POINTER_22                                (0x400000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00400000 */
8729 #define BLUE_AESLEPRIVPOINTERREG_POINTER_23                                (0x800000 << BLUE_AESLEPRIVPOINTERREG_POINTER_Pos)   /*!<0x00800000 */
8730 
8731 /* ===============================================   AESLEPRIVHASHREG   =============================================== */
8732 #define BLUE_AESLEPRIVHASHREG_HASH_Pos                                     (0UL)   /*!< BLUE AESLEPRIVHASHREG: HASH (Bit 0) */
8733 #define BLUE_AESLEPRIVHASHREG_HASH_Msk                                     (0x00ffffffUL)  /*!< BLUE AESLEPRIVHASHREG: HASH (Bitfield-Mask: 0xffffff) */
8734 #define BLUE_AESLEPRIVHASHREG_HASH                                         BLUE_AESLEPRIVHASHREG_HASH_Msk
8735 #define BLUE_AESLEPRIVHASHREG_HASH_0                                       (0x000001 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000001 */
8736 #define BLUE_AESLEPRIVHASHREG_HASH_1                                       (0x000002 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000002 */
8737 #define BLUE_AESLEPRIVHASHREG_HASH_2                                       (0x000004 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000004 */
8738 #define BLUE_AESLEPRIVHASHREG_HASH_3                                       (0x000008 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000008 */
8739 #define BLUE_AESLEPRIVHASHREG_HASH_4                                       (0x000010 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000010 */
8740 #define BLUE_AESLEPRIVHASHREG_HASH_5                                       (0x000020 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000020 */
8741 #define BLUE_AESLEPRIVHASHREG_HASH_6                                       (0x000040 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000040 */
8742 #define BLUE_AESLEPRIVHASHREG_HASH_7                                       (0x000080 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000080 */
8743 #define BLUE_AESLEPRIVHASHREG_HASH_8                                       (0x000100 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000100 */
8744 #define BLUE_AESLEPRIVHASHREG_HASH_9                                       (0x000200 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000200 */
8745 #define BLUE_AESLEPRIVHASHREG_HASH_10                                      (0x000400 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000400 */
8746 #define BLUE_AESLEPRIVHASHREG_HASH_11                                      (0x000800 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00000800 */
8747 #define BLUE_AESLEPRIVHASHREG_HASH_12                                      (0x001000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00001000 */
8748 #define BLUE_AESLEPRIVHASHREG_HASH_13                                      (0x002000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00002000 */
8749 #define BLUE_AESLEPRIVHASHREG_HASH_14                                      (0x004000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00004000 */
8750 #define BLUE_AESLEPRIVHASHREG_HASH_15                                      (0x008000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00008000 */
8751 #define BLUE_AESLEPRIVHASHREG_HASH_16                                      (0x010000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00010000 */
8752 #define BLUE_AESLEPRIVHASHREG_HASH_17                                      (0x020000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00020000 */
8753 #define BLUE_AESLEPRIVHASHREG_HASH_18                                      (0x040000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00040000 */
8754 #define BLUE_AESLEPRIVHASHREG_HASH_19                                      (0x080000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00080000 */
8755 #define BLUE_AESLEPRIVHASHREG_HASH_20                                      (0x100000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00100000 */
8756 #define BLUE_AESLEPRIVHASHREG_HASH_21                                      (0x200000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00200000 */
8757 #define BLUE_AESLEPRIVHASHREG_HASH_22                                      (0x400000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00400000 */
8758 #define BLUE_AESLEPRIVHASHREG_HASH_23                                      (0x800000 << BLUE_AESLEPRIVHASHREG_HASH_Pos)   /*!<0x00800000 */
8759 
8760 /* ===============================================   AESLEPRIVPRANDREG   =============================================== */
8761 #define BLUE_AESLEPRIVPRANDREG_PRAND_Pos                                   (0UL)   /*!< BLUE AESLEPRIVPRANDREG: PRAND (Bit 0) */
8762 #define BLUE_AESLEPRIVPRANDREG_PRAND_Msk                                   (0x00ffffffUL)  /*!< BLUE AESLEPRIVPRANDREG: PRAND (Bitfield-Mask: 0xffffff) */
8763 #define BLUE_AESLEPRIVPRANDREG_PRAND                                       BLUE_AESLEPRIVPRANDREG_PRAND_Msk
8764 #define BLUE_AESLEPRIVPRANDREG_PRAND_0                                     (0x000001 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000001 */
8765 #define BLUE_AESLEPRIVPRANDREG_PRAND_1                                     (0x000002 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000002 */
8766 #define BLUE_AESLEPRIVPRANDREG_PRAND_2                                     (0x000004 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000004 */
8767 #define BLUE_AESLEPRIVPRANDREG_PRAND_3                                     (0x000008 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000008 */
8768 #define BLUE_AESLEPRIVPRANDREG_PRAND_4                                     (0x000010 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000010 */
8769 #define BLUE_AESLEPRIVPRANDREG_PRAND_5                                     (0x000020 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000020 */
8770 #define BLUE_AESLEPRIVPRANDREG_PRAND_6                                     (0x000040 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000040 */
8771 #define BLUE_AESLEPRIVPRANDREG_PRAND_7                                     (0x000080 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000080 */
8772 #define BLUE_AESLEPRIVPRANDREG_PRAND_8                                     (0x000100 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000100 */
8773 #define BLUE_AESLEPRIVPRANDREG_PRAND_9                                     (0x000200 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000200 */
8774 #define BLUE_AESLEPRIVPRANDREG_PRAND_10                                    (0x000400 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000400 */
8775 #define BLUE_AESLEPRIVPRANDREG_PRAND_11                                    (0x000800 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00000800 */
8776 #define BLUE_AESLEPRIVPRANDREG_PRAND_12                                    (0x001000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00001000 */
8777 #define BLUE_AESLEPRIVPRANDREG_PRAND_13                                    (0x002000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00002000 */
8778 #define BLUE_AESLEPRIVPRANDREG_PRAND_14                                    (0x004000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00004000 */
8779 #define BLUE_AESLEPRIVPRANDREG_PRAND_15                                    (0x008000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00008000 */
8780 #define BLUE_AESLEPRIVPRANDREG_PRAND_16                                    (0x010000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00010000 */
8781 #define BLUE_AESLEPRIVPRANDREG_PRAND_17                                    (0x020000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00020000 */
8782 #define BLUE_AESLEPRIVPRANDREG_PRAND_18                                    (0x040000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00040000 */
8783 #define BLUE_AESLEPRIVPRANDREG_PRAND_19                                    (0x080000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00080000 */
8784 #define BLUE_AESLEPRIVPRANDREG_PRAND_20                                    (0x100000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00100000 */
8785 #define BLUE_AESLEPRIVPRANDREG_PRAND_21                                    (0x200000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00200000 */
8786 #define BLUE_AESLEPRIVPRANDREG_PRAND_22                                    (0x400000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00400000 */
8787 #define BLUE_AESLEPRIVPRANDREG_PRAND_23                                    (0x800000 << BLUE_AESLEPRIVPRANDREG_PRAND_Pos)   /*!<0x00800000 */
8788 
8789 /* ===============================================   AESLEPRIVCMDREG   =============================================== */
8790 #define BLUE_AESLEPRIVCMDREG_START_Pos                                     (0UL)   /*!< BLUE AESLEPRIVCMDREG: START (Bit 0) */
8791 #define BLUE_AESLEPRIVCMDREG_START_Msk                                     (0x00000001UL)  /*!< BLUE AESLEPRIVCMDREG: START (Bitfield-Mask: 0x1) */
8792 #define BLUE_AESLEPRIVCMDREG_START                                         BLUE_AESLEPRIVCMDREG_START_Msk
8793 #define BLUE_AESLEPRIVCMDREG_INTENA_Pos                                    (1UL)   /*!< BLUE AESLEPRIVCMDREG: INTENA (Bit 1) */
8794 #define BLUE_AESLEPRIVCMDREG_INTENA_Msk                                    (0x00000002UL)  /*!< BLUE AESLEPRIVCMDREG: INTENA (Bitfield-Mask: 0x1) */
8795 #define BLUE_AESLEPRIVCMDREG_INTENA                                        BLUE_AESLEPRIVCMDREG_INTENA_Msk
8796 #define BLUE_AESLEPRIVCMDREG_NBKEYS_Pos                                    (2UL)   /*!< BLUE AESLEPRIVCMDREG: NBKEYS (Bit 2) */
8797 #define BLUE_AESLEPRIVCMDREG_NBKEYS_Msk                                    (0x000003fcUL)  /*!< BLUE AESLEPRIVCMDREG: NBKEYS (Bitfield-Mask: 0xff) */
8798 #define BLUE_AESLEPRIVCMDREG_NBKEYS                                        BLUE_AESLEPRIVCMDREG_NBKEYS_Msk
8799 #define BLUE_AESLEPRIVCMDREG_NBKEYS_0                                      (0x01 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000004 */
8800 #define BLUE_AESLEPRIVCMDREG_NBKEYS_1                                      (0x02 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000008 */
8801 #define BLUE_AESLEPRIVCMDREG_NBKEYS_2                                      (0x04 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000010 */
8802 #define BLUE_AESLEPRIVCMDREG_NBKEYS_3                                      (0x08 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000020 */
8803 #define BLUE_AESLEPRIVCMDREG_NBKEYS_4                                      (0x10 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000040 */
8804 #define BLUE_AESLEPRIVCMDREG_NBKEYS_5                                      (0x20 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000080 */
8805 #define BLUE_AESLEPRIVCMDREG_NBKEYS_6                                      (0x40 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000100 */
8806 #define BLUE_AESLEPRIVCMDREG_NBKEYS_7                                      (0x80 << BLUE_AESLEPRIVCMDREG_NBKEYS_Pos)   /*!<0x00000200 */
8807 
8808 /* ===============================================   AESLEPRIVSTATREG   =============================================== */
8809 #define BLUE_AESLEPRIVSTATREG_BUSY_Pos                                     (0UL)   /*!< BLUE AESLEPRIVSTATREG: BUSY (Bit 0) */
8810 #define BLUE_AESLEPRIVSTATREG_BUSY_Msk                                     (0x00000001UL)  /*!< BLUE AESLEPRIVSTATREG: BUSY (Bitfield-Mask: 0x1) */
8811 #define BLUE_AESLEPRIVSTATREG_BUSY                                         BLUE_AESLEPRIVSTATREG_BUSY_Msk
8812 #define BLUE_AESLEPRIVSTATREG_KEYFND_Pos                                   (1UL)   /*!< BLUE AESLEPRIVSTATREG: KEYFND (Bit 1) */
8813 #define BLUE_AESLEPRIVSTATREG_KEYFND_Msk                                   (0x00000002UL)  /*!< BLUE AESLEPRIVSTATREG: KEYFND (Bitfield-Mask: 0x1) */
8814 #define BLUE_AESLEPRIVSTATREG_KEYFND                                       BLUE_AESLEPRIVSTATREG_KEYFND_Msk
8815 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos                              (2UL)   /*!< BLUE AESLEPRIVSTATREG: KEYFNDINDEX (Bit 2) */
8816 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Msk                              (0x000003fcUL)  /*!< BLUE AESLEPRIVSTATREG: KEYFNDINDEX (Bitfield-Mask: 0xff) */
8817 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX                                  BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Msk
8818 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_0                                (0x01 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000004 */
8819 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_1                                (0x02 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000008 */
8820 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_2                                (0x04 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000010 */
8821 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_3                                (0x08 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000020 */
8822 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_4                                (0x10 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000040 */
8823 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_5                                (0x20 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000080 */
8824 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_6                                (0x40 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000100 */
8825 #define BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_7                                (0x80 << BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos)   /*!<0x00000200 */
8826 
8827 /* ===============================================   DEBUGCMDREG   =============================================== */
8828 #define BLUE_DEBUGCMDREG_CLEARDEBUGINT_Pos                                 (0UL)   /*!< BLUE DEBUGCMDREG: CLEARDEBUGINT (Bit 0) */
8829 #define BLUE_DEBUGCMDREG_CLEARDEBUGINT_Msk                                 (0x00000001UL)  /*!< BLUE DEBUGCMDREG: CLEARDEBUGINT (Bitfield-Mask: 0x1) */
8830 #define BLUE_DEBUGCMDREG_CLEARDEBUGINT                                     BLUE_DEBUGCMDREG_CLEARDEBUGINT_Msk
8831 #define BLUE_DEBUGCMDREG_SEQDEBUGMODE_Pos                                  (1UL)   /*!< BLUE DEBUGCMDREG: SEQDEBUGMODE (Bit 1) */
8832 #define BLUE_DEBUGCMDREG_SEQDEBUGMODE_Msk                                  (0x00000002UL)  /*!< BLUE DEBUGCMDREG: SEQDEBUGMODE (Bitfield-Mask: 0x1) */
8833 #define BLUE_DEBUGCMDREG_SEQDEBUGMODE                                      BLUE_DEBUGCMDREG_SEQDEBUGMODE_Msk
8834 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Pos                                (2UL)   /*!< BLUE DEBUGCMDREG: SEQDEBUGBUSSEL (Bit 2) */
8835 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Msk                                (0x0000003cUL)  /*!< BLUE DEBUGCMDREG: SEQDEBUGBUSSEL (Bitfield-Mask: 0xf) */
8836 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL                                    BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Msk
8837 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_0                                  (0x1 << BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Pos)   /*!<0x00000004 */
8838 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_1                                  (0x2 << BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Pos)   /*!<0x00000008 */
8839 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_2                                  (0x4 << BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Pos)   /*!<0x00000010 */
8840 #define BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_3                                  (0x8 << BLUE_DEBUGCMDREG_SEQDEBUGBUSSEL_Pos)   /*!<0x00000020 */
8841 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_Pos                                  (16UL)   /*!< BLUE DEBUGCMDREG: AESDEBUGMODE (Bit 16) */
8842 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_Msk                                  (0x000f0000UL)  /*!< BLUE DEBUGCMDREG: AESDEBUGMODE (Bitfield-Mask: 0xf) */
8843 #define BLUE_DEBUGCMDREG_AESDEBUGMODE                                      BLUE_DEBUGCMDREG_AESDEBUGMODE_Msk
8844 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_0                                    (0x1 << BLUE_DEBUGCMDREG_AESDEBUGMODE_Pos)   /*!<0x00010000 */
8845 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_1                                    (0x2 << BLUE_DEBUGCMDREG_AESDEBUGMODE_Pos)   /*!<0x00020000 */
8846 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_2                                    (0x4 << BLUE_DEBUGCMDREG_AESDEBUGMODE_Pos)   /*!<0x00040000 */
8847 #define BLUE_DEBUGCMDREG_AESDEBUGMODE_3                                    (0x8 << BLUE_DEBUGCMDREG_AESDEBUGMODE_Pos)   /*!<0x00080000 */
8848 
8849 /* ===============================================   DEBUGSTATUSREG   =============================================== */
8850 #define BLUE_DEBUGSTATUSREG_SEQERROR_0_Pos                                 (0UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_0 (Bit 0) */
8851 #define BLUE_DEBUGSTATUSREG_SEQERROR_0_Msk                                 (0x00000001UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_0 (Bitfield-Mask: 0x1) */
8852 #define BLUE_DEBUGSTATUSREG_SEQERROR_0                                     BLUE_DEBUGSTATUSREG_SEQERROR_0_Msk
8853 #define BLUE_DEBUGSTATUSREG_SEQERROR_1_Pos                                 (1UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_1 (Bit 1) */
8854 #define BLUE_DEBUGSTATUSREG_SEQERROR_1_Msk                                 (0x00000002UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_1 (Bitfield-Mask: 0x1) */
8855 #define BLUE_DEBUGSTATUSREG_SEQERROR_1                                     BLUE_DEBUGSTATUSREG_SEQERROR_1_Msk
8856 #define BLUE_DEBUGSTATUSREG_SEQERROR_2_Pos                                 (2UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_2 (Bit 2) */
8857 #define BLUE_DEBUGSTATUSREG_SEQERROR_2_Msk                                 (0x00000004UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_2 (Bitfield-Mask: 0x1) */
8858 #define BLUE_DEBUGSTATUSREG_SEQERROR_2                                     BLUE_DEBUGSTATUSREG_SEQERROR_2_Msk
8859 #define BLUE_DEBUGSTATUSREG_SEQERROR_3_Pos                                 (3UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_3 (Bit 3) */
8860 #define BLUE_DEBUGSTATUSREG_SEQERROR_3_Msk                                 (0x00000008UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_3 (Bitfield-Mask: 0x1) */
8861 #define BLUE_DEBUGSTATUSREG_SEQERROR_3                                     BLUE_DEBUGSTATUSREG_SEQERROR_3_Msk
8862 #define BLUE_DEBUGSTATUSREG_SEQERROR_4_Pos                                 (4UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_4 (Bit 4) */
8863 #define BLUE_DEBUGSTATUSREG_SEQERROR_4_Msk                                 (0x00000010UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_4 (Bitfield-Mask: 0x1) */
8864 #define BLUE_DEBUGSTATUSREG_SEQERROR_4                                     BLUE_DEBUGSTATUSREG_SEQERROR_4_Msk
8865 #define BLUE_DEBUGSTATUSREG_SEQERROR_5_Pos                                 (5UL)   /*!< BLUE DEBUGSTATUSREG: SEQERROR_5 (Bit 5) */
8866 #define BLUE_DEBUGSTATUSREG_SEQERROR_5_Msk                                 (0x00000020UL)  /*!< BLUE DEBUGSTATUSREG: SEQERROR_5 (Bitfield-Mask: 0x1) */
8867 #define BLUE_DEBUGSTATUSREG_SEQERROR_5                                     BLUE_DEBUGSTATUSREG_SEQERROR_5_Msk
8868 #define BLUE_DEBUGSTATUSREG_AESDBG_0_Pos                                   (16UL)   /*!< BLUE DEBUGSTATUSREG: AESDBG_0 (Bit 16) */
8869 #define BLUE_DEBUGSTATUSREG_AESDBG_0_Msk                                   (0x00010000UL)  /*!< BLUE DEBUGSTATUSREG: AESDBG_0 (Bitfield-Mask: 0x1) */
8870 #define BLUE_DEBUGSTATUSREG_AESDBG_0                                       BLUE_DEBUGSTATUSREG_AESDBG_0_Msk
8871 #define BLUE_DEBUGSTATUSREG_AESDBG_1_Pos                                   (17UL)   /*!< BLUE DEBUGSTATUSREG: AESDBG_1 (Bit 17) */
8872 #define BLUE_DEBUGSTATUSREG_AESDBG_1_Msk                                   (0x00020000UL)  /*!< BLUE DEBUGSTATUSREG: AESDBG_1 (Bitfield-Mask: 0x1) */
8873 #define BLUE_DEBUGSTATUSREG_AESDBG_1                                       BLUE_DEBUGSTATUSREG_AESDBG_1_Msk
8874 #define BLUE_DEBUGSTATUSREG_AESDBG_2_Pos                                   (18UL)   /*!< BLUE DEBUGSTATUSREG: AESDBG_2 (Bit 18) */
8875 #define BLUE_DEBUGSTATUSREG_AESDBG_2_Msk                                   (0x00040000UL)  /*!< BLUE DEBUGSTATUSREG: AESDBG_2 (Bitfield-Mask: 0x1) */
8876 #define BLUE_DEBUGSTATUSREG_AESDBG_2                                       BLUE_DEBUGSTATUSREG_AESDBG_2_Msk
8877 #define BLUE_DEBUGSTATUSREG_AESDBG_3_Pos                                   (19UL)   /*!< BLUE DEBUGSTATUSREG: AESDBG_3 (Bit 19) */
8878 #define BLUE_DEBUGSTATUSREG_AESDBG_3_Msk                                   (0x00080000UL)  /*!< BLUE DEBUGSTATUSREG: AESDBG_3 (Bitfield-Mask: 0x1) */
8879 #define BLUE_DEBUGSTATUSREG_AESDBG_3                                       BLUE_DEBUGSTATUSREG_AESDBG_3_Msk
8880 
8881 
8882 /* =========================================================================================================================== */
8883 /* ================                                     WAKEUP                                                ================ */
8884 /* =========================================================================================================================== */
8885 
8886 
8887 /* ===============================================   WAKEUP_BLOCK_VERSION   =============================================== */
8888 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos                        (0UL)   /*!< WAKEUP WAKEUP_BLOCK_VERSION: SUB_VERSION (Bit 0) */
8889 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Msk                        (0x000000ffUL)  /*!< WAKEUP WAKEUP_BLOCK_VERSION: SUB_VERSION (Bitfield-Mask: 0xff) */
8890 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION                            WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Msk
8891 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_0                          (0x01 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000001 */
8892 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_1                          (0x02 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000002 */
8893 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_2                          (0x04 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000004 */
8894 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_3                          (0x08 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000008 */
8895 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_4                          (0x10 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000010 */
8896 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_5                          (0x20 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000020 */
8897 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_6                          (0x40 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000040 */
8898 #define WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_7                          (0x80 << WAKEUP_WAKEUP_BLOCK_VERSION_SUB_VERSION_Pos)   /*!<0x00000080 */
8899 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos                     (8UL)   /*!< WAKEUP WAKEUP_BLOCK_VERSION: VERSION_NUMBER (Bit 8) */
8900 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Msk                     (0x0000ff00UL)  /*!< WAKEUP WAKEUP_BLOCK_VERSION: VERSION_NUMBER (Bitfield-Mask: 0xff) */
8901 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER                         WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Msk
8902 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_0                       (0x01 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00000100 */
8903 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_1                       (0x02 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00000200 */
8904 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_2                       (0x04 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00000400 */
8905 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_3                       (0x08 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00000800 */
8906 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_4                       (0x10 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00001000 */
8907 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_5                       (0x20 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00002000 */
8908 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_6                       (0x40 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00004000 */
8909 #define WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_7                       (0x80 << WAKEUP_WAKEUP_BLOCK_VERSION_VERSION_NUMBER_Pos)   /*!<0x00008000 */
8910 
8911 /* ===============================================   WAKEUP_OFFSET_1   =============================================== */
8912 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos                                   (0UL)   /*!< WAKEUP WAKEUP_OFFSET_1: MODE0 (Bit 0) */
8913 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_Msk                                   (0x000000ffUL)  /*!< WAKEUP WAKEUP_OFFSET_1: MODE0 (Bitfield-Mask: 0xff) */
8914 #define WAKEUP_WAKEUP_OFFSET_1_MODE0                                       WAKEUP_WAKEUP_OFFSET_1_MODE0_Msk
8915 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000001 */
8916 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000002 */
8917 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000004 */
8918 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000008 */
8919 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000010 */
8920 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000020 */
8921 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000040 */
8922 #define WAKEUP_WAKEUP_OFFSET_1_MODE0_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_1_MODE0_Pos)   /*!<0x00000080 */
8923 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos                                   (8UL)   /*!< WAKEUP WAKEUP_OFFSET_1: MODE1 (Bit 8) */
8924 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_Msk                                   (0x0000ff00UL)  /*!< WAKEUP WAKEUP_OFFSET_1: MODE1 (Bitfield-Mask: 0xff) */
8925 #define WAKEUP_WAKEUP_OFFSET_1_MODE1                                       WAKEUP_WAKEUP_OFFSET_1_MODE1_Msk
8926 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00000100 */
8927 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00000200 */
8928 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00000400 */
8929 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00000800 */
8930 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00001000 */
8931 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00002000 */
8932 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00004000 */
8933 #define WAKEUP_WAKEUP_OFFSET_1_MODE1_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_1_MODE1_Pos)   /*!<0x00008000 */
8934 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos                                   (16UL)   /*!< WAKEUP WAKEUP_OFFSET_1: MODE2 (Bit 16) */
8935 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_Msk                                   (0x00ff0000UL)  /*!< WAKEUP WAKEUP_OFFSET_1: MODE2 (Bitfield-Mask: 0xff) */
8936 #define WAKEUP_WAKEUP_OFFSET_1_MODE2                                       WAKEUP_WAKEUP_OFFSET_1_MODE2_Msk
8937 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00010000 */
8938 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00020000 */
8939 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00040000 */
8940 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00080000 */
8941 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00100000 */
8942 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00200000 */
8943 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00400000 */
8944 #define WAKEUP_WAKEUP_OFFSET_1_MODE2_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_1_MODE2_Pos)   /*!<0x00800000 */
8945 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos                                   (24UL)   /*!< WAKEUP WAKEUP_OFFSET_1: MODE3 (Bit 24) */
8946 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_Msk                                   (0xff000000UL)  /*!< WAKEUP WAKEUP_OFFSET_1: MODE3 (Bitfield-Mask: 0xff) */
8947 #define WAKEUP_WAKEUP_OFFSET_1_MODE3                                       WAKEUP_WAKEUP_OFFSET_1_MODE3_Msk
8948 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x01000000 */
8949 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x02000000 */
8950 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x04000000 */
8951 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x08000000 */
8952 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x10000000 */
8953 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x20000000 */
8954 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x40000000 */
8955 #define WAKEUP_WAKEUP_OFFSET_1_MODE3_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_1_MODE3_Pos)   /*!<0x80000000 */
8956 
8957 /* ===============================================   WAKEUP_OFFSET_2   =============================================== */
8958 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos                                   (0UL)   /*!< WAKEUP WAKEUP_OFFSET_2: MODE4 (Bit 0) */
8959 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_Msk                                   (0x000000ffUL)  /*!< WAKEUP WAKEUP_OFFSET_2: MODE4 (Bitfield-Mask: 0xff) */
8960 #define WAKEUP_WAKEUP_OFFSET_2_MODE4                                       WAKEUP_WAKEUP_OFFSET_2_MODE4_Msk
8961 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000001 */
8962 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000002 */
8963 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000004 */
8964 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000008 */
8965 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000010 */
8966 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000020 */
8967 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000040 */
8968 #define WAKEUP_WAKEUP_OFFSET_2_MODE4_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_2_MODE4_Pos)   /*!<0x00000080 */
8969 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos                                   (8UL)   /*!< WAKEUP WAKEUP_OFFSET_2: MODE5 (Bit 8) */
8970 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_Msk                                   (0x0000ff00UL)  /*!< WAKEUP WAKEUP_OFFSET_2: MODE5 (Bitfield-Mask: 0xff) */
8971 #define WAKEUP_WAKEUP_OFFSET_2_MODE5                                       WAKEUP_WAKEUP_OFFSET_2_MODE5_Msk
8972 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00000100 */
8973 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00000200 */
8974 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00000400 */
8975 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00000800 */
8976 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00001000 */
8977 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00002000 */
8978 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00004000 */
8979 #define WAKEUP_WAKEUP_OFFSET_2_MODE5_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_2_MODE5_Pos)   /*!<0x00008000 */
8980 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos                                   (16UL)   /*!< WAKEUP WAKEUP_OFFSET_2: MODE6 (Bit 16) */
8981 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_Msk                                   (0x00ff0000UL)  /*!< WAKEUP WAKEUP_OFFSET_2: MODE6 (Bitfield-Mask: 0xff) */
8982 #define WAKEUP_WAKEUP_OFFSET_2_MODE6                                       WAKEUP_WAKEUP_OFFSET_2_MODE6_Msk
8983 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00010000 */
8984 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00020000 */
8985 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00040000 */
8986 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00080000 */
8987 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00100000 */
8988 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00200000 */
8989 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00400000 */
8990 #define WAKEUP_WAKEUP_OFFSET_2_MODE6_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_2_MODE6_Pos)   /*!<0x00800000 */
8991 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos                                   (24UL)   /*!< WAKEUP WAKEUP_OFFSET_2: MODE7 (Bit 24) */
8992 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_Msk                                   (0xff000000UL)  /*!< WAKEUP WAKEUP_OFFSET_2: MODE7 (Bitfield-Mask: 0xff) */
8993 #define WAKEUP_WAKEUP_OFFSET_2_MODE7                                       WAKEUP_WAKEUP_OFFSET_2_MODE7_Msk
8994 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_0                                     (0x01 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x01000000 */
8995 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_1                                     (0x02 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x02000000 */
8996 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_2                                     (0x04 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x04000000 */
8997 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_3                                     (0x08 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x08000000 */
8998 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_4                                     (0x10 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x10000000 */
8999 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_5                                     (0x20 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x20000000 */
9000 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_6                                     (0x40 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x40000000 */
9001 #define WAKEUP_WAKEUP_OFFSET_2_MODE7_7                                     (0x80 << WAKEUP_WAKEUP_OFFSET_2_MODE7_Pos)   /*!<0x80000000 */
9002 
9003 /* ===============================================   ABSOLUTE_TIME   =============================================== */
9004 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos                             (0UL)   /*!< WAKEUP ABSOLUTE_TIME: ABSOLUTE_TIME (Bit 0) */
9005 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Msk                             (0xffffffffUL)  /*!< WAKEUP ABSOLUTE_TIME: ABSOLUTE_TIME (Bitfield-Mask: 0xffffffffL) */
9006 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME                                 WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Msk
9007 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_0                               (0x00000001 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000001 */
9008 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_1                               (0x00000002 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000002 */
9009 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_2                               (0x00000004 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000004 */
9010 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_3                               (0x00000008 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000008 */
9011 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_4                               (0x00000010 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000010 */
9012 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_5                               (0x00000020 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000020 */
9013 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_6                               (0x00000040 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000040 */
9014 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_7                               (0x00000080 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000080 */
9015 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_8                               (0x00000100 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000100 */
9016 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_9                               (0x00000200 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000200 */
9017 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_10                              (0x00000400 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000400 */
9018 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_11                              (0x00000800 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00000800 */
9019 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_12                              (0x00001000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00001000 */
9020 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_13                              (0x00002000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00002000 */
9021 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_14                              (0x00004000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00004000 */
9022 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_15                              (0x00008000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00008000 */
9023 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_16                              (0x00010000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00010000 */
9024 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_17                              (0x00020000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00020000 */
9025 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_18                              (0x00040000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00040000 */
9026 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_19                              (0x00080000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00080000 */
9027 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_20                              (0x00100000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00100000 */
9028 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_21                              (0x00200000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00200000 */
9029 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_22                              (0x00400000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00400000 */
9030 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_23                              (0x00800000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x00800000 */
9031 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_24                              (0x01000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x01000000 */
9032 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_25                              (0x02000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x02000000 */
9033 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_26                              (0x04000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x04000000 */
9034 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_27                              (0x08000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x08000000 */
9035 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_28                              (0x10000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x10000000 */
9036 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_29                              (0x20000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x20000000 */
9037 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_30                              (0x40000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x40000000 */
9038 #define WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_31                              (0x80000000 << WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos)   /*!<0x80000000 */
9039 
9040 /* ===============================================   MINIMUM_PERIOD_LENGTH   =============================================== */
9041 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos                            (4UL)   /*!< WAKEUP MINIMUM_PERIOD_LENGTH: LENGTH (Bit 4) */
9042 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Msk                            (0x00003ff0UL)  /*!< WAKEUP MINIMUM_PERIOD_LENGTH: LENGTH (Bitfield-Mask: 0x3ff) */
9043 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH                                WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Msk
9044 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_0                              (0x01 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000010 */
9045 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_1                              (0x02 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000020 */
9046 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_2                              (0x04 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000040 */
9047 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_3                              (0x08 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000080 */
9048 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_4                              (0x10 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000100 */
9049 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_5                              (0x20 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000200 */
9050 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_6                              (0x40 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000400 */
9051 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_7                              (0x80 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000800 */
9052 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_8                              (0x100 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00001000 */
9053 #define WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_9                              (0x200 << WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00002000 */
9054 
9055 /* ===============================================   AVERAGE_PERIOD_LENGTH   =============================================== */
9056 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos                      (0UL)   /*!< WAKEUP AVERAGE_PERIOD_LENGTH: LENGTH_FRACT (Bit 0) */
9057 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Msk                      (0x0000000fUL)  /*!< WAKEUP AVERAGE_PERIOD_LENGTH: LENGTH_FRACT (Bitfield-Mask: 0xf) */
9058 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT                          WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Msk
9059 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_0                        (0x1 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos)   /*!<0x00000001 */
9060 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_1                        (0x2 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos)   /*!<0x00000002 */
9061 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_2                        (0x4 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos)   /*!<0x00000004 */
9062 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_3                        (0x8 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos)   /*!<0x00000008 */
9063 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos                        (4UL)   /*!< WAKEUP AVERAGE_PERIOD_LENGTH: LENGTH_INT (Bit 4) */
9064 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Msk                        (0x00003ff0UL)  /*!< WAKEUP AVERAGE_PERIOD_LENGTH: LENGTH_INT (Bitfield-Mask: 0x3ff) */
9065 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT                            WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Msk
9066 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_0                          (0x01 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000010 */
9067 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_1                          (0x02 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000020 */
9068 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_2                          (0x04 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000040 */
9069 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_3                          (0x08 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000080 */
9070 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_4                          (0x10 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000100 */
9071 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_5                          (0x20 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000200 */
9072 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_6                          (0x40 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000400 */
9073 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_7                          (0x80 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00000800 */
9074 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_8                          (0x100 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00001000 */
9075 #define WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_9                          (0x200 << WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos)   /*!<0x00002000 */
9076 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos                     (24UL)   /*!< WAKEUP AVERAGE_PERIOD_LENGTH: AVERAGE_COUNT (Bit 24) */
9077 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Msk                     (0xff000000UL)  /*!< WAKEUP AVERAGE_PERIOD_LENGTH: AVERAGE_COUNT (Bitfield-Mask: 0xff) */
9078 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT                         WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Msk
9079 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_0                       (0x01 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x01000000 */
9080 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_1                       (0x02 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x02000000 */
9081 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_2                       (0x04 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x04000000 */
9082 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_3                       (0x08 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x08000000 */
9083 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_4                       (0x10 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x10000000 */
9084 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_5                       (0x20 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x20000000 */
9085 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_6                       (0x40 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x40000000 */
9086 #define WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_7                       (0x80 << WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos)   /*!<0x80000000 */
9087 
9088 /* ===============================================   MAXIMUM_PERIOD_LENGTH   =============================================== */
9089 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos                            (4UL)   /*!< WAKEUP MAXIMUM_PERIOD_LENGTH: LENGTH (Bit 4) */
9090 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Msk                            (0x00003ff0UL)  /*!< WAKEUP MAXIMUM_PERIOD_LENGTH: LENGTH (Bitfield-Mask: 0x3ff) */
9091 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH                                WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Msk
9092 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_0                              (0x01 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000010 */
9093 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_1                              (0x02 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000020 */
9094 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_2                              (0x04 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000040 */
9095 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_3                              (0x08 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000080 */
9096 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_4                              (0x10 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000100 */
9097 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_5                              (0x20 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000200 */
9098 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_6                              (0x40 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000400 */
9099 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_7                              (0x80 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00000800 */
9100 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_8                              (0x100 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00001000 */
9101 #define WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_9                              (0x200 << WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos)   /*!<0x00002000 */
9102 
9103 /* ===============================================   STATISTICS_RESTART   =============================================== */
9104 #define WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX_Pos                          (0UL)   /*!< WAKEUP STATISTICS_RESTART: CLR_MIN_MAX (Bit 0) */
9105 #define WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX_Msk                          (0x00000001UL)  /*!< WAKEUP STATISTICS_RESTART: CLR_MIN_MAX (Bitfield-Mask: 0x1) */
9106 #define WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX                              WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX_Msk
9107 #define WAKEUP_STATISTICS_RESTART_CLR_AVR_Pos                              (1UL)   /*!< WAKEUP STATISTICS_RESTART: CLR_AVR (Bit 1) */
9108 #define WAKEUP_STATISTICS_RESTART_CLR_AVR_Msk                              (0x00000002UL)  /*!< WAKEUP STATISTICS_RESTART: CLR_AVR (Bitfield-Mask: 0x1) */
9109 #define WAKEUP_STATISTICS_RESTART_CLR_AVR                                  WAKEUP_STATISTICS_RESTART_CLR_AVR_Msk
9110 
9111 /* ===============================================   BLUE_WAKEUP_TIME   =============================================== */
9112 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos                            (0UL)   /*!< WAKEUP BLUE_WAKEUP_TIME: WAKEUP_TIME (Bit 0) */
9113 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Msk                            (0xffffffffUL)  /*!< WAKEUP BLUE_WAKEUP_TIME: WAKEUP_TIME (Bitfield-Mask: 0xffffffffL) */
9114 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME                                WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Msk
9115 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_0                              (0x00000001 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000001 */
9116 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_1                              (0x00000002 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000002 */
9117 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_2                              (0x00000004 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000004 */
9118 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_3                              (0x00000008 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000008 */
9119 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_4                              (0x00000010 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000010 */
9120 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_5                              (0x00000020 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000020 */
9121 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_6                              (0x00000040 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000040 */
9122 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_7                              (0x00000080 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000080 */
9123 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_8                              (0x00000100 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000100 */
9124 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_9                              (0x00000200 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000200 */
9125 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_10                             (0x00000400 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000400 */
9126 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_11                             (0x00000800 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000800 */
9127 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_12                             (0x00001000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00001000 */
9128 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_13                             (0x00002000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00002000 */
9129 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_14                             (0x00004000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00004000 */
9130 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_15                             (0x00008000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00008000 */
9131 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_16                             (0x00010000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00010000 */
9132 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_17                             (0x00020000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00020000 */
9133 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_18                             (0x00040000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00040000 */
9134 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_19                             (0x00080000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00080000 */
9135 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_20                             (0x00100000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00100000 */
9136 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_21                             (0x00200000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00200000 */
9137 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_22                             (0x00400000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00400000 */
9138 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_23                             (0x00800000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00800000 */
9139 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_24                             (0x01000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x01000000 */
9140 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_25                             (0x02000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x02000000 */
9141 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_26                             (0x04000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x04000000 */
9142 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_27                             (0x08000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x08000000 */
9143 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_28                             (0x10000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x10000000 */
9144 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_29                             (0x20000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x20000000 */
9145 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_30                             (0x40000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x40000000 */
9146 #define WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_31                             (0x80000000 << WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x80000000 */
9147 
9148 /* ===============================================   BLUE_SLEEP_REQUEST_MODE   =============================================== */
9149 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos                  (0UL)   /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: SLEEP_REQ_MODE (Bit 0) */
9150 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Msk                  (0x00000007UL)  /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: SLEEP_REQ_MODE (Bitfield-Mask: 0x7) */
9151 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE                      WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Msk
9152 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_0                    (0x1 << WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000001 */
9153 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_1                    (0x2 << WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000002 */
9154 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_2                    (0x4 << WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000004 */
9155 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN_Pos                        (29UL)   /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: SLEEP_EN (Bit 29) */
9156 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN_Msk                        (0x20000000UL)  /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: SLEEP_EN (Bitfield-Mask: 0x1) */
9157 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN                            WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN_Msk
9158 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN_Pos                   (30UL)   /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: BLE_WAKEUP_EN (Bit 30) */
9159 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN_Msk                   (0x40000000UL)  /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: BLE_WAKEUP_EN (Bitfield-Mask: 0x1) */
9160 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN                       WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN_Msk
9161 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Pos                  (31UL)   /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: FORCE_SLEEPING (Bit 31) */
9162 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk                  (0x80000000UL)  /*!< WAKEUP BLUE_SLEEP_REQUEST_MODE: FORCE_SLEEPING (Bitfield-Mask: 0x1) */
9163 #define WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING                      WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk
9164 
9165 /* ===============================================   CM0_WAKEUP_TIME   =============================================== */
9166 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos                             (4UL)   /*!< WAKEUP CM0_WAKEUP_TIME: WAKEUP_TIME (Bit 4) */
9167 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Msk                             (0xfffffff0UL)  /*!< WAKEUP CM0_WAKEUP_TIME: WAKEUP_TIME (Bitfield-Mask: 0xfffffff) */
9168 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME                                 WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Msk
9169 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_0                               (0x0000001 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000010 */
9170 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_1                               (0x0000002 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000020 */
9171 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_2                               (0x0000004 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000040 */
9172 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_3                               (0x0000008 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000080 */
9173 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_4                               (0x0000010 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000100 */
9174 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_5                               (0x0000020 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000200 */
9175 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_6                               (0x0000040 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000400 */
9176 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_7                               (0x0000080 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00000800 */
9177 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_8                               (0x0000100 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00001000 */
9178 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_9                               (0x0000200 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00002000 */
9179 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_10                              (0x0000400 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00004000 */
9180 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_11                              (0x0000800 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00008000 */
9181 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_12                              (0x0001000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00010000 */
9182 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_13                              (0x0002000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00020000 */
9183 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_14                              (0x0004000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00040000 */
9184 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_15                              (0x0008000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00080000 */
9185 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_16                              (0x0010000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00100000 */
9186 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_17                              (0x0020000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00200000 */
9187 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_18                              (0x0040000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00400000 */
9188 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_19                              (0x0080000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x00800000 */
9189 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_20                              (0x0100000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x01000000 */
9190 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_21                              (0x0200000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x02000000 */
9191 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_22                              (0x0400000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x04000000 */
9192 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_23                              (0x0800000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x08000000 */
9193 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_24                              (0x1000000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x10000000 */
9194 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_25                              (0x2000000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x20000000 */
9195 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_26                              (0x4000000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x40000000 */
9196 #define WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_27                              (0x8000000 << WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos)   /*!<0x80000000 */
9197 
9198 /* ===============================================   CM0_SLEEP_REQUEST_MODE   =============================================== */
9199 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos                   (0UL)   /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: SLEEP_REQ_MODE (Bit 0) */
9200 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Msk                   (0x00000007UL)  /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: SLEEP_REQ_MODE (Bitfield-Mask: 0x7) */
9201 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE                       WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Msk
9202 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_0                     (0x1 << WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000001 */
9203 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_1                     (0x2 << WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000002 */
9204 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_2                     (0x4 << WAKEUP_CM0_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE_Pos)   /*!<0x00000004 */
9205 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN_Pos                    (30UL)   /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: CPU_WAKEUP_EN (Bit 30) */
9206 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN_Msk                    (0x40000000UL)  /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: CPU_WAKEUP_EN (Bitfield-Mask: 0x1) */
9207 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN                        WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN_Msk
9208 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Pos                   (31UL)   /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: FORCE_SLEEPING (Bit 31) */
9209 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk                   (0x80000000UL)  /*!< WAKEUP CM0_SLEEP_REQUEST_MODE: FORCE_SLEEPING (Bitfield-Mask: 0x1) */
9210 #define WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING                       WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk
9211 
9212 /* ===============================================   WAKEUP_BLE_IRQ_ENABLE   =============================================== */
9213 #define WAKEUP_WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT_Pos                         (0UL)   /*!< WAKEUP WAKEUP_BLE_IRQ_ENABLE: WAKEUP_IT (Bit 0) */
9214 #define WAKEUP_WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT_Msk                         (0x00000001UL)  /*!< WAKEUP WAKEUP_BLE_IRQ_ENABLE: WAKEUP_IT (Bitfield-Mask: 0x1) */
9215 #define WAKEUP_WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT                             WAKEUP_WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT_Msk
9216 
9217 /* ===============================================   WAKEUP_BLE_IRQ_STATUS   =============================================== */
9218 #define WAKEUP_WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT_Pos                         (0UL)   /*!< WAKEUP WAKEUP_BLE_IRQ_STATUS: WAKEUP_IT (Bit 0) */
9219 #define WAKEUP_WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT_Msk                         (0x00000001UL)  /*!< WAKEUP WAKEUP_BLE_IRQ_STATUS: WAKEUP_IT (Bitfield-Mask: 0x1) */
9220 #define WAKEUP_WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT                             WAKEUP_WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT_Msk
9221 
9222 /* ===============================================   WAKEUP_CM0_IRQ_ENABLE   =============================================== */
9223 #define WAKEUP_WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT_Pos                         (0UL)   /*!< WAKEUP WAKEUP_CM0_IRQ_ENABLE: WAKEUP_IT (Bit 0) */
9224 #define WAKEUP_WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT_Msk                         (0x00000001UL)  /*!< WAKEUP WAKEUP_CM0_IRQ_ENABLE: WAKEUP_IT (Bitfield-Mask: 0x1) */
9225 #define WAKEUP_WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT                             WAKEUP_WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT_Msk
9226 
9227 /* ===============================================   WAKEUP_CM0_IRQ_STATUS   =============================================== */
9228 #define WAKEUP_WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT_Pos                         (0UL)   /*!< WAKEUP WAKEUP_CM0_IRQ_STATUS: WAKEUP_IT (Bit 0) */
9229 #define WAKEUP_WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT_Msk                         (0x00000001UL)  /*!< WAKEUP WAKEUP_CM0_IRQ_STATUS: WAKEUP_IT (Bitfield-Mask: 0x1) */
9230 #define WAKEUP_WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT                             WAKEUP_WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT_Msk
9231 
9232 
9233 /* =========================================================================================================================== */
9234 /* ================                                     RADIO_CTRL                                            ================ */
9235 /* =========================================================================================================================== */
9236 
9237 
9238 /* ===============================================   RADIO_CONTROL_ID   =============================================== */
9239 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos                     (0UL)   /*!< RADIO_CTRL RADIO_CONTROL_ID: IDENTIFICATION (Bit 0) */
9240 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Msk                     (0xffffffffUL)  /*!< RADIO_CTRL RADIO_CONTROL_ID: IDENTIFICATION (Bitfield-Mask: 0xffffffffL) */
9241 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION                         RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Msk
9242 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_0                       (0x00000001 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000001 */
9243 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_1                       (0x00000002 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000002 */
9244 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_2                       (0x00000004 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000004 */
9245 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_3                       (0x00000008 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000008 */
9246 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_4                       (0x00000010 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000010 */
9247 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_5                       (0x00000020 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000020 */
9248 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_6                       (0x00000040 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000040 */
9249 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_7                       (0x00000080 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000080 */
9250 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_8                       (0x00000100 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000100 */
9251 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_9                       (0x00000200 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000200 */
9252 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_10                      (0x00000400 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000400 */
9253 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_11                      (0x00000800 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00000800 */
9254 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_12                      (0x00001000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00001000 */
9255 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_13                      (0x00002000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00002000 */
9256 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_14                      (0x00004000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00004000 */
9257 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_15                      (0x00008000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00008000 */
9258 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_16                      (0x00010000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00010000 */
9259 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_17                      (0x00020000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00020000 */
9260 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_18                      (0x00040000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00040000 */
9261 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_19                      (0x00080000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00080000 */
9262 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_20                      (0x00100000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00100000 */
9263 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_21                      (0x00200000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00200000 */
9264 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_22                      (0x00400000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00400000 */
9265 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_23                      (0x00800000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x00800000 */
9266 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_24                      (0x01000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x01000000 */
9267 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_25                      (0x02000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x02000000 */
9268 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_26                      (0x04000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x04000000 */
9269 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_27                      (0x08000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x08000000 */
9270 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_28                      (0x10000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x10000000 */
9271 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_29                      (0x20000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x20000000 */
9272 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_30                      (0x40000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x40000000 */
9273 #define RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_31                      (0x80000000 << RADIO_CTRL_RADIO_CONTROL_ID_IDENTIFICATION_Pos)   /*!<0x80000000 */
9274 
9275 /* ===============================================   CLK32COUNT_REG   =============================================== */
9276 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos                           (0UL)   /*!< RADIO_CTRL CLK32COUNT_REG: SLOW_COUNT (Bit 0) */
9277 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Msk                           (0x000001ffUL)  /*!< RADIO_CTRL CLK32COUNT_REG: SLOW_COUNT (Bitfield-Mask: 0x1ff) */
9278 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT                               RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Msk
9279 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_0                             (0x01 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000001 */
9280 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_1                             (0x02 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000002 */
9281 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_2                             (0x04 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000004 */
9282 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_3                             (0x08 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000008 */
9283 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_4                             (0x10 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000010 */
9284 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_5                             (0x20 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000020 */
9285 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_6                             (0x40 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000040 */
9286 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_7                             (0x80 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000080 */
9287 #define RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_8                             (0x100 << RADIO_CTRL_CLK32COUNT_REG_SLOW_COUNT_Pos)   /*!<0x00000100 */
9288 
9289 /* ===============================================   CLK32PERIOD_REG   =============================================== */
9290 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos                         (0UL)   /*!< RADIO_CTRL CLK32PERIOD_REG: SLOW_PERIOD (Bit 0) */
9291 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Msk                         (0x0007ffffUL)  /*!< RADIO_CTRL CLK32PERIOD_REG: SLOW_PERIOD (Bitfield-Mask: 0x7ffff) */
9292 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD                             RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Msk
9293 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_0                           (0x0001 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000001 */
9294 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_1                           (0x0002 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000002 */
9295 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_2                           (0x0004 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000004 */
9296 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_3                           (0x0008 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000008 */
9297 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_4                           (0x0010 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000010 */
9298 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_5                           (0x0020 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000020 */
9299 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_6                           (0x0040 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000040 */
9300 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_7                           (0x0080 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000080 */
9301 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_8                           (0x0100 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000100 */
9302 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_9                           (0x0200 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000200 */
9303 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_10                          (0x0400 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000400 */
9304 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_11                          (0x0800 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00000800 */
9305 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_12                          (0x1000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00001000 */
9306 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_13                          (0x2000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00002000 */
9307 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_14                          (0x4000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00004000 */
9308 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_15                          (0x8000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00008000 */
9309 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_16                          (0x10000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00010000 */
9310 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_17                          (0x20000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00020000 */
9311 #define RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_18                          (0x40000 << RADIO_CTRL_CLK32PERIOD_REG_SLOW_PERIOD_Pos)   /*!<0x00040000 */
9312 
9313 /* ===============================================   CLK32FREQUENCY_REG   =============================================== */
9314 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos                   (0UL)   /*!< RADIO_CTRL CLK32FREQUENCY_REG: SLOW_FREQUENCY (Bit 0) */
9315 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Msk                   (0x07ffffffUL)  /*!< RADIO_CTRL CLK32FREQUENCY_REG: SLOW_FREQUENCY (Bitfield-Mask: 0x7ffffff) */
9316 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY                       RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Msk
9317 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_0                     (0x000001 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000001 */
9318 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_1                     (0x000002 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000002 */
9319 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_2                     (0x000004 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000004 */
9320 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_3                     (0x000008 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000008 */
9321 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_4                     (0x000010 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000010 */
9322 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_5                     (0x000020 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000020 */
9323 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_6                     (0x000040 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000040 */
9324 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_7                     (0x000080 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000080 */
9325 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_8                     (0x000100 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000100 */
9326 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_9                     (0x000200 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000200 */
9327 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_10                    (0x000400 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000400 */
9328 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_11                    (0x000800 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00000800 */
9329 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_12                    (0x001000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00001000 */
9330 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_13                    (0x002000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00002000 */
9331 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_14                    (0x004000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00004000 */
9332 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_15                    (0x008000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00008000 */
9333 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_16                    (0x010000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00010000 */
9334 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_17                    (0x020000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00020000 */
9335 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_18                    (0x040000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00040000 */
9336 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_19                    (0x080000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00080000 */
9337 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_20                    (0x100000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00100000 */
9338 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_21                    (0x200000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00200000 */
9339 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_22                    (0x400000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00400000 */
9340 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_23                    (0x800000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x00800000 */
9341 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_24                    (0x1000000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x01000000 */
9342 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_25                    (0x2000000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x02000000 */
9343 #define RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_26                    (0x4000000 << RADIO_CTRL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos)   /*!<0x04000000 */
9344 
9345 /* ===============================================   RADIO_CONTROL_IRQ_STATUS   =============================================== */
9346 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ_Pos                (0UL)   /*!< RADIO_CTRL RADIO_CONTROL_IRQ_STATUS: SLOW_CLK_IRQ (Bit 0) */
9347 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ_Msk                (0x00000001UL)  /*!< RADIO_CTRL RADIO_CONTROL_IRQ_STATUS: SLOW_CLK_IRQ (Bitfield-Mask: 0x1) */
9348 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ                    RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ_Msk
9349 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos              (8UL)   /*!< RADIO_CTRL RADIO_CONTROL_IRQ_STATUS: RADIO_FSM_IRQ (Bit 8) */
9350 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Msk              (0x00003f00UL)  /*!< RADIO_CTRL RADIO_CONTROL_IRQ_STATUS: RADIO_FSM_IRQ (Bitfield-Mask: 0x3f) */
9351 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ                  RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Msk
9352 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_0                (0x1 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00000100 */
9353 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_1                (0x2 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00000200 */
9354 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_2                (0x4 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00000400 */
9355 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_3                (0x8 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00000800 */
9356 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_4                (0x10 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00001000 */
9357 #define RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_5                (0x20 << RADIO_CTRL_RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos)   /*!<0x00002000 */
9358 
9359 /* ===============================================   RADIO_CONTROL_IRQ_ENABLE   =============================================== */
9360 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK_Pos          (0UL)   /*!< RADIO_CTRL RADIO_CONTROL_IRQ_ENABLE: SLOW_CLK_IRQ_MASK (Bit 0) */
9361 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK_Msk          (0x00000001UL)  /*!< RADIO_CTRL RADIO_CONTROL_IRQ_ENABLE: SLOW_CLK_IRQ_MASK (Bitfield-Mask: 0x1) */
9362 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK              RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK_Msk
9363 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos         (8UL)   /*!< RADIO_CTRL RADIO_CONTROL_IRQ_ENABLE: RADIO_FSM_IRQ_MASK (Bit 8) */
9364 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Msk         (0x00003f00UL)  /*!< RADIO_CTRL RADIO_CONTROL_IRQ_ENABLE: RADIO_FSM_IRQ_MASK (Bitfield-Mask: 0x3f) */
9365 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK             RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Msk
9366 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_0           (0x1 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00000100 */
9367 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_1           (0x2 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00000200 */
9368 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_2           (0x4 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00000400 */
9369 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_3           (0x8 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00000800 */
9370 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_4           (0x10 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00001000 */
9371 #define RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_5           (0x20 << RADIO_CTRL_RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos)   /*!<0x00002000 */
9372 
9373 
9374 /* =========================================================================================================================== */
9375 /* ================                                     RRM                                                   ================ */
9376 /* =========================================================================================================================== */
9377 
9378 
9379 /* ===============================================   RRM_ID   =============================================== */
9380 #define RRM_RRM_ID_IDENTIFICATION_Pos                                      (0UL)   /*!< RRM RRM_ID: IDENTIFICATION (Bit 0) */
9381 #define RRM_RRM_ID_IDENTIFICATION_Msk                                      (0x0000000fUL)  /*!< RRM RRM_ID: IDENTIFICATION (Bitfield-Mask: 0xf) */
9382 #define RRM_RRM_ID_IDENTIFICATION                                          RRM_RRM_ID_IDENTIFICATION_Msk
9383 #define RRM_RRM_ID_IDENTIFICATION_0                                        (0x1 << RRM_RRM_ID_IDENTIFICATION_Pos)   /*!<0x00000001 */
9384 #define RRM_RRM_ID_IDENTIFICATION_1                                        (0x2 << RRM_RRM_ID_IDENTIFICATION_Pos)   /*!<0x00000002 */
9385 #define RRM_RRM_ID_IDENTIFICATION_2                                        (0x4 << RRM_RRM_ID_IDENTIFICATION_Pos)   /*!<0x00000004 */
9386 #define RRM_RRM_ID_IDENTIFICATION_3                                        (0x8 << RRM_RRM_ID_IDENTIFICATION_Pos)   /*!<0x00000008 */
9387 
9388 /* ===============================================   RRM_CTRL   =============================================== */
9389 #define RRM_RRM_CTRL_PRIORITY_Pos                                          (0UL)   /*!< RRM RRM_CTRL: PRIORITY (Bit 0) */
9390 #define RRM_RRM_CTRL_PRIORITY_Msk                                          (0x00000003UL)  /*!< RRM RRM_CTRL: PRIORITY (Bitfield-Mask: 0x3) */
9391 #define RRM_RRM_CTRL_PRIORITY                                              RRM_RRM_CTRL_PRIORITY_Msk
9392 #define RRM_RRM_CTRL_PRIORITY_0                                            (0x1 << RRM_RRM_CTRL_PRIORITY_Pos)   /*!<0x00000001 */
9393 #define RRM_RRM_CTRL_PRIORITY_1                                            (0x2 << RRM_RRM_CTRL_PRIORITY_Pos)   /*!<0x00000002 */
9394 
9395 /* ===============================================   UDRA_CTRL0   =============================================== */
9396 #define RRM_UDRA_CTRL0_RELOAD_RDCFGPTR_Pos                                 (0UL)   /*!< RRM UDRA_CTRL0: RELOAD_RDCFGPTR (Bit 0) */
9397 #define RRM_UDRA_CTRL0_RELOAD_RDCFGPTR_Msk                                 (0x00000001UL)  /*!< RRM UDRA_CTRL0: RELOAD_RDCFGPTR (Bitfield-Mask: 0x1) */
9398 #define RRM_UDRA_CTRL0_RELOAD_RDCFGPTR                                     RRM_UDRA_CTRL0_RELOAD_RDCFGPTR_Msk
9399 
9400 /* ===============================================   UDRA_IRQ_ENABLE   =============================================== */
9401 #define RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED_Pos                     (0UL)   /*!< RRM UDRA_IRQ_ENABLE: RADIO_CFG_PTR_RELOADED (Bit 0) */
9402 #define RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED_Msk                     (0x00000001UL)  /*!< RRM UDRA_IRQ_ENABLE: RADIO_CFG_PTR_RELOADED (Bitfield-Mask: 0x1) */
9403 #define RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED                         RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED_Msk
9404 #define RRM_UDRA_IRQ_ENABLE_CMD_START_Pos                                  (1UL)   /*!< RRM UDRA_IRQ_ENABLE: CMD_START (Bit 1) */
9405 #define RRM_UDRA_IRQ_ENABLE_CMD_START_Msk                                  (0x00000002UL)  /*!< RRM UDRA_IRQ_ENABLE: CMD_START (Bitfield-Mask: 0x1) */
9406 #define RRM_UDRA_IRQ_ENABLE_CMD_START                                      RRM_UDRA_IRQ_ENABLE_CMD_START_Msk
9407 #define RRM_UDRA_IRQ_ENABLE_CMD_END_Pos                                    (2UL)   /*!< RRM UDRA_IRQ_ENABLE: CMD_END (Bit 2) */
9408 #define RRM_UDRA_IRQ_ENABLE_CMD_END_Msk                                    (0x00000004UL)  /*!< RRM UDRA_IRQ_ENABLE: CMD_END (Bitfield-Mask: 0x1) */
9409 #define RRM_UDRA_IRQ_ENABLE_CMD_END                                        RRM_UDRA_IRQ_ENABLE_CMD_END_Msk
9410 #define RRM_UDRA_IRQ_ENABLE_CMD_NUMBER_ERROR_Pos                           (3UL)   /*!< RRM UDRA_IRQ_ENABLE: CMD_NUMBER_ERROR (Bit 3) */
9411 #define RRM_UDRA_IRQ_ENABLE_CMD_NUMBER_ERROR_Msk                           (0x00000008UL)  /*!< RRM UDRA_IRQ_ENABLE: CMD_NUMBER_ERROR (Bitfield-Mask: 0x1) */
9412 #define RRM_UDRA_IRQ_ENABLE_CMD_NUMBER_ERROR                               RRM_UDRA_IRQ_ENABLE_CMD_NUMBER_ERROR_Msk
9413 
9414 /* ===============================================   UDRA_IRQ_STATUS   =============================================== */
9415 #define RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED_Pos                     (0UL)   /*!< RRM UDRA_IRQ_STATUS: RADIO_CFG_PTR_RELOADED (Bit 0) */
9416 #define RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED_Msk                     (0x00000001UL)  /*!< RRM UDRA_IRQ_STATUS: RADIO_CFG_PTR_RELOADED (Bitfield-Mask: 0x1) */
9417 #define RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED                         RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED_Msk
9418 #define RRM_UDRA_IRQ_STATUS_CMD_START_Pos                                  (1UL)   /*!< RRM UDRA_IRQ_STATUS: CMD_START (Bit 1) */
9419 #define RRM_UDRA_IRQ_STATUS_CMD_START_Msk                                  (0x00000002UL)  /*!< RRM UDRA_IRQ_STATUS: CMD_START (Bitfield-Mask: 0x1) */
9420 #define RRM_UDRA_IRQ_STATUS_CMD_START                                      RRM_UDRA_IRQ_STATUS_CMD_START_Msk
9421 #define RRM_UDRA_IRQ_STATUS_CMD_END_Pos                                    (2UL)   /*!< RRM UDRA_IRQ_STATUS: CMD_END (Bit 2) */
9422 #define RRM_UDRA_IRQ_STATUS_CMD_END_Msk                                    (0x00000004UL)  /*!< RRM UDRA_IRQ_STATUS: CMD_END (Bitfield-Mask: 0x1) */
9423 #define RRM_UDRA_IRQ_STATUS_CMD_END                                        RRM_UDRA_IRQ_STATUS_CMD_END_Msk
9424 #define RRM_UDRA_IRQ_STATUS_CMD_NUMBER_ERROR_Pos                           (3UL)   /*!< RRM UDRA_IRQ_STATUS: CMD_NUMBER_ERROR (Bit 3) */
9425 #define RRM_UDRA_IRQ_STATUS_CMD_NUMBER_ERROR_Msk                           (0x00000008UL)  /*!< RRM UDRA_IRQ_STATUS: CMD_NUMBER_ERROR (Bitfield-Mask: 0x1) */
9426 #define RRM_UDRA_IRQ_STATUS_CMD_NUMBER_ERROR                               RRM_UDRA_IRQ_STATUS_CMD_NUMBER_ERROR_Msk
9427 
9428 /* ===============================================   UDRA_RADIO_CFG_PTR   =============================================== */
9429 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos                    (0UL)   /*!< RRM UDRA_RADIO_CFG_PTR: RADIO_CONFIG_ADDRESS (Bit 0) */
9430 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Msk                    (0xffffffffUL)  /*!< RRM UDRA_RADIO_CFG_PTR: RADIO_CONFIG_ADDRESS (Bitfield-Mask: 0xffffffffL) */
9431 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS                        RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Msk
9432 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_0                      (0x00000001 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000001 */
9433 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_1                      (0x00000002 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000002 */
9434 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_2                      (0x00000004 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000004 */
9435 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_3                      (0x00000008 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000008 */
9436 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_4                      (0x00000010 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000010 */
9437 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_5                      (0x00000020 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000020 */
9438 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_6                      (0x00000040 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000040 */
9439 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_7                      (0x00000080 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000080 */
9440 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_8                      (0x00000100 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000100 */
9441 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_9                      (0x00000200 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000200 */
9442 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_10                     (0x00000400 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000400 */
9443 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_11                     (0x00000800 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00000800 */
9444 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_12                     (0x00001000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00001000 */
9445 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_13                     (0x00002000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00002000 */
9446 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_14                     (0x00004000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00004000 */
9447 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_15                     (0x00008000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00008000 */
9448 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_16                     (0x00010000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00010000 */
9449 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_17                     (0x00020000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00020000 */
9450 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_18                     (0x00040000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00040000 */
9451 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_19                     (0x00080000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00080000 */
9452 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_20                     (0x00100000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00100000 */
9453 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_21                     (0x00200000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00200000 */
9454 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_22                     (0x00400000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00400000 */
9455 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_23                     (0x00800000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x00800000 */
9456 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_24                     (0x01000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x01000000 */
9457 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_25                     (0x02000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x02000000 */
9458 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_26                     (0x04000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x04000000 */
9459 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_27                     (0x08000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x08000000 */
9460 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_28                     (0x10000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x10000000 */
9461 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_29                     (0x20000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x20000000 */
9462 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_30                     (0x40000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x40000000 */
9463 #define RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_31                     (0x80000000 << RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos)   /*!<0x80000000 */
9464 
9465 /* ===============================================   SEMA_IRQ_ENABLE   =============================================== */
9466 #define RRM_SEMA_IRQ_ENABLE_LOCK_Pos                                       (0UL)   /*!< RRM SEMA_IRQ_ENABLE: LOCK (Bit 0) */
9467 #define RRM_SEMA_IRQ_ENABLE_LOCK_Msk                                       (0x00000001UL)  /*!< RRM SEMA_IRQ_ENABLE: LOCK (Bitfield-Mask: 0x1) */
9468 #define RRM_SEMA_IRQ_ENABLE_LOCK                                           RRM_SEMA_IRQ_ENABLE_LOCK_Msk
9469 #define RRM_SEMA_IRQ_ENABLE_UNLOCK_Pos                                     (1UL)   /*!< RRM SEMA_IRQ_ENABLE: UNLOCK (Bit 1) */
9470 #define RRM_SEMA_IRQ_ENABLE_UNLOCK_Msk                                     (0x00000002UL)  /*!< RRM SEMA_IRQ_ENABLE: UNLOCK (Bitfield-Mask: 0x1) */
9471 #define RRM_SEMA_IRQ_ENABLE_UNLOCK                                         RRM_SEMA_IRQ_ENABLE_UNLOCK_Msk
9472 
9473 /* ===============================================   SEMA_IRQ_STATUS   =============================================== */
9474 #define RRM_SEMA_IRQ_STATUS_LOCK_Pos                                       (0UL)   /*!< RRM SEMA_IRQ_STATUS: LOCK (Bit 0) */
9475 #define RRM_SEMA_IRQ_STATUS_LOCK_Msk                                       (0x00000001UL)  /*!< RRM SEMA_IRQ_STATUS: LOCK (Bitfield-Mask: 0x1) */
9476 #define RRM_SEMA_IRQ_STATUS_LOCK                                           RRM_SEMA_IRQ_STATUS_LOCK_Msk
9477 #define RRM_SEMA_IRQ_STATUS_UNLOCK_Pos                                     (1UL)   /*!< RRM SEMA_IRQ_STATUS: UNLOCK (Bit 1) */
9478 #define RRM_SEMA_IRQ_STATUS_UNLOCK_Msk                                     (0x00000002UL)  /*!< RRM SEMA_IRQ_STATUS: UNLOCK (Bitfield-Mask: 0x1) */
9479 #define RRM_SEMA_IRQ_STATUS_UNLOCK                                         RRM_SEMA_IRQ_STATUS_UNLOCK_Msk
9480 
9481 /* ===============================================   BLE_IRQ_ENABLE   =============================================== */
9482 #define RRM_BLE_IRQ_ENABLE_PORT_GRANT_Pos                                  (0UL)   /*!< RRM BLE_IRQ_ENABLE: PORT_GRANT (Bit 0) */
9483 #define RRM_BLE_IRQ_ENABLE_PORT_GRANT_Msk                                  (0x00000001UL)  /*!< RRM BLE_IRQ_ENABLE: PORT_GRANT (Bitfield-Mask: 0x1) */
9484 #define RRM_BLE_IRQ_ENABLE_PORT_GRANT                                      RRM_BLE_IRQ_ENABLE_PORT_GRANT_Msk
9485 #define RRM_BLE_IRQ_ENABLE_PORT_RELEASE_Pos                                (1UL)   /*!< RRM BLE_IRQ_ENABLE: PORT_RELEASE (Bit 1) */
9486 #define RRM_BLE_IRQ_ENABLE_PORT_RELEASE_Msk                                (0x00000002UL)  /*!< RRM BLE_IRQ_ENABLE: PORT_RELEASE (Bitfield-Mask: 0x1) */
9487 #define RRM_BLE_IRQ_ENABLE_PORT_RELEASE                                    RRM_BLE_IRQ_ENABLE_PORT_RELEASE_Msk
9488 #define RRM_BLE_IRQ_ENABLE_PORT_PREEMPT_Pos                                (2UL)   /*!< RRM BLE_IRQ_ENABLE: PORT_PREEMPT (Bit 2) */
9489 #define RRM_BLE_IRQ_ENABLE_PORT_PREEMPT_Msk                                (0x00000004UL)  /*!< RRM BLE_IRQ_ENABLE: PORT_PREEMPT (Bitfield-Mask: 0x1) */
9490 #define RRM_BLE_IRQ_ENABLE_PORT_PREEMPT                                    RRM_BLE_IRQ_ENABLE_PORT_PREEMPT_Msk
9491 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_START_Pos                              (3UL)   /*!< RRM BLE_IRQ_ENABLE: PORT_CMD_START (Bit 3) */
9492 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_START_Msk                              (0x00000008UL)  /*!< RRM BLE_IRQ_ENABLE: PORT_CMD_START (Bitfield-Mask: 0x1) */
9493 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_START                                  RRM_BLE_IRQ_ENABLE_PORT_CMD_START_Msk
9494 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_END_Pos                                (4UL)   /*!< RRM BLE_IRQ_ENABLE: PORT_CMD_END (Bit 4) */
9495 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_END_Msk                                (0x00000010UL)  /*!< RRM BLE_IRQ_ENABLE: PORT_CMD_END (Bitfield-Mask: 0x1) */
9496 #define RRM_BLE_IRQ_ENABLE_PORT_CMD_END                                    RRM_BLE_IRQ_ENABLE_PORT_CMD_END_Msk
9497 
9498 /* ===============================================   BLE_IRQ_STATUS   =============================================== */
9499 #define RRM_BLE_IRQ_STATUS_PORT_GRANT_Pos                                  (0UL)   /*!< RRM BLE_IRQ_STATUS: PORT_GRANT (Bit 0) */
9500 #define RRM_BLE_IRQ_STATUS_PORT_GRANT_Msk                                  (0x00000001UL)  /*!< RRM BLE_IRQ_STATUS: PORT_GRANT (Bitfield-Mask: 0x1) */
9501 #define RRM_BLE_IRQ_STATUS_PORT_GRANT                                      RRM_BLE_IRQ_STATUS_PORT_GRANT_Msk
9502 #define RRM_BLE_IRQ_STATUS_PORT_RELEASE_Pos                                (1UL)   /*!< RRM BLE_IRQ_STATUS: PORT_RELEASE (Bit 1) */
9503 #define RRM_BLE_IRQ_STATUS_PORT_RELEASE_Msk                                (0x00000002UL)  /*!< RRM BLE_IRQ_STATUS: PORT_RELEASE (Bitfield-Mask: 0x1) */
9504 #define RRM_BLE_IRQ_STATUS_PORT_RELEASE                                    RRM_BLE_IRQ_STATUS_PORT_RELEASE_Msk
9505 #define RRM_BLE_IRQ_STATUS_PORT_PREEMPT_Pos                                (2UL)   /*!< RRM BLE_IRQ_STATUS: PORT_PREEMPT (Bit 2) */
9506 #define RRM_BLE_IRQ_STATUS_PORT_PREEMPT_Msk                                (0x00000004UL)  /*!< RRM BLE_IRQ_STATUS: PORT_PREEMPT (Bitfield-Mask: 0x1) */
9507 #define RRM_BLE_IRQ_STATUS_PORT_PREEMPT                                    RRM_BLE_IRQ_STATUS_PORT_PREEMPT_Msk
9508 #define RRM_BLE_IRQ_STATUS_CMD_START_Pos                                   (3UL)   /*!< RRM BLE_IRQ_STATUS: CMD_START (Bit 3) */
9509 #define RRM_BLE_IRQ_STATUS_CMD_START_Msk                                   (0x00000008UL)  /*!< RRM BLE_IRQ_STATUS: CMD_START (Bitfield-Mask: 0x1) */
9510 #define RRM_BLE_IRQ_STATUS_CMD_START                                       RRM_BLE_IRQ_STATUS_CMD_START_Msk
9511 #define RRM_BLE_IRQ_STATUS_CMD_END_Pos                                     (4UL)   /*!< RRM BLE_IRQ_STATUS: CMD_END (Bit 4) */
9512 #define RRM_BLE_IRQ_STATUS_CMD_END_Msk                                     (0x00000010UL)  /*!< RRM BLE_IRQ_STATUS: CMD_END (Bitfield-Mask: 0x1) */
9513 #define RRM_BLE_IRQ_STATUS_CMD_END                                         RRM_BLE_IRQ_STATUS_CMD_END_Msk
9514 
9515 /* ===============================================   VP_CPU_CMD_BUS   =============================================== */
9516 #define RRM_VP_CPU_CMD_BUS_COMMAND_Pos                                     (0UL)   /*!< RRM VP_CPU_CMD_BUS: COMMAND (Bit 0) */
9517 #define RRM_VP_CPU_CMD_BUS_COMMAND_Msk                                     (0x00000007UL)  /*!< RRM VP_CPU_CMD_BUS: COMMAND (Bitfield-Mask: 0x7) */
9518 #define RRM_VP_CPU_CMD_BUS_COMMAND                                         RRM_VP_CPU_CMD_BUS_COMMAND_Msk
9519 #define RRM_VP_CPU_CMD_BUS_COMMAND_0                                       (0x1 << RRM_VP_CPU_CMD_BUS_COMMAND_Pos)   /*!<0x00000001 */
9520 #define RRM_VP_CPU_CMD_BUS_COMMAND_1                                       (0x2 << RRM_VP_CPU_CMD_BUS_COMMAND_Pos)   /*!<0x00000002 */
9521 #define RRM_VP_CPU_CMD_BUS_COMMAND_2                                       (0x4 << RRM_VP_CPU_CMD_BUS_COMMAND_Pos)   /*!<0x00000004 */
9522 #define RRM_VP_CPU_CMD_BUS_COMMAND_REQ_Pos                                 (3UL)   /*!< RRM VP_CPU_CMD_BUS: COMMAND_REQ (Bit 3) */
9523 #define RRM_VP_CPU_CMD_BUS_COMMAND_REQ_Msk                                 (0x00000008UL)  /*!< RRM VP_CPU_CMD_BUS: COMMAND_REQ (Bitfield-Mask: 0x1) */
9524 #define RRM_VP_CPU_CMD_BUS_COMMAND_REQ                                     RRM_VP_CPU_CMD_BUS_COMMAND_REQ_Msk
9525 
9526 /* ===============================================   VP_CPU_SEMA_BUS   =============================================== */
9527 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Pos                                  (0UL)   /*!< RRM VP_CPU_SEMA_BUS: TAKE_PRIO (Bit 0) */
9528 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Msk                                  (0x00000007UL)  /*!< RRM VP_CPU_SEMA_BUS: TAKE_PRIO (Bitfield-Mask: 0x7) */
9529 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO                                      RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Msk
9530 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_0                                    (0x1 << RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Pos)   /*!<0x00000001 */
9531 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_1                                    (0x2 << RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Pos)   /*!<0x00000002 */
9532 #define RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_2                                    (0x4 << RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Pos)   /*!<0x00000004 */
9533 #define RRM_VP_CPU_SEMA_BUS_TAKE_REQ_Pos                                   (3UL)   /*!< RRM VP_CPU_SEMA_BUS: TAKE_REQ (Bit 3) */
9534 #define RRM_VP_CPU_SEMA_BUS_TAKE_REQ_Msk                                   (0x00000008UL)  /*!< RRM VP_CPU_SEMA_BUS: TAKE_REQ (Bitfield-Mask: 0x1) */
9535 #define RRM_VP_CPU_SEMA_BUS_TAKE_REQ                                       RRM_VP_CPU_SEMA_BUS_TAKE_REQ_Msk
9536 #define RRM_VP_CPU_SEMA_BUS_TAKE_PREEMPT_Pos                               (4UL)   /*!< RRM VP_CPU_SEMA_BUS: TAKE_PREEMPT (Bit 4) */
9537 #define RRM_VP_CPU_SEMA_BUS_TAKE_PREEMPT_Msk                               (0x00000010UL)  /*!< RRM VP_CPU_SEMA_BUS: TAKE_PREEMPT (Bitfield-Mask: 0x1) */
9538 #define RRM_VP_CPU_SEMA_BUS_TAKE_PREEMPT                                   RRM_VP_CPU_SEMA_BUS_TAKE_PREEMPT_Msk
9539 
9540 /* ===============================================   VP_CPU_IRQ_ENABLE   =============================================== */
9541 #define RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT_Pos                               (0UL)   /*!< RRM VP_CPU_IRQ_ENABLE: PORT_GRANT (Bit 0) */
9542 #define RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT_Msk                               (0x00000001UL)  /*!< RRM VP_CPU_IRQ_ENABLE: PORT_GRANT (Bitfield-Mask: 0x1) */
9543 #define RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT                                   RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT_Msk
9544 #define RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE_Pos                             (1UL)   /*!< RRM VP_CPU_IRQ_ENABLE: PORT_RELEASE (Bit 1) */
9545 #define RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE_Msk                             (0x00000002UL)  /*!< RRM VP_CPU_IRQ_ENABLE: PORT_RELEASE (Bitfield-Mask: 0x1) */
9546 #define RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE                                 RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE_Msk
9547 #define RRM_VP_CPU_IRQ_ENABLE_PORT_PREEMPT_Pos                             (2UL)   /*!< RRM VP_CPU_IRQ_ENABLE: PORT_PREEMPT (Bit 2) */
9548 #define RRM_VP_CPU_IRQ_ENABLE_PORT_PREEMPT_Msk                             (0x00000004UL)  /*!< RRM VP_CPU_IRQ_ENABLE: PORT_PREEMPT (Bitfield-Mask: 0x1) */
9549 #define RRM_VP_CPU_IRQ_ENABLE_PORT_PREEMPT                                 RRM_VP_CPU_IRQ_ENABLE_PORT_PREEMPT_Msk
9550 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START_Pos                           (3UL)   /*!< RRM VP_CPU_IRQ_ENABLE: PORT_CMD_START (Bit 3) */
9551 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START_Msk                           (0x00000008UL)  /*!< RRM VP_CPU_IRQ_ENABLE: PORT_CMD_START (Bitfield-Mask: 0x1) */
9552 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START                               RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START_Msk
9553 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END_Pos                             (4UL)   /*!< RRM VP_CPU_IRQ_ENABLE: PORT_CMD_END (Bit 4) */
9554 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END_Msk                             (0x00000010UL)  /*!< RRM VP_CPU_IRQ_ENABLE: PORT_CMD_END (Bitfield-Mask: 0x1) */
9555 #define RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END                                 RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END_Msk
9556 
9557 /* ===============================================   VP_CPU_IRQ_STATUS   =============================================== */
9558 #define RRM_VP_CPU_IRQ_STATUS_PORT_GRANT_Pos                               (0UL)   /*!< RRM VP_CPU_IRQ_STATUS: PORT_GRANT (Bit 0) */
9559 #define RRM_VP_CPU_IRQ_STATUS_PORT_GRANT_Msk                               (0x00000001UL)  /*!< RRM VP_CPU_IRQ_STATUS: PORT_GRANT (Bitfield-Mask: 0x1) */
9560 #define RRM_VP_CPU_IRQ_STATUS_PORT_GRANT                                   RRM_VP_CPU_IRQ_STATUS_PORT_GRANT_Msk
9561 #define RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE_Pos                             (1UL)   /*!< RRM VP_CPU_IRQ_STATUS: PORT_RELEASE (Bit 1) */
9562 #define RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE_Msk                             (0x00000002UL)  /*!< RRM VP_CPU_IRQ_STATUS: PORT_RELEASE (Bitfield-Mask: 0x1) */
9563 #define RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE                                 RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE_Msk
9564 #define RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT_Pos                             (2UL)   /*!< RRM VP_CPU_IRQ_STATUS: PORT_PREEMPT (Bit 2) */
9565 #define RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT_Msk                             (0x00000004UL)  /*!< RRM VP_CPU_IRQ_STATUS: PORT_PREEMPT (Bitfield-Mask: 0x1) */
9566 #define RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT                                 RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT_Msk
9567 #define RRM_VP_CPU_IRQ_STATUS_CMD_START_Pos                                (3UL)   /*!< RRM VP_CPU_IRQ_STATUS: CMD_START (Bit 3) */
9568 #define RRM_VP_CPU_IRQ_STATUS_CMD_START_Msk                                (0x00000008UL)  /*!< RRM VP_CPU_IRQ_STATUS: CMD_START (Bitfield-Mask: 0x1) */
9569 #define RRM_VP_CPU_IRQ_STATUS_CMD_START                                    RRM_VP_CPU_IRQ_STATUS_CMD_START_Msk
9570 #define RRM_VP_CPU_IRQ_STATUS_CMD_END_Pos                                  (4UL)   /*!< RRM VP_CPU_IRQ_STATUS: CMD_END (Bit 4) */
9571 #define RRM_VP_CPU_IRQ_STATUS_CMD_END_Msk                                  (0x00000010UL)  /*!< RRM VP_CPU_IRQ_STATUS: CMD_END (Bitfield-Mask: 0x1) */
9572 #define RRM_VP_CPU_IRQ_STATUS_CMD_END                                      RRM_VP_CPU_IRQ_STATUS_CMD_END_Msk
9573 
9574 /* ===============================================   AA0_DIG_USR   =============================================== */
9575 #define RRM_AA0_DIG_USR_AA_7_0_Pos                                         (0UL)   /*!< RRM AA0_DIG_USR: AA_7_0 (Bit 0) */
9576 #define RRM_AA0_DIG_USR_AA_7_0_Msk                                         (0x000000ffUL)  /*!< RRM AA0_DIG_USR: AA_7_0 (Bitfield-Mask: 0xff) */
9577 #define RRM_AA0_DIG_USR_AA_7_0                                             RRM_AA0_DIG_USR_AA_7_0_Msk
9578 #define RRM_AA0_DIG_USR_AA_7_0_0                                           (0x01 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000001 */
9579 #define RRM_AA0_DIG_USR_AA_7_0_1                                           (0x02 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000002 */
9580 #define RRM_AA0_DIG_USR_AA_7_0_2                                           (0x04 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000004 */
9581 #define RRM_AA0_DIG_USR_AA_7_0_3                                           (0x08 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000008 */
9582 #define RRM_AA0_DIG_USR_AA_7_0_4                                           (0x10 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000010 */
9583 #define RRM_AA0_DIG_USR_AA_7_0_5                                           (0x20 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000020 */
9584 #define RRM_AA0_DIG_USR_AA_7_0_6                                           (0x40 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000040 */
9585 #define RRM_AA0_DIG_USR_AA_7_0_7                                           (0x80 << RRM_AA0_DIG_USR_AA_7_0_Pos)   /*!<0x00000080 */
9586 
9587 /* ===============================================   AA1_DIG_USR   =============================================== */
9588 #define RRM_AA1_DIG_USR_AA_15_8_Pos                                        (0UL)   /*!< RRM AA1_DIG_USR: AA_15_8 (Bit 0) */
9589 #define RRM_AA1_DIG_USR_AA_15_8_Msk                                        (0x000000ffUL)  /*!< RRM AA1_DIG_USR: AA_15_8 (Bitfield-Mask: 0xff) */
9590 #define RRM_AA1_DIG_USR_AA_15_8                                            RRM_AA1_DIG_USR_AA_15_8_Msk
9591 #define RRM_AA1_DIG_USR_AA_15_8_0                                          (0x01 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000001 */
9592 #define RRM_AA1_DIG_USR_AA_15_8_1                                          (0x02 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000002 */
9593 #define RRM_AA1_DIG_USR_AA_15_8_2                                          (0x04 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000004 */
9594 #define RRM_AA1_DIG_USR_AA_15_8_3                                          (0x08 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000008 */
9595 #define RRM_AA1_DIG_USR_AA_15_8_4                                          (0x10 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000010 */
9596 #define RRM_AA1_DIG_USR_AA_15_8_5                                          (0x20 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000020 */
9597 #define RRM_AA1_DIG_USR_AA_15_8_6                                          (0x40 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000040 */
9598 #define RRM_AA1_DIG_USR_AA_15_8_7                                          (0x80 << RRM_AA1_DIG_USR_AA_15_8_Pos)   /*!<0x00000080 */
9599 
9600 /* ===============================================   AA2_DIG_USR   =============================================== */
9601 #define RRM_AA2_DIG_USR_AA_23_16_Pos                                       (0UL)   /*!< RRM AA2_DIG_USR: AA_23_16 (Bit 0) */
9602 #define RRM_AA2_DIG_USR_AA_23_16_Msk                                       (0x000000ffUL)  /*!< RRM AA2_DIG_USR: AA_23_16 (Bitfield-Mask: 0xff) */
9603 #define RRM_AA2_DIG_USR_AA_23_16                                           RRM_AA2_DIG_USR_AA_23_16_Msk
9604 #define RRM_AA2_DIG_USR_AA_23_16_0                                         (0x01 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000001 */
9605 #define RRM_AA2_DIG_USR_AA_23_16_1                                         (0x02 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000002 */
9606 #define RRM_AA2_DIG_USR_AA_23_16_2                                         (0x04 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000004 */
9607 #define RRM_AA2_DIG_USR_AA_23_16_3                                         (0x08 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000008 */
9608 #define RRM_AA2_DIG_USR_AA_23_16_4                                         (0x10 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000010 */
9609 #define RRM_AA2_DIG_USR_AA_23_16_5                                         (0x20 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000020 */
9610 #define RRM_AA2_DIG_USR_AA_23_16_6                                         (0x40 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000040 */
9611 #define RRM_AA2_DIG_USR_AA_23_16_7                                         (0x80 << RRM_AA2_DIG_USR_AA_23_16_Pos)   /*!<0x00000080 */
9612 
9613 /* ===============================================   AA3_DIG_USR   =============================================== */
9614 #define RRM_AA3_DIG_USR_AA_31_24_Pos                                       (0UL)   /*!< RRM AA3_DIG_USR: AA_31_24 (Bit 0) */
9615 #define RRM_AA3_DIG_USR_AA_31_24_Msk                                       (0x000000ffUL)  /*!< RRM AA3_DIG_USR: AA_31_24 (Bitfield-Mask: 0xff) */
9616 #define RRM_AA3_DIG_USR_AA_31_24                                           RRM_AA3_DIG_USR_AA_31_24_Msk
9617 #define RRM_AA3_DIG_USR_AA_31_24_0                                         (0x01 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000001 */
9618 #define RRM_AA3_DIG_USR_AA_31_24_1                                         (0x02 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000002 */
9619 #define RRM_AA3_DIG_USR_AA_31_24_2                                         (0x04 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000004 */
9620 #define RRM_AA3_DIG_USR_AA_31_24_3                                         (0x08 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000008 */
9621 #define RRM_AA3_DIG_USR_AA_31_24_4                                         (0x10 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000010 */
9622 #define RRM_AA3_DIG_USR_AA_31_24_5                                         (0x20 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000020 */
9623 #define RRM_AA3_DIG_USR_AA_31_24_6                                         (0x40 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000040 */
9624 #define RRM_AA3_DIG_USR_AA_31_24_7                                         (0x80 << RRM_AA3_DIG_USR_AA_31_24_Pos)   /*!<0x00000080 */
9625 
9626 /* ===============================================   DEM_MOD_DIG_USR   =============================================== */
9627 #define RRM_DEM_MOD_DIG_USR_SPARE_Pos                                      (0UL)   /*!< RRM DEM_MOD_DIG_USR: SPARE (Bit 0) */
9628 #define RRM_DEM_MOD_DIG_USR_SPARE_Msk                                      (0x00000001UL)  /*!< RRM DEM_MOD_DIG_USR: SPARE (Bitfield-Mask: 0x1) */
9629 #define RRM_DEM_MOD_DIG_USR_SPARE                                          RRM_DEM_MOD_DIG_USR_SPARE_Msk
9630 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos                                (1UL)   /*!< RRM DEM_MOD_DIG_USR: CHANNEL_NUM (Bit 1) */
9631 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Msk                                (0x000000feUL)  /*!< RRM DEM_MOD_DIG_USR: CHANNEL_NUM (Bitfield-Mask: 0x7f) */
9632 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM                                    RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Msk
9633 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_0                                  (0x1 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000002 */
9634 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_1                                  (0x2 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000004 */
9635 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_2                                  (0x4 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000008 */
9636 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_3                                  (0x8 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000010 */
9637 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_4                                  (0x10 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000020 */
9638 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_5                                  (0x20 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000040 */
9639 #define RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_6                                  (0x40 << RRM_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos)   /*!<0x00000080 */
9640 
9641 /* ===============================================   RADIO_FSM_USR   =============================================== */
9642 #define RRM_RADIO_FSM_USR_SPARE_Pos                                        (0UL)   /*!< RRM RADIO_FSM_USR: SPARE (Bit 0) */
9643 #define RRM_RADIO_FSM_USR_SPARE_Msk                                        (0x00000001UL)  /*!< RRM RADIO_FSM_USR: SPARE (Bitfield-Mask: 0x1) */
9644 #define RRM_RADIO_FSM_USR_SPARE                                            RRM_RADIO_FSM_USR_SPARE_Msk
9645 #define RRM_RADIO_FSM_USR_EN_CALIB_CBP_Pos                                 (1UL)   /*!< RRM RADIO_FSM_USR: EN_CALIB_CBP (Bit 1) */
9646 #define RRM_RADIO_FSM_USR_EN_CALIB_CBP_Msk                                 (0x00000002UL)  /*!< RRM RADIO_FSM_USR: EN_CALIB_CBP (Bitfield-Mask: 0x1) */
9647 #define RRM_RADIO_FSM_USR_EN_CALIB_CBP                                     RRM_RADIO_FSM_USR_EN_CALIB_CBP_Msk
9648 #define RRM_RADIO_FSM_USR_EN_CALIB_SYNTH_Pos                               (2UL)   /*!< RRM RADIO_FSM_USR: EN_CALIB_SYNTH (Bit 2) */
9649 #define RRM_RADIO_FSM_USR_EN_CALIB_SYNTH_Msk                               (0x00000004UL)  /*!< RRM RADIO_FSM_USR: EN_CALIB_SYNTH (Bitfield-Mask: 0x1) */
9650 #define RRM_RADIO_FSM_USR_EN_CALIB_SYNTH                                   RRM_RADIO_FSM_USR_EN_CALIB_SYNTH_Msk
9651 #define RRM_RADIO_FSM_USR_PA_POWER_Pos                                     (3UL)   /*!< RRM RADIO_FSM_USR: PA_POWER (Bit 3) */
9652 #define RRM_RADIO_FSM_USR_PA_POWER_Msk                                     (0x000000f8UL)  /*!< RRM RADIO_FSM_USR: PA_POWER (Bitfield-Mask: 0x1f) */
9653 #define RRM_RADIO_FSM_USR_PA_POWER                                         RRM_RADIO_FSM_USR_PA_POWER_Msk
9654 #define RRM_RADIO_FSM_USR_PA_POWER_0                                       (0x1 << RRM_RADIO_FSM_USR_PA_POWER_Pos)   /*!<0x00000008 */
9655 #define RRM_RADIO_FSM_USR_PA_POWER_1                                       (0x2 << RRM_RADIO_FSM_USR_PA_POWER_Pos)   /*!<0x00000010 */
9656 #define RRM_RADIO_FSM_USR_PA_POWER_2                                       (0x4 << RRM_RADIO_FSM_USR_PA_POWER_Pos)   /*!<0x00000020 */
9657 #define RRM_RADIO_FSM_USR_PA_POWER_3                                       (0x8 << RRM_RADIO_FSM_USR_PA_POWER_Pos)   /*!<0x00000040 */
9658 #define RRM_RADIO_FSM_USR_PA_POWER_4                                       (0x10 << RRM_RADIO_FSM_USR_PA_POWER_Pos)   /*!<0x00000080 */
9659 
9660 /* ===============================================   PHYCTRL_DIG_USR   =============================================== */
9661 #define RRM_PHYCTRL_DIG_USR_RXTXPHY_Pos                                    (0UL)   /*!< RRM PHYCTRL_DIG_USR: RXTXPHY (Bit 0) */
9662 #define RRM_PHYCTRL_DIG_USR_RXTXPHY_Msk                                    (0x00000007UL)  /*!< RRM PHYCTRL_DIG_USR: RXTXPHY (Bitfield-Mask: 0x7) */
9663 #define RRM_PHYCTRL_DIG_USR_RXTXPHY                                        RRM_PHYCTRL_DIG_USR_RXTXPHY_Msk
9664 #define RRM_PHYCTRL_DIG_USR_RXTXPHY_0                                      (0x1 << RRM_PHYCTRL_DIG_USR_RXTXPHY_Pos)   /*!<0x00000001 */
9665 #define RRM_PHYCTRL_DIG_USR_RXTXPHY_1                                      (0x2 << RRM_PHYCTRL_DIG_USR_RXTXPHY_Pos)   /*!<0x00000002 */
9666 #define RRM_PHYCTRL_DIG_USR_RXTXPHY_2                                      (0x4 << RRM_PHYCTRL_DIG_USR_RXTXPHY_Pos)   /*!<0x00000004 */
9667 #define RRM_PHYCTRL_DIG_USR_SPARE_Pos                                      (3UL)   /*!< RRM PHYCTRL_DIG_USR: SPARE (Bit 3) */
9668 #define RRM_PHYCTRL_DIG_USR_SPARE_Msk                                      (0x000000F8UL)  /*!< RRM PHYCTRL_DIG_USR: SPARE (Bitfield-Mask: 0x1F) */
9669 #define RRM_PHYCTRL_DIG_USR_SPARE                                          RRM_PHYCTRL_DIG_USR_SPARE_Msk
9670 
9671 /* ===============================================   AFC0_DIG_ENG   =============================================== */
9672 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Pos                                (0UL)   /*!< RRM AFC0_DIG_ENG: AFC_GAIN_AFTER (Bit 0) */
9673 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Msk                                (0x0000000fUL)  /*!< RRM AFC0_DIG_ENG: AFC_GAIN_AFTER (Bitfield-Mask: 0xf) */
9674 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER                                    RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Msk
9675 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_0                                  (0x1 << RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Pos)   /*!<0x00000001 */
9676 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_1                                  (0x2 << RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Pos)   /*!<0x00000002 */
9677 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_2                                  (0x4 << RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Pos)   /*!<0x00000004 */
9678 #define RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_3                                  (0x8 << RRM_AFC0_DIG_ENG_AFC_GAIN_AFTER_Pos)   /*!<0x00000008 */
9679 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Pos                               (4UL)   /*!< RRM AFC0_DIG_ENG: AFC_GAIN_BEFORE (Bit 4) */
9680 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Msk                               (0x000000f0UL)  /*!< RRM AFC0_DIG_ENG: AFC_GAIN_BEFORE (Bitfield-Mask: 0xf) */
9681 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE                                   RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Msk
9682 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_0                                 (0x1 << RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Pos)   /*!<0x00000010 */
9683 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_1                                 (0x2 << RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Pos)   /*!<0x00000020 */
9684 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_2                                 (0x4 << RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Pos)   /*!<0x00000040 */
9685 #define RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_3                                 (0x8 << RRM_AFC0_DIG_ENG_AFC_GAIN_BEFORE_Pos)   /*!<0x00000080 */
9686 
9687 /* ===============================================   AFC1_DIG_ENG   =============================================== */
9688 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos                               (0UL)   /*!< RRM AFC1_DIG_ENG: AFC_DELAY_AFTER (Bit 0) */
9689 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Msk                               (0x0000000fUL)  /*!< RRM AFC1_DIG_ENG: AFC_DELAY_AFTER (Bitfield-Mask: 0xf) */
9690 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER                                   RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Msk
9691 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_0                                 (0x1 << RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos)   /*!<0x00000001 */
9692 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_1                                 (0x2 << RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos)   /*!<0x00000002 */
9693 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_2                                 (0x4 << RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos)   /*!<0x00000004 */
9694 #define RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_3                                 (0x8 << RRM_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos)   /*!<0x00000008 */
9695 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos                              (4UL)   /*!< RRM AFC1_DIG_ENG: AFC_DELAY_BEFORE (Bit 4) */
9696 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Msk                              (0x000000f0UL)  /*!< RRM AFC1_DIG_ENG: AFC_DELAY_BEFORE (Bitfield-Mask: 0xf) */
9697 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE                                  RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Msk
9698 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_0                                (0x1 << RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos)   /*!<0x00000010 */
9699 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_1                                (0x2 << RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos)   /*!<0x00000020 */
9700 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_2                                (0x4 << RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos)   /*!<0x00000040 */
9701 #define RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_3                                (0x8 << RRM_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos)   /*!<0x00000080 */
9702 
9703 /* ===============================================   AFC2_DIG_ENG   =============================================== */
9704 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos                                (0UL)   /*!< RRM AFC2_DIG_ENG: AFC_FREQ_LIMIT (Bit 0) */
9705 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Msk                                (0x0000007fUL)  /*!< RRM AFC2_DIG_ENG: AFC_FREQ_LIMIT (Bitfield-Mask: 0x7f) */
9706 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT                                    RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Msk
9707 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_0                                  (0x1 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000001 */
9708 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_1                                  (0x2 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000002 */
9709 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_2                                  (0x4 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000004 */
9710 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_3                                  (0x8 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000008 */
9711 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_4                                  (0x10 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000010 */
9712 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_5                                  (0x20 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000020 */
9713 #define RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_6                                  (0x40 << RRM_AFC2_DIG_ENG_AFC_FREQ_LIMIT_Pos)   /*!<0x00000040 */
9714 #define RRM_AFC2_DIG_ENG_AFC_ENABLE_Pos                                    (7UL)   /*!< RRM AFC2_DIG_ENG: AFC_ENABLE (Bit 7) */
9715 #define RRM_AFC2_DIG_ENG_AFC_ENABLE_Msk                                    (0x00000080UL)  /*!< RRM AFC2_DIG_ENG: AFC_ENABLE (Bitfield-Mask: 0x1) */
9716 #define RRM_AFC2_DIG_ENG_AFC_ENABLE                                        RRM_AFC2_DIG_ENG_AFC_ENABLE_Msk
9717 
9718 /* ===============================================   AFC3_DIG_ENG   =============================================== */
9719 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos                              (0UL)   /*!< RRM AFC3_DIG_ENG: AFC_MINMAX_LIMIT (Bit 0) */
9720 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Msk                              (0x000000ffUL)  /*!< RRM AFC3_DIG_ENG: AFC_MINMAX_LIMIT (Bitfield-Mask: 0xff) */
9721 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT                                  RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Msk
9722 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_0                                (0x01 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000001 */
9723 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_1                                (0x02 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000002 */
9724 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_2                                (0x04 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000004 */
9725 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_3                                (0x08 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000008 */
9726 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_4                                (0x10 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000010 */
9727 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_5                                (0x20 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000020 */
9728 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_6                                (0x40 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000040 */
9729 #define RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_7                                (0x80 << RRM_AFC3_DIG_ENG_AFC_MINMAX_LIMIT_Pos)   /*!<0x00000080 */
9730 
9731 /* ===============================================   CR0_DIG_ENG   =============================================== */
9732 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Pos                                  (0UL)   /*!< RRM CR0_DIG_ENG: CR_GAIN_AFTER (Bit 0) */
9733 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Msk                                  (0x0000000fUL)  /*!< RRM CR0_DIG_ENG: CR_GAIN_AFTER (Bitfield-Mask: 0xf) */
9734 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER                                      RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Msk
9735 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_0                                    (0x1 << RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Pos)   /*!<0x00000001 */
9736 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_1                                    (0x2 << RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Pos)   /*!<0x00000002 */
9737 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_2                                    (0x4 << RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Pos)   /*!<0x00000004 */
9738 #define RRM_CR0_DIG_ENG_CR_GAIN_AFTER_3                                    (0x8 << RRM_CR0_DIG_ENG_CR_GAIN_AFTER_Pos)   /*!<0x00000008 */
9739 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos                                 (4UL)   /*!< RRM CR0_DIG_ENG: CR_GAIN_BEFORE (Bit 4) */
9740 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Msk                                 (0x000000f0UL)  /*!< RRM CR0_DIG_ENG: CR_GAIN_BEFORE (Bitfield-Mask: 0xf) */
9741 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE                                     RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Msk
9742 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_0                                   (0x1 << RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos)   /*!<0x00000010 */
9743 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_1                                   (0x2 << RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos)   /*!<0x00000020 */
9744 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_2                                   (0x4 << RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos)   /*!<0x00000040 */
9745 #define RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_3                                   (0x8 << RRM_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos)   /*!<0x00000080 */
9746 
9747 /* ===============================================   CR0_LR   =============================================== */
9748 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_Pos                                    (0UL)   /*!< RRM CR0_LR: CR_LR_GAIN_AFTER (Bit 0) */
9749 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_Msk                                    (0x0000000fUL)  /*!< RRM CR0_LR: CR_LR_GAIN_AFTER (Bitfield-Mask: 0xf) */
9750 #define RRM_CR0_LR_CR_LR_GAIN_AFTER                                        RRM_CR0_LR_CR_LR_GAIN_AFTER_Msk
9751 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_0                                      (0x1 << RRM_CR0_LR_CR_LR_GAIN_AFTER_Pos)   /*!<0x00000001 */
9752 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_1                                      (0x2 << RRM_CR0_LR_CR_LR_GAIN_AFTER_Pos)   /*!<0x00000002 */
9753 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_2                                      (0x4 << RRM_CR0_LR_CR_LR_GAIN_AFTER_Pos)   /*!<0x00000004 */
9754 #define RRM_CR0_LR_CR_LR_GAIN_AFTER_3                                      (0x8 << RRM_CR0_LR_CR_LR_GAIN_AFTER_Pos)   /*!<0x00000008 */
9755 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_Pos                                   (4UL)   /*!< RRM CR0_LR: CR_LR_GAIN_BEFORE (Bit 4) */
9756 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_Msk                                   (0x000000f0UL)  /*!< RRM CR0_LR: CR_LR_GAIN_BEFORE (Bitfield-Mask: 0xf) */
9757 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE                                       RRM_CR0_LR_CR_LR_GAIN_BEFORE_Msk
9758 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_0                                     (0x1 << RRM_CR0_LR_CR_LR_GAIN_BEFORE_Pos)   /*!<0x00000010 */
9759 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_1                                     (0x2 << RRM_CR0_LR_CR_LR_GAIN_BEFORE_Pos)   /*!<0x00000020 */
9760 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_2                                     (0x4 << RRM_CR0_LR_CR_LR_GAIN_BEFORE_Pos)   /*!<0x00000040 */
9761 #define RRM_CR0_LR_CR_LR_GAIN_BEFORE_3                                     (0x8 << RRM_CR0_LR_CR_LR_GAIN_BEFORE_Pos)   /*!<0x00000080 */
9762 
9763 /* ===============================================   VIT_CONF_DIG_ENG   =============================================== */
9764 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos                                  (0UL)   /*!< RRM VIT_CONF_DIG_ENG: VIT_CONF (Bit 0) */
9765 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_Msk                                  (0x000000ffUL)  /*!< RRM VIT_CONF_DIG_ENG: VIT_CONF (Bitfield-Mask: 0xff) */
9766 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF                                      RRM_VIT_CONF_DIG_ENG_VIT_CONF_Msk
9767 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_0                                    (0x01 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000001 */
9768 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_1                                    (0x02 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000002 */
9769 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_2                                    (0x04 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000004 */
9770 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_3                                    (0x08 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000008 */
9771 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_4                                    (0x10 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000010 */
9772 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_5                                    (0x20 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000020 */
9773 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_6                                    (0x40 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000040 */
9774 #define RRM_VIT_CONF_DIG_ENG_VIT_CONF_7                                    (0x80 << RRM_VIT_CONF_DIG_ENG_VIT_CONF_Pos)   /*!<0x00000080 */
9775 
9776 /* ===============================================   LR_PD_THR_DIG_ENG   =============================================== */
9777 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos                                (0UL)   /*!< RRM LR_PD_THR_DIG_ENG: LR_PD_THR (Bit 0) */
9778 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Msk                                (0x000000ffUL)  /*!< RRM LR_PD_THR_DIG_ENG: LR_PD_THR (Bitfield-Mask: 0xff) */
9779 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR                                    RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Msk
9780 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_0                                  (0x01 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000001 */
9781 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_1                                  (0x02 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000002 */
9782 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_2                                  (0x04 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000004 */
9783 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_3                                  (0x08 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000008 */
9784 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_4                                  (0x10 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000010 */
9785 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_5                                  (0x20 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000020 */
9786 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_6                                  (0x40 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000040 */
9787 #define RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_7                                  (0x80 << RRM_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos)   /*!<0x00000080 */
9788 
9789 /* ===============================================   LR_RSSI_THR_DIG_ENG   =============================================== */
9790 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos                            (0UL)   /*!< RRM LR_RSSI_THR_DIG_ENG: LR_RSSI_THR (Bit 0) */
9791 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Msk                            (0x000000ffUL)  /*!< RRM LR_RSSI_THR_DIG_ENG: LR_RSSI_THR (Bitfield-Mask: 0xff) */
9792 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR                                RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Msk
9793 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_0                              (0x01 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000001 */
9794 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_1                              (0x02 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000002 */
9795 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_2                              (0x04 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000004 */
9796 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_3                              (0x08 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000008 */
9797 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_4                              (0x10 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000010 */
9798 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_5                              (0x20 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000020 */
9799 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_6                              (0x40 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000040 */
9800 #define RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_7                              (0x80 << RRM_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos)   /*!<0x00000080 */
9801 
9802 /* ===============================================   LR_AAC_THR_DIG_ENG   =============================================== */
9803 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos                              (0UL)   /*!< RRM LR_AAC_THR_DIG_ENG: LR_AAC_THR (Bit 0) */
9804 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Msk                              (0x000000ffUL)  /*!< RRM LR_AAC_THR_DIG_ENG: LR_AAC_THR (Bitfield-Mask: 0xff) */
9805 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR                                  RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Msk
9806 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_0                                (0x01 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000001 */
9807 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_1                                (0x02 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000002 */
9808 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_2                                (0x04 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000004 */
9809 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_3                                (0x08 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000008 */
9810 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_4                                (0x10 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000010 */
9811 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_5                                (0x20 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000020 */
9812 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_6                                (0x40 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000040 */
9813 #define RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_7                                (0x80 << RRM_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos)   /*!<0x00000080 */
9814 
9815 /* ===============================================   DTB0_DIG_ENG   =============================================== */
9816 #define RRM_DTB0_DIG_ENG_DTB_EN_Pos                                        (0UL)   /*!< RRM DTB0_DIG_ENG: DTB_EN (Bit 0) */
9817 #define RRM_DTB0_DIG_ENG_DTB_EN_Msk                                        (0x00000001UL)  /*!< RRM DTB0_DIG_ENG: DTB_EN (Bitfield-Mask: 0x1) */
9818 #define RRM_DTB0_DIG_ENG_DTB_EN                                            RRM_DTB0_DIG_ENG_DTB_EN_Msk
9819 #define RRM_DTB0_DIG_ENG_DTB_CFG_Pos                                       (1UL)   /*!< RRM DTB0_DIG_ENG: DTB_CFG (Bit 1) */
9820 #define RRM_DTB0_DIG_ENG_DTB_CFG_Msk                                       (0x0000001eUL)  /*!< RRM DTB0_DIG_ENG: DTB_CFG (Bitfield-Mask: 0xf) */
9821 #define RRM_DTB0_DIG_ENG_DTB_CFG                                           RRM_DTB0_DIG_ENG_DTB_CFG_Msk
9822 #define RRM_DTB0_DIG_ENG_DTB_CFG_0                                         (0x1 << RRM_DTB0_DIG_ENG_DTB_CFG_Pos)   /*!<0x00000002 */
9823 #define RRM_DTB0_DIG_ENG_DTB_CFG_1                                         (0x2 << RRM_DTB0_DIG_ENG_DTB_CFG_Pos)   /*!<0x00000004 */
9824 #define RRM_DTB0_DIG_ENG_DTB_CFG_2                                         (0x4 << RRM_DTB0_DIG_ENG_DTB_CFG_Pos)   /*!<0x00000008 */
9825 #define RRM_DTB0_DIG_ENG_DTB_CFG_3                                         (0x8 << RRM_DTB0_DIG_ENG_DTB_CFG_Pos)   /*!<0x00000010 */
9826 #define RRM_DTB0_DIG_ENG_SPARE_Pos                                         (5UL)   /*!< RRM DTB0_DIG_ENG: SPARE (Bit 5) */
9827 #define RRM_DTB0_DIG_ENG_SPARE_Msk                                         (0x000000e0UL)  /*!< RRM DTB0_DIG_ENG: SPARE (Bitfield-Mask: 0x7) */
9828 #define RRM_DTB0_DIG_ENG_SPARE                                             RRM_DTB0_DIG_ENG_SPARE_Msk
9829 
9830 
9831 /* ===============================================   DTB5_DIG_ENG   =============================================== */
9832 #define RRM_DTB5_DIG_ENG_RXTX_START_SEL_Pos                                (0UL)   /*!< RRM DTB5_DIG_ENG: RXTX_START_SEL (Bit 0) */
9833 #define RRM_DTB5_DIG_ENG_RXTX_START_SEL_Msk                                (0x00000001UL)  /*!< RRM DTB5_DIG_ENG: RXTX_START_SEL (Bitfield-Mask: 0x1) */
9834 #define RRM_DTB5_DIG_ENG_RXTX_START_SEL                                    RRM_DTB5_DIG_ENG_RXTX_START_SEL_Msk
9835 #define RRM_DTB5_DIG_ENG_TX_ACTIVE_Pos                                     (1UL)   /*!< RRM DTB5_DIG_ENG: TX_ACTIVE (Bit 1) */
9836 #define RRM_DTB5_DIG_ENG_TX_ACTIVE_Msk                                     (0x00000002UL)  /*!< RRM DTB5_DIG_ENG: TX_ACTIVE (Bitfield-Mask: 0x1) */
9837 #define RRM_DTB5_DIG_ENG_TX_ACTIVE                                         RRM_DTB5_DIG_ENG_TX_ACTIVE_Msk
9838 #define RRM_DTB5_DIG_ENG_RX_ACTIVE_Pos                                     (2UL)   /*!< RRM DTB5_DIG_ENG: RX_ACTIVE (Bit 2) */
9839 #define RRM_DTB5_DIG_ENG_RX_ACTIVE_Msk                                     (0x00000004UL)  /*!< RRM DTB5_DIG_ENG: RX_ACTIVE (Bitfield-Mask: 0x1) */
9840 #define RRM_DTB5_DIG_ENG_RX_ACTIVE                                         RRM_DTB5_DIG_ENG_RX_ACTIVE_Msk
9841 #define RRM_DTB5_DIG_ENG_INITIALIZE_Pos                                    (3UL)   /*!< RRM DTB5_DIG_ENG: INITIALIZE (Bit 3) */
9842 #define RRM_DTB5_DIG_ENG_INITIALIZE_Msk                                    (0x00000008UL)  /*!< RRM DTB5_DIG_ENG: INITIALIZE (Bitfield-Mask: 0x1) */
9843 #define RRM_DTB5_DIG_ENG_INITIALIZE                                        RRM_DTB5_DIG_ENG_INITIALIZE_Msk
9844 #define RRM_DTB5_DIG_ENG_PORT_SELECTED_EN_Pos                              (4UL)   /*!< RRM DTB5_DIG_ENG: PORT_SELECTED_EN (Bit 4) */
9845 #define RRM_DTB5_DIG_ENG_PORT_SELECTED_EN_Msk                              (0x00000010UL)  /*!< RRM DTB5_DIG_ENG: PORT_SELECTED_EN (Bitfield-Mask: 0x1) */
9846 #define RRM_DTB5_DIG_ENG_PORT_SELECTED_EN                                  RRM_DTB5_DIG_ENG_PORT_SELECTED_EN_Msk
9847 #define RRM_DTB5_DIG_ENG_SPARE_Pos                                         (5UL)   /*!< RRM DTB5_DIG_ENG: SPARE (Bit 5) */
9848 #define RRM_DTB5_DIG_ENG_SPARE_Msk                                         (0x000000e0UL)  /*!< RRM DTB5_DIG_ENG: SPARE (Bitfield-Mask: 0x7) */
9849 #define RRM_DTB5_DIG_ENG_SPARE                                             RRM_DTB5_DIG_ENG_SPARE_Msk
9850 
9851 
9852 /* ===============================================   MOD0_DIG_TST   =============================================== */
9853 #define RRM_MOD0_DIG_TST_MOD_DIG_TEST_SEL_Pos                              (0UL)   /*!< RRM MOD0_DIG_TST: MOD_DIG_TEST_SEL (Bit 0) */
9854 #define RRM_MOD0_DIG_TST_MOD_DIG_TEST_SEL_Msk                              (0x00000001UL)  /*!< RRM MOD0_DIG_TST: MOD_DIG_TEST_SEL (Bitfield-Mask: 0x1) */
9855 #define RRM_MOD0_DIG_TST_MOD_DIG_TEST_SEL                                  RRM_MOD0_DIG_TST_MOD_DIG_TEST_SEL_Msk
9856 #define RRM_MOD0_DIG_TST_SPARE_Pos                                         (1UL)   /*!< RRM MOD0_DIG_TST: SPARE (Bit 1) */
9857 #define RRM_MOD0_DIG_TST_SPARE_Msk                                         (0x00000006UL)  /*!< RRM MOD0_DIG_TST: SPARE (Bitfield-Mask: 0x3) */
9858 #define RRM_MOD0_DIG_TST_SPARE                                             RRM_MOD0_DIG_TST_SPARE_Msk
9859 #define RRM_MOD0_DIG_TST_PMU_NO_MODULTATION_Pos                            (3UL)   /*!< RRM MOD0_DIG_TST: PMU_NO_MODULTATION (Bit 3) */
9860 #define RRM_MOD0_DIG_TST_PMU_NO_MODULTATION_Msk                            (0x00000008UL)  /*!< RRM MOD0_DIG_TST: PMU_NO_MODULTATION (Bitfield-Mask: 0x1) */
9861 #define RRM_MOD0_DIG_TST_PMU_NO_MODULTATION                                RRM_MOD0_DIG_TST_PMU_NO_MODULTATION_Msk
9862 #define RRM_MOD0_DIG_TST_KFORCE_3_0_Pos                                    (4UL)   /*!< RRM MOD0_DIG_TST: KFORCE_3_0 (Bit 4) */
9863 #define RRM_MOD0_DIG_TST_KFORCE_3_0_Msk                                    (0x000000f0UL)  /*!< RRM MOD0_DIG_TST: KFORCE_3_0 (Bitfield-Mask: 0xf) */
9864 #define RRM_MOD0_DIG_TST_KFORCE_3_0                                        RRM_MOD0_DIG_TST_KFORCE_3_0_Msk
9865 #define RRM_MOD0_DIG_TST_KFORCE_3_0_0                                      (0x1 << RRM_MOD0_DIG_TST_KFORCE_3_0_Pos)   /*!<0x00000010 */
9866 #define RRM_MOD0_DIG_TST_KFORCE_3_0_1                                      (0x2 << RRM_MOD0_DIG_TST_KFORCE_3_0_Pos)   /*!<0x00000020 */
9867 #define RRM_MOD0_DIG_TST_KFORCE_3_0_2                                      (0x4 << RRM_MOD0_DIG_TST_KFORCE_3_0_Pos)   /*!<0x00000040 */
9868 #define RRM_MOD0_DIG_TST_KFORCE_3_0_3                                      (0x8 << RRM_MOD0_DIG_TST_KFORCE_3_0_Pos)   /*!<0x00000080 */
9869 
9870 /* ===============================================   MOD1_DIG_TST   =============================================== */
9871 #define RRM_MOD1_DIG_TST_KFORCE_11_4_Pos                                   (0UL)   /*!< RRM MOD1_DIG_TST: KFORCE_11_4 (Bit 0) */
9872 #define RRM_MOD1_DIG_TST_KFORCE_11_4_Msk                                   (0x000000ffUL)  /*!< RRM MOD1_DIG_TST: KFORCE_11_4 (Bitfield-Mask: 0xff) */
9873 #define RRM_MOD1_DIG_TST_KFORCE_11_4                                       RRM_MOD1_DIG_TST_KFORCE_11_4_Msk
9874 #define RRM_MOD1_DIG_TST_KFORCE_11_4_0                                     (0x01 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000001 */
9875 #define RRM_MOD1_DIG_TST_KFORCE_11_4_1                                     (0x02 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000002 */
9876 #define RRM_MOD1_DIG_TST_KFORCE_11_4_2                                     (0x04 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000004 */
9877 #define RRM_MOD1_DIG_TST_KFORCE_11_4_3                                     (0x08 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000008 */
9878 #define RRM_MOD1_DIG_TST_KFORCE_11_4_4                                     (0x10 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000010 */
9879 #define RRM_MOD1_DIG_TST_KFORCE_11_4_5                                     (0x20 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000020 */
9880 #define RRM_MOD1_DIG_TST_KFORCE_11_4_6                                     (0x40 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000040 */
9881 #define RRM_MOD1_DIG_TST_KFORCE_11_4_7                                     (0x80 << RRM_MOD1_DIG_TST_KFORCE_11_4_Pos)   /*!<0x00000080 */
9882 
9883 /* ===============================================   MOD2_DIG_TST   =============================================== */
9884 #define RRM_MOD2_DIG_TST_KFORCE_19_12_Pos                                  (0UL)   /*!< RRM MOD2_DIG_TST: KFORCE_19_12 (Bit 0) */
9885 #define RRM_MOD2_DIG_TST_KFORCE_19_12_Msk                                  (0x000000ffUL)  /*!< RRM MOD2_DIG_TST: KFORCE_19_12 (Bitfield-Mask: 0xff) */
9886 #define RRM_MOD2_DIG_TST_KFORCE_19_12                                      RRM_MOD2_DIG_TST_KFORCE_19_12_Msk
9887 #define RRM_MOD2_DIG_TST_KFORCE_19_12_0                                    (0x01 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000001 */
9888 #define RRM_MOD2_DIG_TST_KFORCE_19_12_1                                    (0x02 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000002 */
9889 #define RRM_MOD2_DIG_TST_KFORCE_19_12_2                                    (0x04 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000004 */
9890 #define RRM_MOD2_DIG_TST_KFORCE_19_12_3                                    (0x08 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000008 */
9891 #define RRM_MOD2_DIG_TST_KFORCE_19_12_4                                    (0x10 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000010 */
9892 #define RRM_MOD2_DIG_TST_KFORCE_19_12_5                                    (0x20 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000020 */
9893 #define RRM_MOD2_DIG_TST_KFORCE_19_12_6                                    (0x40 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000040 */
9894 #define RRM_MOD2_DIG_TST_KFORCE_19_12_7                                    (0x80 << RRM_MOD2_DIG_TST_KFORCE_19_12_Pos)   /*!<0x00000080 */
9895 
9896 /* ===============================================   MOD3_DIG_TST   =============================================== */
9897 #define RRM_MOD3_DIG_TST_AFORCE_Pos                                        (0UL)   /*!< RRM MOD3_DIG_TST: AFORCE (Bit 0) */
9898 #define RRM_MOD3_DIG_TST_AFORCE_Msk                                        (0x00000007UL)  /*!< RRM MOD3_DIG_TST: AFORCE (Bitfield-Mask: 0x7) */
9899 #define RRM_MOD3_DIG_TST_AFORCE                                            RRM_MOD3_DIG_TST_AFORCE_Msk
9900 #define RRM_MOD3_DIG_TST_AFORCE_0                                          (0x1 << RRM_MOD3_DIG_TST_AFORCE_Pos)   /*!<0x00000001 */
9901 #define RRM_MOD3_DIG_TST_AFORCE_1                                          (0x2 << RRM_MOD3_DIG_TST_AFORCE_Pos)   /*!<0x00000002 */
9902 #define RRM_MOD3_DIG_TST_AFORCE_2                                          (0x4 << RRM_MOD3_DIG_TST_AFORCE_Pos)   /*!<0x00000004 */
9903 #define RRM_MOD3_DIG_TST_MFORCE_Pos                                        (3UL)   /*!< RRM MOD3_DIG_TST: MFORCE (Bit 3) */
9904 #define RRM_MOD3_DIG_TST_MFORCE_Msk                                        (0x000000f8UL)  /*!< RRM MOD3_DIG_TST: MFORCE (Bitfield-Mask: 0x1f) */
9905 #define RRM_MOD3_DIG_TST_MFORCE                                            RRM_MOD3_DIG_TST_MFORCE_Msk
9906 #define RRM_MOD3_DIG_TST_MFORCE_0                                          (0x1 << RRM_MOD3_DIG_TST_MFORCE_Pos)   /*!<0x00000008 */
9907 #define RRM_MOD3_DIG_TST_MFORCE_1                                          (0x2 << RRM_MOD3_DIG_TST_MFORCE_Pos)   /*!<0x00000010 */
9908 #define RRM_MOD3_DIG_TST_MFORCE_2                                          (0x4 << RRM_MOD3_DIG_TST_MFORCE_Pos)   /*!<0x00000020 */
9909 #define RRM_MOD3_DIG_TST_MFORCE_3                                          (0x8 << RRM_MOD3_DIG_TST_MFORCE_Pos)   /*!<0x00000040 */
9910 #define RRM_MOD3_DIG_TST_MFORCE_4                                          (0x10 << RRM_MOD3_DIG_TST_MFORCE_Pos)   /*!<0x00000080 */
9911 
9912 
9913 /* ===============================================   RXADC_ANA_USR   =============================================== */
9914 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Pos                        (0UL)   /*!< RRM RXADC_ANA_USR: RFD_RXADC_DELAYTRIM_I (Bit 0) */
9915 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Msk                        (0x00000007UL)  /*!< RRM RXADC_ANA_USR: RFD_RXADC_DELAYTRIM_I (Bitfield-Mask: 0x7) */
9916 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I                            RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Msk
9917 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_0                          (0x1 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Pos)   /*!<0x00000001 */
9918 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_1                          (0x2 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Pos)   /*!<0x00000002 */
9919 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_2                          (0x4 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Pos)   /*!<0x00000004 */
9920 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Pos                        (3UL)   /*!< RRM RXADC_ANA_USR: RFD_RXADC_DELAYTRIM_Q (Bit 3) */
9921 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Msk                        (0x00000038UL)  /*!< RRM RXADC_ANA_USR: RFD_RXADC_DELAYTRIM_Q (Bitfield-Mask: 0x7) */
9922 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q                            RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Msk
9923 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_0                          (0x1 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Pos)   /*!<0x00000008 */
9924 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_1                          (0x2 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Pos)   /*!<0x00000010 */
9925 #define RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_2                          (0x4 << RRM_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Pos)   /*!<0x00000020 */
9926 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL_Pos                    (6UL)   /*!< RRM RXADC_ANA_USR: RXADC_DELAYTRIM_I_TST_SEL (Bit 6) */
9927 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL_Msk                    (0x00000040UL)  /*!< RRM RXADC_ANA_USR: RXADC_DELAYTRIM_I_TST_SEL (Bitfield-Mask: 0x1) */
9928 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL                        RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL_Msk
9929 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL_Pos                    (7UL)   /*!< RRM RXADC_ANA_USR: RXADC_DELAYTRIM_Q_TST_SEL (Bit 7) */
9930 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL_Msk                    (0x00000080UL)  /*!< RRM RXADC_ANA_USR: SPARE (Bitfield-Mask: 0x1) */
9931 #define RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL                        RRM_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL_Msk
9932 
9933 
9934 /* ===============================================   LDO_ANA_ENG   =============================================== */
9935 #define RRM_LDO_ANA_ENG_SPARE_0_Pos                                        (0UL)   /*!< RRM LDO_ANA_ENG: SPARE_0 (Bit 0) */
9936 #define RRM_LDO_ANA_ENG_SPARE_0_Msk                                        (0x00000001UL)  /*!< RRM LDO_ANA_ENG: SPARE_0 (Bitfield-Mask: 0x1) */
9937 #define RRM_LDO_ANA_ENG_SPARE_0                                            RRM_LDO_ANA_ENG_SPARE_0_Msk
9938 #define RRM_LDO_ANA_ENG_RFD_LDO_TRANSFO_BYPASS_Pos                         (1UL)   /*!< RRM LDO_ANA_ENG: RFD_LDO_TRANSFO_BYPASS (Bit 1) */
9939 #define RRM_LDO_ANA_ENG_RFD_LDO_TRANSFO_BYPASS_Msk                         (0x00000002UL)  /*!< RRM LDO_ANA_ENG: RFD_LDO_TRANSFO_BYPASS (Bitfield-Mask: 0x1) */
9940 #define RRM_LDO_ANA_ENG_RFD_LDO_TRANSFO_BYPASS                             RRM_LDO_ANA_ENG_RFD_LDO_TRANSFO_BYPASS_Msk
9941 #define RRM_LDO_ANA_ENG_RFD_LDO_RXADC_BYPASS_Pos                           (2UL)   /*!< RRM LDO_ANA_ENG: RFD_LDO_RXADC_BYPASS (Bit 2) */
9942 #define RRM_LDO_ANA_ENG_RFD_LDO_RXADC_BYPASS_Msk                           (0x00000004UL)  /*!< RRM LDO_ANA_ENG: RFD_LDO_RXADC_BYPASS (Bitfield-Mask: 0x1) */
9943 #define RRM_LDO_ANA_ENG_RFD_LDO_RXADC_BYPASS                               RRM_LDO_ANA_ENG_RFD_LDO_RXADC_BYPASS_Msk
9944 #define RRM_LDO_ANA_ENG_RFD_LDO_RX_TX_BYPASS_Pos                           (3UL)   /*!< RRM LDO_ANA_ENG: RFD_LDO_RX_TX_BYPASS (Bit 3) */
9945 #define RRM_LDO_ANA_ENG_RFD_LDO_RX_TX_BYPASS_Msk                           (0x00000008UL)  /*!< RRM LDO_ANA_ENG: RFD_LDO_RX_TX_BYPASS (Bitfield-Mask: 0x1) */
9946 #define RRM_LDO_ANA_ENG_RFD_LDO_RX_TX_BYPASS                               RRM_LDO_ANA_ENG_RFD_LDO_RX_TX_BYPASS_Msk
9947 #define RRM_LDO_ANA_ENG_SPARE_1_Pos                                        (4UL)   /*!< RRM LDO_ANA_ENG: SPARE_1 (Bit 4) */
9948 #define RRM_LDO_ANA_ENG_SPARE_1_Msk                                        (0x000000f0UL)  /*!< RRM LDO_ANA_ENG: SPARE_1 (Bitfield-Mask: 0xf) */
9949 #define RRM_LDO_ANA_ENG_SPARE_1                                            RRM_LDO_ANA_ENG_SPARE_1_Msk
9950 
9951 
9952 /* ===============================================   CBIAS0_ANA_ENG   =============================================== */
9953 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos                        (0UL)   /*!< RRM CBIAS0_ANA_ENG: RFD_CBIAS_IBIAS_TRIM (Bit 0) */
9954 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Msk                        (0x0000000fUL)  /*!< RRM CBIAS0_ANA_ENG: RFD_CBIAS_IBIAS_TRIM (Bitfield-Mask: 0xf) */
9955 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM                            RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Msk
9956 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_0                          (0x1 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos)   /*!<0x00000001 */
9957 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_1                          (0x2 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos)   /*!<0x00000002 */
9958 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_2                          (0x4 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos)   /*!<0x00000004 */
9959 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_3                          (0x8 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos)   /*!<0x00000008 */
9960 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos                        (4UL)   /*!< RRM CBIAS0_ANA_ENG: RFD_CBIAS_IPTAT_TRIM (Bit 4) */
9961 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Msk                        (0x000000f0UL)  /*!< RRM CBIAS0_ANA_ENG: RFD_CBIAS_IPTAT_TRIM (Bitfield-Mask: 0xf) */
9962 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM                            RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Msk
9963 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_0                          (0x1 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos)   /*!<0x00000010 */
9964 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_1                          (0x2 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos)   /*!<0x00000020 */
9965 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_2                          (0x4 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos)   /*!<0x00000040 */
9966 #define RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_3                          (0x8 << RRM_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos)   /*!<0x00000080 */
9967 
9968 /* ===============================================   CBIAS1_ANA_ENG   =============================================== */
9969 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Pos                          (0UL)   /*!< RRM CBIAS1_ANA_ENG: RFD_CBIAS_VBG_TRIM (Bit 0) */
9970 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Msk                          (0x0000000fUL)  /*!< RRM CBIAS1_ANA_ENG: RFD_CBIAS_VBG_TRIM (Bitfield-Mask: 0xf) */
9971 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM                              RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Msk
9972 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_0                            (0x1 << RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Pos)   /*!<0x00000001 */
9973 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_1                            (0x2 << RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Pos)   /*!<0x00000002 */
9974 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_2                            (0x4 << RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Pos)   /*!<0x00000004 */
9975 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_3                            (0x8 << RRM_CBIAS1_ANA_ENG_RFD_CBIAS_VBG_TRIM_Pos)   /*!<0x00000008 */
9976 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_ENA_ATB_CURR_Pos                      (4UL)   /*!< RRM CBIAS1_ANA_ENG: RFD_CBIAS_ENA_ATB_CURR (Bit 4) */
9977 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_ENA_ATB_CURR_Msk                      (0x00000010UL)  /*!< RRM CBIAS1_ANA_ENG: RFD_CBIAS_ENA_ATB_CURR (Bitfield-Mask: 0x1) */
9978 #define RRM_CBIAS1_ANA_ENG_RFD_CBIAS_ENA_ATB_CURR                          RRM_CBIAS1_ANA_ENG_RFD_CBIAS_ENA_ATB_CURR_Msk
9979 #define RRM_CBIAS1_ANA_ENG_CBIAS_CURR2_PREBOOST_Pos                        (5UL)   /*!< RRM CBIAS1_ANA_ENG: CBIAS_CURR2_PREBOOST (Bit 5) */
9980 #define RRM_CBIAS1_ANA_ENG_CBIAS_CURR2_PREBOOST_Msk                        (0x00000020UL)  /*!< RRM CBIAS1_ANA_ENG: CBIAS_CURR2_PREBOOST (Bitfield-Mask: 0x1) */
9981 #define RRM_CBIAS1_ANA_ENG_CBIAS_CURR2_PREBOOST                            RRM_CBIAS1_ANA_ENG_CBIAS_CURR2_PREBOOST_Msk
9982 #define RRM_CBIAS1_ANA_ENG_CBIAS_VBG_TRIM_TST_SEL_Pos                      (6UL)   /*!< RRM CBIAS1_ANA_ENG: CBIAS_VBG_TRIM_TST_SEL (Bit 6) */
9983 #define RRM_CBIAS1_ANA_ENG_CBIAS_VBG_TRIM_TST_SEL_Msk                      (0x00000040UL)  /*!< RRM CBIAS1_ANA_ENG: CBIAS_VBG_TRIM_TST_SEL (Bitfield-Mask: 0x1) */
9984 #define RRM_CBIAS1_ANA_ENG_CBIAS_VBG_TRIM_TST_SEL                          RRM_CBIAS1_ANA_ENG_CBIAS_VBG_TRIM_TST_SEL_Msk
9985 #define RRM_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL_Pos                         (7UL)   /*!< RRM CBIAS1_ANA_ENG: CBIAS0_TRIM_TST_SEL (Bit 7) */
9986 #define RRM_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL_Msk                         (0x00000080UL)  /*!< RRM CBIAS1_ANA_ENG: CBIAS0_TRIM_TST_SEL (Bitfield-Mask: 0x1) */
9987 #define RRM_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL                             RRM_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL_Msk
9988 
9989 /* ===============================================   CBIAS_ANA_TEST   =============================================== */
9990 #define RRM_CBIAS_ANA_TEST_CBIAS_ANA_TST_SEL_Pos                           (0UL)   /*!< RRM CBIAS_ANA_TEST: CBIAS_ANA_TST_SEL (Bit 0) */
9991 #define RRM_CBIAS_ANA_TEST_CBIAS_ANA_TST_SEL_Msk                           (0x00000001UL)  /*!< RRM CBIAS_ANA_TEST: CBIAS_ANA_TST_SEL (Bitfield-Mask: 0x1) */
9992 #define RRM_CBIAS_ANA_TEST_CBIAS_ANA_TST_SEL                               RRM_CBIAS_ANA_TEST_CBIAS_ANA_TST_SEL_Msk
9993 #define RRM_CBIAS_ANA_TEST_SPARE_0_Pos                                     (1UL)   /*!< RRM CBIAS_ANA_TEST: SPARE_0 (Bit 1) */
9994 #define RRM_CBIAS_ANA_TEST_SPARE_0_Msk                                     (0x00000002UL)  /*!< RRM CBIAS_ANA_TEST: SPARE_0 (Bitfield-Mask: 0x1) */
9995 #define RRM_CBIAS_ANA_TEST_SPARE_0                                         RRM_CBIAS_ANA_TEST_SPARE_0_Msk
9996 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_CORE_Pos                          (2UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_CORE (Bit 2) */
9997 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_CORE_Msk                          (0x00000004UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_CORE (Bitfield-Mask: 0x1) */
9998 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_CORE                              RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_CORE_Msk
9999 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_1_Pos                        (3UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_SEL_CURR_1 (Bit 3) */
10000 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_1_Msk                        (0x00000008UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_SEL_CURR_1 (Bitfield-Mask: 0x1) */
10001 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_1                            RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_1_Msk
10002 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_2_Pos                        (4UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_SEL_CURR_2 (Bit 4) */
10003 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_2_Msk                        (0x00000010UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_SEL_CURR_2 (Bitfield-Mask: 0x1) */
10004 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_2                            RRM_CBIAS_ANA_TEST_RFD_CBIAS_SEL_CURR_2_Msk
10005 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_NF_OFF_Pos                        (5UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_NF_OFF (Bit 5) */
10006 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_NF_OFF_Msk                        (0x00000020UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_NF_OFF (Bitfield-Mask: 0x1) */
10007 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_NF_OFF                            RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_NF_OFF_Msk
10008 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_BOOST_Pos                     (6UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_VBG_BOOST (Bit 6) */
10009 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_BOOST_Msk                     (0x00000040UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_VBG_BOOST (Bitfield-Mask: 0x1) */
10010 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_BOOST                         RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_BOOST_Msk
10011 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_Pos                           (7UL)   /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_VBG (Bit 7) */
10012 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_Msk                           (0x00000080UL)  /*!< RRM CBIAS_ANA_TEST: RFD_CBIAS_ENA_VBG (Bitfield-Mask: 0x1) */
10013 #define RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG                               RRM_CBIAS_ANA_TEST_RFD_CBIAS_ENA_VBG_Msk
10014 
10015 /* ===============================================   SYNTHCAL0_DIG_OUT   =============================================== */
10016 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos                       (0UL)   /*!< RRM SYNTHCAL0_DIG_OUT: VCO_CALAMP_OUT_6_0 (Bit 0) */
10017 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Msk                       (0x0000007fUL)  /*!< RRM SYNTHCAL0_DIG_OUT: VCO_CALAMP_OUT_6_0 (Bitfield-Mask: 0x7f) */
10018 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0                           RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Msk
10019 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_0                         (0x1 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000001 */
10020 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_1                         (0x2 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000002 */
10021 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_2                         (0x4 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000004 */
10022 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_3                         (0x8 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000008 */
10023 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_4                         (0x10 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000010 */
10024 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_5                         (0x20 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000020 */
10025 #define RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_6                         (0x40 << RRM_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos)   /*!<0x00000040 */
10026 #define RRM_SYNTHCAL0_DIG_OUT_RESERVE_Pos                                  (7UL)   /*!< RRM SYNTHCAL0_DIG_OUT: RESERVE (Bit 7) */
10027 #define RRM_SYNTHCAL0_DIG_OUT_RESERVE_Msk                                  (0x00000080UL)  /*!< RRM SYNTHCAL0_DIG_OUT: RESERVE (Bitfield-Mask: 0x1) */
10028 #define RRM_SYNTHCAL0_DIG_OUT_RESERVE                                      RRM_SYNTHCAL0_DIG_OUT_RESERVE_Msk
10029 
10030 /* ===============================================   SYNTHCAL1_DIG_OUT   =============================================== */
10031 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos                      (0UL)   /*!< RRM SYNTHCAL1_DIG_OUT: VCO_CALAMP_OUT_10_7 (Bit 0) */
10032 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Msk                      (0x0000000fUL)  /*!< RRM SYNTHCAL1_DIG_OUT: VCO_CALAMP_OUT_10_7 (Bitfield-Mask: 0xf) */
10033 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7                          RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Msk
10034 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_0                        (0x1 << RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos)   /*!<0x00000001 */
10035 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_1                        (0x2 << RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos)   /*!<0x00000002 */
10036 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_2                        (0x4 << RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos)   /*!<0x00000004 */
10037 #define RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_3                        (0x8 << RRM_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos)   /*!<0x00000008 */
10038 #define RRM_SYNTHCAL1_DIG_OUT_SPARE_Pos                                    (4UL)   /*!< RRM SYNTHCAL1_DIG_OUT: SPARE (Bit 4) */
10039 #define RRM_SYNTHCAL1_DIG_OUT_SPARE_Msk                                    (0x000000f0UL)  /*!< RRM SYNTHCAL1_DIG_OUT: SPARE (Bitfield-Mask: 0xf) */
10040 #define RRM_SYNTHCAL1_DIG_OUT_SPARE                                        RRM_SYNTHCAL1_DIG_OUT_SPARE_Msk
10041 
10042 /* ===============================================   SYNTHCAL2_DIG_OUT   =============================================== */
10043 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos                          (0UL)   /*!< RRM SYNTHCAL2_DIG_OUT: VCO_CALFREQ_OUT (Bit 0) */
10044 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Msk                          (0x0000007fUL)  /*!< RRM SYNTHCAL2_DIG_OUT: VCO_CALFREQ_OUT (Bitfield-Mask: 0x7f) */
10045 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT                              RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Msk
10046 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_0                            (0x1 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000001 */
10047 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_1                            (0x2 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000002 */
10048 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_2                            (0x4 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000004 */
10049 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_3                            (0x8 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000008 */
10050 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_4                            (0x10 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000010 */
10051 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_5                            (0x20 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000020 */
10052 #define RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_6                            (0x40 << RRM_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos)   /*!<0x00000040 */
10053 #define RRM_SYNTHCAL2_DIG_OUT_RESERVE_Pos                                  (7UL)   /*!< RRM SYNTHCAL2_DIG_OUT: RESERVE (Bit 7) */
10054 #define RRM_SYNTHCAL2_DIG_OUT_RESERVE_Msk                                  (0x00000080UL)  /*!< RRM SYNTHCAL2_DIG_OUT: RESERVE (Bitfield-Mask: 0x1) */
10055 #define RRM_SYNTHCAL2_DIG_OUT_RESERVE                                      RRM_SYNTHCAL2_DIG_OUT_RESERVE_Msk
10056 
10057 /* ===============================================   SYNTHCAL3_DIG_OUT   =============================================== */
10058 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos                       (0UL)   /*!< RRM SYNTHCAL3_DIG_OUT: SYNTHCAL_DEBUG_BUS (Bit 0) */
10059 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Msk                       (0x0000000fUL)  /*!< RRM SYNTHCAL3_DIG_OUT: SYNTHCAL_DEBUG_BUS (Bitfield-Mask: 0xf) */
10060 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS                           RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Msk
10061 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_0                         (0x1 << RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos)   /*!<0x00000001 */
10062 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_1                         (0x2 << RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos)   /*!<0x00000002 */
10063 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_2                         (0x4 << RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos)   /*!<0x00000004 */
10064 #define RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_3                         (0x8 << RRM_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos)   /*!<0x00000008 */
10065 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_Pos                                  (4UL)   /*!< RRM SYNTHCAL3_DIG_OUT: RESERVE (Bit 4) */
10066 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_Msk                                  (0x000000f0UL)  /*!< RRM SYNTHCAL3_DIG_OUT: RESERVE (Bitfield-Mask: 0xf) */
10067 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE                                      RRM_SYNTHCAL3_DIG_OUT_RESERVE_Msk
10068 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_0                                    (0x1 << RRM_SYNTHCAL3_DIG_OUT_RESERVE_Pos)   /*!<0x00000010 */
10069 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_1                                    (0x2 << RRM_SYNTHCAL3_DIG_OUT_RESERVE_Pos)   /*!<0x00000020 */
10070 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_2                                    (0x4 << RRM_SYNTHCAL3_DIG_OUT_RESERVE_Pos)   /*!<0x00000040 */
10071 #define RRM_SYNTHCAL3_DIG_OUT_RESERVE_3                                    (0x8 << RRM_SYNTHCAL3_DIG_OUT_RESERVE_Pos)   /*!<0x00000080 */
10072 
10073 /* ===============================================   SYNTHCAL4_DIG_OUT   =============================================== */
10074 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos                     (0UL)   /*!< RRM SYNTHCAL4_DIG_OUT: MOD_REF_DAC_WORD_OUT (Bit 0) */
10075 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Msk                     (0x0000003fUL)  /*!< RRM SYNTHCAL4_DIG_OUT: MOD_REF_DAC_WORD_OUT (Bitfield-Mask: 0x3f) */
10076 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT                         RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Msk
10077 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_0                       (0x1 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000001 */
10078 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_1                       (0x2 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000002 */
10079 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_2                       (0x4 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000004 */
10080 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_3                       (0x8 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000008 */
10081 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_4                       (0x10 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000010 */
10082 #define RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_5                       (0x20 << RRM_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos)   /*!<0x00000020 */
10083 #define RRM_SYNTHCAL4_DIG_OUT_SPARE_Pos                                    (6UL)   /*!< RRM SYNTHCAL4_DIG_OUT: SPARE (Bit 6) */
10084 #define RRM_SYNTHCAL4_DIG_OUT_SPARE_Msk                                    (0x000000c0UL)  /*!< RRM SYNTHCAL4_DIG_OUT: SPARE (Bitfield-Mask: 0x3) */
10085 #define RRM_SYNTHCAL4_DIG_OUT_SPARE                                        RRM_SYNTHCAL4_DIG_OUT_SPARE_Msk
10086 
10087 /* ===============================================   SYNTHCAL5_DIG_OUT   =============================================== */
10088 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos                           (0UL)   /*!< RRM SYNTHCAL5_DIG_OUT: CBP_CALIB_WORD (Bit 0) */
10089 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Msk                           (0x0000000fUL)  /*!< RRM SYNTHCAL5_DIG_OUT: CBP_CALIB_WORD (Bitfield-Mask: 0xf) */
10090 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD                               RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Msk
10091 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_0                             (0x1 << RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos)   /*!<0x00000001 */
10092 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_1                             (0x2 << RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos)   /*!<0x00000002 */
10093 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_2                             (0x4 << RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos)   /*!<0x00000004 */
10094 #define RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_3                             (0x8 << RRM_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos)   /*!<0x00000008 */
10095 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_Pos                                  (4UL)   /*!< RRM SYNTHCAL5_DIG_OUT: RESERVE (Bit 4) */
10096 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_Msk                                  (0x000000f0UL)  /*!< RRM SYNTHCAL5_DIG_OUT: RESERVE (Bitfield-Mask: 0xf) */
10097 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE                                      RRM_SYNTHCAL5_DIG_OUT_RESERVE_Msk
10098 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_0                                    (0x1 << RRM_SYNTHCAL5_DIG_OUT_RESERVE_Pos)   /*!<0x00000010 */
10099 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_1                                    (0x2 << RRM_SYNTHCAL5_DIG_OUT_RESERVE_Pos)   /*!<0x00000020 */
10100 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_2                                    (0x4 << RRM_SYNTHCAL5_DIG_OUT_RESERVE_Pos)   /*!<0x00000040 */
10101 #define RRM_SYNTHCAL5_DIG_OUT_RESERVE_3                                    (0x8 << RRM_SYNTHCAL5_DIG_OUT_RESERVE_Pos)   /*!<0x00000080 */
10102 
10103 /* ===============================================   FSM_STATUS_DIG_OUT   =============================================== */
10104 #define RRM_FSM_STATUS_DIG_OUT_STATUS_Pos                                  (0UL)   /*!< RRM FSM_STATUS_DIG_OUT: STATUS (Bit 0) */
10105 #define RRM_FSM_STATUS_DIG_OUT_STATUS_Msk                                  (0x0000001fUL)  /*!< RRM FSM_STATUS_DIG_OUT: STATUS (Bitfield-Mask: 0x1f) */
10106 #define RRM_FSM_STATUS_DIG_OUT_STATUS                                      RRM_FSM_STATUS_DIG_OUT_STATUS_Msk
10107 #define RRM_FSM_STATUS_DIG_OUT_STATUS_0                                    (0x1 << RRM_FSM_STATUS_DIG_OUT_STATUS_Pos)   /*!<0x00000001 */
10108 #define RRM_FSM_STATUS_DIG_OUT_STATUS_1                                    (0x2 << RRM_FSM_STATUS_DIG_OUT_STATUS_Pos)   /*!<0x00000002 */
10109 #define RRM_FSM_STATUS_DIG_OUT_STATUS_2                                    (0x4 << RRM_FSM_STATUS_DIG_OUT_STATUS_Pos)   /*!<0x00000004 */
10110 #define RRM_FSM_STATUS_DIG_OUT_STATUS_3                                    (0x8 << RRM_FSM_STATUS_DIG_OUT_STATUS_Pos)   /*!<0x00000008 */
10111 #define RRM_FSM_STATUS_DIG_OUT_STATUS_4                                    (0x10 << RRM_FSM_STATUS_DIG_OUT_STATUS_Pos)   /*!<0x00000010 */
10112 #define RRM_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR_Pos                         (7UL)   /*!< RRM FSM_STATUS_DIG_OUT: SYNTH_CAL_ERROR (Bit 7) */
10113 #define RRM_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR_Msk                         (0x00000080UL)  /*!< RRM FSM_STATUS_DIG_OUT: SYNTH_CAL_ERROR (Bitfield-Mask: 0x1) */
10114 #define RRM_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR                             RRM_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR_Msk
10115 
10116 /* ===============================================   IRQ_STATUS_DIG_OUT   =============================================== */
10117 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos                                 (0UL)   /*!< RRM IRQ_STATUS_DIG_OUT: RESERVE (Bit 0) */
10118 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_Msk                                 (0x000000ffUL)  /*!< RRM IRQ_STATUS_DIG_OUT: RESERVE (Bitfield-Mask: 0xff) */
10119 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE                                     RRM_IRQ_STATUS_DIG_OUT_RESERVE_Msk
10120 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_0                                   (0x01 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000001 */
10121 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_1                                   (0x02 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000002 */
10122 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_2                                   (0x04 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000004 */
10123 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_3                                   (0x08 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000008 */
10124 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_4                                   (0x10 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000010 */
10125 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_5                                   (0x20 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000020 */
10126 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_6                                   (0x40 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000040 */
10127 #define RRM_IRQ_STATUS_DIG_OUT_RESERVE_7                                   (0x80 << RRM_IRQ_STATUS_DIG_OUT_RESERVE_Pos)   /*!<0x00000080 */
10128 
10129 
10130 /* ===============================================   RSSI0_DIG_OUT   =============================================== */
10131 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos                            (0UL)   /*!< RRM RSSI0_DIG_OUT: RSSI_MEAS_OUT_7_0 (Bit 0) */
10132 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Msk                            (0x000000ffUL)  /*!< RRM RSSI0_DIG_OUT: RSSI_MEAS_OUT_7_0 (Bitfield-Mask: 0xff) */
10133 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0                                RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Msk
10134 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_0                              (0x01 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000001 */
10135 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_1                              (0x02 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000002 */
10136 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_2                              (0x04 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000004 */
10137 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_3                              (0x08 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000008 */
10138 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_4                              (0x10 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000010 */
10139 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_5                              (0x20 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000020 */
10140 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_6                              (0x40 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000040 */
10141 #define RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_7                              (0x80 << RRM_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos)   /*!<0x00000080 */
10142 
10143 /* ===============================================   RSSI1_DIG_OUT   =============================================== */
10144 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos                           (0UL)   /*!< RRM RSSI1_DIG_OUT: RSSI_MEAS_OUT_15_8 (Bit 0) */
10145 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Msk                           (0x000000ffUL)  /*!< RRM RSSI1_DIG_OUT: RSSI_MEAS_OUT_15_8 (Bitfield-Mask: 0xff) */
10146 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8                               RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Msk
10147 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_0                             (0x01 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000001 */
10148 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_1                             (0x02 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000002 */
10149 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_2                             (0x04 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000004 */
10150 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_3                             (0x08 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000008 */
10151 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_4                             (0x10 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000010 */
10152 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_5                             (0x20 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000020 */
10153 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_6                             (0x40 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000040 */
10154 #define RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_7                             (0x80 << RRM_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos)   /*!<0x00000080 */
10155 
10156 /* ===============================================   AGC_DIG_OUT   =============================================== */
10157 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_Pos                                    (0UL)   /*!< RRM AGC_DIG_OUT: AGC_ATT_OUT (Bit 0) */
10158 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_Msk                                    (0x0000000fUL)  /*!< RRM AGC_DIG_OUT: AGC_ATT_OUT (Bitfield-Mask: 0xf) */
10159 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT                                        RRM_AGC_DIG_OUT_AGC_ATT_OUT_Msk
10160 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_0                                      (0x1 << RRM_AGC_DIG_OUT_AGC_ATT_OUT_Pos)   /*!<0x00000001 */
10161 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_1                                      (0x2 << RRM_AGC_DIG_OUT_AGC_ATT_OUT_Pos)   /*!<0x00000002 */
10162 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_2                                      (0x4 << RRM_AGC_DIG_OUT_AGC_ATT_OUT_Pos)   /*!<0x00000004 */
10163 #define RRM_AGC_DIG_OUT_AGC_ATT_OUT_3                                      (0x8 << RRM_AGC_DIG_OUT_AGC_ATT_OUT_Pos)   /*!<0x00000008 */
10164 #define RRM_AGC_DIG_OUT_RESERVE_Pos                                        (4UL)   /*!< RRM AGC_DIG_OUT: RESERVE (Bit 4) */
10165 #define RRM_AGC_DIG_OUT_RESERVE_Msk                                        (0x000000f0UL)  /*!< RRM AGC_DIG_OUT: RESERVE (Bitfield-Mask: 0xf) */
10166 #define RRM_AGC_DIG_OUT_RESERVE                                            RRM_AGC_DIG_OUT_RESERVE_Msk
10167 #define RRM_AGC_DIG_OUT_RESERVE_0                                          (0x1 << RRM_AGC_DIG_OUT_RESERVE_Pos)   /*!<0x00000010 */
10168 #define RRM_AGC_DIG_OUT_RESERVE_1                                          (0x2 << RRM_AGC_DIG_OUT_RESERVE_Pos)   /*!<0x00000020 */
10169 #define RRM_AGC_DIG_OUT_RESERVE_2                                          (0x4 << RRM_AGC_DIG_OUT_RESERVE_Pos)   /*!<0x00000040 */
10170 #define RRM_AGC_DIG_OUT_RESERVE_3                                          (0x8 << RRM_AGC_DIG_OUT_RESERVE_Pos)   /*!<0x00000080 */
10171 
10172 /* ===============================================   DEMOD_DIG_OUT   =============================================== */
10173 #define RRM_DEMOD_DIG_OUT_CI_FIELD_Pos                                     (0UL)   /*!< RRM DEMOD_DIG_OUT: CI_FIELD (Bit 0) */
10174 #define RRM_DEMOD_DIG_OUT_CI_FIELD_Msk                                     (0x00000003UL)  /*!< RRM DEMOD_DIG_OUT: CI_FIELD (Bitfield-Mask: 0x3) */
10175 #define RRM_DEMOD_DIG_OUT_CI_FIELD                                         RRM_DEMOD_DIG_OUT_CI_FIELD_Msk
10176 #define RRM_DEMOD_DIG_OUT_CI_FIELD_0                                       (0x1 << RRM_DEMOD_DIG_OUT_CI_FIELD_Pos)   /*!<0x00000001 */
10177 #define RRM_DEMOD_DIG_OUT_CI_FIELD_1                                       (0x2 << RRM_DEMOD_DIG_OUT_CI_FIELD_Pos)   /*!<0x00000002 */
10178 #define RRM_DEMOD_DIG_OUT_AAC_FOUND_Pos                                    (2UL)   /*!< RRM DEMOD_DIG_OUT: AAC_FOUND (Bit 2) */
10179 #define RRM_DEMOD_DIG_OUT_AAC_FOUND_Msk                                    (0x00000004UL)  /*!< RRM DEMOD_DIG_OUT: AAC_FOUND (Bitfield-Mask: 0x1) */
10180 #define RRM_DEMOD_DIG_OUT_AAC_FOUND                                        RRM_DEMOD_DIG_OUT_AAC_FOUND_Msk
10181 #define RRM_DEMOD_DIG_OUT_PD_FOUND_Pos                                     (3UL)   /*!< RRM DEMOD_DIG_OUT: PD_FOUND (Bit 3) */
10182 #define RRM_DEMOD_DIG_OUT_PD_FOUND_Msk                                     (0x00000008UL)  /*!< RRM DEMOD_DIG_OUT: PD_FOUND (Bitfield-Mask: 0x1) */
10183 #define RRM_DEMOD_DIG_OUT_PD_FOUND                                         RRM_DEMOD_DIG_OUT_PD_FOUND_Msk
10184 #define RRM_DEMOD_DIG_OUT_RX_END_Pos                                       (4UL)   /*!< RRM DEMOD_DIG_OUT: RX_END (Bit 4) */
10185 #define RRM_DEMOD_DIG_OUT_RX_END_Msk                                       (0x00000010UL)  /*!< RRM DEMOD_DIG_OUT: RX_END (Bitfield-Mask: 0x1) */
10186 #define RRM_DEMOD_DIG_OUT_RX_END                                           RRM_DEMOD_DIG_OUT_RX_END_Msk
10187 #define RRM_DEMOD_DIG_OUT_RESERVE_Pos                                      (5UL)   /*!< RRM DEMOD_DIG_OUT: RESERVE (Bit 5) */
10188 #define RRM_DEMOD_DIG_OUT_RESERVE_Msk                                      (0x000000e0UL)  /*!< RRM DEMOD_DIG_OUT: RESERVE (Bitfield-Mask: 0x7) */
10189 #define RRM_DEMOD_DIG_OUT_RESERVE                                          RRM_DEMOD_DIG_OUT_RESERVE_Msk
10190 #define RRM_DEMOD_DIG_OUT_RESERVE_0                                        (0x1 << RRM_DEMOD_DIG_OUT_RESERVE_Pos)   /*!<0x00000020 */
10191 #define RRM_DEMOD_DIG_OUT_RESERVE_1                                        (0x2 << RRM_DEMOD_DIG_OUT_RESERVE_Pos)   /*!<0x00000040 */
10192 #define RRM_DEMOD_DIG_OUT_RESERVE_2                                        (0x4 << RRM_DEMOD_DIG_OUT_RESERVE_Pos)   /*!<0x00000080 */
10193 
10194 /* ===============================================   AGC0_ANA_TST   =============================================== */
10195 #define RRM_AGC0_ANA_TST_AGC0_ANA_TST_SEL_Pos                              (0UL)   /*!< RRM AGC0_ANA_TST: AGC0_ANA_TST_SEL (Bit 0) */
10196 #define RRM_AGC0_ANA_TST_AGC0_ANA_TST_SEL_Msk                              (0x00000001UL)  /*!< RRM AGC0_ANA_TST: AGC0_ANA_TST_SEL (Bitfield-Mask: 0x1) */
10197 #define RRM_AGC0_ANA_TST_AGC0_ANA_TST_SEL                                  RRM_AGC0_ANA_TST_AGC0_ANA_TST_SEL_Msk
10198 #define RRM_AGC0_ANA_TST_AGC_ANT_Pos                                       (1UL)   /*!< RRM AGC0_ANA_TST: AGC_ANT (Bit 1) */
10199 #define RRM_AGC0_ANA_TST_AGC_ANT_Msk                                       (0x0000000eUL)  /*!< RRM AGC0_ANA_TST: AGC_ANT (Bitfield-Mask: 0x7) */
10200 #define RRM_AGC0_ANA_TST_AGC_ANT                                           RRM_AGC0_ANA_TST_AGC_ANT_Msk
10201 #define RRM_AGC0_ANA_TST_AGC_ANT_0                                         (0x1 << RRM_AGC0_ANA_TST_AGC_ANT_Pos)   /*!<0x00000002 */
10202 #define RRM_AGC0_ANA_TST_AGC_ANT_1                                         (0x2 << RRM_AGC0_ANA_TST_AGC_ANT_Pos)   /*!<0x00000004 */
10203 #define RRM_AGC0_ANA_TST_AGC_ANT_2                                         (0x4 << RRM_AGC0_ANA_TST_AGC_ANT_Pos)   /*!<0x00000008 */
10204 #define RRM_AGC0_ANA_TST_AGC_LNA_Pos                                       (4UL)   /*!< RRM AGC0_ANA_TST: AGC_LNA (Bit 4) */
10205 #define RRM_AGC0_ANA_TST_AGC_LNA_Msk                                       (0x00000010UL)  /*!< RRM AGC0_ANA_TST: AGC_LNA (Bitfield-Mask: 0x1) */
10206 #define RRM_AGC0_ANA_TST_AGC_LNA                                           RRM_AGC0_ANA_TST_AGC_LNA_Msk
10207 #define RRM_AGC0_ANA_TST_SPARE_Pos                                         (5UL)   /*!< RRM AGC0_ANA_TST: SPARE (Bit 5) */
10208 #define RRM_AGC0_ANA_TST_SPARE_Msk                                         (0x000000e0UL)  /*!< RRM AGC0_ANA_TST: SPARE (Bitfield-Mask: 0x7) */
10209 #define RRM_AGC0_ANA_TST_SPARE                                             RRM_AGC0_ANA_TST_SPARE_Msk
10210 
10211 /* ===============================================   AGC1_ANA_TST   =============================================== */
10212 #define RRM_AGC1_ANA_TST_AGC1_ANA_TST_SEL_Pos                              (0UL)   /*!< RRM AGC1_ANA_TST: AGC1_ANA_TST_SEL (Bit 0) */
10213 #define RRM_AGC1_ANA_TST_AGC1_ANA_TST_SEL_Msk                              (0x00000001UL)  /*!< RRM AGC1_ANA_TST: AGC1_ANA_TST_SEL (Bitfield-Mask: 0x1) */
10214 #define RRM_AGC1_ANA_TST_AGC1_ANA_TST_SEL                                  RRM_AGC1_ANA_TST_AGC1_ANA_TST_SEL_Msk
10215 #define RRM_AGC1_ANA_TST_AGC_IFATT_Pos                                     (1UL)   /*!< RRM AGC1_ANA_TST: AGC_IFATT (Bit 1) */
10216 #define RRM_AGC1_ANA_TST_AGC_IFATT_Msk                                     (0x0000003eUL)  /*!< RRM AGC1_ANA_TST: AGC_IFATT (Bitfield-Mask: 0x1f) */
10217 #define RRM_AGC1_ANA_TST_AGC_IFATT                                         RRM_AGC1_ANA_TST_AGC_IFATT_Msk
10218 #define RRM_AGC1_ANA_TST_AGC_IFATT_0                                       (0x1 << RRM_AGC1_ANA_TST_AGC_IFATT_Pos)   /*!<0x00000002 */
10219 #define RRM_AGC1_ANA_TST_AGC_IFATT_1                                       (0x2 << RRM_AGC1_ANA_TST_AGC_IFATT_Pos)   /*!<0x00000004 */
10220 #define RRM_AGC1_ANA_TST_AGC_IFATT_2                                       (0x4 << RRM_AGC1_ANA_TST_AGC_IFATT_Pos)   /*!<0x00000008 */
10221 #define RRM_AGC1_ANA_TST_AGC_IFATT_3                                       (0x8 << RRM_AGC1_ANA_TST_AGC_IFATT_Pos)   /*!<0x00000010 */
10222 #define RRM_AGC1_ANA_TST_AGC_IFATT_4                                       (0x10 << RRM_AGC1_ANA_TST_AGC_IFATT_Pos)   /*!<0x00000020 */
10223 #define RRM_AGC1_ANA_TST_SPARE_Pos                                         (6UL)   /*!< RRM AGC1_ANA_TST: SPARE (Bit 6) */
10224 #define RRM_AGC1_ANA_TST_SPARE_Msk                                         (0x000000c0UL)  /*!< RRM AGC1_ANA_TST: SPARE (Bitfield-Mask: 0x3) */
10225 #define RRM_AGC1_ANA_TST_SPARE                                             RRM_AGC1_ANA_TST_SPARE_Msk
10226 
10227 /* ===============================================   AGC2_ANA_TST   =============================================== */
10228 #define RRM_AGC2_ANA_TST_AGC2_ANA_TST_SEL_Pos                              (0UL)   /*!< RRM AGC2_ANA_TST: AGC2_ANA_TST_SEL (Bit 0) */
10229 #define RRM_AGC2_ANA_TST_AGC2_ANA_TST_SEL_Msk                              (0x00000001UL)  /*!< RRM AGC2_ANA_TST: AGC2_ANA_TST_SEL (Bitfield-Mask: 0x1) */
10230 #define RRM_AGC2_ANA_TST_AGC2_ANA_TST_SEL                                  RRM_AGC2_ANA_TST_AGC2_ANA_TST_SEL_Msk
10231 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Pos                         (1UL)   /*!< RRM AGC2_ANA_TST: AGC_ANTENNAE_USR_TRIM (Bit 1) */
10232 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Msk                         (0x0000000eUL)  /*!< RRM AGC2_ANA_TST: AGC_ANTENNAE_USR_TRIM (Bitfield-Mask: 0x7) */
10233 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM                             RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Msk
10234 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_0                           (0x1 << RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Pos)   /*!<0x00000002 */
10235 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_1                           (0x2 << RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Pos)   /*!<0x00000004 */
10236 #define RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_2                           (0x4 << RRM_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Pos)   /*!<0x00000008 */
10237 #define RRM_AGC2_ANA_TST_SPARE_Pos                                         (4UL)   /*!< RRM AGC2_ANA_TST: SPARE (Bit 4) */
10238 #define RRM_AGC2_ANA_TST_SPARE_Msk                                         (0x000000f0UL)  /*!< RRM AGC2_ANA_TST: SPARE (Bitfield-Mask: 0xf) */
10239 #define RRM_AGC2_ANA_TST_SPARE                                             RRM_AGC2_ANA_TST_SPARE_Msk
10240 
10241 /* ===============================================   AGC0_DIG_ENG   =============================================== */
10242 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos                                  (0UL)   /*!< RRM AGC0_DIG_ENG: AGC_THR_HIGH (Bit 0) */
10243 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Msk                                  (0x0000003fUL)  /*!< RRM AGC0_DIG_ENG: AGC_THR_HIGH (Bitfield-Mask: 0x3f) */
10244 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH                                      RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Msk
10245 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_0                                    (0x1 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000001 */
10246 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_1                                    (0x2 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000002 */
10247 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_2                                    (0x4 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000004 */
10248 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_3                                    (0x8 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000008 */
10249 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_4                                    (0x10 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000010 */
10250 #define RRM_AGC0_DIG_ENG_AGC_THR_HIGH_5                                    (0x20 << RRM_AGC0_DIG_ENG_AGC_THR_HIGH_Pos)   /*!<0x00000020 */
10251 #define RRM_AGC0_DIG_ENG_AGC_ENABLE_Pos                                    (6UL)   /*!< RRM AGC0_DIG_ENG: AGC_ENABLE (Bit 6) */
10252 #define RRM_AGC0_DIG_ENG_AGC_ENABLE_Msk                                    (0x00000040UL)  /*!< RRM AGC0_DIG_ENG: AGC_ENABLE (Bitfield-Mask: 0x1) */
10253 #define RRM_AGC0_DIG_ENG_AGC_ENABLE                                        RRM_AGC0_DIG_ENG_AGC_ENABLE_Msk
10254 #define RRM_AGC0_DIG_ENG_SPARE_Pos                                         (7UL)   /*!< RRM AGC0_DIG_ENG: SPARE (Bit 7) */
10255 #define RRM_AGC0_DIG_ENG_SPARE_Msk                                         (0x00000080UL)  /*!< RRM AGC0_DIG_ENG: SPARE (Bitfield-Mask: 0x1) */
10256 #define RRM_AGC0_DIG_ENG_SPARE                                             RRM_AGC0_DIG_ENG_SPARE_Msk
10257 
10258 /* ===============================================   AGC1_DIG_ENG   =============================================== */
10259 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos                                 (0UL)   /*!< RRM AGC1_DIG_ENG: AGC_THR_LOW_6 (Bit 0) */
10260 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Msk                                 (0x0000003fUL)  /*!< RRM AGC1_DIG_ENG: AGC_THR_LOW_6 (Bitfield-Mask: 0x3f) */
10261 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6                                     RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Msk
10262 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_0                                   (0x1 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000001 */
10263 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_1                                   (0x2 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000002 */
10264 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_2                                   (0x4 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000004 */
10265 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_3                                   (0x8 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000008 */
10266 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_4                                   (0x10 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000010 */
10267 #define RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_5                                   (0x20 << RRM_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos)   /*!<0x00000020 */
10268 #define RRM_AGC1_DIG_ENG_AGC_AUTOLOCK_Pos                                  (6UL)   /*!< RRM AGC1_DIG_ENG: AGC_AUTOLOCK (Bit 6) */
10269 #define RRM_AGC1_DIG_ENG_AGC_AUTOLOCK_Msk                                  (0x00000040UL)  /*!< RRM AGC1_DIG_ENG: AGC_AUTOLOCK (Bitfield-Mask: 0x1) */
10270 #define RRM_AGC1_DIG_ENG_AGC_AUTOLOCK                                      RRM_AGC1_DIG_ENG_AGC_AUTOLOCK_Msk
10271 #define RRM_AGC1_DIG_ENG_AGC_LOCK_SYNC_Pos                                 (7UL)   /*!< RRM AGC1_DIG_ENG: AGC_LOCK_SYNC (Bit 7) */
10272 #define RRM_AGC1_DIG_ENG_AGC_LOCK_SYNC_Msk                                 (0x00000080UL)  /*!< RRM AGC1_DIG_ENG: AGC_LOCK_SYNC (Bitfield-Mask: 0x1) */
10273 #define RRM_AGC1_DIG_ENG_AGC_LOCK_SYNC                                     RRM_AGC1_DIG_ENG_AGC_LOCK_SYNC_Msk
10274 
10275 /* ===============================================   AGC2_DIG_ENG   =============================================== */
10276 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos                                (0UL)   /*!< RRM AGC2_DIG_ENG: AGC_THR_LOW_12 (Bit 0) */
10277 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Msk                                (0x0000003fUL)  /*!< RRM AGC2_DIG_ENG: AGC_THR_LOW_12 (Bitfield-Mask: 0x3f) */
10278 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12                                    RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Msk
10279 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_0                                  (0x1 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000001 */
10280 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_1                                  (0x2 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000002 */
10281 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_2                                  (0x4 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000004 */
10282 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_3                                  (0x8 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000008 */
10283 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_4                                  (0x10 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000010 */
10284 #define RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_5                                  (0x20 << RRM_AGC2_DIG_ENG_AGC_THR_LOW_12_Pos)   /*!<0x00000020 */
10285 #define RRM_AGC2_DIG_ENG_SPARE_Pos                                         (6UL)   /*!< RRM AGC2_DIG_ENG: SPARE (Bit 6) */
10286 #define RRM_AGC2_DIG_ENG_SPARE_Msk                                         (0x000000c0UL)  /*!< RRM AGC2_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10287 #define RRM_AGC2_DIG_ENG_SPARE                                             RRM_AGC2_DIG_ENG_SPARE_Msk
10288 
10289 /* ===============================================   AGC3_DIG_ENG   =============================================== */
10290 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos                                  (0UL)   /*!< RRM AGC3_DIG_ENG: AUTOLOCK_THR (Bit 0) */
10291 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Msk                                  (0x0000003fUL)  /*!< RRM AGC3_DIG_ENG: AUTOLOCK_THR (Bitfield-Mask: 0x3f) */
10292 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR                                      RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Msk
10293 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_0                                    (0x1 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000001 */
10294 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_1                                    (0x2 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000002 */
10295 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_2                                    (0x4 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000004 */
10296 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_3                                    (0x8 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000008 */
10297 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_4                                    (0x10 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000010 */
10298 #define RRM_AGC3_DIG_ENG_AUTOLOCK_THR_5                                    (0x20 << RRM_AGC3_DIG_ENG_AUTOLOCK_THR_Pos)   /*!<0x00000020 */
10299 #define RRM_AGC3_DIG_ENG_SPARE_Pos                                         (6UL)   /*!< RRM AGC3_DIG_ENG: SPARE (Bit 6) */
10300 #define RRM_AGC3_DIG_ENG_SPARE_Msk                                         (0x000000c0UL)  /*!< RRM AGC3_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10301 #define RRM_AGC3_DIG_ENG_SPARE                                             RRM_AGC3_DIG_ENG_SPARE_Msk
10302 
10303 /* ===============================================   AGC4_DIG_ENG   =============================================== */
10304 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Pos                            (0UL)   /*!< RRM AGC4_DIG_ENG: AGC_HOLD_TIME_FAST (Bit 0) */
10305 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Msk                            (0x0000000fUL)  /*!< RRM AGC4_DIG_ENG: AGC_HOLD_TIME_FAST (Bitfield-Mask: 0xf) */
10306 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST                                RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Msk
10307 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_0                              (0x1 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Pos)   /*!<0x00000001 */
10308 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_1                              (0x2 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Pos)   /*!<0x00000002 */
10309 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_2                              (0x4 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Pos)   /*!<0x00000004 */
10310 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_3                              (0x8 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_FAST_Pos)   /*!<0x00000008 */
10311 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Pos                            (4UL)   /*!< RRM AGC4_DIG_ENG: AGC_HOLD_TIME_SLOW (Bit 4) */
10312 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Msk                            (0x000000f0UL)  /*!< RRM AGC4_DIG_ENG: AGC_HOLD_TIME_SLOW (Bitfield-Mask: 0xf) */
10313 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW                                RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Msk
10314 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_0                              (0x1 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Pos)   /*!<0x00000010 */
10315 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_1                              (0x2 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Pos)   /*!<0x00000020 */
10316 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_2                              (0x4 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Pos)   /*!<0x00000040 */
10317 #define RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_3                              (0x8 << RRM_AGC4_DIG_ENG_AGC_HOLD_TIME_SLOW_Pos)   /*!<0x00000080 */
10318 
10319 /* ===============================================   AGC5_DIG_ENG   =============================================== */
10320 #define RRM_AGC5_DIG_ENG_T_MEAS_Pos                                        (0UL)   /*!< RRM AGC5_DIG_ENG: T_MEAS (Bit 0) */
10321 #define RRM_AGC5_DIG_ENG_T_MEAS_Msk                                        (0x0000000fUL)  /*!< RRM AGC5_DIG_ENG: T_MEAS (Bitfield-Mask: 0xf) */
10322 #define RRM_AGC5_DIG_ENG_T_MEAS                                            RRM_AGC5_DIG_ENG_T_MEAS_Msk
10323 #define RRM_AGC5_DIG_ENG_T_MEAS_0                                          (0x1 << RRM_AGC5_DIG_ENG_T_MEAS_Pos)   /*!<0x00000001 */
10324 #define RRM_AGC5_DIG_ENG_T_MEAS_1                                          (0x2 << RRM_AGC5_DIG_ENG_T_MEAS_Pos)   /*!<0x00000002 */
10325 #define RRM_AGC5_DIG_ENG_T_MEAS_2                                          (0x4 << RRM_AGC5_DIG_ENG_T_MEAS_Pos)   /*!<0x00000004 */
10326 #define RRM_AGC5_DIG_ENG_T_MEAS_3                                          (0x8 << RRM_AGC5_DIG_ENG_T_MEAS_Pos)   /*!<0x00000008 */
10327 #define RRM_AGC5_DIG_ENG_T_INT_Pos                                         (4UL)   /*!< RRM AGC5_DIG_ENG: T_INT (Bit 4) */
10328 #define RRM_AGC5_DIG_ENG_T_INT_Msk                                         (0x000000f0UL)  /*!< RRM AGC5_DIG_ENG: T_INT (Bitfield-Mask: 0xf) */
10329 #define RRM_AGC5_DIG_ENG_T_INT                                             RRM_AGC5_DIG_ENG_T_INT_Msk
10330 #define RRM_AGC5_DIG_ENG_T_INT_0                                           (0x1 << RRM_AGC5_DIG_ENG_T_INT_Pos)   /*!<0x00000010 */
10331 #define RRM_AGC5_DIG_ENG_T_INT_1                                           (0x2 << RRM_AGC5_DIG_ENG_T_INT_Pos)   /*!<0x00000020 */
10332 #define RRM_AGC5_DIG_ENG_T_INT_2                                           (0x4 << RRM_AGC5_DIG_ENG_T_INT_Pos)   /*!<0x00000040 */
10333 #define RRM_AGC5_DIG_ENG_T_INT_3                                           (0x8 << RRM_AGC5_DIG_ENG_T_INT_Pos)   /*!<0x00000080 */
10334 
10335 /* ===============================================   AGC6_DIG_ENG   =============================================== */
10336 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos                            (0UL)   /*!< RRM AGC6_DIG_ENG: HOLD_TIME_SEL_10_4 (Bit 0) */
10337 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Msk                            (0x0000007fUL)  /*!< RRM AGC6_DIG_ENG: HOLD_TIME_SEL_10_4 (Bitfield-Mask: 0x7f) */
10338 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4                                RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Msk
10339 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_0                              (0x1 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000001 */
10340 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_1                              (0x2 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000002 */
10341 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_2                              (0x4 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000004 */
10342 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_3                              (0x8 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000008 */
10343 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_4                              (0x10 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000010 */
10344 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_5                              (0x20 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000020 */
10345 #define RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_6                              (0x40 << RRM_AGC6_DIG_ENG_HOLD_TIME_SEL_10_4_Pos)   /*!<0x00000040 */
10346 #define RRM_AGC6_DIG_ENG_SPARE_Pos                                         (7UL)   /*!< RRM AGC6_DIG_ENG: SPARE (Bit 7) */
10347 #define RRM_AGC6_DIG_ENG_SPARE_Msk                                         (0x00000080UL)  /*!< RRM AGC6_DIG_ENG: SPARE (Bitfield-Mask: 0x1) */
10348 #define RRM_AGC6_DIG_ENG_SPARE                                             RRM_AGC6_DIG_ENG_SPARE_Msk
10349 
10350 /* ===============================================   AGC7_DIG_ENG   =============================================== */
10351 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos                               (0UL)   /*!< RRM AGC7_DIG_ENG: TH_LOW_SEL_10_4 (Bit 0) */
10352 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Msk                               (0x0000007fUL)  /*!< RRM AGC7_DIG_ENG: TH_LOW_SEL_10_4 (Bitfield-Mask: 0x7f) */
10353 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4                                   RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Msk
10354 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_0                                 (0x1 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000001 */
10355 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_1                                 (0x2 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000002 */
10356 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_2                                 (0x4 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000004 */
10357 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_3                                 (0x8 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000008 */
10358 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_4                                 (0x10 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000010 */
10359 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_5                                 (0x20 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000020 */
10360 #define RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_6                                 (0x40 << RRM_AGC7_DIG_ENG_TH_LOW_SEL_10_4_Pos)   /*!<0x00000040 */
10361 #define RRM_AGC7_DIG_ENG_SPARE_Pos                                         (7UL)   /*!< RRM AGC7_DIG_ENG: SPARE (Bit 7) */
10362 #define RRM_AGC7_DIG_ENG_SPARE_Msk                                         (0x00000080UL)  /*!< RRM AGC7_DIG_ENG: SPARE (Bitfield-Mask: 0x1) */
10363 #define RRM_AGC7_DIG_ENG_SPARE                                             RRM_AGC7_DIG_ENG_SPARE_Msk
10364 
10365 /* ===============================================   AGC8_DIG_ENG   =============================================== */
10366 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Pos                             (0UL)   /*!< RRM AGC8_DIG_ENG: HOLD_TIME_SEL_3_0 (Bit 0) */
10367 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Msk                             (0x0000000fUL)  /*!< RRM AGC8_DIG_ENG: HOLD_TIME_SEL_3_0 (Bitfield-Mask: 0xf) */
10368 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0                                 RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Msk
10369 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_0                               (0x1 << RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Pos)   /*!<0x00000001 */
10370 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_1                               (0x2 << RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Pos)   /*!<0x00000002 */
10371 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_2                               (0x4 << RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Pos)   /*!<0x00000004 */
10372 #define RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_3                               (0x8 << RRM_AGC8_DIG_ENG_HOLD_TIME_SEL_3_0_Pos)   /*!<0x00000008 */
10373 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Pos                                (4UL)   /*!< RRM AGC8_DIG_ENG: TH_LOW_SEL_3_0 (Bit 4) */
10374 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Msk                                (0x000000f0UL)  /*!< RRM AGC8_DIG_ENG: TH_LOW_SEL_3_0 (Bitfield-Mask: 0xf) */
10375 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0                                    RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Msk
10376 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_0                                  (0x1 << RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Pos)   /*!<0x00000010 */
10377 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_1                                  (0x2 << RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Pos)   /*!<0x00000020 */
10378 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_2                                  (0x4 << RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Pos)   /*!<0x00000040 */
10379 #define RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_3                                  (0x8 << RRM_AGC8_DIG_ENG_TH_LOW_SEL_3_0_Pos)   /*!<0x00000080 */
10380 
10381 /* ===============================================   AGC9_DIG_ENG   =============================================== */
10382 #define RRM_AGC9_DIG_ENG_START_SEQ_Pos                                     (0UL)   /*!< RRM AGC9_DIG_ENG: START_SEQ (Bit 0) */
10383 #define RRM_AGC9_DIG_ENG_START_SEQ_Msk                                     (0x0000000fUL)  /*!< RRM AGC9_DIG_ENG: START_SEQ (Bitfield-Mask: 0xf) */
10384 #define RRM_AGC9_DIG_ENG_START_SEQ                                         RRM_AGC9_DIG_ENG_START_SEQ_Msk
10385 #define RRM_AGC9_DIG_ENG_START_SEQ_0                                       (0x1 << RRM_AGC9_DIG_ENG_START_SEQ_Pos)   /*!<0x00000001 */
10386 #define RRM_AGC9_DIG_ENG_START_SEQ_1                                       (0x2 << RRM_AGC9_DIG_ENG_START_SEQ_Pos)   /*!<0x00000002 */
10387 #define RRM_AGC9_DIG_ENG_START_SEQ_2                                       (0x4 << RRM_AGC9_DIG_ENG_START_SEQ_Pos)   /*!<0x00000004 */
10388 #define RRM_AGC9_DIG_ENG_START_SEQ_3                                       (0x8 << RRM_AGC9_DIG_ENG_START_SEQ_Pos)   /*!<0x00000008 */
10389 #define RRM_AGC9_DIG_ENG_MAX_SEQ_Pos                                       (4UL)   /*!< RRM AGC9_DIG_ENG: MAX_SEQ (Bit 4) */
10390 #define RRM_AGC9_DIG_ENG_MAX_SEQ_Msk                                       (0x000000f0UL)  /*!< RRM AGC9_DIG_ENG: MAX_SEQ (Bitfield-Mask: 0xf) */
10391 #define RRM_AGC9_DIG_ENG_MAX_SEQ                                           RRM_AGC9_DIG_ENG_MAX_SEQ_Msk
10392 #define RRM_AGC9_DIG_ENG_MAX_SEQ_0                                         (0x1 << RRM_AGC9_DIG_ENG_MAX_SEQ_Pos)   /*!<0x00000010 */
10393 #define RRM_AGC9_DIG_ENG_MAX_SEQ_1                                         (0x2 << RRM_AGC9_DIG_ENG_MAX_SEQ_Pos)   /*!<0x00000020 */
10394 #define RRM_AGC9_DIG_ENG_MAX_SEQ_2                                         (0x4 << RRM_AGC9_DIG_ENG_MAX_SEQ_Pos)   /*!<0x00000040 */
10395 #define RRM_AGC9_DIG_ENG_MAX_SEQ_3                                         (0x8 << RRM_AGC9_DIG_ENG_MAX_SEQ_Pos)   /*!<0x00000080 */
10396 
10397 /* ===============================================   AGC10_DIG_ENG   =============================================== */
10398 #define RRM_AGC10_DIG_ENG_ATT_0_Pos                                        (0UL)   /*!< RRM AGC10_DIG_ENG: ATT_0 (Bit 0) */
10399 #define RRM_AGC10_DIG_ENG_ATT_0_Msk                                        (0x0000003fUL)  /*!< RRM AGC10_DIG_ENG: ATT_0 (Bitfield-Mask: 0x3f) */
10400 #define RRM_AGC10_DIG_ENG_ATT_0                                            RRM_AGC10_DIG_ENG_ATT_0_Msk
10401 #define RRM_AGC10_DIG_ENG_ATT_0_0                                          (0x1 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000001 */
10402 #define RRM_AGC10_DIG_ENG_ATT_0_1                                          (0x2 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000002 */
10403 #define RRM_AGC10_DIG_ENG_ATT_0_2                                          (0x4 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000004 */
10404 #define RRM_AGC10_DIG_ENG_ATT_0_3                                          (0x8 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000008 */
10405 #define RRM_AGC10_DIG_ENG_ATT_0_4                                          (0x10 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000010 */
10406 #define RRM_AGC10_DIG_ENG_ATT_0_5                                          (0x20 << RRM_AGC10_DIG_ENG_ATT_0_Pos)   /*!<0x00000020 */
10407 #define RRM_AGC10_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC10_DIG_ENG: SPARE (Bit 6) */
10408 #define RRM_AGC10_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC10_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10409 #define RRM_AGC10_DIG_ENG_SPARE                                            RRM_AGC10_DIG_ENG_SPARE_Msk
10410 
10411 /* ===============================================   AGC11_DIG_ENG   =============================================== */
10412 #define RRM_AGC11_DIG_ENG_ATT_1_Pos                                        (0UL)   /*!< RRM AGC11_DIG_ENG: ATT_1 (Bit 0) */
10413 #define RRM_AGC11_DIG_ENG_ATT_1_Msk                                        (0x0000003fUL)  /*!< RRM AGC11_DIG_ENG: ATT_1 (Bitfield-Mask: 0x3f) */
10414 #define RRM_AGC11_DIG_ENG_ATT_1                                            RRM_AGC11_DIG_ENG_ATT_1_Msk
10415 #define RRM_AGC11_DIG_ENG_ATT_1_0                                          (0x1 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000001 */
10416 #define RRM_AGC11_DIG_ENG_ATT_1_1                                          (0x2 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000002 */
10417 #define RRM_AGC11_DIG_ENG_ATT_1_2                                          (0x4 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000004 */
10418 #define RRM_AGC11_DIG_ENG_ATT_1_3                                          (0x8 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000008 */
10419 #define RRM_AGC11_DIG_ENG_ATT_1_4                                          (0x10 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000010 */
10420 #define RRM_AGC11_DIG_ENG_ATT_1_5                                          (0x20 << RRM_AGC11_DIG_ENG_ATT_1_Pos)   /*!<0x00000020 */
10421 #define RRM_AGC11_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC11_DIG_ENG: SPARE (Bit 6) */
10422 #define RRM_AGC11_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC11_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10423 #define RRM_AGC11_DIG_ENG_SPARE                                            RRM_AGC11_DIG_ENG_SPARE_Msk
10424 
10425 /* ===============================================   AGC12_DIG_ENG   =============================================== */
10426 #define RRM_AGC12_DIG_ENG_ATT_2_Pos                                        (0UL)   /*!< RRM AGC12_DIG_ENG: ATT_2 (Bit 0) */
10427 #define RRM_AGC12_DIG_ENG_ATT_2_Msk                                        (0x0000003fUL)  /*!< RRM AGC12_DIG_ENG: ATT_2 (Bitfield-Mask: 0x3f) */
10428 #define RRM_AGC12_DIG_ENG_ATT_2                                            RRM_AGC12_DIG_ENG_ATT_2_Msk
10429 #define RRM_AGC12_DIG_ENG_ATT_2_0                                          (0x1 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000001 */
10430 #define RRM_AGC12_DIG_ENG_ATT_2_1                                          (0x2 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000002 */
10431 #define RRM_AGC12_DIG_ENG_ATT_2_2                                          (0x4 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000004 */
10432 #define RRM_AGC12_DIG_ENG_ATT_2_3                                          (0x8 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000008 */
10433 #define RRM_AGC12_DIG_ENG_ATT_2_4                                          (0x10 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000010 */
10434 #define RRM_AGC12_DIG_ENG_ATT_2_5                                          (0x20 << RRM_AGC12_DIG_ENG_ATT_2_Pos)   /*!<0x00000020 */
10435 #define RRM_AGC12_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC12_DIG_ENG: SPARE (Bit 6) */
10436 #define RRM_AGC12_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC12_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10437 #define RRM_AGC12_DIG_ENG_SPARE                                            RRM_AGC12_DIG_ENG_SPARE_Msk
10438 
10439 /* ===============================================   AGC13_DIG_ENG   =============================================== */
10440 #define RRM_AGC13_DIG_ENG_ATT_3_Pos                                        (0UL)   /*!< RRM AGC13_DIG_ENG: ATT_3 (Bit 0) */
10441 #define RRM_AGC13_DIG_ENG_ATT_3_Msk                                        (0x0000003fUL)  /*!< RRM AGC13_DIG_ENG: ATT_3 (Bitfield-Mask: 0x3f) */
10442 #define RRM_AGC13_DIG_ENG_ATT_3                                            RRM_AGC13_DIG_ENG_ATT_3_Msk
10443 #define RRM_AGC13_DIG_ENG_ATT_3_0                                          (0x1 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000001 */
10444 #define RRM_AGC13_DIG_ENG_ATT_3_1                                          (0x2 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000002 */
10445 #define RRM_AGC13_DIG_ENG_ATT_3_2                                          (0x4 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000004 */
10446 #define RRM_AGC13_DIG_ENG_ATT_3_3                                          (0x8 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000008 */
10447 #define RRM_AGC13_DIG_ENG_ATT_3_4                                          (0x10 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000010 */
10448 #define RRM_AGC13_DIG_ENG_ATT_3_5                                          (0x20 << RRM_AGC13_DIG_ENG_ATT_3_Pos)   /*!<0x00000020 */
10449 #define RRM_AGC13_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC13_DIG_ENG: SPARE (Bit 6) */
10450 #define RRM_AGC13_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC13_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10451 #define RRM_AGC13_DIG_ENG_SPARE                                            RRM_AGC13_DIG_ENG_SPARE_Msk
10452 
10453 /* ===============================================   AGC14_DIG_ENG   =============================================== */
10454 #define RRM_AGC14_DIG_ENG_ATT_4_Pos                                        (0UL)   /*!< RRM AGC14_DIG_ENG: ATT_4 (Bit 0) */
10455 #define RRM_AGC14_DIG_ENG_ATT_4_Msk                                        (0x0000003fUL)  /*!< RRM AGC14_DIG_ENG: ATT_4 (Bitfield-Mask: 0x3f) */
10456 #define RRM_AGC14_DIG_ENG_ATT_4                                            RRM_AGC14_DIG_ENG_ATT_4_Msk
10457 #define RRM_AGC14_DIG_ENG_ATT_4_0                                          (0x1 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000001 */
10458 #define RRM_AGC14_DIG_ENG_ATT_4_1                                          (0x2 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000002 */
10459 #define RRM_AGC14_DIG_ENG_ATT_4_2                                          (0x4 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000004 */
10460 #define RRM_AGC14_DIG_ENG_ATT_4_3                                          (0x8 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000008 */
10461 #define RRM_AGC14_DIG_ENG_ATT_4_4                                          (0x10 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000010 */
10462 #define RRM_AGC14_DIG_ENG_ATT_4_5                                          (0x20 << RRM_AGC14_DIG_ENG_ATT_4_Pos)   /*!<0x00000020 */
10463 #define RRM_AGC14_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC14_DIG_ENG: SPARE (Bit 6) */
10464 #define RRM_AGC14_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC14_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10465 #define RRM_AGC14_DIG_ENG_SPARE                                            RRM_AGC14_DIG_ENG_SPARE_Msk
10466 
10467 /* ===============================================   AGC15_DIG_ENG   =============================================== */
10468 #define RRM_AGC15_DIG_ENG_ATT_5_Pos                                        (0UL)   /*!< RRM AGC15_DIG_ENG: ATT_5 (Bit 0) */
10469 #define RRM_AGC15_DIG_ENG_ATT_5_Msk                                        (0x0000003fUL)  /*!< RRM AGC15_DIG_ENG: ATT_5 (Bitfield-Mask: 0x3f) */
10470 #define RRM_AGC15_DIG_ENG_ATT_5                                            RRM_AGC15_DIG_ENG_ATT_5_Msk
10471 #define RRM_AGC15_DIG_ENG_ATT_5_0                                          (0x1 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000001 */
10472 #define RRM_AGC15_DIG_ENG_ATT_5_1                                          (0x2 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000002 */
10473 #define RRM_AGC15_DIG_ENG_ATT_5_2                                          (0x4 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000004 */
10474 #define RRM_AGC15_DIG_ENG_ATT_5_3                                          (0x8 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000008 */
10475 #define RRM_AGC15_DIG_ENG_ATT_5_4                                          (0x10 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000010 */
10476 #define RRM_AGC15_DIG_ENG_ATT_5_5                                          (0x20 << RRM_AGC15_DIG_ENG_ATT_5_Pos)   /*!<0x00000020 */
10477 #define RRM_AGC15_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC15_DIG_ENG: SPARE (Bit 6) */
10478 #define RRM_AGC15_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC15_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10479 #define RRM_AGC15_DIG_ENG_SPARE                                            RRM_AGC15_DIG_ENG_SPARE_Msk
10480 
10481 /* ===============================================   AGC16_DIG_ENG   =============================================== */
10482 #define RRM_AGC16_DIG_ENG_ATT_6_Pos                                        (0UL)   /*!< RRM AGC16_DIG_ENG: ATT_6 (Bit 0) */
10483 #define RRM_AGC16_DIG_ENG_ATT_6_Msk                                        (0x0000003fUL)  /*!< RRM AGC16_DIG_ENG: ATT_6 (Bitfield-Mask: 0x3f) */
10484 #define RRM_AGC16_DIG_ENG_ATT_6                                            RRM_AGC16_DIG_ENG_ATT_6_Msk
10485 #define RRM_AGC16_DIG_ENG_ATT_6_0                                          (0x1 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000001 */
10486 #define RRM_AGC16_DIG_ENG_ATT_6_1                                          (0x2 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000002 */
10487 #define RRM_AGC16_DIG_ENG_ATT_6_2                                          (0x4 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000004 */
10488 #define RRM_AGC16_DIG_ENG_ATT_6_3                                          (0x8 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000008 */
10489 #define RRM_AGC16_DIG_ENG_ATT_6_4                                          (0x10 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000010 */
10490 #define RRM_AGC16_DIG_ENG_ATT_6_5                                          (0x20 << RRM_AGC16_DIG_ENG_ATT_6_Pos)   /*!<0x00000020 */
10491 #define RRM_AGC16_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC16_DIG_ENG: SPARE (Bit 6) */
10492 #define RRM_AGC16_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC16_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10493 #define RRM_AGC16_DIG_ENG_SPARE                                            RRM_AGC16_DIG_ENG_SPARE_Msk
10494 
10495 /* ===============================================   AGC17_DIG_ENG   =============================================== */
10496 #define RRM_AGC17_DIG_ENG_ATT_7_Pos                                        (0UL)   /*!< RRM AGC17_DIG_ENG: ATT_7 (Bit 0) */
10497 #define RRM_AGC17_DIG_ENG_ATT_7_Msk                                        (0x0000003fUL)  /*!< RRM AGC17_DIG_ENG: ATT_7 (Bitfield-Mask: 0x3f) */
10498 #define RRM_AGC17_DIG_ENG_ATT_7                                            RRM_AGC17_DIG_ENG_ATT_7_Msk
10499 #define RRM_AGC17_DIG_ENG_ATT_7_0                                          (0x1 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000001 */
10500 #define RRM_AGC17_DIG_ENG_ATT_7_1                                          (0x2 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000002 */
10501 #define RRM_AGC17_DIG_ENG_ATT_7_2                                          (0x4 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000004 */
10502 #define RRM_AGC17_DIG_ENG_ATT_7_3                                          (0x8 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000008 */
10503 #define RRM_AGC17_DIG_ENG_ATT_7_4                                          (0x10 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000010 */
10504 #define RRM_AGC17_DIG_ENG_ATT_7_5                                          (0x20 << RRM_AGC17_DIG_ENG_ATT_7_Pos)   /*!<0x00000020 */
10505 #define RRM_AGC17_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC17_DIG_ENG: SPARE (Bit 6) */
10506 #define RRM_AGC17_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC17_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10507 #define RRM_AGC17_DIG_ENG_SPARE                                            RRM_AGC17_DIG_ENG_SPARE_Msk
10508 
10509 /* ===============================================   AGC18_DIG_ENG   =============================================== */
10510 #define RRM_AGC18_DIG_ENG_ATT_8_Pos                                        (0UL)   /*!< RRM AGC18_DIG_ENG: ATT_8 (Bit 0) */
10511 #define RRM_AGC18_DIG_ENG_ATT_8_Msk                                        (0x0000003fUL)  /*!< RRM AGC18_DIG_ENG: ATT_8 (Bitfield-Mask: 0x3f) */
10512 #define RRM_AGC18_DIG_ENG_ATT_8                                            RRM_AGC18_DIG_ENG_ATT_8_Msk
10513 #define RRM_AGC18_DIG_ENG_ATT_8_0                                          (0x1 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000001 */
10514 #define RRM_AGC18_DIG_ENG_ATT_8_1                                          (0x2 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000002 */
10515 #define RRM_AGC18_DIG_ENG_ATT_8_2                                          (0x4 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000004 */
10516 #define RRM_AGC18_DIG_ENG_ATT_8_3                                          (0x8 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000008 */
10517 #define RRM_AGC18_DIG_ENG_ATT_8_4                                          (0x10 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000010 */
10518 #define RRM_AGC18_DIG_ENG_ATT_8_5                                          (0x20 << RRM_AGC18_DIG_ENG_ATT_8_Pos)   /*!<0x00000020 */
10519 #define RRM_AGC18_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC18_DIG_ENG: SPARE (Bit 6) */
10520 #define RRM_AGC18_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC18_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10521 #define RRM_AGC18_DIG_ENG_SPARE                                            RRM_AGC18_DIG_ENG_SPARE_Msk
10522 
10523 /* ===============================================   AGC19_DIG_ENG   =============================================== */
10524 #define RRM_AGC19_DIG_ENG_ATT_9_Pos                                        (0UL)   /*!< RRM AGC19_DIG_ENG: ATT_9 (Bit 0) */
10525 #define RRM_AGC19_DIG_ENG_ATT_9_Msk                                        (0x0000003fUL)  /*!< RRM AGC19_DIG_ENG: ATT_9 (Bitfield-Mask: 0x3f) */
10526 #define RRM_AGC19_DIG_ENG_ATT_9                                            RRM_AGC19_DIG_ENG_ATT_9_Msk
10527 #define RRM_AGC19_DIG_ENG_ATT_9_0                                          (0x1 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000001 */
10528 #define RRM_AGC19_DIG_ENG_ATT_9_1                                          (0x2 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000002 */
10529 #define RRM_AGC19_DIG_ENG_ATT_9_2                                          (0x4 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000004 */
10530 #define RRM_AGC19_DIG_ENG_ATT_9_3                                          (0x8 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000008 */
10531 #define RRM_AGC19_DIG_ENG_ATT_9_4                                          (0x10 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000010 */
10532 #define RRM_AGC19_DIG_ENG_ATT_9_5                                          (0x20 << RRM_AGC19_DIG_ENG_ATT_9_Pos)   /*!<0x00000020 */
10533 #define RRM_AGC19_DIG_ENG_SPARE_Pos                                        (6UL)   /*!< RRM AGC19_DIG_ENG: SPARE (Bit 6) */
10534 #define RRM_AGC19_DIG_ENG_SPARE_Msk                                        (0x000000c0UL)  /*!< RRM AGC19_DIG_ENG: SPARE (Bitfield-Mask: 0x3) */
10535 #define RRM_AGC19_DIG_ENG_SPARE                                            RRM_AGC19_DIG_ENG_SPARE_Msk
10536 
10537 /* ===============================================   AGC20_DIG_ENG   =============================================== */
10538 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos                                  (0UL)   /*!< RRM AGC20_DIG_ENG: I_GAIN_COMP (Bit 0) */
10539 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_Msk                                  (0x000000ffUL)  /*!< RRM AGC20_DIG_ENG: I_GAIN_COMP (Bitfield-Mask: 0xff) */
10540 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP                                      RRM_AGC20_DIG_ENG_I_GAIN_COMP_Msk
10541 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_0                                    (0x01 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000001 */
10542 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_1                                    (0x02 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000002 */
10543 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_2                                    (0x04 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000004 */
10544 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_3                                    (0x08 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000008 */
10545 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_4                                    (0x10 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000010 */
10546 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_5                                    (0x20 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000020 */
10547 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_6                                    (0x40 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000040 */
10548 #define RRM_AGC20_DIG_ENG_I_GAIN_COMP_7                                    (0x80 << RRM_AGC20_DIG_ENG_I_GAIN_COMP_Pos)   /*!<0x00000080 */
10549 
10550 /* =====================================================    RXADC_HW_TRIM_OUT    ===================================================== */
10551 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Pos                     (0UL)    /*!<RRM RXADC_HW_TRIM_OUT: HW_RXADC_DELAYTRIM_I (Bit 0) */
10552 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Msk                     (0x7UL)    /*!< RRM RXADC_HW_TRIM_OUT: HW_RXADC_DELAYTRIM_I (Bitfield-Mask: 0x07) */
10553 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I                         RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Msk
10554 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_0                       (0x1U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Pos)
10555 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_1                       (0x2U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Pos)
10556 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_2                       (0x4U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Pos)
10557 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Pos                     (3UL)    /*!<RRM RXADC_HW_TRIM_OUT: HW_RXADC_DELAYTRIM_Q (Bit 3) */
10558 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Msk                     (0x38UL)   /*!< RRM RXADC_HW_TRIM_OUT: HW_RXADC_DELAYTRIM_Q (Bitfield-Mask: 0x07) */
10559 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q                         RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Msk
10560 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_0                       (0x1U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Pos)
10561 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_1                       (0x2U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Pos)
10562 #define RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_2                       (0x4U << RRM_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Pos)
10563 
10564 /* =====================================================    CBIAS0_HW_TRIM_OUT    ===================================================== */
10565 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos                     (0UL)    /*!<RRM CBIAS0_HW_TRIM_OUT: HW_CBIAS_IBIAS_TRIM (Bit 0) */
10566 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Msk                     (0xfUL)    /*!< RRM CBIAS0_HW_TRIM_OUT: HW_CBIAS_IBIAS_TRIM (Bitfield-Mask: 0x0f) */
10567 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM                         RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Msk
10568 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_0                       (0x1U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos)
10569 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_1                       (0x2U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos)
10570 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_2                       (0x4U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos)
10571 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_3                       (0x8U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos)
10572 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos                     (4UL)    /*!<RRM CBIAS0_HW_TRIM_OUT: HW_CBIAS_IPTAT_TRIM (Bit 4) */
10573 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Msk                     (0xf0UL)   /*!< RRM CBIAS0_HW_TRIM_OUT: HW_CBIAS_IPTAT_TRIM (Bitfield-Mask: 0x0f) */
10574 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM                         RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Msk
10575 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_0                       (0x1U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos)
10576 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_1                       (0x2U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos)
10577 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_2                       (0x4U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos)
10578 #define RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_3                       (0x8U << RRM_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos)
10579 
10580 /* =====================================================    CBIAS1_HW_TRIM_OUT    ===================================================== */
10581 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Pos                       (0UL)    /*!<RRM CBIAS1_HW_TRIM_OUT: HW_CBIAS_VBG_TRIM (Bit 0) */
10582 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Msk                       (0xfUL)    /*!< RRM CBIAS1_HW_TRIM_OUT: HW_CBIAS_VBG_TRIM (Bitfield-Mask: 0x0f) */
10583 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM                           RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Msk
10584 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_0                         (0x1U << RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Pos)
10585 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_1                         (0x2U << RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Pos)
10586 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_2                         (0x4U << RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Pos)
10587 #define RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_3                         (0x8U << RRM_CBIAS1_HW_TRIM_OUT_HW_CBIAS_VBG_TRIM_Pos)
10588 
10589 /* =====================================================    AGC_HW_TRIM_OUT    ===================================================== */
10590 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Pos                       (1UL)    /*!<RRM AGC_HW_TRIM_OUT: HW_AGC_ANTENNAE_TRIM (Bit 1) */
10591 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Msk                       (0xeUL)    /*!< RRM AGC_HW_TRIM_OUT: HW_AGC_ANTENNAE_TRIM (Bitfield-Mask: 0x07) */
10592 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM                           RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Msk
10593 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_0                         (0x1U << RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Pos)
10594 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_1                         (0x2U << RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Pos)
10595 #define RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_2                         (0x4U << RRM_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Pos)
10596 
10597 /** @} */ /* End of group PosMask_peripherals */
10598 
10599 /** @addtogroup Exported_macros
10600   * @{
10601   */
10602 
10603 /*********************** UART Instances : Asynchronous mode *******************/
10604 #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10605 
10606 /*********************** UART Instances : FIFO mode ***************************/
10607 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10608                                          ((INSTANCE) == LPUART1))
10609 
10610 /*********************** UART Instances : SPI Slave mode **********************/
10611 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10612 
10613 /*********************** USART Instances : Synchronous mode *******************/
10614 #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10615 
10616 /*********************** USART Instances : Auto Baud Rate detection ***********/
10617 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10618 
10619 /*********************** UART Instances : Half-Duplex mode ********************/
10620 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10621                                                  ((INSTANCE) == LPUART1))
10622 
10623 /*********************** UART Instances : LIN mode ****************************/
10624 #define IS_UART_LIN_INSTANCE(INSTANCE)    ((INSTANCE) == USART1)
10625 
10626 /*********************** UART Instances : Hardware Flow control ***************/
10627 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10628                                            ((INSTANCE) == LPUART1))
10629 
10630 /*********************** UART Instances : Smard card mode *********************/
10631 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10632 
10633 
10634 /*********************** UART Instances : Driver Enable ***********************/
10635 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \
10636                                                   ((INSTANCE) == LPUART1))
10637 
10638 /*********************** UART Instances : IRDA mode ***************************/
10639 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
10640 
10641 /*********************** UART Instances : Wake-up from Stop mode **************/
10642 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (0U)
10643 
10644 /******************** LPUART Instance *****************************************/
10645 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
10646 
10647 
10648 /******************************* ADC Instances ********************************/
10649 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10650 
10651 /******************************* AES Instances ********************************/
10652 #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2))
10653 
10654 /******************************* CRC Instances ********************************/
10655 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10656 
10657 /******************************** DMA Instances *******************************/
10658 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10659                                        ((INSTANCE) == DMA1_Channel2) || \
10660                                        ((INSTANCE) == DMA1_Channel3) || \
10661                                        ((INSTANCE) == DMA1_Channel4) || \
10662                                        ((INSTANCE) == DMA1_Channel5) || \
10663                                        ((INSTANCE) == DMA1_Channel6) || \
10664                                        ((INSTANCE) == DMA1_Channel7) || \
10665                                        ((INSTANCE) == DMA1_Channel8))
10666 
10667 /******************************** DMAMUX Instances ****************************/
10668 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
10669 
10670 /******************************* GPIO Instances *******************************/
10671 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10672                                         ((INSTANCE) == GPIOB))
10673 
10674 /******************************* GPIO AF Instances ****************************/
10675 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
10676 
10677 /**************************** GPIO Lock Instances *****************************/
10678 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10679 
10680 /******************************** I2C Instances *******************************/
10681 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10682                                        ((INSTANCE) == I2C2))
10683 
10684 /******************************** PKA Instances *******************************/
10685 #define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA)
10686 
10687 /******************************* RNG Instances ********************************/
10688 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
10689 
10690 /****************************** RTC Instances *********************************/
10691 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10692 
10693 /******************************* SMBUS Instances ******************************/
10694 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10695                                          ((INSTANCE) == I2C2))
10696 
10697 /******************************** SPI Instances *******************************/
10698 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10699                                        ((INSTANCE) == SPI2) || \
10700                                        ((INSTANCE) == SPI3))
10701 
10702 /******************************** I2S Instances *******************************/
10703 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
10704                                         ((INSTANCE) == SPI3))
10705 
10706 /****************** LPTIM Instances : All supported instances *****************/
10707 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1))
10708 
10709 /****************** TIM Instances : All supported instances *******************/
10710 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1))
10711 
10712 /****************************** IWDG Instances ********************************/
10713 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
10714 
10715 /****************** TIM Instances : supporting the break function *************/
10716 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10717 
10718 /************** TIM Instances : supporting Break source selection *************/
10719 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
10720 
10721 /****************** TIM Instances : supporting 2 break inputs *****************/
10722 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10723 
10724 /************* TIM Instances : at least 1 capture/compare channel *************/
10725 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10726 
10727 /************ TIM Instances : at least 2 capture/compare channels *************/
10728 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10729 
10730 /************ TIM Instances : at least 3 capture/compare channels *************/
10731 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10732 
10733 /************ TIM Instances : at least 4 capture/compare channels *************/
10734 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10735 
10736 /************ TIM Instances : at least 5 compare channels *********************/
10737 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10738 
10739 /************ TIM Instances : at least 6 compare channels *********************/
10740 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10741 
10742 /******************* TIM Instances : Timer input selection ********************/
10743 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
10744 
10745 /******************* TIM Instances : output(s) available **********************/
10746 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10747   ((((INSTANCE) == TIM1) &&                  \
10748     (((CHANNEL) == TIM_CHANNEL_1) ||          \
10749      ((CHANNEL) == TIM_CHANNEL_2) ||          \
10750      ((CHANNEL) == TIM_CHANNEL_3) ||          \
10751      ((CHANNEL) == TIM_CHANNEL_4) ||          \
10752      ((CHANNEL) == TIM_CHANNEL_5) ||          \
10753      ((CHANNEL) == TIM_CHANNEL_6))))
10754 
10755 /****************** TIM Instances : supporting complementary output(s) ********/
10756 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10757   ((((INSTANCE) == TIM1) &&                    \
10758     (((CHANNEL) == TIM_CHANNEL_1) ||                \
10759      ((CHANNEL) == TIM_CHANNEL_2) ||                \
10760      ((CHANNEL) == TIM_CHANNEL_3) ||                \
10761      ((CHANNEL) == TIM_CHANNEL_4) ||                \
10762      ((CHANNEL) == TIM_CHANNEL_5) ||                \
10763      ((CHANNEL) == TIM_CHANNEL_6))))
10764 
10765 /****************** TIM Instances : supporting clock division *****************/
10766 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1))
10767 
10768 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
10769 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
10770 
10771 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10772 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
10773 
10774 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10775 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1))
10776 
10777 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10778 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1))
10779 
10780 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10781 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10782 
10783 /****************** TIM Instances : supporting commutation event generation ***/
10784 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10785 
10786 /****************** TIM Instances : supporting counting mode selection ********/
10787 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))
10788 
10789 /****************** TIM Instances : supporting encoder interface **************/
10790 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))
10791 
10792 /****************** TIM Instances : supporting Hall sensor interface **********/
10793 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
10794 
10795 /**************** TIM Instances : external trigger input available ************/
10796 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1))
10797 
10798 /************* TIM Instances : supporting ETR source selection ***************/
10799 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10800 
10801 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10802 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10803 
10804 /****************** TIM Instances : supporting OCxREF clear *******************/
10805 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1))
10806 
10807 /****************** TIM Instances : remapping capability **********************/
10808 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10809 
10810 /****************** TIM Instances : supporting repetition counter *************/
10811 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))
10812 
10813 /****************** TIM Instances : supporting synchronization ****************/
10814 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
10815 
10816 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
10817 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10818 
10819 /******************* TIM Instances : Timer input XOR function *****************/
10820 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1))
10821 
10822 /************ TIM Instances : Advanced timers  ********************************/
10823 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
10824 
10825 /**
10826   * @}
10827   */
10828 
10829 #ifdef __cplusplus
10830 }
10831 #endif /* __cplusplus */
10832 
10833 #endif /* __STM32WB06_H */
10834 
10835 /**
10836   * @}
10837   */
10838 
10839 /**
10840   * @}
10841   */
10842