/** ****************************************************************************** * @file stm32wb06.h * @author MCD Application Team * @brief CMSIS Cortex Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32wb06 devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32wb06 * @{ */ #ifndef __STM32WB06_H #define __STM32WB06_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief stm32wb06 Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* ========================================= stm32wb06 Specific Interrupt Numbers ========================================= */ FLASH_IRQn = 0, /*!< 0 NVM interrupt */ RCC_IRQn = 1, /*!< 1 RCC interrupt */ PVD_IRQn = 2, /*!< 2 PVD interrupt */ I2C1_IRQn = 3, /*!< 3 I2C1 interrurpt */ I2C2_IRQn = 4, /*!< 4 I2C2 interrupt */ SPI1_IRQn = 5, /*!< 5 SPI1 interrupt */ SPI2_IRQn = 6, /*!< 6 SPI2 interrupt */ SPI3_IRQn = 7, /*!< 7 SPI3 interrupt */ USART1_IRQn = 8, /*!< 8 USART interrupt */ LPUART1_IRQn = 9, /*!< 9 Low Power UART interrupt */ TIM1_IRQn = 10, /*!< 10 Timer 1 interrupt */ RTC_IRQn = 11, /*!< 11 RTC interrupt */ ADC_IRQn = 12, /*!< 12 ADC interrupt */ PKA_IRQn = 13, /*!< 13 PKA interrupt */ UPCONV_IRQn = 14, /*!< 14 AHB_UP_CONVERTER interrupt */ GPIOA_IRQn = 15, /*!< 15 GPIOA interrupt */ GPIOB_IRQn = 16, /*!< 16 GPIOB interrupt */ DMA_IRQn = 17, /*!< 17 DMA interrupt */ RADIO_TXRX_IRQn = 18, /*!< 18 RADIO Tx/Rx interrupt */ RADIO_TIMER_ERROR_IRQn = 20, /*!< 20 RADIO TIMER Error interrupt */ RADIO_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 RADIO TIMER CPU Wakeup interrupt */ RADIO_TIMER_TXRX_WKUP_IRQn = 24, /*!< 24 RADIO TIMER Tx/Rx Wakeup interrupt */ RADIO_TXRX_SEQ_IRQn = 25 /*!< 25 RADIO Tx/Rx sequence interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ /** @addtogroup Configuration_of_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ #define __CM0PLUS_REV 1 /*!< CM0PLUS Core Revision r0p1 */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __VTOR_PRESENT 1 /*!< Vector Table Offset Register supported */ #define __MPU_PRESENT 1 /*!< M0+ provides an MPU */ #define __FPU_PRESENT 0 /*!< FPU not present */ /** * @} */ /*!< Device Electronic Signature */ #define PACKAGE_BASE ((uint32_t)0x10001EECU) /*!< Package data register base address */ #define UID64_BASE ((uint32_t)0x10001EF0U) /*!< 64-bit Unique device Identification */ #define FLASHSIZE_BASE ((uint32_t)0x40001014U) /*!< Flash size data register base address */ #define RAMSIZE_BASE ((uint32_t)0x48500090U) /*!< RAM size data register base address */ #define DEV_ID_BASE ((uint32_t)0x40000000U) /*!< Device version and cut version register base address */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ #include /* ======================================== Start of section using anonymous unions ======================================== */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" #pragma clang diagnostic ignored "-Wnested-anon-types" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_peripherals * @{ */ /* =========================================================================================================================== */ /* ================ DMA ================ */ /* =========================================================================================================================== */ /** * @brief Direct memory access controller (DMA) */ typedef struct /*!< DMA Structure */ { __IO uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ __IO uint32_t IFCR; /*!< (@ 0x00000004) Interrupt flag clear register */ } DMA_TypeDef; typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ __IO uint32_t RESERVED; } DMA_Channel_TypeDef; /* =========================================================================================================================== */ /* ================ DMAMUX ================ */ /* =========================================================================================================================== */ /** * @brief Direct memory access Multiplexer (DMAMUX) */ /** * @brief DMA Multiplexer */ typedef struct /*!< DMAMUX Structure */ { __IO uint32_t CxCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ } DMAMUX_Channel_TypeDef; /* =========================================================================================================================== */ /* ================ CRC ================ */ /* =========================================================================================================================== */ /** * @brief Cyclic redundancy check calculation unit (CRC) */ typedef struct /*!< CRC Structure */ { __IO uint32_t DR; /*!< (@ 0x00000000) Data register */ __IO uint32_t IDR; /*!< (@ 0x00000004) Independent data register */ __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ __IO uint32_t RESERVED; __IO uint32_t INIT; /*!< (@ 0x00000010) Initial CRC value */ __IO uint32_t POL; /*!< (@ 0x00000014) Polynomial */ } CRC_TypeDef; /*!< Size = 24 (0x18) */ /* =========================================================================================================================== */ /* ================ IWDG ================ */ /* =========================================================================================================================== */ /** * @brief Independent watchdog (IWDG) */ typedef struct /*!< IWDG Structure */ { __IO uint32_t KR; /*!< (@ 0x00000000) Key register */ __IO uint32_t PR; /*!< (@ 0x00000004) Prescaler register */ __IO uint32_t RLR; /*!< (@ 0x00000008) Reload register */ __IO uint32_t SR; /*!< (@ 0x0000000C) Status register */ __IO uint32_t WINR; /*!< (@ 0x00000010) Window register */ } IWDG_TypeDef; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ /* ================ I2C ================ */ /* =========================================================================================================================== */ /** * @brief Inter-integrated circuit (I2C) */ typedef struct /*!< I2C Structure */ { __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ __IO uint32_t OAR1; /*!< (@ 0x00000008) Own address register 1 */ __IO uint32_t OAR2; /*!< (@ 0x0000000C) Own address register 2 */ __IO uint32_t TIMINGR; /*!< (@ 0x00000010) Timing register */ __IO uint32_t TIMEOUTR; /*!< (@ 0x00000014) Status register 1 */ __IO uint32_t ISR; /*!< (@ 0x00000018) Interrupt and Status register */ __IO uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clear register */ __IO uint32_t PECR; /*!< (@ 0x00000020) PEC register */ __IO uint32_t RXDR; /*!< (@ 0x00000024) Receive data register */ __IO uint32_t TXDR; /*!< (@ 0x00000028) Transmit data register */ } I2C_TypeDef; /*!< Size = 44 (0x2c) */ /* =========================================================================================================================== */ /* ================ FLASH ================ */ /* =========================================================================================================================== */ /** * @brief FLASH (FLASH) */ typedef struct /*!< FLASH Structure */ { __IO uint32_t COMMAND; /*!< (@ 0x00000000) Command register */ __IO uint32_t CONFIG; /*!< (@ 0x00000004) Configuration register */ __IO uint32_t IRQSTAT; /*!< (@ 0x00000008) The interrupt status register shows the masked version of the interrupt raw register. */ __IO uint32_t IRQMASK; /*!< (@ 0x0000000C) The mask bit in IRQMASK will mask the condition in the status register IRQSTAT and prevent the generation of the interrupt. */ __IO uint32_t IRQRAW; /*!< (@ 0x00000010) The raw status register shows the unmasked condition of interrupt events. */ __IO uint32_t SIZE; /*!< (@ 0x00000014) SIZE register */ __IO uint32_t ADDRESS; /*!< (@ 0x00000018) Address register */ __IO uint32_t RESERVED[2]; __IO uint32_t LFSRVAL; /*!< (@ 0x00000024) LFSRVAL register */ __IO uint32_t RESERVED2[3]; __IO uint32_t PAGEPROT0; /*!< (@ 0x00000034) Main Flash page protection register 0 */ __IO uint32_t PAGEPROT1; /*!< (@ 0x00000038) Main Flash page protection register 1 */ __IO uint32_t RESERVED1; __IO uint32_t DATA0; /*!< (@ 0x00000040) Data register 0 */ __IO uint32_t DATA1; /*!< (@ 0x00000044) Data register 1 */ __IO uint32_t DATA2; /*!< (@ 0x00000048) Data register 2 */ __IO uint32_t DATA3; /*!< (@ 0x0000004C) Data register 3 */ } FLASH_TypeDef; /*!< Size = 80 (0x50) */ /* =========================================================================================================================== */ /* ================ SPI ================ */ /* =========================================================================================================================== */ /** * @brief Serial peripheral interface/Inter-IC sound (SPI) */ typedef struct /*!< SPI Structure */ { __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ __IO uint32_t DR; /*!< (@ 0x0000000C) Data register */ __IO uint32_t CRCPR; /*!< (@ 0x00000010) CRC polynomial register */ __IO uint32_t RXCRCR; /*!< (@ 0x00000014) RX CRC register */ __IO uint32_t TXCRCR; /*!< (@ 0x00000018) TX CRC register */ __IO uint32_t I2SCFGR; /*!< (@ 0x0000001C) I2S configuration register */ __IO uint32_t I2SPR; /*!< (@ 0x00000020) I2S prescaler register */ } SPI_TypeDef; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ /* ================ RCC ================ */ /* =========================================================================================================================== */ /** * @brief Reset and clock control (RCC) */ typedef struct /*!< RCC Structure */ { __IO uint32_t CR; /*!< (@ 0x00000000) Clock control register */ __IO uint32_t ICSCR; /*!< (@ 0x00000004) Internal clock sources calibration register */ __IO uint32_t CFGR; /*!< (@ 0x00000008) Clock configuration register */ __IO uint32_t CSSWCR; /*!< (@ 0x0000000C) Clocks Sources Software Calibration register */ __IO uint32_t RESERVED[2]; __IO uint32_t CIER; /*!< (@ 0x00000018) Clock interrupt enable register */ __IO uint32_t CIFR; /*!< (@ 0x0000001C) Clock interrupt flag register */ __IO uint32_t CSCMDR; /*!< (@ 0x00000020) Clock Switch Command register */ __IO uint32_t RESERVED1[3]; __IO uint32_t AHBRSTR; /*!< (@ 0x00000030) AHB0 macro cells reset register */ __IO uint32_t APB0RSTR; /*!< (@ 0x00000034) APB0 macro cells reset register */ __IO uint32_t APB1RSTR; /*!< (@ 0x00000038) APB1 peripheral reset register 1 */ __IO uint32_t RESERVED2; __IO uint32_t APB2RSTR; /*!< (@ 0x00000040) APB2 peripheral reset register 2 */ __IO uint32_t RESERVED3[3]; __IO uint32_t AHBENR; /*!< (@ 0x00000050) AHB0 macro cells clock enable register */ __IO uint32_t APB0ENR; /*!< (@ 0x00000054) APB0 macro cells clock enable register */ __IO uint32_t APB1ENR; /*!< (@ 0x00000058) APB1ENR1 */ __IO uint32_t RESERVED4; __IO uint32_t APB2ENR; /*!< (@ 0x00000060) APB2ENR */ __IO uint32_t RESERVED5[12]; __IO uint32_t CSR; /*!< (@ 0x00000094) CSR */ __IO uint32_t RFSWHSECR; /*!< (@ 0x00000098) RF Software High Speed External register */ __IO uint32_t RFHSECR; /*!< (@ 0x0000009C) RF High Speed External register */ } RCC_TypeDef; /*!< Size = 160 (0xA0) */ /* =========================================================================================================================== */ /* ================ PWR ================ */ /* =========================================================================================================================== */ /** * @brief Power control (PWR) */ typedef struct /*!< PWR Structure */ { __IO uint32_t CR1; /*!< (@ 0x00000000) Power control register 1 */ __IO uint32_t CR2; /*!< (@ 0x00000004) Power control register 2 */ __IO uint32_t CR3; /*!< (@ 0x00000008) Power control register 3 */ __IO uint32_t CR4; /*!< (@ 0x0000000C) Power control register 4 */ __IO uint32_t SR1; /*!< (@ 0x00000010) Power status register 1 */ __IO uint32_t SR2; /*!< (@ 0x00000014) Power status register 2 */ __IO uint32_t RESERVED; __IO uint32_t CR5; /*!< (@ 0x0000001C) Power control register 5 */ __IO uint32_t PUCRA; /*!< (@ 0x00000020) Power Port A pull-up control register */ __IO uint32_t PDCRA; /*!< (@ 0x00000024) Power Port A pull-down control register */ __IO uint32_t PUCRB; /*!< (@ 0x00000028) Power Port B pull-up control register */ __IO uint32_t PDCRB; /*!< (@ 0x0000002C) Power Port B pull-down control register */ __IO uint32_t CR6; /*!< (@ 0x00000030) Power control register 6 */ __IO uint32_t CR7; /*!< (@ 0x00000034) Power control register 7 */ __IO uint32_t SR3; /*!< (@ 0x00000038) Power status register 3 */ __IO uint32_t RESERVED1; __IO uint32_t IOxCFG; /*!< (@ 0x00000040) IO DEEPSTOP drive configuration register */ __IO uint32_t RESERVED2[16]; __IO uint32_t DBGR; /*!< (@ 0x00000084) Debug register */ __IO uint32_t EXTSRR; /*!< (@ 0x00000088) Power status clear register */ __IO uint32_t DBGSMPS; /*!< (@ 0x0000008C) This register drives some control signals for the SMPS */ __IO uint32_t TRIMR; /*!< (@ 0x00000090) This register provides the trimming values applied by hardware according to the trimmingdone at EWS. */ __IO uint32_t ENGTRIM; /*!< (@ 0x00000094) This register allows the software overloading the hardware trimming flashed at EWS. */ __IO uint32_t DBG1; /*!< (@ 0x00000098) This register shows the current states of the FLASH FSM and SMPS FSM. */ __IO uint32_t DBG2; /*!< (@ 0x0000009C) This register shows the current states of the FLASH FSM and SMPS FSM. */ } PWR_TypeDef; /*!< Size = 160 (0xA0) */ /* =========================================================================================================================== */ /* ================ SYSCFG ================ */ /* =========================================================================================================================== */ /** * @brief System configuration controller (SYSCFG) */ typedef struct /*!< SYSCFG Structure */ { __IO uint32_t DIE_ID; /*!< (@ 0x00000000) This register provides the device version and cut information. */ __IO uint32_t JTAG_ID; /*!< (@ 0x00000004) This register provides the JTAG ID of the stm32wb06. */ __IO uint32_t I2C_FMP_CTRL; /*!< (@ 0x00000008) This register allows activating the Fast-mode Plus driving capability on I2C open-drain pads. */ __IO uint32_t IO_DTR; /*!< (@ 0x0000000C) IO_DTR */ __IO uint32_t IO_IBER; /*!< (@ 0x00000010) IO_IBER */ __IO uint32_t IO_IEVR; /*!< (@ 0x00000014) I/O Interrupt polarity event register */ __IO uint32_t IO_IER; /*!< (@ 0x00000018) I/O Interrupt Enable register */ __IO uint32_t IO_ISCR; /*!< (@ 0x0000001C) I/O Interrupt Status and Clear register */ __IO uint32_t PWRC_IER; /*!< (@ 0x00000020) This register allows control of the enable or mask on the interrupt sources of the Power Controller (PWRC) block. */ __IO uint32_t PWRC_ISCR; /*!< (@ 0x00000024) Power Controller Interrupt Status and Clear register */ __IO uint32_t RESERVED; /*!< (@ 0x00000028) */ __IO uint32_t BLERXTX_DTR; /*!< (@ 0x0000002C) MR_BLE RX or TX sequence information detection type register */ __IO uint32_t BLERXTX_IBER; /*!< (@ 0x00000030) MR_BLE RX or TX sequence information detection type register */ __IO uint32_t BLERXTX_IEVR; /*!< (@ 0x00000034) MR_BLE RX or TX sequence information detection event register */ __IO uint32_t BLERXTX_IER; /*!< (@ 0x00000038) MR_BLE RX or TX Interrupt Enable Register */ __IO uint32_t BLERXTX_ISCR; /*!< (@ 0x0000003C) MR_BLE RX or TX sequence information detection status and clear register */ } SYSCFG_TypeDef; /*!< Size = 64 (0x40) */ /* =========================================================================================================================== */ /* ================ RNG ================ */ /* =========================================================================================================================== */ /** * @brief Random number generator (RNG) */ typedef struct /*!< RNG Structure */ { __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ __IO uint32_t SR; /*!< (@ 0x00000004) Status register */ __IO uint32_t VAL; /*!< (@ 0x00000008) Data register */ } RNG_TypeDef; /*!< Size = 12 (0xC) */ /* =========================================================================================================================== */ /* ================ GPIO ================ */ /* =========================================================================================================================== */ /** * @brief General-purpose I/Os (GPIO) */ typedef struct /*!< GPIO Structure */ { __IO uint32_t MODER; /*!< (@ 0x00000000) GPIO port mode register */ __IO uint32_t OTYPER; /*!< (@ 0x00000004) GPIO port output type register */ __IO uint32_t OSPEEDR; /*!< (@ 0x00000008) GPIO port output speed register */ __IO uint32_t PUPDR; /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register */ __IO uint32_t IDR; /*!< (@ 0x00000010) GPIO port input data register */ __IO uint32_t ODR; /*!< (@ 0x00000014) GPIO port output data register */ __IO uint32_t BSRR; /*!< (@ 0x00000018) GPIO port bit set/reset register */ __IO uint32_t LCKR; /*!< (@ 0x0000001C) GPIO port configuration lock register */ __IO uint32_t AFR[2]; /*!< (@ 0x00000020) GPIO alternate function register */ __IO uint32_t BRR; /*!< (@ 0x00000028) GPIO bit reset register */ } GPIO_TypeDef; /*!< Size = 44 (0x2C) */ /* =========================================================================================================================== */ /* ================ TIM ================ */ /* =========================================================================================================================== */ /** * @brief Advanced-timers (TIM) */ typedef struct /*!< TIM Structure */ { __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ __IO uint32_t SMCR; /*!< (@ 0x00000008) Slave mode control register */ __IO uint32_t DIER; /*!< (@ 0x0000000C) Interrupt enable register */ __IO uint32_t SR; /*!< (@ 0x00000010) Status register */ __IO uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ __IO uint32_t CCMR1; /*!< (@ 0x00000018) Input capture and output compare mode register 1 */ __IO uint32_t CCMR2; /*!< (@ 0x0000001C) Input capture and output compare mode register 2 */ __IO uint32_t CCER; /*!< (@ 0x00000020) Capture/compare enable register */ __IO uint32_t CNT; /*!< (@ 0x00000024) Counter */ __IO uint32_t PSC; /*!< (@ 0x00000028) Prescaler */ __IO uint32_t ARR; /*!< (@ 0x0000002C) Auto-reload register */ __IO uint32_t RCR; /*!< (@ 0x00000030) Repetition counter register */ __IO uint32_t CCR1; /*!< (@ 0x00000034) Capture/compare register 1 */ __IO uint32_t CCR2; /*!< (@ 0x00000038) Capture/compare register 2 */ __IO uint32_t CCR3; /*!< (@ 0x0000003C) Capture/compare register 3 */ __IO uint32_t CCR4; /*!< (@ 0x00000040) Capture/compare register 4 */ __IO uint32_t BDTR; /*!< (@ 0x00000044) Break and dead-time register */ __IO uint32_t RESERVED[3]; __IO uint32_t CCMR3; /*!< (@ 0x00000054) Output compare mode register 3 */ __IO uint32_t CCR5; /*!< (@ 0x00000058) Capture/compare register 4 */ __IO uint32_t CCR6; /*!< (@ 0x0000005C) Capture/compare register 4 */ __IO uint32_t AF1; /*!< (@ 0x00000060) TIM1 alternate function option register 1 */ __IO uint32_t AF2; /*!< (@ 0x00000064) TIM1 alternate function option register 2 */ } TIM_TypeDef; /*!< Size = 104 (0x68) */ /* =========================================================================================================================== */ /* ================ USART ================ */ /* =========================================================================================================================== */ /** * @brief Universal synchronous asynchronous receiver transmitter (USART) */ typedef struct /*!< USART Structure */ { __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ __IO uint32_t CR3; /*!< (@ 0x00000008) Control register 3 */ __IO uint32_t BRR; /*!< (@ 0x0000000C) Baud rate register */ __IO uint32_t GTPR; /*!< (@ 0x00000010) Guard time and prescaler register */ __IO uint32_t RTOR; /*!< (@ 0x00000014) Receiver timeout register */ __IO uint32_t RQR; /*!< (@ 0x00000018) Request register */ __IO uint32_t ISR; /*!< (@ 0x0000001C) Interrupt & status register */ __IO uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ __IO uint32_t RDR; /*!< (@ 0x00000024) Receive data register */ __IO uint32_t TDR; /*!< (@ 0x00000028) Transmit data register */ __IO uint32_t PRESC; /*!< (@ 0x0000002C) Prescaler register */ } USART_TypeDef; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ RTC ================ */ /* =========================================================================================================================== */ /** * @brief Real-time clock (RTC) */ typedef struct /*!< RTC Structure */ { __IO uint32_t TR; /*!< (@ 0x00000000) Time register */ __IO uint32_t DR; /*!< (@ 0x00000004) Date register */ __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ __IO uint32_t ISR; /*!< (@ 0x0000000C) Initialization and status register */ __IO uint32_t PRER; /*!< (@ 0x00000010) Prescaler register */ __IO uint32_t WUTR; /*!< (@ 0x00000014) Wakeup timer register */ __IO uint32_t RESERVED; __IO uint32_t ALRMAR; /*!< (@ 0x0000001C) Alarm A register */ __IO uint32_t RESERVED1; __IO uint32_t WPR; /*!< (@ 0x00000024) Write protection register */ __IO uint32_t SSR; /*!< (@ 0x00000028) Sub second register */ __IO uint32_t SHIFTR; /*!< (@ 0x0000002C) Shift control register */ __IO uint32_t RESERVED2[3]; __IO uint32_t CALR; /*!< (@ 0x0000003C) Calibration register */ __IO uint32_t RESERVED3; __IO uint32_t ALRMASSR; /*!< (@ 0x00000044) Alarm A sub second register */ __IO uint32_t RESERVED4[2]; __IO uint32_t BKP0R; /*!< (@ 0x00000050) Backup register 0 */ __IO uint32_t BKP1R; /*!< (@ 0x00000054) Backup register 1 */ } RTC_TypeDef; /*!< Size = 88 (0x58) */ /* =========================================================================================================================== */ /* ================ PKA ================ */ /* =========================================================================================================================== */ /** * @brief PKA (PKA) */ typedef struct /*!< PKA Structure */ { __IO uint32_t CSR; /*!< (@ 0x00000000) Command and status register */ __IO uint32_t ISR; /*!< (@ 0x00000004) Interrupt register */ __IO uint32_t IEN; /*!< (@ 0x00000008) Interrupt enable register */ uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ __IO uint32_t RAM[256]; /*!< PKA RAM Address offset: 0x400 -> 0x07FF */ } PKA_TypeDef; /*!< Size = 12 (0x0C) */ /* ===================================================== Bits definition for PKA RAM ===================================================== */ #define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ /* Compute ECC scalar multiplication input data */ #define PKA_ECC_SCALAR_MUL_IN_K ((0x046CU - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0490U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x04B4U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ /* Compute ECC scalar multiplication output data */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0490U - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x04B4U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0400U - PKA_RAM_OFFSET)>>2) /*!< Output ERROR */ /* =========================================================================================================================== */ /* ================ ADC ================ */ /* =========================================================================================================================== */ /** * @brief ADC (ADC) */ typedef struct /*!< ADC Structure */ { __IO uint32_t VERSION_ID; /*!< (@ 0x00000000) VERSION_ID register */ __IO uint32_t CONF; /*!< (@ 0x00000004) ADC configuration register */ __IO uint32_t CTRL; /*!< (@ 0x00000008) ADC control register */ __IO uint32_t OCM_CTRL; /*!< (@ 0x0000000C) Occasionnal mode control register */ __IO uint32_t PGA_CONF; /*!< (@ 0x00000010) PGA configuration register */ __IO uint32_t SWITCH; /*!< (@ 0x00000014) ADC switch control for Input Selection */ __IO uint32_t DF_CONF; /*!< (@ 0x00000018) Decimation filter configuration register */ __IO uint32_t DS_CONF; /*!< (@ 0x0000001C) Downsampler configuration register */ __IO uint32_t SEQ_1; /*!< (@ 0x00000020) ADC regular sequence configuration register 1 */ __IO uint32_t SEQ_2; /*!< (@ 0x00000024) ADC regular sequence configuration register 2 */ __IO uint32_t COMP_1; /*!< (@ 0x00000028) ADC Gain & offset correction values register 1 */ __IO uint32_t COMP_2; /*!< (@ 0x0000002C) ADC Gain & offset correction values register 2 */ __IO uint32_t COMP_3; /*!< (@ 0x00000030) ADC Gain & offset correction values register 3 */ __IO uint32_t COMP_4; /*!< (@ 0x00000034) ADC Gain & offset correction values register 4 */ __IO uint32_t COMP_SEL; /*!< (@ 0x00000038) ADC Gain & Offset selection values register */ __IO uint32_t WD_TH; /*!< (@ 0x0000003C) High/low limits for event monitoring a channel register */ __IO uint32_t WD_CONF; /*!< (@ 0x00000040) Channel selection for event monitoring register */ __IO uint32_t DS_DATAOUT; /*!< (@ 0x00000044) Downsampler Data output register */ __IO uint32_t DF_DATAOUT; /*!< (@ 0x00000048) Decimation filter Data output register */ __IO uint32_t IRQ_STATUS; /*!< (@ 0x0000004C) Interrupt Status register */ __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000050) Enable/disable Interrupts */ __IO uint32_t TIMER_CONF; /*!< (@ 0x00000054) Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it */ } ADC_TypeDef; /*!< Size = 88 (0x58) */ /* =========================================================================================================================== */ /* ================ AHBUPCONV ================ */ /* =========================================================================================================================== */ /** * @brief AHBUPCONV (AHBUPCONV) */ typedef struct /*!< AHBUPCONV structure */ { __IO uint32_t COMMAND; /*!< (@ 0x00000000) Command register */ __IO uint32_t STATUS; /*!< (@ 0x00000004) Status register */ } AHBUPCONV_TypeDef; /*!< Size = 8 (0x8) */ /* =========================================================================================================================== */ /* ================ BLUE ================ */ /* =========================================================================================================================== */ /** * @brief BLUE Radio (BLUE) */ typedef struct /*!< BLUE structure */ { __IO uint32_t CONTROLLERVERNUMREG; /*!< (@ 0x00000000) Controller Version Number register */ __IO uint32_t INTERRUPT1REG; /*!< (@ 0x00000004) Interrupt1 register */ __IO uint32_t INTERRUPT2REG; /*!< (@ 0x00000008) Interrupt2 register */ __IO uint32_t TIMEOUTDESTREG; /*!< (@ 0x0000000C) TimeoutDest register */ __IO uint32_t TIMEOUTREG; /*!< (@ 0x00000010) Timeout register */ __IO uint32_t TIMERCAPTUREREG; /*!< (@ 0x00000014) TimerCapture register */ __IO uint32_t CMDREG; /*!< (@ 0x00000018) Cmd register */ __IO uint32_t STATUSREG; /*!< (@ 0x0000001C) Status register */ __IO uint32_t INTERRUPT1ENABLEREG; /*!< (@ 0x00000020) Interrupt1Enable register */ __IO uint32_t INTERRUPT1LATENCYREG; /*!< (@ 0x00000024) Interrupt1Latency register */ __IO uint32_t MANAESKEY0REG; /*!< (@ 0x00000028) ManAesKey0 register */ __IO uint32_t MANAESKEY1REG; /*!< (@ 0x0000002C) ManAesKey1 register */ __IO uint32_t MANAESKEY2REG; /*!< (@ 0x00000030) ManAesKey2 register */ __IO uint32_t MANAESKEY3REG; /*!< (@ 0x00000034) ManAesKey3 register */ __IO uint32_t MANAESCLEARTEXT0REG; /*!< (@ 0x00000038) ManAesClearText0 register */ __IO uint32_t MANAESCLEARTEXT1REG; /*!< (@ 0x0000003C) ManAesClearText1 register */ __IO uint32_t MANAESCLEARTEXT2REG; /*!< (@ 0x00000040) ManAesClearText2 register */ __IO uint32_t MANAESCLEARTEXT3REG; /*!< (@ 0x00000044) ManAesClearText3 register */ __IO uint32_t MANAESCIPHERTEXT0REG; /*!< (@ 0x00000048) ManAESCipherText0 register */ __IO uint32_t MANAESCIPHERTEXT1REG; /*!< (@ 0x0000004C) ManAESCipherText1 register */ __IO uint32_t MANAESCIPHERTEXT2REG; /*!< (@ 0x00000050) ManAESCipherText2 register */ __IO uint32_t MANAESCIPHERTEXT3REG; /*!< (@ 0x00000054) ManAESCipherText3 register */ __IO uint32_t MANAESCMDREG; /*!< (@ 0x00000058) ManAESCmd register */ __IO uint32_t MANAESSTATREG; /*!< (@ 0x0000005C) ManAESStat register */ __IO uint32_t AESLEPRIVPOINTERREG; /*!< (@ 0x00000060) AesLePrivPointer register */ __IO uint32_t AESLEPRIVHASHREG; /*!< (@ 0x00000064) AesLePrivHash register */ __IO uint32_t AESLEPRIVPRANDREG; /*!< (@ 0x00000068) AesLePrivPrand register */ __IO uint32_t AESLEPRIVCMDREG; /*!< (@ 0x0000006C) AesLePrivCmd register */ __IO uint32_t AESLEPRIVSTATREG; /*!< (@ 0x00000070) AesLePrivStat register */ __IO uint32_t DEBUGCMDREG; /*!< (@ 0x00000074) DebugCmd register */ __IO uint32_t DEBUGSTATUSREG; /*!< (@ 0x00000078) DebugStatus register */ __IO uint32_t RESERVED; } BLUE_TypeDef; /*!< Size = 128 (0x80) */ /* =========================================================================================================================== */ /* ================ RADIO_CTRL ================ */ /* =========================================================================================================================== */ /** * @brief Radio Controller (RADIO_CTRL) */ typedef struct /*!< Radio Control structure */ { __IO uint32_t RADIO_CONTROL_ID; /*!< (@ 0x00000000) Radio Controller ID register */ __IO uint32_t CLK32COUNT_REG; /*!< (@ 0x00000004) Window length register */ __IO uint32_t CLK32PERIOD_REG; /*!< (@ 0x00000008) Slow clock period register */ __IO uint32_t CLK32FREQUENCY_REG; /*!< (@ 0x0000000C) Slow clock frequency register */ __IO uint32_t RADIO_CONTROL_IRQ_STATUS; /*!< (@ 0x00000010) Radio Controller Interrupt Status register */ __IO uint32_t RADIO_CONTROL_IRQ_ENABLE; /*!< (@ 0x00000014) Radio Controller Interrupt Control register */ __IO uint32_t RESERVED; } RADIO_CTRL_TypeDef; /*!< Size = 28 (0x1C) */ /* =========================================================================================================================== */ /* ================ RRM ================ */ /* =========================================================================================================================== */ /** * @brief RRM (RRM) */ typedef struct /*!< RRM structure */ { __IO uint32_t RRM_ID; /*!< (@ 0x00) RRM_ID register */ __IO uint32_t RRM_CTRL; /*!< (@ 0x04) RRM_CTRL register */ __IO uint32_t RESERVED[2]; __IO uint32_t UDRA_CTRL0; /*!< (@ 0x10) UDRA_CTRL0 register */ __IO uint32_t UDRA_IRQ_ENABLE; /*!< (@ 0x14) UDRA_IRQ_ENABLE register */ __IO uint32_t UDRA_IRQ_STATUS; /*!< (@ 0x18) UDRA_IRQ_STATUS register */ __IO uint32_t UDRA_RADIO_CFG_PTR; /*!< (@ 0x1C) UDRA_RADIO_CFG_PTR register */ __IO uint32_t SEMA_IRQ_ENABLE; /*!< (@ 0x20) SEMA_IRQ_ENABLE register */ __IO uint32_t SEMA_IRQ_STATUS; /*!< (@ 0x24) SEMA_IRQ_STATUS register */ __IO uint32_t BLE_IRQ_ENABLE; /*!< (@ 0x28) BLE_IRQ_ENABLE register */ __IO uint32_t BLE_IRQ_STATUS; /*!< (@ 0x2C) BLE_IRQ_STATUS register */ __IO uint32_t RESERVED1[12]; __IO uint32_t VP_CPU_CMD_BUS; /*!< (@ 0x60) VP_CPU_CMD_BUS register */ __IO uint32_t VP_CPU_SEMA_BUS; /*!< (@ 0x64) VP_CPU_SEMA_BUS register */ __IO uint32_t VP_CPU_IRQ_ENABLE; /*!< (@ 0x68) VP_CPU_IRQ_ENABLE register */ __IO uint32_t VP_CPU_IRQ_STATUS; /*!< (@ 0x6C) VP_CPU_IRQ_STATUS register */ __IO uint32_t RESERVED2[36]; __IO uint32_t AA0_DIG_USR; /*!< (@ 0x100+0x00) AA0_DIG_USR register */ __IO uint32_t AA1_DIG_USR; /*!< (@ 0x100+0x04) AA1_DIG_USR register */ __IO uint32_t AA2_DIG_USR; /*!< (@ 0x100+0x08) AA2_DIG_USR register */ __IO uint32_t AA3_DIG_USR; /*!< (@ 0x100+0x0C) AA3_DIG_USR register */ __IO uint32_t DEM_MOD_DIG_USR; /*!< (@ 0x100+0x10) DEM_MOD_DIG_USR register */ __IO uint32_t RADIO_FSM_USR; /*!< (@ 0x100+0x14) RADIO_FSM_USR register */ __IO uint32_t PHYCTRL_DIG_USR; /*!< (@ 0x100+0x18) PHYCTRL_DIG_USR register */ __IO uint32_t RESERVED3[10]; __IO uint32_t AFC0_DIG_ENG; /*!< (@ 0x100+0x44) AFC0_DIG_ENG register */ __IO uint32_t AFC1_DIG_ENG; /*!< (@ 0x100+0x48) AFC1_DIG_ENG register */ __IO uint32_t AFC2_DIG_ENG; /*!< (@ 0x100+0x4C) AFC2_DIG_ENG register */ __IO uint32_t AFC3_DIG_ENG; /*!< (@ 0x100+0x50) AFC3_DIG_ENG register */ __IO uint32_t CR0_DIG_ENG; /*!< (@ 0x100+0x54) CR0_DIG_ENG register */ __IO uint32_t RESERVED4[4]; __IO uint32_t CR0_LR; /*!< (@ 0x100+0x68) CR0_LR register */ __IO uint32_t VIT_CONF_DIG_ENG; /*!< (@ 0x100+0x6C) VIT_CONF_DIG_ENG register */ __IO uint32_t RESERVED5[5]; __IO uint32_t LR_PD_THR_DIG_ENG; /*!< (@ 0x100+0x84) LR_PD_THR_DIG_ENG register */ __IO uint32_t LR_RSSI_THR_DIG_ENG; /*!< (@ 0x100+0x88) LR_RSSI_THR_DIG_ENG register */ __IO uint32_t LR_AAC_THR_DIG_ENG; /*!< (@ 0x100+0x8C) LR_AAC_THR_DIG_ENG register */ __IO uint32_t RESERVED6[19]; __IO uint32_t DTB0_DIG_ENG; /*!< (@ 0x100+0xDC) DTB0_DIG_ENG register */ __IO uint32_t RESERVED7[4]; __IO uint32_t DTB5_DIG_ENG; /*!< (@ 0x100+0xF0) DTB5_DIG_ENG register */ __IO uint32_t RESERVED8[16]; __IO uint32_t MOD0_DIG_TST; /*!< (@ 0x100+0x134) MOD0_DIG_TST register */ __IO uint32_t MOD1_DIG_TST; /*!< (@ 0x100+0x138) MOD1_DIG_TST register */ __IO uint32_t MOD2_DIG_TST; /*!< (@ 0x100+0x13C) MOD2_DIG_TST register */ __IO uint32_t MOD3_DIG_TST; /*!< (@ 0x100+0x140) MOD3_DIG_TST register */ __IO uint32_t RESERVED9; __IO uint32_t RXADC_ANA_USR; /*!< (@ 0x100+0x148) RXADC_ANA_USR register */ __IO uint32_t RESERVED10[2]; __IO uint32_t LDO_ANA_ENG; /*!< (@ 0x100+0x154) LDO_ANA_ENG register */ __IO uint32_t RESERVED11[7]; __IO uint32_t CBIAS0_ANA_ENG; /*!< (@ 0x100+0x174) CBIAS0_ANA_ENG register */ __IO uint32_t CBIAS1_ANA_ENG; /*!< (@ 0x100+0x178) CBIAS1_ANA_ENG register */ __IO uint32_t CBIAS_ANA_TEST; /*!< (@ 0x100+0x17C) CBIAS_ANA_TEST register */ __IO uint32_t SYNTHCAL0_DIG_OUT; /*!< (@ 0x100+0x180) SYNTHCAL0_DIG_OUT register */ __IO uint32_t SYNTHCAL1_DIG_OUT; /*!< (@ 0x100+0x184) SYNTHCAL1_DIG_OUT register */ __IO uint32_t SYNTHCAL2_DIG_OUT; /*!< (@ 0x100+0x188) SYNTHCAL2_DIG_OUT register */ __IO uint32_t SYNTHCAL3_DIG_OUT; /*!< (@ 0x100+0x18C) SYNTHCAL3_DIG_OUT register */ __IO uint32_t SYNTHCAL4_DIG_OUT; /*!< (@ 0x100+0x190) SYNTHCAL4_DIG_OUT register */ __IO uint32_t SYNTHCAL5_DIG_OUT; /*!< (@ 0x100+0x194) SYNTHCAL5_DIG_OUT register */ __IO uint32_t FSM_STATUS_DIG_OUT;/*!< (@ 0x100+0x198) FSM_STATUS_DIG_OUT register */ __IO uint32_t IRQ_STATUS_DIG_OUT;/*!< (@ 0x100+0x19C) IRQ_STATUS_DIG_OUT register */ __IO uint32_t RESERVED12; __IO uint32_t RSSI0_DIG_OUT; /*!< (@ 0x100+0x1A4) RSSI0_DIG_OUT register */ __IO uint32_t RSSI1_DIG_OUT; /*!< (@ 0x100+0x1A8) RSSI1_DIG_OUT register */ __IO uint32_t AGC_DIG_OUT; /*!< (@ 0x100+0x1AC) AGC_DIG_OUT register */ __IO uint32_t DEMOD_DIG_OUT; /*!< (@ 0x100+0x1B0) DEMOD_DIG_OUT register */ __IO uint32_t AGC0_ANA_TST; /*!< (@ 0x100+0x1B4) AGC0_ANA_TST register */ __IO uint32_t AGC1_ANA_TST; /*!< (@ 0x100+0x1B8) AGC1_ANA_TST register */ __IO uint32_t AGC2_ANA_TST; /*!< (@ 0x100+0x1BC) AGC2_ANA_TST register */ __IO uint32_t AGC0_DIG_ENG; /*!< (@ 0x100+0x1C0) AGC0_DIG_ENG register */ __IO uint32_t AGC1_DIG_ENG; /*!< (@ 0x100+0x1C4) AGC1_DIG_ENG register */ __IO uint32_t AGC2_DIG_ENG; /*!< (@ 0x100+0x1C8) AGC2_DIG_ENG register */ __IO uint32_t AGC3_DIG_ENG; /*!< (@ 0x100+0x1CC) AGC3_DIG_ENG register */ __IO uint32_t AGC4_DIG_ENG; /*!< (@ 0x100+0x1D0) AGC4_DIG_ENG register */ __IO uint32_t AGC5_DIG_ENG; /*!< (@ 0x100+0x1D4) AGC5_DIG_ENG register */ __IO uint32_t AGC6_DIG_ENG; /*!< (@ 0x100+0x1D8) AGC6_DIG_ENG register */ __IO uint32_t AGC7_DIG_ENG; /*!< (@ 0x100+0x1DC) AGC7_DIG_ENG register */ __IO uint32_t AGC8_DIG_ENG; /*!< (@ 0x100+0x1E0) AGC8_DIG_ENG register */ __IO uint32_t AGC9_DIG_ENG; /*!< (@ 0x100+0x1E4) AGC9_DIG_ENG register */ __IO uint32_t AGC10_DIG_ENG; /*!< (@ 0x100+0x1E8) AGC10_DIG_ENG register */ __IO uint32_t AGC11_DIG_ENG; /*!< (@ 0x100+0x1EC) AGC11_DIG_ENG register */ __IO uint32_t AGC12_DIG_ENG; /*!< (@ 0x100+0x1F0) AGC12_DIG_ENG register */ __IO uint32_t AGC13_DIG_ENG; /*!< (@ 0x100+0x1F4) AGC13_DIG_ENG register */ __IO uint32_t AGC14_DIG_ENG; /*!< (@ 0x100+0x1F8) AGC14_DIG_ENG register */ __IO uint32_t AGC15_DIG_ENG; /*!< (@ 0x100+0x1FC) AGC15_DIG_ENG register */ __IO uint32_t AGC16_DIG_ENG; /*!< (@ 0x100+0x200) AGC16_DIG_ENG register */ __IO uint32_t AGC17_DIG_ENG; /*!< (@ 0x100+0x204) AGC17_DIG_ENG register */ __IO uint32_t AGC18_DIG_ENG; /*!< (@ 0x100+0x208) AGC18_DIG_ENG register */ __IO uint32_t AGC19_DIG_ENG; /*!< (@ 0x100+0x20C) AGC19_DIG_ENG register */ __IO uint32_t AGC20_DIG_ENG; /*!< (@ 0x100+0x210) AGC20_DIG_ENG register */ __IO uint32_t RESERVED13[4]; __IO uint32_t RXADC_HW_TRIM_OUT; /*!< (@ 0x100+0x224) RXADC_HW_TRIM_OUT register */ __IO uint32_t CBIAS0_HW_TRIM_OUT; /*!< (@ 0x100+0x228) CBIAS0_HW_TRIM_OUT register */ __IO uint32_t CBIAS1_HW_TRIM_OUT; /*!< (@ 0x100+0x22C) CBIAS1_HW_TRIM_OUT register */ __IO uint32_t AGC_HW_TRIM_OUT; /*!< (@ 0x100+0x230) AGC_HW_TRIM_OUT register */ __IO uint32_t RESERVED14; } RRM_TypeDef; /*!< Size = 824 (0x338) */ /* =========================================================================================================================== */ /* ================ WAKEUP ================ */ /* =========================================================================================================================== */ /** * @brief Wakeup (WAKEUP) */ typedef struct /*!< Wakeup structure */ { __IO uint32_t WAKEUP_BLOCK_VERSION; /*!< (@ 0x00000000) Wakeup block version register */ __IO uint32_t RESERVED; __IO uint32_t WAKEUP_OFFSET[2]; /*!< (@ 0x00000008) Wakeup offset_x register */ __IO uint32_t ABSOLUTE_TIME; /*!< (@ 0x00000010) Absolute time register */ __IO uint32_t MINIMUM_PERIOD_LENGTH; /*!< (@ 0x00000014) Minimum period length register */ __IO uint32_t AVERAGE_PERIOD_LENGTH; /*!< (@ 0x00000018) Average period length register */ __IO uint32_t MAXIMUM_PERIOD_LENGTH; /*!< (@ 0x0000001C) Maximum period length register */ __IO uint32_t STATISTICS_RESTART; /*!< (@ 0x00000020) Statistics restart register */ __IO uint32_t BLUE_WAKEUP_TIME; /*!< (@ 0x00000024) BLE wakeup time register */ __IO uint32_t BLUE_SLEEP_REQUEST_MODE; /*!< (@ 0x00000028) BLE sleep request mode register */ __IO uint32_t CM0_WAKEUP_TIME; /*!< (@ 0x0000002C) CPU wakeup time register */ __IO uint32_t CM0_SLEEP_REQUEST_MODE; /*!< (@ 0x00000030) CPU sleep request mode register */ __IO uint32_t RESERVED1[3]; __IO uint32_t WAKEUP_BLE_IRQ_ENABLE; /*!< (@ 0x00000040) Wakeup BLE interrupt enable register */ __IO uint32_t WAKEUP_BLE_IRQ_STATUS; /*!< (@ 0x00000044) Wakeup BLE interrupt status register */ __IO uint32_t WAKEUP_CM0_IRQ_ENABLE; /*!< (@ 0x00000048) Wakeup CPU interrupt enable register */ __IO uint32_t WAKEUP_CM0_IRQ_STATUS; /*!< (@ 0x0000004C) Wakeup CPU interrupt status register */ __IO uint32_t RESERVED2; } WAKEUP_TypeDef; /*!< Size = 84 (0x54) */ /** @} */ /* End of group Device_Peripheral_peripherals */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_peripheralAddr * @{ */ #define NVM_BASE (0x10040000U) /*!< Main FLASH base address */ #define SRAM_BASE (0x20000000U) /*!< SRAM base address */ #define PERIPH_BASE (0x40000000U) /*!< Peripheral base address */ /*!< Memory, OTP bytes */ /* Base addresses */ #define SYSTEM_MEMORY_BASE (0x10000000U) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ #define OTP_AREA_BASE (0x10001800U) /*!< OTP area : 1kB (0x10001800 – 0x10001BFF) */ #define SRAM0_BASE SRAM_BASE /*!< SRAM0 (16 KB) base address */ #define SRAM1_BASE (SRAM_BASE + 0x00004000U) /*!< SRAM1 (16 KB) base address */ #define SRAM2_BASE (SRAM_BASE + 0x00008000U) /*!< SRAM2 (16 KB) base address */ #define SRAM3_BASE (SRAM_BASE + 0x0000C000U) /*!< SRAM3 (16 KB) base address */ /* End addresses */ #define SRAM0_END_ADDR (0x20003FFFU) /*!< RAM0 : 16KB (0x20000000 – 0x20003FFF) */ #define SRAM1_END_ADDR (0x20007FFFU) /*!< RAM1 : 16KB (0x20000000 – 0x20007FFF) */ #define SRAM2_END_ADDR (0x2000BFFFU) /*!< RAM2 : 16KB (0x20000000 – 0x2000BFFF) */ #define SRAM3_END_ADDR (0x2000FFFFU) /*!< RAM3 : 16KB (0x20000000 – 0x2000FFFF) */ #define SYSTEM_MEMORY_END_ADDR (0x100017FFU) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ #define OTP_AREA_END_ADDR (0x10001BFFU) /*!< OTP area : 1KB (0x10001800 – 0x10001BFF) */ /*!< Peripheral memory map */ #define APB0PERIPH_BASE PERIPH_BASE #define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000U) #define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000U) #define APB2PERIPH_BASE (PERIPH_BASE + 0x20000000U) /*!< APB0 peripherals */ #define SYSCFG_BASE (APB0PERIPH_BASE + 0x0000U) #define FLASH_BASE (APB0PERIPH_BASE + 0x1000U) #define TIM1_BASE (APB0PERIPH_BASE + 0x2000U) #define IWDG_BASE (APB0PERIPH_BASE + 0x3000U) #define RTC_BASE (APB0PERIPH_BASE + 0x4000U) #define AHBUPCONV_BASE (APB0PERIPH_BASE + 0x5000U) /*!< APB1 peripherals */ #define I2C1_BASE (APB1PERIPH_BASE + 0x0000U) #define I2C2_BASE (APB1PERIPH_BASE + 0x1000U) #define SPI1_BASE (APB1PERIPH_BASE + 0x2000U) #define SPI2_BASE (APB1PERIPH_BASE + 0x3000U) #define USART1_BASE (APB1PERIPH_BASE + 0x4000U) #define LPUART1_BASE (APB1PERIPH_BASE + 0x5000U) #define ADC1_BASE (APB1PERIPH_BASE + 0x6000U) #define SPI3_BASE (APB1PERIPH_BASE + 0x7000U) /*!< AHB peripherals */ #define GPIOA_BASE (AHBPERIPH_BASE + 0x000000UL) #define GPIOB_BASE (AHBPERIPH_BASE + 0x100000UL) #define CRC_BASE (AHBPERIPH_BASE + 0x200000UL) #define PKA_BASE (AHBPERIPH_BASE + 0x300000UL) #define PKA_RAM_BASE (AHBPERIPH_BASE + 0x300400UL) #define RCC_BASE (AHBPERIPH_BASE + 0x400000UL) #define PWR_BASE (AHBPERIPH_BASE + 0x500000UL) #define RNG_BASE (AHBPERIPH_BASE + 0x600000UL) #define DMA1_BASE (AHBPERIPH_BASE + 0x700000UL) #define DMAMUX1_BASE (AHBPERIPH_BASE + 0x800000UL) #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) #define DMA1_Channel8_BASE (DMA1_BASE + 0x0094) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008) #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C) #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010) #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014) #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018) #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C) /*!< APB2 peripherals */ #define BLUE_BASE (APB2PERIPH_BASE + 0x0000U) #define RADIO_CTRL_BASE (APB2PERIPH_BASE + 0x1000U) #define RRM_BASE (APB2PERIPH_BASE + 0x1400U) #define WAKEUP_BASE (APB2PERIPH_BASE + 0x1800U) /** @} */ /* End of group Device_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_declaration * @{ */ /* Peripherals available on APB0 bus */ #define SYSCFG ((SYSCFG_TypeDef*) SYSCFG_BASE) #define FLASH ((FLASH_TypeDef*) FLASH_BASE) #define TIM1 ((TIM_TypeDef*) TIM1_BASE) #define IWDG ((IWDG_TypeDef*) IWDG_BASE) #define RTC ((RTC_TypeDef*) RTC_BASE) #define AHBUPCONV ((AHBUPCONV_TypeDef*) AHBUPCONV_BASE) /* Peripherals available on APB1 bus */ #define I2C1 ((I2C_TypeDef*) I2C1_BASE) #define I2C2 ((I2C_TypeDef*) I2C2_BASE) #define SPI1 ((SPI_TypeDef*) SPI1_BASE) #define SPI2 ((SPI_TypeDef*) SPI2_BASE) #define USART1 ((USART_TypeDef*) USART1_BASE) #define LPUART1 ((USART_TypeDef*) LPUART1_BASE) #define ADC1 ((ADC_TypeDef*) ADC1_BASE) #define SPI3 ((SPI_TypeDef*) SPI3_BASE) /* Peripherals available on AHB bus */ #define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) #define CRC ((CRC_TypeDef*) CRC_BASE) #define PKA ((PKA_TypeDef*) PKA_BASE) #define RCC ((RCC_TypeDef*) RCC_BASE) #define PWR ((PWR_TypeDef*) PWR_BASE) #define RNG ((RNG_TypeDef*) RNG_BASE) #define DMA1 ((DMA_TypeDef*) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) /* Peripherals available on APB2 bus */ #define BLUE ((BLUE_TypeDef*) BLUE_BASE) #define RADIO (BLUE) #define RADIO_CTRL ((RADIO_CTRL_TypeDef*) RADIO_CTRL_BASE) #define RRM ((RRM_TypeDef*) RRM_BASE) #define WAKEUP ((WAKEUP_TypeDef*) WAKEUP_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ /* ========================================= End of section using anonymous unions ========================================= */ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ #elif (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #endif /* =========================================================================================================================== */ /* ================ Pos/Mask Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup PosMask_peripherals * @{ */ /* =========================================================================================================================== */ /*===================== AHBUPCONV ===================== */ /* =========================================================================================================================== */ /* ===================================================== COMMAND ===================================================== */ #define AHBUPCONV_COMMAND_STALL_AUTO_CLEAR_Pos (5UL) /*!