1 /** 2 ****************************************************************************** 3 * @file stm32c031xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32c031xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2022 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 /** @addtogroup CMSIS_Device 28 * @{ 29 */ 30 31 /** @addtogroup stm32c031xx 32 * @{ 33 */ 34 35 #ifndef STM32C031xx_H 36 #define STM32C031xx_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif /* __cplusplus */ 41 42 /** @addtogroup Configuration_section_for_CMSIS 43 * @{ 44 */ 45 46 /** 47 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 48 */ 49 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ 50 #define __MPU_PRESENT 1 /*!< STM32C0xx provides an MPU */ 51 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ 52 #define __NVIC_PRIO_BITS 2 /*!< STM32C0xx uses 2 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief stm32c031xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ 74 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ 77 /****** STM32C0xxxx specific Interrupt Numbers ****************************************************************/ 78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 79 RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ 80 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 81 RCC_IRQn = 4, /*!< RCC global Interrupt */ 82 EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ 83 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 84 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 85 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 86 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 87 DMAMUX1_IRQn = 11, /*!< DMAMUX Interrupts */ 88 ADC1_IRQn = 12, /*!< ADC1 Interrupts */ 89 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 90 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 91 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 92 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 93 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 94 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 95 I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ 96 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 97 USART1_IRQn = 27, /*!< USART1 Interrupt */ 98 USART2_IRQn = 28, /*!< USART2 Interrupt */ 99 } IRQn_Type; 100 101 /** 102 * @} 103 */ 104 105 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ 106 #include "system_stm32c0xx.h" 107 #include <stdint.h> 108 109 /** @addtogroup Peripheral_registers_structures 110 * @{ 111 */ 112 113 /** 114 * @brief Analog to Digital Converter 115 */ 116 typedef struct 117 { 118 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 119 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 120 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 121 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 122 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 123 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 124 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 125 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 126 __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 127 __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 128 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 129 __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ 130 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ 131 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 132 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ 133 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ 134 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ 135 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ 136 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ 137 } ADC_TypeDef; 138 139 typedef struct 140 { 141 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 142 } ADC_Common_TypeDef; 143 144 /* Legacy registers naming */ 145 #define TR1 AWD1TR 146 #define TR2 AWD2TR 147 #define TR3 AWD3TR 148 149 /** 150 * @brief CRC calculation unit 151 */ 152 typedef struct 153 { 154 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 155 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 156 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 157 uint32_t RESERVED1; /*!< Reserved, 0x0C */ 158 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 159 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 160 } CRC_TypeDef; 161 162 163 /** 164 * @brief Debug MCU 165 */ 166 typedef struct 167 { 168 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 169 __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ 170 __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ 171 __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ 172 } DBG_TypeDef; 173 174 /** 175 * @brief DMA Controller 176 */ 177 typedef struct 178 { 179 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 180 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 181 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 182 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 183 } DMA_Channel_TypeDef; 184 185 typedef struct 186 { 187 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 188 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 189 } DMA_TypeDef; 190 191 /** 192 * @brief DMA Multiplexer 193 */ 194 typedef struct 195 { 196 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ 197 }DMAMUX_Channel_TypeDef; 198 199 typedef struct 200 { 201 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ 202 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ 203 }DMAMUX_ChannelStatus_TypeDef; 204 205 typedef struct 206 { 207 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ 208 }DMAMUX_RequestGen_TypeDef; 209 210 typedef struct 211 { 212 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ 213 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ 214 }DMAMUX_RequestGenStatus_TypeDef; 215 216 /** 217 * @brief Asynch Interrupt/Event Controller (EXTI) 218 */ 219 typedef struct 220 { 221 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ 222 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ 223 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ 224 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ 225 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ 226 uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ 227 uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ 228 uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ 229 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ 230 uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ 231 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ 232 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ 233 } EXTI_TypeDef; 234 235 /** 236 * @brief FLASH Registers 237 */ 238 typedef struct 239 { 240 __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ 241 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ 242 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ 243 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ 244 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ 245 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ 246 uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ 247 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ 248 __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ 249 __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ 250 __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ 251 __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ 252 __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ 253 __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ 254 uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ 255 __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ 256 } FLASH_TypeDef; 257 258 /** 259 * @brief General Purpose I/O 260 */ 261 typedef struct 262 { 263 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 264 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 265 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 266 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 267 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 268 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 269 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 270 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 271 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 272 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 273 } GPIO_TypeDef; 274 275 276 /** 277 * @brief Inter-integrated Circuit Interface 278 */ 279 typedef struct 280 { 281 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 282 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 283 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 284 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 285 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 286 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 287 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 288 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 289 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 290 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 291 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 292 } I2C_TypeDef; 293 294 /** 295 * @brief Independent WATCHDOG 296 */ 297 typedef struct 298 { 299 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 300 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 301 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 302 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 303 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 304 } IWDG_TypeDef; 305 306 307 /** 308 * @brief Power Control 309 */ 310 typedef struct 311 { 312 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ 313 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x04 */ 314 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ 315 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ 316 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ 317 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ 318 __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ 319 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 320 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ 321 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ 322 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ 323 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ 324 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ 325 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ 326 __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ 327 __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ 328 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ 329 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ 330 __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ 331 __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ 332 uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ 333 __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ 334 __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ 335 __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ 336 __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ 337 } PWR_TypeDef; 338 339 /** 340 * @brief Reset and Clock Control 341 */ 342 typedef struct 343 { 344 __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ 345 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ 346 __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ 347 uint32_t RESERVED0[3]; /*!< Reserved, Address offset: 0x0C -- 0x14 */ 348 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ 349 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ 350 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ 351 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ 352 __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ 353 __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ 354 __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ 355 __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ 356 __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ 357 __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ 358 __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ 359 __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ 360 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ 361 __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ 362 __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ 363 __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ 364 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ 365 __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ 366 __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ 367 } RCC_TypeDef; 368 369 /** 370 * @brief Real-Time Clock 371 */ 372 typedef struct 373 { 374 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 375 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 376 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ 377 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ 378 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 379 uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ 380 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ 381 uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ 382 uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ 383 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 384 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ 385 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 386 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 387 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 388 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 389 uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ 390 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ 391 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 392 uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ 393 uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ 394 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ 395 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ 396 uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ 397 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ 398 } RTC_TypeDef; 399 400 /** 401 * @brief Serial Peripheral Interface 402 */ 403 typedef struct 404 { 405 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 406 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 407 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 408 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 409 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 410 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 411 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 412 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 413 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 414 } SPI_TypeDef; 415 416 /** 417 * @brief System configuration controller 418 */ 419 typedef struct 420 { 421 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 422 uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ 423 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 424 uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ 425 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ 426 uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ 427 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ 428 } SYSCFG_TypeDef; 429 430 /** 431 * @brief TIM 432 */ 433 typedef struct 434 { 435 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 436 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 437 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 438 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 439 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 440 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 441 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 442 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 443 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 444 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 445 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 446 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 447 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 448 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 449 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 450 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 451 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 452 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 453 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 454 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 455 __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ 456 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 457 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 458 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 459 __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ 460 __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ 461 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ 462 } TIM_TypeDef; 463 464 /** 465 * @brief Universal Synchronous Asynchronous Receiver Transmitter 466 */ 467 typedef struct 468 { 469 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 470 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 471 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 472 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 473 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 474 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 475 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 476 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 477 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 478 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 479 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 480 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ 481 482 } USART_TypeDef; 483 484 /** 485 * @brief Window WATCHDOG 486 */ 487 typedef struct 488 { 489 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 490 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 491 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 492 } WWDG_TypeDef; 493 494 495 /** @addtogroup Peripheral_memory_map 496 * @{ 497 */ 498 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ 499 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ 500 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ 501 #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ 502 503 #define SRAM_SIZE_MAX (0x00003000UL) /*!< maximum SRAM size (up to 12 KBytes) */ 504 505 #define FLASH_SIZE_DEFAULT 0x8000U /*!< Flash memory default size */ 506 507 #define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ 508 ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ 509 (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) 510 511 /*!< Peripheral memory map */ 512 #define APBPERIPH_BASE (PERIPH_BASE) 513 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 514 515 /*!< APB peripherals */ 516 517 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 518 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 519 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 520 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 521 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 522 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 523 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 524 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 525 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 526 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 527 #define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) 528 #define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ 529 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 530 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 531 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 532 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 533 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 534 #define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) 535 536 537 /*!< AHB peripherals */ 538 #define DMA1_BASE (AHBPERIPH_BASE) 539 #define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) 540 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 541 #define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) 542 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) 543 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 544 545 546 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 547 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 548 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 549 550 551 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) 552 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) 553 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) 554 555 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) 556 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) 557 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) 558 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) 559 560 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) 561 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) 562 #define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) 563 564 /*!< IOPORT */ 565 #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) 566 #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) 567 #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) 568 #define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) 569 #define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) 570 571 /*!< Device Electronic Signature */ 572 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ 573 #define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */ 574 #define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */ 575 576 /** 577 * @} 578 */ 579 580 /** @addtogroup Peripheral_declaration 581 * @{ 582 */ 583 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 584 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 585 #define RTC ((RTC_TypeDef *) RTC_BASE) 586 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 587 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 588 #define USART2 ((USART_TypeDef *) USART2_BASE) 589 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 590 #define PWR ((PWR_TypeDef *) PWR_BASE) 591 #define RCC ((RCC_TypeDef *) RCC_BASE) 592 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 593 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 594 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 595 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 596 #define USART1 ((USART_TypeDef *) USART1_BASE) 597 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 598 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 599 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 600 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 601 #define CRC ((CRC_TypeDef *) CRC_BASE) 602 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 603 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 604 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 605 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 606 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 607 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 608 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) 609 #define ADC (ADC1_COMMON) /* Kept for legacy purpose */ 610 611 612 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 613 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 614 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 615 616 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) 617 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) 618 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) 619 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) 620 621 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) 622 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) 623 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) 624 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) 625 626 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) 627 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) 628 #define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) 629 630 #define DBG ((DBG_TypeDef *) DBG_BASE) 631 632 /** 633 * @} 634 */ 635 636 /** @addtogroup Exported_constants 637 * @{ 638 */ 639 640 /** @addtogroup Peripheral_Registers_Bits_Definition 641 * @{ 642 */ 643 644 /******************************************************************************/ 645 /* Peripheral Registers Bits Definition */ 646 /******************************************************************************/ 647 648 /******************************************************************************/ 649 /* */ 650 /* Analog to Digital Converter (ADC) */ 651 /* */ 652 /******************************************************************************/ 653 /******************** Bit definition for ADC_ISR register *******************/ 654 #define ADC_ISR_ADRDY_Pos (0U) 655 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 656 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 657 #define ADC_ISR_EOSMP_Pos (1U) 658 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 659 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 660 #define ADC_ISR_EOC_Pos (2U) 661 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 662 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 663 #define ADC_ISR_EOS_Pos (3U) 664 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 665 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 666 #define ADC_ISR_OVR_Pos (4U) 667 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 668 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 669 #define ADC_ISR_AWD1_Pos (7U) 670 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 671 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 672 #define ADC_ISR_AWD2_Pos (8U) 673 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 674 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 675 #define ADC_ISR_AWD3_Pos (9U) 676 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 677 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 678 #define ADC_ISR_EOCAL_Pos (11U) 679 #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 680 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ 681 #define ADC_ISR_CCRDY_Pos (13U) 682 #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ 683 #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ 684 685 /* Legacy defines */ 686 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 687 688 /******************** Bit definition for ADC_IER register *******************/ 689 #define ADC_IER_ADRDYIE_Pos (0U) 690 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 691 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 692 #define ADC_IER_EOSMPIE_Pos (1U) 693 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 694 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 695 #define ADC_IER_EOCIE_Pos (2U) 696 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 697 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 698 #define ADC_IER_EOSIE_Pos (3U) 699 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 700 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 701 #define ADC_IER_OVRIE_Pos (4U) 702 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 703 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 704 #define ADC_IER_AWD1IE_Pos (7U) 705 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 706 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 707 #define ADC_IER_AWD2IE_Pos (8U) 708 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 709 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 710 #define ADC_IER_AWD3IE_Pos (9U) 711 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 712 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 713 #define ADC_IER_EOCALIE_Pos (11U) 714 #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 715 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ 716 #define ADC_IER_CCRDYIE_Pos (13U) 717 #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ 718 #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ 719 720 /* Legacy defines */ 721 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 722 723 /******************** Bit definition for ADC_CR register ********************/ 724 #define ADC_CR_ADEN_Pos (0U) 725 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 726 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 727 #define ADC_CR_ADDIS_Pos (1U) 728 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 729 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 730 #define ADC_CR_ADSTART_Pos (2U) 731 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 732 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 733 #define ADC_CR_ADSTP_Pos (4U) 734 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 735 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 736 #define ADC_CR_ADVREGEN_Pos (28U) 737 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 738 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 739 #define ADC_CR_ADCAL_Pos (31U) 740 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 741 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 742 743 /******************** Bit definition for ADC_CFGR1 register *****************/ 744 #define ADC_CFGR1_DMAEN_Pos (0U) 745 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 746 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 747 #define ADC_CFGR1_DMACFG_Pos (1U) 748 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 749 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 750 751 #define ADC_CFGR1_SCANDIR_Pos (2U) 752 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 753 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 754 755 #define ADC_CFGR1_RES_Pos (3U) 756 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 757 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 758 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 759 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 760 761 #define ADC_CFGR1_ALIGN_Pos (5U) 762 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 763 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 764 765 #define ADC_CFGR1_EXTSEL_Pos (6U) 766 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 767 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 768 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 769 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 770 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 771 772 #define ADC_CFGR1_EXTEN_Pos (10U) 773 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 774 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 775 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 776 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 777 778 #define ADC_CFGR1_OVRMOD_Pos (12U) 779 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 780 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 781 #define ADC_CFGR1_CONT_Pos (13U) 782 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 783 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 784 #define ADC_CFGR1_WAIT_Pos (14U) 785 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 786 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 787 #define ADC_CFGR1_AUTOFF_Pos (15U) 788 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 789 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 790 #define ADC_CFGR1_DISCEN_Pos (16U) 791 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 792 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 793 #define ADC_CFGR1_CHSELRMOD_Pos (21U) 794 #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ 795 #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ 796 797 #define ADC_CFGR1_AWD1SGL_Pos (22U) 798 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 799 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 800 #define ADC_CFGR1_AWD1EN_Pos (23U) 801 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 802 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 803 804 #define ADC_CFGR1_AWD1CH_Pos (26U) 805 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 806 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 807 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 808 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 809 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 810 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 811 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 812 813 /* Legacy defines */ 814 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 815 816 /******************** Bit definition for ADC_CFGR2 register *****************/ 817 #define ADC_CFGR2_OVSE_Pos (0U) 818 #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 819 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 820 821 #define ADC_CFGR2_OVSR_Pos (2U) 822 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 823 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 824 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 825 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 826 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 827 828 #define ADC_CFGR2_OVSS_Pos (5U) 829 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 830 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 831 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 832 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 833 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 834 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 835 836 #define ADC_CFGR2_TOVS_Pos (9U) 837 #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ 838 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 839 840 #define ADC_CFGR2_LFTRIG_Pos (29U) 841 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ 842 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ 843 844 #define ADC_CFGR2_CKMODE_Pos (30U) 845 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 846 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 847 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 848 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 849 850 /******************** Bit definition for ADC_SMPR register ******************/ 851 #define ADC_SMPR_SMP1_Pos (0U) 852 #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ 853 #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ 854 #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ 855 #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ 856 #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ 857 858 #define ADC_SMPR_SMP2_Pos (4U) 859 #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ 860 #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ 861 #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ 862 #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ 863 #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ 864 865 #define ADC_SMPR_SMPSEL_Pos (8U) 866 #define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ 867 #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ 868 #define ADC_SMPR_SMPSEL0_Pos (8U) 869 #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ 870 #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ 871 #define ADC_SMPR_SMPSEL1_Pos (9U) 872 #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ 873 #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ 874 #define ADC_SMPR_SMPSEL2_Pos (10U) 875 #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ 876 #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ 877 #define ADC_SMPR_SMPSEL3_Pos (11U) 878 #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ 879 #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ 880 #define ADC_SMPR_SMPSEL4_Pos (12U) 881 #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ 882 #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ 883 #define ADC_SMPR_SMPSEL5_Pos (13U) 884 #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ 885 #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ 886 #define ADC_SMPR_SMPSEL6_Pos (14U) 887 #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ 888 #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ 889 #define ADC_SMPR_SMPSEL7_Pos (15U) 890 #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ 891 #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ 892 #define ADC_SMPR_SMPSEL8_Pos (16U) 893 #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ 894 #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ 895 #define ADC_SMPR_SMPSEL9_Pos (17U) 896 #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ 897 #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ 898 #define ADC_SMPR_SMPSEL10_Pos (18U) 899 #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ 900 #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ 901 #define ADC_SMPR_SMPSEL11_Pos (19U) 902 #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ 903 #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ 904 #define ADC_SMPR_SMPSEL12_Pos (20U) 905 #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ 906 #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ 907 #define ADC_SMPR_SMPSEL13_Pos (21U) 908 #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ 909 #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ 910 #define ADC_SMPR_SMPSEL14_Pos (22U) 911 #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ 912 #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ 913 #define ADC_SMPR_SMPSEL15_Pos (23U) 914 #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ 915 #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ 916 #define ADC_SMPR_SMPSEL16_Pos (24U) 917 #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ 918 #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ 919 #define ADC_SMPR_SMPSEL17_Pos (25U) 920 #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ 921 #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ 922 #define ADC_SMPR_SMPSEL18_Pos (26U) 923 #define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ 924 #define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ 925 926 /******************** Bit definition for ADC_AWD1TR register *******************/ 927 #define ADC_AWD1TR_LT1_Pos (0U) 928 #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ 929 #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 930 #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ 931 #define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ 932 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ 933 #define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ 934 #define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ 935 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ 936 #define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ 937 #define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ 938 #define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ 939 #define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ 940 #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ 941 #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ 942 943 #define ADC_AWD1TR_HT1_Pos (16U) 944 #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ 945 #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 946 #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ 947 #define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ 948 #define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ 949 #define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ 950 #define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ 951 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ 952 #define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ 953 #define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ 954 #define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ 955 #define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ 956 #define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ 957 #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ 958 959 /* Legacy definitions */ 960 #define ADC_TR1_LT1 ADC_AWD1TR_LT1 961 #define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 962 #define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 963 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 964 #define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 965 #define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 966 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 967 #define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 968 #define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 969 #define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 970 #define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 971 #define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 972 #define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 973 974 #define ADC_TR1_HT1 ADC_AWD1TR_HT1 975 #define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 976 #define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 977 #define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 978 #define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 979 #define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 980 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 981 #define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 982 #define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 983 #define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 984 #define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 985 #define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 986 #define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 987 988 /******************** Bit definition for ADC_AWD2TR register *******************/ 989 #define ADC_AWD2TR_LT2_Pos (0U) 990 #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ 991 #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 992 #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ 993 #define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ 994 #define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ 995 #define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ 996 #define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ 997 #define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ 998 #define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ 999 #define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ 1000 #define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ 1001 #define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ 1002 #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ 1003 #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ 1004 1005 #define ADC_AWD2TR_HT2_Pos (16U) 1006 #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ 1007 #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1008 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ 1009 #define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ 1010 #define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ 1011 #define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ 1012 #define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ 1013 #define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ 1014 #define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ 1015 #define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ 1016 #define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ 1017 #define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ 1018 #define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ 1019 #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ 1020 1021 /* Legacy definitions */ 1022 #define ADC_TR2_LT2 ADC_AWD2TR_LT2 1023 #define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 1024 #define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 1025 #define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 1026 #define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 1027 #define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 1028 #define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 1029 #define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 1030 #define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 1031 #define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 1032 #define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 1033 #define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 1034 #define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 1035 1036 #define ADC_TR2_HT2 ADC_AWD2TR_HT2 1037 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 1038 #define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 1039 #define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 1040 #define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 1041 #define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 1042 #define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 1043 #define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 1044 #define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 1045 #define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 1046 #define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 1047 #define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 1048 #define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 1049 1050 /******************** Bit definition for ADC_CHSELR register ****************/ 1051 #define ADC_CHSELR_CHSEL_Pos (0U) 1052 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFFF */ 1053 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 1054 #define ADC_CHSELR_CHSEL22_Pos (22U) 1055 #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00400000 */ 1056 #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 22, available when ADC_CFGR1_CHSELRMOD is reset */ 1057 #define ADC_CHSELR_CHSEL21_Pos (21U) 1058 #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00200000 */ 1059 #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 21, available when ADC_CFGR1_CHSELRMOD is reset */ 1060 #define ADC_CHSELR_CHSEL20_Pos (20U) 1061 #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00100000 */ 1062 #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 20, available when ADC_CFGR1_CHSELRMOD is reset */ 1063 #define ADC_CHSELR_CHSEL19_Pos (19U) 1064 #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00080000 */ 1065 #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 19, available when ADC_CFGR1_CHSELRMOD is reset */ 1066 #define ADC_CHSELR_CHSEL18_Pos (18U) 1067 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 1068 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 1069 #define ADC_CHSELR_CHSEL17_Pos (17U) 1070 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 1071 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 1072 #define ADC_CHSELR_CHSEL16_Pos (16U) 1073 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 1074 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 1075 #define ADC_CHSELR_CHSEL15_Pos (15U) 1076 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 1077 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 1078 #define ADC_CHSELR_CHSEL14_Pos (14U) 1079 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 1080 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 1081 #define ADC_CHSELR_CHSEL13_Pos (13U) 1082 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 1083 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 1084 #define ADC_CHSELR_CHSEL12_Pos (12U) 1085 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 1086 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 1087 #define ADC_CHSELR_CHSEL11_Pos (11U) 1088 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 1089 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 1090 #define ADC_CHSELR_CHSEL10_Pos (10U) 1091 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 1092 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 1093 #define ADC_CHSELR_CHSEL9_Pos (9U) 1094 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 1095 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 1096 #define ADC_CHSELR_CHSEL8_Pos (8U) 1097 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 1098 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 1099 #define ADC_CHSELR_CHSEL7_Pos (7U) 1100 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 1101 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 1102 #define ADC_CHSELR_CHSEL6_Pos (6U) 1103 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 1104 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 1105 #define ADC_CHSELR_CHSEL5_Pos (5U) 1106 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 1107 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 1108 #define ADC_CHSELR_CHSEL4_Pos (4U) 1109 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 1110 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 1111 #define ADC_CHSELR_CHSEL3_Pos (3U) 1112 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 1113 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 1114 #define ADC_CHSELR_CHSEL2_Pos (2U) 1115 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 1116 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 1117 #define ADC_CHSELR_CHSEL1_Pos (1U) 1118 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 1119 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 1120 #define ADC_CHSELR_CHSEL0_Pos (0U) 1121 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 1122 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 1123 1124 #define ADC_CHSELR_SQ_ALL_Pos (0U) 1125 #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ 1126 #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ 1127 1128 #define ADC_CHSELR_SQ8_Pos (28U) 1129 #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ 1130 #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ 1131 #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ 1132 #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ 1133 #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ 1134 #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ 1135 1136 #define ADC_CHSELR_SQ7_Pos (24U) 1137 #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ 1138 #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ 1139 #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ 1140 #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ 1141 #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ 1142 #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ 1143 1144 #define ADC_CHSELR_SQ6_Pos (20U) 1145 #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ 1146 #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ 1147 #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ 1148 #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ 1149 #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ 1150 #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ 1151 1152 #define ADC_CHSELR_SQ5_Pos (16U) 1153 #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ 1154 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ 1155 #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ 1156 #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ 1157 #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ 1158 #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ 1159 1160 #define ADC_CHSELR_SQ4_Pos (12U) 1161 #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ 1162 #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ 1163 #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ 1164 #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ 1165 #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ 1166 #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ 1167 1168 #define ADC_CHSELR_SQ3_Pos (8U) 1169 #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ 1170 #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ 1171 #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ 1172 #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ 1173 #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ 1174 #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ 1175 1176 #define ADC_CHSELR_SQ2_Pos (4U) 1177 #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ 1178 #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ 1179 #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ 1180 #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ 1181 #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ 1182 #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ 1183 1184 #define ADC_CHSELR_SQ1_Pos (0U) 1185 #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ 1186 #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ 1187 #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ 1188 #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ 1189 #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ 1190 #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ 1191 1192 /******************** Bit definition for ADC_AWD3TR register *******************/ 1193 #define ADC_AWD3TR_LT3_Pos (0U) 1194 #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ 1195 #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1196 #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ 1197 #define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ 1198 #define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ 1199 #define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ 1200 #define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ 1201 #define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ 1202 #define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ 1203 #define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ 1204 #define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ 1205 #define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ 1206 #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ 1207 #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ 1208 1209 #define ADC_AWD3TR_HT3_Pos (16U) 1210 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ 1211 #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1212 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ 1213 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ 1214 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ 1215 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ 1216 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ 1217 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ 1218 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ 1219 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ 1220 #define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ 1221 #define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ 1222 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ 1223 #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ 1224 1225 /* Legacy definitions */ 1226 #define ADC_TR3_LT3 ADC_AWD3TR_LT3 1227 #define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 1228 #define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 1229 #define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 1230 #define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 1231 #define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 1232 #define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 1233 #define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 1234 #define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 1235 #define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 1236 #define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 1237 #define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 1238 #define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 1239 1240 #define ADC_TR3_HT3 ADC_AWD3TR_HT3 1241 #define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 1242 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 1243 #define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 1244 #define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 1245 #define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 1246 #define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 1247 #define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 1248 #define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 1249 #define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 1250 #define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 1251 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 1252 #define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 1253 1254 /******************** Bit definition for ADC_DR register ********************/ 1255 #define ADC_DR_DATA_Pos (0U) 1256 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1257 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1258 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 1259 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 1260 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 1261 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 1262 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 1263 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 1264 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 1265 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 1266 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 1267 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 1268 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 1269 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 1270 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 1271 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 1272 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 1273 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 1274 1275 /******************** Bit definition for ADC_AWD2CR register ****************/ 1276 #define ADC_AWD2CR_AWD2CH_Pos (0U) 1277 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ 1278 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1279 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1280 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1281 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1282 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1283 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1284 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1285 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1286 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1287 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1288 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1289 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1290 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1291 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1292 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1293 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1294 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1295 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1296 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1297 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ 1298 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ 1299 #define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ 1300 #define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ 1301 #define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ 1302 1303 /******************** Bit definition for ADC_AWD3CR register ****************/ 1304 #define ADC_AWD3CR_AWD3CH_Pos (0U) 1305 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ 1306 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1307 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1308 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1309 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1310 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1311 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1312 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1313 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1314 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1315 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1316 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1317 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1318 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1319 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1320 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1321 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1322 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1323 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1324 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1325 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ 1326 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ 1327 #define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ 1328 #define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ 1329 #define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ 1330 1331 /******************** Bit definition for ADC_CALFACT register ***************/ 1332 #define ADC_CALFACT_CALFACT_Pos (0U) 1333 #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 1334 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ 1335 #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ 1336 #define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ 1337 #define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ 1338 #define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ 1339 #define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ 1340 #define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ 1341 #define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ 1342 1343 /************************* ADC Common registers *****************************/ 1344 /******************** Bit definition for ADC_CCR register *******************/ 1345 #define ADC_CCR_PRESC_Pos (18U) 1346 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 1347 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 1348 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 1349 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 1350 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 1351 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 1352 1353 #define ADC_CCR_VREFEN_Pos (22U) 1354 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1355 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 1356 #define ADC_CCR_TSEN_Pos (23U) 1357 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 1358 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 1359 1360 /* Legacy */ 1361 #define ADC_CCR_LFMEN_Pos (25U) 1362 #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ 1363 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32C0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32C0) */ 1364 1365 1366 /******************************************************************************/ 1367 /* */ 1368 /* CRC calculation unit */ 1369 /* */ 1370 /******************************************************************************/ 1371 /******************* Bit definition for CRC_DR register *********************/ 1372 #define CRC_DR_DR_Pos (0U) 1373 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1374 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1375 1376 /******************* Bit definition for CRC_IDR register ********************/ 1377 #define CRC_IDR_IDR_Pos (0U) 1378 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ 1379 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ 1380 1381 /******************** Bit definition for CRC_CR register ********************/ 1382 #define CRC_CR_RESET_Pos (0U) 1383 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1384 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1385 #define CRC_CR_POLYSIZE_Pos (3U) 1386 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 1387 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 1388 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 1389 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 1390 #define CRC_CR_REV_IN_Pos (5U) 1391 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1392 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1393 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1394 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1395 #define CRC_CR_REV_OUT_Pos (7U) 1396 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1397 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1398 1399 /******************* Bit definition for CRC_INIT register *******************/ 1400 #define CRC_INIT_INIT_Pos (0U) 1401 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1402 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1403 1404 /******************* Bit definition for CRC_POL register ********************/ 1405 #define CRC_POL_POL_Pos (0U) 1406 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 1407 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 1408 1409 /******************************************************************************/ 1410 /* */ 1411 /* Debug MCU */ 1412 /* */ 1413 /******************************************************************************/ 1414 1415 /********************************* DEVICE ID ********************************/ 1416 #define DEV_ID 0x453UL 1417 1418 /******************** Bit definition for DBG_IDCODE register *************/ 1419 #define DBG_IDCODE_DEV_ID_Pos (0U) 1420 #define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1421 #define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk 1422 #define DBG_IDCODE_REV_ID_Pos (16U) 1423 #define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1424 #define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk 1425 1426 /******************** Bit definition for DBG_CR register *****************/ 1427 #define DBG_CR_DBG_STOP_Pos (1U) 1428 #define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1429 #define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk 1430 #define DBG_CR_DBG_STANDBY_Pos (2U) 1431 #define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1432 #define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk 1433 1434 /******************** Bit definition for DBG_APB_FZ1 register ***********/ 1435 #define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) 1436 #define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 1437 #define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk 1438 #define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) 1439 #define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 1440 #define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk 1441 #define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) 1442 #define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1443 #define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk 1444 #define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) 1445 #define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1446 #define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk 1447 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) 1448 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ 1449 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk 1450 1451 /******************** Bit definition for DBG_APB_FZ2 register ************/ 1452 #define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) 1453 #define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 1454 #define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk 1455 #define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) 1456 #define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ 1457 #define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk 1458 #define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) 1459 #define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 1460 #define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk 1461 #define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) 1462 #define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 1463 #define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk 1464 1465 /******************************************************************************/ 1466 /* */ 1467 /* DMA Controller (DMA) */ 1468 /* */ 1469 /******************************************************************************/ 1470 1471 /******************* Bit definition for DMA_ISR register ********************/ 1472 #define DMA_ISR_GIF1_Pos (0U) 1473 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1474 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1475 #define DMA_ISR_TCIF1_Pos (1U) 1476 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1477 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1478 #define DMA_ISR_HTIF1_Pos (2U) 1479 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1480 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1481 #define DMA_ISR_TEIF1_Pos (3U) 1482 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1483 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1484 #define DMA_ISR_GIF2_Pos (4U) 1485 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1486 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1487 #define DMA_ISR_TCIF2_Pos (5U) 1488 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1489 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1490 #define DMA_ISR_HTIF2_Pos (6U) 1491 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1492 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1493 #define DMA_ISR_TEIF2_Pos (7U) 1494 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1495 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1496 #define DMA_ISR_GIF3_Pos (8U) 1497 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1498 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1499 #define DMA_ISR_TCIF3_Pos (9U) 1500 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1501 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1502 #define DMA_ISR_HTIF3_Pos (10U) 1503 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1504 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1505 #define DMA_ISR_TEIF3_Pos (11U) 1506 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1507 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1508 1509 /******************* Bit definition for DMA_IFCR register *******************/ 1510 #define DMA_IFCR_CGIF1_Pos (0U) 1511 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1512 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ 1513 #define DMA_IFCR_CTCIF1_Pos (1U) 1514 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1515 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1516 #define DMA_IFCR_CHTIF1_Pos (2U) 1517 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1518 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1519 #define DMA_IFCR_CTEIF1_Pos (3U) 1520 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1521 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1522 #define DMA_IFCR_CGIF2_Pos (4U) 1523 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1524 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1525 #define DMA_IFCR_CTCIF2_Pos (5U) 1526 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1527 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1528 #define DMA_IFCR_CHTIF2_Pos (6U) 1529 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1530 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1531 #define DMA_IFCR_CTEIF2_Pos (7U) 1532 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1533 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1534 #define DMA_IFCR_CGIF3_Pos (8U) 1535 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1536 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1537 #define DMA_IFCR_CTCIF3_Pos (9U) 1538 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1539 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1540 #define DMA_IFCR_CHTIF3_Pos (10U) 1541 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1542 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1543 #define DMA_IFCR_CTEIF3_Pos (11U) 1544 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1545 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1546 1547 /******************* Bit definition for DMA_CCR register ********************/ 1548 #define DMA_CCR_EN_Pos (0U) 1549 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1550 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1551 #define DMA_CCR_TCIE_Pos (1U) 1552 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1553 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1554 #define DMA_CCR_HTIE_Pos (2U) 1555 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1556 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1557 #define DMA_CCR_TEIE_Pos (3U) 1558 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1559 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1560 #define DMA_CCR_DIR_Pos (4U) 1561 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1562 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1563 #define DMA_CCR_CIRC_Pos (5U) 1564 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1565 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1566 #define DMA_CCR_PINC_Pos (6U) 1567 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1568 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1569 #define DMA_CCR_MINC_Pos (7U) 1570 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1571 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1572 1573 #define DMA_CCR_PSIZE_Pos (8U) 1574 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1575 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1576 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1577 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1578 1579 #define DMA_CCR_MSIZE_Pos (10U) 1580 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1581 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1582 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1583 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1584 1585 #define DMA_CCR_PL_Pos (12U) 1586 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1587 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1588 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1589 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1590 1591 #define DMA_CCR_MEM2MEM_Pos (14U) 1592 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1593 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1594 1595 /****************** Bit definition for DMA_CNDTR register *******************/ 1596 #define DMA_CNDTR_NDT_Pos (0U) 1597 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1598 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1599 1600 /****************** Bit definition for DMA_CPAR register ********************/ 1601 #define DMA_CPAR_PA_Pos (0U) 1602 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1603 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1604 1605 /****************** Bit definition for DMA_CMAR register ********************/ 1606 #define DMA_CMAR_MA_Pos (0U) 1607 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1608 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1609 1610 /******************************************************************************/ 1611 /* */ 1612 /* DMAMUX Controller */ 1613 /* */ 1614 /******************************************************************************/ 1615 /******************** Bits definition for DMAMUX_CxCR register **************/ 1616 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) 1617 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ 1618 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ 1619 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ 1620 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ 1621 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ 1622 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ 1623 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ 1624 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ 1625 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ 1626 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ 1627 #define DMAMUX_CxCR_SOIE_Pos (8U) 1628 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ 1629 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ 1630 #define DMAMUX_CxCR_EGE_Pos (9U) 1631 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ 1632 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ 1633 #define DMAMUX_CxCR_SE_Pos (16U) 1634 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ 1635 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ 1636 #define DMAMUX_CxCR_SPOL_Pos (17U) 1637 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ 1638 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ 1639 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ 1640 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ 1641 #define DMAMUX_CxCR_NBREQ_Pos (19U) 1642 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ 1643 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ 1644 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ 1645 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ 1646 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ 1647 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ 1648 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ 1649 #define DMAMUX_CxCR_SYNC_ID_Pos (24U) 1650 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ 1651 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ 1652 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ 1653 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ 1654 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ 1655 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ 1656 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ 1657 1658 /******************* Bits definition for DMAMUX_CSR register **************/ 1659 #define DMAMUX_CSR_SOF0_Pos (0U) 1660 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ 1661 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ 1662 #define DMAMUX_CSR_SOF1_Pos (1U) 1663 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ 1664 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ 1665 #define DMAMUX_CSR_SOF2_Pos (2U) 1666 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ 1667 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ 1668 1669 /******************** Bits definition for DMAMUX_CFR register **************/ 1670 #define DMAMUX_CFR_CSOF0_Pos (0U) 1671 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ 1672 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ 1673 #define DMAMUX_CFR_CSOF1_Pos (1U) 1674 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ 1675 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ 1676 #define DMAMUX_CFR_CSOF2_Pos (2U) 1677 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ 1678 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ 1679 1680 /******************** Bits definition for DMAMUX_RGxCR register ************/ 1681 #define DMAMUX_RGxCR_SIG_ID_Pos (0U) 1682 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ 1683 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ 1684 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ 1685 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ 1686 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ 1687 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ 1688 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ 1689 #define DMAMUX_RGxCR_OIE_Pos (8U) 1690 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ 1691 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ 1692 #define DMAMUX_RGxCR_GE_Pos (16U) 1693 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ 1694 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ 1695 #define DMAMUX_RGxCR_GPOL_Pos (17U) 1696 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ 1697 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ 1698 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ 1699 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ 1700 #define DMAMUX_RGxCR_GNBREQ_Pos (19U) 1701 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ 1702 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ 1703 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ 1704 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ 1705 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ 1706 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ 1707 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ 1708 1709 /******************** Bits definition for DMAMUX_RGSR register **************/ 1710 #define DMAMUX_RGSR_OF0_Pos (0U) 1711 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ 1712 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ 1713 #define DMAMUX_RGSR_OF1_Pos (1U) 1714 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ 1715 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ 1716 #define DMAMUX_RGSR_OF2_Pos (2U) 1717 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ 1718 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ 1719 #define DMAMUX_RGSR_OF3_Pos (3U) 1720 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ 1721 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ 1722 1723 /******************** Bits definition for DMAMUX_RGCFR register **************/ 1724 #define DMAMUX_RGCFR_COF0_Pos (0U) 1725 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ 1726 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ 1727 #define DMAMUX_RGCFR_COF1_Pos (1U) 1728 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ 1729 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ 1730 #define DMAMUX_RGCFR_COF2_Pos (2U) 1731 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ 1732 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ 1733 #define DMAMUX_RGCFR_COF3_Pos (3U) 1734 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ 1735 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ 1736 1737 /***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/ 1738 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U) 1739 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */ 1740 #define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */ 1741 1742 /***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/ 1743 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U) 1744 #define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */ 1745 #define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */ 1746 1747 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U) 1748 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */ 1749 #define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */ 1750 1751 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U) 1752 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */ 1753 #define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */ 1754 1755 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U) 1756 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */ 1757 #define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */ 1758 1759 /******************************************************************************/ 1760 /* */ 1761 /* External Interrupt/Event Controller */ 1762 /* */ 1763 /******************************************************************************/ 1764 /****************** Bit definition for EXTI_RTSR1 register ******************/ 1765 #define EXTI_RTSR1_RT0_Pos (0U) 1766 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 1767 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ 1768 #define EXTI_RTSR1_RT1_Pos (1U) 1769 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 1770 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ 1771 #define EXTI_RTSR1_RT2_Pos (2U) 1772 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 1773 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ 1774 #define EXTI_RTSR1_RT3_Pos (3U) 1775 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 1776 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ 1777 #define EXTI_RTSR1_RT4_Pos (4U) 1778 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 1779 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ 1780 #define EXTI_RTSR1_RT5_Pos (5U) 1781 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 1782 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ 1783 #define EXTI_RTSR1_RT6_Pos (6U) 1784 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 1785 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ 1786 #define EXTI_RTSR1_RT7_Pos (7U) 1787 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 1788 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ 1789 #define EXTI_RTSR1_RT8_Pos (8U) 1790 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 1791 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ 1792 #define EXTI_RTSR1_RT9_Pos (9U) 1793 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 1794 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ 1795 #define EXTI_RTSR1_RT10_Pos (10U) 1796 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 1797 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ 1798 #define EXTI_RTSR1_RT11_Pos (11U) 1799 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 1800 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ 1801 #define EXTI_RTSR1_RT12_Pos (12U) 1802 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 1803 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ 1804 #define EXTI_RTSR1_RT13_Pos (13U) 1805 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 1806 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ 1807 #define EXTI_RTSR1_RT14_Pos (14U) 1808 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 1809 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ 1810 #define EXTI_RTSR1_RT15_Pos (15U) 1811 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 1812 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ 1813 1814 /****************** Bit definition for EXTI_FTSR1 register ******************/ 1815 #define EXTI_FTSR1_FT0_Pos (0U) 1816 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 1817 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ 1818 #define EXTI_FTSR1_FT1_Pos (1U) 1819 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 1820 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ 1821 #define EXTI_FTSR1_FT2_Pos (2U) 1822 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 1823 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ 1824 #define EXTI_FTSR1_FT3_Pos (3U) 1825 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 1826 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ 1827 #define EXTI_FTSR1_FT4_Pos (4U) 1828 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 1829 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ 1830 #define EXTI_FTSR1_FT5_Pos (5U) 1831 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 1832 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ 1833 #define EXTI_FTSR1_FT6_Pos (6U) 1834 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 1835 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ 1836 #define EXTI_FTSR1_FT7_Pos (7U) 1837 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 1838 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ 1839 #define EXTI_FTSR1_FT8_Pos (8U) 1840 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 1841 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ 1842 #define EXTI_FTSR1_FT9_Pos (9U) 1843 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 1844 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ 1845 #define EXTI_FTSR1_FT10_Pos (10U) 1846 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 1847 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ 1848 #define EXTI_FTSR1_FT11_Pos (11U) 1849 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 1850 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ 1851 #define EXTI_FTSR1_FT12_Pos (12U) 1852 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 1853 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ 1854 #define EXTI_FTSR1_FT13_Pos (13U) 1855 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 1856 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ 1857 #define EXTI_FTSR1_FT14_Pos (14U) 1858 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 1859 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ 1860 #define EXTI_FTSR1_FT15_Pos (15U) 1861 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 1862 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ 1863 1864 /****************** Bit definition for EXTI_SWIER1 register *****************/ 1865 #define EXTI_SWIER1_SWI0_Pos (0U) 1866 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 1867 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 1868 #define EXTI_SWIER1_SWI1_Pos (1U) 1869 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 1870 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 1871 #define EXTI_SWIER1_SWI2_Pos (2U) 1872 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 1873 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 1874 #define EXTI_SWIER1_SWI3_Pos (3U) 1875 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 1876 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 1877 #define EXTI_SWIER1_SWI4_Pos (4U) 1878 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 1879 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 1880 #define EXTI_SWIER1_SWI5_Pos (5U) 1881 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 1882 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 1883 #define EXTI_SWIER1_SWI6_Pos (6U) 1884 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 1885 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 1886 #define EXTI_SWIER1_SWI7_Pos (7U) 1887 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 1888 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 1889 #define EXTI_SWIER1_SWI8_Pos (8U) 1890 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 1891 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 1892 #define EXTI_SWIER1_SWI9_Pos (9U) 1893 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 1894 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 1895 #define EXTI_SWIER1_SWI10_Pos (10U) 1896 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 1897 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 1898 #define EXTI_SWIER1_SWI11_Pos (11U) 1899 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 1900 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 1901 #define EXTI_SWIER1_SWI12_Pos (12U) 1902 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 1903 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 1904 #define EXTI_SWIER1_SWI13_Pos (13U) 1905 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 1906 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 1907 #define EXTI_SWIER1_SWI14_Pos (14U) 1908 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 1909 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 1910 #define EXTI_SWIER1_SWI15_Pos (15U) 1911 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 1912 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 1913 1914 /******************* Bit definition for EXTI_RPR1 register ******************/ 1915 #define EXTI_RPR1_RPIF0_Pos (0U) 1916 #define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ 1917 #define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ 1918 #define EXTI_RPR1_RPIF1_Pos (1U) 1919 #define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ 1920 #define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ 1921 #define EXTI_RPR1_RPIF2_Pos (2U) 1922 #define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ 1923 #define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ 1924 #define EXTI_RPR1_RPIF3_Pos (3U) 1925 #define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ 1926 #define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ 1927 #define EXTI_RPR1_RPIF4_Pos (4U) 1928 #define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ 1929 #define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ 1930 #define EXTI_RPR1_RPIF5_Pos (5U) 1931 #define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ 1932 #define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ 1933 #define EXTI_RPR1_RPIF6_Pos (6U) 1934 #define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ 1935 #define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ 1936 #define EXTI_RPR1_RPIF7_Pos (7U) 1937 #define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ 1938 #define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ 1939 #define EXTI_RPR1_RPIF8_Pos (8U) 1940 #define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ 1941 #define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ 1942 #define EXTI_RPR1_RPIF9_Pos (9U) 1943 #define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ 1944 #define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ 1945 #define EXTI_RPR1_RPIF10_Pos (10U) 1946 #define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ 1947 #define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ 1948 #define EXTI_RPR1_RPIF11_Pos (11U) 1949 #define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ 1950 #define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ 1951 #define EXTI_RPR1_RPIF12_Pos (12U) 1952 #define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ 1953 #define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ 1954 #define EXTI_RPR1_RPIF13_Pos (13U) 1955 #define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ 1956 #define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ 1957 #define EXTI_RPR1_RPIF14_Pos (14U) 1958 #define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ 1959 #define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ 1960 #define EXTI_RPR1_RPIF15_Pos (15U) 1961 #define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ 1962 #define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ 1963 1964 /******************* Bit definition for EXTI_FPR1 register ******************/ 1965 #define EXTI_FPR1_FPIF0_Pos (0U) 1966 #define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ 1967 #define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ 1968 #define EXTI_FPR1_FPIF1_Pos (1U) 1969 #define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ 1970 #define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ 1971 #define EXTI_FPR1_FPIF2_Pos (2U) 1972 #define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ 1973 #define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ 1974 #define EXTI_FPR1_FPIF3_Pos (3U) 1975 #define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ 1976 #define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ 1977 #define EXTI_FPR1_FPIF4_Pos (4U) 1978 #define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ 1979 #define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ 1980 #define EXTI_FPR1_FPIF5_Pos (5U) 1981 #define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ 1982 #define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ 1983 #define EXTI_FPR1_FPIF6_Pos (6U) 1984 #define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ 1985 #define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ 1986 #define EXTI_FPR1_FPIF7_Pos (7U) 1987 #define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ 1988 #define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ 1989 #define EXTI_FPR1_FPIF8_Pos (8U) 1990 #define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ 1991 #define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ 1992 #define EXTI_FPR1_FPIF9_Pos (9U) 1993 #define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ 1994 #define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ 1995 #define EXTI_FPR1_FPIF10_Pos (10U) 1996 #define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ 1997 #define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ 1998 #define EXTI_FPR1_FPIF11_Pos (11U) 1999 #define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ 2000 #define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ 2001 #define EXTI_FPR1_FPIF12_Pos (12U) 2002 #define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ 2003 #define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ 2004 #define EXTI_FPR1_FPIF13_Pos (13U) 2005 #define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ 2006 #define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ 2007 #define EXTI_FPR1_FPIF14_Pos (14U) 2008 #define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ 2009 #define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ 2010 #define EXTI_FPR1_FPIF15_Pos (15U) 2011 #define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ 2012 #define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ 2013 2014 /***************** Bit definition for EXTI_EXTICR1 register **************/ 2015 #define EXTI_EXTICR1_EXTI0_Pos (0U) 2016 #define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ 2017 #define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 2018 #define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ 2019 #define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ 2020 #define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ 2021 #define EXTI_EXTICR1_EXTI1_Pos (8U) 2022 #define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ 2023 #define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 2024 #define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ 2025 #define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ 2026 #define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ 2027 #define EXTI_EXTICR1_EXTI2_Pos (16U) 2028 #define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ 2029 #define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 2030 #define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ 2031 #define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ 2032 #define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ 2033 #define EXTI_EXTICR1_EXTI3_Pos (24U) 2034 #define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ 2035 #define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 2036 #define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ 2037 #define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ 2038 #define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ 2039 2040 /***************** Bit definition for EXTI_EXTICR2 register **************/ 2041 #define EXTI_EXTICR2_EXTI4_Pos (0U) 2042 #define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ 2043 #define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 2044 #define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ 2045 #define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ 2046 #define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ 2047 #define EXTI_EXTICR2_EXTI5_Pos (8U) 2048 #define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ 2049 #define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 2050 #define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ 2051 #define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ 2052 #define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ 2053 #define EXTI_EXTICR2_EXTI6_Pos (16U) 2054 #define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ 2055 #define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 2056 #define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ 2057 #define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ 2058 #define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ 2059 #define EXTI_EXTICR2_EXTI7_Pos (24U) 2060 #define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ 2061 #define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 2062 #define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ 2063 #define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ 2064 #define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ 2065 2066 /***************** Bit definition for EXTI_EXTICR3 register **************/ 2067 #define EXTI_EXTICR3_EXTI8_Pos (0U) 2068 #define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ 2069 #define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 2070 #define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ 2071 #define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ 2072 #define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ 2073 #define EXTI_EXTICR3_EXTI9_Pos (8U) 2074 #define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ 2075 #define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 2076 #define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ 2077 #define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ 2078 #define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ 2079 #define EXTI_EXTICR3_EXTI10_Pos (16U) 2080 #define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ 2081 #define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 2082 #define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ 2083 #define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ 2084 #define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ 2085 #define EXTI_EXTICR3_EXTI11_Pos (24U) 2086 #define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ 2087 #define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 2088 #define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ 2089 #define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ 2090 #define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ 2091 2092 /***************** Bit definition for EXTI_EXTICR4 register **************/ 2093 #define EXTI_EXTICR4_EXTI12_Pos (0U) 2094 #define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 2095 #define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 2096 #define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ 2097 #define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ 2098 #define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ 2099 #define EXTI_EXTICR4_EXTI13_Pos (8U) 2100 #define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ 2101 #define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 2102 #define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ 2103 #define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ 2104 #define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ 2105 #define EXTI_EXTICR4_EXTI14_Pos (16U) 2106 #define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ 2107 #define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 2108 #define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ 2109 #define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ 2110 #define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ 2111 #define EXTI_EXTICR4_EXTI15_Pos (24U) 2112 #define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ 2113 #define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 2114 #define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ 2115 #define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ 2116 #define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ 2117 2118 /******************* Bit definition for EXTI_IMR1 register ******************/ 2119 #define EXTI_IMR1_IM0_Pos (0U) 2120 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 2121 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ 2122 #define EXTI_IMR1_IM1_Pos (1U) 2123 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 2124 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ 2125 #define EXTI_IMR1_IM2_Pos (2U) 2126 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 2127 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ 2128 #define EXTI_IMR1_IM3_Pos (3U) 2129 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 2130 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ 2131 #define EXTI_IMR1_IM4_Pos (4U) 2132 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 2133 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ 2134 #define EXTI_IMR1_IM5_Pos (5U) 2135 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 2136 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ 2137 #define EXTI_IMR1_IM6_Pos (6U) 2138 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 2139 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ 2140 #define EXTI_IMR1_IM7_Pos (7U) 2141 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 2142 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ 2143 #define EXTI_IMR1_IM8_Pos (8U) 2144 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 2145 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ 2146 #define EXTI_IMR1_IM9_Pos (9U) 2147 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 2148 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ 2149 #define EXTI_IMR1_IM10_Pos (10U) 2150 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 2151 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ 2152 #define EXTI_IMR1_IM11_Pos (11U) 2153 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 2154 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ 2155 #define EXTI_IMR1_IM12_Pos (12U) 2156 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 2157 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ 2158 #define EXTI_IMR1_IM13_Pos (13U) 2159 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 2160 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ 2161 #define EXTI_IMR1_IM14_Pos (14U) 2162 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 2163 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ 2164 #define EXTI_IMR1_IM15_Pos (15U) 2165 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 2166 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ 2167 #define EXTI_IMR1_IM19_Pos (19U) 2168 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 2169 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ 2170 #define EXTI_IMR1_IM23_Pos (23U) 2171 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 2172 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ 2173 #define EXTI_IMR1_IM25_Pos (25U) 2174 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 2175 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ 2176 #define EXTI_IMR1_IM31_Pos (31U) 2177 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ 2178 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ 2179 2180 #define EXTI_IMR1_IM_Pos (0U) 2181 #define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ 2182 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ 2183 2184 /******************* Bit definition for EXTI_EMR1 register ******************/ 2185 #define EXTI_EMR1_EM0_Pos (0U) 2186 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 2187 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ 2188 #define EXTI_EMR1_EM1_Pos (1U) 2189 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 2190 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ 2191 #define EXTI_EMR1_EM2_Pos (2U) 2192 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 2193 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ 2194 #define EXTI_EMR1_EM3_Pos (3U) 2195 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 2196 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ 2197 #define EXTI_EMR1_EM4_Pos (4U) 2198 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 2199 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ 2200 #define EXTI_EMR1_EM5_Pos (5U) 2201 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 2202 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ 2203 #define EXTI_EMR1_EM6_Pos (6U) 2204 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 2205 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ 2206 #define EXTI_EMR1_EM7_Pos (7U) 2207 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 2208 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ 2209 #define EXTI_EMR1_EM8_Pos (8U) 2210 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 2211 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ 2212 #define EXTI_EMR1_EM9_Pos (9U) 2213 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 2214 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ 2215 #define EXTI_EMR1_EM10_Pos (10U) 2216 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 2217 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ 2218 #define EXTI_EMR1_EM11_Pos (11U) 2219 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 2220 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ 2221 #define EXTI_EMR1_EM12_Pos (12U) 2222 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 2223 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ 2224 #define EXTI_EMR1_EM13_Pos (13U) 2225 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 2226 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ 2227 #define EXTI_EMR1_EM14_Pos (14U) 2228 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 2229 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ 2230 #define EXTI_EMR1_EM15_Pos (15U) 2231 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 2232 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ 2233 2234 #define EXTI_EMR1_EM16_Pos (16U) 2235 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ 2236 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ 2237 #define EXTI_EMR1_EM17_Pos (17U) 2238 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ 2239 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ 2240 #define EXTI_EMR1_EM18_Pos (18U) 2241 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ 2242 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ 2243 #define EXTI_EMR1_EM19_Pos (19U) 2244 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 2245 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ 2246 #define EXTI_EMR1_EM23_Pos (23U) 2247 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ 2248 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ 2249 #define EXTI_EMR1_EM25_Pos (25U) 2250 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ 2251 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ 2252 #define EXTI_EMR1_EM31_Pos (31U) 2253 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ 2254 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ 2255 2256 2257 /******************************************************************************/ 2258 /* */ 2259 /* FLASH */ 2260 /* */ 2261 /******************************************************************************/ 2262 2263 #define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ 2264 #define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ 2265 #define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ 2266 2267 /******************* Bits definition for FLASH_ACR register *****************/ 2268 #define FLASH_ACR_LATENCY_Pos (0U) 2269 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 2270 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 2271 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2272 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 2273 #define FLASH_ACR_PRFTEN_Pos (8U) 2274 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 2275 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 2276 #define FLASH_ACR_ICEN_Pos (9U) 2277 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 2278 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk 2279 #define FLASH_ACR_ICRST_Pos (11U) 2280 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 2281 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk 2282 #define FLASH_ACR_PROGEMPTY_Pos (16U) 2283 #define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ 2284 #define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk 2285 #define FLASH_ACR_DBG_SWEN_Pos (18U) 2286 #define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ 2287 #define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk 2288 2289 /******************* Bits definition for FLASH_SR register ******************/ 2290 #define FLASH_SR_EOP_Pos (0U) 2291 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 2292 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 2293 #define FLASH_SR_OPERR_Pos (1U) 2294 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 2295 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk 2296 #define FLASH_SR_PROGERR_Pos (3U) 2297 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 2298 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk 2299 #define FLASH_SR_WRPERR_Pos (4U) 2300 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 2301 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 2302 #define FLASH_SR_PGAERR_Pos (5U) 2303 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 2304 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 2305 #define FLASH_SR_SIZERR_Pos (6U) 2306 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 2307 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk 2308 #define FLASH_SR_PGSERR_Pos (7U) 2309 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 2310 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk 2311 #define FLASH_SR_MISERR_Pos (8U) 2312 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 2313 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk 2314 #define FLASH_SR_FASTERR_Pos (9U) 2315 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 2316 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk 2317 #define FLASH_SR_RDERR_Pos (14U) 2318 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ 2319 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk 2320 #define FLASH_SR_OPTVERR_Pos (15U) 2321 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 2322 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk 2323 #define FLASH_SR_BSY1_Pos (16U) 2324 #define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ 2325 #define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk 2326 #define FLASH_SR_CFGBSY_Pos (18U) 2327 #define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ 2328 #define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk 2329 2330 /******************* Bits definition for FLASH_CR register ******************/ 2331 #define FLASH_CR_PG_Pos (0U) 2332 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 2333 #define FLASH_CR_PG FLASH_CR_PG_Msk 2334 #define FLASH_CR_PER_Pos (1U) 2335 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 2336 #define FLASH_CR_PER FLASH_CR_PER_Msk 2337 #define FLASH_CR_MER1_Pos (2U) 2338 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ 2339 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk 2340 #define FLASH_CR_PNB_Pos (3U) 2341 #define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x00000078 */ 2342 #define FLASH_CR_PNB FLASH_CR_PNB_Msk 2343 #define FLASH_CR_STRT_Pos (16U) 2344 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 2345 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 2346 #define FLASH_CR_OPTSTRT_Pos (17U) 2347 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 2348 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk 2349 #define FLASH_CR_FSTPG_Pos (18U) 2350 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 2351 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk 2352 #define FLASH_CR_EOPIE_Pos (24U) 2353 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 2354 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 2355 #define FLASH_CR_ERRIE_Pos (25U) 2356 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 2357 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk 2358 #define FLASH_CR_RDERRIE_Pos (26U) 2359 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ 2360 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk 2361 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 2362 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 2363 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk 2364 #define FLASH_CR_SEC_PROT_Pos (28U) 2365 #define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ 2366 #define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk 2367 #define FLASH_CR_OPTLOCK_Pos (30U) 2368 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 2369 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk 2370 #define FLASH_CR_LOCK_Pos (31U) 2371 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 2372 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 2373 2374 /******************* Bits definition for FLASH_OPTR register ****************/ 2375 #define FLASH_OPTR_RDP_Pos (0U) 2376 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 2377 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk 2378 #define FLASH_OPTR_BOR_EN_Pos (8U) 2379 #define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ 2380 #define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk 2381 #define FLASH_OPTR_BORR_LEV_Pos (9U) 2382 #define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ 2383 #define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk 2384 #define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ 2385 #define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ 2386 #define FLASH_OPTR_BORF_LEV_Pos (11U) 2387 #define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ 2388 #define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk 2389 #define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ 2390 #define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ 2391 #define FLASH_OPTR_nRST_STOP_Pos (13U) 2392 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ 2393 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk 2394 #define FLASH_OPTR_nRST_STDBY_Pos (14U) 2395 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ 2396 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk 2397 #define FLASH_OPTR_nRST_SHDW_Pos (15U) 2398 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ 2399 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk 2400 #define FLASH_OPTR_IWDG_SW_Pos (16U) 2401 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 2402 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk 2403 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 2404 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ 2405 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk 2406 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 2407 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ 2408 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk 2409 #define FLASH_OPTR_WWDG_SW_Pos (19U) 2410 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 2411 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk 2412 #define FLASH_OPTR_HSE_NOT_REMAPPED_Pos (21U) 2413 #define FLASH_OPTR_HSE_NOT_REMAPPED_Msk (0x1UL << FLASH_OPTR_HSE_NOT_REMAPPED_Pos) /*!< 0x00200000 */ 2414 #define FLASH_OPTR_HSE_NOT_REMAPPED FLASH_OPTR_HSE_NOT_REMAPPED_Msk 2415 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) 2416 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ 2417 #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk 2418 #define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U) 2419 #define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */ 2420 #define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk 2421 #define FLASH_OPTR_nBOOT_SEL_Pos (24U) 2422 #define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ 2423 #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk 2424 #define FLASH_OPTR_nBOOT1_Pos (25U) 2425 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ 2426 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk 2427 #define FLASH_OPTR_nBOOT0_Pos (26U) 2428 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ 2429 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk 2430 #define FLASH_OPTR_NRST_MODE_Pos (27U) 2431 #define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ 2432 #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk 2433 #define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ 2434 #define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ 2435 #define FLASH_OPTR_IRHEN_Pos (29U) 2436 #define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ 2437 #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk 2438 2439 /****************** Bits definition for FLASH_PCROP1ASR register ************/ 2440 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) 2441 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x3FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000003F */ 2442 #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk 2443 2444 /****************** Bits definition for FLASH_PCROP1AER register ************/ 2445 #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) 2446 #define FLASH_PCROP1AER_PCROP1A_END_Msk (0x3FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000003F */ 2447 #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk 2448 #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) 2449 #define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ 2450 #define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk 2451 2452 /****************** Bits definition for FLASH_WRP1AR register ***************/ 2453 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 2454 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000000F */ 2455 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk 2456 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 2457 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x000F0000 */ 2458 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk 2459 2460 /****************** Bits definition for FLASH_WRP1BR register ***************/ 2461 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 2462 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000000F */ 2463 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk 2464 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 2465 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x000F0000 */ 2466 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk 2467 2468 /****************** Bits definition for FLASH_PCROP1BSR register ************/ 2469 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) 2470 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x3FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000003F */ 2471 #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk 2472 2473 /****************** Bits definition for FLASH_PCROP1BER register ************/ 2474 #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) 2475 #define FLASH_PCROP1BER_PCROP1B_END_Msk (0x3FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000003F */ 2476 #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk 2477 2478 2479 /****************** Bits definition for FLASH_SECR register *****************/ 2480 #define FLASH_SECR_SEC_SIZE_Pos (0U) 2481 #define FLASH_SECR_SEC_SIZE_Msk (0x1FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000001F */ 2482 #define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk 2483 #define FLASH_SECR_BOOT_LOCK_Pos (16U) 2484 #define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ 2485 #define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk 2486 2487 /******************************************************************************/ 2488 /* */ 2489 /* General Purpose I/O */ 2490 /* */ 2491 /******************************************************************************/ 2492 /****************** Bits definition for GPIO_MODER register *****************/ 2493 #define GPIO_MODER_MODE0_Pos (0U) 2494 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 2495 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 2496 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 2497 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 2498 #define GPIO_MODER_MODE1_Pos (2U) 2499 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 2500 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 2501 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 2502 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 2503 #define GPIO_MODER_MODE2_Pos (4U) 2504 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 2505 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 2506 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 2507 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 2508 #define GPIO_MODER_MODE3_Pos (6U) 2509 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 2510 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 2511 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 2512 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 2513 #define GPIO_MODER_MODE4_Pos (8U) 2514 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 2515 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 2516 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 2517 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 2518 #define GPIO_MODER_MODE5_Pos (10U) 2519 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 2520 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 2521 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 2522 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 2523 #define GPIO_MODER_MODE6_Pos (12U) 2524 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 2525 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 2526 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 2527 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 2528 #define GPIO_MODER_MODE7_Pos (14U) 2529 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 2530 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 2531 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 2532 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 2533 #define GPIO_MODER_MODE8_Pos (16U) 2534 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 2535 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 2536 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 2537 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 2538 #define GPIO_MODER_MODE9_Pos (18U) 2539 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 2540 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 2541 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 2542 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 2543 #define GPIO_MODER_MODE10_Pos (20U) 2544 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 2545 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 2546 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 2547 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 2548 #define GPIO_MODER_MODE11_Pos (22U) 2549 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 2550 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 2551 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 2552 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 2553 #define GPIO_MODER_MODE12_Pos (24U) 2554 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 2555 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 2556 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 2557 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 2558 #define GPIO_MODER_MODE13_Pos (26U) 2559 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 2560 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 2561 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 2562 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 2563 #define GPIO_MODER_MODE14_Pos (28U) 2564 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 2565 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 2566 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 2567 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 2568 #define GPIO_MODER_MODE15_Pos (30U) 2569 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 2570 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 2571 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 2572 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 2573 2574 /****************** Bits definition for GPIO_OTYPER register ****************/ 2575 #define GPIO_OTYPER_OT0_Pos (0U) 2576 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 2577 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 2578 #define GPIO_OTYPER_OT1_Pos (1U) 2579 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 2580 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 2581 #define GPIO_OTYPER_OT2_Pos (2U) 2582 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 2583 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 2584 #define GPIO_OTYPER_OT3_Pos (3U) 2585 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 2586 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 2587 #define GPIO_OTYPER_OT4_Pos (4U) 2588 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 2589 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 2590 #define GPIO_OTYPER_OT5_Pos (5U) 2591 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 2592 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 2593 #define GPIO_OTYPER_OT6_Pos (6U) 2594 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 2595 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 2596 #define GPIO_OTYPER_OT7_Pos (7U) 2597 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 2598 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 2599 #define GPIO_OTYPER_OT8_Pos (8U) 2600 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 2601 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 2602 #define GPIO_OTYPER_OT9_Pos (9U) 2603 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 2604 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 2605 #define GPIO_OTYPER_OT10_Pos (10U) 2606 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 2607 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 2608 #define GPIO_OTYPER_OT11_Pos (11U) 2609 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 2610 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 2611 #define GPIO_OTYPER_OT12_Pos (12U) 2612 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 2613 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 2614 #define GPIO_OTYPER_OT13_Pos (13U) 2615 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 2616 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 2617 #define GPIO_OTYPER_OT14_Pos (14U) 2618 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 2619 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 2620 #define GPIO_OTYPER_OT15_Pos (15U) 2621 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 2622 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 2623 2624 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 2625 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 2626 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 2627 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 2628 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 2629 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 2630 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 2631 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 2632 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 2633 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 2634 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 2635 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 2636 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 2637 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 2638 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 2639 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 2640 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 2641 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 2642 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 2643 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 2644 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 2645 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 2646 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 2647 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 2648 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 2649 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 2650 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 2651 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 2652 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 2653 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 2654 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 2655 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 2656 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 2657 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 2658 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 2659 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 2660 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 2661 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 2662 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 2663 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 2664 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 2665 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 2666 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 2667 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 2668 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 2669 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 2670 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 2671 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 2672 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 2673 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 2674 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 2675 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 2676 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 2677 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 2678 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 2679 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 2680 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 2681 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 2682 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 2683 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 2684 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 2685 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 2686 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 2687 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 2688 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 2689 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 2690 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 2691 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 2692 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 2693 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 2694 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 2695 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 2696 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 2697 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 2698 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 2699 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 2700 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 2701 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 2702 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 2703 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 2704 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 2705 2706 /****************** Bits definition for GPIO_PUPDR register *****************/ 2707 #define GPIO_PUPDR_PUPD0_Pos (0U) 2708 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 2709 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 2710 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 2711 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 2712 #define GPIO_PUPDR_PUPD1_Pos (2U) 2713 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 2714 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 2715 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 2716 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 2717 #define GPIO_PUPDR_PUPD2_Pos (4U) 2718 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 2719 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 2720 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 2721 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 2722 #define GPIO_PUPDR_PUPD3_Pos (6U) 2723 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 2724 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 2725 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 2726 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 2727 #define GPIO_PUPDR_PUPD4_Pos (8U) 2728 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 2729 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 2730 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 2731 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 2732 #define GPIO_PUPDR_PUPD5_Pos (10U) 2733 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 2734 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 2735 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 2736 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 2737 #define GPIO_PUPDR_PUPD6_Pos (12U) 2738 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 2739 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 2740 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 2741 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 2742 #define GPIO_PUPDR_PUPD7_Pos (14U) 2743 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 2744 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 2745 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 2746 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 2747 #define GPIO_PUPDR_PUPD8_Pos (16U) 2748 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 2749 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 2750 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 2751 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 2752 #define GPIO_PUPDR_PUPD9_Pos (18U) 2753 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 2754 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 2755 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 2756 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 2757 #define GPIO_PUPDR_PUPD10_Pos (20U) 2758 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 2759 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 2760 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 2761 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 2762 #define GPIO_PUPDR_PUPD11_Pos (22U) 2763 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 2764 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 2765 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 2766 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 2767 #define GPIO_PUPDR_PUPD12_Pos (24U) 2768 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 2769 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 2770 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 2771 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 2772 #define GPIO_PUPDR_PUPD13_Pos (26U) 2773 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 2774 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 2775 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 2776 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 2777 #define GPIO_PUPDR_PUPD14_Pos (28U) 2778 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 2779 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 2780 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 2781 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 2782 #define GPIO_PUPDR_PUPD15_Pos (30U) 2783 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 2784 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 2785 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 2786 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 2787 2788 /****************** Bits definition for GPIO_IDR register *******************/ 2789 #define GPIO_IDR_ID0_Pos (0U) 2790 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 2791 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 2792 #define GPIO_IDR_ID1_Pos (1U) 2793 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 2794 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 2795 #define GPIO_IDR_ID2_Pos (2U) 2796 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 2797 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 2798 #define GPIO_IDR_ID3_Pos (3U) 2799 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 2800 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 2801 #define GPIO_IDR_ID4_Pos (4U) 2802 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 2803 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 2804 #define GPIO_IDR_ID5_Pos (5U) 2805 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 2806 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 2807 #define GPIO_IDR_ID6_Pos (6U) 2808 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 2809 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 2810 #define GPIO_IDR_ID7_Pos (7U) 2811 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 2812 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 2813 #define GPIO_IDR_ID8_Pos (8U) 2814 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 2815 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 2816 #define GPIO_IDR_ID9_Pos (9U) 2817 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 2818 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 2819 #define GPIO_IDR_ID10_Pos (10U) 2820 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 2821 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 2822 #define GPIO_IDR_ID11_Pos (11U) 2823 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 2824 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 2825 #define GPIO_IDR_ID12_Pos (12U) 2826 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 2827 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 2828 #define GPIO_IDR_ID13_Pos (13U) 2829 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 2830 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 2831 #define GPIO_IDR_ID14_Pos (14U) 2832 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 2833 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 2834 #define GPIO_IDR_ID15_Pos (15U) 2835 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 2836 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 2837 2838 /****************** Bits definition for GPIO_ODR register *******************/ 2839 #define GPIO_ODR_OD0_Pos (0U) 2840 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 2841 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 2842 #define GPIO_ODR_OD1_Pos (1U) 2843 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 2844 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 2845 #define GPIO_ODR_OD2_Pos (2U) 2846 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 2847 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 2848 #define GPIO_ODR_OD3_Pos (3U) 2849 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 2850 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 2851 #define GPIO_ODR_OD4_Pos (4U) 2852 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 2853 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 2854 #define GPIO_ODR_OD5_Pos (5U) 2855 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 2856 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 2857 #define GPIO_ODR_OD6_Pos (6U) 2858 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 2859 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 2860 #define GPIO_ODR_OD7_Pos (7U) 2861 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 2862 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 2863 #define GPIO_ODR_OD8_Pos (8U) 2864 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 2865 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 2866 #define GPIO_ODR_OD9_Pos (9U) 2867 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 2868 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 2869 #define GPIO_ODR_OD10_Pos (10U) 2870 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 2871 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 2872 #define GPIO_ODR_OD11_Pos (11U) 2873 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 2874 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 2875 #define GPIO_ODR_OD12_Pos (12U) 2876 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 2877 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 2878 #define GPIO_ODR_OD13_Pos (13U) 2879 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 2880 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 2881 #define GPIO_ODR_OD14_Pos (14U) 2882 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 2883 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 2884 #define GPIO_ODR_OD15_Pos (15U) 2885 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 2886 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 2887 2888 /****************** Bits definition for GPIO_BSRR register ******************/ 2889 #define GPIO_BSRR_BS0_Pos (0U) 2890 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 2891 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 2892 #define GPIO_BSRR_BS1_Pos (1U) 2893 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 2894 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 2895 #define GPIO_BSRR_BS2_Pos (2U) 2896 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 2897 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 2898 #define GPIO_BSRR_BS3_Pos (3U) 2899 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 2900 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 2901 #define GPIO_BSRR_BS4_Pos (4U) 2902 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 2903 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 2904 #define GPIO_BSRR_BS5_Pos (5U) 2905 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 2906 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 2907 #define GPIO_BSRR_BS6_Pos (6U) 2908 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 2909 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 2910 #define GPIO_BSRR_BS7_Pos (7U) 2911 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 2912 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 2913 #define GPIO_BSRR_BS8_Pos (8U) 2914 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 2915 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 2916 #define GPIO_BSRR_BS9_Pos (9U) 2917 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 2918 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 2919 #define GPIO_BSRR_BS10_Pos (10U) 2920 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 2921 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 2922 #define GPIO_BSRR_BS11_Pos (11U) 2923 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 2924 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 2925 #define GPIO_BSRR_BS12_Pos (12U) 2926 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 2927 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 2928 #define GPIO_BSRR_BS13_Pos (13U) 2929 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 2930 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 2931 #define GPIO_BSRR_BS14_Pos (14U) 2932 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 2933 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 2934 #define GPIO_BSRR_BS15_Pos (15U) 2935 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 2936 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 2937 #define GPIO_BSRR_BR0_Pos (16U) 2938 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 2939 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 2940 #define GPIO_BSRR_BR1_Pos (17U) 2941 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 2942 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 2943 #define GPIO_BSRR_BR2_Pos (18U) 2944 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 2945 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 2946 #define GPIO_BSRR_BR3_Pos (19U) 2947 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 2948 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 2949 #define GPIO_BSRR_BR4_Pos (20U) 2950 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 2951 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 2952 #define GPIO_BSRR_BR5_Pos (21U) 2953 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 2954 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 2955 #define GPIO_BSRR_BR6_Pos (22U) 2956 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 2957 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 2958 #define GPIO_BSRR_BR7_Pos (23U) 2959 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 2960 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 2961 #define GPIO_BSRR_BR8_Pos (24U) 2962 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 2963 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 2964 #define GPIO_BSRR_BR9_Pos (25U) 2965 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 2966 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 2967 #define GPIO_BSRR_BR10_Pos (26U) 2968 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 2969 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 2970 #define GPIO_BSRR_BR11_Pos (27U) 2971 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 2972 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 2973 #define GPIO_BSRR_BR12_Pos (28U) 2974 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 2975 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 2976 #define GPIO_BSRR_BR13_Pos (29U) 2977 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 2978 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 2979 #define GPIO_BSRR_BR14_Pos (30U) 2980 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 2981 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 2982 #define GPIO_BSRR_BR15_Pos (31U) 2983 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 2984 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 2985 2986 /****************** Bit definition for GPIO_LCKR register *********************/ 2987 #define GPIO_LCKR_LCK0_Pos (0U) 2988 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2989 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2990 #define GPIO_LCKR_LCK1_Pos (1U) 2991 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2992 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2993 #define GPIO_LCKR_LCK2_Pos (2U) 2994 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2995 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2996 #define GPIO_LCKR_LCK3_Pos (3U) 2997 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2998 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2999 #define GPIO_LCKR_LCK4_Pos (4U) 3000 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3001 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3002 #define GPIO_LCKR_LCK5_Pos (5U) 3003 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3004 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3005 #define GPIO_LCKR_LCK6_Pos (6U) 3006 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3007 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3008 #define GPIO_LCKR_LCK7_Pos (7U) 3009 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3010 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3011 #define GPIO_LCKR_LCK8_Pos (8U) 3012 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3013 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3014 #define GPIO_LCKR_LCK9_Pos (9U) 3015 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3016 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3017 #define GPIO_LCKR_LCK10_Pos (10U) 3018 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3019 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3020 #define GPIO_LCKR_LCK11_Pos (11U) 3021 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3022 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3023 #define GPIO_LCKR_LCK12_Pos (12U) 3024 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3025 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3026 #define GPIO_LCKR_LCK13_Pos (13U) 3027 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3028 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3029 #define GPIO_LCKR_LCK14_Pos (14U) 3030 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3031 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3032 #define GPIO_LCKR_LCK15_Pos (15U) 3033 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3034 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3035 #define GPIO_LCKR_LCKK_Pos (16U) 3036 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3037 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3038 3039 /****************** Bit definition for GPIO_AFRL register *********************/ 3040 #define GPIO_AFRL_AFSEL0_Pos (0U) 3041 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3042 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3043 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 3044 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 3045 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 3046 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 3047 #define GPIO_AFRL_AFSEL1_Pos (4U) 3048 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3049 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3050 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 3051 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 3052 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 3053 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 3054 #define GPIO_AFRL_AFSEL2_Pos (8U) 3055 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3056 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3057 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 3058 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 3059 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 3060 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 3061 #define GPIO_AFRL_AFSEL3_Pos (12U) 3062 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3063 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3064 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 3065 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 3066 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 3067 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 3068 #define GPIO_AFRL_AFSEL4_Pos (16U) 3069 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3070 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3071 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 3072 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 3073 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 3074 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 3075 #define GPIO_AFRL_AFSEL5_Pos (20U) 3076 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3077 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3078 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 3079 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 3080 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 3081 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 3082 #define GPIO_AFRL_AFSEL6_Pos (24U) 3083 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3084 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3085 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 3086 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 3087 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 3088 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 3089 #define GPIO_AFRL_AFSEL7_Pos (28U) 3090 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3091 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3092 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 3093 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 3094 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 3095 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 3096 3097 /****************** Bit definition for GPIO_AFRH register *********************/ 3098 #define GPIO_AFRH_AFSEL8_Pos (0U) 3099 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3100 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3101 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 3102 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 3103 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 3104 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 3105 #define GPIO_AFRH_AFSEL9_Pos (4U) 3106 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3107 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3108 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 3109 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 3110 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 3111 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 3112 #define GPIO_AFRH_AFSEL10_Pos (8U) 3113 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3114 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3115 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 3116 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 3117 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 3118 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 3119 #define GPIO_AFRH_AFSEL11_Pos (12U) 3120 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3121 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3122 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 3123 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 3124 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 3125 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 3126 #define GPIO_AFRH_AFSEL12_Pos (16U) 3127 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3128 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3129 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 3130 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 3131 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 3132 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 3133 #define GPIO_AFRH_AFSEL13_Pos (20U) 3134 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3135 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3136 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 3137 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 3138 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 3139 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 3140 #define GPIO_AFRH_AFSEL14_Pos (24U) 3141 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3142 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3143 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 3144 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 3145 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 3146 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 3147 #define GPIO_AFRH_AFSEL15_Pos (28U) 3148 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3149 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3150 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 3151 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 3152 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 3153 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 3154 3155 /****************** Bits definition for GPIO_BRR register ******************/ 3156 #define GPIO_BRR_BR0_Pos (0U) 3157 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 3158 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 3159 #define GPIO_BRR_BR1_Pos (1U) 3160 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 3161 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 3162 #define GPIO_BRR_BR2_Pos (2U) 3163 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 3164 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 3165 #define GPIO_BRR_BR3_Pos (3U) 3166 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 3167 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 3168 #define GPIO_BRR_BR4_Pos (4U) 3169 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 3170 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 3171 #define GPIO_BRR_BR5_Pos (5U) 3172 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 3173 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 3174 #define GPIO_BRR_BR6_Pos (6U) 3175 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 3176 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 3177 #define GPIO_BRR_BR7_Pos (7U) 3178 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 3179 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 3180 #define GPIO_BRR_BR8_Pos (8U) 3181 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 3182 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 3183 #define GPIO_BRR_BR9_Pos (9U) 3184 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 3185 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 3186 #define GPIO_BRR_BR10_Pos (10U) 3187 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 3188 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 3189 #define GPIO_BRR_BR11_Pos (11U) 3190 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 3191 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 3192 #define GPIO_BRR_BR12_Pos (12U) 3193 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 3194 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 3195 #define GPIO_BRR_BR13_Pos (13U) 3196 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 3197 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 3198 #define GPIO_BRR_BR14_Pos (14U) 3199 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 3200 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 3201 #define GPIO_BRR_BR15_Pos (15U) 3202 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 3203 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 3204 3205 3206 /******************************************************************************/ 3207 /* */ 3208 /* Inter-integrated Circuit Interface (I2C) */ 3209 /* */ 3210 /******************************************************************************/ 3211 /******************* Bit definition for I2C_CR1 register *******************/ 3212 #define I2C_CR1_PE_Pos (0U) 3213 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3214 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 3215 #define I2C_CR1_TXIE_Pos (1U) 3216 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 3217 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 3218 #define I2C_CR1_RXIE_Pos (2U) 3219 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 3220 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 3221 #define I2C_CR1_ADDRIE_Pos (3U) 3222 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 3223 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 3224 #define I2C_CR1_NACKIE_Pos (4U) 3225 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 3226 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 3227 #define I2C_CR1_STOPIE_Pos (5U) 3228 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 3229 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 3230 #define I2C_CR1_TCIE_Pos (6U) 3231 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 3232 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 3233 #define I2C_CR1_ERRIE_Pos (7U) 3234 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 3235 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 3236 #define I2C_CR1_DNF_Pos (8U) 3237 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 3238 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 3239 #define I2C_CR1_ANFOFF_Pos (12U) 3240 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 3241 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 3242 #define I2C_CR1_SWRST_Pos (13U) 3243 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 3244 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 3245 #define I2C_CR1_TXDMAEN_Pos (14U) 3246 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 3247 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 3248 #define I2C_CR1_RXDMAEN_Pos (15U) 3249 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 3250 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 3251 #define I2C_CR1_SBC_Pos (16U) 3252 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 3253 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 3254 #define I2C_CR1_NOSTRETCH_Pos (17U) 3255 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 3256 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 3257 #define I2C_CR1_WUPEN_Pos (18U) 3258 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 3259 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 3260 #define I2C_CR1_GCEN_Pos (19U) 3261 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 3262 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 3263 #define I2C_CR1_SMBHEN_Pos (20U) 3264 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 3265 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 3266 #define I2C_CR1_SMBDEN_Pos (21U) 3267 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 3268 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 3269 #define I2C_CR1_ALERTEN_Pos (22U) 3270 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 3271 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 3272 #define I2C_CR1_PECEN_Pos (23U) 3273 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 3274 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 3275 3276 /****************** Bit definition for I2C_CR2 register ********************/ 3277 #define I2C_CR2_SADD_Pos (0U) 3278 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 3279 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 3280 #define I2C_CR2_RD_WRN_Pos (10U) 3281 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 3282 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 3283 #define I2C_CR2_ADD10_Pos (11U) 3284 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 3285 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 3286 #define I2C_CR2_HEAD10R_Pos (12U) 3287 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 3288 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 3289 #define I2C_CR2_START_Pos (13U) 3290 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 3291 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 3292 #define I2C_CR2_STOP_Pos (14U) 3293 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 3294 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 3295 #define I2C_CR2_NACK_Pos (15U) 3296 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 3297 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 3298 #define I2C_CR2_NBYTES_Pos (16U) 3299 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 3300 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 3301 #define I2C_CR2_RELOAD_Pos (24U) 3302 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 3303 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 3304 #define I2C_CR2_AUTOEND_Pos (25U) 3305 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 3306 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 3307 #define I2C_CR2_PECBYTE_Pos (26U) 3308 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 3309 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 3310 3311 /******************* Bit definition for I2C_OAR1 register ******************/ 3312 #define I2C_OAR1_OA1_Pos (0U) 3313 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 3314 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 3315 #define I2C_OAR1_OA1MODE_Pos (10U) 3316 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 3317 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 3318 #define I2C_OAR1_OA1EN_Pos (15U) 3319 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 3320 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 3321 3322 /******************* Bit definition for I2C_OAR2 register ******************/ 3323 #define I2C_OAR2_OA2_Pos (1U) 3324 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 3325 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 3326 #define I2C_OAR2_OA2MSK_Pos (8U) 3327 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 3328 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 3329 #define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ 3330 #define I2C_OAR2_OA2MASK01_Pos (8U) 3331 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 3332 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 3333 #define I2C_OAR2_OA2MASK02_Pos (9U) 3334 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 3335 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 3336 #define I2C_OAR2_OA2MASK03_Pos (8U) 3337 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 3338 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 3339 #define I2C_OAR2_OA2MASK04_Pos (10U) 3340 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 3341 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 3342 #define I2C_OAR2_OA2MASK05_Pos (8U) 3343 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 3344 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 3345 #define I2C_OAR2_OA2MASK06_Pos (9U) 3346 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 3347 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 3348 #define I2C_OAR2_OA2MASK07_Pos (8U) 3349 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 3350 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 3351 #define I2C_OAR2_OA2EN_Pos (15U) 3352 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 3353 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 3354 3355 /******************* Bit definition for I2C_TIMINGR register *******************/ 3356 #define I2C_TIMINGR_SCLL_Pos (0U) 3357 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 3358 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 3359 #define I2C_TIMINGR_SCLH_Pos (8U) 3360 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 3361 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 3362 #define I2C_TIMINGR_SDADEL_Pos (16U) 3363 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 3364 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 3365 #define I2C_TIMINGR_SCLDEL_Pos (20U) 3366 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 3367 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 3368 #define I2C_TIMINGR_PRESC_Pos (28U) 3369 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 3370 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 3371 3372 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 3373 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 3374 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 3375 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 3376 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 3377 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 3378 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 3379 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 3380 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 3381 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 3382 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 3383 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 3384 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 3385 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 3386 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 3387 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 3388 3389 /****************** Bit definition for I2C_ISR register *********************/ 3390 #define I2C_ISR_TXE_Pos (0U) 3391 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 3392 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 3393 #define I2C_ISR_TXIS_Pos (1U) 3394 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 3395 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 3396 #define I2C_ISR_RXNE_Pos (2U) 3397 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 3398 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 3399 #define I2C_ISR_ADDR_Pos (3U) 3400 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 3401 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 3402 #define I2C_ISR_NACKF_Pos (4U) 3403 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 3404 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 3405 #define I2C_ISR_STOPF_Pos (5U) 3406 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 3407 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 3408 #define I2C_ISR_TC_Pos (6U) 3409 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 3410 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 3411 #define I2C_ISR_TCR_Pos (7U) 3412 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 3413 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 3414 #define I2C_ISR_BERR_Pos (8U) 3415 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 3416 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 3417 #define I2C_ISR_ARLO_Pos (9U) 3418 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 3419 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 3420 #define I2C_ISR_OVR_Pos (10U) 3421 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 3422 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 3423 #define I2C_ISR_PECERR_Pos (11U) 3424 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 3425 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 3426 #define I2C_ISR_TIMEOUT_Pos (12U) 3427 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 3428 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 3429 #define I2C_ISR_ALERT_Pos (13U) 3430 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 3431 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 3432 #define I2C_ISR_BUSY_Pos (15U) 3433 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 3434 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 3435 #define I2C_ISR_DIR_Pos (16U) 3436 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 3437 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 3438 #define I2C_ISR_ADDCODE_Pos (17U) 3439 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 3440 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 3441 3442 /****************** Bit definition for I2C_ICR register *********************/ 3443 #define I2C_ICR_ADDRCF_Pos (3U) 3444 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 3445 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 3446 #define I2C_ICR_NACKCF_Pos (4U) 3447 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 3448 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 3449 #define I2C_ICR_STOPCF_Pos (5U) 3450 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 3451 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 3452 #define I2C_ICR_BERRCF_Pos (8U) 3453 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 3454 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 3455 #define I2C_ICR_ARLOCF_Pos (9U) 3456 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 3457 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 3458 #define I2C_ICR_OVRCF_Pos (10U) 3459 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 3460 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 3461 #define I2C_ICR_PECCF_Pos (11U) 3462 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 3463 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 3464 #define I2C_ICR_TIMOUTCF_Pos (12U) 3465 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 3466 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 3467 #define I2C_ICR_ALERTCF_Pos (13U) 3468 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 3469 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 3470 3471 /****************** Bit definition for I2C_PECR register *********************/ 3472 #define I2C_PECR_PEC_Pos (0U) 3473 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 3474 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 3475 3476 /****************** Bit definition for I2C_RXDR register *********************/ 3477 #define I2C_RXDR_RXDATA_Pos (0U) 3478 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 3479 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 3480 3481 /****************** Bit definition for I2C_TXDR register *********************/ 3482 #define I2C_TXDR_TXDATA_Pos (0U) 3483 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 3484 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 3485 3486 3487 /******************************************************************************/ 3488 /* */ 3489 /* Independent WATCHDOG (IWDG) */ 3490 /* */ 3491 /******************************************************************************/ 3492 /******************* Bit definition for IWDG_KR register ********************/ 3493 #define IWDG_KR_KEY_Pos (0U) 3494 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3495 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 3496 3497 /******************* Bit definition for IWDG_PR register ********************/ 3498 #define IWDG_PR_PR_Pos (0U) 3499 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3500 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 3501 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3502 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3503 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3504 3505 /******************* Bit definition for IWDG_RLR register *******************/ 3506 #define IWDG_RLR_RL_Pos (0U) 3507 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3508 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 3509 3510 /******************* Bit definition for IWDG_SR register ********************/ 3511 #define IWDG_SR_PVU_Pos (0U) 3512 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3513 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3514 #define IWDG_SR_RVU_Pos (1U) 3515 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3516 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3517 #define IWDG_SR_WVU_Pos (2U) 3518 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 3519 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 3520 3521 /******************* Bit definition for IWDG_KR register ********************/ 3522 #define IWDG_WINR_WIN_Pos (0U) 3523 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 3524 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 3525 3526 3527 /******************************************************************************/ 3528 /* */ 3529 /* Power Control */ 3530 /* */ 3531 /******************************************************************************/ 3532 #define PWR_BOR_SUPPORT /*!< PWR feature available only on specific devices: Brown-Out Reset feature */ 3533 #define PWR_SHDW_SUPPORT /*!< PWR feature available only on specific devices: Shutdown mode */ 3534 3535 /******************** Bit definition for PWR_CR1 register ********************/ 3536 #define PWR_CR1_LPMS_Pos (0U) 3537 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 3538 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */ 3539 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ 3540 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ 3541 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ 3542 #define PWR_CR1_FPD_STOP_Pos (3U) 3543 #define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */ 3544 #define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */ 3545 #define PWR_CR1_FPD_SLP_Pos (5U) 3546 #define PWR_CR1_FPD_SLP_Msk (0x1UL << PWR_CR1_FPD_SLP_Pos) /*!< 0x00000020 */ 3547 #define PWR_CR1_FPD_SLP PWR_CR1_FPD_SLP_Msk /*!< Flash power down mode during sleep */ 3548 3549 /******************** Bit definition for PWR_CR3 register ********************/ 3550 #define PWR_CR3_EWUP_Pos (0U) 3551 #define PWR_CR3_EWUP_Msk (0x2FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000002F */ 3552 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up Lines */ 3553 #define PWR_CR3_EWUP1_Pos (0U) 3554 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 3555 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Line 1 */ 3556 #define PWR_CR3_EWUP2_Pos (1U) 3557 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ 3558 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable external WKUP pin 2 */ 3559 #define PWR_CR3_EWUP3_Pos (2U) 3560 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ 3561 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP pin 3 */ 3562 #define PWR_CR3_EWUP4_Pos (3U) 3563 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ 3564 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable external WKUP pin 4 */ 3565 #define PWR_CR3_EWUP6_Pos (5U) 3566 #define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */ 3567 #define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable external WKUP pin 6 */ 3568 #define PWR_CR3_APC_Pos (10U) 3569 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 3570 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ 3571 #define PWR_CR3_EIWUL_Pos (15U) 3572 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */ 3573 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */ 3574 3575 /******************** Bit definition for PWR_CR4 register ********************/ 3576 #define PWR_CR4_WP_Pos (0U) 3577 #define PWR_CR4_WP_Msk (0x2FUL << PWR_CR4_WP_Pos) /*!< 0x0000002F */ 3578 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Line polarity */ 3579 #define PWR_CR4_WP1_Pos (0U) 3580 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 3581 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Line 1 polarity */ 3582 #define PWR_CR4_WP2_Pos (1U) 3583 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ 3584 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Line 2 polarity */ 3585 #define PWR_CR4_WP3_Pos (2U) 3586 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ 3587 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Line 3 polarity */ 3588 #define PWR_CR4_WP4_Pos (3U) 3589 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ 3590 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Line 4 polarity */ 3591 #define PWR_CR4_WP6_Pos (5U) 3592 #define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */ 3593 #define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Line 6 polarity */ 3594 3595 /******************** Bit definition for PWR_SR1 register ********************/ 3596 #define PWR_SR1_WUF_Pos (0U) 3597 #define PWR_SR1_WUF_Msk (0x2FUL << PWR_SR1_WUF_Pos) /*!< 0x0000002F */ 3598 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */ 3599 #define PWR_SR1_WUF1_Pos (0U) 3600 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 3601 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */ 3602 #define PWR_SR1_WUF2_Pos (1U) 3603 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ 3604 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */ 3605 #define PWR_SR1_WUF3_Pos (2U) 3606 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ 3607 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wakeup Flag 3 */ 3608 #define PWR_SR1_WUF4_Pos (3U) 3609 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ 3610 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */ 3611 #define PWR_SR1_WUF6_Pos (5U) 3612 #define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */ 3613 #define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */ 3614 #define PWR_SR1_SBF_Pos (8U) 3615 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ 3616 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */ 3617 #define PWR_SR1_WUFI_Pos (15U) 3618 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 3619 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */ 3620 3621 /******************** Bit definition for PWR_SR2 register ********************/ 3622 #define PWR_SR2_FLASH_RDY_Pos (7U) 3623 #define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */ 3624 #define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */ 3625 3626 /******************** Bit definition for PWR_SCR register ********************/ 3627 #define PWR_SCR_CWUF_Pos (0U) 3628 #define PWR_SCR_CWUF_Msk (0x2FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000002F */ 3629 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ 3630 #define PWR_SCR_CWUF1_Pos (0U) 3631 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 3632 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ 3633 #define PWR_SCR_CWUF2_Pos (1U) 3634 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ 3635 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ 3636 #define PWR_SCR_CWUF3_Pos (2U) 3637 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ 3638 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */ 3639 #define PWR_SCR_CWUF4_Pos (3U) 3640 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ 3641 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ 3642 #define PWR_SCR_CWUF6_Pos (5U) 3643 #define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */ 3644 #define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */ 3645 #define PWR_SCR_CSBF_Pos (8U) 3646 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ 3647 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */ 3648 3649 /******************** Bit definition for PWR_PUCRA register *****************/ 3650 #define PWR_PUCRA_PU0_Pos (0U) 3651 #define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */ 3652 #define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */ 3653 #define PWR_PUCRA_PU1_Pos (1U) 3654 #define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */ 3655 #define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */ 3656 #define PWR_PUCRA_PU2_Pos (2U) 3657 #define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */ 3658 #define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */ 3659 #define PWR_PUCRA_PU3_Pos (3U) 3660 #define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */ 3661 #define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */ 3662 #define PWR_PUCRA_PU4_Pos (4U) 3663 #define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */ 3664 #define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */ 3665 #define PWR_PUCRA_PU5_Pos (5U) 3666 #define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */ 3667 #define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */ 3668 #define PWR_PUCRA_PU6_Pos (6U) 3669 #define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */ 3670 #define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */ 3671 #define PWR_PUCRA_PU7_Pos (7U) 3672 #define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */ 3673 #define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */ 3674 #define PWR_PUCRA_PU8_Pos (8U) 3675 #define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */ 3676 #define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */ 3677 #define PWR_PUCRA_PU9_Pos (9U) 3678 #define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */ 3679 #define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */ 3680 #define PWR_PUCRA_PU10_Pos (10U) 3681 #define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */ 3682 #define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */ 3683 #define PWR_PUCRA_PU11_Pos (11U) 3684 #define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */ 3685 #define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */ 3686 #define PWR_PUCRA_PU12_Pos (12U) 3687 #define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */ 3688 #define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */ 3689 #define PWR_PUCRA_PU13_Pos (13U) 3690 #define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */ 3691 #define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */ 3692 #define PWR_PUCRA_PU14_Pos (14U) 3693 #define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */ 3694 #define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */ 3695 #define PWR_PUCRA_PU15_Pos (15U) 3696 #define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */ 3697 #define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */ 3698 /******************** Bit definition for PWR_PDCRA register *****************/ 3699 #define PWR_PDCRA_PD0_Pos (0U) 3700 #define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */ 3701 #define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */ 3702 #define PWR_PDCRA_PD1_Pos (1U) 3703 #define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */ 3704 #define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */ 3705 #define PWR_PDCRA_PD2_Pos (2U) 3706 #define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */ 3707 #define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */ 3708 #define PWR_PDCRA_PD3_Pos (3U) 3709 #define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */ 3710 #define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */ 3711 #define PWR_PDCRA_PD4_Pos (4U) 3712 #define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */ 3713 #define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */ 3714 #define PWR_PDCRA_PD5_Pos (5U) 3715 #define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */ 3716 #define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */ 3717 #define PWR_PDCRA_PD6_Pos (6U) 3718 #define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */ 3719 #define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */ 3720 #define PWR_PDCRA_PD7_Pos (7U) 3721 #define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */ 3722 #define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */ 3723 #define PWR_PDCRA_PD8_Pos (8U) 3724 #define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */ 3725 #define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */ 3726 #define PWR_PDCRA_PD9_Pos (9U) 3727 #define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */ 3728 #define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */ 3729 #define PWR_PDCRA_PD10_Pos (10U) 3730 #define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */ 3731 #define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */ 3732 #define PWR_PDCRA_PD11_Pos (11U) 3733 #define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */ 3734 #define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */ 3735 #define PWR_PDCRA_PD12_Pos (12U) 3736 #define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */ 3737 #define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */ 3738 #define PWR_PDCRA_PD13_Pos (13U) 3739 #define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */ 3740 #define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */ 3741 #define PWR_PDCRA_PD14_Pos (14U) 3742 #define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */ 3743 #define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */ 3744 #define PWR_PDCRA_PD15_Pos (15U) 3745 #define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */ 3746 #define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */ 3747 /******************** Bit definition for PWR_PUCRB register *****************/ 3748 #define PWR_PUCRB_PU0_Pos (0U) 3749 #define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */ 3750 #define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */ 3751 #define PWR_PUCRB_PU1_Pos (1U) 3752 #define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */ 3753 #define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */ 3754 #define PWR_PUCRB_PU2_Pos (2U) 3755 #define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */ 3756 #define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */ 3757 #define PWR_PUCRB_PU3_Pos (3U) 3758 #define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */ 3759 #define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */ 3760 #define PWR_PUCRB_PU4_Pos (4U) 3761 #define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */ 3762 #define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */ 3763 #define PWR_PUCRB_PU5_Pos (5U) 3764 #define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */ 3765 #define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */ 3766 #define PWR_PUCRB_PU6_Pos (6U) 3767 #define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */ 3768 #define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */ 3769 #define PWR_PUCRB_PU7_Pos (7U) 3770 #define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */ 3771 #define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */ 3772 #define PWR_PUCRB_PU8_Pos (8U) 3773 #define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */ 3774 #define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */ 3775 #define PWR_PUCRB_PU9_Pos (9U) 3776 #define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */ 3777 #define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */ 3778 #define PWR_PUCRB_PU10_Pos (10U) 3779 #define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */ 3780 #define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */ 3781 #define PWR_PUCRB_PU11_Pos (11U) 3782 #define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */ 3783 #define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */ 3784 #define PWR_PUCRB_PU12_Pos (12U) 3785 #define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */ 3786 #define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */ 3787 #define PWR_PUCRB_PU13_Pos (13U) 3788 #define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */ 3789 #define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */ 3790 #define PWR_PUCRB_PU14_Pos (14U) 3791 #define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */ 3792 #define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */ 3793 #define PWR_PUCRB_PU15_Pos (15U) 3794 #define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */ 3795 #define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */ 3796 /******************** Bit definition for PWR_PDCRB register *****************/ 3797 #define PWR_PDCRB_PD0_Pos (0U) 3798 #define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */ 3799 #define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */ 3800 #define PWR_PDCRB_PD1_Pos (1U) 3801 #define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */ 3802 #define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */ 3803 #define PWR_PDCRB_PD2_Pos (2U) 3804 #define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */ 3805 #define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */ 3806 #define PWR_PDCRB_PD3_Pos (3U) 3807 #define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */ 3808 #define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */ 3809 #define PWR_PDCRB_PD4_Pos (4U) 3810 #define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */ 3811 #define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */ 3812 #define PWR_PDCRB_PD5_Pos (5U) 3813 #define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */ 3814 #define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */ 3815 #define PWR_PDCRB_PD6_Pos (6U) 3816 #define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */ 3817 #define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */ 3818 #define PWR_PDCRB_PD7_Pos (7U) 3819 #define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */ 3820 #define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */ 3821 #define PWR_PDCRB_PD8_Pos (8U) 3822 #define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */ 3823 #define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */ 3824 #define PWR_PDCRB_PD9_Pos (9U) 3825 #define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */ 3826 #define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */ 3827 #define PWR_PDCRB_PD10_Pos (10U) 3828 #define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */ 3829 #define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */ 3830 #define PWR_PDCRB_PD11_Pos (11U) 3831 #define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */ 3832 #define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */ 3833 #define PWR_PDCRB_PD12_Pos (12U) 3834 #define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */ 3835 #define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */ 3836 #define PWR_PDCRB_PD13_Pos (13U) 3837 #define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */ 3838 #define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */ 3839 #define PWR_PDCRB_PD14_Pos (14U) 3840 #define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */ 3841 #define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */ 3842 #define PWR_PDCRB_PD15_Pos (15U) 3843 #define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */ 3844 #define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */ 3845 /******************** Bit definition for PWR_PUCRC register *****************/ 3846 #define PWR_PUCRC_PU6_Pos (6U) 3847 #define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */ 3848 #define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */ 3849 #define PWR_PUCRC_PU7_Pos (7U) 3850 #define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */ 3851 #define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */ 3852 #define PWR_PUCRC_PU13_Pos (13U) 3853 #define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */ 3854 #define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */ 3855 #define PWR_PUCRC_PU14_Pos (14U) 3856 #define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */ 3857 #define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */ 3858 #define PWR_PUCRC_PU15_Pos (15U) 3859 #define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */ 3860 #define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */ 3861 3862 /******************** Bit definition for PWR_PDCRC register *****************/ 3863 #define PWR_PDCRC_PD6_Pos (6U) 3864 #define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */ 3865 #define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */ 3866 #define PWR_PDCRC_PD7_Pos (7U) 3867 #define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */ 3868 #define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */ 3869 #define PWR_PDCRC_PD13_Pos (13U) 3870 #define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */ 3871 #define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */ 3872 #define PWR_PDCRC_PD14_Pos (14U) 3873 #define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */ 3874 #define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */ 3875 #define PWR_PDCRC_PD15_Pos (15U) 3876 #define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */ 3877 #define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */ 3878 3879 /******************** Bit definition for PWR_PUCRD register *****************/ 3880 #define PWR_PUCRD_PU0_Pos (0U) 3881 #define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */ 3882 #define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */ 3883 #define PWR_PUCRD_PU1_Pos (1U) 3884 #define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */ 3885 #define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */ 3886 #define PWR_PUCRD_PU2_Pos (2U) 3887 #define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */ 3888 #define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */ 3889 #define PWR_PUCRD_PU3_Pos (3U) 3890 #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ 3891 #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ 3892 3893 /******************** Bit definition for PWR_PDCRD register *****************/ 3894 #define PWR_PDCRD_PD0_Pos (0U) 3895 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ 3896 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */ 3897 #define PWR_PDCRD_PD1_Pos (1U) 3898 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */ 3899 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */ 3900 #define PWR_PDCRD_PD2_Pos (2U) 3901 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */ 3902 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */ 3903 #define PWR_PDCRD_PD3_Pos (3U) 3904 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */ 3905 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */ 3906 /******************** Bit definition for PWR_PUCRF register *****************/ 3907 #define PWR_PUCRF_PU0_Pos (0U) 3908 #define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */ 3909 #define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */ 3910 #define PWR_PUCRF_PU1_Pos (1U) 3911 #define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */ 3912 #define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */ 3913 #define PWR_PUCRF_PU2_Pos (2U) 3914 #define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */ 3915 #define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */ 3916 3917 /******************** Bit definition for PWR_PDCRF register *****************/ 3918 #define PWR_PDCRF_PD0_Pos (0U) 3919 #define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */ 3920 #define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */ 3921 #define PWR_PDCRF_PD1_Pos (1U) 3922 #define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */ 3923 #define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */ 3924 #define PWR_PDCRF_PD2_Pos (2U) 3925 #define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */ 3926 #define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */ 3927 3928 /******************** Bits definition for PWR_BKP0R register ***************/ 3929 #define PWR_BKP0R_Pos (0U) 3930 #define PWR_BKP0R_Msk (0xFFFFFFFFUL << PWR_BKP0R_Pos) /*!< 0xFFFFFFFF */ 3931 #define PWR_BKP0R PWR_BKP0R_Msk 3932 3933 /******************** Bits definition for PWR_BKP1R register ***************/ 3934 #define PWR_BKP1R_Pos (0U) 3935 #define PWR_BKP1R_Msk (0xFFFFFFFFUL << PWR_BKP1R_Pos) /*!< 0xFFFFFFFF */ 3936 #define PWR_BKP1R PWR_BKP1R_Msk 3937 3938 /******************** Bits definition for PWR_BKP2R register ***************/ 3939 #define PWR_BKP2R_Pos (0U) 3940 #define PWR_BKP2R_Msk (0xFFFFFFFFUL << PWR_BKP2R_Pos) /*!< 0xFFFFFFFF */ 3941 #define PWR_BKP2R PWR_BKP2R_Msk 3942 3943 /******************** Bits definition for PWR_BKP3R register ***************/ 3944 #define PWR_BKP3R_Pos (0U) 3945 #define PWR_BKP3R_Msk (0xFFFFFFFFUL << PWR_BKP3R_Pos) /*!< 0xFFFFFFFF */ 3946 #define PWR_BKP3R PWR_BKP3R_Msk 3947 /******************************************************************************/ 3948 /* */ 3949 /* Reset and Clock Control */ 3950 /* */ 3951 /******************************************************************************/ 3952 3953 /******************** Bit definition for RCC_CR register *****************/ 3954 #define RCC_CR_SYSDIV_Pos (2U) 3955 #define RCC_CR_SYSDIV_Msk (0x7UL << RCC_CR_SYSDIV_Pos) /*!< 0x0000001C */ 3956 #define RCC_CR_SYSDIV RCC_CR_SYSDIV_Msk /*!< Clock division factor for system clock */ 3957 #define RCC_CR_SYSDIV_0 (0x1UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000004 */ 3958 #define RCC_CR_SYSDIV_1 (0x2UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000008 */ 3959 #define RCC_CR_SYSDIV_2 (0x4UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000010 */ 3960 #define RCC_CR_HSIKERDIV_Pos (5U) 3961 #define RCC_CR_HSIKERDIV_Msk (0x7UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x000000E0 */ 3962 #define RCC_CR_HSIKERDIV RCC_CR_HSIKERDIV_Msk /*!< HSI48 clock division factor for HSI kernel clocks inputs */ 3963 #define RCC_CR_HSIKERDIV_0 (0x1UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x00000020 */ 3964 #define RCC_CR_HSIKERDIV_1 (0x2UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x00000040 */ 3965 #define RCC_CR_HSIKERDIV_2 (0x4UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x00000080 */ 3966 #define RCC_CR_HSION_Pos (8U) 3967 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 3968 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3969 #define RCC_CR_HSIKERON_Pos (9U) 3970 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 3971 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ 3972 #define RCC_CR_HSIRDY_Pos (10U) 3973 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 3974 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3975 #define RCC_CR_HSIDIV_Pos (11U) 3976 #define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */ 3977 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */ 3978 #define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */ 3979 #define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */ 3980 #define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */ 3981 #define RCC_CR_HSEON_Pos (16U) 3982 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3983 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3984 #define RCC_CR_HSERDY_Pos (17U) 3985 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3986 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */ 3987 #define RCC_CR_HSEBYP_Pos (18U) 3988 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3989 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3990 #define RCC_CR_CSSON_Pos (19U) 3991 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 3992 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 3993 3994 /******************** Bit definition for RCC_ICSCR register ***************/ 3995 /*!< HSICAL configuration */ 3996 #define RCC_ICSCR_HSICAL_Pos (0U) 3997 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 3998 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 3999 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */ 4000 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */ 4001 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */ 4002 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */ 4003 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */ 4004 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */ 4005 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */ 4006 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */ 4007 4008 /*!< HSITRIM configuration */ 4009 #define RCC_ICSCR_HSITRIM_Pos (8U) 4010 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */ 4011 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */ 4012 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */ 4013 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */ 4014 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */ 4015 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */ 4016 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */ 4017 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */ 4018 #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */ 4019 4020 /******************** Bit definition for RCC_CFGR register ***************/ 4021 /*!< SW configuration */ 4022 #define RCC_CFGR_SW_Pos (0U) 4023 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ 4024 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */ 4025 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4026 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4027 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ 4028 4029 /*!< SWS configuration */ 4030 #define RCC_CFGR_SWS_Pos (3U) 4031 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ 4032 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */ 4033 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4034 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ 4035 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ 4036 4037 #define RCC_CFGR_SWS_HSI (0UL) /*!< HSI used as system clock */ 4038 #define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ 4039 #define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ 4040 #define RCC_CFGR_SWS_LSE (0x00000020UL) /*!< LSE used as system clock */ 4041 4042 /*!< HPRE configuration */ 4043 #define RCC_CFGR_HPRE_Pos (8U) 4044 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ 4045 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4046 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */ 4047 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */ 4048 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */ 4049 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */ 4050 4051 /*!< PPRE configuration */ 4052 #define RCC_CFGR_PPRE_Pos (12U) 4053 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */ 4054 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */ 4055 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */ 4056 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */ 4057 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */ 4058 4059 /*!< MCO2SEL configuration */ 4060 #define RCC_CFGR_MCO2SEL_Pos (16U) 4061 #define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00070000 */ 4062 #define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (Clock output selection) */ 4063 #define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00010000 */ 4064 #define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00020000 */ 4065 #define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00040000 */ 4066 4067 /*!< MCO2 Prescaler configuration */ 4068 #define RCC_CFGR_MCO2PRE_Pos (20U) 4069 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00700000 */ 4070 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO prescaler [2:0] */ 4071 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00100000 */ 4072 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00200000 */ 4073 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00400000 */ 4074 4075 /*!< MCOSEL configuration */ 4076 #define RCC_CFGR_MCOSEL_Pos (24U) 4077 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4078 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */ 4079 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4080 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4081 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4082 4083 /*!< MCO Prescaler configuration */ 4084 #define RCC_CFGR_MCOPRE_Pos (28U) 4085 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4086 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */ 4087 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4088 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4089 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4090 4091 /******************** Bit definition for RCC_CIER register ******************/ 4092 #define RCC_CIER_LSIRDYIE_Pos (0U) 4093 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 4094 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk 4095 #define RCC_CIER_LSERDYIE_Pos (1U) 4096 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 4097 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 4098 #define RCC_CIER_HSIRDYIE_Pos (3U) 4099 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 4100 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 4101 #define RCC_CIER_HSERDYIE_Pos (4U) 4102 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 4103 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 4104 4105 /******************** Bit definition for RCC_CIFR register ******************/ 4106 #define RCC_CIFR_LSIRDYF_Pos (0U) 4107 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 4108 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk 4109 #define RCC_CIFR_LSERDYF_Pos (1U) 4110 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 4111 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 4112 #define RCC_CIFR_HSIRDYF_Pos (3U) 4113 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 4114 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 4115 #define RCC_CIFR_HSERDYF_Pos (4U) 4116 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 4117 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 4118 #define RCC_CIFR_CSSF_Pos (8U) 4119 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 4120 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 4121 #define RCC_CIFR_LSECSSF_Pos (9U) 4122 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 4123 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 4124 4125 /******************** Bit definition for RCC_CICR register ******************/ 4126 #define RCC_CICR_LSIRDYC_Pos (0U) 4127 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 4128 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk 4129 #define RCC_CICR_LSERDYC_Pos (1U) 4130 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 4131 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 4132 #define RCC_CICR_HSIRDYC_Pos (3U) 4133 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 4134 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 4135 #define RCC_CICR_HSERDYC_Pos (4U) 4136 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 4137 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 4138 #define RCC_CICR_CSSC_Pos (8U) 4139 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 4140 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 4141 #define RCC_CICR_LSECSSC_Pos (9U) 4142 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 4143 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 4144 4145 /******************** Bit definition for RCC_IOPRSTR register ****************/ 4146 #define RCC_IOPRSTR_GPIOARST_Pos (0U) 4147 #define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4148 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk 4149 #define RCC_IOPRSTR_GPIOBRST_Pos (1U) 4150 #define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4151 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk 4152 #define RCC_IOPRSTR_GPIOCRST_Pos (2U) 4153 #define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4154 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk 4155 #define RCC_IOPRSTR_GPIODRST_Pos (3U) 4156 #define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4157 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk 4158 #define RCC_IOPRSTR_GPIOFRST_Pos (5U) 4159 #define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */ 4160 #define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk 4161 4162 /******************** Bit definition for RCC_AHBRSTR register ***************/ 4163 #define RCC_AHBRSTR_DMA1RST_Pos (0U) 4164 #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */ 4165 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk 4166 #define RCC_AHBRSTR_FLASHRST_Pos (8U) 4167 #define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */ 4168 #define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk 4169 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4170 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4171 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk 4172 4173 /******************** Bit definition for RCC_APBRSTR1 register **************/ 4174 #define RCC_APBRSTR1_TIM3RST_Pos (1U) 4175 #define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */ 4176 #define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk 4177 #define RCC_APBRSTR1_USART2RST_Pos (17U) 4178 #define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00010000 */ 4179 #define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk 4180 #define RCC_APBRSTR1_I2C1RST_Pos (21U) 4181 #define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */ 4182 #define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk 4183 #define RCC_APBRSTR1_DBGRST_Pos (27U) 4184 #define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */ 4185 #define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk 4186 #define RCC_APBRSTR1_PWRRST_Pos (28U) 4187 #define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */ 4188 #define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk 4189 4190 /******************** Bit definition for RCC_APBRSTR2 register **************/ 4191 #define RCC_APBRSTR2_SYSCFGRST_Pos (0U) 4192 #define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */ 4193 #define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk 4194 #define RCC_APBRSTR2_TIM1RST_Pos (11U) 4195 #define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */ 4196 #define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk 4197 #define RCC_APBRSTR2_SPI1RST_Pos (12U) 4198 #define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */ 4199 #define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk 4200 #define RCC_APBRSTR2_USART1RST_Pos (14U) 4201 #define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */ 4202 #define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk 4203 #define RCC_APBRSTR2_TIM14RST_Pos (15U) 4204 #define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */ 4205 #define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk 4206 #define RCC_APBRSTR2_TIM16RST_Pos (17U) 4207 #define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */ 4208 #define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk 4209 #define RCC_APBRSTR2_TIM17RST_Pos (18U) 4210 #define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */ 4211 #define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk 4212 #define RCC_APBRSTR2_ADCRST_Pos (20U) 4213 #define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */ 4214 #define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk 4215 4216 /******************** Bit definition for RCC_IOPENR register ****************/ 4217 #define RCC_IOPENR_GPIOAEN_Pos (0U) 4218 #define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4219 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk 4220 #define RCC_IOPENR_GPIOBEN_Pos (1U) 4221 #define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4222 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk 4223 #define RCC_IOPENR_GPIOCEN_Pos (2U) 4224 #define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4225 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk 4226 #define RCC_IOPENR_GPIODEN_Pos (3U) 4227 #define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */ 4228 #define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk 4229 #define RCC_IOPENR_GPIOFEN_Pos (5U) 4230 #define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */ 4231 #define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk 4232 4233 /******************** Bit definition for RCC_AHBENR register ****************/ 4234 #define RCC_AHBENR_DMA1EN_Pos (0U) 4235 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 4236 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk 4237 #define RCC_AHBENR_FLASHEN_Pos (8U) 4238 #define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */ 4239 #define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk 4240 #define RCC_AHBENR_CRCEN_Pos (12U) 4241 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4242 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk 4243 4244 /******************** Bit definition for RCC_APBENR1 register ***************/ 4245 #define RCC_APBENR1_TIM3EN_Pos (1U) 4246 #define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */ 4247 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk 4248 #define RCC_APBENR1_RTCAPBEN_Pos (10U) 4249 #define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ 4250 #define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk 4251 #define RCC_APBENR1_WWDGEN_Pos (11U) 4252 #define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */ 4253 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk 4254 #define RCC_APBENR1_USART2EN_Pos (17U) 4255 #define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00010000 */ 4256 #define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk 4257 #define RCC_APBENR1_I2C1EN_Pos (21U) 4258 #define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */ 4259 #define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk 4260 #define RCC_APBENR1_DBGEN_Pos (27U) 4261 #define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */ 4262 #define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk 4263 #define RCC_APBENR1_PWREN_Pos (28U) 4264 #define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */ 4265 #define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk 4266 4267 /******************** Bit definition for RCC_APBENR2 register **************/ 4268 #define RCC_APBENR2_SYSCFGEN_Pos (0U) 4269 #define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ 4270 #define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk 4271 #define RCC_APBENR2_TIM1EN_Pos (11U) 4272 #define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */ 4273 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk 4274 #define RCC_APBENR2_SPI1EN_Pos (12U) 4275 #define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */ 4276 #define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk 4277 #define RCC_APBENR2_USART1EN_Pos (14U) 4278 #define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */ 4279 #define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk 4280 #define RCC_APBENR2_TIM14EN_Pos (15U) 4281 #define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */ 4282 #define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk 4283 #define RCC_APBENR2_TIM16EN_Pos (17U) 4284 #define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */ 4285 #define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk 4286 #define RCC_APBENR2_TIM17EN_Pos (18U) 4287 #define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */ 4288 #define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk 4289 #define RCC_APBENR2_ADCEN_Pos (20U) 4290 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */ 4291 #define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk 4292 4293 /******************** Bit definition for RCC_IOPSMENR register *************/ 4294 #define RCC_IOPSMENR_GPIOASMEN_Pos (0U) 4295 #define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ 4296 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk 4297 #define RCC_IOPSMENR_GPIOBSMEN_Pos (1U) 4298 #define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ 4299 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk 4300 #define RCC_IOPSMENR_GPIOCSMEN_Pos (2U) 4301 #define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ 4302 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk 4303 #define RCC_IOPSMENR_GPIODSMEN_Pos (3U) 4304 #define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */ 4305 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk 4306 #define RCC_IOPSMENR_GPIOFSMEN_Pos (5U) 4307 #define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */ 4308 #define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk 4309 4310 /******************** Bit definition for RCC_AHBSMENR register *************/ 4311 #define RCC_AHBSMENR_DMA1SMEN_Pos (0U) 4312 #define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ 4313 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk 4314 #define RCC_AHBSMENR_FLASHSMEN_Pos (8U) 4315 #define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ 4316 #define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk 4317 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U) 4318 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ 4319 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk 4320 #define RCC_AHBSMENR_CRCSMEN_Pos (12U) 4321 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 4322 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk 4323 4324 /******************** Bit definition for RCC_APBSMENR1 register *************/ 4325 #define RCC_APBSMENR1_TIM3SMEN_Pos (1U) 4326 #define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ 4327 #define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk 4328 #define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U) 4329 #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ 4330 #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk 4331 #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) 4332 #define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ 4333 #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk 4334 #define RCC_APBSMENR1_USART2SMEN_Pos (17U) 4335 #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00010000 */ 4336 #define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk 4337 #define RCC_APBSMENR1_I2C1SMEN_Pos (21U) 4338 #define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ 4339 #define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk 4340 #define RCC_APBSMENR1_DBGSMEN_Pos (27U) 4341 #define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */ 4342 #define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk 4343 #define RCC_APBSMENR1_PWRSMEN_Pos (28U) 4344 #define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */ 4345 #define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk 4346 4347 /******************** Bit definition for RCC_APBSMENR2 register *************/ 4348 #define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U) 4349 #define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 4350 #define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk 4351 #define RCC_APBSMENR2_TIM1SMEN_Pos (11U) 4352 #define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */ 4353 #define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk 4354 #define RCC_APBSMENR2_SPI1SMEN_Pos (12U) 4355 #define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */ 4356 #define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk 4357 #define RCC_APBSMENR2_USART1SMEN_Pos (14U) 4358 #define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */ 4359 #define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk 4360 #define RCC_APBSMENR2_TIM14SMEN_Pos (15U) 4361 #define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */ 4362 #define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk 4363 #define RCC_APBSMENR2_TIM16SMEN_Pos (17U) 4364 #define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */ 4365 #define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk 4366 #define RCC_APBSMENR2_TIM17SMEN_Pos (18U) 4367 #define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */ 4368 #define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk 4369 #define RCC_APBSMENR2_ADCSMEN_Pos (20U) 4370 #define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */ 4371 #define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk 4372 4373 /******************** Bit definition for RCC_CCIPR register ******************/ 4374 #define RCC_CCIPR_USART1SEL_Pos (0U) 4375 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 4376 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 4377 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 4378 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 4379 #define RCC_CCIPR_I2C1SEL_Pos (12U) 4380 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 4381 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 4382 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 4383 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 4384 #define RCC_CCIPR_I2S1SEL_Pos (14U) 4385 #define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */ 4386 #define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk 4387 #define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */ 4388 #define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */ 4389 #define RCC_CCIPR_ADCSEL_Pos (30U) 4390 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */ 4391 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk 4392 #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */ 4393 #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */ 4394 4395 /******************** Bit definition for RCC_CSR1 register ******************/ 4396 #define RCC_CSR1_LSEON_Pos (0U) 4397 #define RCC_CSR1_LSEON_Msk (0x1UL << RCC_CSR1_LSEON_Pos) /*!< 0x00000001 */ 4398 #define RCC_CSR1_LSEON RCC_CSR1_LSEON_Msk 4399 #define RCC_CSR1_LSERDY_Pos (1U) 4400 #define RCC_CSR1_LSERDY_Msk (0x1UL << RCC_CSR1_LSERDY_Pos) /*!< 0x00000002 */ 4401 #define RCC_CSR1_LSERDY RCC_CSR1_LSERDY_Msk 4402 #define RCC_CSR1_LSEBYP_Pos (2U) 4403 #define RCC_CSR1_LSEBYP_Msk (0x1UL << RCC_CSR1_LSEBYP_Pos) /*!< 0x00000004 */ 4404 #define RCC_CSR1_LSEBYP RCC_CSR1_LSEBYP_Msk 4405 #define RCC_CSR1_LSEDRV_Pos (3U) 4406 #define RCC_CSR1_LSEDRV_Msk (0x3UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000018 */ 4407 #define RCC_CSR1_LSEDRV RCC_CSR1_LSEDRV_Msk 4408 #define RCC_CSR1_LSEDRV_0 (0x1UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000008 */ 4409 #define RCC_CSR1_LSEDRV_1 (0x2UL << RCC_CSR1_LSEDRV_Pos) /*!< 0x00000010 */ 4410 #define RCC_CSR1_LSECSSON_Pos (5U) 4411 #define RCC_CSR1_LSECSSON_Msk (0x1UL << RCC_CSR1_LSECSSON_Pos) /*!< 0x00000020 */ 4412 #define RCC_CSR1_LSECSSON RCC_CSR1_LSECSSON_Msk 4413 #define RCC_CSR1_LSECSSD_Pos (6U) 4414 #define RCC_CSR1_LSECSSD_Msk (0x1UL << RCC_CSR1_LSECSSD_Pos) /*!< 0x00000040 */ 4415 #define RCC_CSR1_LSECSSD RCC_CSR1_LSECSSD_Msk 4416 #define RCC_CSR1_RTCSEL_Pos (8U) 4417 #define RCC_CSR1_RTCSEL_Msk (0x3UL << RCC_CSR1_RTCSEL_Pos) /*!< 0x00000300 */ 4418 #define RCC_CSR1_RTCSEL RCC_CSR1_RTCSEL_Msk 4419 #define RCC_CSR1_RTCSEL_0 (0x1UL << RCC_CSR1_RTCSEL_Pos) /*!< 0x00000100 */ 4420 #define RCC_CSR1_RTCSEL_1 (0x2UL << RCC_CSR1_RTCSEL_Pos) /*!< 0x00000200 */ 4421 #define RCC_CSR1_RTCEN_Pos (15U) 4422 #define RCC_CSR1_RTCEN_Msk (0x1UL << RCC_CSR1_RTCEN_Pos) /*!< 0x00008000 */ 4423 #define RCC_CSR1_RTCEN RCC_CSR1_RTCEN_Msk 4424 #define RCC_CSR1_RTCRST_Pos (16U) 4425 #define RCC_CSR1_RTCRST_Msk (0x1UL << RCC_CSR1_RTCRST_Pos) /*!< 0x00010000 */ 4426 #define RCC_CSR1_RTCRST RCC_CSR1_RTCRST_Msk 4427 #define RCC_CSR1_LSCOEN_Pos (24U) 4428 #define RCC_CSR1_LSCOEN_Msk (0x1UL << RCC_CSR1_LSCOEN_Pos) /*!< 0x01000000 */ 4429 #define RCC_CSR1_LSCOEN RCC_CSR1_LSCOEN_Msk 4430 #define RCC_CSR1_LSCOSEL_Pos (25U) 4431 #define RCC_CSR1_LSCOSEL_Msk (0x1UL << RCC_CSR1_LSCOSEL_Pos) /*!< 0x02000000 */ 4432 #define RCC_CSR1_LSCOSEL RCC_CSR1_LSCOSEL_Msk 4433 4434 /******************** Bit definition for RCC_CSR2 register *******************/ 4435 #define RCC_CSR2_LSION_Pos (0U) 4436 #define RCC_CSR2_LSION_Msk (0x1UL << RCC_CSR2_LSION_Pos) /*!< 0x00000001 */ 4437 #define RCC_CSR2_LSION RCC_CSR2_LSION_Msk 4438 #define RCC_CSR2_LSIRDY_Pos (1U) 4439 #define RCC_CSR2_LSIRDY_Msk (0x1UL << RCC_CSR2_LSIRDY_Pos) /*!< 0x00000002 */ 4440 #define RCC_CSR2_LSIRDY RCC_CSR2_LSIRDY_Msk 4441 #define RCC_CSR2_RMVF_Pos (23U) 4442 #define RCC_CSR2_RMVF_Msk (0x1UL << RCC_CSR2_RMVF_Pos) /*!< 0x00800000 */ 4443 #define RCC_CSR2_RMVF RCC_CSR2_RMVF_Msk 4444 #define RCC_CSR2_OBLRSTF_Pos (25U) 4445 #define RCC_CSR2_OBLRSTF_Msk (0x1UL << RCC_CSR2_OBLRSTF_Pos) /*!< 0x02000000 */ 4446 #define RCC_CSR2_OBLRSTF RCC_CSR2_OBLRSTF_Msk 4447 #define RCC_CSR2_PINRSTF_Pos (26U) 4448 #define RCC_CSR2_PINRSTF_Msk (0x1UL << RCC_CSR2_PINRSTF_Pos) /*!< 0x04000000 */ 4449 #define RCC_CSR2_PINRSTF RCC_CSR2_PINRSTF_Msk 4450 #define RCC_CSR2_PWRRSTF_Pos (27U) 4451 #define RCC_CSR2_PWRRSTF_Msk (0x1UL << RCC_CSR2_PWRRSTF_Pos) /*!< 0x08000000 */ 4452 #define RCC_CSR2_PWRRSTF RCC_CSR2_PWRRSTF_Msk 4453 #define RCC_CSR2_SFTRSTF_Pos (28U) 4454 #define RCC_CSR2_SFTRSTF_Msk (0x1UL << RCC_CSR2_SFTRSTF_Pos) /*!< 0x10000000 */ 4455 #define RCC_CSR2_SFTRSTF RCC_CSR2_SFTRSTF_Msk 4456 #define RCC_CSR2_IWDGRSTF_Pos (29U) 4457 #define RCC_CSR2_IWDGRSTF_Msk (0x1UL << RCC_CSR2_IWDGRSTF_Pos) /*!< 0x20000000 */ 4458 #define RCC_CSR2_IWDGRSTF RCC_CSR2_IWDGRSTF_Msk 4459 #define RCC_CSR2_WWDGRSTF_Pos (30U) 4460 #define RCC_CSR2_WWDGRSTF_Msk (0x1UL << RCC_CSR2_WWDGRSTF_Pos) /*!< 0x40000000 */ 4461 #define RCC_CSR2_WWDGRSTF RCC_CSR2_WWDGRSTF_Msk 4462 #define RCC_CSR2_LPWRRSTF_Pos (31U) 4463 #define RCC_CSR2_LPWRRSTF_Msk (0x1UL << RCC_CSR2_LPWRRSTF_Pos) /*!< 0x80000000 */ 4464 #define RCC_CSR2_LPWRRSTF RCC_CSR2_LPWRRSTF_Msk 4465 4466 /******************************************************************************/ 4467 /* */ 4468 /* Real-Time Clock (RTC) */ 4469 /* */ 4470 /******************************************************************************/ 4471 /******************** Bits definition for RTC_TR register *******************/ 4472 #define RTC_TR_PM_Pos (22U) 4473 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4474 #define RTC_TR_PM RTC_TR_PM_Msk 4475 #define RTC_TR_HT_Pos (20U) 4476 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4477 #define RTC_TR_HT RTC_TR_HT_Msk 4478 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4479 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4480 #define RTC_TR_HU_Pos (16U) 4481 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4482 #define RTC_TR_HU RTC_TR_HU_Msk 4483 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4484 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4485 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4486 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4487 #define RTC_TR_MNT_Pos (12U) 4488 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4489 #define RTC_TR_MNT RTC_TR_MNT_Msk 4490 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4491 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4492 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4493 #define RTC_TR_MNU_Pos (8U) 4494 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 4495 #define RTC_TR_MNU RTC_TR_MNU_Msk 4496 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 4497 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 4498 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 4499 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 4500 #define RTC_TR_ST_Pos (4U) 4501 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 4502 #define RTC_TR_ST RTC_TR_ST_Msk 4503 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 4504 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 4505 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 4506 #define RTC_TR_SU_Pos (0U) 4507 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 4508 #define RTC_TR_SU RTC_TR_SU_Msk 4509 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 4510 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 4511 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 4512 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 4513 4514 /******************** Bits definition for RTC_DR register *******************/ 4515 #define RTC_DR_YT_Pos (20U) 4516 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 4517 #define RTC_DR_YT RTC_DR_YT_Msk 4518 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 4519 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 4520 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 4521 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 4522 #define RTC_DR_YU_Pos (16U) 4523 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 4524 #define RTC_DR_YU RTC_DR_YU_Msk 4525 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 4526 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 4527 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 4528 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 4529 #define RTC_DR_WDU_Pos (13U) 4530 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 4531 #define RTC_DR_WDU RTC_DR_WDU_Msk 4532 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 4533 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 4534 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 4535 #define RTC_DR_MT_Pos (12U) 4536 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 4537 #define RTC_DR_MT RTC_DR_MT_Msk 4538 #define RTC_DR_MU_Pos (8U) 4539 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 4540 #define RTC_DR_MU RTC_DR_MU_Msk 4541 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4542 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4543 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4544 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4545 #define RTC_DR_DT_Pos (4U) 4546 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4547 #define RTC_DR_DT RTC_DR_DT_Msk 4548 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4549 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4550 #define RTC_DR_DU_Pos (0U) 4551 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4552 #define RTC_DR_DU RTC_DR_DU_Msk 4553 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4554 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4555 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4556 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4557 4558 /******************** Bits definition for RTC_SSR register ******************/ 4559 #define RTC_SSR_SS_Pos (0U) 4560 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4561 #define RTC_SSR_SS RTC_SSR_SS_Msk 4562 4563 /******************** Bits definition for RTC_ICSR register ******************/ 4564 #define RTC_ICSR_RECALPF_Pos (16U) 4565 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ 4566 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk 4567 #define RTC_ICSR_INIT_Pos (7U) 4568 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ 4569 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk 4570 #define RTC_ICSR_INITF_Pos (6U) 4571 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ 4572 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk 4573 #define RTC_ICSR_RSF_Pos (5U) 4574 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ 4575 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk 4576 #define RTC_ICSR_INITS_Pos (4U) 4577 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ 4578 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk 4579 #define RTC_ICSR_SHPF_Pos (3U) 4580 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ 4581 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk 4582 #define RTC_ICSR_ALRAWF_Pos (0U) 4583 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ 4584 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk 4585 4586 /******************** Bits definition for RTC_PRER register *****************/ 4587 #define RTC_PRER_PREDIV_A_Pos (16U) 4588 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4589 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 4590 #define RTC_PRER_PREDIV_S_Pos (0U) 4591 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4592 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 4593 /******************** Bits definition for RTC_CR register *******************/ 4594 #define RTC_CR_OUT2EN_Pos (31U) 4595 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ 4596 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ 4597 #define RTC_CR_TAMPALRM_TYPE_Pos (30U) 4598 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ 4599 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ 4600 #define RTC_CR_TAMPALRM_PU_Pos (29U) 4601 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ 4602 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ 4603 #define RTC_CR_COE_Pos (23U) 4604 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4605 #define RTC_CR_COE RTC_CR_COE_Msk 4606 #define RTC_CR_OSEL_Pos (21U) 4607 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4608 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 4609 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4610 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4611 #define RTC_CR_POL_Pos (20U) 4612 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4613 #define RTC_CR_POL RTC_CR_POL_Msk 4614 #define RTC_CR_COSEL_Pos (19U) 4615 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4616 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 4617 #define RTC_CR_BKP_Pos (18U) 4618 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4619 #define RTC_CR_BKP RTC_CR_BKP_Msk 4620 #define RTC_CR_SUB1H_Pos (17U) 4621 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4622 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 4623 #define RTC_CR_ADD1H_Pos (16U) 4624 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4625 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 4626 #define RTC_CR_TSIE_Pos (15U) 4627 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4628 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ 4629 #define RTC_CR_ALRAIE_Pos (12U) 4630 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4631 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 4632 #define RTC_CR_TSE_Pos (11U) 4633 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4634 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ 4635 #define RTC_CR_ALRAE_Pos (8U) 4636 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4637 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 4638 #define RTC_CR_FMT_Pos (6U) 4639 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4640 #define RTC_CR_FMT RTC_CR_FMT_Msk 4641 #define RTC_CR_BYPSHAD_Pos (5U) 4642 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4643 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 4644 #define RTC_CR_REFCKON_Pos (4U) 4645 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4646 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 4647 #define RTC_CR_TSEDGE_Pos (3U) 4648 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4649 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ 4650 4651 /******************** Bits definition for RTC_WPR register ******************/ 4652 #define RTC_WPR_KEY_Pos (0U) 4653 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4654 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 4655 4656 /******************** Bits definition for RTC_CALR register *****************/ 4657 #define RTC_CALR_CALP_Pos (15U) 4658 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4659 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 4660 #define RTC_CALR_CALW8_Pos (14U) 4661 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4662 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 4663 #define RTC_CALR_CALW16_Pos (13U) 4664 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4665 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 4666 #define RTC_CALR_CALM_Pos (0U) 4667 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4668 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 4669 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4670 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4671 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4672 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4673 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4674 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4675 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4676 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4677 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4678 4679 /******************** Bits definition for RTC_SHIFTR register ***************/ 4680 #define RTC_SHIFTR_ADD1S_Pos (31U) 4681 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4682 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 4683 #define RTC_SHIFTR_SUBFS_Pos (0U) 4684 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4685 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 4686 /******************** Bits definition for RTC_TSTR register *****************/ 4687 #define RTC_TSTR_PM_Pos (22U) 4688 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4689 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ 4690 #define RTC_TSTR_HT_Pos (20U) 4691 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4692 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 4693 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4694 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4695 #define RTC_TSTR_HU_Pos (16U) 4696 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4697 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 4698 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4699 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4700 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4701 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4702 #define RTC_TSTR_MNT_Pos (12U) 4703 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4704 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 4705 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4706 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4707 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4708 #define RTC_TSTR_MNU_Pos (8U) 4709 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4710 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 4711 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4712 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4713 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4714 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4715 #define RTC_TSTR_ST_Pos (4U) 4716 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4717 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 4718 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4719 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4720 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4721 #define RTC_TSTR_SU_Pos (0U) 4722 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4723 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 4724 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4725 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4726 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4727 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4728 4729 /******************** Bits definition for RTC_TSDR register *****************/ 4730 #define RTC_TSDR_WDU_Pos (13U) 4731 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4732 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ 4733 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4734 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4735 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4736 #define RTC_TSDR_MT_Pos (12U) 4737 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4738 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 4739 #define RTC_TSDR_MU_Pos (8U) 4740 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4741 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 4742 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4743 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4744 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4745 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4746 #define RTC_TSDR_DT_Pos (4U) 4747 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4748 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 4749 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4750 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4751 #define RTC_TSDR_DU_Pos (0U) 4752 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4753 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 4754 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4755 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4756 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4757 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4758 4759 /******************** Bits definition for RTC_TSSSR register ****************/ 4760 #define RTC_TSSSR_SS_Pos (0U) 4761 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4762 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ 4763 4764 /******************** Bits definition for RTC_ALRMAR register ***************/ 4765 #define RTC_ALRMAR_MSK4_Pos (31U) 4766 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4767 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 4768 #define RTC_ALRMAR_WDSEL_Pos (30U) 4769 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4770 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 4771 #define RTC_ALRMAR_DT_Pos (28U) 4772 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4773 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 4774 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4775 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4776 #define RTC_ALRMAR_DU_Pos (24U) 4777 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4778 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 4779 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4780 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4781 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4782 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4783 #define RTC_ALRMAR_MSK3_Pos (23U) 4784 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4785 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 4786 #define RTC_ALRMAR_PM_Pos (22U) 4787 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4788 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 4789 #define RTC_ALRMAR_HT_Pos (20U) 4790 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4791 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 4792 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4793 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4794 #define RTC_ALRMAR_HU_Pos (16U) 4795 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4796 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 4797 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4798 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4799 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4800 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4801 #define RTC_ALRMAR_MSK2_Pos (15U) 4802 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4803 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 4804 #define RTC_ALRMAR_MNT_Pos (12U) 4805 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4806 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 4807 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4808 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4809 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4810 #define RTC_ALRMAR_MNU_Pos (8U) 4811 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4812 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 4813 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4814 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4815 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4816 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4817 #define RTC_ALRMAR_MSK1_Pos (7U) 4818 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4819 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 4820 #define RTC_ALRMAR_ST_Pos (4U) 4821 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4822 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 4823 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4824 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4825 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4826 #define RTC_ALRMAR_SU_Pos (0U) 4827 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4828 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 4829 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4830 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4831 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4832 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4833 4834 /******************** Bits definition for RTC_ALRMASSR register *************/ 4835 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4836 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4837 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4838 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4839 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4840 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4841 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4842 #define RTC_ALRMASSR_SS_Pos (0U) 4843 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4844 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4845 4846 /******************** Bits definition for RTC_SR register *******************/ 4847 #define RTC_SR_TSOVF_Pos (4U) 4848 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ 4849 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ 4850 #define RTC_SR_TSF_Pos (3U) 4851 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ 4852 #define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ 4853 #define RTC_SR_ALRAF_Pos (0U) 4854 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ 4855 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk 4856 4857 /******************** Bits definition for RTC_MISR register *****************/ 4858 #define RTC_MISR_TSOVMF_Pos (4U) 4859 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ 4860 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ 4861 #define RTC_MISR_TSMF_Pos (3U) 4862 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ 4863 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ 4864 #define RTC_MISR_ALRAMF_Pos (0U) 4865 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ 4866 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk 4867 4868 /******************** Bits definition for RTC_SCR register ******************/ 4869 #define RTC_SCR_CTSOVF_Pos (4U) 4870 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ 4871 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ 4872 #define RTC_SCR_CTSF_Pos (3U) 4873 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ 4874 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ 4875 #define RTC_SCR_CALRAF_Pos (0U) 4876 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ 4877 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk 4878 4879 /******************************************************************************/ 4880 /* */ 4881 /* Serial Peripheral Interface (SPI) */ 4882 /* */ 4883 /******************************************************************************/ 4884 4885 #define SPI_I2S_SUPPORT /*!< I2S support */ 4886 4887 /******************* Bit definition for SPI_CR1 register ********************/ 4888 #define SPI_CR1_CPHA_Pos (0U) 4889 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4890 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 4891 #define SPI_CR1_CPOL_Pos (1U) 4892 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4893 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 4894 #define SPI_CR1_MSTR_Pos (2U) 4895 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4896 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 4897 4898 #define SPI_CR1_BR_Pos (3U) 4899 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4900 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 4901 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4902 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4903 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4904 4905 #define SPI_CR1_SPE_Pos (6U) 4906 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4907 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 4908 #define SPI_CR1_LSBFIRST_Pos (7U) 4909 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4910 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 4911 #define SPI_CR1_SSI_Pos (8U) 4912 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4913 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 4914 #define SPI_CR1_SSM_Pos (9U) 4915 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4916 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 4917 #define SPI_CR1_RXONLY_Pos (10U) 4918 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4919 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 4920 #define SPI_CR1_CRCL_Pos (11U) 4921 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 4922 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 4923 #define SPI_CR1_CRCNEXT_Pos (12U) 4924 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4925 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 4926 #define SPI_CR1_CRCEN_Pos (13U) 4927 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4928 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 4929 #define SPI_CR1_BIDIOE_Pos (14U) 4930 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4931 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 4932 #define SPI_CR1_BIDIMODE_Pos (15U) 4933 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4934 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 4935 4936 /******************* Bit definition for SPI_CR2 register ********************/ 4937 #define SPI_CR2_RXDMAEN_Pos (0U) 4938 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4939 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4940 #define SPI_CR2_TXDMAEN_Pos (1U) 4941 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4942 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4943 #define SPI_CR2_SSOE_Pos (2U) 4944 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4945 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4946 #define SPI_CR2_NSSP_Pos (3U) 4947 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 4948 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 4949 #define SPI_CR2_FRF_Pos (4U) 4950 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4951 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4952 #define SPI_CR2_ERRIE_Pos (5U) 4953 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4954 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4955 #define SPI_CR2_RXNEIE_Pos (6U) 4956 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4957 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4958 #define SPI_CR2_TXEIE_Pos (7U) 4959 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4960 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4961 #define SPI_CR2_DS_Pos (8U) 4962 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 4963 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 4964 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 4965 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 4966 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 4967 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 4968 #define SPI_CR2_FRXTH_Pos (12U) 4969 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 4970 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 4971 #define SPI_CR2_LDMARX_Pos (13U) 4972 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 4973 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 4974 #define SPI_CR2_LDMATX_Pos (14U) 4975 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 4976 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 4977 4978 /******************** Bit definition for SPI_SR register ********************/ 4979 #define SPI_SR_RXNE_Pos (0U) 4980 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4981 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4982 #define SPI_SR_TXE_Pos (1U) 4983 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4984 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4985 #define SPI_SR_CHSIDE_Pos (2U) 4986 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4987 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4988 #define SPI_SR_UDR_Pos (3U) 4989 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4990 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 4991 #define SPI_SR_CRCERR_Pos (4U) 4992 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4993 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4994 #define SPI_SR_MODF_Pos (5U) 4995 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4996 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4997 #define SPI_SR_OVR_Pos (6U) 4998 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4999 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5000 #define SPI_SR_BSY_Pos (7U) 5001 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5002 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5003 #define SPI_SR_FRE_Pos (8U) 5004 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5005 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 5006 #define SPI_SR_FRLVL_Pos (9U) 5007 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 5008 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 5009 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 5010 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 5011 #define SPI_SR_FTLVL_Pos (11U) 5012 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 5013 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 5014 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 5015 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 5016 5017 /******************** Bit definition for SPI_DR register ********************/ 5018 #define SPI_DR_DR_Pos (0U) 5019 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5020 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 5021 5022 /******************* Bit definition for SPI_CRCPR register ******************/ 5023 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5024 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5025 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 5026 5027 /****************** Bit definition for SPI_RXCRCR register ******************/ 5028 #define SPI_RXCRCR_RXCRC_Pos (0U) 5029 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5030 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 5031 5032 /****************** Bit definition for SPI_TXCRCR register ******************/ 5033 #define SPI_TXCRCR_TXCRC_Pos (0U) 5034 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5035 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 5036 5037 /****************** Bit definition for SPI_I2SCFGR register *****************/ 5038 #define SPI_I2SCFGR_CHLEN_Pos (0U) 5039 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 5040 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 5041 #define SPI_I2SCFGR_DATLEN_Pos (1U) 5042 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 5043 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 5044 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 5045 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 5046 #define SPI_I2SCFGR_CKPOL_Pos (3U) 5047 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 5048 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 5049 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 5050 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 5051 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 5052 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 5053 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 5054 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 5055 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 5056 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 5057 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 5058 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 5059 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 5060 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 5061 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 5062 #define SPI_I2SCFGR_I2SE_Pos (10U) 5063 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 5064 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 5065 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 5066 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 5067 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 5068 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 5069 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 5070 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 5071 5072 /****************** Bit definition for SPI_I2SPR register *******************/ 5073 #define SPI_I2SPR_I2SDIV_Pos (0U) 5074 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 5075 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 5076 #define SPI_I2SPR_ODD_Pos (8U) 5077 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 5078 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 5079 #define SPI_I2SPR_MCKOE_Pos (9U) 5080 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 5081 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 5082 5083 /******************************************************************************/ 5084 /* */ 5085 /* SYSCFG */ 5086 /* */ 5087 /******************************************************************************/ 5088 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 5089 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 5090 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 5091 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5092 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 5093 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 5094 #define SYSCFG_CFGR1_PA11_RMP_Pos (3U) 5095 #define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */ 5096 #define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */ 5097 #define SYSCFG_CFGR1_PA12_RMP_Pos (4U) 5098 #define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */ 5099 #define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */ 5100 #define SYSCFG_CFGR1_IR_POL_Pos (5U) 5101 #define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */ 5102 #define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */ 5103 #define SYSCFG_CFGR1_IR_MOD_Pos (6U) 5104 #define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */ 5105 #define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */ 5106 #define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */ 5107 #define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */ 5108 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 5109 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 5110 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 5111 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 5112 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 5113 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 5114 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 5115 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 5116 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 5117 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 5118 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 5119 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 5120 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 5121 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 5122 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ 5123 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U) 5124 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */ 5125 #define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */ 5126 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U) 5127 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */ 5128 #define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */ 5129 #define SYSCFG_CFGR1_I2C_PC14_FMP_Pos (24U) 5130 #define SYSCFG_CFGR1_I2C_PC14_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PC14_FMP_Pos) /*!< 0x01000000 */ 5131 #define SYSCFG_CFGR1_I2C_PC14_FMP SYSCFG_CFGR1_I2C_PC14_FMP_Msk /*!< Enable Fast Mode Plus on PC14 */ 5132 5133 /****************** Bit definition for SYSCFG_CFGR2 register ****************/ 5134 #define SYSCFG_CFGR2_CLL_Pos (0U) 5135 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 5136 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1/16/17 */ 5137 5138 /****************** Bit definition for SYSCFG_CFGR3 register ****************/ 5139 #define SYSCFG_CFGR3_PINMUX0_Pos (0U) 5140 #define SYSCFG_CFGR3_PINMUX0_Msk (0x3UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000003 */ 5141 #define SYSCFG_CFGR3_PINMUX0 SYSCFG_CFGR3_PINMUX0_Msk /*!< Pin GPIO multiplexer 0 */ 5142 #define SYSCFG_CFGR3_PINMUX0_0 (0x1UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000001 */ 5143 #define SYSCFG_CFGR3_PINMUX0_1 (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000002 */ 5144 #define SYSCFG_CFGR3_PINMUX1_Pos (2U) 5145 #define SYSCFG_CFGR3_PINMUX1_Msk (0x3UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x0000000C */ 5146 #define SYSCFG_CFGR3_PINMUX1 SYSCFG_CFGR3_PINMUX1_Msk /*!< Pin GPIO multiplexer 1 */ 5147 #define SYSCFG_CFGR3_PINMUX1_0 (0x1UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000004 */ 5148 #define SYSCFG_CFGR3_PINMUX1_1 (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000008 */ 5149 #define SYSCFG_CFGR3_PINMUX2_Pos (4U) 5150 #define SYSCFG_CFGR3_PINMUX2_Msk (0x3UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000030 */ 5151 #define SYSCFG_CFGR3_PINMUX2 SYSCFG_CFGR3_PINMUX2_Msk /*!< Pin GPIO multiplexer 2 */ 5152 #define SYSCFG_CFGR3_PINMUX2_0 (0x1UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000010 */ 5153 #define SYSCFG_CFGR3_PINMUX2_1 (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000020 */ 5154 #define SYSCFG_CFGR3_PINMUX3_Pos (6U) 5155 #define SYSCFG_CFGR3_PINMUX3_Msk (0x3UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x000000C0 */ 5156 #define SYSCFG_CFGR3_PINMUX3 SYSCFG_CFGR3_PINMUX3_Msk /*!< Pin GPIO multiplexer 3 */ 5157 #define SYSCFG_CFGR3_PINMUX3_0 (0x1UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000040 */ 5158 #define SYSCFG_CFGR3_PINMUX3_1 (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000080 */ 5159 #define SYSCFG_CFGR3_PINMUX4_Pos (8U) 5160 #define SYSCFG_CFGR3_PINMUX4_Msk (0x3UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000300 */ 5161 #define SYSCFG_CFGR3_PINMUX4 SYSCFG_CFGR3_PINMUX4_Msk /*!< Pin GPIO multiplexer 4 */ 5162 #define SYSCFG_CFGR3_PINMUX4_0 (0x1UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000100 */ 5163 #define SYSCFG_CFGR3_PINMUX4_1 (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000200 */ 5164 #define SYSCFG_CFGR3_PINMUX5_Pos (10U) 5165 #define SYSCFG_CFGR3_PINMUX5_Msk (0x3UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000C00 */ 5166 #define SYSCFG_CFGR3_PINMUX5 SYSCFG_CFGR3_PINMUX5_Msk /*!< Pin GPIO multiplexer 5 */ 5167 #define SYSCFG_CFGR3_PINMUX5_0 (0x1UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000400 */ 5168 #define SYSCFG_CFGR3_PINMUX5_1 (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000800 */ 5169 5170 /***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/ 5171 #define SYSCFG_ITLINE0_SR_WWDG_Pos (0U) 5172 #define SYSCFG_ITLINE0_SR_WWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_WWDG_Pos) /*!< 0x00000001 */ 5173 #define SYSCFG_ITLINE0_SR_WWDG SYSCFG_ITLINE0_SR_WWDG_Msk /*!< EWDG interrupt */ 5174 #define SYSCFG_ITLINE2_SR_RTC_Pos (1U) 5175 #define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ 5176 #define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC interrupt */ 5177 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) 5178 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ 5179 #define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ 5180 #define SYSCFG_ITLINE4_SR_RCC_Pos (0U) 5181 #define SYSCFG_ITLINE4_SR_RCC_Msk (0x1UL << SYSCFG_ITLINE4_SR_RCC_Pos) /*!< 0x00000001 */ 5182 #define SYSCFG_ITLINE4_SR_RCC SYSCFG_ITLINE4_SR_RCC_Msk /*!< RCC interrupt */ 5183 #define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) 5184 #define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ 5185 #define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ 5186 #define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) 5187 #define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ 5188 #define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ 5189 #define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) 5190 #define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ 5191 #define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ 5192 #define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) 5193 #define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ 5194 #define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ 5195 #define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) 5196 #define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ 5197 #define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ 5198 #define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) 5199 #define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ 5200 #define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ 5201 #define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) 5202 #define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ 5203 #define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ 5204 #define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) 5205 #define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ 5206 #define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ 5207 #define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) 5208 #define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ 5209 #define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ 5210 #define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) 5211 #define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ 5212 #define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ 5213 #define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) 5214 #define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ 5215 #define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ 5216 #define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) 5217 #define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ 5218 #define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ 5219 #define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) 5220 #define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ 5221 #define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ 5222 #define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) 5223 #define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ 5224 #define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ 5225 #define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) 5226 #define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ 5227 #define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ 5228 #define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) 5229 #define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ 5230 #define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ 5231 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) 5232 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ 5233 #define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ 5234 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) 5235 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ 5236 #define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ 5237 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) 5238 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ 5239 #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA1 Channel 3 Interrupt */ 5240 #define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) 5241 #define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ 5242 #define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ 5243 #define SYSCFG_ITLINE12_SR_ADC_Pos (0U) 5244 #define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ 5245 #define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ 5246 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) 5247 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ 5248 #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ 5249 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) 5250 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ 5251 #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ 5252 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) 5253 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ 5254 #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ 5255 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) 5256 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ 5257 #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ 5258 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) 5259 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ 5260 #define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ 5261 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) 5262 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ 5263 #define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ 5264 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) 5265 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ 5266 #define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ 5267 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) 5268 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ 5269 #define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ 5270 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) 5271 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ 5272 #define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ 5273 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) 5274 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ 5275 #define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt */ 5276 #define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) 5277 #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ 5278 #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ 5279 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) 5280 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ 5281 #define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */ 5282 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) 5283 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ 5284 #define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */ 5285 5286 /******************************************************************************/ 5287 /* */ 5288 /* TIM */ 5289 /* */ 5290 /******************************************************************************/ 5291 /******************* Bit definition for TIM_CR1 register ********************/ 5292 #define TIM_CR1_CEN_Pos (0U) 5293 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 5294 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 5295 #define TIM_CR1_UDIS_Pos (1U) 5296 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 5297 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 5298 #define TIM_CR1_URS_Pos (2U) 5299 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 5300 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 5301 #define TIM_CR1_OPM_Pos (3U) 5302 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 5303 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 5304 #define TIM_CR1_DIR_Pos (4U) 5305 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 5306 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 5307 5308 #define TIM_CR1_CMS_Pos (5U) 5309 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 5310 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 5311 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 5312 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 5313 5314 #define TIM_CR1_ARPE_Pos (7U) 5315 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 5316 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 5317 5318 #define TIM_CR1_CKD_Pos (8U) 5319 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 5320 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 5321 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 5322 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 5323 5324 #define TIM_CR1_UIFREMAP_Pos (11U) 5325 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 5326 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 5327 5328 /******************* Bit definition for TIM_CR2 register ********************/ 5329 #define TIM_CR2_CCPC_Pos (0U) 5330 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 5331 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 5332 #define TIM_CR2_CCUS_Pos (2U) 5333 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 5334 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 5335 #define TIM_CR2_CCDS_Pos (3U) 5336 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 5337 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 5338 5339 #define TIM_CR2_MMS_Pos (4U) 5340 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 5341 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5342 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 5343 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 5344 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 5345 5346 #define TIM_CR2_TI1S_Pos (7U) 5347 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 5348 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 5349 #define TIM_CR2_OIS1_Pos (8U) 5350 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 5351 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 5352 #define TIM_CR2_OIS1N_Pos (9U) 5353 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 5354 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 5355 #define TIM_CR2_OIS2_Pos (10U) 5356 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 5357 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 5358 #define TIM_CR2_OIS2N_Pos (11U) 5359 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 5360 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 5361 #define TIM_CR2_OIS3_Pos (12U) 5362 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 5363 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 5364 #define TIM_CR2_OIS3N_Pos (13U) 5365 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 5366 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 5367 #define TIM_CR2_OIS4_Pos (14U) 5368 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 5369 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 5370 #define TIM_CR2_OIS5_Pos (16U) 5371 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 5372 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 5373 #define TIM_CR2_OIS6_Pos (18U) 5374 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 5375 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 5376 5377 #define TIM_CR2_MMS2_Pos (20U) 5378 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 5379 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5380 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 5381 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 5382 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 5383 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 5384 5385 /******************* Bit definition for TIM_SMCR register *******************/ 5386 #define TIM_SMCR_SMS_Pos (0U) 5387 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 5388 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 5389 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 5390 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 5391 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 5392 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 5393 5394 #define TIM_SMCR_OCCS_Pos (3U) 5395 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 5396 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 5397 5398 #define TIM_SMCR_TS_Pos (4U) 5399 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ 5400 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 5401 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 5402 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 5403 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 5404 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ 5405 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ 5406 5407 #define TIM_SMCR_MSM_Pos (7U) 5408 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 5409 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 5410 5411 #define TIM_SMCR_ETF_Pos (8U) 5412 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 5413 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 5414 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 5415 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 5416 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 5417 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5418 5419 #define TIM_SMCR_ETPS_Pos (12U) 5420 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5421 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5422 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5423 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5424 5425 #define TIM_SMCR_ECE_Pos (14U) 5426 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5427 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5428 #define TIM_SMCR_ETP_Pos (15U) 5429 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5430 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5431 5432 /******************* Bit definition for TIM_DIER register *******************/ 5433 #define TIM_DIER_UIE_Pos (0U) 5434 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5435 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5436 #define TIM_DIER_CC1IE_Pos (1U) 5437 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5438 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5439 #define TIM_DIER_CC2IE_Pos (2U) 5440 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5441 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5442 #define TIM_DIER_CC3IE_Pos (3U) 5443 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5444 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5445 #define TIM_DIER_CC4IE_Pos (4U) 5446 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5447 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5448 #define TIM_DIER_COMIE_Pos (5U) 5449 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 5450 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 5451 #define TIM_DIER_TIE_Pos (6U) 5452 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5453 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5454 #define TIM_DIER_BIE_Pos (7U) 5455 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 5456 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 5457 #define TIM_DIER_UDE_Pos (8U) 5458 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5459 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5460 #define TIM_DIER_CC1DE_Pos (9U) 5461 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5462 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5463 #define TIM_DIER_CC2DE_Pos (10U) 5464 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5465 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5466 #define TIM_DIER_CC3DE_Pos (11U) 5467 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5468 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5469 #define TIM_DIER_CC4DE_Pos (12U) 5470 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5471 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5472 #define TIM_DIER_COMDE_Pos (13U) 5473 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 5474 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 5475 #define TIM_DIER_TDE_Pos (14U) 5476 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5477 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5478 5479 /******************** Bit definition for TIM_SR register ********************/ 5480 #define TIM_SR_UIF_Pos (0U) 5481 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5482 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5483 #define TIM_SR_CC1IF_Pos (1U) 5484 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5485 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5486 #define TIM_SR_CC2IF_Pos (2U) 5487 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5488 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5489 #define TIM_SR_CC3IF_Pos (3U) 5490 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5491 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5492 #define TIM_SR_CC4IF_Pos (4U) 5493 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5494 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5495 #define TIM_SR_COMIF_Pos (5U) 5496 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 5497 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 5498 #define TIM_SR_TIF_Pos (6U) 5499 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5500 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5501 #define TIM_SR_BIF_Pos (7U) 5502 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 5503 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 5504 #define TIM_SR_B2IF_Pos (8U) 5505 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 5506 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 5507 #define TIM_SR_CC1OF_Pos (9U) 5508 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5509 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5510 #define TIM_SR_CC2OF_Pos (10U) 5511 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5512 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5513 #define TIM_SR_CC3OF_Pos (11U) 5514 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5515 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5516 #define TIM_SR_CC4OF_Pos (12U) 5517 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5518 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5519 #define TIM_SR_SBIF_Pos (13U) 5520 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 5521 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 5522 #define TIM_SR_CC5IF_Pos (16U) 5523 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 5524 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 5525 #define TIM_SR_CC6IF_Pos (17U) 5526 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 5527 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 5528 5529 5530 /******************* Bit definition for TIM_EGR register ********************/ 5531 #define TIM_EGR_UG_Pos (0U) 5532 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5533 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5534 #define TIM_EGR_CC1G_Pos (1U) 5535 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5536 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5537 #define TIM_EGR_CC2G_Pos (2U) 5538 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5539 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5540 #define TIM_EGR_CC3G_Pos (3U) 5541 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5542 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5543 #define TIM_EGR_CC4G_Pos (4U) 5544 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5545 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5546 #define TIM_EGR_COMG_Pos (5U) 5547 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 5548 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 5549 #define TIM_EGR_TG_Pos (6U) 5550 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5551 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5552 #define TIM_EGR_BG_Pos (7U) 5553 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 5554 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 5555 #define TIM_EGR_B2G_Pos (8U) 5556 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 5557 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 5558 5559 5560 /****************** Bit definition for TIM_CCMR1 register *******************/ 5561 #define TIM_CCMR1_CC1S_Pos (0U) 5562 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5563 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5564 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5565 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5566 5567 #define TIM_CCMR1_OC1FE_Pos (2U) 5568 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5569 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5570 #define TIM_CCMR1_OC1PE_Pos (3U) 5571 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5572 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5573 5574 #define TIM_CCMR1_OC1M_Pos (4U) 5575 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 5576 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5577 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5578 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5579 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5580 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 5581 5582 #define TIM_CCMR1_OC1CE_Pos (7U) 5583 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5584 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 5585 5586 #define TIM_CCMR1_CC2S_Pos (8U) 5587 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5588 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5589 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5590 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5591 5592 #define TIM_CCMR1_OC2FE_Pos (10U) 5593 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5594 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5595 #define TIM_CCMR1_OC2PE_Pos (11U) 5596 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5597 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5598 5599 #define TIM_CCMR1_OC2M_Pos (12U) 5600 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 5601 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5602 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5603 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5604 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5605 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 5606 5607 #define TIM_CCMR1_OC2CE_Pos (15U) 5608 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5609 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5610 5611 /*----------------------------------------------------------------------------*/ 5612 #define TIM_CCMR1_IC1PSC_Pos (2U) 5613 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5614 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5615 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5616 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5617 5618 #define TIM_CCMR1_IC1F_Pos (4U) 5619 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5620 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5621 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5622 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5623 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5624 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5625 5626 #define TIM_CCMR1_IC2PSC_Pos (10U) 5627 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5628 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5629 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5630 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5631 5632 #define TIM_CCMR1_IC2F_Pos (12U) 5633 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5634 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5635 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5636 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5637 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5638 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5639 5640 /****************** Bit definition for TIM_CCMR2 register *******************/ 5641 #define TIM_CCMR2_CC3S_Pos (0U) 5642 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5643 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5644 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5645 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5646 5647 #define TIM_CCMR2_OC3FE_Pos (2U) 5648 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5649 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5650 #define TIM_CCMR2_OC3PE_Pos (3U) 5651 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5652 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5653 5654 #define TIM_CCMR2_OC3M_Pos (4U) 5655 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 5656 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5657 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5658 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5659 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5660 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 5661 5662 #define TIM_CCMR2_OC3CE_Pos (7U) 5663 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5664 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5665 5666 #define TIM_CCMR2_CC4S_Pos (8U) 5667 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5668 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5669 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5670 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5671 5672 #define TIM_CCMR2_OC4FE_Pos (10U) 5673 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5674 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5675 #define TIM_CCMR2_OC4PE_Pos (11U) 5676 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5677 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5678 5679 #define TIM_CCMR2_OC4M_Pos (12U) 5680 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 5681 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5682 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5683 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5684 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5685 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 5686 5687 #define TIM_CCMR2_OC4CE_Pos (15U) 5688 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5689 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5690 5691 /*----------------------------------------------------------------------------*/ 5692 #define TIM_CCMR2_IC3PSC_Pos (2U) 5693 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 5694 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5695 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 5696 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 5697 5698 #define TIM_CCMR2_IC3F_Pos (4U) 5699 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 5700 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5701 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 5702 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 5703 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 5704 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 5705 5706 #define TIM_CCMR2_IC4PSC_Pos (10U) 5707 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 5708 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5709 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 5710 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 5711 5712 #define TIM_CCMR2_IC4F_Pos (12U) 5713 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 5714 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5715 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 5716 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 5717 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 5718 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 5719 5720 /****************** Bit definition for TIM_CCMR3 register *******************/ 5721 #define TIM_CCMR3_OC5FE_Pos (2U) 5722 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 5723 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 5724 #define TIM_CCMR3_OC5PE_Pos (3U) 5725 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 5726 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 5727 5728 #define TIM_CCMR3_OC5M_Pos (4U) 5729 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 5730 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 5731 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 5732 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 5733 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 5734 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 5735 5736 #define TIM_CCMR3_OC5CE_Pos (7U) 5737 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 5738 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 5739 5740 #define TIM_CCMR3_OC6FE_Pos (10U) 5741 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 5742 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 5743 #define TIM_CCMR3_OC6PE_Pos (11U) 5744 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 5745 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 5746 5747 #define TIM_CCMR3_OC6M_Pos (12U) 5748 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 5749 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 5750 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 5751 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 5752 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 5753 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 5754 5755 #define TIM_CCMR3_OC6CE_Pos (15U) 5756 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 5757 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 5758 5759 /******************* Bit definition for TIM_CCER register *******************/ 5760 #define TIM_CCER_CC1E_Pos (0U) 5761 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 5762 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 5763 #define TIM_CCER_CC1P_Pos (1U) 5764 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 5765 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 5766 #define TIM_CCER_CC1NE_Pos (2U) 5767 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 5768 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 5769 #define TIM_CCER_CC1NP_Pos (3U) 5770 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 5771 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 5772 #define TIM_CCER_CC2E_Pos (4U) 5773 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 5774 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 5775 #define TIM_CCER_CC2P_Pos (5U) 5776 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 5777 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 5778 #define TIM_CCER_CC2NE_Pos (6U) 5779 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 5780 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 5781 #define TIM_CCER_CC2NP_Pos (7U) 5782 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 5783 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 5784 #define TIM_CCER_CC3E_Pos (8U) 5785 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 5786 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 5787 #define TIM_CCER_CC3P_Pos (9U) 5788 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 5789 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 5790 #define TIM_CCER_CC3NE_Pos (10U) 5791 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 5792 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 5793 #define TIM_CCER_CC3NP_Pos (11U) 5794 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 5795 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 5796 #define TIM_CCER_CC4E_Pos (12U) 5797 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 5798 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 5799 #define TIM_CCER_CC4P_Pos (13U) 5800 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 5801 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 5802 #define TIM_CCER_CC4NP_Pos (15U) 5803 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 5804 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 5805 #define TIM_CCER_CC5E_Pos (16U) 5806 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 5807 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 5808 #define TIM_CCER_CC5P_Pos (17U) 5809 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 5810 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 5811 #define TIM_CCER_CC6E_Pos (20U) 5812 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 5813 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 5814 #define TIM_CCER_CC6P_Pos (21U) 5815 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 5816 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 5817 5818 /******************* Bit definition for TIM_CNT register ********************/ 5819 #define TIM_CNT_CNT_Pos (0U) 5820 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 5821 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 5822 #define TIM_CNT_UIFCPY_Pos (31U) 5823 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 5824 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 5825 5826 /******************* Bit definition for TIM_PSC register ********************/ 5827 #define TIM_PSC_PSC_Pos (0U) 5828 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 5829 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 5830 5831 /******************* Bit definition for TIM_ARR register ********************/ 5832 #define TIM_ARR_ARR_Pos (0U) 5833 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 5834 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 5835 5836 /******************* Bit definition for TIM_RCR register ********************/ 5837 #define TIM_RCR_REP_Pos (0U) 5838 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 5839 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 5840 5841 /******************* Bit definition for TIM_CCR1 register *******************/ 5842 #define TIM_CCR1_CCR1_Pos (0U) 5843 #define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */ 5844 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5845 5846 /******************* Bit definition for TIM_CCR2 register *******************/ 5847 #define TIM_CCR2_CCR2_Pos (0U) 5848 #define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */ 5849 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5850 5851 /******************* Bit definition for TIM_CCR3 register *******************/ 5852 #define TIM_CCR3_CCR3_Pos (0U) 5853 #define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */ 5854 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5855 5856 /******************* Bit definition for TIM_CCR4 register *******************/ 5857 #define TIM_CCR4_CCR4_Pos (0U) 5858 #define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */ 5859 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5860 5861 /******************* Bit definition for TIM_CCR5 register *******************/ 5862 #define TIM_CCR5_CCR5_Pos (0U) 5863 #define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */ 5864 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 5865 #define TIM_CCR5_GC5C1_Pos (29U) 5866 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 5867 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 5868 #define TIM_CCR5_GC5C2_Pos (30U) 5869 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 5870 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 5871 #define TIM_CCR5_GC5C3_Pos (31U) 5872 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 5873 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 5874 5875 /******************* Bit definition for TIM_CCR6 register *******************/ 5876 #define TIM_CCR6_CCR6_Pos (0U) 5877 #define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */ 5878 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 5879 5880 /******************* Bit definition for TIM_BDTR register *******************/ 5881 #define TIM_BDTR_DTG_Pos (0U) 5882 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 5883 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 5884 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 5885 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 5886 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 5887 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 5888 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 5889 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 5890 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 5891 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 5892 5893 #define TIM_BDTR_LOCK_Pos (8U) 5894 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 5895 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 5896 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 5897 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 5898 5899 #define TIM_BDTR_OSSI_Pos (10U) 5900 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 5901 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 5902 #define TIM_BDTR_OSSR_Pos (11U) 5903 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 5904 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 5905 #define TIM_BDTR_BKE_Pos (12U) 5906 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 5907 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 5908 #define TIM_BDTR_BKP_Pos (13U) 5909 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 5910 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 5911 #define TIM_BDTR_AOE_Pos (14U) 5912 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 5913 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 5914 #define TIM_BDTR_MOE_Pos (15U) 5915 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 5916 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 5917 5918 #define TIM_BDTR_BKF_Pos (16U) 5919 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 5920 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 5921 #define TIM_BDTR_BK2F_Pos (20U) 5922 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 5923 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 5924 5925 #define TIM_BDTR_BK2E_Pos (24U) 5926 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 5927 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 5928 #define TIM_BDTR_BK2P_Pos (25U) 5929 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 5930 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 5931 5932 #define TIM_BDTR_BKDSRM_Pos (26U) 5933 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ 5934 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ 5935 #define TIM_BDTR_BK2DSRM_Pos (27U) 5936 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ 5937 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ 5938 5939 #define TIM_BDTR_BKBID_Pos (28U) 5940 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ 5941 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ 5942 #define TIM_BDTR_BK2BID_Pos (29U) 5943 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ 5944 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ 5945 5946 /******************* Bit definition for TIM_DCR register ********************/ 5947 #define TIM_DCR_DBA_Pos (0U) 5948 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5949 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5950 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5951 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5952 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5953 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5954 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5955 5956 #define TIM_DCR_DBL_Pos (8U) 5957 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5958 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5959 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5960 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5961 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5962 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5963 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5964 5965 /******************* Bit definition for TIM_DMAR register *******************/ 5966 #define TIM_DMAR_DMAB_Pos (0U) 5967 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5968 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5969 5970 /******************* Bit definition for TIM_AF1 register *******************/ 5971 #define TIM_AF1_BKINE_Pos (0U) 5972 #define TIM_AF1_BKINE_Msk (0x1UL << TIM_AF1_BKINE_Pos) /*!< 0x00000001 */ 5973 #define TIM_AF1_BKINE TIM_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 5974 #define TIM_AF1_BKCMP1E_Pos (1U) 5975 #define TIM_AF1_BKCMP1E_Msk (0x1UL << TIM_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 5976 #define TIM_AF1_BKCMP1E TIM_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 5977 #define TIM_AF1_BKCMP2E_Pos (2U) 5978 #define TIM_AF1_BKCMP2E_Msk (0x1UL << TIM_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 5979 #define TIM_AF1_BKCMP2E TIM_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 5980 #define TIM_AF1_BKINP_Pos (9U) 5981 #define TIM_AF1_BKINP_Msk (0x1UL << TIM_AF1_BKINP_Pos) /*!< 0x00000200 */ 5982 #define TIM_AF1_BKINP TIM_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 5983 #define TIM_AF1_BKCMP1P_Pos (10U) 5984 #define TIM_AF1_BKCMP1P_Msk (0x1UL << TIM_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 5985 #define TIM_AF1_BKCMP1P TIM_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 5986 #define TIM_AF1_BKCMP2P_Pos (11U) 5987 #define TIM_AF1_BKCMP2P_Msk (0x1UL << TIM_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 5988 #define TIM_AF1_BKCMP2P TIM_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 5989 5990 #define TIM_AF1_ETRSEL_Pos (14U) 5991 #define TIM_AF1_ETRSEL_Msk (0xFUL << TIM_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 5992 #define TIM_AF1_ETRSEL TIM_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM ETR source selection) */ 5993 #define TIM_AF1_ETRSEL_0 (0x1UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 5994 #define TIM_AF1_ETRSEL_1 (0x2UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 5995 #define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 5996 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 5997 5998 /******************* Bit definition for TIM_AF2 register *******************/ 5999 #define TIM_AF2_BK2INE_Pos (0U) 6000 #define TIM_AF2_BK2INE_Msk (0x1UL << TIM_AF2_BK2INE_Pos) /*!< 0x00000001 */ 6001 #define TIM_AF2_BK2INE TIM_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ 6002 #define TIM_AF2_BK2CMP1E_Pos (1U) 6003 #define TIM_AF2_BK2CMP1E_Msk (0x1UL << TIM_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */ 6004 #define TIM_AF2_BK2CMP1E TIM_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ 6005 #define TIM_AF2_BK2CMP2E_Pos (2U) 6006 #define TIM_AF2_BK2CMP2E_Msk (0x1UL << TIM_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */ 6007 #define TIM_AF2_BK2CMP2E TIM_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ 6008 #define TIM_AF2_BK2INP_Pos (9U) 6009 #define TIM_AF2_BK2INP_Msk (0x1UL << TIM_AF2_BK2INP_Pos) /*!< 0x00000200 */ 6010 #define TIM_AF2_BK2INP TIM_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ 6011 #define TIM_AF2_BK2CMP1P_Pos (10U) 6012 #define TIM_AF2_BK2CMP1P_Msk (0x1UL << TIM_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */ 6013 #define TIM_AF2_BK2CMP1P TIM_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ 6014 #define TIM_AF2_BK2CMP2P_Pos (11U) 6015 #define TIM_AF2_BK2CMP2P_Msk (0x1UL << TIM_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */ 6016 #define TIM_AF2_BK2CMP2P TIM_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ 6017 6018 /******************* Bit definition for TIM_TISEL register *********************/ 6019 #define TIM_TISEL_TI1SEL_Pos (0U) 6020 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ 6021 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/ 6022 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */ 6023 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */ 6024 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */ 6025 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */ 6026 6027 #define TIM_TISEL_TI2SEL_Pos (8U) 6028 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */ 6029 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/ 6030 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */ 6031 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */ 6032 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */ 6033 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */ 6034 6035 #define TIM_TISEL_TI3SEL_Pos (16U) 6036 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */ 6037 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/ 6038 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */ 6039 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */ 6040 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */ 6041 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */ 6042 6043 #define TIM_TISEL_TI4SEL_Pos (24U) 6044 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */ 6045 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/ 6046 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */ 6047 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */ 6048 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */ 6049 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */ 6050 6051 6052 /******************************************************************************/ 6053 /* */ 6054 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 6055 /* */ 6056 /******************************************************************************/ 6057 /****************** Bit definition for USART_CR1 register *******************/ 6058 #define USART_CR1_UE_Pos (0U) 6059 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 6060 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 6061 #define USART_CR1_UESM_Pos (1U) 6062 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 6063 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 6064 #define USART_CR1_RE_Pos (2U) 6065 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 6066 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 6067 #define USART_CR1_TE_Pos (3U) 6068 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 6069 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 6070 #define USART_CR1_IDLEIE_Pos (4U) 6071 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 6072 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 6073 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U) 6074 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */ 6075 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */ 6076 #define USART_CR1_TCIE_Pos (6U) 6077 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 6078 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 6079 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) 6080 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ 6081 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ 6082 #define USART_CR1_PEIE_Pos (8U) 6083 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 6084 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 6085 #define USART_CR1_PS_Pos (9U) 6086 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 6087 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 6088 #define USART_CR1_PCE_Pos (10U) 6089 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 6090 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 6091 #define USART_CR1_WAKE_Pos (11U) 6092 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 6093 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 6094 #define USART_CR1_M_Pos (12U) 6095 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 6096 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 6097 #define USART_CR1_M0_Pos (12U) 6098 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 6099 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 6100 #define USART_CR1_MME_Pos (13U) 6101 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 6102 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 6103 #define USART_CR1_CMIE_Pos (14U) 6104 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 6105 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 6106 #define USART_CR1_OVER8_Pos (15U) 6107 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 6108 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 6109 #define USART_CR1_DEDT_Pos (16U) 6110 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 6111 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 6112 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 6113 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 6114 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 6115 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 6116 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 6117 #define USART_CR1_DEAT_Pos (21U) 6118 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 6119 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 6120 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 6121 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 6122 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 6123 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 6124 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 6125 #define USART_CR1_RTOIE_Pos (26U) 6126 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 6127 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 6128 #define USART_CR1_EOBIE_Pos (27U) 6129 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 6130 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 6131 #define USART_CR1_M1_Pos (28U) 6132 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 6133 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 6134 #define USART_CR1_FIFOEN_Pos (29U) 6135 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ 6136 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ 6137 #define USART_CR1_TXFEIE_Pos (30U) 6138 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ 6139 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ 6140 #define USART_CR1_RXFFIE_Pos (31U) 6141 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ 6142 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ 6143 6144 /****************** Bit definition for USART_CR2 register *******************/ 6145 #define USART_CR2_SLVEN_Pos (0U) 6146 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ 6147 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ 6148 #define USART_CR2_DIS_NSS_Pos (3U) 6149 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ 6150 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */ 6151 #define USART_CR2_ADDM7_Pos (4U) 6152 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 6153 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 6154 #define USART_CR2_LBDL_Pos (5U) 6155 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 6156 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 6157 #define USART_CR2_LBDIE_Pos (6U) 6158 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 6159 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 6160 #define USART_CR2_LBCL_Pos (8U) 6161 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 6162 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 6163 #define USART_CR2_CPHA_Pos (9U) 6164 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 6165 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 6166 #define USART_CR2_CPOL_Pos (10U) 6167 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 6168 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 6169 #define USART_CR2_CLKEN_Pos (11U) 6170 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 6171 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 6172 #define USART_CR2_STOP_Pos (12U) 6173 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 6174 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 6175 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 6176 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 6177 #define USART_CR2_LINEN_Pos (14U) 6178 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 6179 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 6180 #define USART_CR2_SWAP_Pos (15U) 6181 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 6182 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 6183 #define USART_CR2_RXINV_Pos (16U) 6184 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 6185 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 6186 #define USART_CR2_TXINV_Pos (17U) 6187 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 6188 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 6189 #define USART_CR2_DATAINV_Pos (18U) 6190 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 6191 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 6192 #define USART_CR2_MSBFIRST_Pos (19U) 6193 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 6194 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 6195 #define USART_CR2_ABREN_Pos (20U) 6196 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 6197 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 6198 #define USART_CR2_ABRMODE_Pos (21U) 6199 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 6200 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 6201 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 6202 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 6203 #define USART_CR2_RTOEN_Pos (23U) 6204 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 6205 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 6206 #define USART_CR2_ADD_Pos (24U) 6207 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 6208 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6209 6210 /****************** Bit definition for USART_CR3 register *******************/ 6211 #define USART_CR3_EIE_Pos (0U) 6212 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6213 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6214 #define USART_CR3_IREN_Pos (1U) 6215 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6216 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6217 #define USART_CR3_IRLP_Pos (2U) 6218 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6219 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6220 #define USART_CR3_HDSEL_Pos (3U) 6221 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6222 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6223 #define USART_CR3_NACK_Pos (4U) 6224 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6225 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 6226 #define USART_CR3_SCEN_Pos (5U) 6227 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6228 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 6229 #define USART_CR3_DMAR_Pos (6U) 6230 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6231 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6232 #define USART_CR3_DMAT_Pos (7U) 6233 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6234 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6235 #define USART_CR3_RTSE_Pos (8U) 6236 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6237 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6238 #define USART_CR3_CTSE_Pos (9U) 6239 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6240 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6241 #define USART_CR3_CTSIE_Pos (10U) 6242 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6243 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6244 #define USART_CR3_ONEBIT_Pos (11U) 6245 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6246 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6247 #define USART_CR3_OVRDIS_Pos (12U) 6248 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 6249 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 6250 #define USART_CR3_DDRE_Pos (13U) 6251 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 6252 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 6253 #define USART_CR3_DEM_Pos (14U) 6254 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 6255 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 6256 #define USART_CR3_DEP_Pos (15U) 6257 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 6258 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 6259 #define USART_CR3_SCARCNT_Pos (17U) 6260 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 6261 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 6262 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 6263 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 6264 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 6265 #define USART_CR3_WUS_Pos (20U) 6266 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 6267 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 6268 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 6269 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 6270 #define USART_CR3_WUFIE_Pos (22U) 6271 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 6272 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 6273 #define USART_CR3_TXFTIE_Pos (23U) 6274 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ 6275 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ 6276 #define USART_CR3_TCBGTIE_Pos (24U) 6277 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 6278 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 6279 #define USART_CR3_RXFTCFG_Pos (25U) 6280 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ 6281 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ 6282 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ 6283 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ 6284 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ 6285 #define USART_CR3_RXFTIE_Pos (28U) 6286 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ 6287 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ 6288 #define USART_CR3_TXFTCFG_Pos (29U) 6289 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ 6290 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ 6291 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ 6292 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ 6293 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ 6294 6295 /****************** Bit definition for USART_BRR register *******************/ 6296 #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ 6297 6298 /****************** Bit definition for USART_GTPR register ******************/ 6299 #define USART_GTPR_PSC_Pos (0U) 6300 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6301 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6302 #define USART_GTPR_GT_Pos (8U) 6303 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6304 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 6305 6306 /******************* Bit definition for USART_RTOR register *****************/ 6307 #define USART_RTOR_RTO_Pos (0U) 6308 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 6309 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 6310 #define USART_RTOR_BLEN_Pos (24U) 6311 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 6312 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 6313 6314 /******************* Bit definition for USART_RQR register ******************/ 6315 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ 6316 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ 6317 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ 6318 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ 6319 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ 6320 6321 /******************* Bit definition for USART_ISR register ******************/ 6322 #define USART_ISR_PE_Pos (0U) 6323 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 6324 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 6325 #define USART_ISR_FE_Pos (1U) 6326 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 6327 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 6328 #define USART_ISR_NE_Pos (2U) 6329 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 6330 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 6331 #define USART_ISR_ORE_Pos (3U) 6332 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 6333 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 6334 #define USART_ISR_IDLE_Pos (4U) 6335 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 6336 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 6337 #define USART_ISR_RXNE_RXFNE_Pos (5U) 6338 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */ 6339 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */ 6340 #define USART_ISR_TC_Pos (6U) 6341 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 6342 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 6343 #define USART_ISR_TXE_TXFNF_Pos (7U) 6344 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */ 6345 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */ 6346 #define USART_ISR_LBDF_Pos (8U) 6347 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 6348 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 6349 #define USART_ISR_CTSIF_Pos (9U) 6350 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 6351 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 6352 #define USART_ISR_CTS_Pos (10U) 6353 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 6354 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 6355 #define USART_ISR_RTOF_Pos (11U) 6356 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 6357 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 6358 #define USART_ISR_EOBF_Pos (12U) 6359 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 6360 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 6361 #define USART_ISR_UDR_Pos (13U) 6362 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ 6363 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */ 6364 #define USART_ISR_ABRE_Pos (14U) 6365 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 6366 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 6367 #define USART_ISR_ABRF_Pos (15U) 6368 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 6369 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 6370 #define USART_ISR_BUSY_Pos (16U) 6371 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 6372 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 6373 #define USART_ISR_CMF_Pos (17U) 6374 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 6375 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 6376 #define USART_ISR_SBKF_Pos (18U) 6377 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 6378 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 6379 #define USART_ISR_RWU_Pos (19U) 6380 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 6381 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 6382 #define USART_ISR_WUF_Pos (20U) 6383 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 6384 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 6385 #define USART_ISR_TEACK_Pos (21U) 6386 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 6387 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 6388 #define USART_ISR_REACK_Pos (22U) 6389 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 6390 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 6391 #define USART_ISR_TXFE_Pos (23U) 6392 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ 6393 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */ 6394 #define USART_ISR_RXFF_Pos (24U) 6395 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ 6396 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */ 6397 #define USART_ISR_TCBGT_Pos (25U) 6398 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 6399 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ 6400 #define USART_ISR_RXFT_Pos (26U) 6401 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ 6402 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */ 6403 #define USART_ISR_TXFT_Pos (27U) 6404 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ 6405 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */ 6406 6407 /******************* Bit definition for USART_ICR register ******************/ 6408 #define USART_ICR_PECF_Pos (0U) 6409 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 6410 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 6411 #define USART_ICR_FECF_Pos (1U) 6412 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 6413 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 6414 #define USART_ICR_NECF_Pos (2U) 6415 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 6416 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ 6417 #define USART_ICR_ORECF_Pos (3U) 6418 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 6419 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 6420 #define USART_ICR_IDLECF_Pos (4U) 6421 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 6422 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 6423 #define USART_ICR_TXFECF_Pos (5U) 6424 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ 6425 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */ 6426 #define USART_ICR_TCCF_Pos (6U) 6427 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 6428 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 6429 #define USART_ICR_TCBGTCF_Pos (7U) 6430 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 6431 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 6432 #define USART_ICR_LBDCF_Pos (8U) 6433 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 6434 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 6435 #define USART_ICR_CTSCF_Pos (9U) 6436 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 6437 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 6438 #define USART_ICR_RTOCF_Pos (11U) 6439 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 6440 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 6441 #define USART_ICR_EOBCF_Pos (12U) 6442 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 6443 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 6444 #define USART_ICR_UDRCF_Pos (13U) 6445 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ 6446 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ 6447 #define USART_ICR_CMCF_Pos (17U) 6448 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 6449 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 6450 #define USART_ICR_WUCF_Pos (20U) 6451 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 6452 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 6453 6454 /******************* Bit definition for USART_RDR register ******************/ 6455 #define USART_RDR_RDR_Pos (0U) 6456 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 6457 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 6458 6459 /******************* Bit definition for USART_TDR register ******************/ 6460 #define USART_TDR_TDR_Pos (0U) 6461 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 6462 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 6463 6464 /******************* Bit definition for USART_PRESC register ****************/ 6465 #define USART_PRESC_PRESCALER_Pos (0U) 6466 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ 6467 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ 6468 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ 6469 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ 6470 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ 6471 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ 6472 6473 /******************************************************************************/ 6474 /* */ 6475 /* Window WATCHDOG */ 6476 /* */ 6477 /******************************************************************************/ 6478 /******************* Bit definition for WWDG_CR register ********************/ 6479 #define WWDG_CR_T_Pos (0U) 6480 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 6481 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 6482 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 6483 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 6484 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 6485 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 6486 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 6487 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 6488 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 6489 6490 #define WWDG_CR_WDGA_Pos (7U) 6491 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 6492 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 6493 6494 /******************* Bit definition for WWDG_CFR register *******************/ 6495 #define WWDG_CFR_W_Pos (0U) 6496 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 6497 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 6498 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 6499 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 6500 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 6501 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 6502 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 6503 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 6504 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 6505 6506 #define WWDG_CFR_WDGTB_Pos (11U) 6507 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ 6508 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ 6509 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ 6510 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ 6511 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ 6512 6513 #define WWDG_CFR_EWI_Pos (9U) 6514 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 6515 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 6516 6517 /******************* Bit definition for WWDG_SR register ********************/ 6518 #define WWDG_SR_EWIF_Pos (0U) 6519 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 6520 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 6521 6522 6523 /** @addtogroup Exported_macros 6524 * @{ 6525 */ 6526 6527 /******************************* ADC Instances ********************************/ 6528 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 6529 6530 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 6531 6532 /******************************* CRC Instances ********************************/ 6533 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 6534 6535 /******************************** DMA Instances *******************************/ 6536 6537 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 6538 ((INSTANCE) == DMA1_Channel2) || \ 6539 ((INSTANCE) == DMA1_Channel3)) 6540 6541 /******************************** DMAMUX Instances ****************************/ 6542 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1) 6543 6544 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \ 6545 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \ 6546 ((INSTANCE) == DMAMUX1_RequestGenerator2)) 6547 6548 /******************************* GPIO Instances *******************************/ 6549 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6550 ((INSTANCE) == GPIOB) || \ 6551 ((INSTANCE) == GPIOC) || \ 6552 ((INSTANCE) == GPIOD) || \ 6553 ((INSTANCE) == GPIOF)) 6554 /******************************* GPIO AF Instances ****************************/ 6555 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 6556 6557 /**************************** GPIO Lock Instances *****************************/ 6558 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6559 ((INSTANCE) == GPIOB) || \ 6560 ((INSTANCE) == GPIOC)) 6561 6562 /******************************** I2C Instances *******************************/ 6563 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 6564 6565 /****************************** RTC Instances *********************************/ 6566 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 6567 6568 /****************************** SMBUS Instances *******************************/ 6569 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) 6570 6571 /****************************** WAKEUP_FROMSTOP Instances *******************************/ 6572 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) 6573 6574 /******************************** SPI Instances *******************************/ 6575 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 6576 /******************************** SPI Instances *******************************/ 6577 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 6578 6579 6580 /****************** TIM Instances : All supported instances *******************/ 6581 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6582 ((INSTANCE) == TIM3) || \ 6583 ((INSTANCE) == TIM14) || \ 6584 ((INSTANCE) == TIM16) || \ 6585 ((INSTANCE) == TIM17)) 6586 6587 /****************** TIM Instances : supporting 32 bits counter ****************/ 6588 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0UL) 6589 6590 /****************** TIM Instances : supporting the break function *************/ 6591 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6592 ((INSTANCE) == TIM16) || \ 6593 ((INSTANCE) == TIM17)) 6594 6595 /************** TIM Instances : supporting Break source selection *************/ 6596 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (0UL) 6597 6598 /****************** TIM Instances : supporting 2 break inputs *****************/ 6599 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 6600 6601 /************* TIM Instances : at least 1 capture/compare channel *************/ 6602 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6603 ((INSTANCE) == TIM3) || \ 6604 ((INSTANCE) == TIM14) || \ 6605 ((INSTANCE) == TIM16) || \ 6606 ((INSTANCE) == TIM17)) 6607 6608 /************ TIM Instances : at least 2 capture/compare channels *************/ 6609 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6610 ((INSTANCE) == TIM3)) 6611 6612 /************ TIM Instances : at least 3 capture/compare channels *************/ 6613 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6614 ((INSTANCE) == TIM3)) 6615 6616 /************ TIM Instances : at least 4 capture/compare channels *************/ 6617 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6618 ((INSTANCE) == TIM3)) 6619 6620 /****************** TIM Instances : at least 5 capture/compare channels *******/ 6621 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 6622 6623 /****************** TIM Instances : at least 6 capture/compare channels *******/ 6624 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 6625 6626 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ 6627 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6628 ((INSTANCE) == TIM16) || \ 6629 ((INSTANCE) == TIM17)) 6630 6631 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 6632 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6633 ((INSTANCE) == TIM3) || \ 6634 ((INSTANCE) == TIM16) || \ 6635 ((INSTANCE) == TIM17)) 6636 6637 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 6638 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6639 ((INSTANCE) == TIM3) || \ 6640 ((INSTANCE) == TIM14) || \ 6641 ((INSTANCE) == TIM16) || \ 6642 ((INSTANCE) == TIM17)) 6643 6644 /******************** TIM Instances : DMA burst feature ***********************/ 6645 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6646 ((INSTANCE) == TIM3) || \ 6647 ((INSTANCE) == TIM16) || \ 6648 ((INSTANCE) == TIM17)) 6649 6650 /******************* TIM Instances : output(s) available **********************/ 6651 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 6652 ((((INSTANCE) == TIM1) && \ 6653 (((CHANNEL) == TIM_CHANNEL_1) || \ 6654 ((CHANNEL) == TIM_CHANNEL_2) || \ 6655 ((CHANNEL) == TIM_CHANNEL_3) || \ 6656 ((CHANNEL) == TIM_CHANNEL_4) || \ 6657 ((CHANNEL) == TIM_CHANNEL_5) || \ 6658 ((CHANNEL) == TIM_CHANNEL_6))) \ 6659 || \ 6660 (((INSTANCE) == TIM3) && \ 6661 (((CHANNEL) == TIM_CHANNEL_1) || \ 6662 ((CHANNEL) == TIM_CHANNEL_2) || \ 6663 ((CHANNEL) == TIM_CHANNEL_3) || \ 6664 ((CHANNEL) == TIM_CHANNEL_4))) \ 6665 || \ 6666 (((INSTANCE) == TIM14) && \ 6667 (((CHANNEL) == TIM_CHANNEL_1))) \ 6668 || \ 6669 (((INSTANCE) == TIM16) && \ 6670 (((CHANNEL) == TIM_CHANNEL_1))) \ 6671 || \ 6672 (((INSTANCE) == TIM17) && \ 6673 (((CHANNEL) == TIM_CHANNEL_1)))) 6674 6675 /****************** TIM Instances : supporting complementary output(s) ********/ 6676 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 6677 ((((INSTANCE) == TIM1) && \ 6678 (((CHANNEL) == TIM_CHANNEL_1) || \ 6679 ((CHANNEL) == TIM_CHANNEL_2) || \ 6680 ((CHANNEL) == TIM_CHANNEL_3))) \ 6681 || \ 6682 (((INSTANCE) == TIM16) && \ 6683 ((CHANNEL) == TIM_CHANNEL_1)) \ 6684 || \ 6685 (((INSTANCE) == TIM17) && \ 6686 ((CHANNEL) == TIM_CHANNEL_1))) 6687 6688 /****************** TIM Instances : supporting clock division *****************/ 6689 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6690 ((INSTANCE) == TIM3) || \ 6691 ((INSTANCE) == TIM14) || \ 6692 ((INSTANCE) == TIM16) || \ 6693 ((INSTANCE) == TIM17)) 6694 6695 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 6696 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6697 ((INSTANCE) == TIM3)) 6698 6699 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 6700 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6701 ((INSTANCE) == TIM3)) 6702 6703 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 6704 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6705 ((INSTANCE) == TIM3)) 6706 6707 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 6708 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6709 ((INSTANCE) == TIM3)) 6710 6711 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 6712 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 6713 6714 /****************** TIM Instances : supporting commutation event generation ***/ 6715 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6716 ((INSTANCE) == TIM16) || \ 6717 ((INSTANCE) == TIM17)) 6718 6719 /****************** TIM Instances : supporting counting mode selection ********/ 6720 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6721 ((INSTANCE) == TIM3)) 6722 6723 /****************** TIM Instances : supporting encoder interface **************/ 6724 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6725 ((INSTANCE) == TIM3)) 6726 6727 /****************** TIM Instances : supporting Hall sensor interface **********/ 6728 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6729 ((INSTANCE) == TIM3)) 6730 6731 /**************** TIM Instances : external trigger input available ************/ 6732 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6733 ((INSTANCE) == TIM3)) 6734 6735 /**************** TIM Instances : supporting ETR source selection ***************/ 6736 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6737 ((INSTANCE) == TIM3)) 6738 6739 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 6740 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6741 ((INSTANCE) == TIM3)) 6742 6743 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 6744 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6745 ((INSTANCE) == TIM3)) 6746 6747 /****************** TIM Instances : supporting OCxREF clear *******************/ 6748 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6749 ((INSTANCE) == TIM3)) 6750 6751 /****************** TIM Instances : remapping capability **********************/ 6752 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6753 ((INSTANCE) == TIM3)) 6754 6755 /****************** TIM Instances : supporting repetition counter *************/ 6756 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6757 ((INSTANCE) == TIM16) || \ 6758 ((INSTANCE) == TIM17)) 6759 6760 /****************** TIM Instances : supporting synchronization ****************/ 6761 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) 6762 6763 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 6764 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 6765 6766 /******************* TIM Instances : Timer input XOR function *****************/ 6767 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6768 ((INSTANCE) == TIM3)) 6769 6770 /******************* TIM Instances : Timer input selection ********************/ 6771 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \ 6772 ((INSTANCE) == TIM16) || \ 6773 ((INSTANCE) == TIM17)) 6774 6775 /************ TIM Instances : Advanced timers ********************************/ 6776 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 6777 6778 /******************** UART Instances : Asynchronous mode **********************/ 6779 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6780 ((INSTANCE) == USART2)) 6781 /******************** USART Instances : Synchronous mode **********************/ 6782 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6783 ((INSTANCE) == USART2)) 6784 /****************** UART Instances : Hardware Flow control ********************/ 6785 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6786 ((INSTANCE) == USART2)) 6787 /********************* USART Instances : Smard card mode ***********************/ 6788 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6789 /****************** UART Instances : Auto Baud Rate detection ****************/ 6790 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6791 6792 /******************** UART Instances : Half-Duplex mode **********************/ 6793 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6794 ((INSTANCE) == USART2)) 6795 /******************** UART Instances : LIN mode **********************/ 6796 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6797 /******************** UART Instances : Wake-up from Stop mode **********************/ 6798 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6799 6800 /****************** UART Instances : Driver Enable *****************/ 6801 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6802 ((INSTANCE) == USART2)) 6803 /****************** UART Instances : SPI Slave selection mode ***************/ 6804 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6805 ((INSTANCE) == USART2)) 6806 /****************** UART Instances : Driver Enable *****************/ 6807 #define IS_UART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6808 /*********************** UART Instances : IRDA mode ***************************/ 6809 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 6810 /****************************** IWDG Instances ********************************/ 6811 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6812 6813 /****************************** WWDG Instances ********************************/ 6814 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6815 6816 /** 6817 * @} 6818 */ 6819 6820 /** 6821 * @} 6822 */ 6823 6824 /** 6825 * @} 6826 */ 6827 6828 #ifdef __cplusplus 6829 } 6830 #endif /* __cplusplus */ 6831 6832 #endif /* STM32C031xx_H */ 6833 6834 /** 6835 * @} 6836 */ 6837 6838 /** 6839 * @} 6840 */ 6841
