1 /** 2 ****************************************************************************** 3 * @file stm32g050xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32g050xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2018-2021 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 /** @addtogroup CMSIS_Device 28 * @{ 29 */ 30 31 /** @addtogroup stm32g050xx 32 * @{ 33 */ 34 35 #ifndef STM32G050xx_H 36 #define STM32G050xx_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif /* __cplusplus */ 41 42 /** @addtogroup Configuration_section_for_CMSIS 43 * @{ 44 */ 45 46 /** 47 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 48 */ 49 #define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ 50 #define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */ 51 #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ 52 #define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief stm32g050xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ 74 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ 77 /****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ 78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 79 RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ 80 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 81 RCC_IRQn = 4, /*!< RCC global Interrupt */ 82 EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ 83 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 84 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 85 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 86 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 87 DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ 88 ADC1_IRQn = 12, /*!< ADC1 Interrupts */ 89 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 90 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 91 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 92 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ 93 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ 94 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 95 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 96 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 97 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 98 I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ 99 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 100 SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ 101 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 102 USART1_IRQn = 27, /*!< USART1 Interrupt */ 103 USART2_IRQn = 28, /*!< USART2 Interrupt */ 104 } IRQn_Type; 105 106 /** 107 * @} 108 */ 109 110 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ 111 #include "system_stm32g0xx.h" 112 #include <stdint.h> 113 114 /** @addtogroup Peripheral_registers_structures 115 * @{ 116 */ 117 118 /** 119 * @brief Analog to Digital Converter 120 */ 121 typedef struct 122 { 123 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 124 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 125 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 126 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 127 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 128 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 129 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 130 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 131 __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 132 __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 133 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 134 __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ 135 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ 136 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 137 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ 138 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ 139 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ 140 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ 141 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ 142 } ADC_TypeDef; 143 144 typedef struct 145 { 146 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 147 } ADC_Common_TypeDef; 148 149 /* Legacy registers naming */ 150 #define TR1 AWD1TR 151 #define TR2 AWD2TR 152 #define TR3 AWD3TR 153 154 155 156 157 /** 158 * @brief CRC calculation unit 159 */ 160 typedef struct 161 { 162 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 163 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 164 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 165 uint32_t RESERVED1; /*!< Reserved, 0x0C */ 166 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 167 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 168 } CRC_TypeDef; 169 170 171 /** 172 * @brief Debug MCU 173 */ 174 typedef struct 175 { 176 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 177 __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ 178 __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ 179 __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ 180 } DBG_TypeDef; 181 182 /** 183 * @brief DMA Controller 184 */ 185 typedef struct 186 { 187 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 188 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 189 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 190 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 191 } DMA_Channel_TypeDef; 192 193 typedef struct 194 { 195 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 196 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 197 } DMA_TypeDef; 198 199 /** 200 * @brief DMA Multiplexer 201 */ 202 typedef struct 203 { 204 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ 205 }DMAMUX_Channel_TypeDef; 206 207 typedef struct 208 { 209 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ 210 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ 211 }DMAMUX_ChannelStatus_TypeDef; 212 213 typedef struct 214 { 215 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ 216 }DMAMUX_RequestGen_TypeDef; 217 218 typedef struct 219 { 220 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ 221 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ 222 }DMAMUX_RequestGenStatus_TypeDef; 223 224 /** 225 * @brief Asynch Interrupt/Event Controller (EXTI) 226 */ 227 typedef struct 228 { 229 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ 230 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ 231 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ 232 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ 233 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ 234 uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ 235 uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ 236 uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ 237 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ 238 uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ 239 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ 240 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ 241 } EXTI_TypeDef; 242 243 /** 244 * @brief FLASH Registers 245 */ 246 typedef struct 247 { 248 __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ 249 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ 250 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ 251 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ 252 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ 253 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ 254 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ 255 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ 256 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ 257 __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ 258 __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ 259 __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ 260 __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ 261 __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ 262 __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ 263 } FLASH_TypeDef; 264 265 /** 266 * @brief General Purpose I/O 267 */ 268 typedef struct 269 { 270 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 271 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 272 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 273 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 274 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 275 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 276 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 277 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 278 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 279 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 280 } GPIO_TypeDef; 281 282 283 /** 284 * @brief Inter-integrated Circuit Interface 285 */ 286 typedef struct 287 { 288 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 289 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 290 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 291 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 292 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 293 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 294 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 295 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 296 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 297 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 298 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 299 } I2C_TypeDef; 300 301 /** 302 * @brief Independent WATCHDOG 303 */ 304 typedef struct 305 { 306 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 307 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 308 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 309 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 310 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 311 } IWDG_TypeDef; 312 313 314 315 /** 316 * @brief Power Control 317 */ 318 typedef struct 319 { 320 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ 321 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ 322 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ 323 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ 324 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ 325 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ 326 __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ 327 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ 328 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ 329 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ 330 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ 331 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ 332 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ 333 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ 334 __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ 335 __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ 336 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ 337 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ 338 __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ 339 __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ 340 } PWR_TypeDef; 341 342 /** 343 * @brief Reset and Clock Control 344 */ 345 typedef struct 346 { 347 __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ 348 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ 349 __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ 350 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ 351 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ 352 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 353 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ 354 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ 355 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ 356 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ 357 __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ 358 __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ 359 __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ 360 __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ 361 __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ 362 __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ 363 __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ 364 __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ 365 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ 366 __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ 367 __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ 368 __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ 369 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ 370 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ 371 __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ 372 } RCC_TypeDef; 373 374 /** 375 * @brief Real-Time Clock 376 */ 377 typedef struct 378 { 379 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 380 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 381 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ 382 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ 383 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 384 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 385 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ 386 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ 387 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ 388 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 389 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ 390 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 391 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 392 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 393 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 394 uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ 395 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ 396 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 397 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ 398 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ 399 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ 400 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ 401 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ 402 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ 403 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ 404 } RTC_TypeDef; 405 406 /** 407 * @brief Tamper and backup registers 408 */ 409 typedef struct 410 { 411 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ 412 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ 413 uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ 414 __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ 415 uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ 416 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ 417 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ 418 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ 419 uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ 420 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ 421 uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ 422 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ 423 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ 424 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ 425 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ 426 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ 427 } TAMP_TypeDef; 428 429 /** 430 * @brief Serial Peripheral Interface 431 */ 432 typedef struct 433 { 434 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 435 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 436 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 437 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 438 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 439 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 440 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 441 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 442 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 443 } SPI_TypeDef; 444 445 /** 446 * @brief System configuration controller 447 */ 448 typedef struct 449 { 450 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 451 uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ 452 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 453 uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ 454 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ 455 } SYSCFG_TypeDef; 456 457 /** 458 * @brief TIM 459 */ 460 typedef struct 461 { 462 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 463 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 464 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 465 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 466 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 467 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 468 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 469 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 470 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 471 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 472 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 473 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 474 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 475 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 476 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 477 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 478 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 479 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 480 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 481 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 482 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ 483 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 484 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 485 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 486 __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ 487 __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ 488 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ 489 } TIM_TypeDef; 490 491 /** 492 * @brief Universal Synchronous Asynchronous Receiver Transmitter 493 */ 494 typedef struct 495 { 496 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 497 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 498 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 499 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 500 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 501 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 502 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 503 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 504 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 505 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 506 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 507 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ 508 } USART_TypeDef; 509 510 511 /** 512 * @brief Window WATCHDOG 513 */ 514 typedef struct 515 { 516 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 517 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 518 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 519 } WWDG_TypeDef; 520 521 522 /** 523 * @} 524 */ 525 526 /** @addtogroup Peripheral_memory_map 527 * @{ 528 */ 529 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ 530 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ 531 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ 532 #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ 533 #define SRAM_SIZE_MAX (0x00004000UL) /*!< maximum SRAM size (up to 16 KBytes) */ 534 535 #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) 536 537 /*!< Peripheral memory map */ 538 #define APBPERIPH_BASE (PERIPH_BASE) 539 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 540 541 /*!< APB peripherals */ 542 543 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 544 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) 545 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) 546 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 547 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 548 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 549 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 550 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 551 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 552 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 553 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) 554 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 555 #define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) 556 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 557 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 558 #define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) 559 #define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ 560 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 561 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 562 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 563 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) 564 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 565 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 566 #define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) 567 568 569 /*!< AHB peripherals */ 570 #define DMA1_BASE (AHBPERIPH_BASE) 571 #define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) 572 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 573 #define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) 574 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) 575 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 576 577 578 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 579 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 580 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 581 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 582 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 583 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 584 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 585 586 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) 587 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) 588 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) 589 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) 590 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) 591 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) 592 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) 593 594 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) 595 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) 596 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) 597 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) 598 599 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) 600 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) 601 602 /*!< IOPORT */ 603 #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) 604 #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) 605 #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) 606 #define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) 607 #define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) 608 609 /*!< Device Electronic Signature */ 610 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ 611 #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ 612 #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ 613 614 /** 615 * @} 616 */ 617 618 /** @addtogroup Peripheral_declaration 619 * @{ 620 */ 621 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 622 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 623 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 624 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 625 #define RTC ((RTC_TypeDef *) RTC_BASE) 626 #define TAMP ((TAMP_TypeDef *) TAMP_BASE) 627 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 628 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 629 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 630 #define USART2 ((USART_TypeDef *) USART2_BASE) 631 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 632 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 633 #define PWR ((PWR_TypeDef *) PWR_BASE) 634 #define RCC ((RCC_TypeDef *) RCC_BASE) 635 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 636 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 637 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 638 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 639 #define USART1 ((USART_TypeDef *) USART1_BASE) 640 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 641 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 642 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 643 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 644 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 645 #define CRC ((CRC_TypeDef *) CRC_BASE) 646 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 647 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 648 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 649 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 650 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 651 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 652 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) 653 #define ADC (ADC1_COMMON) /* Kept for legacy purpose */ 654 655 656 657 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 658 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 659 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 660 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 661 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 662 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 663 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 664 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) 665 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) 666 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) 667 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) 668 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) 669 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) 670 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) 671 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) 672 673 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) 674 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) 675 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) 676 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) 677 678 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) 679 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) 680 681 #define DBG ((DBG_TypeDef *) DBG_BASE) 682 683 /** 684 * @} 685 */ 686 687 /** @addtogroup Exported_constants 688 * @{ 689 */ 690 691 /** @addtogroup Hardware_Constant_Definition 692 * @{ 693 */ 694 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ 695 696 /** 697 * @} 698 */ 699 700 /** @addtogroup Peripheral_Registers_Bits_Definition 701 * @{ 702 */ 703 704 /******************************************************************************/ 705 /* Peripheral Registers Bits Definition */ 706 /******************************************************************************/ 707 708 /******************************************************************************/ 709 /* */ 710 /* Analog to Digital Converter (ADC) */ 711 /* */ 712 /******************************************************************************/ 713 /******************** Bit definition for ADC_ISR register *******************/ 714 #define ADC_ISR_ADRDY_Pos (0U) 715 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 716 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 717 #define ADC_ISR_EOSMP_Pos (1U) 718 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 719 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 720 #define ADC_ISR_EOC_Pos (2U) 721 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 722 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 723 #define ADC_ISR_EOS_Pos (3U) 724 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 725 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 726 #define ADC_ISR_OVR_Pos (4U) 727 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 728 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 729 #define ADC_ISR_AWD1_Pos (7U) 730 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 731 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 732 #define ADC_ISR_AWD2_Pos (8U) 733 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 734 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 735 #define ADC_ISR_AWD3_Pos (9U) 736 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 737 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 738 #define ADC_ISR_EOCAL_Pos (11U) 739 #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 740 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ 741 #define ADC_ISR_CCRDY_Pos (13U) 742 #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ 743 #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ 744 745 /* Legacy defines */ 746 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 747 748 /******************** Bit definition for ADC_IER register *******************/ 749 #define ADC_IER_ADRDYIE_Pos (0U) 750 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 751 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 752 #define ADC_IER_EOSMPIE_Pos (1U) 753 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 754 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 755 #define ADC_IER_EOCIE_Pos (2U) 756 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 757 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 758 #define ADC_IER_EOSIE_Pos (3U) 759 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 760 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 761 #define ADC_IER_OVRIE_Pos (4U) 762 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 763 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 764 #define ADC_IER_AWD1IE_Pos (7U) 765 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 766 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 767 #define ADC_IER_AWD2IE_Pos (8U) 768 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 769 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 770 #define ADC_IER_AWD3IE_Pos (9U) 771 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 772 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 773 #define ADC_IER_EOCALIE_Pos (11U) 774 #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 775 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ 776 #define ADC_IER_CCRDYIE_Pos (13U) 777 #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ 778 #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ 779 780 /* Legacy defines */ 781 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 782 783 /******************** Bit definition for ADC_CR register ********************/ 784 #define ADC_CR_ADEN_Pos (0U) 785 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 786 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 787 #define ADC_CR_ADDIS_Pos (1U) 788 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 789 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 790 #define ADC_CR_ADSTART_Pos (2U) 791 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 792 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 793 #define ADC_CR_ADSTP_Pos (4U) 794 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 795 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 796 #define ADC_CR_ADVREGEN_Pos (28U) 797 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 798 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 799 #define ADC_CR_ADCAL_Pos (31U) 800 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 801 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 802 803 /******************** Bit definition for ADC_CFGR1 register *****************/ 804 #define ADC_CFGR1_DMAEN_Pos (0U) 805 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 806 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 807 #define ADC_CFGR1_DMACFG_Pos (1U) 808 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 809 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 810 811 #define ADC_CFGR1_SCANDIR_Pos (2U) 812 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 813 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 814 815 #define ADC_CFGR1_RES_Pos (3U) 816 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 817 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 818 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 819 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 820 821 #define ADC_CFGR1_ALIGN_Pos (5U) 822 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 823 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 824 825 #define ADC_CFGR1_EXTSEL_Pos (6U) 826 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 827 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 828 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 829 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 830 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 831 832 #define ADC_CFGR1_EXTEN_Pos (10U) 833 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 834 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 835 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 836 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 837 838 #define ADC_CFGR1_OVRMOD_Pos (12U) 839 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 840 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 841 #define ADC_CFGR1_CONT_Pos (13U) 842 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 843 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 844 #define ADC_CFGR1_WAIT_Pos (14U) 845 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 846 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 847 #define ADC_CFGR1_AUTOFF_Pos (15U) 848 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 849 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 850 #define ADC_CFGR1_DISCEN_Pos (16U) 851 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 852 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 853 #define ADC_CFGR1_CHSELRMOD_Pos (21U) 854 #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ 855 #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ 856 857 #define ADC_CFGR1_AWD1SGL_Pos (22U) 858 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 859 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 860 #define ADC_CFGR1_AWD1EN_Pos (23U) 861 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 862 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 863 864 #define ADC_CFGR1_AWD1CH_Pos (26U) 865 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 866 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 867 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 868 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 869 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 870 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 871 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 872 873 /* Legacy defines */ 874 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 875 876 /******************** Bit definition for ADC_CFGR2 register *****************/ 877 #define ADC_CFGR2_OVSE_Pos (0U) 878 #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 879 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 880 881 #define ADC_CFGR2_OVSR_Pos (2U) 882 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 883 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 884 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 885 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 886 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 887 888 #define ADC_CFGR2_OVSS_Pos (5U) 889 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 890 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 891 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 892 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 893 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 894 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 895 896 #define ADC_CFGR2_TOVS_Pos (9U) 897 #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ 898 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 899 900 #define ADC_CFGR2_LFTRIG_Pos (29U) 901 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ 902 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ 903 904 #define ADC_CFGR2_CKMODE_Pos (30U) 905 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 906 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 907 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 908 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 909 910 /******************** Bit definition for ADC_SMPR register ******************/ 911 #define ADC_SMPR_SMP1_Pos (0U) 912 #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ 913 #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ 914 #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ 915 #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ 916 #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ 917 918 #define ADC_SMPR_SMP2_Pos (4U) 919 #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ 920 #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ 921 #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ 922 #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ 923 #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ 924 925 #define ADC_SMPR_SMPSEL_Pos (8U) 926 #define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ 927 #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ 928 #define ADC_SMPR_SMPSEL0_Pos (8U) 929 #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ 930 #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ 931 #define ADC_SMPR_SMPSEL1_Pos (9U) 932 #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ 933 #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ 934 #define ADC_SMPR_SMPSEL2_Pos (10U) 935 #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ 936 #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ 937 #define ADC_SMPR_SMPSEL3_Pos (11U) 938 #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ 939 #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ 940 #define ADC_SMPR_SMPSEL4_Pos (12U) 941 #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ 942 #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ 943 #define ADC_SMPR_SMPSEL5_Pos (13U) 944 #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ 945 #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ 946 #define ADC_SMPR_SMPSEL6_Pos (14U) 947 #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ 948 #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ 949 #define ADC_SMPR_SMPSEL7_Pos (15U) 950 #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ 951 #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ 952 #define ADC_SMPR_SMPSEL8_Pos (16U) 953 #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ 954 #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ 955 #define ADC_SMPR_SMPSEL9_Pos (17U) 956 #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ 957 #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ 958 #define ADC_SMPR_SMPSEL10_Pos (18U) 959 #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ 960 #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ 961 #define ADC_SMPR_SMPSEL11_Pos (19U) 962 #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ 963 #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ 964 #define ADC_SMPR_SMPSEL12_Pos (20U) 965 #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ 966 #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ 967 #define ADC_SMPR_SMPSEL13_Pos (21U) 968 #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ 969 #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ 970 #define ADC_SMPR_SMPSEL14_Pos (22U) 971 #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ 972 #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ 973 #define ADC_SMPR_SMPSEL15_Pos (23U) 974 #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ 975 #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ 976 #define ADC_SMPR_SMPSEL16_Pos (24U) 977 #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ 978 #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ 979 #define ADC_SMPR_SMPSEL17_Pos (25U) 980 #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ 981 #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ 982 #define ADC_SMPR_SMPSEL18_Pos (26U) 983 #define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ 984 #define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ 985 986 /******************** Bit definition for ADC_AWD1TR register *******************/ 987 #define ADC_AWD1TR_LT1_Pos (0U) 988 #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ 989 #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 990 #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ 991 #define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ 992 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ 993 #define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ 994 #define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ 995 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ 996 #define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ 997 #define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ 998 #define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ 999 #define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ 1000 #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ 1001 #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ 1002 1003 #define ADC_AWD1TR_HT1_Pos (16U) 1004 #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ 1005 #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1006 #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ 1007 #define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ 1008 #define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ 1009 #define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ 1010 #define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ 1011 #define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ 1012 #define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ 1013 #define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ 1014 #define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ 1015 #define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ 1016 #define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ 1017 #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ 1018 1019 /* Legacy definitions */ 1020 #define ADC_TR1_LT1 ADC_AWD1TR_LT1 1021 #define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 1022 #define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 1023 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 1024 #define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 1025 #define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 1026 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 1027 #define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 1028 #define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 1029 #define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 1030 #define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 1031 #define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 1032 #define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 1033 1034 #define ADC_TR1_HT1 ADC_AWD1TR_HT1 1035 #define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 1036 #define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 1037 #define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 1038 #define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 1039 #define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 1040 #define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 1041 #define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 1042 #define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 1043 #define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 1044 #define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 1045 #define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 1046 #define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 1047 1048 /******************** Bit definition for ADC_AWD2TR register *******************/ 1049 #define ADC_AWD2TR_LT2_Pos (0U) 1050 #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ 1051 #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1052 #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ 1053 #define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ 1054 #define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ 1055 #define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ 1056 #define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ 1057 #define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ 1058 #define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ 1059 #define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ 1060 #define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ 1061 #define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ 1062 #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ 1063 #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ 1064 1065 #define ADC_AWD2TR_HT2_Pos (16U) 1066 #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ 1067 #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1068 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ 1069 #define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ 1070 #define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ 1071 #define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ 1072 #define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ 1073 #define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ 1074 #define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ 1075 #define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ 1076 #define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ 1077 #define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ 1078 #define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ 1079 #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ 1080 1081 /* Legacy definitions */ 1082 #define ADC_TR2_LT2 ADC_AWD2TR_LT2 1083 #define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 1084 #define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 1085 #define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 1086 #define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 1087 #define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 1088 #define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 1089 #define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 1090 #define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 1091 #define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 1092 #define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 1093 #define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 1094 #define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 1095 1096 #define ADC_TR2_HT2 ADC_AWD2TR_HT2 1097 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 1098 #define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 1099 #define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 1100 #define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 1101 #define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 1102 #define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 1103 #define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 1104 #define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 1105 #define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 1106 #define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 1107 #define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 1108 #define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 1109 1110 /******************** Bit definition for ADC_CHSELR register ****************/ 1111 #define ADC_CHSELR_CHSEL_Pos (0U) 1112 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 1113 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 1114 #define ADC_CHSELR_CHSEL18_Pos (18U) 1115 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 1116 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 1117 #define ADC_CHSELR_CHSEL17_Pos (17U) 1118 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 1119 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 1120 #define ADC_CHSELR_CHSEL16_Pos (16U) 1121 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 1122 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 1123 #define ADC_CHSELR_CHSEL15_Pos (15U) 1124 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 1125 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 1126 #define ADC_CHSELR_CHSEL14_Pos (14U) 1127 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 1128 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 1129 #define ADC_CHSELR_CHSEL13_Pos (13U) 1130 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 1131 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 1132 #define ADC_CHSELR_CHSEL12_Pos (12U) 1133 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 1134 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 1135 #define ADC_CHSELR_CHSEL11_Pos (11U) 1136 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 1137 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 1138 #define ADC_CHSELR_CHSEL10_Pos (10U) 1139 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 1140 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 1141 #define ADC_CHSELR_CHSEL9_Pos (9U) 1142 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 1143 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 1144 #define ADC_CHSELR_CHSEL8_Pos (8U) 1145 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 1146 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 1147 #define ADC_CHSELR_CHSEL7_Pos (7U) 1148 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 1149 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 1150 #define ADC_CHSELR_CHSEL6_Pos (6U) 1151 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 1152 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 1153 #define ADC_CHSELR_CHSEL5_Pos (5U) 1154 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 1155 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 1156 #define ADC_CHSELR_CHSEL4_Pos (4U) 1157 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 1158 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 1159 #define ADC_CHSELR_CHSEL3_Pos (3U) 1160 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 1161 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 1162 #define ADC_CHSELR_CHSEL2_Pos (2U) 1163 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 1164 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 1165 #define ADC_CHSELR_CHSEL1_Pos (1U) 1166 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 1167 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 1168 #define ADC_CHSELR_CHSEL0_Pos (0U) 1169 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 1170 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 1171 1172 #define ADC_CHSELR_SQ_ALL_Pos (0U) 1173 #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ 1174 #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ 1175 1176 #define ADC_CHSELR_SQ8_Pos (28U) 1177 #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ 1178 #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ 1179 #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ 1180 #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ 1181 #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ 1182 #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ 1183 1184 #define ADC_CHSELR_SQ7_Pos (24U) 1185 #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ 1186 #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ 1187 #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ 1188 #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ 1189 #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ 1190 #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ 1191 1192 #define ADC_CHSELR_SQ6_Pos (20U) 1193 #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ 1194 #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ 1195 #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ 1196 #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ 1197 #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ 1198 #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ 1199 1200 #define ADC_CHSELR_SQ5_Pos (16U) 1201 #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ 1202 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ 1203 #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ 1204 #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ 1205 #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ 1206 #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ 1207 1208 #define ADC_CHSELR_SQ4_Pos (12U) 1209 #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ 1210 #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ 1211 #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ 1212 #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ 1213 #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ 1214 #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ 1215 1216 #define ADC_CHSELR_SQ3_Pos (8U) 1217 #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ 1218 #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ 1219 #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ 1220 #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ 1221 #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ 1222 #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ 1223 1224 #define ADC_CHSELR_SQ2_Pos (4U) 1225 #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ 1226 #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ 1227 #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ 1228 #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ 1229 #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ 1230 #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ 1231 1232 #define ADC_CHSELR_SQ1_Pos (0U) 1233 #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ 1234 #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ 1235 #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ 1236 #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ 1237 #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ 1238 #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ 1239 1240 /******************** Bit definition for ADC_AWD3TR register *******************/ 1241 #define ADC_AWD3TR_LT3_Pos (0U) 1242 #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ 1243 #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1244 #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ 1245 #define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ 1246 #define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ 1247 #define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ 1248 #define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ 1249 #define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ 1250 #define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ 1251 #define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ 1252 #define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ 1253 #define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ 1254 #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ 1255 #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ 1256 1257 #define ADC_AWD3TR_HT3_Pos (16U) 1258 #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ 1259 #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1260 #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ 1261 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ 1262 #define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ 1263 #define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ 1264 #define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ 1265 #define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ 1266 #define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ 1267 #define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ 1268 #define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ 1269 #define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ 1270 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ 1271 #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ 1272 1273 /* Legacy definitions */ 1274 #define ADC_TR3_LT3 ADC_AWD3TR_LT3 1275 #define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 1276 #define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 1277 #define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 1278 #define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 1279 #define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 1280 #define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 1281 #define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 1282 #define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 1283 #define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 1284 #define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 1285 #define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 1286 #define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 1287 1288 #define ADC_TR3_HT3 ADC_AWD3TR_HT3 1289 #define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 1290 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 1291 #define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 1292 #define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 1293 #define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 1294 #define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 1295 #define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 1296 #define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 1297 #define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 1298 #define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 1299 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 1300 #define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 1301 1302 /******************** Bit definition for ADC_DR register ********************/ 1303 #define ADC_DR_DATA_Pos (0U) 1304 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1305 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1306 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 1307 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 1308 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 1309 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 1310 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 1311 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 1312 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 1313 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 1314 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 1315 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 1316 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 1317 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 1318 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 1319 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 1320 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 1321 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 1322 1323 /******************** Bit definition for ADC_AWD2CR register ****************/ 1324 #define ADC_AWD2CR_AWD2CH_Pos (0U) 1325 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ 1326 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1327 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1328 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1329 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1330 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1331 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1332 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1333 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1334 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1335 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1336 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1337 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1338 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1339 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1340 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1341 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1342 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1343 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1344 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1345 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ 1346 1347 /******************** Bit definition for ADC_AWD3CR register ****************/ 1348 #define ADC_AWD3CR_AWD3CH_Pos (0U) 1349 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ 1350 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1351 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1352 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1353 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1354 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1355 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1356 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1357 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1358 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1359 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1360 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1361 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1362 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1363 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1364 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1365 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1366 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1367 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1368 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1369 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ 1370 1371 /******************** Bit definition for ADC_CALFACT register ***************/ 1372 #define ADC_CALFACT_CALFACT_Pos (0U) 1373 #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 1374 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ 1375 #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ 1376 #define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ 1377 #define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ 1378 #define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ 1379 #define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ 1380 #define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ 1381 #define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ 1382 1383 /************************* ADC Common registers *****************************/ 1384 /******************** Bit definition for ADC_CCR register *******************/ 1385 #define ADC_CCR_PRESC_Pos (18U) 1386 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 1387 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 1388 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 1389 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 1390 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 1391 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 1392 1393 #define ADC_CCR_VREFEN_Pos (22U) 1394 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1395 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 1396 #define ADC_CCR_TSEN_Pos (23U) 1397 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 1398 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 1399 #define ADC_CCR_VBATEN_Pos (24U) 1400 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1401 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 1402 1403 /* Legacy */ 1404 #define ADC_CCR_LFMEN_Pos (25U) 1405 #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ 1406 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ 1407 1408 1409 /******************************************************************************/ 1410 /* */ 1411 /* CRC calculation unit */ 1412 /* */ 1413 /******************************************************************************/ 1414 /******************* Bit definition for CRC_DR register *********************/ 1415 #define CRC_DR_DR_Pos (0U) 1416 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1417 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1418 1419 /******************* Bit definition for CRC_IDR register ********************/ 1420 #define CRC_IDR_IDR_Pos (0U) 1421 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ 1422 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ 1423 1424 /******************** Bit definition for CRC_CR register ********************/ 1425 #define CRC_CR_RESET_Pos (0U) 1426 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1427 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1428 #define CRC_CR_POLYSIZE_Pos (3U) 1429 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 1430 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 1431 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 1432 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 1433 #define CRC_CR_REV_IN_Pos (5U) 1434 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1435 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1436 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1437 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1438 #define CRC_CR_REV_OUT_Pos (7U) 1439 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1440 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1441 1442 /******************* Bit definition for CRC_INIT register *******************/ 1443 #define CRC_INIT_INIT_Pos (0U) 1444 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1445 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1446 1447 /******************* Bit definition for CRC_POL register ********************/ 1448 #define CRC_POL_POL_Pos (0U) 1449 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 1450 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 1451 1452 1453 1454 /******************************************************************************/ 1455 /* */ 1456 /* Debug MCU */ 1457 /* */ 1458 /******************************************************************************/ 1459 1460 /******************************************************************************/ 1461 /* */ 1462 /* DMA Controller (DMA) */ 1463 /* */ 1464 /******************************************************************************/ 1465 1466 /******************* Bit definition for DMA_ISR register ********************/ 1467 #define DMA_ISR_GIF1_Pos (0U) 1468 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1469 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1470 #define DMA_ISR_TCIF1_Pos (1U) 1471 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1472 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1473 #define DMA_ISR_HTIF1_Pos (2U) 1474 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1475 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1476 #define DMA_ISR_TEIF1_Pos (3U) 1477 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1478 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1479 #define DMA_ISR_GIF2_Pos (4U) 1480 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1481 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1482 #define DMA_ISR_TCIF2_Pos (5U) 1483 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1484 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1485 #define DMA_ISR_HTIF2_Pos (6U) 1486 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1487 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1488 #define DMA_ISR_TEIF2_Pos (7U) 1489 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1490 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1491 #define DMA_ISR_GIF3_Pos (8U) 1492 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1493 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1494 #define DMA_ISR_TCIF3_Pos (9U) 1495 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1496 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1497 #define DMA_ISR_HTIF3_Pos (10U) 1498 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1499 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1500 #define DMA_ISR_TEIF3_Pos (11U) 1501 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1502 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1503 #define DMA_ISR_GIF4_Pos (12U) 1504 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1505 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1506 #define DMA_ISR_TCIF4_Pos (13U) 1507 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1508 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1509 #define DMA_ISR_HTIF4_Pos (14U) 1510 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1511 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1512 #define DMA_ISR_TEIF4_Pos (15U) 1513 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1514 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1515 #define DMA_ISR_GIF5_Pos (16U) 1516 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1517 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1518 #define DMA_ISR_TCIF5_Pos (17U) 1519 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1520 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1521 #define DMA_ISR_HTIF5_Pos (18U) 1522 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1523 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1524 #define DMA_ISR_TEIF5_Pos (19U) 1525 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1526 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1527 #define DMA_ISR_GIF6_Pos (20U) 1528 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 1529 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 1530 #define DMA_ISR_TCIF6_Pos (21U) 1531 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 1532 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 1533 #define DMA_ISR_HTIF6_Pos (22U) 1534 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 1535 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 1536 #define DMA_ISR_TEIF6_Pos (23U) 1537 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 1538 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 1539 #define DMA_ISR_GIF7_Pos (24U) 1540 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 1541 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 1542 #define DMA_ISR_TCIF7_Pos (25U) 1543 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 1544 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 1545 #define DMA_ISR_HTIF7_Pos (26U) 1546 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 1547 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 1548 #define DMA_ISR_TEIF7_Pos (27U) 1549 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 1550 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 1551 1552 /******************* Bit definition for DMA_IFCR register *******************/ 1553 #define DMA_IFCR_CGIF1_Pos (0U) 1554 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1555 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ 1556 #define DMA_IFCR_CTCIF1_Pos (1U) 1557 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1558 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1559 #define DMA_IFCR_CHTIF1_Pos (2U) 1560 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1561 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1562 #define DMA_IFCR_CTEIF1_Pos (3U) 1563 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1564 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1565 #define DMA_IFCR_CGIF2_Pos (4U) 1566 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1567 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1568 #define DMA_IFCR_CTCIF2_Pos (5U) 1569 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1570 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1571 #define DMA_IFCR_CHTIF2_Pos (6U) 1572 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1573 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1574 #define DMA_IFCR_CTEIF2_Pos (7U) 1575 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1576 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1577 #define DMA_IFCR_CGIF3_Pos (8U) 1578 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1579 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1580 #define DMA_IFCR_CTCIF3_Pos (9U) 1581 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1582 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1583 #define DMA_IFCR_CHTIF3_Pos (10U) 1584 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1585 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1586 #define DMA_IFCR_CTEIF3_Pos (11U) 1587 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1588 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1589 #define DMA_IFCR_CGIF4_Pos (12U) 1590 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1591 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1592 #define DMA_IFCR_CTCIF4_Pos (13U) 1593 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1594 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1595 #define DMA_IFCR_CHTIF4_Pos (14U) 1596 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1597 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1598 #define DMA_IFCR_CTEIF4_Pos (15U) 1599 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1600 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1601 #define DMA_IFCR_CGIF5_Pos (16U) 1602 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1603 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1604 #define DMA_IFCR_CTCIF5_Pos (17U) 1605 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1606 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1607 #define DMA_IFCR_CHTIF5_Pos (18U) 1608 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1609 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1610 #define DMA_IFCR_CTEIF5_Pos (19U) 1611 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1612 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1613 #define DMA_IFCR_CGIF6_Pos (20U) 1614 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 1615 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 1616 #define DMA_IFCR_CTCIF6_Pos (21U) 1617 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 1618 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 1619 #define DMA_IFCR_CHTIF6_Pos (22U) 1620 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 1621 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 1622 #define DMA_IFCR_CTEIF6_Pos (23U) 1623 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 1624 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 1625 #define DMA_IFCR_CGIF7_Pos (24U) 1626 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 1627 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 1628 #define DMA_IFCR_CTCIF7_Pos (25U) 1629 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 1630 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 1631 #define DMA_IFCR_CHTIF7_Pos (26U) 1632 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 1633 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 1634 #define DMA_IFCR_CTEIF7_Pos (27U) 1635 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 1636 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 1637 1638 /******************* Bit definition for DMA_CCR register ********************/ 1639 #define DMA_CCR_EN_Pos (0U) 1640 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1641 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1642 #define DMA_CCR_TCIE_Pos (1U) 1643 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1644 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1645 #define DMA_CCR_HTIE_Pos (2U) 1646 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1647 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1648 #define DMA_CCR_TEIE_Pos (3U) 1649 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1650 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1651 #define DMA_CCR_DIR_Pos (4U) 1652 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1653 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1654 #define DMA_CCR_CIRC_Pos (5U) 1655 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1656 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1657 #define DMA_CCR_PINC_Pos (6U) 1658 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1659 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1660 #define DMA_CCR_MINC_Pos (7U) 1661 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1662 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1663 1664 #define DMA_CCR_PSIZE_Pos (8U) 1665 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1666 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1667 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1668 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1669 1670 #define DMA_CCR_MSIZE_Pos (10U) 1671 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1672 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1673 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1674 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1675 1676 #define DMA_CCR_PL_Pos (12U) 1677 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1678 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1679 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1680 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1681 1682 #define DMA_CCR_MEM2MEM_Pos (14U) 1683 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1684 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1685 1686 /****************** Bit definition for DMA_CNDTR register *******************/ 1687 #define DMA_CNDTR_NDT_Pos (0U) 1688 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1689 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1690 1691 /****************** Bit definition for DMA_CPAR register ********************/ 1692 #define DMA_CPAR_PA_Pos (0U) 1693 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1694 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1695 1696 /****************** Bit definition for DMA_CMAR register ********************/ 1697 #define DMA_CMAR_MA_Pos (0U) 1698 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1699 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1700 1701 /******************************************************************************/ 1702 /* */ 1703 /* DMAMUX Controller */ 1704 /* */ 1705 /******************************************************************************/ 1706 /******************** Bits definition for DMAMUX_CxCR register **************/ 1707 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) 1708 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */ 1709 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ 1710 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ 1711 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ 1712 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ 1713 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ 1714 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ 1715 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ 1716 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ 1717 #define DMAMUX_CxCR_SOIE_Pos (8U) 1718 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ 1719 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ 1720 #define DMAMUX_CxCR_EGE_Pos (9U) 1721 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ 1722 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ 1723 #define DMAMUX_CxCR_SE_Pos (16U) 1724 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ 1725 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ 1726 #define DMAMUX_CxCR_SPOL_Pos (17U) 1727 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ 1728 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ 1729 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ 1730 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ 1731 #define DMAMUX_CxCR_NBREQ_Pos (19U) 1732 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ 1733 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ 1734 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ 1735 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ 1736 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ 1737 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ 1738 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ 1739 #define DMAMUX_CxCR_SYNC_ID_Pos (24U) 1740 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ 1741 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ 1742 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ 1743 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ 1744 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ 1745 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ 1746 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ 1747 1748 /******************* Bits definition for DMAMUX_CSR register **************/ 1749 #define DMAMUX_CSR_SOF0_Pos (0U) 1750 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ 1751 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ 1752 #define DMAMUX_CSR_SOF1_Pos (1U) 1753 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ 1754 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ 1755 #define DMAMUX_CSR_SOF2_Pos (2U) 1756 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ 1757 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ 1758 #define DMAMUX_CSR_SOF3_Pos (3U) 1759 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ 1760 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ 1761 #define DMAMUX_CSR_SOF4_Pos (4U) 1762 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ 1763 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ 1764 #define DMAMUX_CSR_SOF5_Pos (5U) 1765 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ 1766 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ 1767 #define DMAMUX_CSR_SOF6_Pos (6U) 1768 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ 1769 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ 1770 1771 /******************** Bits definition for DMAMUX_CFR register **************/ 1772 #define DMAMUX_CFR_CSOF0_Pos (0U) 1773 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ 1774 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ 1775 #define DMAMUX_CFR_CSOF1_Pos (1U) 1776 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ 1777 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ 1778 #define DMAMUX_CFR_CSOF2_Pos (2U) 1779 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ 1780 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ 1781 #define DMAMUX_CFR_CSOF3_Pos (3U) 1782 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ 1783 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ 1784 #define DMAMUX_CFR_CSOF4_Pos (4U) 1785 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ 1786 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ 1787 #define DMAMUX_CFR_CSOF5_Pos (5U) 1788 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ 1789 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ 1790 #define DMAMUX_CFR_CSOF6_Pos (6U) 1791 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ 1792 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ 1793 1794 /******************** Bits definition for DMAMUX_RGxCR register ************/ 1795 #define DMAMUX_RGxCR_SIG_ID_Pos (0U) 1796 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ 1797 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ 1798 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ 1799 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ 1800 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ 1801 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ 1802 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ 1803 #define DMAMUX_RGxCR_OIE_Pos (8U) 1804 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ 1805 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ 1806 #define DMAMUX_RGxCR_GE_Pos (16U) 1807 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ 1808 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ 1809 #define DMAMUX_RGxCR_GPOL_Pos (17U) 1810 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ 1811 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ 1812 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ 1813 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ 1814 #define DMAMUX_RGxCR_GNBREQ_Pos (19U) 1815 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ 1816 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ 1817 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ 1818 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ 1819 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ 1820 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ 1821 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ 1822 1823 /******************** Bits definition for DMAMUX_RGSR register **************/ 1824 #define DMAMUX_RGSR_OF0_Pos (0U) 1825 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ 1826 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ 1827 #define DMAMUX_RGSR_OF1_Pos (1U) 1828 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ 1829 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ 1830 #define DMAMUX_RGSR_OF2_Pos (2U) 1831 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ 1832 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ 1833 #define DMAMUX_RGSR_OF3_Pos (3U) 1834 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ 1835 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ 1836 1837 /******************** Bits definition for DMAMUX_RGCFR register **************/ 1838 #define DMAMUX_RGCFR_COF0_Pos (0U) 1839 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ 1840 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ 1841 #define DMAMUX_RGCFR_COF1_Pos (1U) 1842 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ 1843 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ 1844 #define DMAMUX_RGCFR_COF2_Pos (2U) 1845 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ 1846 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ 1847 #define DMAMUX_RGCFR_COF3_Pos (3U) 1848 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ 1849 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ 1850 1851 /******************************************************************************/ 1852 /* */ 1853 /* External Interrupt/Event Controller */ 1854 /* */ 1855 /******************************************************************************/ 1856 /****************** Bit definition for EXTI_RTSR1 register ******************/ 1857 #define EXTI_RTSR1_RT0_Pos (0U) 1858 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 1859 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ 1860 #define EXTI_RTSR1_RT1_Pos (1U) 1861 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 1862 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ 1863 #define EXTI_RTSR1_RT2_Pos (2U) 1864 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 1865 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ 1866 #define EXTI_RTSR1_RT3_Pos (3U) 1867 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 1868 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ 1869 #define EXTI_RTSR1_RT4_Pos (4U) 1870 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 1871 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ 1872 #define EXTI_RTSR1_RT5_Pos (5U) 1873 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 1874 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ 1875 #define EXTI_RTSR1_RT6_Pos (6U) 1876 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 1877 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ 1878 #define EXTI_RTSR1_RT7_Pos (7U) 1879 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 1880 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ 1881 #define EXTI_RTSR1_RT8_Pos (8U) 1882 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 1883 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ 1884 #define EXTI_RTSR1_RT9_Pos (9U) 1885 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 1886 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ 1887 #define EXTI_RTSR1_RT10_Pos (10U) 1888 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 1889 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ 1890 #define EXTI_RTSR1_RT11_Pos (11U) 1891 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 1892 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ 1893 #define EXTI_RTSR1_RT12_Pos (12U) 1894 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 1895 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ 1896 #define EXTI_RTSR1_RT13_Pos (13U) 1897 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 1898 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ 1899 #define EXTI_RTSR1_RT14_Pos (14U) 1900 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 1901 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ 1902 #define EXTI_RTSR1_RT15_Pos (15U) 1903 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 1904 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ 1905 1906 /****************** Bit definition for EXTI_FTSR1 register ******************/ 1907 #define EXTI_FTSR1_FT0_Pos (0U) 1908 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 1909 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ 1910 #define EXTI_FTSR1_FT1_Pos (1U) 1911 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 1912 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ 1913 #define EXTI_FTSR1_FT2_Pos (2U) 1914 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 1915 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ 1916 #define EXTI_FTSR1_FT3_Pos (3U) 1917 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 1918 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ 1919 #define EXTI_FTSR1_FT4_Pos (4U) 1920 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 1921 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ 1922 #define EXTI_FTSR1_FT5_Pos (5U) 1923 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 1924 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ 1925 #define EXTI_FTSR1_FT6_Pos (6U) 1926 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 1927 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ 1928 #define EXTI_FTSR1_FT7_Pos (7U) 1929 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 1930 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ 1931 #define EXTI_FTSR1_FT8_Pos (8U) 1932 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 1933 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ 1934 #define EXTI_FTSR1_FT9_Pos (9U) 1935 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 1936 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ 1937 #define EXTI_FTSR1_FT10_Pos (10U) 1938 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 1939 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ 1940 #define EXTI_FTSR1_FT11_Pos (11U) 1941 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 1942 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ 1943 #define EXTI_FTSR1_FT12_Pos (12U) 1944 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 1945 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ 1946 #define EXTI_FTSR1_FT13_Pos (13U) 1947 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 1948 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ 1949 #define EXTI_FTSR1_FT14_Pos (14U) 1950 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 1951 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ 1952 #define EXTI_FTSR1_FT15_Pos (15U) 1953 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 1954 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ 1955 1956 /****************** Bit definition for EXTI_SWIER1 register *****************/ 1957 #define EXTI_SWIER1_SWI0_Pos (0U) 1958 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 1959 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 1960 #define EXTI_SWIER1_SWI1_Pos (1U) 1961 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 1962 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 1963 #define EXTI_SWIER1_SWI2_Pos (2U) 1964 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 1965 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 1966 #define EXTI_SWIER1_SWI3_Pos (3U) 1967 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 1968 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 1969 #define EXTI_SWIER1_SWI4_Pos (4U) 1970 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 1971 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 1972 #define EXTI_SWIER1_SWI5_Pos (5U) 1973 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 1974 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 1975 #define EXTI_SWIER1_SWI6_Pos (6U) 1976 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 1977 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 1978 #define EXTI_SWIER1_SWI7_Pos (7U) 1979 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 1980 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 1981 #define EXTI_SWIER1_SWI8_Pos (8U) 1982 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 1983 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 1984 #define EXTI_SWIER1_SWI9_Pos (9U) 1985 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 1986 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 1987 #define EXTI_SWIER1_SWI10_Pos (10U) 1988 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 1989 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 1990 #define EXTI_SWIER1_SWI11_Pos (11U) 1991 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 1992 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 1993 #define EXTI_SWIER1_SWI12_Pos (12U) 1994 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 1995 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 1996 #define EXTI_SWIER1_SWI13_Pos (13U) 1997 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 1998 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 1999 #define EXTI_SWIER1_SWI14_Pos (14U) 2000 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 2001 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 2002 #define EXTI_SWIER1_SWI15_Pos (15U) 2003 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 2004 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 2005 2006 /******************* Bit definition for EXTI_RPR1 register ******************/ 2007 #define EXTI_RPR1_RPIF0_Pos (0U) 2008 #define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ 2009 #define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ 2010 #define EXTI_RPR1_RPIF1_Pos (1U) 2011 #define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ 2012 #define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ 2013 #define EXTI_RPR1_RPIF2_Pos (2U) 2014 #define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ 2015 #define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ 2016 #define EXTI_RPR1_RPIF3_Pos (3U) 2017 #define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ 2018 #define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ 2019 #define EXTI_RPR1_RPIF4_Pos (4U) 2020 #define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ 2021 #define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ 2022 #define EXTI_RPR1_RPIF5_Pos (5U) 2023 #define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ 2024 #define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ 2025 #define EXTI_RPR1_RPIF6_Pos (6U) 2026 #define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ 2027 #define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ 2028 #define EXTI_RPR1_RPIF7_Pos (7U) 2029 #define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ 2030 #define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ 2031 #define EXTI_RPR1_RPIF8_Pos (8U) 2032 #define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ 2033 #define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ 2034 #define EXTI_RPR1_RPIF9_Pos (9U) 2035 #define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ 2036 #define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ 2037 #define EXTI_RPR1_RPIF10_Pos (10U) 2038 #define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ 2039 #define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ 2040 #define EXTI_RPR1_RPIF11_Pos (11U) 2041 #define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ 2042 #define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ 2043 #define EXTI_RPR1_RPIF12_Pos (12U) 2044 #define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ 2045 #define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ 2046 #define EXTI_RPR1_RPIF13_Pos (13U) 2047 #define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ 2048 #define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ 2049 #define EXTI_RPR1_RPIF14_Pos (14U) 2050 #define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ 2051 #define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ 2052 #define EXTI_RPR1_RPIF15_Pos (15U) 2053 #define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ 2054 #define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ 2055 2056 /******************* Bit definition for EXTI_FPR1 register ******************/ 2057 #define EXTI_FPR1_FPIF0_Pos (0U) 2058 #define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ 2059 #define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ 2060 #define EXTI_FPR1_FPIF1_Pos (1U) 2061 #define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ 2062 #define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ 2063 #define EXTI_FPR1_FPIF2_Pos (2U) 2064 #define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ 2065 #define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ 2066 #define EXTI_FPR1_FPIF3_Pos (3U) 2067 #define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ 2068 #define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ 2069 #define EXTI_FPR1_FPIF4_Pos (4U) 2070 #define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ 2071 #define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ 2072 #define EXTI_FPR1_FPIF5_Pos (5U) 2073 #define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ 2074 #define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ 2075 #define EXTI_FPR1_FPIF6_Pos (6U) 2076 #define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ 2077 #define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ 2078 #define EXTI_FPR1_FPIF7_Pos (7U) 2079 #define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ 2080 #define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ 2081 #define EXTI_FPR1_FPIF8_Pos (8U) 2082 #define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ 2083 #define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ 2084 #define EXTI_FPR1_FPIF9_Pos (9U) 2085 #define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ 2086 #define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ 2087 #define EXTI_FPR1_FPIF10_Pos (10U) 2088 #define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ 2089 #define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ 2090 #define EXTI_FPR1_FPIF11_Pos (11U) 2091 #define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ 2092 #define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ 2093 #define EXTI_FPR1_FPIF12_Pos (12U) 2094 #define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ 2095 #define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ 2096 #define EXTI_FPR1_FPIF13_Pos (13U) 2097 #define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ 2098 #define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ 2099 #define EXTI_FPR1_FPIF14_Pos (14U) 2100 #define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ 2101 #define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ 2102 #define EXTI_FPR1_FPIF15_Pos (15U) 2103 #define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ 2104 #define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ 2105 2106 /***************** Bit definition for EXTI_EXTICR1 register **************/ 2107 #define EXTI_EXTICR1_EXTI0_Pos (0U) 2108 #define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ 2109 #define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 2110 #define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ 2111 #define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ 2112 #define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ 2113 #define EXTI_EXTICR1_EXTI1_Pos (8U) 2114 #define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ 2115 #define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 2116 #define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ 2117 #define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ 2118 #define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ 2119 #define EXTI_EXTICR1_EXTI2_Pos (16U) 2120 #define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ 2121 #define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 2122 #define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ 2123 #define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ 2124 #define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ 2125 #define EXTI_EXTICR1_EXTI3_Pos (24U) 2126 #define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ 2127 #define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 2128 #define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ 2129 #define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ 2130 #define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ 2131 2132 /***************** Bit definition for EXTI_EXTICR2 register **************/ 2133 #define EXTI_EXTICR2_EXTI4_Pos (0U) 2134 #define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ 2135 #define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 2136 #define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ 2137 #define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ 2138 #define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ 2139 #define EXTI_EXTICR2_EXTI5_Pos (8U) 2140 #define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ 2141 #define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 2142 #define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ 2143 #define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ 2144 #define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ 2145 #define EXTI_EXTICR2_EXTI6_Pos (16U) 2146 #define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ 2147 #define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 2148 #define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ 2149 #define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ 2150 #define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ 2151 #define EXTI_EXTICR2_EXTI7_Pos (24U) 2152 #define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ 2153 #define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 2154 #define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ 2155 #define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ 2156 #define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ 2157 2158 /***************** Bit definition for EXTI_EXTICR3 register **************/ 2159 #define EXTI_EXTICR3_EXTI8_Pos (0U) 2160 #define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ 2161 #define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 2162 #define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ 2163 #define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ 2164 #define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ 2165 #define EXTI_EXTICR3_EXTI9_Pos (8U) 2166 #define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ 2167 #define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 2168 #define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ 2169 #define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ 2170 #define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ 2171 #define EXTI_EXTICR3_EXTI10_Pos (16U) 2172 #define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ 2173 #define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 2174 #define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ 2175 #define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ 2176 #define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ 2177 #define EXTI_EXTICR3_EXTI11_Pos (24U) 2178 #define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ 2179 #define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 2180 #define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ 2181 #define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ 2182 #define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ 2183 2184 /***************** Bit definition for EXTI_EXTICR4 register **************/ 2185 #define EXTI_EXTICR4_EXTI12_Pos (0U) 2186 #define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 2187 #define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 2188 #define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ 2189 #define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ 2190 #define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ 2191 #define EXTI_EXTICR4_EXTI13_Pos (8U) 2192 #define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ 2193 #define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 2194 #define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ 2195 #define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ 2196 #define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ 2197 #define EXTI_EXTICR4_EXTI14_Pos (16U) 2198 #define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ 2199 #define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 2200 #define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ 2201 #define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ 2202 #define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ 2203 #define EXTI_EXTICR4_EXTI15_Pos (24U) 2204 #define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ 2205 #define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 2206 #define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ 2207 #define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ 2208 #define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ 2209 2210 /******************* Bit definition for EXTI_IMR1 register ******************/ 2211 #define EXTI_IMR1_IM0_Pos (0U) 2212 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 2213 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ 2214 #define EXTI_IMR1_IM1_Pos (1U) 2215 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 2216 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ 2217 #define EXTI_IMR1_IM2_Pos (2U) 2218 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 2219 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ 2220 #define EXTI_IMR1_IM3_Pos (3U) 2221 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 2222 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ 2223 #define EXTI_IMR1_IM4_Pos (4U) 2224 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 2225 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ 2226 #define EXTI_IMR1_IM5_Pos (5U) 2227 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 2228 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ 2229 #define EXTI_IMR1_IM6_Pos (6U) 2230 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 2231 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ 2232 #define EXTI_IMR1_IM7_Pos (7U) 2233 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 2234 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ 2235 #define EXTI_IMR1_IM8_Pos (8U) 2236 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 2237 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ 2238 #define EXTI_IMR1_IM9_Pos (9U) 2239 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 2240 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ 2241 #define EXTI_IMR1_IM10_Pos (10U) 2242 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 2243 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ 2244 #define EXTI_IMR1_IM11_Pos (11U) 2245 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 2246 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ 2247 #define EXTI_IMR1_IM12_Pos (12U) 2248 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 2249 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ 2250 #define EXTI_IMR1_IM13_Pos (13U) 2251 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 2252 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ 2253 #define EXTI_IMR1_IM14_Pos (14U) 2254 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 2255 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ 2256 #define EXTI_IMR1_IM15_Pos (15U) 2257 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 2258 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ 2259 #define EXTI_IMR1_IM19_Pos (19U) 2260 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 2261 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ 2262 #define EXTI_IMR1_IM21_Pos (21U) 2263 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ 2264 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ 2265 #define EXTI_IMR1_IM23_Pos (23U) 2266 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 2267 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ 2268 #define EXTI_IMR1_IM25_Pos (25U) 2269 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 2270 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ 2271 #define EXTI_IMR1_IM31_Pos (31U) 2272 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ 2273 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ 2274 #define EXTI_IMR1_IM_Pos (0U) 2275 #define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x82A8FFFF */ 2276 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ 2277 2278 2279 /******************* Bit definition for EXTI_EMR1 register ******************/ 2280 #define EXTI_EMR1_EM0_Pos (0U) 2281 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 2282 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ 2283 #define EXTI_EMR1_EM1_Pos (1U) 2284 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 2285 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ 2286 #define EXTI_EMR1_EM2_Pos (2U) 2287 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 2288 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ 2289 #define EXTI_EMR1_EM3_Pos (3U) 2290 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 2291 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ 2292 #define EXTI_EMR1_EM4_Pos (4U) 2293 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 2294 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ 2295 #define EXTI_EMR1_EM5_Pos (5U) 2296 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 2297 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ 2298 #define EXTI_EMR1_EM6_Pos (6U) 2299 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 2300 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ 2301 #define EXTI_EMR1_EM7_Pos (7U) 2302 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 2303 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ 2304 #define EXTI_EMR1_EM8_Pos (8U) 2305 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 2306 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ 2307 #define EXTI_EMR1_EM9_Pos (9U) 2308 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 2309 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ 2310 #define EXTI_EMR1_EM10_Pos (10U) 2311 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 2312 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ 2313 #define EXTI_EMR1_EM11_Pos (11U) 2314 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 2315 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ 2316 #define EXTI_EMR1_EM12_Pos (12U) 2317 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 2318 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ 2319 #define EXTI_EMR1_EM13_Pos (13U) 2320 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 2321 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ 2322 #define EXTI_EMR1_EM14_Pos (14U) 2323 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 2324 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ 2325 #define EXTI_EMR1_EM15_Pos (15U) 2326 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 2327 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ 2328 #define EXTI_EMR1_EM19_Pos (19U) 2329 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 2330 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ 2331 #define EXTI_EMR1_EM21_Pos (21U) 2332 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ 2333 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ 2334 #define EXTI_EMR1_EM23_Pos (23U) 2335 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ 2336 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ 2337 #define EXTI_EMR1_EM25_Pos (25U) 2338 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ 2339 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ 2340 #define EXTI_EMR1_EM31_Pos (31U) 2341 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ 2342 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ 2343 2344 2345 /******************************************************************************/ 2346 /* */ 2347 /* FLASH */ 2348 /* */ 2349 /******************************************************************************/ 2350 /* Note: No specific macro feature on this device */ 2351 2352 /******************* Bits definition for FLASH_ACR register *****************/ 2353 #define FLASH_ACR_LATENCY_Pos (0U) 2354 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 2355 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 2356 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2357 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 2358 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 2359 #define FLASH_ACR_PRFTEN_Pos (8U) 2360 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 2361 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 2362 #define FLASH_ACR_ICEN_Pos (9U) 2363 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 2364 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk 2365 #define FLASH_ACR_ICRST_Pos (11U) 2366 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 2367 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk 2368 #define FLASH_ACR_PROGEMPTY_Pos (16U) 2369 #define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ 2370 #define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk 2371 2372 /******************* Bits definition for FLASH_SR register ******************/ 2373 #define FLASH_SR_EOP_Pos (0U) 2374 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 2375 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 2376 #define FLASH_SR_OPERR_Pos (1U) 2377 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 2378 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk 2379 #define FLASH_SR_PROGERR_Pos (3U) 2380 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 2381 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk 2382 #define FLASH_SR_WRPERR_Pos (4U) 2383 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 2384 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 2385 #define FLASH_SR_PGAERR_Pos (5U) 2386 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 2387 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 2388 #define FLASH_SR_SIZERR_Pos (6U) 2389 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 2390 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk 2391 #define FLASH_SR_PGSERR_Pos (7U) 2392 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 2393 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk 2394 #define FLASH_SR_MISERR_Pos (8U) 2395 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 2396 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk 2397 #define FLASH_SR_FASTERR_Pos (9U) 2398 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 2399 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk 2400 #define FLASH_SR_OPTVERR_Pos (15U) 2401 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 2402 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk 2403 #define FLASH_SR_BSY1_Pos (16U) 2404 #define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ 2405 #define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk 2406 #define FLASH_SR_CFGBSY_Pos (18U) 2407 #define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ 2408 #define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk 2409 2410 /******************* Bits definition for FLASH_CR register ******************/ 2411 #define FLASH_CR_PG_Pos (0U) 2412 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 2413 #define FLASH_CR_PG FLASH_CR_PG_Msk 2414 #define FLASH_CR_PER_Pos (1U) 2415 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 2416 #define FLASH_CR_PER FLASH_CR_PER_Msk 2417 #define FLASH_CR_MER1_Pos (2U) 2418 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ 2419 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk 2420 #define FLASH_CR_PNB_Pos (3U) 2421 #define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */ 2422 #define FLASH_CR_PNB FLASH_CR_PNB_Msk 2423 #define FLASH_CR_STRT_Pos (16U) 2424 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 2425 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 2426 #define FLASH_CR_OPTSTRT_Pos (17U) 2427 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 2428 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk 2429 #define FLASH_CR_FSTPG_Pos (18U) 2430 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 2431 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk 2432 #define FLASH_CR_EOPIE_Pos (24U) 2433 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 2434 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 2435 #define FLASH_CR_ERRIE_Pos (25U) 2436 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 2437 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk 2438 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 2439 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 2440 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk 2441 #define FLASH_CR_OPTLOCK_Pos (30U) 2442 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 2443 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk 2444 #define FLASH_CR_LOCK_Pos (31U) 2445 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 2446 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 2447 2448 /******************* Bits definition for FLASH_ECCR register ****************/ 2449 #define FLASH_ECCR_ADDR_ECC_Pos (0U) 2450 #define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ 2451 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk 2452 #define FLASH_ECCR_SYSF_ECC_Pos (20U) 2453 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ 2454 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk 2455 #define FLASH_ECCR_ECCCIE_Pos (24U) 2456 #define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ 2457 #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk 2458 #define FLASH_ECCR_ECCC_Pos (30U) 2459 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ 2460 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk 2461 #define FLASH_ECCR_ECCD_Pos (31U) 2462 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ 2463 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk 2464 2465 /******************* Bits definition for FLASH_OPTR register ****************/ 2466 #define FLASH_OPTR_RDP_Pos (0U) 2467 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 2468 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk 2469 #define FLASH_OPTR_nRST_STOP_Pos (13U) 2470 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ 2471 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk 2472 #define FLASH_OPTR_nRST_STDBY_Pos (14U) 2473 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ 2474 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk 2475 #define FLASH_OPTR_IWDG_SW_Pos (16U) 2476 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 2477 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk 2478 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 2479 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ 2480 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk 2481 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 2482 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ 2483 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk 2484 #define FLASH_OPTR_WWDG_SW_Pos (19U) 2485 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 2486 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk 2487 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) 2488 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ 2489 #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk 2490 #define FLASH_OPTR_nBOOT_SEL_Pos (24U) 2491 #define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ 2492 #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk 2493 #define FLASH_OPTR_nBOOT1_Pos (25U) 2494 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ 2495 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk 2496 #define FLASH_OPTR_nBOOT0_Pos (26U) 2497 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ 2498 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk 2499 2500 /****************** Bits definition for FLASH_WRP1AR register ***************/ 2501 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 2502 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ 2503 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk 2504 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 2505 #define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ 2506 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk 2507 2508 /****************** Bits definition for FLASH_WRP1BR register ***************/ 2509 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 2510 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ 2511 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk 2512 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 2513 #define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ 2514 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk 2515 2516 2517 /******************************************************************************/ 2518 /* */ 2519 /* General Purpose I/O */ 2520 /* */ 2521 /******************************************************************************/ 2522 /****************** Bits definition for GPIO_MODER register *****************/ 2523 #define GPIO_MODER_MODE0_Pos (0U) 2524 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 2525 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 2526 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 2527 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 2528 #define GPIO_MODER_MODE1_Pos (2U) 2529 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 2530 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 2531 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 2532 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 2533 #define GPIO_MODER_MODE2_Pos (4U) 2534 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 2535 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 2536 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 2537 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 2538 #define GPIO_MODER_MODE3_Pos (6U) 2539 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 2540 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 2541 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 2542 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 2543 #define GPIO_MODER_MODE4_Pos (8U) 2544 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 2545 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 2546 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 2547 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 2548 #define GPIO_MODER_MODE5_Pos (10U) 2549 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 2550 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 2551 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 2552 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 2553 #define GPIO_MODER_MODE6_Pos (12U) 2554 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 2555 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 2556 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 2557 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 2558 #define GPIO_MODER_MODE7_Pos (14U) 2559 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 2560 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 2561 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 2562 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 2563 #define GPIO_MODER_MODE8_Pos (16U) 2564 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 2565 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 2566 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 2567 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 2568 #define GPIO_MODER_MODE9_Pos (18U) 2569 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 2570 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 2571 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 2572 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 2573 #define GPIO_MODER_MODE10_Pos (20U) 2574 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 2575 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 2576 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 2577 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 2578 #define GPIO_MODER_MODE11_Pos (22U) 2579 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 2580 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 2581 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 2582 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 2583 #define GPIO_MODER_MODE12_Pos (24U) 2584 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 2585 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 2586 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 2587 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 2588 #define GPIO_MODER_MODE13_Pos (26U) 2589 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 2590 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 2591 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 2592 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 2593 #define GPIO_MODER_MODE14_Pos (28U) 2594 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 2595 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 2596 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 2597 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 2598 #define GPIO_MODER_MODE15_Pos (30U) 2599 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 2600 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 2601 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 2602 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 2603 2604 /****************** Bits definition for GPIO_OTYPER register ****************/ 2605 #define GPIO_OTYPER_OT0_Pos (0U) 2606 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 2607 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 2608 #define GPIO_OTYPER_OT1_Pos (1U) 2609 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 2610 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 2611 #define GPIO_OTYPER_OT2_Pos (2U) 2612 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 2613 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 2614 #define GPIO_OTYPER_OT3_Pos (3U) 2615 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 2616 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 2617 #define GPIO_OTYPER_OT4_Pos (4U) 2618 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 2619 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 2620 #define GPIO_OTYPER_OT5_Pos (5U) 2621 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 2622 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 2623 #define GPIO_OTYPER_OT6_Pos (6U) 2624 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 2625 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 2626 #define GPIO_OTYPER_OT7_Pos (7U) 2627 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 2628 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 2629 #define GPIO_OTYPER_OT8_Pos (8U) 2630 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 2631 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 2632 #define GPIO_OTYPER_OT9_Pos (9U) 2633 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 2634 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 2635 #define GPIO_OTYPER_OT10_Pos (10U) 2636 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 2637 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 2638 #define GPIO_OTYPER_OT11_Pos (11U) 2639 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 2640 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 2641 #define GPIO_OTYPER_OT12_Pos (12U) 2642 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 2643 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 2644 #define GPIO_OTYPER_OT13_Pos (13U) 2645 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 2646 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 2647 #define GPIO_OTYPER_OT14_Pos (14U) 2648 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 2649 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 2650 #define GPIO_OTYPER_OT15_Pos (15U) 2651 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 2652 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 2653 2654 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 2655 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 2656 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 2657 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 2658 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 2659 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 2660 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 2661 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 2662 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 2663 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 2664 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 2665 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 2666 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 2667 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 2668 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 2669 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 2670 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 2671 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 2672 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 2673 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 2674 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 2675 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 2676 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 2677 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 2678 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 2679 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 2680 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 2681 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 2682 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 2683 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 2684 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 2685 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 2686 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 2687 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 2688 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 2689 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 2690 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 2691 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 2692 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 2693 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 2694 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 2695 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 2696 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 2697 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 2698 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 2699 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 2700 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 2701 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 2702 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 2703 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 2704 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 2705 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 2706 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 2707 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 2708 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 2709 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 2710 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 2711 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 2712 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 2713 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 2714 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 2715 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 2716 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 2717 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 2718 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 2719 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 2720 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 2721 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 2722 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 2723 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 2724 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 2725 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 2726 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 2727 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 2728 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 2729 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 2730 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 2731 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 2732 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 2733 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 2734 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 2735 2736 /****************** Bits definition for GPIO_PUPDR register *****************/ 2737 #define GPIO_PUPDR_PUPD0_Pos (0U) 2738 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 2739 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 2740 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 2741 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 2742 #define GPIO_PUPDR_PUPD1_Pos (2U) 2743 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 2744 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 2745 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 2746 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 2747 #define GPIO_PUPDR_PUPD2_Pos (4U) 2748 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 2749 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 2750 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 2751 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 2752 #define GPIO_PUPDR_PUPD3_Pos (6U) 2753 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 2754 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 2755 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 2756 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 2757 #define GPIO_PUPDR_PUPD4_Pos (8U) 2758 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 2759 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 2760 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 2761 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 2762 #define GPIO_PUPDR_PUPD5_Pos (10U) 2763 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 2764 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 2765 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 2766 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 2767 #define GPIO_PUPDR_PUPD6_Pos (12U) 2768 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 2769 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 2770 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 2771 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 2772 #define GPIO_PUPDR_PUPD7_Pos (14U) 2773 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 2774 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 2775 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 2776 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 2777 #define GPIO_PUPDR_PUPD8_Pos (16U) 2778 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 2779 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 2780 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 2781 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 2782 #define GPIO_PUPDR_PUPD9_Pos (18U) 2783 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 2784 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 2785 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 2786 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 2787 #define GPIO_PUPDR_PUPD10_Pos (20U) 2788 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 2789 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 2790 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 2791 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 2792 #define GPIO_PUPDR_PUPD11_Pos (22U) 2793 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 2794 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 2795 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 2796 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 2797 #define GPIO_PUPDR_PUPD12_Pos (24U) 2798 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 2799 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 2800 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 2801 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 2802 #define GPIO_PUPDR_PUPD13_Pos (26U) 2803 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 2804 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 2805 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 2806 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 2807 #define GPIO_PUPDR_PUPD14_Pos (28U) 2808 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 2809 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 2810 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 2811 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 2812 #define GPIO_PUPDR_PUPD15_Pos (30U) 2813 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 2814 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 2815 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 2816 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 2817 2818 /****************** Bits definition for GPIO_IDR register *******************/ 2819 #define GPIO_IDR_ID0_Pos (0U) 2820 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 2821 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 2822 #define GPIO_IDR_ID1_Pos (1U) 2823 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 2824 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 2825 #define GPIO_IDR_ID2_Pos (2U) 2826 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 2827 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 2828 #define GPIO_IDR_ID3_Pos (3U) 2829 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 2830 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 2831 #define GPIO_IDR_ID4_Pos (4U) 2832 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 2833 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 2834 #define GPIO_IDR_ID5_Pos (5U) 2835 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 2836 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 2837 #define GPIO_IDR_ID6_Pos (6U) 2838 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 2839 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 2840 #define GPIO_IDR_ID7_Pos (7U) 2841 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 2842 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 2843 #define GPIO_IDR_ID8_Pos (8U) 2844 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 2845 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 2846 #define GPIO_IDR_ID9_Pos (9U) 2847 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 2848 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 2849 #define GPIO_IDR_ID10_Pos (10U) 2850 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 2851 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 2852 #define GPIO_IDR_ID11_Pos (11U) 2853 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 2854 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 2855 #define GPIO_IDR_ID12_Pos (12U) 2856 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 2857 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 2858 #define GPIO_IDR_ID13_Pos (13U) 2859 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 2860 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 2861 #define GPIO_IDR_ID14_Pos (14U) 2862 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 2863 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 2864 #define GPIO_IDR_ID15_Pos (15U) 2865 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 2866 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 2867 2868 /****************** Bits definition for GPIO_ODR register *******************/ 2869 #define GPIO_ODR_OD0_Pos (0U) 2870 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 2871 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 2872 #define GPIO_ODR_OD1_Pos (1U) 2873 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 2874 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 2875 #define GPIO_ODR_OD2_Pos (2U) 2876 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 2877 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 2878 #define GPIO_ODR_OD3_Pos (3U) 2879 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 2880 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 2881 #define GPIO_ODR_OD4_Pos (4U) 2882 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 2883 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 2884 #define GPIO_ODR_OD5_Pos (5U) 2885 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 2886 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 2887 #define GPIO_ODR_OD6_Pos (6U) 2888 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 2889 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 2890 #define GPIO_ODR_OD7_Pos (7U) 2891 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 2892 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 2893 #define GPIO_ODR_OD8_Pos (8U) 2894 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 2895 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 2896 #define GPIO_ODR_OD9_Pos (9U) 2897 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 2898 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 2899 #define GPIO_ODR_OD10_Pos (10U) 2900 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 2901 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 2902 #define GPIO_ODR_OD11_Pos (11U) 2903 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 2904 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 2905 #define GPIO_ODR_OD12_Pos (12U) 2906 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 2907 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 2908 #define GPIO_ODR_OD13_Pos (13U) 2909 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 2910 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 2911 #define GPIO_ODR_OD14_Pos (14U) 2912 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 2913 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 2914 #define GPIO_ODR_OD15_Pos (15U) 2915 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 2916 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 2917 2918 /****************** Bits definition for GPIO_BSRR register ******************/ 2919 #define GPIO_BSRR_BS0_Pos (0U) 2920 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 2921 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 2922 #define GPIO_BSRR_BS1_Pos (1U) 2923 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 2924 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 2925 #define GPIO_BSRR_BS2_Pos (2U) 2926 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 2927 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 2928 #define GPIO_BSRR_BS3_Pos (3U) 2929 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 2930 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 2931 #define GPIO_BSRR_BS4_Pos (4U) 2932 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 2933 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 2934 #define GPIO_BSRR_BS5_Pos (5U) 2935 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 2936 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 2937 #define GPIO_BSRR_BS6_Pos (6U) 2938 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 2939 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 2940 #define GPIO_BSRR_BS7_Pos (7U) 2941 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 2942 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 2943 #define GPIO_BSRR_BS8_Pos (8U) 2944 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 2945 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 2946 #define GPIO_BSRR_BS9_Pos (9U) 2947 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 2948 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 2949 #define GPIO_BSRR_BS10_Pos (10U) 2950 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 2951 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 2952 #define GPIO_BSRR_BS11_Pos (11U) 2953 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 2954 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 2955 #define GPIO_BSRR_BS12_Pos (12U) 2956 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 2957 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 2958 #define GPIO_BSRR_BS13_Pos (13U) 2959 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 2960 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 2961 #define GPIO_BSRR_BS14_Pos (14U) 2962 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 2963 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 2964 #define GPIO_BSRR_BS15_Pos (15U) 2965 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 2966 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 2967 #define GPIO_BSRR_BR0_Pos (16U) 2968 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 2969 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 2970 #define GPIO_BSRR_BR1_Pos (17U) 2971 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 2972 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 2973 #define GPIO_BSRR_BR2_Pos (18U) 2974 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 2975 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 2976 #define GPIO_BSRR_BR3_Pos (19U) 2977 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 2978 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 2979 #define GPIO_BSRR_BR4_Pos (20U) 2980 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 2981 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 2982 #define GPIO_BSRR_BR5_Pos (21U) 2983 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 2984 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 2985 #define GPIO_BSRR_BR6_Pos (22U) 2986 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 2987 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 2988 #define GPIO_BSRR_BR7_Pos (23U) 2989 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 2990 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 2991 #define GPIO_BSRR_BR8_Pos (24U) 2992 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 2993 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 2994 #define GPIO_BSRR_BR9_Pos (25U) 2995 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 2996 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 2997 #define GPIO_BSRR_BR10_Pos (26U) 2998 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 2999 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 3000 #define GPIO_BSRR_BR11_Pos (27U) 3001 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 3002 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 3003 #define GPIO_BSRR_BR12_Pos (28U) 3004 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 3005 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 3006 #define GPIO_BSRR_BR13_Pos (29U) 3007 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 3008 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 3009 #define GPIO_BSRR_BR14_Pos (30U) 3010 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 3011 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 3012 #define GPIO_BSRR_BR15_Pos (31U) 3013 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 3014 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 3015 3016 /****************** Bit definition for GPIO_LCKR register *********************/ 3017 #define GPIO_LCKR_LCK0_Pos (0U) 3018 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 3019 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 3020 #define GPIO_LCKR_LCK1_Pos (1U) 3021 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 3022 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 3023 #define GPIO_LCKR_LCK2_Pos (2U) 3024 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 3025 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 3026 #define GPIO_LCKR_LCK3_Pos (3U) 3027 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 3028 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 3029 #define GPIO_LCKR_LCK4_Pos (4U) 3030 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3031 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3032 #define GPIO_LCKR_LCK5_Pos (5U) 3033 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3034 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3035 #define GPIO_LCKR_LCK6_Pos (6U) 3036 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3037 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3038 #define GPIO_LCKR_LCK7_Pos (7U) 3039 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3040 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3041 #define GPIO_LCKR_LCK8_Pos (8U) 3042 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3043 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3044 #define GPIO_LCKR_LCK9_Pos (9U) 3045 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3046 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3047 #define GPIO_LCKR_LCK10_Pos (10U) 3048 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3049 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3050 #define GPIO_LCKR_LCK11_Pos (11U) 3051 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3052 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3053 #define GPIO_LCKR_LCK12_Pos (12U) 3054 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3055 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3056 #define GPIO_LCKR_LCK13_Pos (13U) 3057 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3058 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3059 #define GPIO_LCKR_LCK14_Pos (14U) 3060 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3061 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3062 #define GPIO_LCKR_LCK15_Pos (15U) 3063 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3064 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3065 #define GPIO_LCKR_LCKK_Pos (16U) 3066 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3067 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3068 3069 /****************** Bit definition for GPIO_AFRL register *********************/ 3070 #define GPIO_AFRL_AFSEL0_Pos (0U) 3071 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3072 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3073 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 3074 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 3075 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 3076 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 3077 #define GPIO_AFRL_AFSEL1_Pos (4U) 3078 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3079 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3080 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 3081 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 3082 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 3083 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 3084 #define GPIO_AFRL_AFSEL2_Pos (8U) 3085 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3086 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3087 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 3088 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 3089 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 3090 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 3091 #define GPIO_AFRL_AFSEL3_Pos (12U) 3092 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3093 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3094 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 3095 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 3096 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 3097 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 3098 #define GPIO_AFRL_AFSEL4_Pos (16U) 3099 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3100 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3101 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 3102 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 3103 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 3104 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 3105 #define GPIO_AFRL_AFSEL5_Pos (20U) 3106 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3107 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3108 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 3109 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 3110 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 3111 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 3112 #define GPIO_AFRL_AFSEL6_Pos (24U) 3113 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3114 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3115 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 3116 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 3117 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 3118 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 3119 #define GPIO_AFRL_AFSEL7_Pos (28U) 3120 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3121 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3122 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 3123 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 3124 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 3125 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 3126 3127 /****************** Bit definition for GPIO_AFRH register *********************/ 3128 #define GPIO_AFRH_AFSEL8_Pos (0U) 3129 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3130 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3131 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 3132 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 3133 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 3134 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 3135 #define GPIO_AFRH_AFSEL9_Pos (4U) 3136 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3137 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3138 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 3139 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 3140 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 3141 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 3142 #define GPIO_AFRH_AFSEL10_Pos (8U) 3143 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3144 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3145 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 3146 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 3147 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 3148 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 3149 #define GPIO_AFRH_AFSEL11_Pos (12U) 3150 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3151 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3152 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 3153 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 3154 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 3155 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 3156 #define GPIO_AFRH_AFSEL12_Pos (16U) 3157 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3158 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3159 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 3160 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 3161 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 3162 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 3163 #define GPIO_AFRH_AFSEL13_Pos (20U) 3164 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3165 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3166 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 3167 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 3168 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 3169 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 3170 #define GPIO_AFRH_AFSEL14_Pos (24U) 3171 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3172 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3173 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 3174 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 3175 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 3176 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 3177 #define GPIO_AFRH_AFSEL15_Pos (28U) 3178 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3179 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3180 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 3181 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 3182 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 3183 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 3184 3185 /****************** Bits definition for GPIO_BRR register ******************/ 3186 #define GPIO_BRR_BR0_Pos (0U) 3187 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 3188 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 3189 #define GPIO_BRR_BR1_Pos (1U) 3190 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 3191 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 3192 #define GPIO_BRR_BR2_Pos (2U) 3193 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 3194 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 3195 #define GPIO_BRR_BR3_Pos (3U) 3196 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 3197 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 3198 #define GPIO_BRR_BR4_Pos (4U) 3199 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 3200 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 3201 #define GPIO_BRR_BR5_Pos (5U) 3202 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 3203 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 3204 #define GPIO_BRR_BR6_Pos (6U) 3205 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 3206 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 3207 #define GPIO_BRR_BR7_Pos (7U) 3208 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 3209 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 3210 #define GPIO_BRR_BR8_Pos (8U) 3211 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 3212 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 3213 #define GPIO_BRR_BR9_Pos (9U) 3214 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 3215 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 3216 #define GPIO_BRR_BR10_Pos (10U) 3217 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 3218 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 3219 #define GPIO_BRR_BR11_Pos (11U) 3220 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 3221 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 3222 #define GPIO_BRR_BR12_Pos (12U) 3223 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 3224 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 3225 #define GPIO_BRR_BR13_Pos (13U) 3226 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 3227 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 3228 #define GPIO_BRR_BR14_Pos (14U) 3229 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 3230 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 3231 #define GPIO_BRR_BR15_Pos (15U) 3232 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 3233 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 3234 3235 3236 /******************************************************************************/ 3237 /* */ 3238 /* Inter-integrated Circuit Interface (I2C) */ 3239 /* */ 3240 /******************************************************************************/ 3241 /******************* Bit definition for I2C_CR1 register *******************/ 3242 #define I2C_CR1_PE_Pos (0U) 3243 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3244 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 3245 #define I2C_CR1_TXIE_Pos (1U) 3246 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 3247 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 3248 #define I2C_CR1_RXIE_Pos (2U) 3249 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 3250 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 3251 #define I2C_CR1_ADDRIE_Pos (3U) 3252 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 3253 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 3254 #define I2C_CR1_NACKIE_Pos (4U) 3255 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 3256 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 3257 #define I2C_CR1_STOPIE_Pos (5U) 3258 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 3259 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 3260 #define I2C_CR1_TCIE_Pos (6U) 3261 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 3262 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 3263 #define I2C_CR1_ERRIE_Pos (7U) 3264 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 3265 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 3266 #define I2C_CR1_DNF_Pos (8U) 3267 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 3268 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 3269 #define I2C_CR1_ANFOFF_Pos (12U) 3270 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 3271 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 3272 #define I2C_CR1_SWRST_Pos (13U) 3273 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 3274 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 3275 #define I2C_CR1_TXDMAEN_Pos (14U) 3276 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 3277 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 3278 #define I2C_CR1_RXDMAEN_Pos (15U) 3279 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 3280 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 3281 #define I2C_CR1_SBC_Pos (16U) 3282 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 3283 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 3284 #define I2C_CR1_NOSTRETCH_Pos (17U) 3285 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 3286 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 3287 #define I2C_CR1_WUPEN_Pos (18U) 3288 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 3289 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 3290 #define I2C_CR1_GCEN_Pos (19U) 3291 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 3292 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 3293 #define I2C_CR1_SMBHEN_Pos (20U) 3294 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 3295 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 3296 #define I2C_CR1_SMBDEN_Pos (21U) 3297 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 3298 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 3299 #define I2C_CR1_ALERTEN_Pos (22U) 3300 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 3301 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 3302 #define I2C_CR1_PECEN_Pos (23U) 3303 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 3304 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 3305 3306 /****************** Bit definition for I2C_CR2 register ********************/ 3307 #define I2C_CR2_SADD_Pos (0U) 3308 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 3309 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 3310 #define I2C_CR2_RD_WRN_Pos (10U) 3311 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 3312 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 3313 #define I2C_CR2_ADD10_Pos (11U) 3314 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 3315 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 3316 #define I2C_CR2_HEAD10R_Pos (12U) 3317 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 3318 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 3319 #define I2C_CR2_START_Pos (13U) 3320 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 3321 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 3322 #define I2C_CR2_STOP_Pos (14U) 3323 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 3324 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 3325 #define I2C_CR2_NACK_Pos (15U) 3326 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 3327 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 3328 #define I2C_CR2_NBYTES_Pos (16U) 3329 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 3330 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 3331 #define I2C_CR2_RELOAD_Pos (24U) 3332 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 3333 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 3334 #define I2C_CR2_AUTOEND_Pos (25U) 3335 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 3336 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 3337 #define I2C_CR2_PECBYTE_Pos (26U) 3338 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 3339 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 3340 3341 /******************* Bit definition for I2C_OAR1 register ******************/ 3342 #define I2C_OAR1_OA1_Pos (0U) 3343 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 3344 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 3345 #define I2C_OAR1_OA1MODE_Pos (10U) 3346 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 3347 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 3348 #define I2C_OAR1_OA1EN_Pos (15U) 3349 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 3350 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 3351 3352 /******************* Bit definition for I2C_OAR2 register ******************/ 3353 #define I2C_OAR2_OA2_Pos (1U) 3354 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 3355 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 3356 #define I2C_OAR2_OA2MSK_Pos (8U) 3357 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 3358 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 3359 #define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ 3360 #define I2C_OAR2_OA2MASK01_Pos (8U) 3361 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 3362 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 3363 #define I2C_OAR2_OA2MASK02_Pos (9U) 3364 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 3365 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 3366 #define I2C_OAR2_OA2MASK03_Pos (8U) 3367 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 3368 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 3369 #define I2C_OAR2_OA2MASK04_Pos (10U) 3370 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 3371 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 3372 #define I2C_OAR2_OA2MASK05_Pos (8U) 3373 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 3374 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 3375 #define I2C_OAR2_OA2MASK06_Pos (9U) 3376 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 3377 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 3378 #define I2C_OAR2_OA2MASK07_Pos (8U) 3379 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 3380 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 3381 #define I2C_OAR2_OA2EN_Pos (15U) 3382 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 3383 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 3384 3385 /******************* Bit definition for I2C_TIMINGR register *******************/ 3386 #define I2C_TIMINGR_SCLL_Pos (0U) 3387 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 3388 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 3389 #define I2C_TIMINGR_SCLH_Pos (8U) 3390 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 3391 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 3392 #define I2C_TIMINGR_SDADEL_Pos (16U) 3393 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 3394 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 3395 #define I2C_TIMINGR_SCLDEL_Pos (20U) 3396 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 3397 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 3398 #define I2C_TIMINGR_PRESC_Pos (28U) 3399 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 3400 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 3401 3402 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 3403 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 3404 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 3405 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 3406 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 3407 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 3408 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 3409 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 3410 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 3411 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 3412 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 3413 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 3414 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 3415 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 3416 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 3417 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 3418 3419 /****************** Bit definition for I2C_ISR register *********************/ 3420 #define I2C_ISR_TXE_Pos (0U) 3421 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 3422 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 3423 #define I2C_ISR_TXIS_Pos (1U) 3424 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 3425 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 3426 #define I2C_ISR_RXNE_Pos (2U) 3427 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 3428 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 3429 #define I2C_ISR_ADDR_Pos (3U) 3430 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 3431 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 3432 #define I2C_ISR_NACKF_Pos (4U) 3433 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 3434 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 3435 #define I2C_ISR_STOPF_Pos (5U) 3436 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 3437 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 3438 #define I2C_ISR_TC_Pos (6U) 3439 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 3440 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 3441 #define I2C_ISR_TCR_Pos (7U) 3442 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 3443 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 3444 #define I2C_ISR_BERR_Pos (8U) 3445 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 3446 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 3447 #define I2C_ISR_ARLO_Pos (9U) 3448 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 3449 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 3450 #define I2C_ISR_OVR_Pos (10U) 3451 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 3452 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 3453 #define I2C_ISR_PECERR_Pos (11U) 3454 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 3455 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 3456 #define I2C_ISR_TIMEOUT_Pos (12U) 3457 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 3458 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 3459 #define I2C_ISR_ALERT_Pos (13U) 3460 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 3461 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 3462 #define I2C_ISR_BUSY_Pos (15U) 3463 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 3464 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 3465 #define I2C_ISR_DIR_Pos (16U) 3466 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 3467 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 3468 #define I2C_ISR_ADDCODE_Pos (17U) 3469 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 3470 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 3471 3472 /****************** Bit definition for I2C_ICR register *********************/ 3473 #define I2C_ICR_ADDRCF_Pos (3U) 3474 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 3475 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 3476 #define I2C_ICR_NACKCF_Pos (4U) 3477 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 3478 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 3479 #define I2C_ICR_STOPCF_Pos (5U) 3480 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 3481 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 3482 #define I2C_ICR_BERRCF_Pos (8U) 3483 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 3484 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 3485 #define I2C_ICR_ARLOCF_Pos (9U) 3486 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 3487 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 3488 #define I2C_ICR_OVRCF_Pos (10U) 3489 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 3490 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 3491 #define I2C_ICR_PECCF_Pos (11U) 3492 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 3493 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 3494 #define I2C_ICR_TIMOUTCF_Pos (12U) 3495 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 3496 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 3497 #define I2C_ICR_ALERTCF_Pos (13U) 3498 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 3499 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 3500 3501 /****************** Bit definition for I2C_PECR register *********************/ 3502 #define I2C_PECR_PEC_Pos (0U) 3503 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 3504 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 3505 3506 /****************** Bit definition for I2C_RXDR register *********************/ 3507 #define I2C_RXDR_RXDATA_Pos (0U) 3508 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 3509 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 3510 3511 /****************** Bit definition for I2C_TXDR register *********************/ 3512 #define I2C_TXDR_TXDATA_Pos (0U) 3513 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 3514 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 3515 3516 3517 /******************************************************************************/ 3518 /* */ 3519 /* Independent WATCHDOG (IWDG) */ 3520 /* */ 3521 /******************************************************************************/ 3522 /******************* Bit definition for IWDG_KR register ********************/ 3523 #define IWDG_KR_KEY_Pos (0U) 3524 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3525 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 3526 3527 /******************* Bit definition for IWDG_PR register ********************/ 3528 #define IWDG_PR_PR_Pos (0U) 3529 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3530 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 3531 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3532 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3533 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3534 3535 /******************* Bit definition for IWDG_RLR register *******************/ 3536 #define IWDG_RLR_RL_Pos (0U) 3537 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3538 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 3539 3540 /******************* Bit definition for IWDG_SR register ********************/ 3541 #define IWDG_SR_PVU_Pos (0U) 3542 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3543 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3544 #define IWDG_SR_RVU_Pos (1U) 3545 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3546 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3547 #define IWDG_SR_WVU_Pos (2U) 3548 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 3549 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 3550 3551 /******************* Bit definition for IWDG_KR register ********************/ 3552 #define IWDG_WINR_WIN_Pos (0U) 3553 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 3554 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 3555 3556 3557 /******************************************************************************/ 3558 /* */ 3559 /* Power Control */ 3560 /* */ 3561 /******************************************************************************/ 3562 /* Note: No specific macro feature on this device */ 3563 3564 /******************** Bit definition for PWR_CR1 register ********************/ 3565 #define PWR_CR1_LPMS_Pos (0U) 3566 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 3567 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */ 3568 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ 3569 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ 3570 #define PWR_CR1_FPD_STOP_Pos (3U) 3571 #define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */ 3572 #define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */ 3573 #define PWR_CR1_FPD_LPRUN_Pos (4U) 3574 #define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */ 3575 #define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */ 3576 #define PWR_CR1_FPD_LPSLP_Pos (5U) 3577 #define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */ 3578 #define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */ 3579 #define PWR_CR1_DBP_Pos (8U) 3580 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ 3581 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ 3582 #define PWR_CR1_VOS_Pos (9U) 3583 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ 3584 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */ 3585 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */ 3586 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */ 3587 #define PWR_CR1_LPR_Pos (14U) 3588 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ 3589 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ 3590 3591 3592 /******************** Bit definition for PWR_CR3 register ********************/ 3593 #define PWR_CR3_EWUP_Pos (0U) 3594 #define PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000002B */ 3595 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */ 3596 #define PWR_CR3_EWUP1_Pos (0U) 3597 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 3598 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3599 #define PWR_CR3_EWUP2_Pos (1U) 3600 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ 3601 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3602 #define PWR_CR3_EWUP4_Pos (3U) 3603 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ 3604 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */ 3605 #define PWR_CR3_EWUP6_Pos (5U) 3606 #define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */ 3607 #define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */ 3608 #define PWR_CR3_APC_Pos (10U) 3609 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 3610 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ 3611 #define PWR_CR3_EIWUL_Pos (15U) 3612 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */ 3613 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */ 3614 3615 /******************** Bit definition for PWR_CR4 register ********************/ 3616 #define PWR_CR4_WP_Pos (0U) 3617 #define PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos) /*!< 0x0000002B */ 3618 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */ 3619 #define PWR_CR4_WP1_Pos (0U) 3620 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 3621 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */ 3622 #define PWR_CR4_WP2_Pos (1U) 3623 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ 3624 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */ 3625 #define PWR_CR4_WP4_Pos (3U) 3626 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ 3627 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */ 3628 #define PWR_CR4_WP6_Pos (5U) 3629 #define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */ 3630 #define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */ 3631 #define PWR_CR4_VBE_Pos (8U) 3632 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ 3633 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */ 3634 #define PWR_CR4_VBRS_Pos (9U) 3635 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ 3636 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */ 3637 3638 /******************** Bit definition for PWR_SR1 register ********************/ 3639 #define PWR_SR1_WUF_Pos (0U) 3640 #define PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos) /*!< 0x0000002B */ 3641 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */ 3642 #define PWR_SR1_WUF1_Pos (0U) 3643 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 3644 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */ 3645 #define PWR_SR1_WUF2_Pos (1U) 3646 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ 3647 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */ 3648 #define PWR_SR1_WUF4_Pos (3U) 3649 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ 3650 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */ 3651 #define PWR_SR1_WUF6_Pos (5U) 3652 #define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */ 3653 #define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */ 3654 #define PWR_SR1_SBF_Pos (8U) 3655 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ 3656 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */ 3657 #define PWR_SR1_WUFI_Pos (15U) 3658 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 3659 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */ 3660 3661 /******************** Bit definition for PWR_SR2 register ********************/ 3662 #define PWR_SR2_FLASH_RDY_Pos (7U) 3663 #define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */ 3664 #define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */ 3665 #define PWR_SR2_REGLPS_Pos (8U) 3666 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ 3667 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */ 3668 #define PWR_SR2_REGLPF_Pos (9U) 3669 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ 3670 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */ 3671 #define PWR_SR2_VOSF_Pos (10U) 3672 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ 3673 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */ 3674 3675 /******************** Bit definition for PWR_SCR register ********************/ 3676 #define PWR_SCR_CWUF_Pos (0U) 3677 #define PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000002B */ 3678 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ 3679 #define PWR_SCR_CWUF1_Pos (0U) 3680 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 3681 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ 3682 #define PWR_SCR_CWUF2_Pos (1U) 3683 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ 3684 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ 3685 #define PWR_SCR_CWUF4_Pos (3U) 3686 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ 3687 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ 3688 #define PWR_SCR_CWUF6_Pos (5U) 3689 #define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */ 3690 #define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */ 3691 #define PWR_SCR_CSBF_Pos (8U) 3692 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ 3693 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */ 3694 3695 /******************** Bit definition for PWR_PUCRA register *****************/ 3696 #define PWR_PUCRA_PU0_Pos (0U) 3697 #define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */ 3698 #define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */ 3699 #define PWR_PUCRA_PU1_Pos (1U) 3700 #define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */ 3701 #define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */ 3702 #define PWR_PUCRA_PU2_Pos (2U) 3703 #define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */ 3704 #define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */ 3705 #define PWR_PUCRA_PU3_Pos (3U) 3706 #define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */ 3707 #define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */ 3708 #define PWR_PUCRA_PU4_Pos (4U) 3709 #define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */ 3710 #define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */ 3711 #define PWR_PUCRA_PU5_Pos (5U) 3712 #define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */ 3713 #define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */ 3714 #define PWR_PUCRA_PU6_Pos (6U) 3715 #define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */ 3716 #define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */ 3717 #define PWR_PUCRA_PU7_Pos (7U) 3718 #define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */ 3719 #define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */ 3720 #define PWR_PUCRA_PU8_Pos (8U) 3721 #define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */ 3722 #define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */ 3723 #define PWR_PUCRA_PU9_Pos (9U) 3724 #define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */ 3725 #define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */ 3726 #define PWR_PUCRA_PU10_Pos (10U) 3727 #define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */ 3728 #define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */ 3729 #define PWR_PUCRA_PU11_Pos (11U) 3730 #define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */ 3731 #define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */ 3732 #define PWR_PUCRA_PU12_Pos (12U) 3733 #define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */ 3734 #define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */ 3735 #define PWR_PUCRA_PU13_Pos (13U) 3736 #define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */ 3737 #define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */ 3738 #define PWR_PUCRA_PU14_Pos (14U) 3739 #define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */ 3740 #define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */ 3741 #define PWR_PUCRA_PU15_Pos (15U) 3742 #define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */ 3743 #define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */ 3744 3745 /******************** Bit definition for PWR_PDCRA register *****************/ 3746 #define PWR_PDCRA_PD0_Pos (0U) 3747 #define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */ 3748 #define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */ 3749 #define PWR_PDCRA_PD1_Pos (1U) 3750 #define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */ 3751 #define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */ 3752 #define PWR_PDCRA_PD2_Pos (2U) 3753 #define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */ 3754 #define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */ 3755 #define PWR_PDCRA_PD3_Pos (3U) 3756 #define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */ 3757 #define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */ 3758 #define PWR_PDCRA_PD4_Pos (4U) 3759 #define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */ 3760 #define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */ 3761 #define PWR_PDCRA_PD5_Pos (5U) 3762 #define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */ 3763 #define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */ 3764 #define PWR_PDCRA_PD6_Pos (6U) 3765 #define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */ 3766 #define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */ 3767 #define PWR_PDCRA_PD7_Pos (7U) 3768 #define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */ 3769 #define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */ 3770 #define PWR_PDCRA_PD8_Pos (8U) 3771 #define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */ 3772 #define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */ 3773 #define PWR_PDCRA_PD9_Pos (9U) 3774 #define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */ 3775 #define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */ 3776 #define PWR_PDCRA_PD10_Pos (10U) 3777 #define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */ 3778 #define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */ 3779 #define PWR_PDCRA_PD11_Pos (11U) 3780 #define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */ 3781 #define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */ 3782 #define PWR_PDCRA_PD12_Pos (12U) 3783 #define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */ 3784 #define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */ 3785 #define PWR_PDCRA_PD13_Pos (13U) 3786 #define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */ 3787 #define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */ 3788 #define PWR_PDCRA_PD14_Pos (14U) 3789 #define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */ 3790 #define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */ 3791 #define PWR_PDCRA_PD15_Pos (15U) 3792 #define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */ 3793 #define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */ 3794 3795 /******************** Bit definition for PWR_PUCRB register *****************/ 3796 #define PWR_PUCRB_PU0_Pos (0U) 3797 #define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */ 3798 #define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */ 3799 #define PWR_PUCRB_PU1_Pos (1U) 3800 #define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */ 3801 #define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */ 3802 #define PWR_PUCRB_PU2_Pos (2U) 3803 #define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */ 3804 #define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */ 3805 #define PWR_PUCRB_PU3_Pos (3U) 3806 #define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */ 3807 #define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */ 3808 #define PWR_PUCRB_PU4_Pos (4U) 3809 #define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */ 3810 #define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */ 3811 #define PWR_PUCRB_PU5_Pos (5U) 3812 #define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */ 3813 #define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */ 3814 #define PWR_PUCRB_PU6_Pos (6U) 3815 #define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */ 3816 #define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */ 3817 #define PWR_PUCRB_PU7_Pos (7U) 3818 #define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */ 3819 #define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */ 3820 #define PWR_PUCRB_PU8_Pos (8U) 3821 #define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */ 3822 #define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */ 3823 #define PWR_PUCRB_PU9_Pos (9U) 3824 #define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */ 3825 #define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */ 3826 #define PWR_PUCRB_PU10_Pos (10U) 3827 #define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */ 3828 #define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */ 3829 #define PWR_PUCRB_PU11_Pos (11U) 3830 #define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */ 3831 #define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */ 3832 #define PWR_PUCRB_PU12_Pos (12U) 3833 #define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */ 3834 #define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */ 3835 #define PWR_PUCRB_PU13_Pos (13U) 3836 #define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */ 3837 #define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */ 3838 #define PWR_PUCRB_PU14_Pos (14U) 3839 #define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */ 3840 #define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */ 3841 #define PWR_PUCRB_PU15_Pos (15U) 3842 #define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */ 3843 #define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */ 3844 3845 /******************** Bit definition for PWR_PDCRB register *****************/ 3846 #define PWR_PDCRB_PD0_Pos (0U) 3847 #define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */ 3848 #define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */ 3849 #define PWR_PDCRB_PD1_Pos (1U) 3850 #define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */ 3851 #define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */ 3852 #define PWR_PDCRB_PD2_Pos (2U) 3853 #define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */ 3854 #define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */ 3855 #define PWR_PDCRB_PD3_Pos (3U) 3856 #define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */ 3857 #define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */ 3858 #define PWR_PDCRB_PD4_Pos (4U) 3859 #define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */ 3860 #define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */ 3861 #define PWR_PDCRB_PD5_Pos (5U) 3862 #define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */ 3863 #define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */ 3864 #define PWR_PDCRB_PD6_Pos (6U) 3865 #define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */ 3866 #define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */ 3867 #define PWR_PDCRB_PD7_Pos (7U) 3868 #define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */ 3869 #define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */ 3870 #define PWR_PDCRB_PD8_Pos (8U) 3871 #define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */ 3872 #define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */ 3873 #define PWR_PDCRB_PD9_Pos (9U) 3874 #define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */ 3875 #define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */ 3876 #define PWR_PDCRB_PD10_Pos (10U) 3877 #define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */ 3878 #define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */ 3879 #define PWR_PDCRB_PD11_Pos (11U) 3880 #define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */ 3881 #define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */ 3882 #define PWR_PDCRB_PD12_Pos (12U) 3883 #define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */ 3884 #define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */ 3885 #define PWR_PDCRB_PD13_Pos (13U) 3886 #define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */ 3887 #define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */ 3888 #define PWR_PDCRB_PD14_Pos (14U) 3889 #define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */ 3890 #define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */ 3891 #define PWR_PDCRB_PD15_Pos (15U) 3892 #define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */ 3893 #define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */ 3894 3895 /******************** Bit definition for PWR_PUCRC register *****************/ 3896 #define PWR_PUCRC_PU6_Pos (6U) 3897 #define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */ 3898 #define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */ 3899 #define PWR_PUCRC_PU7_Pos (7U) 3900 #define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */ 3901 #define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */ 3902 #define PWR_PUCRC_PU13_Pos (13U) 3903 #define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */ 3904 #define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */ 3905 #define PWR_PUCRC_PU14_Pos (14U) 3906 #define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */ 3907 #define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */ 3908 #define PWR_PUCRC_PU15_Pos (15U) 3909 #define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */ 3910 #define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */ 3911 3912 /******************** Bit definition for PWR_PDCRC register *****************/ 3913 #define PWR_PDCRC_PD6_Pos (6U) 3914 #define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */ 3915 #define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */ 3916 #define PWR_PDCRC_PD7_Pos (7U) 3917 #define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */ 3918 #define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */ 3919 #define PWR_PDCRC_PD13_Pos (13U) 3920 #define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */ 3921 #define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */ 3922 #define PWR_PDCRC_PD14_Pos (14U) 3923 #define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */ 3924 #define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */ 3925 #define PWR_PDCRC_PD15_Pos (15U) 3926 #define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */ 3927 #define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */ 3928 3929 /******************** Bit definition for PWR_PUCRD register *****************/ 3930 #define PWR_PUCRD_PU0_Pos (0U) 3931 #define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */ 3932 #define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */ 3933 #define PWR_PUCRD_PU1_Pos (1U) 3934 #define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */ 3935 #define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */ 3936 #define PWR_PUCRD_PU2_Pos (2U) 3937 #define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */ 3938 #define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */ 3939 #define PWR_PUCRD_PU3_Pos (3U) 3940 #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ 3941 #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ 3942 3943 /******************** Bit definition for PWR_PDCRD register *****************/ 3944 #define PWR_PDCRD_PD0_Pos (0U) 3945 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ 3946 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */ 3947 #define PWR_PDCRD_PD1_Pos (1U) 3948 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */ 3949 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */ 3950 #define PWR_PDCRD_PD2_Pos (2U) 3951 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */ 3952 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */ 3953 #define PWR_PDCRD_PD3_Pos (3U) 3954 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */ 3955 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */ 3956 3957 /******************** Bit definition for PWR_PUCRF register *****************/ 3958 #define PWR_PUCRF_PU0_Pos (0U) 3959 #define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */ 3960 #define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */ 3961 #define PWR_PUCRF_PU1_Pos (1U) 3962 #define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */ 3963 #define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */ 3964 #define PWR_PUCRF_PU2_Pos (2U) 3965 #define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */ 3966 #define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */ 3967 3968 /******************** Bit definition for PWR_PDCRF register *****************/ 3969 #define PWR_PDCRF_PD0_Pos (0U) 3970 #define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */ 3971 #define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */ 3972 #define PWR_PDCRF_PD1_Pos (1U) 3973 #define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */ 3974 #define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */ 3975 #define PWR_PDCRF_PD2_Pos (2U) 3976 #define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */ 3977 #define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */ 3978 3979 /******************************************************************************/ 3980 /* */ 3981 /* Reset and Clock Control */ 3982 /* */ 3983 /******************************************************************************/ 3984 /* 3985 * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) 3986 */ 3987 3988 /******************** Bit definition for RCC_CR register *****************/ 3989 #define RCC_CR_HSION_Pos (8U) 3990 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 3991 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3992 #define RCC_CR_HSIKERON_Pos (9U) 3993 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 3994 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ 3995 #define RCC_CR_HSIRDY_Pos (10U) 3996 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 3997 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3998 #define RCC_CR_HSIDIV_Pos (11U) 3999 #define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */ 4000 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */ 4001 #define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */ 4002 #define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */ 4003 #define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */ 4004 #define RCC_CR_HSEON_Pos (16U) 4005 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 4006 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 4007 #define RCC_CR_HSERDY_Pos (17U) 4008 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 4009 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */ 4010 #define RCC_CR_HSEBYP_Pos (18U) 4011 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 4012 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 4013 #define RCC_CR_CSSON_Pos (19U) 4014 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 4015 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 4016 4017 #define RCC_CR_PLLON_Pos (24U) 4018 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 4019 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ 4020 #define RCC_CR_PLLRDY_Pos (25U) 4021 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 4022 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ 4023 4024 /******************** Bit definition for RCC_ICSCR register ***************/ 4025 /*!< HSICAL configuration */ 4026 #define RCC_ICSCR_HSICAL_Pos (0U) 4027 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 4028 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 4029 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */ 4030 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */ 4031 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */ 4032 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */ 4033 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */ 4034 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */ 4035 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */ 4036 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */ 4037 4038 /*!< HSITRIM configuration */ 4039 #define RCC_ICSCR_HSITRIM_Pos (8U) 4040 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */ 4041 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */ 4042 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */ 4043 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */ 4044 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */ 4045 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */ 4046 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */ 4047 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */ 4048 #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */ 4049 4050 /******************** Bit definition for RCC_CFGR register ***************/ 4051 /*!< SW configuration */ 4052 #define RCC_CFGR_SW_Pos (0U) 4053 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ 4054 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */ 4055 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4056 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4057 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ 4058 4059 /*!< SWS configuration */ 4060 #define RCC_CFGR_SWS_Pos (3U) 4061 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ 4062 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */ 4063 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4064 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ 4065 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ 4066 4067 #define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ 4068 #define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ 4069 #define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ 4070 #define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ 4071 #define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ 4072 4073 /*!< HPRE configuration */ 4074 #define RCC_CFGR_HPRE_Pos (8U) 4075 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ 4076 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4077 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */ 4078 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */ 4079 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */ 4080 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */ 4081 4082 /*!< PPRE configuration */ 4083 #define RCC_CFGR_PPRE_Pos (12U) 4084 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */ 4085 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */ 4086 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */ 4087 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */ 4088 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */ 4089 4090 4091 /*!< MCOSEL configuration */ 4092 #define RCC_CFGR_MCOSEL_Pos (24U) 4093 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4094 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */ 4095 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4096 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4097 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4098 4099 /*!< MCO Prescaler configuration */ 4100 #define RCC_CFGR_MCOPRE_Pos (28U) 4101 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4102 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */ 4103 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4104 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4105 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4106 4107 /******************** Bit definition for RCC_PLLCFGR register ***************/ 4108 #define RCC_PLLCFGR_PLLSRC_Pos (0U) 4109 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ 4110 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 4111 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */ 4112 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */ 4113 4114 #define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */ 4115 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U) 4116 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */ 4117 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */ 4118 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U) 4119 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */ 4120 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */ 4121 4122 #define RCC_PLLCFGR_PLLM_Pos (4U) 4123 #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ 4124 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 4125 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 4126 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 4127 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ 4128 4129 #define RCC_PLLCFGR_PLLN_Pos (8U) 4130 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ 4131 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 4132 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ 4133 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ 4134 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ 4135 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ 4136 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ 4137 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ 4138 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ 4139 4140 #define RCC_PLLCFGR_PLLPEN_Pos (16U) 4141 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ 4142 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk 4143 4144 #define RCC_PLLCFGR_PLLP_Pos (17U) 4145 #define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */ 4146 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 4147 #define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ 4148 #define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */ 4149 #define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */ 4150 #define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */ 4151 #define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */ 4152 4153 4154 #define RCC_PLLCFGR_PLLREN_Pos (28U) 4155 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */ 4156 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk 4157 4158 #define RCC_PLLCFGR_PLLR_Pos (29U) 4159 #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */ 4160 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 4161 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */ 4162 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */ 4163 #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */ 4164 4165 /******************** Bit definition for RCC_CIER register ******************/ 4166 #define RCC_CIER_LSIRDYIE_Pos (0U) 4167 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 4168 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk 4169 #define RCC_CIER_LSERDYIE_Pos (1U) 4170 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 4171 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 4172 #define RCC_CIER_HSIRDYIE_Pos (3U) 4173 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 4174 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 4175 #define RCC_CIER_HSERDYIE_Pos (4U) 4176 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 4177 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 4178 #define RCC_CIER_PLLRDYIE_Pos (5U) 4179 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ 4180 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk 4181 4182 /******************** Bit definition for RCC_CIFR register ******************/ 4183 #define RCC_CIFR_LSIRDYF_Pos (0U) 4184 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 4185 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk 4186 #define RCC_CIFR_LSERDYF_Pos (1U) 4187 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 4188 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 4189 #define RCC_CIFR_HSIRDYF_Pos (3U) 4190 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 4191 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 4192 #define RCC_CIFR_HSERDYF_Pos (4U) 4193 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 4194 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 4195 #define RCC_CIFR_PLLRDYF_Pos (5U) 4196 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ 4197 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk 4198 #define RCC_CIFR_CSSF_Pos (8U) 4199 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 4200 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 4201 #define RCC_CIFR_LSECSSF_Pos (9U) 4202 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 4203 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 4204 4205 /******************** Bit definition for RCC_CICR register ******************/ 4206 #define RCC_CICR_LSIRDYC_Pos (0U) 4207 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 4208 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk 4209 #define RCC_CICR_LSERDYC_Pos (1U) 4210 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 4211 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 4212 #define RCC_CICR_HSIRDYC_Pos (3U) 4213 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 4214 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 4215 #define RCC_CICR_HSERDYC_Pos (4U) 4216 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 4217 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 4218 #define RCC_CICR_PLLRDYC_Pos (5U) 4219 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ 4220 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk 4221 #define RCC_CICR_CSSC_Pos (8U) 4222 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 4223 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 4224 #define RCC_CICR_LSECSSC_Pos (9U) 4225 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 4226 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 4227 4228 /******************** Bit definition for RCC_IOPRSTR register ****************/ 4229 #define RCC_IOPRSTR_GPIOARST_Pos (0U) 4230 #define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4231 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk 4232 #define RCC_IOPRSTR_GPIOBRST_Pos (1U) 4233 #define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4234 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk 4235 #define RCC_IOPRSTR_GPIOCRST_Pos (2U) 4236 #define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4237 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk 4238 #define RCC_IOPRSTR_GPIODRST_Pos (3U) 4239 #define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4240 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk 4241 #define RCC_IOPRSTR_GPIOFRST_Pos (5U) 4242 #define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */ 4243 #define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk 4244 4245 /******************** Bit definition for RCC_AHBRSTR register ***************/ 4246 #define RCC_AHBRSTR_DMA1RST_Pos (0U) 4247 #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */ 4248 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk 4249 #define RCC_AHBRSTR_FLASHRST_Pos (8U) 4250 #define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */ 4251 #define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk 4252 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4253 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4254 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk 4255 4256 /******************** Bit definition for RCC_APBRSTR1 register **************/ 4257 #define RCC_APBRSTR1_TIM3RST_Pos (1U) 4258 #define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */ 4259 #define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk 4260 #define RCC_APBRSTR1_TIM6RST_Pos (4U) 4261 #define RCC_APBRSTR1_TIM6RST_Msk (0x1UL << RCC_APBRSTR1_TIM6RST_Pos) /*!< 0x00000010 */ 4262 #define RCC_APBRSTR1_TIM6RST RCC_APBRSTR1_TIM6RST_Msk 4263 #define RCC_APBRSTR1_TIM7RST_Pos (5U) 4264 #define RCC_APBRSTR1_TIM7RST_Msk (0x1UL << RCC_APBRSTR1_TIM7RST_Pos) /*!< 0x00000020 */ 4265 #define RCC_APBRSTR1_TIM7RST RCC_APBRSTR1_TIM7RST_Msk 4266 #define RCC_APBRSTR1_SPI2RST_Pos (14U) 4267 #define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */ 4268 #define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk 4269 #define RCC_APBRSTR1_USART2RST_Pos (17U) 4270 #define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */ 4271 #define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk 4272 #define RCC_APBRSTR1_I2C1RST_Pos (21U) 4273 #define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */ 4274 #define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk 4275 #define RCC_APBRSTR1_I2C2RST_Pos (22U) 4276 #define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */ 4277 #define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk 4278 #define RCC_APBRSTR1_DBGRST_Pos (27U) 4279 #define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */ 4280 #define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk 4281 #define RCC_APBRSTR1_PWRRST_Pos (28U) 4282 #define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */ 4283 #define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk 4284 4285 /******************** Bit definition for RCC_APBRSTR2 register **************/ 4286 #define RCC_APBRSTR2_SYSCFGRST_Pos (0U) 4287 #define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */ 4288 #define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk 4289 #define RCC_APBRSTR2_TIM1RST_Pos (11U) 4290 #define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */ 4291 #define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk 4292 #define RCC_APBRSTR2_SPI1RST_Pos (12U) 4293 #define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */ 4294 #define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk 4295 #define RCC_APBRSTR2_USART1RST_Pos (14U) 4296 #define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */ 4297 #define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk 4298 #define RCC_APBRSTR2_TIM14RST_Pos (15U) 4299 #define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */ 4300 #define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk 4301 #define RCC_APBRSTR2_TIM15RST_Pos (16U) 4302 #define RCC_APBRSTR2_TIM15RST_Msk (0x1UL << RCC_APBRSTR2_TIM15RST_Pos) /*!< 0x00010000 */ 4303 #define RCC_APBRSTR2_TIM15RST RCC_APBRSTR2_TIM15RST_Msk 4304 #define RCC_APBRSTR2_TIM16RST_Pos (17U) 4305 #define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */ 4306 #define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk 4307 #define RCC_APBRSTR2_TIM17RST_Pos (18U) 4308 #define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */ 4309 #define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk 4310 #define RCC_APBRSTR2_ADCRST_Pos (20U) 4311 #define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */ 4312 #define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk 4313 4314 /******************** Bit definition for RCC_IOPENR register ****************/ 4315 #define RCC_IOPENR_GPIOAEN_Pos (0U) 4316 #define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4317 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk 4318 #define RCC_IOPENR_GPIOBEN_Pos (1U) 4319 #define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4320 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk 4321 #define RCC_IOPENR_GPIOCEN_Pos (2U) 4322 #define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4323 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk 4324 #define RCC_IOPENR_GPIODEN_Pos (3U) 4325 #define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */ 4326 #define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk 4327 #define RCC_IOPENR_GPIOFEN_Pos (5U) 4328 #define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */ 4329 #define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk 4330 4331 /******************** Bit definition for RCC_AHBENR register ****************/ 4332 #define RCC_AHBENR_DMA1EN_Pos (0U) 4333 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 4334 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk 4335 #define RCC_AHBENR_FLASHEN_Pos (8U) 4336 #define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */ 4337 #define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk 4338 #define RCC_AHBENR_CRCEN_Pos (12U) 4339 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4340 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk 4341 4342 /******************** Bit definition for RCC_APBENR1 register ***************/ 4343 #define RCC_APBENR1_TIM3EN_Pos (1U) 4344 #define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */ 4345 #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk 4346 #define RCC_APBENR1_TIM6EN_Pos (4U) 4347 #define RCC_APBENR1_TIM6EN_Msk (0x1UL << RCC_APBENR1_TIM6EN_Pos) /*!< 0x00000010 */ 4348 #define RCC_APBENR1_TIM6EN RCC_APBENR1_TIM6EN_Msk 4349 #define RCC_APBENR1_TIM7EN_Pos (5U) 4350 #define RCC_APBENR1_TIM7EN_Msk (0x1UL << RCC_APBENR1_TIM7EN_Pos) /*!< 0x00000020 */ 4351 #define RCC_APBENR1_TIM7EN RCC_APBENR1_TIM7EN_Msk 4352 #define RCC_APBENR1_RTCAPBEN_Pos (10U) 4353 #define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ 4354 #define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk 4355 #define RCC_APBENR1_WWDGEN_Pos (11U) 4356 #define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */ 4357 #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk 4358 #define RCC_APBENR1_SPI2EN_Pos (14U) 4359 #define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */ 4360 #define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk 4361 #define RCC_APBENR1_USART2EN_Pos (17U) 4362 #define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */ 4363 #define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk 4364 #define RCC_APBENR1_I2C1EN_Pos (21U) 4365 #define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */ 4366 #define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk 4367 #define RCC_APBENR1_I2C2EN_Pos (22U) 4368 #define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */ 4369 #define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk 4370 #define RCC_APBENR1_DBGEN_Pos (27U) 4371 #define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */ 4372 #define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk 4373 #define RCC_APBENR1_PWREN_Pos (28U) 4374 #define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */ 4375 #define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk 4376 4377 /******************** Bit definition for RCC_APBENR2 register **************/ 4378 #define RCC_APBENR2_SYSCFGEN_Pos (0U) 4379 #define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ 4380 #define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk 4381 #define RCC_APBENR2_TIM1EN_Pos (11U) 4382 #define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */ 4383 #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk 4384 #define RCC_APBENR2_SPI1EN_Pos (12U) 4385 #define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */ 4386 #define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk 4387 #define RCC_APBENR2_USART1EN_Pos (14U) 4388 #define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */ 4389 #define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk 4390 #define RCC_APBENR2_TIM14EN_Pos (15U) 4391 #define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */ 4392 #define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk 4393 #define RCC_APBENR2_TIM15EN_Pos (16U) 4394 #define RCC_APBENR2_TIM15EN_Msk (0x1UL << RCC_APBENR2_TIM15EN_Pos) /*!< 0x00010000 */ 4395 #define RCC_APBENR2_TIM15EN RCC_APBENR2_TIM15EN_Msk 4396 #define RCC_APBENR2_TIM16EN_Pos (17U) 4397 #define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */ 4398 #define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk 4399 #define RCC_APBENR2_TIM17EN_Pos (18U) 4400 #define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */ 4401 #define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk 4402 #define RCC_APBENR2_ADCEN_Pos (20U) 4403 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */ 4404 #define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk 4405 4406 /******************** Bit definition for RCC_IOPSMENR register *************/ 4407 #define RCC_IOPSMENR_GPIOASMEN_Pos (0U) 4408 #define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ 4409 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk 4410 #define RCC_IOPSMENR_GPIOBSMEN_Pos (1U) 4411 #define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ 4412 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk 4413 #define RCC_IOPSMENR_GPIOCSMEN_Pos (2U) 4414 #define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ 4415 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk 4416 #define RCC_IOPSMENR_GPIODSMEN_Pos (3U) 4417 #define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */ 4418 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk 4419 #define RCC_IOPSMENR_GPIOFSMEN_Pos (5U) 4420 #define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */ 4421 #define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk 4422 4423 /******************** Bit definition for RCC_AHBSMENR register *************/ 4424 #define RCC_AHBSMENR_DMA1SMEN_Pos (0U) 4425 #define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ 4426 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk 4427 #define RCC_AHBSMENR_FLASHSMEN_Pos (8U) 4428 #define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ 4429 #define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk 4430 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U) 4431 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ 4432 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk 4433 #define RCC_AHBSMENR_CRCSMEN_Pos (12U) 4434 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 4435 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk 4436 4437 /******************** Bit definition for RCC_APBSMENR1 register *************/ 4438 #define RCC_APBSMENR1_TIM3SMEN_Pos (1U) 4439 #define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ 4440 #define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk 4441 #define RCC_APBSMENR1_TIM6SMEN_Pos (4U) 4442 #define RCC_APBSMENR1_TIM6SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */ 4443 #define RCC_APBSMENR1_TIM6SMEN RCC_APBSMENR1_TIM6SMEN_Msk 4444 #define RCC_APBSMENR1_TIM7SMEN_Pos (5U) 4445 #define RCC_APBSMENR1_TIM7SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */ 4446 #define RCC_APBSMENR1_TIM7SMEN RCC_APBSMENR1_TIM7SMEN_Msk 4447 #define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U) 4448 #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ 4449 #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk 4450 #define RCC_APBSMENR1_WWDGSMEN_Pos (11U) 4451 #define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ 4452 #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk 4453 #define RCC_APBSMENR1_SPI2SMEN_Pos (14U) 4454 #define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ 4455 #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk 4456 #define RCC_APBSMENR1_USART2SMEN_Pos (17U) 4457 #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ 4458 #define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk 4459 #define RCC_APBSMENR1_I2C1SMEN_Pos (21U) 4460 #define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ 4461 #define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk 4462 #define RCC_APBSMENR1_I2C2SMEN_Pos (22U) 4463 #define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */ 4464 #define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk 4465 #define RCC_APBSMENR1_DBGSMEN_Pos (27U) 4466 #define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */ 4467 #define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk 4468 #define RCC_APBSMENR1_PWRSMEN_Pos (28U) 4469 #define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */ 4470 #define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk 4471 4472 /******************** Bit definition for RCC_APBSMENR2 register *************/ 4473 #define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U) 4474 #define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 4475 #define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk 4476 #define RCC_APBSMENR2_TIM1SMEN_Pos (11U) 4477 #define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */ 4478 #define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk 4479 #define RCC_APBSMENR2_SPI1SMEN_Pos (12U) 4480 #define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */ 4481 #define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk 4482 #define RCC_APBSMENR2_USART1SMEN_Pos (14U) 4483 #define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */ 4484 #define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk 4485 #define RCC_APBSMENR2_TIM14SMEN_Pos (15U) 4486 #define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */ 4487 #define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk 4488 #define RCC_APBSMENR2_TIM15SMEN_Pos (16U) 4489 #define RCC_APBSMENR2_TIM15SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos) /*!< 0x00010000 */ 4490 #define RCC_APBSMENR2_TIM15SMEN RCC_APBSMENR2_TIM15SMEN_Msk 4491 #define RCC_APBSMENR2_TIM16SMEN_Pos (17U) 4492 #define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */ 4493 #define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk 4494 #define RCC_APBSMENR2_TIM17SMEN_Pos (18U) 4495 #define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */ 4496 #define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk 4497 #define RCC_APBSMENR2_ADCSMEN_Pos (20U) 4498 #define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */ 4499 #define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk 4500 4501 /******************** Bit definition for RCC_CCIPR register ******************/ 4502 #define RCC_CCIPR_USART1SEL_Pos (0U) 4503 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 4504 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 4505 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 4506 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 4507 4508 4509 4510 4511 #define RCC_CCIPR_I2C1SEL_Pos (12U) 4512 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 4513 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 4514 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 4515 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 4516 4517 #define RCC_CCIPR_I2S1SEL_Pos (14U) 4518 #define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */ 4519 #define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk 4520 #define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */ 4521 #define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */ 4522 4523 4524 4525 4526 #define RCC_CCIPR_ADCSEL_Pos (30U) 4527 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */ 4528 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk 4529 #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */ 4530 #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */ 4531 4532 /******************** Bit definition for RCC_BDCR register ******************/ 4533 #define RCC_BDCR_LSEON_Pos (0U) 4534 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 4535 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 4536 #define RCC_BDCR_LSERDY_Pos (1U) 4537 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 4538 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 4539 #define RCC_BDCR_LSEBYP_Pos (2U) 4540 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 4541 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 4542 4543 #define RCC_BDCR_LSEDRV_Pos (3U) 4544 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 4545 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 4546 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 4547 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 4548 4549 #define RCC_BDCR_LSECSSON_Pos (5U) 4550 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ 4551 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk 4552 #define RCC_BDCR_LSECSSD_Pos (6U) 4553 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ 4554 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk 4555 4556 #define RCC_BDCR_RTCSEL_Pos (8U) 4557 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 4558 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 4559 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 4560 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 4561 4562 #define RCC_BDCR_RTCEN_Pos (15U) 4563 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 4564 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 4565 #define RCC_BDCR_BDRST_Pos (16U) 4566 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 4567 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 4568 4569 #define RCC_BDCR_LSCOEN_Pos (24U) 4570 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ 4571 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk 4572 #define RCC_BDCR_LSCOSEL_Pos (25U) 4573 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ 4574 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk 4575 4576 /******************** Bit definition for RCC_CSR register *******************/ 4577 #define RCC_CSR_LSION_Pos (0U) 4578 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 4579 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 4580 #define RCC_CSR_LSIRDY_Pos (1U) 4581 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 4582 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 4583 4584 #define RCC_CSR_RMVF_Pos (23U) 4585 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 4586 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 4587 #define RCC_CSR_OBLRSTF_Pos (25U) 4588 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 4589 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk 4590 #define RCC_CSR_PINRSTF_Pos (26U) 4591 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 4592 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 4593 #define RCC_CSR_PWRRSTF_Pos (27U) 4594 #define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */ 4595 #define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk 4596 #define RCC_CSR_SFTRSTF_Pos (28U) 4597 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 4598 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 4599 #define RCC_CSR_IWDGRSTF_Pos (29U) 4600 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 4601 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 4602 #define RCC_CSR_WWDGRSTF_Pos (30U) 4603 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 4604 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 4605 #define RCC_CSR_LPWRRSTF_Pos (31U) 4606 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 4607 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 4608 4609 /******************************************************************************/ 4610 /* */ 4611 /* Real-Time Clock (RTC) */ 4612 /* */ 4613 /******************************************************************************/ 4614 /* 4615 * @brief Specific device feature definitions 4616 */ 4617 #define RTC_WAKEUP_SUPPORT 4618 #define RTC_BACKUP_SUPPORT 4619 4620 /******************** Bits definition for RTC_TR register *******************/ 4621 #define RTC_TR_PM_Pos (22U) 4622 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4623 #define RTC_TR_PM RTC_TR_PM_Msk 4624 #define RTC_TR_HT_Pos (20U) 4625 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4626 #define RTC_TR_HT RTC_TR_HT_Msk 4627 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4628 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4629 #define RTC_TR_HU_Pos (16U) 4630 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4631 #define RTC_TR_HU RTC_TR_HU_Msk 4632 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4633 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4634 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4635 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4636 #define RTC_TR_MNT_Pos (12U) 4637 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4638 #define RTC_TR_MNT RTC_TR_MNT_Msk 4639 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4640 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4641 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4642 #define RTC_TR_MNU_Pos (8U) 4643 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 4644 #define RTC_TR_MNU RTC_TR_MNU_Msk 4645 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 4646 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 4647 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 4648 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 4649 #define RTC_TR_ST_Pos (4U) 4650 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 4651 #define RTC_TR_ST RTC_TR_ST_Msk 4652 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 4653 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 4654 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 4655 #define RTC_TR_SU_Pos (0U) 4656 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 4657 #define RTC_TR_SU RTC_TR_SU_Msk 4658 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 4659 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 4660 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 4661 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 4662 4663 /******************** Bits definition for RTC_DR register *******************/ 4664 #define RTC_DR_YT_Pos (20U) 4665 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 4666 #define RTC_DR_YT RTC_DR_YT_Msk 4667 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 4668 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 4669 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 4670 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 4671 #define RTC_DR_YU_Pos (16U) 4672 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 4673 #define RTC_DR_YU RTC_DR_YU_Msk 4674 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 4675 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 4676 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 4677 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 4678 #define RTC_DR_WDU_Pos (13U) 4679 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 4680 #define RTC_DR_WDU RTC_DR_WDU_Msk 4681 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 4682 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 4683 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 4684 #define RTC_DR_MT_Pos (12U) 4685 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 4686 #define RTC_DR_MT RTC_DR_MT_Msk 4687 #define RTC_DR_MU_Pos (8U) 4688 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 4689 #define RTC_DR_MU RTC_DR_MU_Msk 4690 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4691 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4692 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4693 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4694 #define RTC_DR_DT_Pos (4U) 4695 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4696 #define RTC_DR_DT RTC_DR_DT_Msk 4697 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4698 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4699 #define RTC_DR_DU_Pos (0U) 4700 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4701 #define RTC_DR_DU RTC_DR_DU_Msk 4702 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4703 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4704 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4705 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4706 4707 /******************** Bits definition for RTC_SSR register ******************/ 4708 #define RTC_SSR_SS_Pos (0U) 4709 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4710 #define RTC_SSR_SS RTC_SSR_SS_Msk 4711 4712 /******************** Bits definition for RTC_ICSR register ******************/ 4713 #define RTC_ICSR_RECALPF_Pos (16U) 4714 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ 4715 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk 4716 #define RTC_ICSR_INIT_Pos (7U) 4717 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ 4718 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk 4719 #define RTC_ICSR_INITF_Pos (6U) 4720 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ 4721 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk 4722 #define RTC_ICSR_RSF_Pos (5U) 4723 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ 4724 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk 4725 #define RTC_ICSR_INITS_Pos (4U) 4726 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ 4727 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk 4728 #define RTC_ICSR_SHPF_Pos (3U) 4729 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ 4730 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk 4731 #define RTC_ICSR_WUTWF_Pos (2U) 4732 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ 4733 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */ 4734 #define RTC_ICSR_ALRBWF_Pos (1U) 4735 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ 4736 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk 4737 #define RTC_ICSR_ALRAWF_Pos (0U) 4738 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ 4739 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk 4740 4741 /******************** Bits definition for RTC_PRER register *****************/ 4742 #define RTC_PRER_PREDIV_A_Pos (16U) 4743 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4744 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 4745 #define RTC_PRER_PREDIV_S_Pos (0U) 4746 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4747 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 4748 4749 /******************** Bits definition for RTC_WUTR register *****************/ 4750 #define RTC_WUTR_WUT_Pos (0U) 4751 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 4752 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ 4753 4754 /******************** Bits definition for RTC_CR register *******************/ 4755 #define RTC_CR_OUT2EN_Pos (31U) 4756 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ 4757 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ 4758 #define RTC_CR_TAMPALRM_TYPE_Pos (30U) 4759 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ 4760 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ 4761 #define RTC_CR_TAMPALRM_PU_Pos (29U) 4762 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ 4763 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ 4764 #define RTC_CR_TAMPOE_Pos (26U) 4765 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ 4766 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ 4767 #define RTC_CR_TAMPTS_Pos (25U) 4768 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ 4769 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ 4770 #define RTC_CR_ITSE_Pos (24U) 4771 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ 4772 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ 4773 #define RTC_CR_COE_Pos (23U) 4774 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4775 #define RTC_CR_COE RTC_CR_COE_Msk 4776 #define RTC_CR_OSEL_Pos (21U) 4777 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4778 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 4779 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4780 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4781 #define RTC_CR_POL_Pos (20U) 4782 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4783 #define RTC_CR_POL RTC_CR_POL_Msk 4784 #define RTC_CR_COSEL_Pos (19U) 4785 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4786 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 4787 #define RTC_CR_BKP_Pos (18U) 4788 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4789 #define RTC_CR_BKP RTC_CR_BKP_Msk 4790 #define RTC_CR_SUB1H_Pos (17U) 4791 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4792 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 4793 #define RTC_CR_ADD1H_Pos (16U) 4794 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4795 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 4796 #define RTC_CR_TSIE_Pos (15U) 4797 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4798 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ 4799 #define RTC_CR_WUTIE_Pos (14U) 4800 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 4801 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ 4802 #define RTC_CR_ALRBIE_Pos (13U) 4803 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 4804 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 4805 #define RTC_CR_ALRAIE_Pos (12U) 4806 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4807 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 4808 #define RTC_CR_TSE_Pos (11U) 4809 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4810 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ 4811 #define RTC_CR_WUTE_Pos (10U) 4812 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 4813 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ 4814 #define RTC_CR_ALRBE_Pos (9U) 4815 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 4816 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 4817 #define RTC_CR_ALRAE_Pos (8U) 4818 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4819 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 4820 #define RTC_CR_FMT_Pos (6U) 4821 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4822 #define RTC_CR_FMT RTC_CR_FMT_Msk 4823 #define RTC_CR_BYPSHAD_Pos (5U) 4824 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4825 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 4826 #define RTC_CR_REFCKON_Pos (4U) 4827 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4828 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 4829 #define RTC_CR_TSEDGE_Pos (3U) 4830 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4831 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ 4832 #define RTC_CR_WUCKSEL_Pos (0U) 4833 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 4834 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ 4835 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 4836 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 4837 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 4838 4839 /******************** Bits definition for RTC_WPR register ******************/ 4840 #define RTC_WPR_KEY_Pos (0U) 4841 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4842 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 4843 4844 /******************** Bits definition for RTC_CALR register *****************/ 4845 #define RTC_CALR_CALP_Pos (15U) 4846 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4847 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 4848 #define RTC_CALR_CALW8_Pos (14U) 4849 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4850 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 4851 #define RTC_CALR_CALW16_Pos (13U) 4852 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4853 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 4854 #define RTC_CALR_CALM_Pos (0U) 4855 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4856 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 4857 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4858 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4859 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4860 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4861 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4862 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4863 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4864 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4865 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4866 4867 /******************** Bits definition for RTC_SHIFTR register ***************/ 4868 #define RTC_SHIFTR_SUBFS_Pos (0U) 4869 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4870 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 4871 #define RTC_SHIFTR_ADD1S_Pos (31U) 4872 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4873 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 4874 4875 /******************** Bits definition for RTC_TSTR register *****************/ 4876 #define RTC_TSTR_PM_Pos (22U) 4877 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4878 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ 4879 #define RTC_TSTR_HT_Pos (20U) 4880 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4881 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 4882 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4883 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4884 #define RTC_TSTR_HU_Pos (16U) 4885 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4886 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 4887 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4888 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4889 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4890 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4891 #define RTC_TSTR_MNT_Pos (12U) 4892 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4893 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 4894 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4895 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4896 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4897 #define RTC_TSTR_MNU_Pos (8U) 4898 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4899 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 4900 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4901 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4902 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4903 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4904 #define RTC_TSTR_ST_Pos (4U) 4905 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4906 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 4907 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4908 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4909 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4910 #define RTC_TSTR_SU_Pos (0U) 4911 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4912 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 4913 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4914 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4915 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4916 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4917 4918 /******************** Bits definition for RTC_TSDR register *****************/ 4919 #define RTC_TSDR_WDU_Pos (13U) 4920 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4921 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ 4922 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4923 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4924 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4925 #define RTC_TSDR_MT_Pos (12U) 4926 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4927 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 4928 #define RTC_TSDR_MU_Pos (8U) 4929 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4930 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 4931 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4932 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4933 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4934 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4935 #define RTC_TSDR_DT_Pos (4U) 4936 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4937 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 4938 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4939 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4940 #define RTC_TSDR_DU_Pos (0U) 4941 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4942 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 4943 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4944 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4945 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4946 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4947 4948 /******************** Bits definition for RTC_TSSSR register ****************/ 4949 #define RTC_TSSSR_SS_Pos (0U) 4950 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4951 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ 4952 4953 /******************** Bits definition for RTC_ALRMAR register ***************/ 4954 #define RTC_ALRMAR_MSK4_Pos (31U) 4955 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4956 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 4957 #define RTC_ALRMAR_WDSEL_Pos (30U) 4958 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4959 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 4960 #define RTC_ALRMAR_DT_Pos (28U) 4961 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4962 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 4963 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4964 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4965 #define RTC_ALRMAR_DU_Pos (24U) 4966 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4967 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 4968 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4969 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4970 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4971 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4972 #define RTC_ALRMAR_MSK3_Pos (23U) 4973 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4974 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 4975 #define RTC_ALRMAR_PM_Pos (22U) 4976 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4977 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 4978 #define RTC_ALRMAR_HT_Pos (20U) 4979 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4980 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 4981 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4982 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4983 #define RTC_ALRMAR_HU_Pos (16U) 4984 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4985 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 4986 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4987 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4988 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4989 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4990 #define RTC_ALRMAR_MSK2_Pos (15U) 4991 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4992 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 4993 #define RTC_ALRMAR_MNT_Pos (12U) 4994 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4995 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 4996 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4997 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4998 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4999 #define RTC_ALRMAR_MNU_Pos (8U) 5000 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 5001 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 5002 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 5003 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 5004 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 5005 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 5006 #define RTC_ALRMAR_MSK1_Pos (7U) 5007 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 5008 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 5009 #define RTC_ALRMAR_ST_Pos (4U) 5010 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 5011 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 5012 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 5013 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 5014 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 5015 #define RTC_ALRMAR_SU_Pos (0U) 5016 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 5017 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 5018 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 5019 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 5020 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 5021 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 5022 5023 /******************** Bits definition for RTC_ALRMASSR register *************/ 5024 #define RTC_ALRMASSR_MASKSS_Pos (24U) 5025 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 5026 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 5027 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 5028 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 5029 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 5030 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 5031 #define RTC_ALRMASSR_SS_Pos (0U) 5032 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 5033 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 5034 5035 /******************** Bits definition for RTC_ALRMBR register ***************/ 5036 #define RTC_ALRMBR_MSK4_Pos (31U) 5037 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 5038 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 5039 #define RTC_ALRMBR_WDSEL_Pos (30U) 5040 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 5041 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 5042 #define RTC_ALRMBR_DT_Pos (28U) 5043 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 5044 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 5045 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 5046 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 5047 #define RTC_ALRMBR_DU_Pos (24U) 5048 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 5049 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 5050 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 5051 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 5052 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 5053 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 5054 #define RTC_ALRMBR_MSK3_Pos (23U) 5055 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 5056 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 5057 #define RTC_ALRMBR_PM_Pos (22U) 5058 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 5059 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 5060 #define RTC_ALRMBR_HT_Pos (20U) 5061 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 5062 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 5063 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 5064 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 5065 #define RTC_ALRMBR_HU_Pos (16U) 5066 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 5067 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 5068 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 5069 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 5070 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 5071 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 5072 #define RTC_ALRMBR_MSK2_Pos (15U) 5073 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 5074 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 5075 #define RTC_ALRMBR_MNT_Pos (12U) 5076 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 5077 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 5078 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 5079 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 5080 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 5081 #define RTC_ALRMBR_MNU_Pos (8U) 5082 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 5083 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 5084 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 5085 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 5086 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 5087 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 5088 #define RTC_ALRMBR_MSK1_Pos (7U) 5089 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 5090 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 5091 #define RTC_ALRMBR_ST_Pos (4U) 5092 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 5093 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 5094 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 5095 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 5096 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 5097 #define RTC_ALRMBR_SU_Pos (0U) 5098 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 5099 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 5100 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 5101 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 5102 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 5103 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 5104 5105 /******************** Bits definition for RTC_ALRMASSR register *************/ 5106 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 5107 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 5108 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 5109 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 5110 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 5111 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 5112 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 5113 #define RTC_ALRMBSSR_SS_Pos (0U) 5114 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 5115 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 5116 5117 /******************** Bits definition for RTC_SR register *******************/ 5118 #define RTC_SR_ITSF_Pos (5U) 5119 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ 5120 #define RTC_SR_ITSF RTC_SR_ITSF_Msk 5121 #define RTC_SR_TSOVF_Pos (4U) 5122 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ 5123 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ 5124 #define RTC_SR_TSF_Pos (3U) 5125 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ 5126 #define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ 5127 #define RTC_SR_WUTF_Pos (2U) 5128 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ 5129 #define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ 5130 #define RTC_SR_ALRBF_Pos (1U) 5131 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ 5132 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk 5133 #define RTC_SR_ALRAF_Pos (0U) 5134 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ 5135 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk 5136 5137 /******************** Bits definition for RTC_MISR register *****************/ 5138 #define RTC_MISR_ITSMF_Pos (5U) 5139 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ 5140 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk 5141 #define RTC_MISR_TSOVMF_Pos (4U) 5142 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ 5143 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ 5144 #define RTC_MISR_TSMF_Pos (3U) 5145 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ 5146 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ 5147 #define RTC_MISR_WUTMF_Pos (2U) 5148 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ 5149 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ 5150 #define RTC_MISR_ALRBMF_Pos (1U) 5151 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ 5152 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk 5153 #define RTC_MISR_ALRAMF_Pos (0U) 5154 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ 5155 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk 5156 5157 /******************** Bits definition for RTC_SCR register ******************/ 5158 #define RTC_SCR_CITSF_Pos (5U) 5159 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ 5160 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk 5161 #define RTC_SCR_CTSOVF_Pos (4U) 5162 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ 5163 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ 5164 #define RTC_SCR_CTSF_Pos (3U) 5165 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ 5166 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ 5167 #define RTC_SCR_CWUTF_Pos (2U) 5168 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ 5169 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ 5170 #define RTC_SCR_CALRBF_Pos (1U) 5171 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ 5172 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk 5173 #define RTC_SCR_CALRAF_Pos (0U) 5174 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ 5175 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk 5176 5177 /******************************************************************************/ 5178 /* */ 5179 /* Tamper and backup register (TAMP) */ 5180 /* */ 5181 /******************************************************************************/ 5182 /******************** Bits definition for TAMP_CR1 register *****************/ 5183 #define TAMP_CR1_TAMP1E_Pos (0U) 5184 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ 5185 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk 5186 #define TAMP_CR1_TAMP2E_Pos (1U) 5187 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ 5188 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk 5189 #define TAMP_CR1_ITAMP3E_Pos (18U) 5190 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ 5191 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk 5192 #define TAMP_CR1_ITAMP4E_Pos (19U) 5193 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ 5194 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk 5195 #define TAMP_CR1_ITAMP5E_Pos (20U) 5196 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ 5197 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk 5198 #define TAMP_CR1_ITAMP6E_Pos (21U) 5199 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ 5200 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk 5201 5202 /******************** Bits definition for TAMP_CR2 register *****************/ 5203 #define TAMP_CR2_TAMP1NOERASE_Pos (0U) 5204 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ 5205 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk 5206 #define TAMP_CR2_TAMP2NOERASE_Pos (1U) 5207 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ 5208 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk 5209 #define TAMP_CR2_TAMP1MSK_Pos (16U) 5210 #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ 5211 #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk 5212 #define TAMP_CR2_TAMP2MSK_Pos (17U) 5213 #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ 5214 #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk 5215 #define TAMP_CR2_TAMP1TRG_Pos (24U) 5216 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ 5217 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk 5218 #define TAMP_CR2_TAMP2TRG_Pos (25U) 5219 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ 5220 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk 5221 5222 /******************** Bits definition for TAMP_FLTCR register ***************/ 5223 #define TAMP_FLTCR_TAMPFREQ_0 0x00000001U 5224 #define TAMP_FLTCR_TAMPFREQ_1 0x00000002U 5225 #define TAMP_FLTCR_TAMPFREQ_2 0x00000004U 5226 #define TAMP_FLTCR_TAMPFREQ_Pos (0U) 5227 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ 5228 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk 5229 #define TAMP_FLTCR_TAMPFLT_0 0x00000008U 5230 #define TAMP_FLTCR_TAMPFLT_1 0x00000010U 5231 #define TAMP_FLTCR_TAMPFLT_Pos (3U) 5232 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ 5233 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk 5234 #define TAMP_FLTCR_TAMPPRCH_0 0x00000020U 5235 #define TAMP_FLTCR_TAMPPRCH_1 0x00000040U 5236 #define TAMP_FLTCR_TAMPPRCH_Pos (5U) 5237 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ 5238 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk 5239 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U) 5240 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ 5241 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk 5242 5243 /******************** Bits definition for TAMP_IER register *****************/ 5244 #define TAMP_IER_TAMP1IE_Pos (0U) 5245 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ 5246 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk 5247 #define TAMP_IER_TAMP2IE_Pos (1U) 5248 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ 5249 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk 5250 #define TAMP_IER_ITAMP3IE_Pos (18U) 5251 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ 5252 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk 5253 #define TAMP_IER_ITAMP4IE_Pos (19U) 5254 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ 5255 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk 5256 #define TAMP_IER_ITAMP5IE_Pos (20U) 5257 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ 5258 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk 5259 #define TAMP_IER_ITAMP6IE_Pos (21U) 5260 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ 5261 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk 5262 5263 /******************** Bits definition for TAMP_SR register ******************/ 5264 #define TAMP_SR_TAMP1F_Pos (0U) 5265 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ 5266 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk 5267 #define TAMP_SR_TAMP2F_Pos (1U) 5268 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ 5269 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk 5270 #define TAMP_SR_ITAMP3F_Pos (18U) 5271 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ 5272 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk 5273 #define TAMP_SR_ITAMP4F_Pos (19U) 5274 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ 5275 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk 5276 #define TAMP_SR_ITAMP5F_Pos (20U) 5277 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ 5278 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk 5279 #define TAMP_SR_ITAMP6F_Pos (21U) 5280 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ 5281 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk 5282 5283 /******************** Bits definition for TAMP_MISR register ****************/ 5284 #define TAMP_MISR_TAMP1MF_Pos (0U) 5285 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ 5286 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk 5287 #define TAMP_MISR_TAMP2MF_Pos (1U) 5288 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ 5289 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk 5290 #define TAMP_MISR_ITAMP3MF_Pos (18U) 5291 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ 5292 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk 5293 #define TAMP_MISR_ITAMP4MF_Pos (19U) 5294 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ 5295 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk 5296 #define TAMP_MISR_ITAMP5MF_Pos (20U) 5297 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ 5298 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk 5299 #define TAMP_MISR_ITAMP6MF_Pos (21U) 5300 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ 5301 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk 5302 5303 /******************** Bits definition for TAMP_SCR register *****************/ 5304 #define TAMP_SCR_CTAMP1F_Pos (0U) 5305 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ 5306 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk 5307 #define TAMP_SCR_CTAMP2F_Pos (1U) 5308 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ 5309 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk 5310 #define TAMP_SCR_CITAMP3F_Pos (18U) 5311 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ 5312 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk 5313 #define TAMP_SCR_CITAMP4F_Pos (19U) 5314 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ 5315 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk 5316 #define TAMP_SCR_CITAMP5F_Pos (20U) 5317 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ 5318 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk 5319 #define TAMP_SCR_CITAMP6F_Pos (21U) 5320 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ 5321 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk 5322 5323 /******************** Bits definition for TAMP_BKP0R register ***************/ 5324 #define TAMP_BKP0R_Pos (0U) 5325 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5326 #define TAMP_BKP0R TAMP_BKP0R_Msk 5327 5328 /******************** Bits definition for TAMP_BKP1R register ***************/ 5329 #define TAMP_BKP1R_Pos (0U) 5330 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5331 #define TAMP_BKP1R TAMP_BKP1R_Msk 5332 5333 /******************** Bits definition for TAMP_BKP2R register ***************/ 5334 #define TAMP_BKP2R_Pos (0U) 5335 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5336 #define TAMP_BKP2R TAMP_BKP2R_Msk 5337 5338 /******************** Bits definition for TAMP_BKP3R register ***************/ 5339 #define TAMP_BKP3R_Pos (0U) 5340 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5341 #define TAMP_BKP3R TAMP_BKP3R_Msk 5342 5343 /******************** Bits definition for TAMP_BKP4R register ***************/ 5344 #define TAMP_BKP4R_Pos (0U) 5345 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5346 #define TAMP_BKP4R TAMP_BKP4R_Msk 5347 5348 /******************************************************************************/ 5349 /* */ 5350 /* Serial Peripheral Interface (SPI) */ 5351 /* */ 5352 /******************************************************************************/ 5353 /* 5354 * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) 5355 */ 5356 #define SPI_I2S_SUPPORT /*!< I2S support */ 5357 5358 /******************* Bit definition for SPI_CR1 register ********************/ 5359 #define SPI_CR1_CPHA_Pos (0U) 5360 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 5361 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 5362 #define SPI_CR1_CPOL_Pos (1U) 5363 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 5364 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 5365 #define SPI_CR1_MSTR_Pos (2U) 5366 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 5367 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 5368 5369 #define SPI_CR1_BR_Pos (3U) 5370 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 5371 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 5372 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 5373 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 5374 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 5375 5376 #define SPI_CR1_SPE_Pos (6U) 5377 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 5378 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 5379 #define SPI_CR1_LSBFIRST_Pos (7U) 5380 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 5381 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 5382 #define SPI_CR1_SSI_Pos (8U) 5383 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 5384 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 5385 #define SPI_CR1_SSM_Pos (9U) 5386 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 5387 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 5388 #define SPI_CR1_RXONLY_Pos (10U) 5389 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 5390 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 5391 #define SPI_CR1_CRCL_Pos (11U) 5392 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 5393 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 5394 #define SPI_CR1_CRCNEXT_Pos (12U) 5395 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 5396 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 5397 #define SPI_CR1_CRCEN_Pos (13U) 5398 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 5399 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 5400 #define SPI_CR1_BIDIOE_Pos (14U) 5401 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 5402 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 5403 #define SPI_CR1_BIDIMODE_Pos (15U) 5404 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 5405 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 5406 5407 /******************* Bit definition for SPI_CR2 register ********************/ 5408 #define SPI_CR2_RXDMAEN_Pos (0U) 5409 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 5410 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 5411 #define SPI_CR2_TXDMAEN_Pos (1U) 5412 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 5413 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 5414 #define SPI_CR2_SSOE_Pos (2U) 5415 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 5416 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 5417 #define SPI_CR2_NSSP_Pos (3U) 5418 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 5419 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 5420 #define SPI_CR2_FRF_Pos (4U) 5421 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 5422 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 5423 #define SPI_CR2_ERRIE_Pos (5U) 5424 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 5425 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 5426 #define SPI_CR2_RXNEIE_Pos (6U) 5427 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 5428 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 5429 #define SPI_CR2_TXEIE_Pos (7U) 5430 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 5431 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 5432 #define SPI_CR2_DS_Pos (8U) 5433 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 5434 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 5435 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 5436 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 5437 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 5438 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 5439 #define SPI_CR2_FRXTH_Pos (12U) 5440 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 5441 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 5442 #define SPI_CR2_LDMARX_Pos (13U) 5443 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 5444 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 5445 #define SPI_CR2_LDMATX_Pos (14U) 5446 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 5447 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 5448 5449 /******************** Bit definition for SPI_SR register ********************/ 5450 #define SPI_SR_RXNE_Pos (0U) 5451 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 5452 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 5453 #define SPI_SR_TXE_Pos (1U) 5454 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 5455 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 5456 #define SPI_SR_CHSIDE_Pos (2U) 5457 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 5458 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 5459 #define SPI_SR_UDR_Pos (3U) 5460 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 5461 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5462 #define SPI_SR_CRCERR_Pos (4U) 5463 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5464 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5465 #define SPI_SR_MODF_Pos (5U) 5466 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5467 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5468 #define SPI_SR_OVR_Pos (6U) 5469 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5470 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5471 #define SPI_SR_BSY_Pos (7U) 5472 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5473 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5474 #define SPI_SR_FRE_Pos (8U) 5475 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5476 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 5477 #define SPI_SR_FRLVL_Pos (9U) 5478 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 5479 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 5480 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 5481 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 5482 #define SPI_SR_FTLVL_Pos (11U) 5483 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 5484 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 5485 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 5486 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 5487 5488 /******************** Bit definition for SPI_DR register ********************/ 5489 #define SPI_DR_DR_Pos (0U) 5490 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5491 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 5492 5493 /******************* Bit definition for SPI_CRCPR register ******************/ 5494 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5495 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5496 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 5497 5498 /****************** Bit definition for SPI_RXCRCR register ******************/ 5499 #define SPI_RXCRCR_RXCRC_Pos (0U) 5500 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5501 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 5502 5503 /****************** Bit definition for SPI_TXCRCR register ******************/ 5504 #define SPI_TXCRCR_TXCRC_Pos (0U) 5505 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5506 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 5507 5508 /****************** Bit definition for SPI_I2SCFGR register *****************/ 5509 #define SPI_I2SCFGR_CHLEN_Pos (0U) 5510 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 5511 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 5512 #define SPI_I2SCFGR_DATLEN_Pos (1U) 5513 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 5514 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 5515 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 5516 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 5517 #define SPI_I2SCFGR_CKPOL_Pos (3U) 5518 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 5519 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 5520 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 5521 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 5522 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 5523 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 5524 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 5525 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 5526 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 5527 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 5528 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 5529 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 5530 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 5531 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 5532 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 5533 #define SPI_I2SCFGR_I2SE_Pos (10U) 5534 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 5535 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 5536 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 5537 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 5538 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 5539 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 5540 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 5541 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 5542 5543 /****************** Bit definition for SPI_I2SPR register *******************/ 5544 #define SPI_I2SPR_I2SDIV_Pos (0U) 5545 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 5546 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 5547 #define SPI_I2SPR_ODD_Pos (8U) 5548 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 5549 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 5550 #define SPI_I2SPR_MCKOE_Pos (9U) 5551 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 5552 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 5553 5554 /******************************************************************************/ 5555 /* */ 5556 /* SYSCFG */ 5557 /* */ 5558 /******************************************************************************/ 5559 #define SYSCFG_CDEN_SUPPORT 5560 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 5561 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 5562 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 5563 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5564 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 5565 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 5566 #define SYSCFG_CFGR1_PA11_RMP_Pos (3U) 5567 #define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */ 5568 #define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */ 5569 #define SYSCFG_CFGR1_PA12_RMP_Pos (4U) 5570 #define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */ 5571 #define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */ 5572 #define SYSCFG_CFGR1_IR_POL_Pos (5U) 5573 #define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */ 5574 #define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */ 5575 #define SYSCFG_CFGR1_IR_MOD_Pos (6U) 5576 #define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */ 5577 #define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */ 5578 #define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */ 5579 #define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */ 5580 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) 5581 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ 5582 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ 5583 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 5584 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 5585 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 5586 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 5587 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 5588 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 5589 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 5590 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 5591 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 5592 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 5593 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 5594 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 5595 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 5596 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 5597 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ 5598 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) 5599 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ 5600 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */ 5601 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U) 5602 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */ 5603 #define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */ 5604 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U) 5605 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */ 5606 #define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */ 5607 5608 /****************** Bit definition for SYSCFG_CFGR2 register ****************/ 5609 #define SYSCFG_CFGR2_CLL_Pos (0U) 5610 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 5611 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 5612 #define SYSCFG_CFGR2_SPL_Pos (1U) 5613 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ 5614 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 5615 #define SYSCFG_CFGR2_ECCL_Pos (3U) 5616 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ 5617 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */ 5618 #define SYSCFG_CFGR2_SPF_Pos (8U) 5619 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ 5620 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */ 5621 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ 5622 5623 #define SYSCFG_CFGR2_PA1_CDEN_Pos (16U) 5624 #define SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */ 5625 #define SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk /*!< PA[1] Clamping Diode Enable */ 5626 #define SYSCFG_CFGR2_PA3_CDEN_Pos (17U) 5627 #define SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */ 5628 #define SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk /*!< PA[3] Clamping Diode Enable */ 5629 #define SYSCFG_CFGR2_PA5_CDEN_Pos (18U) 5630 #define SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */ 5631 #define SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk /*!< PA[5] Clamping Diode Enable */ 5632 #define SYSCFG_CFGR2_PA6_CDEN_Pos (19U) 5633 #define SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */ 5634 #define SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk /*!< PA[6] Clamping Diode Enable */ 5635 #define SYSCFG_CFGR2_PA13_CDEN_Pos (20U) 5636 #define SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */ 5637 #define SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk /*!< PA[13] Clamping Diode Enable */ 5638 #define SYSCFG_CFGR2_PB0_CDEN_Pos (21U) 5639 #define SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */ 5640 #define SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk /*!< PB[0] Clamping Diode Enable */ 5641 #define SYSCFG_CFGR2_PB1_CDEN_Pos (22U) 5642 #define SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */ 5643 #define SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk /*!< PB[1] Clamping Diode Enable */ 5644 #define SYSCFG_CFGR2_PB2_CDEN_Pos (23U) 5645 #define SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */ 5646 #define SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk /*!< PB[2] Clamping Diode Enable */ 5647 /***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/ 5648 #define SYSCFG_ITLINE0_SR_EWDG_Pos (0U) 5649 #define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */ 5650 #define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */ 5651 #define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) 5652 #define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ 5653 #define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ 5654 #define SYSCFG_ITLINE2_SR_RTC_Pos (1U) 5655 #define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ 5656 #define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */ 5657 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) 5658 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ 5659 #define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ 5660 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) 5661 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ 5662 #define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ 5663 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) 5664 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ 5665 #define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ 5666 #define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) 5667 #define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ 5668 #define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ 5669 #define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) 5670 #define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ 5671 #define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ 5672 #define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) 5673 #define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ 5674 #define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ 5675 #define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) 5676 #define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ 5677 #define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ 5678 #define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) 5679 #define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ 5680 #define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ 5681 #define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) 5682 #define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ 5683 #define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ 5684 #define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) 5685 #define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ 5686 #define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ 5687 #define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) 5688 #define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ 5689 #define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ 5690 #define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) 5691 #define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ 5692 #define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ 5693 #define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) 5694 #define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ 5695 #define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ 5696 #define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) 5697 #define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ 5698 #define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ 5699 #define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) 5700 #define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ 5701 #define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ 5702 #define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) 5703 #define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ 5704 #define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ 5705 #define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) 5706 #define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ 5707 #define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ 5708 #define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) 5709 #define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ 5710 #define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ 5711 #define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) 5712 #define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ 5713 #define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ 5714 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) 5715 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ 5716 #define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ 5717 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) 5718 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ 5719 #define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ 5720 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) 5721 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ 5722 #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ 5723 #define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) 5724 #define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ 5725 #define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ 5726 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) 5727 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ 5728 #define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ 5729 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) 5730 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ 5731 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ 5732 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) 5733 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ 5734 #define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ 5735 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) 5736 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ 5737 #define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ 5738 #define SYSCFG_ITLINE12_SR_ADC_Pos (0U) 5739 #define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ 5740 #define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ 5741 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) 5742 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ 5743 #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ 5744 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) 5745 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ 5746 #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ 5747 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) 5748 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ 5749 #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ 5750 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) 5751 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ 5752 #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ 5753 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) 5754 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ 5755 #define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ 5756 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) 5757 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ 5758 #define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ 5759 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) 5760 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ 5761 #define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ 5762 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) 5763 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ 5764 #define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ 5765 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) 5766 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ 5767 #define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ 5768 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) 5769 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ 5770 #define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ 5771 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) 5772 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ 5773 #define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ 5774 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) 5775 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ 5776 #define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ 5777 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) 5778 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ 5779 #define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ 5780 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) 5781 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ 5782 #define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/ 5783 #define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) 5784 #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ 5785 #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ 5786 #define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) 5787 #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ 5788 #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ 5789 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) 5790 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ 5791 #define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ 5792 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) 5793 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ 5794 #define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ 5795 5796 /******************************************************************************/ 5797 /* */ 5798 /* TIM */ 5799 /* */ 5800 /******************************************************************************/ 5801 /******************* Bit definition for TIM_CR1 register ********************/ 5802 #define TIM_CR1_CEN_Pos (0U) 5803 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 5804 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 5805 #define TIM_CR1_UDIS_Pos (1U) 5806 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 5807 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 5808 #define TIM_CR1_URS_Pos (2U) 5809 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 5810 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 5811 #define TIM_CR1_OPM_Pos (3U) 5812 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 5813 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 5814 #define TIM_CR1_DIR_Pos (4U) 5815 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 5816 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 5817 5818 #define TIM_CR1_CMS_Pos (5U) 5819 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 5820 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 5821 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 5822 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 5823 5824 #define TIM_CR1_ARPE_Pos (7U) 5825 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 5826 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 5827 5828 #define TIM_CR1_CKD_Pos (8U) 5829 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 5830 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 5831 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 5832 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 5833 5834 #define TIM_CR1_UIFREMAP_Pos (11U) 5835 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 5836 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 5837 5838 /******************* Bit definition for TIM_CR2 register ********************/ 5839 #define TIM_CR2_CCPC_Pos (0U) 5840 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 5841 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 5842 #define TIM_CR2_CCUS_Pos (2U) 5843 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 5844 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 5845 #define TIM_CR2_CCDS_Pos (3U) 5846 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 5847 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 5848 5849 #define TIM_CR2_MMS_Pos (4U) 5850 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 5851 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5852 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 5853 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 5854 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 5855 5856 #define TIM_CR2_TI1S_Pos (7U) 5857 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 5858 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 5859 #define TIM_CR2_OIS1_Pos (8U) 5860 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 5861 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 5862 #define TIM_CR2_OIS1N_Pos (9U) 5863 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 5864 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 5865 #define TIM_CR2_OIS2_Pos (10U) 5866 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 5867 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 5868 #define TIM_CR2_OIS2N_Pos (11U) 5869 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 5870 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 5871 #define TIM_CR2_OIS3_Pos (12U) 5872 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 5873 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 5874 #define TIM_CR2_OIS3N_Pos (13U) 5875 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 5876 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 5877 #define TIM_CR2_OIS4_Pos (14U) 5878 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 5879 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 5880 #define TIM_CR2_OIS5_Pos (16U) 5881 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 5882 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 5883 #define TIM_CR2_OIS6_Pos (18U) 5884 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 5885 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 5886 5887 #define TIM_CR2_MMS2_Pos (20U) 5888 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 5889 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5890 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 5891 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 5892 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 5893 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 5894 5895 /******************* Bit definition for TIM_SMCR register *******************/ 5896 #define TIM_SMCR_SMS_Pos (0U) 5897 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 5898 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 5899 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 5900 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 5901 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 5902 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 5903 5904 #define TIM_SMCR_OCCS_Pos (3U) 5905 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 5906 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 5907 5908 #define TIM_SMCR_TS_Pos (4U) 5909 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ 5910 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 5911 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 5912 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 5913 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 5914 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ 5915 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ 5916 5917 #define TIM_SMCR_MSM_Pos (7U) 5918 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 5919 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 5920 5921 #define TIM_SMCR_ETF_Pos (8U) 5922 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 5923 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 5924 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 5925 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 5926 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 5927 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5928 5929 #define TIM_SMCR_ETPS_Pos (12U) 5930 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5931 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5932 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5933 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5934 5935 #define TIM_SMCR_ECE_Pos (14U) 5936 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5937 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5938 #define TIM_SMCR_ETP_Pos (15U) 5939 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5940 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5941 5942 /******************* Bit definition for TIM_DIER register *******************/ 5943 #define TIM_DIER_UIE_Pos (0U) 5944 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5945 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5946 #define TIM_DIER_CC1IE_Pos (1U) 5947 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5948 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5949 #define TIM_DIER_CC2IE_Pos (2U) 5950 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5951 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5952 #define TIM_DIER_CC3IE_Pos (3U) 5953 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5954 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5955 #define TIM_DIER_CC4IE_Pos (4U) 5956 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5957 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5958 #define TIM_DIER_COMIE_Pos (5U) 5959 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 5960 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 5961 #define TIM_DIER_TIE_Pos (6U) 5962 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5963 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5964 #define TIM_DIER_BIE_Pos (7U) 5965 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 5966 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 5967 #define TIM_DIER_UDE_Pos (8U) 5968 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5969 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5970 #define TIM_DIER_CC1DE_Pos (9U) 5971 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5972 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5973 #define TIM_DIER_CC2DE_Pos (10U) 5974 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5975 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5976 #define TIM_DIER_CC3DE_Pos (11U) 5977 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5978 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5979 #define TIM_DIER_CC4DE_Pos (12U) 5980 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5981 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5982 #define TIM_DIER_COMDE_Pos (13U) 5983 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 5984 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 5985 #define TIM_DIER_TDE_Pos (14U) 5986 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5987 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5988 5989 /******************** Bit definition for TIM_SR register ********************/ 5990 #define TIM_SR_UIF_Pos (0U) 5991 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5992 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5993 #define TIM_SR_CC1IF_Pos (1U) 5994 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5995 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5996 #define TIM_SR_CC2IF_Pos (2U) 5997 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5998 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5999 #define TIM_SR_CC3IF_Pos (3U) 6000 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 6001 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 6002 #define TIM_SR_CC4IF_Pos (4U) 6003 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 6004 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 6005 #define TIM_SR_COMIF_Pos (5U) 6006 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 6007 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 6008 #define TIM_SR_TIF_Pos (6U) 6009 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 6010 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 6011 #define TIM_SR_BIF_Pos (7U) 6012 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 6013 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 6014 #define TIM_SR_B2IF_Pos (8U) 6015 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 6016 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 6017 #define TIM_SR_CC1OF_Pos (9U) 6018 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 6019 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 6020 #define TIM_SR_CC2OF_Pos (10U) 6021 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 6022 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 6023 #define TIM_SR_CC3OF_Pos (11U) 6024 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 6025 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 6026 #define TIM_SR_CC4OF_Pos (12U) 6027 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 6028 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 6029 #define TIM_SR_SBIF_Pos (13U) 6030 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 6031 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 6032 #define TIM_SR_CC5IF_Pos (16U) 6033 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 6034 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 6035 #define TIM_SR_CC6IF_Pos (17U) 6036 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 6037 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 6038 6039 6040 /******************* Bit definition for TIM_EGR register ********************/ 6041 #define TIM_EGR_UG_Pos (0U) 6042 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 6043 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 6044 #define TIM_EGR_CC1G_Pos (1U) 6045 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 6046 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 6047 #define TIM_EGR_CC2G_Pos (2U) 6048 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 6049 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 6050 #define TIM_EGR_CC3G_Pos (3U) 6051 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 6052 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 6053 #define TIM_EGR_CC4G_Pos (4U) 6054 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 6055 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 6056 #define TIM_EGR_COMG_Pos (5U) 6057 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 6058 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 6059 #define TIM_EGR_TG_Pos (6U) 6060 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 6061 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 6062 #define TIM_EGR_BG_Pos (7U) 6063 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 6064 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 6065 #define TIM_EGR_B2G_Pos (8U) 6066 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 6067 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 6068 6069 6070 /****************** Bit definition for TIM_CCMR1 register *******************/ 6071 #define TIM_CCMR1_CC1S_Pos (0U) 6072 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 6073 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 6074 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 6075 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 6076 6077 #define TIM_CCMR1_OC1FE_Pos (2U) 6078 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 6079 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 6080 #define TIM_CCMR1_OC1PE_Pos (3U) 6081 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 6082 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 6083 6084 #define TIM_CCMR1_OC1M_Pos (4U) 6085 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 6086 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 6087 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 6088 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 6089 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 6090 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 6091 6092 #define TIM_CCMR1_OC1CE_Pos (7U) 6093 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 6094 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 6095 6096 #define TIM_CCMR1_CC2S_Pos (8U) 6097 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 6098 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 6099 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 6100 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 6101 6102 #define TIM_CCMR1_OC2FE_Pos (10U) 6103 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 6104 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 6105 #define TIM_CCMR1_OC2PE_Pos (11U) 6106 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 6107 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 6108 6109 #define TIM_CCMR1_OC2M_Pos (12U) 6110 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 6111 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 6112 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 6113 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 6114 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 6115 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 6116 6117 #define TIM_CCMR1_OC2CE_Pos (15U) 6118 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 6119 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 6120 6121 /*----------------------------------------------------------------------------*/ 6122 #define TIM_CCMR1_IC1PSC_Pos (2U) 6123 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 6124 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 6125 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 6126 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 6127 6128 #define TIM_CCMR1_IC1F_Pos (4U) 6129 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 6130 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 6131 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 6132 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 6133 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 6134 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 6135 6136 #define TIM_CCMR1_IC2PSC_Pos (10U) 6137 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 6138 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 6139 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 6140 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 6141 6142 #define TIM_CCMR1_IC2F_Pos (12U) 6143 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 6144 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 6145 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 6146 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 6147 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 6148 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 6149 6150 /****************** Bit definition for TIM_CCMR2 register *******************/ 6151 #define TIM_CCMR2_CC3S_Pos (0U) 6152 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 6153 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 6154 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 6155 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 6156 6157 #define TIM_CCMR2_OC3FE_Pos (2U) 6158 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 6159 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 6160 #define TIM_CCMR2_OC3PE_Pos (3U) 6161 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 6162 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 6163 6164 #define TIM_CCMR2_OC3M_Pos (4U) 6165 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 6166 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 6167 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 6168 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 6169 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 6170 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 6171 6172 #define TIM_CCMR2_OC3CE_Pos (7U) 6173 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 6174 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 6175 6176 #define TIM_CCMR2_CC4S_Pos (8U) 6177 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 6178 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 6179 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 6180 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 6181 6182 #define TIM_CCMR2_OC4FE_Pos (10U) 6183 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 6184 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 6185 #define TIM_CCMR2_OC4PE_Pos (11U) 6186 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 6187 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 6188 6189 #define TIM_CCMR2_OC4M_Pos (12U) 6190 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 6191 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 6192 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 6193 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 6194 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 6195 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 6196 6197 #define TIM_CCMR2_OC4CE_Pos (15U) 6198 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 6199 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 6200 6201 /*----------------------------------------------------------------------------*/ 6202 #define TIM_CCMR2_IC3PSC_Pos (2U) 6203 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 6204 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 6205 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 6206 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 6207 6208 #define TIM_CCMR2_IC3F_Pos (4U) 6209 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 6210 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 6211 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 6212 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 6213 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 6214 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 6215 6216 #define TIM_CCMR2_IC4PSC_Pos (10U) 6217 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 6218 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 6219 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 6220 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 6221 6222 #define TIM_CCMR2_IC4F_Pos (12U) 6223 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 6224 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 6225 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 6226 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 6227 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 6228 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 6229 6230 /****************** Bit definition for TIM_CCMR3 register *******************/ 6231 #define TIM_CCMR3_OC5FE_Pos (2U) 6232 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 6233 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 6234 #define TIM_CCMR3_OC5PE_Pos (3U) 6235 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 6236 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 6237 6238 #define TIM_CCMR3_OC5M_Pos (4U) 6239 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 6240 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 6241 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 6242 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 6243 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 6244 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 6245 6246 #define TIM_CCMR3_OC5CE_Pos (7U) 6247 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 6248 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 6249 6250 #define TIM_CCMR3_OC6FE_Pos (10U) 6251 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 6252 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 6253 #define TIM_CCMR3_OC6PE_Pos (11U) 6254 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 6255 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 6256 6257 #define TIM_CCMR3_OC6M_Pos (12U) 6258 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 6259 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 6260 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 6261 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 6262 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 6263 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 6264 6265 #define TIM_CCMR3_OC6CE_Pos (15U) 6266 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 6267 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 6268 6269 /******************* Bit definition for TIM_CCER register *******************/ 6270 #define TIM_CCER_CC1E_Pos (0U) 6271 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 6272 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 6273 #define TIM_CCER_CC1P_Pos (1U) 6274 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 6275 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 6276 #define TIM_CCER_CC1NE_Pos (2U) 6277 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 6278 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 6279 #define TIM_CCER_CC1NP_Pos (3U) 6280 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 6281 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 6282 #define TIM_CCER_CC2E_Pos (4U) 6283 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 6284 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 6285 #define TIM_CCER_CC2P_Pos (5U) 6286 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 6287 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 6288 #define TIM_CCER_CC2NE_Pos (6U) 6289 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 6290 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 6291 #define TIM_CCER_CC2NP_Pos (7U) 6292 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 6293 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 6294 #define TIM_CCER_CC3E_Pos (8U) 6295 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 6296 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 6297 #define TIM_CCER_CC3P_Pos (9U) 6298 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 6299 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 6300 #define TIM_CCER_CC3NE_Pos (10U) 6301 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 6302 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 6303 #define TIM_CCER_CC3NP_Pos (11U) 6304 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 6305 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 6306 #define TIM_CCER_CC4E_Pos (12U) 6307 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 6308 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 6309 #define TIM_CCER_CC4P_Pos (13U) 6310 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 6311 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 6312 #define TIM_CCER_CC4NP_Pos (15U) 6313 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 6314 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 6315 #define TIM_CCER_CC5E_Pos (16U) 6316 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 6317 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 6318 #define TIM_CCER_CC5P_Pos (17U) 6319 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 6320 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 6321 #define TIM_CCER_CC6E_Pos (20U) 6322 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 6323 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 6324 #define TIM_CCER_CC6P_Pos (21U) 6325 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 6326 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 6327 6328 /******************* Bit definition for TIM_CNT register ********************/ 6329 #define TIM_CNT_CNT_Pos (0U) 6330 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 6331 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 6332 #define TIM_CNT_UIFCPY_Pos (31U) 6333 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 6334 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 6335 6336 /******************* Bit definition for TIM_PSC register ********************/ 6337 #define TIM_PSC_PSC_Pos (0U) 6338 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 6339 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 6340 6341 /******************* Bit definition for TIM_ARR register ********************/ 6342 #define TIM_ARR_ARR_Pos (0U) 6343 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 6344 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 6345 6346 /******************* Bit definition for TIM_RCR register ********************/ 6347 #define TIM_RCR_REP_Pos (0U) 6348 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 6349 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 6350 6351 /******************* Bit definition for TIM_CCR1 register *******************/ 6352 #define TIM_CCR1_CCR1_Pos (0U) 6353 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 6354 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 6355 6356 /******************* Bit definition for TIM_CCR2 register *******************/ 6357 #define TIM_CCR2_CCR2_Pos (0U) 6358 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 6359 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 6360 6361 /******************* Bit definition for TIM_CCR3 register *******************/ 6362 #define TIM_CCR3_CCR3_Pos (0U) 6363 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 6364 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 6365 6366 /******************* Bit definition for TIM_CCR4 register *******************/ 6367 #define TIM_CCR4_CCR4_Pos (0U) 6368 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 6369 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 6370 6371 /******************* Bit definition for TIM_CCR5 register *******************/ 6372 #define TIM_CCR5_CCR5_Pos (0U) 6373 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 6374 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 6375 #define TIM_CCR5_GC5C1_Pos (29U) 6376 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 6377 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 6378 #define TIM_CCR5_GC5C2_Pos (30U) 6379 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 6380 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 6381 #define TIM_CCR5_GC5C3_Pos (31U) 6382 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 6383 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 6384 6385 /******************* Bit definition for TIM_CCR6 register *******************/ 6386 #define TIM_CCR6_CCR6_Pos (0U) 6387 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 6388 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 6389 6390 /******************* Bit definition for TIM_BDTR register *******************/ 6391 #define TIM_BDTR_DTG_Pos (0U) 6392 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 6393 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 6394 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 6395 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 6396 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 6397 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 6398 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 6399 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 6400 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 6401 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 6402 6403 #define TIM_BDTR_LOCK_Pos (8U) 6404 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 6405 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 6406 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 6407 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 6408 6409 #define TIM_BDTR_OSSI_Pos (10U) 6410 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 6411 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 6412 #define TIM_BDTR_OSSR_Pos (11U) 6413 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 6414 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 6415 #define TIM_BDTR_BKE_Pos (12U) 6416 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 6417 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 6418 #define TIM_BDTR_BKP_Pos (13U) 6419 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 6420 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 6421 #define TIM_BDTR_AOE_Pos (14U) 6422 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 6423 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 6424 #define TIM_BDTR_MOE_Pos (15U) 6425 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 6426 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 6427 6428 #define TIM_BDTR_BKF_Pos (16U) 6429 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 6430 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 6431 #define TIM_BDTR_BK2F_Pos (20U) 6432 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 6433 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 6434 6435 #define TIM_BDTR_BK2E_Pos (24U) 6436 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 6437 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 6438 #define TIM_BDTR_BK2P_Pos (25U) 6439 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 6440 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 6441 6442 #define TIM_BDTR_BKDSRM_Pos (26U) 6443 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ 6444 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ 6445 #define TIM_BDTR_BK2DSRM_Pos (27U) 6446 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ 6447 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ 6448 6449 #define TIM_BDTR_BKBID_Pos (28U) 6450 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ 6451 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ 6452 #define TIM_BDTR_BK2BID_Pos (29U) 6453 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ 6454 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ 6455 6456 /******************* Bit definition for TIM_DCR register ********************/ 6457 #define TIM_DCR_DBA_Pos (0U) 6458 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 6459 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 6460 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 6461 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 6462 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 6463 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 6464 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 6465 6466 #define TIM_DCR_DBL_Pos (8U) 6467 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 6468 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 6469 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 6470 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 6471 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 6472 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 6473 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 6474 6475 /******************* Bit definition for TIM_DMAR register *******************/ 6476 #define TIM_DMAR_DMAB_Pos (0U) 6477 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 6478 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 6479 6480 /******************* Bit definition for TIM1_OR1 register *******************/ 6481 #define TIM1_OR1_OCREF_CLR_Pos (0U) 6482 #define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */ 6483 #define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */ 6484 6485 /******************* Bit definition for TIM1_AF1 register *******************/ 6486 #define TIM1_AF1_BKINE_Pos (0U) 6487 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ 6488 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 6489 #define TIM1_AF1_BKCMP1E_Pos (1U) 6490 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 6491 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 6492 #define TIM1_AF1_BKCMP2E_Pos (2U) 6493 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 6494 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 6495 #define TIM1_AF1_BKINP_Pos (9U) 6496 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ 6497 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 6498 #define TIM1_AF1_BKCMP1P_Pos (10U) 6499 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 6500 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 6501 #define TIM1_AF1_BKCMP2P_Pos (11U) 6502 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 6503 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 6504 6505 #define TIM1_AF1_ETRSEL_Pos (14U) 6506 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 6507 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */ 6508 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 6509 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 6510 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 6511 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 6512 6513 /******************* Bit definition for TIM1_AF2 register *******************/ 6514 #define TIM1_AF2_BK2INE_Pos (0U) 6515 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */ 6516 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ 6517 #define TIM1_AF2_BK2CMP1E_Pos (1U) 6518 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */ 6519 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ 6520 #define TIM1_AF2_BK2CMP2E_Pos (2U) 6521 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */ 6522 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ 6523 #define TIM1_AF2_BK2INP_Pos (9U) 6524 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */ 6525 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ 6526 #define TIM1_AF2_BK2CMP1P_Pos (10U) 6527 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */ 6528 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ 6529 #define TIM1_AF2_BK2CMP2P_Pos (11U) 6530 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */ 6531 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ 6532 6533 6534 /******************* Bit definition for TIM3_OR1 register *******************/ 6535 #define TIM3_OR1_OCREF_CLR_Pos (0U) 6536 #define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */ 6537 #define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */ 6538 6539 /******************* Bit definition for TIM3_AF1 register *******************/ 6540 #define TIM3_AF1_ETRSEL_Pos (14U) 6541 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 6542 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */ 6543 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 6544 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 6545 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 6546 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 6547 6548 /******************* Bit definition for TIM14_AF1 register *******************/ 6549 #define TIM14_AF1_ETRSEL_Pos (14U) 6550 #define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 6551 #define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM14 ETR source selection) */ 6552 #define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 6553 #define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 6554 #define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 6555 #define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 6556 6557 /******************* Bit definition for TIM15_AF1 register ******************/ 6558 #define TIM15_AF1_BKINE_Pos (0U) 6559 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */ 6560 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 6561 #define TIM15_AF1_BKCMP1E_Pos (1U) 6562 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 6563 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 6564 #define TIM15_AF1_BKCMP2E_Pos (2U) 6565 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 6566 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 6567 #define TIM15_AF1_BKINP_Pos (9U) 6568 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */ 6569 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 6570 #define TIM15_AF1_BKCMP1P_Pos (10U) 6571 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 6572 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 6573 #define TIM15_AF1_BKCMP2P_Pos (11U) 6574 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 6575 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 6576 6577 /******************* Bit definition for TIM16_AF1 register ******************/ 6578 #define TIM16_AF1_BKINE_Pos (0U) 6579 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */ 6580 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 6581 #define TIM16_AF1_BKCMP1E_Pos (1U) 6582 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 6583 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 6584 #define TIM16_AF1_BKCMP2E_Pos (2U) 6585 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 6586 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 6587 #define TIM16_AF1_BKINP_Pos (9U) 6588 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */ 6589 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 6590 #define TIM16_AF1_BKCMP1P_Pos (10U) 6591 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 6592 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 6593 #define TIM16_AF1_BKCMP2P_Pos (11U) 6594 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 6595 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 6596 6597 /******************* Bit definition for TIM17_AF1 register ******************/ 6598 #define TIM17_AF1_BKINE_Pos (0U) 6599 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */ 6600 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 6601 #define TIM17_AF1_BKCMP1E_Pos (1U) 6602 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 6603 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 6604 #define TIM17_AF1_BKCMP2E_Pos (2U) 6605 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 6606 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 6607 #define TIM17_AF1_BKINP_Pos (9U) 6608 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */ 6609 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 6610 #define TIM17_AF1_BKCMP1P_Pos (10U) 6611 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 6612 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 6613 #define TIM17_AF1_BKCMP2P_Pos (11U) 6614 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 6615 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 6616 6617 /******************* Bit definition for TIM_TISEL register *********************/ 6618 #define TIM_TISEL_TI1SEL_Pos (0U) 6619 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ 6620 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/ 6621 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */ 6622 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */ 6623 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */ 6624 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */ 6625 6626 #define TIM_TISEL_TI2SEL_Pos (8U) 6627 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */ 6628 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/ 6629 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */ 6630 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */ 6631 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */ 6632 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */ 6633 6634 #define TIM_TISEL_TI3SEL_Pos (16U) 6635 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */ 6636 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/ 6637 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */ 6638 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */ 6639 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */ 6640 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */ 6641 6642 #define TIM_TISEL_TI4SEL_Pos (24U) 6643 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */ 6644 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/ 6645 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */ 6646 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */ 6647 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */ 6648 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */ 6649 6650 6651 6652 /******************************************************************************/ 6653 /* */ 6654 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 6655 /* */ 6656 /******************************************************************************/ 6657 /****************** Bit definition for USART_CR1 register *******************/ 6658 #define USART_CR1_UE_Pos (0U) 6659 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 6660 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 6661 #define USART_CR1_UESM_Pos (1U) 6662 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 6663 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 6664 #define USART_CR1_RE_Pos (2U) 6665 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 6666 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 6667 #define USART_CR1_TE_Pos (3U) 6668 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 6669 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 6670 #define USART_CR1_IDLEIE_Pos (4U) 6671 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 6672 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 6673 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U) 6674 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */ 6675 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */ 6676 #define USART_CR1_TCIE_Pos (6U) 6677 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 6678 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 6679 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) 6680 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ 6681 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ 6682 #define USART_CR1_PEIE_Pos (8U) 6683 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 6684 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 6685 #define USART_CR1_PS_Pos (9U) 6686 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 6687 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 6688 #define USART_CR1_PCE_Pos (10U) 6689 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 6690 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 6691 #define USART_CR1_WAKE_Pos (11U) 6692 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 6693 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 6694 #define USART_CR1_M_Pos (12U) 6695 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 6696 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 6697 #define USART_CR1_M0_Pos (12U) 6698 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 6699 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 6700 #define USART_CR1_MME_Pos (13U) 6701 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 6702 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 6703 #define USART_CR1_CMIE_Pos (14U) 6704 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 6705 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 6706 #define USART_CR1_OVER8_Pos (15U) 6707 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 6708 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 6709 #define USART_CR1_DEDT_Pos (16U) 6710 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 6711 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 6712 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 6713 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 6714 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 6715 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 6716 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 6717 #define USART_CR1_DEAT_Pos (21U) 6718 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 6719 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 6720 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 6721 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 6722 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 6723 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 6724 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 6725 #define USART_CR1_RTOIE_Pos (26U) 6726 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 6727 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 6728 #define USART_CR1_EOBIE_Pos (27U) 6729 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 6730 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 6731 #define USART_CR1_M1_Pos (28U) 6732 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 6733 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 6734 #define USART_CR1_FIFOEN_Pos (29U) 6735 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ 6736 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ 6737 #define USART_CR1_TXFEIE_Pos (30U) 6738 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ 6739 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ 6740 #define USART_CR1_RXFFIE_Pos (31U) 6741 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ 6742 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ 6743 6744 /****************** Bit definition for USART_CR2 register *******************/ 6745 #define USART_CR2_SLVEN_Pos (0U) 6746 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ 6747 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ 6748 #define USART_CR2_DIS_NSS_Pos (3U) 6749 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ 6750 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */ 6751 #define USART_CR2_ADDM7_Pos (4U) 6752 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 6753 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 6754 #define USART_CR2_LBDL_Pos (5U) 6755 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 6756 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 6757 #define USART_CR2_LBDIE_Pos (6U) 6758 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 6759 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 6760 #define USART_CR2_LBCL_Pos (8U) 6761 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 6762 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 6763 #define USART_CR2_CPHA_Pos (9U) 6764 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 6765 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 6766 #define USART_CR2_CPOL_Pos (10U) 6767 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 6768 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 6769 #define USART_CR2_CLKEN_Pos (11U) 6770 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 6771 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 6772 #define USART_CR2_STOP_Pos (12U) 6773 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 6774 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 6775 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 6776 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 6777 #define USART_CR2_LINEN_Pos (14U) 6778 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 6779 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 6780 #define USART_CR2_SWAP_Pos (15U) 6781 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 6782 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 6783 #define USART_CR2_RXINV_Pos (16U) 6784 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 6785 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 6786 #define USART_CR2_TXINV_Pos (17U) 6787 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 6788 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 6789 #define USART_CR2_DATAINV_Pos (18U) 6790 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 6791 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 6792 #define USART_CR2_MSBFIRST_Pos (19U) 6793 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 6794 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 6795 #define USART_CR2_ABREN_Pos (20U) 6796 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 6797 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 6798 #define USART_CR2_ABRMODE_Pos (21U) 6799 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 6800 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 6801 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 6802 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 6803 #define USART_CR2_RTOEN_Pos (23U) 6804 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 6805 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 6806 #define USART_CR2_ADD_Pos (24U) 6807 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 6808 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6809 6810 /****************** Bit definition for USART_CR3 register *******************/ 6811 #define USART_CR3_EIE_Pos (0U) 6812 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6813 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6814 #define USART_CR3_IREN_Pos (1U) 6815 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6816 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6817 #define USART_CR3_IRLP_Pos (2U) 6818 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6819 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6820 #define USART_CR3_HDSEL_Pos (3U) 6821 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6822 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6823 #define USART_CR3_NACK_Pos (4U) 6824 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6825 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 6826 #define USART_CR3_SCEN_Pos (5U) 6827 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6828 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 6829 #define USART_CR3_DMAR_Pos (6U) 6830 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6831 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6832 #define USART_CR3_DMAT_Pos (7U) 6833 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6834 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6835 #define USART_CR3_RTSE_Pos (8U) 6836 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6837 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6838 #define USART_CR3_CTSE_Pos (9U) 6839 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6840 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6841 #define USART_CR3_CTSIE_Pos (10U) 6842 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6843 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6844 #define USART_CR3_ONEBIT_Pos (11U) 6845 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6846 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6847 #define USART_CR3_OVRDIS_Pos (12U) 6848 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 6849 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 6850 #define USART_CR3_DDRE_Pos (13U) 6851 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 6852 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 6853 #define USART_CR3_DEM_Pos (14U) 6854 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 6855 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 6856 #define USART_CR3_DEP_Pos (15U) 6857 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 6858 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 6859 #define USART_CR3_SCARCNT_Pos (17U) 6860 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 6861 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 6862 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 6863 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 6864 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 6865 #define USART_CR3_WUS_Pos (20U) 6866 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 6867 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 6868 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 6869 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 6870 #define USART_CR3_WUFIE_Pos (22U) 6871 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 6872 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 6873 #define USART_CR3_TXFTIE_Pos (23U) 6874 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ 6875 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ 6876 #define USART_CR3_TCBGTIE_Pos (24U) 6877 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 6878 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 6879 #define USART_CR3_RXFTCFG_Pos (25U) 6880 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ 6881 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ 6882 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ 6883 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ 6884 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ 6885 #define USART_CR3_RXFTIE_Pos (28U) 6886 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ 6887 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ 6888 #define USART_CR3_TXFTCFG_Pos (29U) 6889 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ 6890 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ 6891 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ 6892 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ 6893 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ 6894 6895 /****************** Bit definition for USART_BRR register *******************/ 6896 #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ 6897 6898 /****************** Bit definition for USART_GTPR register ******************/ 6899 #define USART_GTPR_PSC_Pos (0U) 6900 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6901 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6902 #define USART_GTPR_GT_Pos (8U) 6903 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6904 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 6905 6906 /******************* Bit definition for USART_RTOR register *****************/ 6907 #define USART_RTOR_RTO_Pos (0U) 6908 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 6909 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 6910 #define USART_RTOR_BLEN_Pos (24U) 6911 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 6912 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 6913 6914 /******************* Bit definition for USART_RQR register ******************/ 6915 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ 6916 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ 6917 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ 6918 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ 6919 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ 6920 6921 /******************* Bit definition for USART_ISR register ******************/ 6922 #define USART_ISR_PE_Pos (0U) 6923 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 6924 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 6925 #define USART_ISR_FE_Pos (1U) 6926 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 6927 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 6928 #define USART_ISR_NE_Pos (2U) 6929 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 6930 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 6931 #define USART_ISR_ORE_Pos (3U) 6932 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 6933 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 6934 #define USART_ISR_IDLE_Pos (4U) 6935 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 6936 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 6937 #define USART_ISR_RXNE_RXFNE_Pos (5U) 6938 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */ 6939 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */ 6940 #define USART_ISR_TC_Pos (6U) 6941 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 6942 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 6943 #define USART_ISR_TXE_TXFNF_Pos (7U) 6944 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */ 6945 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */ 6946 #define USART_ISR_LBDF_Pos (8U) 6947 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 6948 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 6949 #define USART_ISR_CTSIF_Pos (9U) 6950 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 6951 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 6952 #define USART_ISR_CTS_Pos (10U) 6953 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 6954 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 6955 #define USART_ISR_RTOF_Pos (11U) 6956 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 6957 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 6958 #define USART_ISR_EOBF_Pos (12U) 6959 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 6960 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 6961 #define USART_ISR_UDR_Pos (13U) 6962 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ 6963 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */ 6964 #define USART_ISR_ABRE_Pos (14U) 6965 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 6966 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 6967 #define USART_ISR_ABRF_Pos (15U) 6968 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 6969 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 6970 #define USART_ISR_BUSY_Pos (16U) 6971 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 6972 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 6973 #define USART_ISR_CMF_Pos (17U) 6974 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 6975 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 6976 #define USART_ISR_SBKF_Pos (18U) 6977 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 6978 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 6979 #define USART_ISR_RWU_Pos (19U) 6980 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 6981 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 6982 #define USART_ISR_WUF_Pos (20U) 6983 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 6984 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 6985 #define USART_ISR_TEACK_Pos (21U) 6986 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 6987 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 6988 #define USART_ISR_REACK_Pos (22U) 6989 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 6990 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 6991 #define USART_ISR_TXFE_Pos (23U) 6992 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ 6993 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */ 6994 #define USART_ISR_RXFF_Pos (24U) 6995 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ 6996 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */ 6997 #define USART_ISR_TCBGT_Pos (25U) 6998 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 6999 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ 7000 #define USART_ISR_RXFT_Pos (26U) 7001 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ 7002 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */ 7003 #define USART_ISR_TXFT_Pos (27U) 7004 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ 7005 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */ 7006 7007 /******************* Bit definition for USART_ICR register ******************/ 7008 #define USART_ICR_PECF_Pos (0U) 7009 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 7010 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 7011 #define USART_ICR_FECF_Pos (1U) 7012 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 7013 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 7014 #define USART_ICR_NECF_Pos (2U) 7015 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 7016 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ 7017 #define USART_ICR_ORECF_Pos (3U) 7018 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 7019 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 7020 #define USART_ICR_IDLECF_Pos (4U) 7021 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 7022 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 7023 #define USART_ICR_TXFECF_Pos (5U) 7024 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ 7025 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */ 7026 #define USART_ICR_TCCF_Pos (6U) 7027 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 7028 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 7029 #define USART_ICR_TCBGTCF_Pos (7U) 7030 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 7031 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 7032 #define USART_ICR_LBDCF_Pos (8U) 7033 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 7034 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 7035 #define USART_ICR_CTSCF_Pos (9U) 7036 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 7037 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 7038 #define USART_ICR_RTOCF_Pos (11U) 7039 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 7040 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 7041 #define USART_ICR_EOBCF_Pos (12U) 7042 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 7043 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 7044 #define USART_ICR_UDRCF_Pos (13U) 7045 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ 7046 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ 7047 #define USART_ICR_CMCF_Pos (17U) 7048 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 7049 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 7050 #define USART_ICR_WUCF_Pos (20U) 7051 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 7052 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 7053 7054 /******************* Bit definition for USART_RDR register ******************/ 7055 #define USART_RDR_RDR_Pos (0U) 7056 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 7057 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 7058 7059 /******************* Bit definition for USART_TDR register ******************/ 7060 #define USART_TDR_TDR_Pos (0U) 7061 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 7062 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 7063 7064 /******************* Bit definition for USART_PRESC register ****************/ 7065 #define USART_PRESC_PRESCALER_Pos (0U) 7066 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ 7067 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ 7068 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ 7069 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ 7070 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ 7071 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ 7072 7073 7074 /******************************************************************************/ 7075 /* */ 7076 /* Window WATCHDOG */ 7077 /* */ 7078 /******************************************************************************/ 7079 /******************* Bit definition for WWDG_CR register ********************/ 7080 #define WWDG_CR_T_Pos (0U) 7081 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 7082 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 7083 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 7084 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 7085 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 7086 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 7087 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 7088 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 7089 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 7090 7091 #define WWDG_CR_WDGA_Pos (7U) 7092 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 7093 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 7094 7095 /******************* Bit definition for WWDG_CFR register *******************/ 7096 #define WWDG_CFR_W_Pos (0U) 7097 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 7098 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 7099 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 7100 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 7101 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 7102 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 7103 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 7104 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 7105 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 7106 7107 #define WWDG_CFR_WDGTB_Pos (11U) 7108 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ 7109 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ 7110 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ 7111 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ 7112 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ 7113 7114 #define WWDG_CFR_EWI_Pos (9U) 7115 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 7116 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 7117 7118 /******************* Bit definition for WWDG_SR register ********************/ 7119 #define WWDG_SR_EWIF_Pos (0U) 7120 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 7121 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 7122 7123 /******************************************************************************/ 7124 /* */ 7125 /* Debug MCU */ 7126 /* */ 7127 /******************************************************************************/ 7128 /******************** Bit definition for DBG_IDCODE register *************/ 7129 #define DBG_IDCODE_DEV_ID_Pos (0U) 7130 #define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 7131 #define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk 7132 #define DBG_IDCODE_REV_ID_Pos (16U) 7133 #define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 7134 #define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk 7135 7136 /******************** Bit definition for DBG_CR register *****************/ 7137 #define DBG_CR_DBG_STOP_Pos (1U) 7138 #define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 7139 #define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk 7140 #define DBG_CR_DBG_STANDBY_Pos (2U) 7141 #define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 7142 #define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk 7143 7144 7145 /******************** Bit definition for DBG_APB_FZ1 register ***********/ 7146 #define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) 7147 #define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 7148 #define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk 7149 #define DBG_APB_FZ1_DBG_TIM6_STOP_Pos (4U) 7150 #define DBG_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 7151 #define DBG_APB_FZ1_DBG_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP_Msk 7152 #define DBG_APB_FZ1_DBG_TIM7_STOP_Pos (5U) 7153 #define DBG_APB_FZ1_DBG_TIM7_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 7154 #define DBG_APB_FZ1_DBG_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP_Msk 7155 #define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) 7156 #define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 7157 #define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk 7158 #define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) 7159 #define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 7160 #define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk 7161 #define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) 7162 #define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 7163 #define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk 7164 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) 7165 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ 7166 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk 7167 7168 /******************** Bit definition for DBG_APB_FZ2 register ************/ 7169 #define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) 7170 #define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 7171 #define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk 7172 #define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) 7173 #define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ 7174 #define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk 7175 #define DBG_APB_FZ2_DBG_TIM15_STOP_Pos (16U) 7176 #define DBG_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ 7177 #define DBG_APB_FZ2_DBG_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP_Msk 7178 #define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) 7179 #define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 7180 #define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk 7181 #define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) 7182 #define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 7183 #define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk 7184 7185 7186 /** @addtogroup Exported_macros 7187 * @{ 7188 */ 7189 7190 /******************************* ADC Instances ********************************/ 7191 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 7192 7193 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 7194 7195 7196 7197 7198 /******************************* CRC Instances ********************************/ 7199 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 7200 7201 7202 /******************************** DMA Instances *******************************/ 7203 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 7204 ((INSTANCE) == DMA1_Channel2) || \ 7205 ((INSTANCE) == DMA1_Channel3) || \ 7206 ((INSTANCE) == DMA1_Channel4) || \ 7207 ((INSTANCE) == DMA1_Channel5) || \ 7208 ((INSTANCE) == DMA1_Channel6) || \ 7209 ((INSTANCE) == DMA1_Channel7)) 7210 7211 /******************************** DMAMUX Instances ****************************/ 7212 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1) 7213 7214 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \ 7215 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \ 7216 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \ 7217 ((INSTANCE) == DMAMUX1_RequestGenerator3)) 7218 7219 /******************************* GPIO Instances *******************************/ 7220 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 7221 ((INSTANCE) == GPIOB) || \ 7222 ((INSTANCE) == GPIOC) || \ 7223 ((INSTANCE) == GPIOD) || \ 7224 ((INSTANCE) == GPIOF)) 7225 /******************************* GPIO AF Instances ****************************/ 7226 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 7227 7228 /**************************** GPIO Lock Instances *****************************/ 7229 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 7230 ((INSTANCE) == GPIOB) || \ 7231 ((INSTANCE) == GPIOC)) 7232 7233 /******************************** I2C Instances *******************************/ 7234 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 7235 ((INSTANCE) == I2C2)) 7236 7237 7238 /****************************** RTC Instances *********************************/ 7239 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 7240 7241 /****************************** SMBUS Instances *******************************/ 7242 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) 7243 7244 /****************************** WAKEUP_FROMSTOP Instances *******************************/ 7245 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) 7246 7247 /******************************** SPI Instances *******************************/ 7248 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 7249 ((INSTANCE) == SPI2)) 7250 7251 /******************************** SPI Instances *******************************/ 7252 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 7253 7254 7255 /****************** TIM Instances : All supported instances *******************/ 7256 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7257 ((INSTANCE) == TIM3) || \ 7258 ((INSTANCE) == TIM6) || \ 7259 ((INSTANCE) == TIM7) || \ 7260 ((INSTANCE) == TIM14) || \ 7261 ((INSTANCE) == TIM15) || \ 7262 ((INSTANCE) == TIM16) || \ 7263 ((INSTANCE) == TIM17)) 7264 7265 /****************** TIM Instances : supporting 32 bits counter ****************/ 7266 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0) 7267 7268 /****************** TIM Instances : supporting the break function *************/ 7269 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7270 ((INSTANCE) == TIM15) || \ 7271 ((INSTANCE) == TIM16) || \ 7272 ((INSTANCE) == TIM17)) 7273 7274 /************** TIM Instances : supporting Break source selection *************/ 7275 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7276 ((INSTANCE) == TIM15) || \ 7277 ((INSTANCE) == TIM16) || \ 7278 ((INSTANCE) == TIM17)) 7279 7280 /****************** TIM Instances : supporting 2 break inputs *****************/ 7281 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 7282 7283 /************* TIM Instances : at least 1 capture/compare channel *************/ 7284 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7285 ((INSTANCE) == TIM3) || \ 7286 ((INSTANCE) == TIM14) || \ 7287 ((INSTANCE) == TIM15) || \ 7288 ((INSTANCE) == TIM16) || \ 7289 ((INSTANCE) == TIM17)) 7290 7291 /************ TIM Instances : at least 2 capture/compare channels *************/ 7292 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7293 ((INSTANCE) == TIM3) || \ 7294 ((INSTANCE) == TIM15)) 7295 7296 /************ TIM Instances : at least 3 capture/compare channels *************/ 7297 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7298 ((INSTANCE) == TIM3)) 7299 7300 /************ TIM Instances : at least 4 capture/compare channels *************/ 7301 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7302 ((INSTANCE) == TIM3)) 7303 7304 /****************** TIM Instances : at least 5 capture/compare channels *******/ 7305 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 7306 7307 /****************** TIM Instances : at least 6 capture/compare channels *******/ 7308 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 7309 7310 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ 7311 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7312 ((INSTANCE) == TIM15) || \ 7313 ((INSTANCE) == TIM16) || \ 7314 ((INSTANCE) == TIM17)) 7315 7316 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 7317 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7318 ((INSTANCE) == TIM3) || \ 7319 ((INSTANCE) == TIM6) || \ 7320 ((INSTANCE) == TIM7) || \ 7321 ((INSTANCE) == TIM15) || \ 7322 ((INSTANCE) == TIM16) || \ 7323 ((INSTANCE) == TIM17)) 7324 7325 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 7326 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7327 ((INSTANCE) == TIM3) || \ 7328 ((INSTANCE) == TIM14) || \ 7329 ((INSTANCE) == TIM15) || \ 7330 ((INSTANCE) == TIM16) || \ 7331 ((INSTANCE) == TIM17)) 7332 7333 /******************** TIM Instances : DMA burst feature ***********************/ 7334 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7335 ((INSTANCE) == TIM3) || \ 7336 ((INSTANCE) == TIM15) || \ 7337 ((INSTANCE) == TIM16) || \ 7338 ((INSTANCE) == TIM17)) 7339 7340 /******************* TIM Instances : output(s) available **********************/ 7341 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 7342 ((((INSTANCE) == TIM1) && \ 7343 (((CHANNEL) == TIM_CHANNEL_1) || \ 7344 ((CHANNEL) == TIM_CHANNEL_2) || \ 7345 ((CHANNEL) == TIM_CHANNEL_3) || \ 7346 ((CHANNEL) == TIM_CHANNEL_4) || \ 7347 ((CHANNEL) == TIM_CHANNEL_5) || \ 7348 ((CHANNEL) == TIM_CHANNEL_6))) \ 7349 || \ 7350 (((INSTANCE) == TIM3) && \ 7351 (((CHANNEL) == TIM_CHANNEL_1) || \ 7352 ((CHANNEL) == TIM_CHANNEL_2) || \ 7353 ((CHANNEL) == TIM_CHANNEL_3) || \ 7354 ((CHANNEL) == TIM_CHANNEL_4))) \ 7355 || \ 7356 (((INSTANCE) == TIM14) && \ 7357 (((CHANNEL) == TIM_CHANNEL_1))) \ 7358 || \ 7359 (((INSTANCE) == TIM15) && \ 7360 (((CHANNEL) == TIM_CHANNEL_1) || \ 7361 ((CHANNEL) == TIM_CHANNEL_2))) \ 7362 || \ 7363 (((INSTANCE) == TIM16) && \ 7364 (((CHANNEL) == TIM_CHANNEL_1))) \ 7365 || \ 7366 (((INSTANCE) == TIM17) && \ 7367 (((CHANNEL) == TIM_CHANNEL_1)))) 7368 7369 /****************** TIM Instances : supporting complementary output(s) ********/ 7370 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 7371 ((((INSTANCE) == TIM1) && \ 7372 (((CHANNEL) == TIM_CHANNEL_1) || \ 7373 ((CHANNEL) == TIM_CHANNEL_2) || \ 7374 ((CHANNEL) == TIM_CHANNEL_3))) \ 7375 || \ 7376 (((INSTANCE) == TIM15) && \ 7377 ((CHANNEL) == TIM_CHANNEL_1)) \ 7378 || \ 7379 (((INSTANCE) == TIM16) && \ 7380 ((CHANNEL) == TIM_CHANNEL_1)) \ 7381 || \ 7382 (((INSTANCE) == TIM17) && \ 7383 ((CHANNEL) == TIM_CHANNEL_1))) 7384 7385 /****************** TIM Instances : supporting clock division *****************/ 7386 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7387 ((INSTANCE) == TIM3) || \ 7388 ((INSTANCE) == TIM14) || \ 7389 ((INSTANCE) == TIM15) || \ 7390 ((INSTANCE) == TIM16) || \ 7391 ((INSTANCE) == TIM17)) 7392 7393 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 7394 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7395 ((INSTANCE) == TIM3)) 7396 7397 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 7398 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7399 ((INSTANCE) == TIM3)) 7400 7401 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 7402 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7403 ((INSTANCE) == TIM3) || \ 7404 ((INSTANCE) == TIM15)) 7405 7406 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 7407 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7408 ((INSTANCE) == TIM3) || \ 7409 ((INSTANCE) == TIM15)) 7410 7411 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 7412 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 7413 7414 /****************** TIM Instances : supporting commutation event generation ***/ 7415 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7416 ((INSTANCE) == TIM15) || \ 7417 ((INSTANCE) == TIM16) || \ 7418 ((INSTANCE) == TIM17)) 7419 7420 /****************** TIM Instances : supporting counting mode selection ********/ 7421 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7422 ((INSTANCE) == TIM3)) 7423 7424 /****************** TIM Instances : supporting encoder interface **************/ 7425 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7426 ((INSTANCE) == TIM3)) 7427 7428 /****************** TIM Instances : supporting Hall sensor interface **********/ 7429 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7430 ((INSTANCE) == TIM3)) 7431 7432 /**************** TIM Instances : external trigger input available ************/ 7433 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7434 ((INSTANCE) == TIM3)) 7435 7436 /************* TIM Instances : supporting ETR source selection ***************/ 7437 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7438 ((INSTANCE) == TIM3)) 7439 7440 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 7441 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7442 ((INSTANCE) == TIM3) || \ 7443 ((INSTANCE) == TIM6) || \ 7444 ((INSTANCE) == TIM7) || \ 7445 ((INSTANCE) == TIM15)) 7446 7447 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 7448 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7449 ((INSTANCE) == TIM3) || \ 7450 ((INSTANCE) == TIM15)) 7451 7452 /****************** TIM Instances : supporting OCxREF clear *******************/ 7453 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7454 ((INSTANCE) == TIM3)) 7455 7456 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ 7457 #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7458 ((INSTANCE) == TIM3)) 7459 7460 /****************** TIM Instances : remapping capability **********************/ 7461 #define IS_TIM_REMAP_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 7462 7463 /****************** TIM Instances : supporting repetition counter *************/ 7464 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7465 ((INSTANCE) == TIM15) || \ 7466 ((INSTANCE) == TIM16) || \ 7467 ((INSTANCE) == TIM17)) 7468 7469 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 7470 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 7471 7472 /******************* TIM Instances : Timer input XOR function *****************/ 7473 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7474 ((INSTANCE) == TIM3) || \ 7475 ((INSTANCE) == TIM15)) 7476 7477 /******************* TIM Instances : Timer input selection ********************/ 7478 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 7479 ((INSTANCE) == TIM3) || \ 7480 ((INSTANCE) == TIM14) || \ 7481 ((INSTANCE) == TIM15) || \ 7482 ((INSTANCE) == TIM16) || \ 7483 ((INSTANCE) == TIM17)) 7484 7485 /************ TIM Instances : Advanced timers ********************************/ 7486 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 7487 7488 /******************** UART Instances : Asynchronous mode **********************/ 7489 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7490 ((INSTANCE) == USART2)) 7491 7492 /******************** USART Instances : Synchronous mode **********************/ 7493 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7494 ((INSTANCE) == USART2)) 7495 /****************** UART Instances : Hardware Flow control ********************/ 7496 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7497 ((INSTANCE) == USART2)) 7498 7499 /********************* USART Instances : Smard card mode ***********************/ 7500 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7501 /****************** UART Instances : Auto Baud Rate detection ****************/ 7502 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7503 /******************** UART Instances : Half-Duplex mode **********************/ 7504 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7505 ((INSTANCE) == USART2)) 7506 7507 /******************** UART Instances : LIN mode **********************/ 7508 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7509 /******************** UART Instances : Wake-up from Stop mode **********************/ 7510 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7511 7512 /****************** UART Instances : Driver Enable *****************/ 7513 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7514 ((INSTANCE) == USART2)) 7515 7516 /****************** UART Instances : SPI Slave selection mode ***************/ 7517 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 7518 ((INSTANCE) == USART2)) 7519 7520 /****************** UART Instances : Driver Enable *****************/ 7521 #define IS_UART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7522 7523 /*********************** UART Instances : IRDA mode ***************************/ 7524 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 7525 7526 #define IS_LPUART_INSTANCE(INSTANCE) (0U) 7527 7528 /****************************** IWDG Instances ********************************/ 7529 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 7530 7531 /****************************** WWDG Instances ********************************/ 7532 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 7533 7534 7535 /******************************************************************************/ 7536 /* For a painless codes migration between the STM32G0xx device product */ 7537 /* lines, the aliases defined below are put in place to overcome the */ 7538 /* differences in the interrupt handlers and IRQn definitions. */ 7539 /* No need to update developed interrupt code when moving across */ 7540 /* product lines within the same STM32G0 Family */ 7541 /******************************************************************************/ 7542 /* Aliases for IRQn_Type */ 7543 #define SVC_IRQn SVCall_IRQn 7544 7545 /** 7546 * @} 7547 */ 7548 7549 /** 7550 * @} 7551 */ 7552 7553 /** 7554 * @} 7555 */ 7556 7557 #ifdef __cplusplus 7558 } 7559 #endif /* __cplusplus */ 7560 7561 #endif /* STM32G050xx_H */ 7562 7563 /** 7564 * @} 7565 */ 7566 7567 /** 7568 * @} 7569 */ 7570
