Searched refs:RCC_CFGR_MCO_PLL (Results 1 – 25 of 76) sorted by relevance
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954 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)956 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
592 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
542 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
197 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
574 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
2907 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro2937 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
2937 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro2951 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
2967 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro2997 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3033 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3063 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3194 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3224 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3008 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3038 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3059 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3089 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3457 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3471 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3482 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3496 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
3879 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro3911 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7207 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7239 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7183 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7215 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7654 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7686 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
8104 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro8136 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
8080 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro8112 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7630 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7662 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
4883 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro4916 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
4876 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro4909 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7647 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7660 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
7737 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divid… macro7750 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
