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Searched refs:RCC_APB1ENR_CECEN (Results 1 – 25 of 33) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h1121 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1123 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1127 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
1613 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1614 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Dstm32f0xx_ll_bus.h146 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h939 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
941 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
948 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
1118 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1119 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Dstm32f1xx_ll_bus.h113 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2208 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
2210 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
2225 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
2566 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
2579 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Dstm32f3xx_ll_bus.h172 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1153 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1155 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
1198 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
1641 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1646 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Dstm32f7xx_ll_bus.h182 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_bus.h254 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
Dstm32f4xx_hal_rcc_ex.h4256 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4258 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
4320 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
4350 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
4370 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f100xb.h1327 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface c… macro
Dstm32f100xe.h1635 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface c… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h3710 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f051x8.h3735 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f071xb.h4187 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f042x6.h7479 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f048xx.h7455 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f072xb.h7974 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f091xc.h8445 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f098xx.h8421 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f078xx.h7950 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f378xx.h8013 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
Dstm32f373xc.h8109 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC clock enabl… macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f446xx.h10662 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h11180 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk macro

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