1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2016 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F0xx_LL_BUS_H
37 #define __STM32F0xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f0xx.h"
45
46 /** @addtogroup STM32F0xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
74 #if defined(DMA2)
75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
76 #endif /*DMA2*/
77 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
79 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
80 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
81 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
82 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
83 #if defined(GPIOD)
84 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
85 #endif /*GPIOD*/
86 #if defined(GPIOE)
87 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
88 #endif /*GPIOE*/
89 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
90 #if defined(TSC)
91 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
92 #endif /*TSC*/
93 /**
94 * @}
95 */
96
97 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
98 * @{
99 */
100 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
101 #if defined(TIM2)
102 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
103 #endif /*TIM2*/
104 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
105 #if defined(TIM6)
106 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
107 #endif /*TIM6*/
108 #if defined(TIM7)
109 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
110 #endif /*TIM7*/
111 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
112 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
113 #if defined(SPI2)
114 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
115 #endif /*SPI2*/
116 #if defined(USART2)
117 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
118 #endif /* USART2 */
119 #if defined(USART3)
120 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
121 #endif /* USART3 */
122 #if defined(USART4)
123 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
124 #endif /* USART4 */
125 #if defined(USART5)
126 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
127 #endif /* USART5 */
128 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
129 #if defined(I2C2)
130 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
131 #endif /*I2C2*/
132 #if defined(USB)
133 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
134 #endif /* USB */
135 #if defined(CAN)
136 #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
137 #endif /*CAN*/
138 #if defined(CRS)
139 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
140 #endif /*CRS*/
141 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
142 #if defined(DAC)
143 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
144 #endif /*DAC*/
145 #if defined(CEC)
146 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
147 #endif /*CEC*/
148 /**
149 * @}
150 */
151
152 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
153 * @{
154 */
155 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
156 #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
157 #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
158 #if defined(USART8)
159 #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
160 #endif /*USART8*/
161 #if defined(USART7)
162 #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
163 #endif /*USART7*/
164 #if defined(USART6)
165 #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
166 #endif /*USART6*/
167 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
168 #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
169 #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
170 #if defined(TIM15)
171 #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
172 #endif /*TIM15*/
173 #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
174 #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
175 #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
176 /**
177 * @}
178 */
179
180 /**
181 * @}
182 */
183
184 /* Exported macro ------------------------------------------------------------*/
185 /* Exported functions --------------------------------------------------------*/
186 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
187 * @{
188 */
189
190 /** @defgroup BUS_LL_EF_AHB1 AHB1
191 * @{
192 */
193
194 /**
195 * @brief Enable AHB1 peripherals clock.
196 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
197 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
198 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
199 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
200 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
201 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
202 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
203 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
204 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
205 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
206 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
207 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock
208 * @param Periphs This parameter can be a combination of the following values:
209 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
210 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
211 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
212 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
213 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
214 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
215 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
220 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
221 *
222 * (*) value not defined in all devices.
223 * @retval None
224 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)225 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
226 {
227 __IO uint32_t tmpreg;
228 SET_BIT(RCC->AHBENR, Periphs);
229 /* Delay after an RCC peripheral clock enabling */
230 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
231 (void)tmpreg;
232 }
233
234 /**
235 * @brief Check if AHB1 peripheral clock is enabled or not
236 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
238 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
239 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
240 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
241 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
242 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
243 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
244 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
245 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
246 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
247 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
248 * @param Periphs This parameter can be a combination of the following values:
249 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
250 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
251 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
252 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
253 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
254 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
255 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
256 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
257 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
258 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
259 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
260 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
261 *
262 * (*) value not defined in all devices.
263 * @retval State of Periphs (1 or 0).
264 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)265 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
266 {
267 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
268 }
269
270 /**
271 * @brief Disable AHB1 peripherals clock.
272 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
273 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
274 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
275 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
276 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
277 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
278 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
279 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
280 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
281 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
282 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
283 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock
284 * @param Periphs This parameter can be a combination of the following values:
285 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
286 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
287 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
288 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
289 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
290 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
291 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
292 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
293 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
294 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
295 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
296 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
297 *
298 * (*) value not defined in all devices.
299 * @retval None
300 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)301 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
302 {
303 CLEAR_BIT(RCC->AHBENR, Periphs);
304 }
305
306 /**
307 * @brief Force AHB1 peripherals reset.
308 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
309 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
310 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
311 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
312 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
313 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
314 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
315 * @param Periphs This parameter can be a combination of the following values:
316 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
317 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
318 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
319 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
320 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
321 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
322 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
323 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
324 *
325 * (*) value not defined in all devices.
326 * @retval None
327 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)328 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
329 {
330 SET_BIT(RCC->AHBRSTR, Periphs);
331 }
332
333 /**
334 * @brief Release AHB1 peripherals reset.
335 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
336 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
337 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
338 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
339 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
340 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
341 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
342 * @param Periphs This parameter can be a combination of the following values:
343 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
347 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
349 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
350 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
351 *
352 * (*) value not defined in all devices.
353 * @retval None
354 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)355 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
356 {
357 CLEAR_BIT(RCC->AHBRSTR, Periphs);
358 }
359
360 /**
361 * @}
362 */
363
364 /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
365 * @{
366 */
367
368 /**
369 * @brief Enable APB1 peripherals clock (available in register 1).
370 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
371 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
372 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
373 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
374 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
375 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
376 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
377 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
378 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
379 * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
380 * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
381 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
382 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
383 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
384 * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
385 * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
386 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
387 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
388 * APB1ENR CECEN LL_APB1_GRP1_EnableClock
389 * @param Periphs This parameter can be a combination of the following values:
390 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
391 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
392 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
393 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
394 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
395 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
396 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
397 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
398 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
399 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
400 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
401 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
402 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
403 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
404 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
405 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
406 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
407 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
408 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
409 *
410 * (*) value not defined in all devices.
411 * @retval None
412 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)413 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
414 {
415 __IO uint32_t tmpreg;
416 SET_BIT(RCC->APB1ENR, Periphs);
417 /* Delay after an RCC peripheral clock enabling */
418 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
419 (void)tmpreg;
420 }
421
422 /**
423 * @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
424 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
425 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
426 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
427 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
428 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
429 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
430 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
431 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
432 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
433 * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
434 * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
435 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
436 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
437 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
438 * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
439 * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
440 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
441 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
442 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
443 * @param Periphs This parameter can be a combination of the following values:
444 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
445 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
446 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
447 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
448 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
449 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
450 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
451 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
452 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
453 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
454 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
455 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
456 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
457 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
458 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
459 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
460 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
461 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
462 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
463 *
464 * (*) value not defined in all devices.
465 * @retval State of Periphs (1 or 0).
466 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)467 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
468 {
469 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
470 }
471
472 /**
473 * @brief Disable APB1 peripherals clock (available in register 1).
474 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
475 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
476 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
477 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
478 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
479 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
480 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
481 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
482 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
483 * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
484 * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
485 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
486 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
487 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
488 * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
489 * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
490 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
491 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
492 * APB1ENR CECEN LL_APB1_GRP1_DisableClock
493 * @param Periphs This parameter can be a combination of the following values:
494 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
495 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
499 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
500 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
501 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
502 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
503 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
504 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
505 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
506 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
507 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
508 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
509 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
510 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
511 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
512 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
513 *
514 * (*) value not defined in all devices.
515 * @retval None
516 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)517 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
518 {
519 CLEAR_BIT(RCC->APB1ENR, Periphs);
520 }
521
522 /**
523 * @brief Force APB1 peripherals reset (available in register 1).
524 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
525 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
526 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
527 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
528 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
529 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
530 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
531 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
532 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
533 * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
534 * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
535 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
536 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
537 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
538 * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
539 * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
540 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
541 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
542 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset
543 * @param Periphs This parameter can be a combination of the following values:
544 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
545 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
546 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
547 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
548 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
549 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
550 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
551 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
552 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
553 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
554 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
555 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
556 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
557 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
558 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
559 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
560 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
561 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
562 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
563 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
564 *
565 * (*) value not defined in all devices.
566 * @retval None
567 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)568 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
569 {
570 SET_BIT(RCC->APB1RSTR, Periphs);
571 }
572
573 /**
574 * @brief Release APB1 peripherals reset (available in register 1).
575 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
576 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
577 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
578 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
579 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
580 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
581 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
582 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
583 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
584 * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
585 * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
586 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
587 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
588 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
589 * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
590 * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
591 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
592 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
593 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
594 * @param Periphs This parameter can be a combination of the following values:
595 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
596 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
597 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
598 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
599 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
600 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
601 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
602 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
603 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
604 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
605 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
606 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
607 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
608 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
609 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
610 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
611 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
612 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
613 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
614 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
615 *
616 * (*) value not defined in all devices.
617 * @retval None
618 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)619 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
620 {
621 CLEAR_BIT(RCC->APB1RSTR, Periphs);
622 }
623
624 /**
625 * @}
626 */
627
628 /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
629 * @{
630 */
631
632 /**
633 * @brief Enable APB1 peripherals clock (available in register 2).
634 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
635 * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
636 * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
637 * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
638 * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
639 * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
640 * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
641 * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
642 * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
643 * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
644 * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
645 * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
646 * @param Periphs This parameter can be a combination of the following values:
647 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
648 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
649 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
650 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
651 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
652 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
653 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
654 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
655 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
656 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
657 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
658 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
659 *
660 * (*) value not defined in all devices.
661 * @retval None
662 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)663 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
664 {
665 __IO uint32_t tmpreg;
666 SET_BIT(RCC->APB2ENR, Periphs);
667 /* Delay after an RCC peripheral clock enabling */
668 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
669 (void)tmpreg;
670 }
671
672 /**
673 * @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
674 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
675 * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
676 * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
677 * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
678 * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
679 * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
680 * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
681 * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
682 * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
683 * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
684 * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
685 * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
686 * @param Periphs This parameter can be a combination of the following values:
687 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
688 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
689 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
690 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
691 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
692 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
693 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
694 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
695 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
696 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
697 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
698 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
699 *
700 * (*) value not defined in all devices.
701 * @retval State of Periphs (1 or 0).
702 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)703 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
704 {
705 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
706 }
707
708 /**
709 * @brief Disable APB1 peripherals clock (available in register 2).
710 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
711 * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
712 * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
713 * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
714 * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
715 * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
716 * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
717 * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
718 * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
719 * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
720 * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
721 * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
722 * @param Periphs This parameter can be a combination of the following values:
723 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
724 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
725 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
726 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
727 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
728 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
729 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
730 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
731 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
732 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
733 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
734 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
735 *
736 * (*) value not defined in all devices.
737 * @retval None
738 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)739 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
740 {
741 CLEAR_BIT(RCC->APB2ENR, Periphs);
742 }
743
744 /**
745 * @brief Force APB1 peripherals reset (available in register 2).
746 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
747 * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
748 * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
749 * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
750 * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
751 * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
752 * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
753 * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
754 * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
755 * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
756 * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
757 * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
758 * @param Periphs This parameter can be a combination of the following values:
759 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
760 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
761 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
762 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
763 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
764 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
765 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
766 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
767 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
768 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
769 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
770 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
771 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
772 *
773 * (*) value not defined in all devices.
774 * @retval None
775 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)776 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
777 {
778 SET_BIT(RCC->APB2RSTR, Periphs);
779 }
780
781 /**
782 * @brief Release APB1 peripherals reset (available in register 2).
783 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
784 * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
785 * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
786 * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
787 * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
788 * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
789 * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
790 * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
791 * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
792 * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
793 * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
794 * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
795 * @param Periphs This parameter can be a combination of the following values:
796 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
797 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
798 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
799 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
800 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
801 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
802 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
803 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
804 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
805 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
806 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
807 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
808 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
809 *
810 * (*) value not defined in all devices.
811 * @retval None
812 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)813 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
814 {
815 CLEAR_BIT(RCC->APB2RSTR, Periphs);
816 }
817
818 /**
819 * @}
820 */
821
822
823 /**
824 * @}
825 */
826
827 /**
828 * @}
829 */
830
831 #endif /* defined(RCC) */
832
833 /**
834 * @}
835 */
836
837 #ifdef __cplusplus
838 }
839 #endif
840
841 #endif /* __STM32F0xx_LL_BUS_H */
842
843
