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Searched refs:OPAMP_CSR_VPSEL_Pos (Results 1 – 25 of 99) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_opamp.h183 …0_SEC (LL_OPAMP_INPUT_NONINVERT_IO0 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
184 …1_SEC (LL_OPAMP_INPUT_NONINVERT_IO1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
185 …2_SEC (LL_OPAMP_INPUT_NONINVERT_IO2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
186 …3_SEC (LL_OPAMP_INPUT_NONINVERT_IO3 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
187 …CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
188 …CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAM…
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h2259 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2260 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2262 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2263 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f318xx.h2260 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2261 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2263 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2264 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f302x8.h2368 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2369 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2371 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2372 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f328xx.h2312 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2313 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2315 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2316 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f302xc.h2563 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2564 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2566 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2567 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f303x8.h2313 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2314 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2316 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2317 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f358xx.h2973 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2974 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2976 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2977 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f303xc.h3015 #define OPAMP_CSR_VPSEL_Pos (2U) macro
3016 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
3018 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
3019 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f302xe.h2586 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2587 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2589 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2590 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f303xe.h3013 #define OPAMP_CSR_VPSEL_Pos (2U) macro
3014 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
3016 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
3017 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f398xx.h2969 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2970 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2972 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2973 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32f334x8.h2498 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2499 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
2501 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
2502 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h6204 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6205 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6207 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6208 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g411xc.h6369 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6370 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6372 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6373 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g441xx.h6552 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6553 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6555 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6556 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32gbk1cb.h6317 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6318 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6320 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6321 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g431xx.h6331 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6332 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6334 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6335 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g4a1xx.h6716 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6717 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6719 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6720 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g491xx.h6495 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6496 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6498 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6499 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g473xx.h7080 #define OPAMP_CSR_VPSEL_Pos (2U) macro
7081 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
7083 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
7084 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g471xx.h6566 #define OPAMP_CSR_VPSEL_Pos (2U) macro
6567 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
6569 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
6570 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g483xx.h7301 #define OPAMP_CSR_VPSEL_Pos (2U) macro
7302 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
7304 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
7305 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
Dstm32g474xx.h10650 #define OPAMP_CSR_VPSEL_Pos (2U) macro
10651 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
10653 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
10654 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h2774 #define OPAMP_CSR_VPSEL_Pos (2U) macro
2775 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C …
2777 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 …
2778 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 …

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