1 /**
2   ******************************************************************************
3   * @file    stm32g471xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32G471xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32g471xx
30   * @{
31   */
32 
33 #ifndef __STM32G471xx_H
34 #define __STM32G471xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32G4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
77 /******  STM32 specific Interrupt Numbers ***************************************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
80   RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                                    */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
97   USB_HP_IRQn                 = 19,     /*!< USB HP Interrupt                                                                   */
98   USB_LP_IRQn                 = 20,     /*!< USB LP  Interrupt                                                                  */
99   FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
100   FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
102   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
103   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
104   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                                            */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
120   USBWakeUp_IRQn              = 42,     /*!< USB Wakeup through EXTI line Interrupt                                             */
121   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
122   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
123   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
125   ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                                             */
126   LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
127   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                                              */
128   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
129   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                                             */
130   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
131   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupts                                                             */
132   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
133   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
134   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
135   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
136   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
137   UCPD1_IRQn                  = 63,     /*!< UCPD global Interrupt                                                              */
138   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
139   COMP4_IRQn                  = 65,     /*!< COMP4                                                                              */
140   CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
141   SAI1_IRQn                   = 76,     /*!< Serial Audio Interface global interrupt                                            */
142   TIM20_BRK_IRQn              = 77,     /*!< TIM20 Break, Transition error and Index error Interrupt                            */
143   TIM20_UP_IRQn               = 78,     /*!< TIM20 Update interrupt                                                             */
144   TIM20_TRG_COM_IRQn          = 79,     /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt                   */
145   TIM20_CC_IRQn               = 80,     /*!< TIM20 Capture Compare interrupt                                                    */
146   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
147   I2C4_EV_IRQn                = 82,     /*!< I2C4 Event interrupt                                                               */
148   I2C4_ER_IRQn                = 83,     /*!< I2C4 Error interrupt                                                               */
149   SPI4_IRQn                   = 84,     /*!< SPI4 Event interrupt                                                               */
150   FDCAN2_IT0_IRQn             = 86,     /*!< FDCAN2 interrupt line 0 interrupt                                                  */
151   FDCAN2_IT1_IRQn             = 87,     /*!< FDCAN2 interrupt line 1 interrupt                                                  */
152   RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
153   LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
154   I2C3_EV_IRQn                = 92,     /*!< I2C3 Event Interrupt                                                               */
155   I2C3_ER_IRQn                = 93,     /*!< I2C3 Error interrupt                                                               */
156   DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
157   QUADSPI_IRQn                = 95,     /*!< QUADSPI interrupt                                                                  */
158   DMA1_Channel8_IRQn          = 96,     /*!< DMA1 Channel 8 interrupt                                                           */
159   DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
160   DMA2_Channel7_IRQn          = 98,     /*!< DMA2 Channel 7 interrupt                                                           */
161   DMA2_Channel8_IRQn          = 99,     /*!< DMA2 Channel 8 interrupt                                                           */
162   CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
163   FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
164 } IRQn_Type;
165 
166 /**
167   * @}
168   */
169 
170 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
171 #include "system_stm32g4xx.h"
172 #include <stdint.h>
173 
174 /** @addtogroup Peripheral_registers_structures
175   * @{
176   */
177 
178 /**
179   * @brief Analog to Digital Converter
180   */
181 
182 typedef struct
183 {
184   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
185   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
186   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
187   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
188   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
189   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
190   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
191        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
192   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
193   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
194   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
195        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
196   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
197   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
198   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
199   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
200   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
201        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
202        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
203   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
204        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
205   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
206   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
207   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
208   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
209        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
210   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
211   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
212   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
213   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
214        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
215   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
216   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
217        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
218        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
219   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
220   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
221        uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
222   __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
223 } ADC_TypeDef;
224 
225 typedef struct
226 {
227   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
228   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
229   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
230   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
231 } ADC_Common_TypeDef;
232 
233 /**
234   * @brief FD Controller Area Network
235   */
236 
237 typedef struct
238 {
239   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
240   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
241        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
242   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
243   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
244   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
245   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
246   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
247   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
248   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
249   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
250   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
251        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
252   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
253   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
254   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
255        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
256   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
257   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
258   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
259   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
260        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
261   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
262   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
263   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
264        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
265   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
266   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
267   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
268   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
269        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
270   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
271   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
272   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
273   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
274   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
275   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
276   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
277   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
278   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
279   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
280   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
281 } FDCAN_GlobalTypeDef;
282 
283 /**
284   * @brief FD Controller Area Network Configuration
285   */
286 
287 typedef struct
288 {
289   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
290 } FDCAN_Config_TypeDef;
291 
292 /**
293   * @brief Comparator
294   */
295 
296 typedef struct
297 {
298   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
299 } COMP_TypeDef;
300 
301 /**
302   * @brief CRC calculation unit
303   */
304 
305 typedef struct
306 {
307   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
308   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
309   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
310   uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
311   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
312   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
313 } CRC_TypeDef;
314 
315 /**
316   * @brief Clock Recovery System
317   */
318 typedef struct
319 {
320   __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
321   __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
322   __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
323   __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
324 } CRS_TypeDef;
325 
326 /**
327   * @brief Digital to Analog Converter
328   */
329 
330 typedef struct
331 {
332   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
333   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
334   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
335   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
336   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
337   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
338   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
339   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
340   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
341   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
342   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
343   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
344   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
345   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
346   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
347   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
348   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
349   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
350   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
351   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
352   __IO uint32_t RESERVED[2];
353   __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
354   __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
355   __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
356 } DAC_TypeDef;
357 
358 /**
359   * @brief Debug MCU
360   */
361 
362 typedef struct
363 {
364   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
365   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
366   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
367   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
368   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
369 } DBGMCU_TypeDef;
370 
371 /**
372   * @brief DMA Controller
373   */
374 
375 typedef struct
376 {
377   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
378   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
379   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
380   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
381 } DMA_Channel_TypeDef;
382 
383 typedef struct
384 {
385   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
386   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
387 } DMA_TypeDef;
388 
389 /**
390   * @brief DMA Multiplexer
391   */
392 
393 typedef struct
394 {
395   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
396 }DMAMUX_Channel_TypeDef;
397 
398 typedef struct
399 {
400   __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
401   __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
402 }DMAMUX_ChannelStatus_TypeDef;
403 
404 typedef struct
405 {
406   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
407 }DMAMUX_RequestGen_TypeDef;
408 
409 typedef struct
410 {
411   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
412   __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
413 }DMAMUX_RequestGenStatus_TypeDef;
414 
415 /**
416   * @brief External Interrupt/Event Controller
417   */
418 
419 typedef struct
420 {
421   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
422   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
423   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
424   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
425   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
426   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
427   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
428   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
429   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
430   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
431   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
432   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
433   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
434   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
435 } EXTI_TypeDef;
436 
437 /**
438   * @brief FLASH Registers
439   */
440 
441 typedef struct
442 {
443   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
444   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
445   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
446   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
447   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
448   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
449   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
450        uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
451   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
452   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
453   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
454   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
455   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
456        uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
457   __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
458   __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
459   __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
460   __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
461        uint32_t RESERVED3[7];     /*!< Reserved3,                                Address offset: 0x54 */
462   __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
463   __IO uint32_t SEC2R;            /*!< FLASH Securable memory register bank2,    Address offset: 0x74 */
464 } FLASH_TypeDef;
465 
466 /**
467   * @brief FMAC
468   */
469 typedef struct
470 {
471   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
472   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
473   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
474   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
475   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
476   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
477   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
478   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
479 } FMAC_TypeDef;
480 
481 
482 /**
483   * @brief General Purpose I/O
484   */
485 
486 typedef struct
487 {
488   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
489   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
490   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
491   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
492   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
493   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
494   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
495   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
496   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
497   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
498 } GPIO_TypeDef;
499 
500 /**
501   * @brief Inter-integrated Circuit Interface
502   */
503 
504 typedef struct
505 {
506   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
507   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
508   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
509   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
510   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
511   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
512   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
513   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
514   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
515   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
516   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
517 } I2C_TypeDef;
518 
519 /**
520   * @brief Independent WATCHDOG
521   */
522 
523 typedef struct
524 {
525   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
526   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
527   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
528   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
529   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
530 } IWDG_TypeDef;
531 
532 /**
533   * @brief LPTIMER
534   */
535 
536 typedef struct
537 {
538   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
539   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
540   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
541   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
542   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
543   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
544   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
545   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
546   __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
547 } LPTIM_TypeDef;
548 
549 /**
550   * @brief Operational Amplifier (OPAMP)
551   */
552 
553 typedef struct
554 {
555   __IO uint32_t CSR;           /*!< OPAMP control/status register,                     Address offset: 0x00 */
556   __IO uint32_t RESERVED[5];   /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
557   __IO uint32_t TCMR;          /*!< OPAMP timer controlled mux mode register,          Address offset: 0x18 */
558 } OPAMP_TypeDef;
559 
560 /**
561   * @brief Power Control
562   */
563 
564 typedef struct
565 {
566   __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
567   __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
568   __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
569   __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
570   __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
571   __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
572   __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
573   uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
574   __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
575   __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
576   __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
577   __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
578   __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
579   __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
580   __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
581   __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
582   __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
583   __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
584   __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
585   __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
586   __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
587   __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
588   uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
589   __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
590 } PWR_TypeDef;
591 
592 /**
593   * @brief QUAD Serial Peripheral Interface
594   */
595 
596 typedef struct
597 {
598   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
599   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
600   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
601   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
602   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
603   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
604   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
605   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
606   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
607   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
608   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
609   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
610   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
611 } QUADSPI_TypeDef;
612 
613 /**
614   * @brief Reset and Clock Control
615   */
616 
617 typedef struct
618 {
619   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
620   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
621   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
622   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
623   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
624   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
625   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
626   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
627   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
628   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
629   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
630   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
631   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
632   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
633   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
634   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
635   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
636   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
637   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
638   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
639   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
640   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
641   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
642   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
643   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
644   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
645   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
646   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
647   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
648   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
649   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
650   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
651   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
652   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
653   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
654   uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
655   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
656   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
657   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
658   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
659 } RCC_TypeDef;
660 
661 /**
662   * @brief Real-Time Clock
663   */
664 /*
665 * @brief Specific device feature definitions
666 */
667 #define RTC_TAMP_INT_6_SUPPORT
668 #define RTC_TAMP_INT_NB        4u
669 
670 #define RTC_TAMP_NB            3u
671 #define RTC_BACKUP_NB          32u
672 
673 
674 typedef struct
675 {
676   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
677   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
678   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
679   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
680   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
681   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
682   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
683        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
684        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
685   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
686   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
687   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
688   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
689   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
690   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
691        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
692   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
693   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
694   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
695   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
696   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
697   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
698        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
699   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
700 } RTC_TypeDef;
701 
702 /**
703   * @brief Tamper and backup registers
704   */
705 
706 typedef struct
707 {
708   __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
709   __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
710        uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
711   __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
712        uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
713        uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
714   __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
715   __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
716   __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
717        uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
718   __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
719        uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
720   __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
721   __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
722   __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
723   __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
724   __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
725   __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
726   __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
727   __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
728   __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
729   __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
730   __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
731   __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
732   __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
733   __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
734   __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
735   __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
736   __IO uint32_t BKP16R;                  /*!< TAMP backup register 16,                Address offset: 0x140 */
737   __IO uint32_t BKP17R;                  /*!< TAMP backup register 17,                Address offset: 0x144 */
738   __IO uint32_t BKP18R;                  /*!< TAMP backup register 18,                Address offset: 0x148 */
739   __IO uint32_t BKP19R;                  /*!< TAMP backup register 19,                Address offset: 0x14C */
740   __IO uint32_t BKP20R;                  /*!< TAMP backup register 20,                Address offset: 0x150 */
741   __IO uint32_t BKP21R;                  /*!< TAMP backup register 21,                Address offset: 0x154 */
742   __IO uint32_t BKP22R;                  /*!< TAMP backup register 22,                Address offset: 0x158 */
743   __IO uint32_t BKP23R;                  /*!< TAMP backup register 23,                Address offset: 0x15C */
744   __IO uint32_t BKP24R;                  /*!< TAMP backup register 24,                Address offset: 0x160 */
745   __IO uint32_t BKP25R;                  /*!< TAMP backup register 25,                Address offset: 0x164 */
746   __IO uint32_t BKP26R;                  /*!< TAMP backup register 26,                Address offset: 0x168 */
747   __IO uint32_t BKP27R;                  /*!< TAMP backup register 27,                Address offset: 0x16C */
748   __IO uint32_t BKP28R;                  /*!< TAMP backup register 28,                Address offset: 0x170 */
749   __IO uint32_t BKP29R;                  /*!< TAMP backup register 29,                Address offset: 0x174 */
750   __IO uint32_t BKP30R;                  /*!< TAMP backup register 30,                Address offset: 0x178 */
751   __IO uint32_t BKP31R;                  /*!< TAMP backup register 31,                Address offset: 0x17C */
752 } TAMP_TypeDef;
753 
754 /**
755   * @brief Serial Audio Interface
756   */
757 
758 typedef struct
759 {
760   uint32_t      RESERVED[17]; /*!< Reserved,                                 Address offset: 0x00 to 0x40 */
761   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
762   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
763 } SAI_TypeDef;
764 
765 typedef struct
766 {
767   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
768   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
769   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
770   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
771   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
772   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
773   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
774   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
775 } SAI_Block_TypeDef;
776 
777 /**
778   * @brief Serial Peripheral Interface
779   */
780 
781 typedef struct
782 {
783   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
784   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
785   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
786   __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
787   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
788   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
789   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
790   __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
791   __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
792 } SPI_TypeDef;
793 
794 /**
795   * @brief System configuration controller
796   */
797 
798 typedef struct
799 {
800   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
801   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
802   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
803   __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
804   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
805   __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
806   __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
807 } SYSCFG_TypeDef;
808 
809 /**
810   * @brief TIM
811   */
812 
813 typedef struct
814 {
815   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
816   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
817   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
818   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
819   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
820   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
821   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
822   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
823   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
824   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
825   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
826   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
827   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
828   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
829   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
830   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
831   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
832   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
833   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
834   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
835   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
836   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
837   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
838   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
839   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
840   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
841   __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
842        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
843   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
844   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
845 } TIM_TypeDef;
846 
847 /**
848   * @brief Universal Synchronous Asynchronous Receiver Transmitter
849   */
850 typedef struct
851 {
852   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
853   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
854   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
855   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
856   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
857   __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
858   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
859   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
860   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
861   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
862   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
863   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
864 } USART_TypeDef;
865 
866 /**
867   * @brief Universal Serial Bus Full Speed Device
868   */
869 
870 typedef struct
871 {
872   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
873   __IO uint16_t RESERVED0;       /*!< Reserved */
874   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
875   __IO uint16_t RESERVED1;       /*!< Reserved */
876   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
877   __IO uint16_t RESERVED2;       /*!< Reserved */
878   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
879   __IO uint16_t RESERVED3;       /*!< Reserved */
880   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
881   __IO uint16_t RESERVED4;       /*!< Reserved */
882   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
883   __IO uint16_t RESERVED5;       /*!< Reserved */
884   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
885   __IO uint16_t RESERVED6;       /*!< Reserved */
886   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
887   __IO uint16_t RESERVED7[17];   /*!< Reserved */
888   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
889   __IO uint16_t RESERVED8;       /*!< Reserved */
890   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
891   __IO uint16_t RESERVED9;       /*!< Reserved */
892   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
893   __IO uint16_t RESERVEDA;       /*!< Reserved */
894   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
895   __IO uint16_t RESERVEDB;       /*!< Reserved */
896   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
897   __IO uint16_t RESERVEDC;       /*!< Reserved */
898   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
899   __IO uint16_t RESERVEDD;       /*!< Reserved */
900   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
901   __IO uint16_t RESERVEDE;       /*!< Reserved */
902 } USB_TypeDef;
903 
904 /**
905   * @brief VREFBUF
906   */
907 
908 typedef struct
909 {
910   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
911   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
912 } VREFBUF_TypeDef;
913 
914 /**
915   * @brief Window WATCHDOG
916   */
917 
918 typedef struct
919 {
920   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
921   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
922   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
923 } WWDG_TypeDef;
924 
925 
926 /**
927   * @brief RNG
928   */
929 typedef struct
930 {
931   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
932   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
933   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
934 } RNG_TypeDef;
935 
936 /**
937   * @brief CORDIC
938   */
939 
940 typedef struct
941 {
942   __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
943   __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
944   __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
945 } CORDIC_TypeDef;
946 
947 /**
948   * @brief UCPD
949   */
950 
951 typedef struct
952 {
953   __IO uint32_t CFG1;          /*!< UCPD configuration register 1,             Address offset: 0x00 */
954   __IO uint32_t CFG2;          /*!< UCPD configuration register 2,             Address offset: 0x04 */
955   __IO uint32_t RESERVED0;     /*!< UCPD reserved register,                    Address offset: 0x08 */
956   __IO uint32_t CR;            /*!< UCPD control register,                     Address offset: 0x0C */
957   __IO uint32_t IMR;           /*!< UCPD interrupt mask register,              Address offset: 0x10 */
958   __IO uint32_t SR;            /*!< UCPD status register,                      Address offset: 0x14 */
959   __IO uint32_t ICR;           /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
960   __IO uint32_t TX_ORDSET;     /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
961   __IO uint32_t TX_PAYSZ;      /*!< UCPD Tx payload size register,             Address offset: 0x20 */
962   __IO uint32_t TXDR;          /*!< UCPD Tx data register,                     Address offset: 0x24 */
963   __IO uint32_t RX_ORDSET;     /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
964   __IO uint32_t RX_PAYSZ;      /*!< UCPD Rx payload size register,             Address offset: 0x2C */
965   __IO uint32_t RXDR;          /*!< UCPD Rx data register,                     Address offset: 0x30 */
966   __IO uint32_t RX_ORDEXT1;    /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
967   __IO uint32_t RX_ORDEXT2;    /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
968 } UCPD_TypeDef;
969 
970 
971 /**
972   * @}
973   */
974 
975 /** @addtogroup Peripheral_memory_map
976   * @{
977   */
978 
979 #define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
980 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
981 #define SRAM2_BASE            (0x20014000UL) /*!< SRAM2(16 KB) base address */
982 #define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
983 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
984 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
985 
986 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
987 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
988 #define SRAM2_BB_BASE         (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
989 #define CCMSRAM_BB_BASE       (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
990 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
991 /* Legacy defines */
992 #define SRAM_BASE             SRAM1_BASE
993 #define SRAM_BB_BASE          SRAM1_BB_BASE
994 
995 #define SRAM1_SIZE_MAX        (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
996 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
997 #define CCMSRAM_SIZE          (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
998 
999 /*!< Peripheral memory map */
1000 #define APB1PERIPH_BASE        PERIPH_BASE
1001 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1002 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1003 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
1004 
1005 
1006 /*!< APB1 peripherals */
1007 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1008 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1009 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1010 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1011 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1012 #define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
1013 #define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
1014 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1015 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1016 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1017 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1018 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1019 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1020 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1021 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1022 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1023 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1024 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1025 #define USB_BASE              (APB1PERIPH_BASE + 0x5C00UL)  /*!< USB_IP Peripheral Registers base address */
1026 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x6000UL)  /*!< USB_IP Packet Memory Area base address */
1027 #define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
1028 #define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
1029 #define FDCAN2_BASE           (APB1PERIPH_BASE + 0x6800UL)
1030 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1031 #define I2C3_BASE             (APB1PERIPH_BASE + 0x7800UL)
1032 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
1033 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
1034 #define I2C4_BASE             (APB1PERIPH_BASE + 0x8400UL)
1035 #define UCPD1_BASE            (APB1PERIPH_BASE + 0xA000UL)
1036 #define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
1037 
1038 /*!< APB2 peripherals */
1039 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
1040 #define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
1041 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
1042 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
1043 #define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
1044 #define COMP4_BASE            (APB2PERIPH_BASE + 0x020CUL)
1045 #define OPAMP_BASE            (APB2PERIPH_BASE + 0x0300UL)
1046 #define OPAMP1_BASE           (APB2PERIPH_BASE + 0x0300UL)
1047 #define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0304UL)
1048 #define OPAMP3_BASE           (APB2PERIPH_BASE + 0x0308UL)
1049 
1050 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
1051 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1052 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1053 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
1054 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
1055 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1056 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
1057 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
1058 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
1059 #define TIM20_BASE            (APB2PERIPH_BASE + 0x5000UL)
1060 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
1061 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
1062 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
1063 
1064 /*!< AHB1 peripherals */
1065 #define DMA1_BASE             (AHB1PERIPH_BASE)
1066 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
1067 #define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
1068 #define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
1069 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
1070 #define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
1071 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
1072 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1073 
1074 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
1075 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
1076 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
1077 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
1078 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
1079 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
1080 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
1081 #define DMA1_Channel8_BASE    (DMA1_BASE + 0x0094UL)
1082 
1083 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
1084 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
1085 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
1086 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
1087 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
1088 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
1089 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
1090 #define DMA2_Channel8_BASE    (DMA2_BASE + 0x0094UL)
1091 
1092 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
1093 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
1094 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
1095 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
1096 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
1097 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
1098 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
1099 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
1100 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
1101 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
1102 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
1103 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
1104 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
1105 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
1106 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
1107 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
1108 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
1109 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
1110 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
1111 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
1112 
1113 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
1114 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
1115 
1116 /*!< AHB2 peripherals */
1117 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
1118 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
1119 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
1120 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
1121 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
1122 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
1123 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
1124 
1125 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
1126 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
1127 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
1128 #define ADC3_BASE             (AHB2PERIPH_BASE + 0x08000400UL)
1129 #define ADC345_COMMON_BASE    (AHB2PERIPH_BASE + 0x08000700UL)
1130 
1131 #define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
1132 #define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
1133 #define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
1134 
1135 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
1136 /* Debug MCU registers base address */
1137 #define DBGMCU_BASE           (0xE0042000UL)
1138 
1139 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
1140 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
1141 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
1142 /**
1143   * @}
1144   */
1145 
1146 /** @addtogroup Peripheral_declaration
1147   * @{
1148   */
1149 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1150 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1151 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1152 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1153 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1154 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1155 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
1156 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1157 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1158 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1159 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1160 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1161 #define USART2              ((USART_TypeDef *) USART2_BASE)
1162 #define USART3              ((USART_TypeDef *) USART3_BASE)
1163 #define UART4               ((USART_TypeDef *) UART4_BASE)
1164 #define UART5               ((USART_TypeDef *) UART5_BASE)
1165 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1166 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1167 #define USB                 ((USB_TypeDef *) USB_BASE)
1168 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1169 #define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1170 #define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1171 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1172 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1173 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1174 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1175 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1176 #define UCPD1              ((UCPD_TypeDef *) UCPD1_BASE)
1177 
1178 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1179 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1180 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1181 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1182 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
1183 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
1184 
1185 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
1186 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1187 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
1188 #define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
1189 
1190 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1191 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1192 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1193 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1194 #define USART1              ((USART_TypeDef *) USART1_BASE)
1195 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1196 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1197 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1198 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
1199 #define TIM20               ((TIM_TypeDef *) TIM20_BASE)
1200 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1201 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1202 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1203 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1204 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1205 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1206 #define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
1207 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1208 #define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
1209 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1210 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1211 
1212 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1213 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1214 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1215 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1216 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1217 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1218 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1219 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1220 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1221 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1222 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1223 #define ADC345_COMMON       ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1224 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1225 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1226 #define DAC3                ((DAC_TypeDef *) DAC3_BASE)
1227 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1228 
1229 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1230 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1231 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1232 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1233 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1234 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1235 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1236 #define DMA1_Channel8       ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1237 
1238 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1239 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1240 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1241 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1242 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1243 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1244 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1245 #define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1246 
1247 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1248 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1249 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1250 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1251 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1252 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1253 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1254 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1255 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1256 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1257 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1258 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1259 #define DMAMUX1_Channel12   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1260 #define DMAMUX1_Channel13   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1261 #define DMAMUX1_Channel14   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1262 #define DMAMUX1_Channel15   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1263 
1264 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1265 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1266 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1267 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1268 
1269 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1270 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1271 
1272 
1273 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1274 
1275 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1276 
1277 /**
1278   * @}
1279   */
1280 
1281 /** @addtogroup Exported_constants
1282   * @{
1283   */
1284 
1285   /** @addtogroup Hardware_Constant_Definition
1286     * @{
1287     */
1288 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1289 
1290   /**
1291     * @}
1292     */
1293 
1294 /** @addtogroup Peripheral_Registers_Bits_Definition
1295   * @{
1296   */
1297 
1298 /******************************************************************************/
1299 /*                         Peripheral Registers_Bits_Definition               */
1300 /******************************************************************************/
1301 
1302 /******************************************************************************/
1303 /*                                                                            */
1304 /*                        Analog to Digital Converter                         */
1305 /*                                                                            */
1306 /******************************************************************************/
1307 
1308 /*
1309  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
1310  */
1311 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1312 
1313 /********************  Bit definition for ADC_ISR register  *******************/
1314 #define ADC_ISR_ADRDY_Pos              (0U)
1315 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1316 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1317 #define ADC_ISR_EOSMP_Pos              (1U)
1318 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1319 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1320 #define ADC_ISR_EOC_Pos                (2U)
1321 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1322 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1323 #define ADC_ISR_EOS_Pos                (3U)
1324 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1325 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1326 #define ADC_ISR_OVR_Pos                (4U)
1327 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1328 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1329 #define ADC_ISR_JEOC_Pos               (5U)
1330 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1331 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1332 #define ADC_ISR_JEOS_Pos               (6U)
1333 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1334 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1335 #define ADC_ISR_AWD1_Pos               (7U)
1336 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1337 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1338 #define ADC_ISR_AWD2_Pos               (8U)
1339 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1340 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1341 #define ADC_ISR_AWD3_Pos               (9U)
1342 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1343 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1344 #define ADC_ISR_JQOVF_Pos              (10U)
1345 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1346 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1347 
1348 /********************  Bit definition for ADC_IER register  *******************/
1349 #define ADC_IER_ADRDYIE_Pos            (0U)
1350 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1351 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1352 #define ADC_IER_EOSMPIE_Pos            (1U)
1353 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1354 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1355 #define ADC_IER_EOCIE_Pos              (2U)
1356 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1357 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1358 #define ADC_IER_EOSIE_Pos              (3U)
1359 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1360 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1361 #define ADC_IER_OVRIE_Pos              (4U)
1362 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1363 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1364 #define ADC_IER_JEOCIE_Pos             (5U)
1365 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1366 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1367 #define ADC_IER_JEOSIE_Pos             (6U)
1368 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1369 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1370 #define ADC_IER_AWD1IE_Pos             (7U)
1371 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1372 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1373 #define ADC_IER_AWD2IE_Pos             (8U)
1374 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1375 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1376 #define ADC_IER_AWD3IE_Pos             (9U)
1377 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1378 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1379 #define ADC_IER_JQOVFIE_Pos            (10U)
1380 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1381 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1382 
1383 /********************  Bit definition for ADC_CR register  ********************/
1384 #define ADC_CR_ADEN_Pos                (0U)
1385 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1386 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1387 #define ADC_CR_ADDIS_Pos               (1U)
1388 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1389 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1390 #define ADC_CR_ADSTART_Pos             (2U)
1391 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1392 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1393 #define ADC_CR_JADSTART_Pos            (3U)
1394 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1395 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1396 #define ADC_CR_ADSTP_Pos               (4U)
1397 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1398 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1399 #define ADC_CR_JADSTP_Pos              (5U)
1400 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1401 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1402 #define ADC_CR_ADVREGEN_Pos            (28U)
1403 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1404 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1405 #define ADC_CR_DEEPPWD_Pos             (29U)
1406 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1407 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1408 #define ADC_CR_ADCALDIF_Pos            (30U)
1409 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1410 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1411 #define ADC_CR_ADCAL_Pos               (31U)
1412 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1413 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1414 
1415 /********************  Bit definition for ADC_CFGR register  ******************/
1416 #define ADC_CFGR_DMAEN_Pos             (0U)
1417 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1418 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1419 #define ADC_CFGR_DMACFG_Pos            (1U)
1420 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1421 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1422 
1423 #define ADC_CFGR_RES_Pos               (3U)
1424 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1425 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1426 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1427 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1428 
1429 #define ADC_CFGR_EXTSEL_Pos            (5U)
1430 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1431 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1432 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1433 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1434 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1435 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1436 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1437 
1438 #define ADC_CFGR_EXTEN_Pos             (10U)
1439 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1440 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1441 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1442 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1443 
1444 #define ADC_CFGR_OVRMOD_Pos            (12U)
1445 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1446 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1447 #define ADC_CFGR_CONT_Pos              (13U)
1448 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1449 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1450 #define ADC_CFGR_AUTDLY_Pos            (14U)
1451 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1452 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1453 #define ADC_CFGR_ALIGN_Pos             (15U)
1454 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1455 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1456 #define ADC_CFGR_DISCEN_Pos            (16U)
1457 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1458 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1459 
1460 #define ADC_CFGR_DISCNUM_Pos           (17U)
1461 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1462 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1463 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1464 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1465 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1466 
1467 #define ADC_CFGR_JDISCEN_Pos           (20U)
1468 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1469 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1470 #define ADC_CFGR_JQM_Pos               (21U)
1471 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1472 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1473 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1474 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1475 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1476 #define ADC_CFGR_AWD1EN_Pos            (23U)
1477 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1478 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1479 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1480 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1481 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1482 #define ADC_CFGR_JAUTO_Pos             (25U)
1483 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1484 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1485 
1486 #define ADC_CFGR_AWD1CH_Pos            (26U)
1487 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1488 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1489 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1490 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1491 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1492 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1493 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1494 
1495 #define ADC_CFGR_JQDIS_Pos             (31U)
1496 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1497 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1498 
1499 /********************  Bit definition for ADC_CFGR2 register  *****************/
1500 #define ADC_CFGR2_ROVSE_Pos            (0U)
1501 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1502 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1503 #define ADC_CFGR2_JOVSE_Pos            (1U)
1504 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1505 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1506 
1507 #define ADC_CFGR2_OVSR_Pos             (2U)
1508 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1509 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1510 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1511 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1512 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1513 
1514 #define ADC_CFGR2_OVSS_Pos             (5U)
1515 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1516 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1517 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1518 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1519 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1520 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1521 
1522 #define ADC_CFGR2_TROVS_Pos            (9U)
1523 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1524 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1525 #define ADC_CFGR2_ROVSM_Pos            (10U)
1526 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1527 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1528 
1529 #define ADC_CFGR2_GCOMP_Pos            (16U)
1530 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1531 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1532 
1533 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1534 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1535 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1536 #define ADC_CFGR2_BULB_Pos             (26U)
1537 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1538 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1539 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1540 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1541 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1542 
1543 /********************  Bit definition for ADC_SMPR1 register  *****************/
1544 #define ADC_SMPR1_SMP0_Pos             (0U)
1545 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1546 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1547 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1548 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1549 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1550 
1551 #define ADC_SMPR1_SMP1_Pos             (3U)
1552 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1553 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1554 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1555 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1556 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1557 
1558 #define ADC_SMPR1_SMP2_Pos             (6U)
1559 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1560 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1561 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1562 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1563 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1564 
1565 #define ADC_SMPR1_SMP3_Pos             (9U)
1566 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1567 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1568 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1569 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1570 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1571 
1572 #define ADC_SMPR1_SMP4_Pos             (12U)
1573 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1574 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1575 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1576 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1577 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1578 
1579 #define ADC_SMPR1_SMP5_Pos             (15U)
1580 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1581 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1582 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1583 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1584 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1585 
1586 #define ADC_SMPR1_SMP6_Pos             (18U)
1587 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1588 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1589 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1590 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1591 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1592 
1593 #define ADC_SMPR1_SMP7_Pos             (21U)
1594 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1595 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1596 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1597 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1598 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1599 
1600 #define ADC_SMPR1_SMP8_Pos             (24U)
1601 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1602 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1603 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1604 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1605 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1606 
1607 #define ADC_SMPR1_SMP9_Pos             (27U)
1608 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1609 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1610 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1611 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1612 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1613 
1614 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1615 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1616 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1617 
1618 /********************  Bit definition for ADC_SMPR2 register  *****************/
1619 #define ADC_SMPR2_SMP10_Pos            (0U)
1620 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1621 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1622 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1623 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1624 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1625 
1626 #define ADC_SMPR2_SMP11_Pos            (3U)
1627 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1628 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1629 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1630 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1631 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1632 
1633 #define ADC_SMPR2_SMP12_Pos            (6U)
1634 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1635 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1636 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1637 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1638 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1639 
1640 #define ADC_SMPR2_SMP13_Pos            (9U)
1641 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1642 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1643 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1644 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1645 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1646 
1647 #define ADC_SMPR2_SMP14_Pos            (12U)
1648 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1649 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1650 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1651 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1652 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1653 
1654 #define ADC_SMPR2_SMP15_Pos            (15U)
1655 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1656 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1657 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1658 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1659 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1660 
1661 #define ADC_SMPR2_SMP16_Pos            (18U)
1662 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1663 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1664 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1665 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1666 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1667 
1668 #define ADC_SMPR2_SMP17_Pos            (21U)
1669 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1670 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1671 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1672 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1673 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1674 
1675 #define ADC_SMPR2_SMP18_Pos            (24U)
1676 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1677 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1678 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1679 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1680 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1681 
1682 /********************  Bit definition for ADC_TR1 register  *******************/
1683 #define ADC_TR1_LT1_Pos                (0U)
1684 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1685 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1686 
1687 #define ADC_TR1_AWDFILT_Pos            (12U)
1688 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
1689 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
1690 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
1691 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
1692 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
1693 
1694 #define ADC_TR1_HT1_Pos                (16U)
1695 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1696 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
1697 
1698 /********************  Bit definition for ADC_TR2 register  *******************/
1699 #define ADC_TR2_LT2_Pos                (0U)
1700 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1701 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1702 
1703 #define ADC_TR2_HT2_Pos                (16U)
1704 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1705 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1706 
1707 /********************  Bit definition for ADC_TR3 register  *******************/
1708 #define ADC_TR3_LT3_Pos                (0U)
1709 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1710 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1711 
1712 #define ADC_TR3_HT3_Pos                (16U)
1713 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1714 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1715 
1716 /********************  Bit definition for ADC_SQR1 register  ******************/
1717 #define ADC_SQR1_L_Pos                 (0U)
1718 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1719 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1720 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1721 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1722 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1723 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1724 
1725 #define ADC_SQR1_SQ1_Pos               (6U)
1726 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1727 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1728 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1729 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1730 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1731 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1732 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1733 
1734 #define ADC_SQR1_SQ2_Pos               (12U)
1735 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1736 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1737 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1738 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1739 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1740 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1741 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1742 
1743 #define ADC_SQR1_SQ3_Pos               (18U)
1744 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1745 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1746 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1747 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1748 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1749 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1750 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1751 
1752 #define ADC_SQR1_SQ4_Pos               (24U)
1753 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1754 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1755 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1756 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1757 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1758 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1759 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1760 
1761 /********************  Bit definition for ADC_SQR2 register  ******************/
1762 #define ADC_SQR2_SQ5_Pos               (0U)
1763 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1764 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1765 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1766 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1767 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1768 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1769 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1770 
1771 #define ADC_SQR2_SQ6_Pos               (6U)
1772 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1773 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1774 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1775 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1776 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1777 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1778 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1779 
1780 #define ADC_SQR2_SQ7_Pos               (12U)
1781 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1782 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1783 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1784 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1785 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1786 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1787 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1788 
1789 #define ADC_SQR2_SQ8_Pos               (18U)
1790 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1791 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1792 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1793 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1794 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1795 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1796 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1797 
1798 #define ADC_SQR2_SQ9_Pos               (24U)
1799 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1800 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1801 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1802 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1803 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1804 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1805 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1806 
1807 /********************  Bit definition for ADC_SQR3 register  ******************/
1808 #define ADC_SQR3_SQ10_Pos              (0U)
1809 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1810 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1811 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1812 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1813 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1814 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1815 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1816 
1817 #define ADC_SQR3_SQ11_Pos              (6U)
1818 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1819 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1820 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1821 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1822 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1823 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1824 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1825 
1826 #define ADC_SQR3_SQ12_Pos              (12U)
1827 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1828 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1829 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1830 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1831 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1832 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1833 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1834 
1835 #define ADC_SQR3_SQ13_Pos              (18U)
1836 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1837 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1838 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1839 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1840 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1841 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1842 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1843 
1844 #define ADC_SQR3_SQ14_Pos              (24U)
1845 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1846 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1847 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1848 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1849 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1850 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1851 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1852 
1853 /********************  Bit definition for ADC_SQR4 register  ******************/
1854 #define ADC_SQR4_SQ15_Pos              (0U)
1855 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1856 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1857 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1858 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1859 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1860 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1861 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1862 
1863 #define ADC_SQR4_SQ16_Pos              (6U)
1864 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1865 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1866 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1867 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1868 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1869 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1870 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1871 
1872 /********************  Bit definition for ADC_DR register  ********************/
1873 #define ADC_DR_RDATA_Pos               (0U)
1874 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1875 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1876 
1877 /********************  Bit definition for ADC_JSQR register  ******************/
1878 #define ADC_JSQR_JL_Pos                (0U)
1879 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1880 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1881 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1882 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1883 
1884 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1885 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
1886 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1887 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1888 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1889 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1890 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1891 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
1892 
1893 #define ADC_JSQR_JEXTEN_Pos            (7U)
1894 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
1895 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1896 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1897 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
1898 
1899 #define ADC_JSQR_JSQ1_Pos              (9U)
1900 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
1901 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1902 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1903 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1904 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1905 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1906 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
1907 
1908 #define ADC_JSQR_JSQ2_Pos              (15U)
1909 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1910 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1911 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1912 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1913 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1914 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1915 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1916 
1917 #define ADC_JSQR_JSQ3_Pos              (21U)
1918 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
1919 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1920 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1921 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1922 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1923 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1924 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
1925 
1926 #define ADC_JSQR_JSQ4_Pos              (27U)
1927 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
1928 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1929 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1930 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1931 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1932 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1933 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
1934 
1935 /********************  Bit definition for ADC_OFR1 register  ******************/
1936 #define ADC_OFR1_OFFSET1_Pos           (0U)
1937 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1938 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1939 
1940 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
1941 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
1942 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
1943 #define ADC_OFR1_SATEN_Pos             (25U)
1944 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
1945 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
1946 
1947 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1948 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1949 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1950 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1951 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1952 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1953 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1954 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1955 
1956 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1957 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1958 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1959 
1960 /********************  Bit definition for ADC_OFR2 register  ******************/
1961 #define ADC_OFR2_OFFSET2_Pos           (0U)
1962 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1963 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1964 
1965 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
1966 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
1967 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
1968 #define ADC_OFR2_SATEN_Pos             (25U)
1969 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
1970 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
1971 
1972 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1973 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1974 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1975 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1976 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1977 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1978 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1979 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1980 
1981 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1982 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1983 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1984 
1985 /********************  Bit definition for ADC_OFR3 register  ******************/
1986 #define ADC_OFR3_OFFSET3_Pos           (0U)
1987 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1988 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1989 
1990 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
1991 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
1992 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
1993 #define ADC_OFR3_SATEN_Pos             (25U)
1994 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
1995 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
1996 
1997 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1998 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1999 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2000 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
2001 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
2002 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2003 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2004 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2005 
2006 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2007 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2008 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2009 
2010 /********************  Bit definition for ADC_OFR4 register  ******************/
2011 #define ADC_OFR4_OFFSET4_Pos           (0U)
2012 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2013 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2014 
2015 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2016 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2017 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2018 #define ADC_OFR4_SATEN_Pos             (25U)
2019 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2020 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2021 
2022 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2023 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2024 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2025 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2026 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2027 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2028 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2029 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2030 
2031 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2032 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2033 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2034 
2035 /********************  Bit definition for ADC_JDR1 register  ******************/
2036 #define ADC_JDR1_JDATA_Pos             (0U)
2037 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2038 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2039 
2040 /********************  Bit definition for ADC_JDR2 register  ******************/
2041 #define ADC_JDR2_JDATA_Pos             (0U)
2042 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2043 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2044 
2045 /********************  Bit definition for ADC_JDR3 register  ******************/
2046 #define ADC_JDR3_JDATA_Pos             (0U)
2047 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2048 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2049 
2050 /********************  Bit definition for ADC_JDR4 register  ******************/
2051 #define ADC_JDR4_JDATA_Pos             (0U)
2052 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2053 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2054 
2055 /********************  Bit definition for ADC_AWD2CR register  ****************/
2056 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2057 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2058 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2059 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2060 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2061 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2062 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2063 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2064 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2065 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2066 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2067 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2068 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2069 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2070 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2071 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2072 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2073 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2074 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2075 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2076 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2077 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2078 
2079 /********************  Bit definition for ADC_AWD3CR register  ****************/
2080 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2081 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2082 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2083 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2084 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2085 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2086 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2087 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2088 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2089 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2090 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2091 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2092 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2093 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2094 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2095 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2096 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2097 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2098 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2099 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2100 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2101 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2102 
2103 /********************  Bit definition for ADC_DIFSEL register  ****************/
2104 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2105 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2106 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2107 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2108 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2109 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2110 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2111 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2112 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2113 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2114 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2115 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2116 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2117 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2118 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2119 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2120 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2121 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2122 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2123 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2124 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2125 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2126 
2127 /********************  Bit definition for ADC_CALFACT register  ***************/
2128 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2129 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2130 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2131 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2132 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2133 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2134 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2135 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2136 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2137 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2138 
2139 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2140 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2141 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2142 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2143 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2144 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2145 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2146 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2147 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2148 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2149 
2150 /********************  Bit definition for ADC_GCOMP register  *****************/
2151 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
2152 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
2153 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
2154 
2155 /*************************  ADC Common registers  *****************************/
2156 /********************  Bit definition for ADC_CSR register  *******************/
2157 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2158 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2159 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2160 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2161 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2162 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2163 #define ADC_CSR_EOC_MST_Pos            (2U)
2164 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2165 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2166 #define ADC_CSR_EOS_MST_Pos            (3U)
2167 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2168 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2169 #define ADC_CSR_OVR_MST_Pos            (4U)
2170 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2171 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2172 #define ADC_CSR_JEOC_MST_Pos           (5U)
2173 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2174 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2175 #define ADC_CSR_JEOS_MST_Pos           (6U)
2176 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2177 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2178 #define ADC_CSR_AWD1_MST_Pos           (7U)
2179 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2180 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2181 #define ADC_CSR_AWD2_MST_Pos           (8U)
2182 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2183 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2184 #define ADC_CSR_AWD3_MST_Pos           (9U)
2185 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2186 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2187 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2188 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2189 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2190 
2191 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2192 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2193 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2194 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2195 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2196 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2197 #define ADC_CSR_EOC_SLV_Pos            (18U)
2198 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2199 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2200 #define ADC_CSR_EOS_SLV_Pos            (19U)
2201 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2202 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2203 #define ADC_CSR_OVR_SLV_Pos            (20U)
2204 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2205 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2206 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2207 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2208 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2209 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2210 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2211 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2212 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2213 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2214 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2215 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2216 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2217 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2218 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2219 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2220 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2221 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2222 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2223 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2224 
2225 /********************  Bit definition for ADC_CCR register  *******************/
2226 #define ADC_CCR_DUAL_Pos               (0U)
2227 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2228 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2229 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2230 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2231 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2232 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2233 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2234 
2235 #define ADC_CCR_DELAY_Pos              (8U)
2236 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2237 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2238 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2239 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2240 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2241 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2242 
2243 #define ADC_CCR_DMACFG_Pos             (13U)
2244 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2245 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2246 
2247 #define ADC_CCR_MDMA_Pos               (14U)
2248 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2249 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2250 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2251 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2252 
2253 #define ADC_CCR_CKMODE_Pos             (16U)
2254 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2255 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2256 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2257 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2258 
2259 #define ADC_CCR_PRESC_Pos              (18U)
2260 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2261 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2262 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2263 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2264 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2265 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2266 
2267 #define ADC_CCR_VREFEN_Pos             (22U)
2268 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2269 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2270 #define ADC_CCR_VSENSESEL_Pos          (23U)
2271 #define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
2272 #define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
2273 #define ADC_CCR_VBATSEL_Pos            (24U)
2274 #define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
2275 #define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
2276 
2277 /********************  Bit definition for ADC_CDR register  *******************/
2278 #define ADC_CDR_RDATA_MST_Pos          (0U)
2279 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2280 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2281 
2282 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2283 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2284 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2285 
2286 
2287 /******************************************************************************/
2288 /*                                                                            */
2289 /*                      Analog Comparators (COMP)                             */
2290 /*                                                                            */
2291 /******************************************************************************/
2292 /**********************  Bit definition for COMP_CSR register  ****************/
2293 #define COMP_CSR_EN_Pos            (0U)
2294 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
2295 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
2296 
2297 #define COMP_CSR_INMSEL_Pos        (4U)
2298 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
2299 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
2300 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
2301 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
2302 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
2303 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
2304 
2305 #define COMP_CSR_INPSEL_Pos        (8U)
2306 #define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
2307 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
2308 
2309 #define COMP_CSR_POLARITY_Pos      (15U)
2310 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
2311 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
2312 
2313 #define COMP_CSR_HYST_Pos          (16U)
2314 #define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
2315 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
2316 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
2317 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
2318 #define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
2319 
2320 #define COMP_CSR_BLANKING_Pos      (19U)
2321 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
2322 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
2323 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
2324 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
2325 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
2326 
2327 #define COMP_CSR_BRGEN_Pos         (22U)
2328 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
2329 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
2330 
2331 #define COMP_CSR_SCALEN_Pos        (23U)
2332 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
2333 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
2334 
2335 #define COMP_CSR_VALUE_Pos         (30U)
2336 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
2337 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
2338 
2339 #define COMP_CSR_LOCK_Pos          (31U)
2340 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
2341 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
2342 
2343 /******************************************************************************/
2344 /*                                                                            */
2345 /*                          CORDIC calculation unit                           */
2346 /*                                                                            */
2347 /******************************************************************************/
2348 /*******************  Bit definition for CORDIC_CSR register  *****************/
2349 #define CORDIC_CSR_FUNC_Pos      (0U)
2350 #define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
2351 #define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
2352 #define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
2353 #define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
2354 #define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
2355 #define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
2356 #define CORDIC_CSR_PRECISION_Pos (4U)
2357 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
2358 #define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
2359 #define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
2360 #define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
2361 #define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
2362 #define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
2363 #define CORDIC_CSR_SCALE_Pos     (8U)
2364 #define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
2365 #define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
2366 #define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
2367 #define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
2368 #define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
2369 #define CORDIC_CSR_IEN_Pos       (16U)
2370 #define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
2371 #define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
2372 #define CORDIC_CSR_DMAREN_Pos    (17U)
2373 #define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
2374 #define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
2375 #define CORDIC_CSR_DMAWEN_Pos    (18U)
2376 #define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
2377 #define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
2378 #define CORDIC_CSR_NRES_Pos      (19U)
2379 #define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
2380 #define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
2381 #define CORDIC_CSR_NARGS_Pos     (20U)
2382 #define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
2383 #define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
2384 #define CORDIC_CSR_RESSIZE_Pos   (21U)
2385 #define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
2386 #define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
2387 #define CORDIC_CSR_ARGSIZE_Pos   (22U)
2388 #define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
2389 #define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
2390 #define CORDIC_CSR_RRDY_Pos      (31U)
2391 #define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
2392 #define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
2393 
2394 /*******************  Bit definition for CORDIC_WDATA register  ***************/
2395 #define CORDIC_WDATA_ARG_Pos     (0U)
2396 #define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
2397 #define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
2398 
2399 /*******************  Bit definition for CORDIC_RDATA register  ***************/
2400 #define CORDIC_RDATA_RES_Pos     (0U)
2401 #define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
2402 #define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
2403 
2404 /******************************************************************************/
2405 /*                                                                            */
2406 /*                          CRC calculation unit                              */
2407 /*                                                                            */
2408 /******************************************************************************/
2409 /*******************  Bit definition for CRC_DR register  *********************/
2410 #define CRC_DR_DR_Pos            (0U)
2411 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2412 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2413 
2414 /*******************  Bit definition for CRC_IDR register  ********************/
2415 #define CRC_IDR_IDR_Pos          (0U)
2416 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
2417 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
2418 
2419 /********************  Bit definition for CRC_CR register  ********************/
2420 #define CRC_CR_RESET_Pos         (0U)
2421 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2422 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2423 #define CRC_CR_POLYSIZE_Pos      (3U)
2424 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2425 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2426 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2427 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2428 #define CRC_CR_REV_IN_Pos        (5U)
2429 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2430 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2431 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2432 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2433 #define CRC_CR_REV_OUT_Pos       (7U)
2434 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2435 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2436 
2437 /*******************  Bit definition for CRC_INIT register  *******************/
2438 #define CRC_INIT_INIT_Pos        (0U)
2439 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2440 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2441 
2442 /*******************  Bit definition for CRC_POL register  ********************/
2443 #define CRC_POL_POL_Pos          (0U)
2444 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2445 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2446 
2447 /******************************************************************************/
2448 /*                                                                            */
2449 /*                          CRS Clock Recovery System                         */
2450 /******************************************************************************/
2451 
2452 /*******************  Bit definition for CRS_CR register  *********************/
2453 #define CRS_CR_SYNCOKIE_Pos       (0U)
2454 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2455 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2456 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2457 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2458 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2459 #define CRS_CR_ERRIE_Pos          (2U)
2460 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2461 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2462 #define CRS_CR_ESYNCIE_Pos        (3U)
2463 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2464 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2465 #define CRS_CR_CEN_Pos            (5U)
2466 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2467 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2468 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2469 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2470 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2471 #define CRS_CR_SWSYNC_Pos         (7U)
2472 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2473 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2474 #define CRS_CR_TRIM_Pos           (8U)
2475 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2476 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2477 
2478 /*******************  Bit definition for CRS_CFGR register  *********************/
2479 #define CRS_CFGR_RELOAD_Pos       (0U)
2480 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2481 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2482 #define CRS_CFGR_FELIM_Pos        (16U)
2483 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2484 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2485 
2486 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2487 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2488 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2489 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2490 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2491 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2492 
2493 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2494 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2495 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2496 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2497 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2498 
2499 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2500 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2501 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2502 
2503 /*******************  Bit definition for CRS_ISR register  *********************/
2504 #define CRS_ISR_SYNCOKF_Pos       (0U)
2505 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2506 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2507 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2508 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2509 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2510 #define CRS_ISR_ERRF_Pos          (2U)
2511 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2512 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2513 #define CRS_ISR_ESYNCF_Pos        (3U)
2514 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2515 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2516 #define CRS_ISR_SYNCERR_Pos       (8U)
2517 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2518 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2519 #define CRS_ISR_SYNCMISS_Pos      (9U)
2520 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2521 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2522 #define CRS_ISR_TRIMOVF_Pos       (10U)
2523 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2524 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2525 #define CRS_ISR_FEDIR_Pos         (15U)
2526 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2527 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2528 #define CRS_ISR_FECAP_Pos         (16U)
2529 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2530 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2531 
2532 /*******************  Bit definition for CRS_ICR register  *********************/
2533 #define CRS_ICR_SYNCOKC_Pos       (0U)
2534 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2535 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2536 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2537 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2538 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2539 #define CRS_ICR_ERRC_Pos          (2U)
2540 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2541 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2542 #define CRS_ICR_ESYNCC_Pos        (3U)
2543 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2544 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2545 
2546 /******************************************************************************/
2547 /*                                                                            */
2548 /*                      Digital to Analog Converter                           */
2549 /*                                                                            */
2550 /******************************************************************************/
2551 /*
2552  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2553  */
2554 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
2555 
2556 /********************  Bit definition for DAC_CR register  ********************/
2557 #define DAC_CR_EN1_Pos              (0U)
2558 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2559 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2560 #define DAC_CR_TEN1_Pos             (1U)
2561 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2562 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2563 
2564 #define DAC_CR_TSEL1_Pos            (2U)
2565 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2566 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2567 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
2568 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
2569 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
2570 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
2571 
2572 #define DAC_CR_WAVE1_Pos            (6U)
2573 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2574 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2575 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
2576 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
2577 
2578 #define DAC_CR_MAMP1_Pos            (8U)
2579 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2580 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2581 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
2582 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
2583 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
2584 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
2585 
2586 #define DAC_CR_DMAEN1_Pos           (12U)
2587 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2588 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2589 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2590 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2591 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2592 #define DAC_CR_CEN1_Pos             (14U)
2593 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2594 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2595 
2596 #define DAC_CR_HFSEL_Pos            (15U)
2597 #define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
2598 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
2599 
2600 #define DAC_CR_EN2_Pos              (16U)
2601 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2602 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2603 #define DAC_CR_TEN2_Pos             (17U)
2604 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2605 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2606 
2607 #define DAC_CR_TSEL2_Pos            (18U)
2608 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2609 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2610 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
2611 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
2612 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
2613 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
2614 
2615 #define DAC_CR_WAVE2_Pos            (22U)
2616 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2617 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2618 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
2619 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
2620 
2621 #define DAC_CR_MAMP2_Pos            (24U)
2622 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2623 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2624 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
2625 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
2626 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
2627 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
2628 
2629 #define DAC_CR_DMAEN2_Pos           (28U)
2630 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2631 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2632 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2633 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2634 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2635 #define DAC_CR_CEN2_Pos             (30U)
2636 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2637 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2638 
2639 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2640 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2641 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2642 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2643 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2644 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2645 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2646 #define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
2647 #define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
2648 #define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
2649 #define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
2650 #define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
2651 #define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
2652 
2653 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2654 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2655 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2656 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2657 #define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
2658 #define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
2659 #define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
2660 
2661 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2662 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2663 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2664 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2665 #define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
2666 #define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
2667 #define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
2668 
2669 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2670 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2671 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2672 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2673 #define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
2674 #define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
2675 #define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
2676 
2677 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2678 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2679 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2680 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2681 #define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
2682 #define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
2683 #define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
2684 
2685 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2686 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2687 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2688 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2689 #define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
2690 #define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
2691 #define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
2692 
2693 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2694 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2695 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2696 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2697 #define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
2698 #define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
2699 #define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
2700 
2701 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2702 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2703 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2704 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2705 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2706 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2707 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2708 
2709 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2710 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2711 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2712 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2713 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2714 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2715 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2716 
2717 /******************  Bit definition for DAC_DHR8RD register  ******************/
2718 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2719 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2720 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2721 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2722 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2723 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2724 
2725 /*******************  Bit definition for DAC_DOR1 register  *******************/
2726 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2727 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2728 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2729 #define DAC_DOR1_DACC1DORB_Pos      (16U)
2730 #define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
2731 #define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
2732 
2733 /*******************  Bit definition for DAC_DOR2 register  *******************/
2734 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2735 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2736 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2737 #define DAC_DOR2_DACC2DORB_Pos      (16U)
2738 #define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
2739 #define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
2740 
2741 /********************  Bit definition for DAC_SR register  ********************/
2742 #define DAC_SR_DAC1RDY_Pos          (11U)
2743 #define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
2744 #define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
2745 #define DAC_SR_DORSTAT1_Pos         (12U)
2746 #define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
2747 #define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
2748 #define DAC_SR_DMAUDR1_Pos          (13U)
2749 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2750 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2751 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2752 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2753 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2754 #define DAC_SR_BWST1_Pos            (15U)
2755 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
2756 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2757 
2758 #define DAC_SR_DAC2RDY_Pos          (27U)
2759 #define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
2760 #define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
2761 #define DAC_SR_DORSTAT2_Pos         (28U)
2762 #define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
2763 #define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
2764 #define DAC_SR_DMAUDR2_Pos          (29U)
2765 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2766 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2767 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2768 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2769 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2770 #define DAC_SR_BWST2_Pos            (31U)
2771 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2772 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2773 
2774 /*******************  Bit definition for DAC_CCR register  ********************/
2775 #define DAC_CCR_OTRIM1_Pos          (0U)
2776 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2777 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2778 #define DAC_CCR_OTRIM2_Pos          (16U)
2779 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2780 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2781 
2782 /*******************  Bit definition for DAC_MCR register  *******************/
2783 #define DAC_MCR_MODE1_Pos           (0U)
2784 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2785 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2786 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
2787 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
2788 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
2789 
2790 #define DAC_MCR_DMADOUBLE1_Pos      (8U)
2791 #define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
2792 #define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
2793 
2794 #define DAC_MCR_SINFORMAT1_Pos      (9U)
2795 #define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
2796 #define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
2797 
2798 #define DAC_MCR_HFSEL_Pos           (14U)
2799 #define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
2800 #define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2801 #define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
2802 #define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
2803 
2804 #define DAC_MCR_MODE2_Pos           (16U)
2805 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
2806 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
2807 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
2808 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
2809 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
2810 
2811 #define DAC_MCR_DMADOUBLE2_Pos      (24U)
2812 #define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
2813 #define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
2814 
2815 #define DAC_MCR_SINFORMAT2_Pos      (25U)
2816 #define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
2817 #define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
2818 
2819 /******************  Bit definition for DAC_SHSR1 register  ******************/
2820 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
2821 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
2822 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
2823 
2824 /******************  Bit definition for DAC_SHSR2 register  ******************/
2825 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
2826 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
2827 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
2828 
2829 /******************  Bit definition for DAC_SHHR register  ******************/
2830 #define DAC_SHHR_THOLD1_Pos         (0U)
2831 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
2832 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
2833 #define DAC_SHHR_THOLD2_Pos         (16U)
2834 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
2835 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
2836 
2837 /******************  Bit definition for DAC_SHRR register  ******************/
2838 #define DAC_SHRR_TREFRESH1_Pos      (0U)
2839 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
2840 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
2841 #define DAC_SHRR_TREFRESH2_Pos      (16U)
2842 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
2843 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
2844 
2845 /******************  Bit definition for DAC_STR1 register  ******************/
2846 #define DAC_STR1_STRSTDATA1_Pos     (0U)
2847 #define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
2848 #define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
2849 #define DAC_STR1_STDIR1_Pos         (12U)
2850 #define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
2851 #define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
2852 
2853 #define DAC_STR1_STINCDATA1_Pos     (16U)
2854 #define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
2855 #define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
2856 
2857 /******************  Bit definition for DAC_STR2 register  ******************/
2858 #define DAC_STR2_STRSTDATA2_Pos     (0U)
2859 #define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
2860 #define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
2861 #define DAC_STR2_STDIR2_Pos         (12U)
2862 #define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
2863 #define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
2864 
2865 #define DAC_STR2_STINCDATA2_Pos     (16U)
2866 #define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
2867 #define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
2868 
2869 /******************  Bit definition for DAC_STMODR register  ****************/
2870 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
2871 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
2872 #define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2873 #define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
2874 #define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
2875 #define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
2876 #define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
2877 
2878 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
2879 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
2880 #define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2881 #define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
2882 #define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
2883 #define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
2884 #define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
2885 
2886 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
2887 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
2888 #define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2889 #define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
2890 #define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
2891 #define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
2892 #define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
2893 
2894 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
2895 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
2896 #define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2897 #define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
2898 #define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
2899 #define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
2900 #define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
2901 
2902 /******************************************************************************/
2903 /*                                                                            */
2904 /*                                 Debug MCU                                  */
2905 /*                                                                            */
2906 /******************************************************************************/
2907 /********************  Bit definition for DBGMCU_IDCODE register  *************/
2908 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
2909 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
2910 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
2911 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
2912 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
2913 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
2914 
2915 /********************  Bit definition for DBGMCU_CR register  *****************/
2916 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
2917 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
2918 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
2919 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
2920 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
2921 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
2922 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
2923 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
2924 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
2925 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
2926 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
2927 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
2928 
2929 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
2930 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
2931 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
2932 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
2933 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
2934 
2935 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
2936 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
2937 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
2938 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
2939 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
2940 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
2941 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
2942 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
2943 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
2944 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
2945 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
2946 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
2947 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
2948 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
2949 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
2950 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
2951 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
2952 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
2953 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
2954 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
2955 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
2956 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
2957 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
2958 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
2959 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
2960 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
2961 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
2962 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
2963 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
2964 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
2965 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
2966 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (30U)
2967 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
2968 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
2969 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
2970 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
2971 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
2972 
2973 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
2974 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)
2975 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
2976 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
2977 
2978 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
2979 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
2980 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
2981 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
2982 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
2983 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
2984 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
2985 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
2986 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
2987 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
2988 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
2989 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
2990 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
2991 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
2992 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
2993 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
2994 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos       (20U)
2995 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
2996 #define DBGMCU_APB2FZ_DBG_TIM20_STOP           DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
2997 
2998 /******************************************************************************/
2999 /*                                                                            */
3000 /*                           DMA Controller (DMA)                             */
3001 /*                                                                            */
3002 /******************************************************************************/
3003 
3004 /*******************  Bit definition for DMA_ISR register  ********************/
3005 #define DMA_ISR_GIF1_Pos       (0U)
3006 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
3007 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
3008 #define DMA_ISR_TCIF1_Pos      (1U)
3009 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
3010 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
3011 #define DMA_ISR_HTIF1_Pos      (2U)
3012 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
3013 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
3014 #define DMA_ISR_TEIF1_Pos      (3U)
3015 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
3016 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
3017 #define DMA_ISR_GIF2_Pos       (4U)
3018 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
3019 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
3020 #define DMA_ISR_TCIF2_Pos      (5U)
3021 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
3022 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
3023 #define DMA_ISR_HTIF2_Pos      (6U)
3024 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
3025 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
3026 #define DMA_ISR_TEIF2_Pos      (7U)
3027 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
3028 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
3029 #define DMA_ISR_GIF3_Pos       (8U)
3030 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
3031 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
3032 #define DMA_ISR_TCIF3_Pos      (9U)
3033 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
3034 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
3035 #define DMA_ISR_HTIF3_Pos      (10U)
3036 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
3037 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
3038 #define DMA_ISR_TEIF3_Pos      (11U)
3039 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
3040 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
3041 #define DMA_ISR_GIF4_Pos       (12U)
3042 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
3043 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
3044 #define DMA_ISR_TCIF4_Pos      (13U)
3045 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
3046 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
3047 #define DMA_ISR_HTIF4_Pos      (14U)
3048 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
3049 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
3050 #define DMA_ISR_TEIF4_Pos      (15U)
3051 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
3052 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
3053 #define DMA_ISR_GIF5_Pos       (16U)
3054 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
3055 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
3056 #define DMA_ISR_TCIF5_Pos      (17U)
3057 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
3058 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
3059 #define DMA_ISR_HTIF5_Pos      (18U)
3060 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
3061 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
3062 #define DMA_ISR_TEIF5_Pos      (19U)
3063 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
3064 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
3065 #define DMA_ISR_GIF6_Pos       (20U)
3066 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
3067 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
3068 #define DMA_ISR_TCIF6_Pos      (21U)
3069 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
3070 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
3071 #define DMA_ISR_HTIF6_Pos      (22U)
3072 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
3073 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
3074 #define DMA_ISR_TEIF6_Pos      (23U)
3075 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
3076 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
3077 #define DMA_ISR_GIF7_Pos       (24U)
3078 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
3079 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
3080 #define DMA_ISR_TCIF7_Pos      (25U)
3081 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
3082 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
3083 #define DMA_ISR_HTIF7_Pos      (26U)
3084 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
3085 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
3086 #define DMA_ISR_TEIF7_Pos      (27U)
3087 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
3088 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
3089 #define DMA_ISR_GIF8_Pos       (28U)
3090 #define DMA_ISR_GIF8_Msk       (0x1UL << DMA_ISR_GIF8_Pos)                     /*!< 0x10000000 */
3091 #define DMA_ISR_GIF8           DMA_ISR_GIF8_Msk                                /*!< Channel 8 Global interrupt flag */
3092 #define DMA_ISR_TCIF8_Pos      (29U)
3093 #define DMA_ISR_TCIF8_Msk      (0x1UL << DMA_ISR_TCIF8_Pos)                    /*!< 0x20000000 */
3094 #define DMA_ISR_TCIF8          DMA_ISR_TCIF8_Msk                               /*!< Channel 8 Transfer Complete flag */
3095 #define DMA_ISR_HTIF8_Pos      (30U)
3096 #define DMA_ISR_HTIF8_Msk      (0x1UL << DMA_ISR_HTIF8_Pos)                    /*!< 0x40000000 */
3097 #define DMA_ISR_HTIF8          DMA_ISR_HTIF8_Msk                               /*!< Channel 8 Half Transfer flag */
3098 #define DMA_ISR_TEIF8_Pos      (31U)
3099 #define DMA_ISR_TEIF8_Msk      (0x1UL << DMA_ISR_TEIF8_Pos)                    /*!< 0x80000000 */
3100 #define DMA_ISR_TEIF8          DMA_ISR_TEIF8_Msk                               /*!< Channel 8 Transfer Error flag */
3101 
3102 /*******************  Bit definition for DMA_IFCR register  *******************/
3103 #define DMA_IFCR_CGIF1_Pos     (0U)
3104 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
3105 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
3106 #define DMA_IFCR_CTCIF1_Pos    (1U)
3107 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
3108 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
3109 #define DMA_IFCR_CHTIF1_Pos    (2U)
3110 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
3111 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
3112 #define DMA_IFCR_CTEIF1_Pos    (3U)
3113 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
3114 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
3115 #define DMA_IFCR_CGIF2_Pos     (4U)
3116 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
3117 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
3118 #define DMA_IFCR_CTCIF2_Pos    (5U)
3119 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
3120 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
3121 #define DMA_IFCR_CHTIF2_Pos    (6U)
3122 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
3123 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
3124 #define DMA_IFCR_CTEIF2_Pos    (7U)
3125 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
3126 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
3127 #define DMA_IFCR_CGIF3_Pos     (8U)
3128 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
3129 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
3130 #define DMA_IFCR_CTCIF3_Pos    (9U)
3131 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
3132 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
3133 #define DMA_IFCR_CHTIF3_Pos    (10U)
3134 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
3135 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
3136 #define DMA_IFCR_CTEIF3_Pos    (11U)
3137 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
3138 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
3139 #define DMA_IFCR_CGIF4_Pos     (12U)
3140 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
3141 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
3142 #define DMA_IFCR_CTCIF4_Pos    (13U)
3143 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
3144 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
3145 #define DMA_IFCR_CHTIF4_Pos    (14U)
3146 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
3147 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
3148 #define DMA_IFCR_CTEIF4_Pos    (15U)
3149 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
3150 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
3151 #define DMA_IFCR_CGIF5_Pos     (16U)
3152 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
3153 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
3154 #define DMA_IFCR_CTCIF5_Pos    (17U)
3155 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
3156 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
3157 #define DMA_IFCR_CHTIF5_Pos    (18U)
3158 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
3159 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
3160 #define DMA_IFCR_CTEIF5_Pos    (19U)
3161 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
3162 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
3163 #define DMA_IFCR_CGIF6_Pos     (20U)
3164 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
3165 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
3166 #define DMA_IFCR_CTCIF6_Pos    (21U)
3167 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
3168 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
3169 #define DMA_IFCR_CHTIF6_Pos    (22U)
3170 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
3171 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
3172 #define DMA_IFCR_CTEIF6_Pos    (23U)
3173 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
3174 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
3175 #define DMA_IFCR_CGIF7_Pos     (24U)
3176 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
3177 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
3178 #define DMA_IFCR_CTCIF7_Pos    (25U)
3179 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
3180 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
3181 #define DMA_IFCR_CHTIF7_Pos    (26U)
3182 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
3183 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
3184 #define DMA_IFCR_CTEIF7_Pos    (27U)
3185 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
3186 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
3187 #define DMA_IFCR_CGIF8_Pos     (28U)
3188 #define DMA_IFCR_CGIF8_Msk     (0x1UL << DMA_IFCR_CGIF8_Pos)                   /*!< 0x10000000 */
3189 #define DMA_IFCR_CGIF8         DMA_IFCR_CGIF8_Msk                              /*!< Channel 8 Global interrupt clear */
3190 #define DMA_IFCR_CTCIF8_Pos    (29U)
3191 #define DMA_IFCR_CTCIF8_Msk    (0x1UL << DMA_IFCR_CTCIF8_Pos)                  /*!< 0x20000000 */
3192 #define DMA_IFCR_CTCIF8        DMA_IFCR_CTCIF8_Msk                             /*!< Channel 8 Transfer Complete clear */
3193 #define DMA_IFCR_CHTIF8_Pos    (30U)
3194 #define DMA_IFCR_CHTIF8_Msk    (0x1UL << DMA_IFCR_CHTIF8_Pos)                  /*!< 0x40000000 */
3195 #define DMA_IFCR_CHTIF8        DMA_IFCR_CHTIF8_Msk                             /*!< Channel 8 Half Transfer clear */
3196 #define DMA_IFCR_CTEIF8_Pos    (31U)
3197 #define DMA_IFCR_CTEIF8_Msk    (0x1UL << DMA_IFCR_CTEIF8_Pos)                  /*!< 0x80000000 */
3198 #define DMA_IFCR_CTEIF8        DMA_IFCR_CTEIF8_Msk                             /*!< Channel 8 Transfer Error clear */
3199 
3200 /*******************  Bit definition for DMA_CCR register  ********************/
3201 #define DMA_CCR_EN_Pos         (0U)
3202 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
3203 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
3204 #define DMA_CCR_TCIE_Pos       (1U)
3205 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
3206 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
3207 #define DMA_CCR_HTIE_Pos       (2U)
3208 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
3209 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
3210 #define DMA_CCR_TEIE_Pos       (3U)
3211 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
3212 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
3213 #define DMA_CCR_DIR_Pos        (4U)
3214 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
3215 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
3216 #define DMA_CCR_CIRC_Pos       (5U)
3217 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
3218 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
3219 #define DMA_CCR_PINC_Pos       (6U)
3220 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
3221 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
3222 #define DMA_CCR_MINC_Pos       (7U)
3223 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
3224 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
3225 
3226 #define DMA_CCR_PSIZE_Pos      (8U)
3227 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
3228 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
3229 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
3230 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
3231 
3232 #define DMA_CCR_MSIZE_Pos      (10U)
3233 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
3234 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
3235 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
3236 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
3237 
3238 #define DMA_CCR_PL_Pos         (12U)
3239 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
3240 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
3241 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
3242 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
3243 
3244 #define DMA_CCR_MEM2MEM_Pos    (14U)
3245 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
3246 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
3247 
3248 /******************  Bit definition for DMA_CNDTR register  *******************/
3249 #define DMA_CNDTR_NDT_Pos      (0U)
3250 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
3251 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
3252 
3253 /******************  Bit definition for DMA_CPAR register  ********************/
3254 #define DMA_CPAR_PA_Pos        (0U)
3255 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
3256 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
3257 
3258 /******************  Bit definition for DMA_CMAR register  ********************/
3259 #define DMA_CMAR_MA_Pos        (0U)
3260 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
3261 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
3262 
3263 /******************************************************************************/
3264 /*                                                                            */
3265 /*                             DMAMUX Controller                              */
3266 /*                                                                            */
3267 /******************************************************************************/
3268 
3269 /********************  Bits definition for DMAMUX_CxCR register  **************/
3270 #define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
3271 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3272 #define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
3273 #define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3274 #define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3275 #define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3276 #define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3277 #define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3278 #define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3279 #define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3280 #define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3281 
3282 #define DMAMUX_CxCR_SOIE_Pos                         (8U)
3283 #define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3284 #define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
3285 
3286 #define DMAMUX_CxCR_EGE_Pos                          (9U)
3287 #define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3288 #define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
3289 
3290 #define DMAMUX_CxCR_SE_Pos                           (16U)
3291 #define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3292 #define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
3293 
3294 #define DMAMUX_CxCR_SPOL_Pos                         (17U)
3295 #define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3296 #define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
3297 #define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3298 #define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3299 
3300 #define DMAMUX_CxCR_NBREQ_Pos                        (19U)
3301 #define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3302 #define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
3303 #define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3304 #define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3305 #define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3306 #define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3307 #define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3308 
3309 #define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
3310 #define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3311 #define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
3312 #define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3313 #define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3314 #define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3315 #define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3316 #define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3317 
3318 /********************  Bits definition for DMAMUX_CSR register  ****************/
3319 #define DMAMUX_CSR_SOF0_Pos                          (0U)
3320 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3321 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
3322 #define DMAMUX_CSR_SOF1_Pos                          (1U)
3323 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3324 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
3325 #define DMAMUX_CSR_SOF2_Pos                          (2U)
3326 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3327 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
3328 #define DMAMUX_CSR_SOF3_Pos                          (3U)
3329 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3330 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
3331 #define DMAMUX_CSR_SOF4_Pos                          (4U)
3332 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3333 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
3334 #define DMAMUX_CSR_SOF5_Pos                          (5U)
3335 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3336 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
3337 #define DMAMUX_CSR_SOF6_Pos                          (6U)
3338 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3339 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
3340 #define DMAMUX_CSR_SOF7_Pos                          (7U)
3341 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3342 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
3343 #define DMAMUX_CSR_SOF8_Pos                          (8U)
3344 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3345 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
3346 #define DMAMUX_CSR_SOF9_Pos                          (9U)
3347 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3348 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
3349 #define DMAMUX_CSR_SOF10_Pos                         (10U)
3350 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3351 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
3352 #define DMAMUX_CSR_SOF11_Pos                         (11U)
3353 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3354 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
3355 #define DMAMUX_CSR_SOF12_Pos                         (12U)
3356 #define DMAMUX_CSR_SOF12_Msk                         (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3357 #define DMAMUX_CSR_SOF12                             DMAMUX_CSR_SOF12_Msk
3358 #define DMAMUX_CSR_SOF13_Pos                         (13U)
3359 #define DMAMUX_CSR_SOF13_Msk                         (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3360 #define DMAMUX_CSR_SOF13                             DMAMUX_CSR_SOF13_Msk
3361 #define DMAMUX_CSR_SOF14_Pos                         (14U)
3362 #define DMAMUX_CSR_SOF14_Msk                         (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3363 #define DMAMUX_CSR_SOF14                             DMAMUX_CSR_SOF14_Msk
3364 #define DMAMUX_CSR_SOF15_Pos                         (15U)
3365 #define DMAMUX_CSR_SOF15_Msk                         (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3366 #define DMAMUX_CSR_SOF15                             DMAMUX_CSR_SOF15_Msk
3367 
3368 /********************  Bits definition for DMAMUX_CFR register  ****************/
3369 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
3370 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3371 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
3372 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
3373 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3374 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
3375 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
3376 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3377 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
3378 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
3379 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3380 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
3381 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
3382 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3383 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
3384 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
3385 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3386 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
3387 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
3388 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3389 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
3390 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
3391 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3392 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
3393 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
3394 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3395 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
3396 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
3397 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3398 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
3399 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
3400 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3401 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
3402 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
3403 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3404 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
3405 #define DMAMUX_CFR_CSOF12_Pos                        (12U)
3406 #define DMAMUX_CFR_CSOF12_Msk                        (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3407 #define DMAMUX_CFR_CSOF12                            DMAMUX_CFR_CSOF12_Msk
3408 #define DMAMUX_CFR_CSOF13_Pos                        (13U)
3409 #define DMAMUX_CFR_CSOF13_Msk                        (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3410 #define DMAMUX_CFR_CSOF13                            DMAMUX_CFR_CSOF13_Msk
3411 #define DMAMUX_CFR_CSOF14_Pos                        (14U)
3412 #define DMAMUX_CFR_CSOF14_Msk                        (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3413 #define DMAMUX_CFR_CSOF14                            DMAMUX_CFR_CSOF14_Msk
3414 #define DMAMUX_CFR_CSOF15_Pos                        (15U)
3415 #define DMAMUX_CFR_CSOF15_Msk                        (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3416 #define DMAMUX_CFR_CSOF15                            DMAMUX_CFR_CSOF15_Msk
3417 
3418 /********************  Bits definition for DMAMUX_RGxCR register  ************/
3419 #define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
3420 #define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3421 #define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
3422 #define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3423 #define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3424 #define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3425 #define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3426 #define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3427 
3428 #define DMAMUX_RGxCR_OIE_Pos                         (8U)
3429 #define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3430 #define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
3431 
3432 #define DMAMUX_RGxCR_GE_Pos                          (16U)
3433 #define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3434 #define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
3435 
3436 #define DMAMUX_RGxCR_GPOL_Pos                        (17U)
3437 #define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3438 #define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
3439 #define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3440 #define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3441 
3442 #define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
3443 #define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3444 #define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
3445 #define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3446 #define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3447 #define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3448 #define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3449 #define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3450 
3451 /********************  Bits definition for DMAMUX_RGSR register  **************/
3452 #define DMAMUX_RGSR_OF0_Pos                          (0U)
3453 #define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3454 #define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
3455 #define DMAMUX_RGSR_OF1_Pos                          (1U)
3456 #define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3457 #define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
3458 #define DMAMUX_RGSR_OF2_Pos                          (2U)
3459 #define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3460 #define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
3461 #define DMAMUX_RGSR_OF3_Pos                          (3U)
3462 #define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3463 #define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
3464 
3465 /********************  Bits definition for DMAMUX_RGCFR register  ************/
3466 #define DMAMUX_RGCFR_COF0_Pos                        (0U)
3467 #define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3468 #define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
3469 #define DMAMUX_RGCFR_COF1_Pos                        (1U)
3470 #define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3471 #define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
3472 #define DMAMUX_RGCFR_COF2_Pos                        (2U)
3473 #define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3474 #define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
3475 #define DMAMUX_RGCFR_COF3_Pos                        (3U)
3476 #define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3477 #define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
3478 
3479 /******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
3480 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
3481 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3482 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3483 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
3484 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3485 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3486 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
3487 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3488 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3489 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
3490 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3491 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3492 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
3493 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3494 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3495 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
3496 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3497 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3498 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
3499 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3500 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3501 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
3502 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3503 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3504 
3505 /******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
3506 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
3507 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3508 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3509 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
3510 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3511 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3512 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
3513 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3514 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3515 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
3516 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3517 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3518 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
3519 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3520 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3521 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
3522 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3523 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3524 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
3525 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3526 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3527 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
3528 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3529 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3530 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
3531 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3532 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3533 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
3534 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3535 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3536 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
3537 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3538 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3539 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
3540 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3541 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3542 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
3543 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3544 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3545 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
3546 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3547 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3548 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
3549 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3550 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3551 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
3552 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3553 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3554 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
3555 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3556 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3557 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
3558 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3559 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3560 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
3561 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3562 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3563 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
3564 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3565 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3566 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
3567 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3568 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3569 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
3570 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3571 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3572 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
3573 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3574 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3575 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
3576 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3577 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3578 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
3579 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3580 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3581 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
3582 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3583 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3584 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
3585 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3586 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3587 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
3588 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3589 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3590 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
3591 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3592 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3593 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
3594 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3595 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3596 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
3597 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3598 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3599 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
3600 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3601 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3602 
3603 
3604 /******************************************************************************/
3605 /*                                                                            */
3606 /*                    External Interrupt/Event Controller                     */
3607 /*                                                                            */
3608 /******************************************************************************/
3609 /*******************  Bit definition for EXTI_IMR1 register  ******************/
3610 #define EXTI_IMR1_IM0_Pos        (0U)
3611 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
3612 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
3613 #define EXTI_IMR1_IM1_Pos        (1U)
3614 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
3615 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
3616 #define EXTI_IMR1_IM2_Pos        (2U)
3617 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
3618 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
3619 #define EXTI_IMR1_IM3_Pos        (3U)
3620 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
3621 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
3622 #define EXTI_IMR1_IM4_Pos        (4U)
3623 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
3624 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
3625 #define EXTI_IMR1_IM5_Pos        (5U)
3626 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
3627 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
3628 #define EXTI_IMR1_IM6_Pos        (6U)
3629 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
3630 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
3631 #define EXTI_IMR1_IM7_Pos        (7U)
3632 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
3633 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
3634 #define EXTI_IMR1_IM8_Pos        (8U)
3635 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
3636 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
3637 #define EXTI_IMR1_IM9_Pos        (9U)
3638 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
3639 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
3640 #define EXTI_IMR1_IM10_Pos       (10U)
3641 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
3642 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
3643 #define EXTI_IMR1_IM11_Pos       (11U)
3644 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
3645 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
3646 #define EXTI_IMR1_IM12_Pos       (12U)
3647 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
3648 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
3649 #define EXTI_IMR1_IM13_Pos       (13U)
3650 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
3651 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
3652 #define EXTI_IMR1_IM14_Pos       (14U)
3653 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
3654 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
3655 #define EXTI_IMR1_IM15_Pos       (15U)
3656 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
3657 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
3658 #define EXTI_IMR1_IM16_Pos       (16U)
3659 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
3660 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
3661 #define EXTI_IMR1_IM17_Pos       (17U)
3662 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
3663 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
3664 #define EXTI_IMR1_IM18_Pos       (18U)
3665 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
3666 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
3667 #define EXTI_IMR1_IM19_Pos       (19U)
3668 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
3669 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
3670 #define EXTI_IMR1_IM20_Pos       (20U)
3671 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
3672 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
3673 #define EXTI_IMR1_IM21_Pos       (21U)
3674 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
3675 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
3676 #define EXTI_IMR1_IM22_Pos       (22U)
3677 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
3678 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
3679 #define EXTI_IMR1_IM23_Pos       (23U)
3680 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
3681 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
3682 #define EXTI_IMR1_IM24_Pos       (24U)
3683 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
3684 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
3685 #define EXTI_IMR1_IM25_Pos       (25U)
3686 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
3687 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
3688 #define EXTI_IMR1_IM26_Pos       (26U)
3689 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
3690 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
3691 #define EXTI_IMR1_IM27_Pos       (27U)
3692 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
3693 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
3694 #define EXTI_IMR1_IM28_Pos       (28U)
3695 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
3696 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
3697 #define EXTI_IMR1_IM29_Pos       (29U)
3698 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
3699 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
3700 #define EXTI_IMR1_IM30_Pos       (30U)
3701 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
3702 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
3703 #define EXTI_IMR1_IM_Pos         (0U)
3704 #define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */
3705 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
3706 
3707 /*******************  Bit definition for EXTI_EMR1 register  ******************/
3708 #define EXTI_EMR1_EM0_Pos        (0U)
3709 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
3710 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
3711 #define EXTI_EMR1_EM1_Pos        (1U)
3712 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
3713 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
3714 #define EXTI_EMR1_EM2_Pos        (2U)
3715 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
3716 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
3717 #define EXTI_EMR1_EM3_Pos        (3U)
3718 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
3719 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
3720 #define EXTI_EMR1_EM4_Pos        (4U)
3721 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
3722 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
3723 #define EXTI_EMR1_EM5_Pos        (5U)
3724 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
3725 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
3726 #define EXTI_EMR1_EM6_Pos        (6U)
3727 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
3728 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
3729 #define EXTI_EMR1_EM7_Pos        (7U)
3730 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
3731 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
3732 #define EXTI_EMR1_EM8_Pos        (8U)
3733 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
3734 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
3735 #define EXTI_EMR1_EM9_Pos        (9U)
3736 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
3737 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
3738 #define EXTI_EMR1_EM10_Pos       (10U)
3739 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
3740 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
3741 #define EXTI_EMR1_EM11_Pos       (11U)
3742 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
3743 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
3744 #define EXTI_EMR1_EM12_Pos       (12U)
3745 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
3746 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
3747 #define EXTI_EMR1_EM13_Pos       (13U)
3748 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
3749 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
3750 #define EXTI_EMR1_EM14_Pos       (14U)
3751 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
3752 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
3753 #define EXTI_EMR1_EM15_Pos       (15U)
3754 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
3755 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
3756 #define EXTI_EMR1_EM16_Pos       (16U)
3757 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
3758 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
3759 #define EXTI_EMR1_EM17_Pos       (17U)
3760 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
3761 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
3762 #define EXTI_EMR1_EM18_Pos       (18U)
3763 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
3764 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
3765 #define EXTI_EMR1_EM19_Pos       (19U)
3766 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
3767 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
3768 #define EXTI_EMR1_EM20_Pos       (20U)
3769 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
3770 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
3771 #define EXTI_EMR1_EM21_Pos       (21U)
3772 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
3773 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
3774 #define EXTI_EMR1_EM22_Pos       (22U)
3775 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
3776 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
3777 #define EXTI_EMR1_EM23_Pos       (23U)
3778 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
3779 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
3780 #define EXTI_EMR1_EM24_Pos       (24U)
3781 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
3782 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
3783 #define EXTI_EMR1_EM25_Pos       (25U)
3784 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
3785 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
3786 #define EXTI_EMR1_EM26_Pos       (26U)
3787 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
3788 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
3789 #define EXTI_EMR1_EM27_Pos       (27U)
3790 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
3791 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
3792 #define EXTI_EMR1_EM28_Pos       (28U)
3793 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
3794 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
3795 #define EXTI_EMR1_EM29_Pos       (29U)
3796 #define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
3797 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
3798 #define EXTI_EMR1_EM30_Pos       (30U)
3799 #define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
3800 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
3801 
3802 /******************  Bit definition for EXTI_RTSR1 register  ******************/
3803 #define EXTI_RTSR1_RT0_Pos       (0U)
3804 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
3805 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
3806 #define EXTI_RTSR1_RT1_Pos       (1U)
3807 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
3808 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
3809 #define EXTI_RTSR1_RT2_Pos       (2U)
3810 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
3811 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
3812 #define EXTI_RTSR1_RT3_Pos       (3U)
3813 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
3814 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
3815 #define EXTI_RTSR1_RT4_Pos       (4U)
3816 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
3817 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
3818 #define EXTI_RTSR1_RT5_Pos       (5U)
3819 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
3820 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
3821 #define EXTI_RTSR1_RT6_Pos       (6U)
3822 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
3823 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
3824 #define EXTI_RTSR1_RT7_Pos       (7U)
3825 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
3826 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
3827 #define EXTI_RTSR1_RT8_Pos       (8U)
3828 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
3829 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
3830 #define EXTI_RTSR1_RT9_Pos       (9U)
3831 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
3832 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
3833 #define EXTI_RTSR1_RT10_Pos      (10U)
3834 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
3835 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
3836 #define EXTI_RTSR1_RT11_Pos      (11U)
3837 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
3838 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
3839 #define EXTI_RTSR1_RT12_Pos      (12U)
3840 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
3841 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
3842 #define EXTI_RTSR1_RT13_Pos      (13U)
3843 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
3844 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
3845 #define EXTI_RTSR1_RT14_Pos      (14U)
3846 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
3847 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
3848 #define EXTI_RTSR1_RT15_Pos      (15U)
3849 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
3850 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
3851 #define EXTI_RTSR1_RT16_Pos      (16U)
3852 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
3853 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
3854 #define EXTI_RTSR1_RT17_Pos      (17U)
3855 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
3856 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
3857 #define EXTI_RTSR1_RT19_Pos      (19U)
3858 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
3859 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
3860 #define EXTI_RTSR1_RT20_Pos      (20U)
3861 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
3862 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
3863 #define EXTI_RTSR1_RT21_Pos      (21U)
3864 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
3865 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
3866 #define EXTI_RTSR1_RT22_Pos      (22U)
3867 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
3868 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
3869 #define EXTI_RTSR1_RT29_Pos      (29U)
3870 #define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
3871 #define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
3872 #define EXTI_RTSR1_RT30_Pos      (30U)
3873 #define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
3874 #define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
3875 
3876 /******************  Bit definition for EXTI_FTSR1 register  ******************/
3877 #define EXTI_FTSR1_FT0_Pos       (0U)
3878 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
3879 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
3880 #define EXTI_FTSR1_FT1_Pos       (1U)
3881 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
3882 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
3883 #define EXTI_FTSR1_FT2_Pos       (2U)
3884 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
3885 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
3886 #define EXTI_FTSR1_FT3_Pos       (3U)
3887 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
3888 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
3889 #define EXTI_FTSR1_FT4_Pos       (4U)
3890 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
3891 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
3892 #define EXTI_FTSR1_FT5_Pos       (5U)
3893 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
3894 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
3895 #define EXTI_FTSR1_FT6_Pos       (6U)
3896 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
3897 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
3898 #define EXTI_FTSR1_FT7_Pos       (7U)
3899 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
3900 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
3901 #define EXTI_FTSR1_FT8_Pos       (8U)
3902 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
3903 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
3904 #define EXTI_FTSR1_FT9_Pos       (9U)
3905 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
3906 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
3907 #define EXTI_FTSR1_FT10_Pos      (10U)
3908 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
3909 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
3910 #define EXTI_FTSR1_FT11_Pos      (11U)
3911 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
3912 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
3913 #define EXTI_FTSR1_FT12_Pos      (12U)
3914 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
3915 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
3916 #define EXTI_FTSR1_FT13_Pos      (13U)
3917 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
3918 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
3919 #define EXTI_FTSR1_FT14_Pos      (14U)
3920 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
3921 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
3922 #define EXTI_FTSR1_FT15_Pos      (15U)
3923 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
3924 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
3925 #define EXTI_FTSR1_FT16_Pos      (16U)
3926 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
3927 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
3928 #define EXTI_FTSR1_FT17_Pos      (17U)
3929 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
3930 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
3931 #define EXTI_FTSR1_FT19_Pos      (19U)
3932 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
3933 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
3934 #define EXTI_FTSR1_FT20_Pos      (20U)
3935 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
3936 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
3937 #define EXTI_FTSR1_FT21_Pos      (21U)
3938 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
3939 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
3940 #define EXTI_FTSR1_FT22_Pos      (22U)
3941 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
3942 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
3943 #define EXTI_FTSR1_FT29_Pos      (29U)
3944 #define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
3945 #define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
3946 #define EXTI_FTSR1_FT30_Pos      (30U)
3947 #define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
3948 #define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
3949 
3950 /******************  Bit definition for EXTI_SWIER1 register  *****************/
3951 #define EXTI_SWIER1_SWI0_Pos     (0U)
3952 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
3953 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
3954 #define EXTI_SWIER1_SWI1_Pos     (1U)
3955 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
3956 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
3957 #define EXTI_SWIER1_SWI2_Pos     (2U)
3958 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
3959 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
3960 #define EXTI_SWIER1_SWI3_Pos     (3U)
3961 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
3962 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
3963 #define EXTI_SWIER1_SWI4_Pos     (4U)
3964 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
3965 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
3966 #define EXTI_SWIER1_SWI5_Pos     (5U)
3967 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
3968 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
3969 #define EXTI_SWIER1_SWI6_Pos     (6U)
3970 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
3971 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
3972 #define EXTI_SWIER1_SWI7_Pos     (7U)
3973 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
3974 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
3975 #define EXTI_SWIER1_SWI8_Pos     (8U)
3976 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
3977 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
3978 #define EXTI_SWIER1_SWI9_Pos     (9U)
3979 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
3980 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
3981 #define EXTI_SWIER1_SWI10_Pos    (10U)
3982 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
3983 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
3984 #define EXTI_SWIER1_SWI11_Pos    (11U)
3985 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
3986 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
3987 #define EXTI_SWIER1_SWI12_Pos    (12U)
3988 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
3989 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
3990 #define EXTI_SWIER1_SWI13_Pos    (13U)
3991 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
3992 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
3993 #define EXTI_SWIER1_SWI14_Pos    (14U)
3994 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
3995 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
3996 #define EXTI_SWIER1_SWI15_Pos    (15U)
3997 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
3998 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
3999 #define EXTI_SWIER1_SWI16_Pos    (16U)
4000 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
4001 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
4002 #define EXTI_SWIER1_SWI17_Pos    (17U)
4003 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
4004 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
4005 #define EXTI_SWIER1_SWI19_Pos    (19U)
4006 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
4007 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
4008 #define EXTI_SWIER1_SWI20_Pos    (20U)
4009 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
4010 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
4011 #define EXTI_SWIER1_SWI21_Pos    (21U)
4012 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
4013 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
4014 #define EXTI_SWIER1_SWI22_Pos    (22U)
4015 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
4016 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
4017 #define EXTI_SWIER1_SWI29_Pos    (29U)
4018 #define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
4019 #define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
4020 #define EXTI_SWIER1_SWI30_Pos    (30U)
4021 #define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
4022 #define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
4023 
4024 /*******************  Bit definition for EXTI_PR1 register  *******************/
4025 #define EXTI_PR1_PIF0_Pos        (0U)
4026 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
4027 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
4028 #define EXTI_PR1_PIF1_Pos        (1U)
4029 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
4030 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
4031 #define EXTI_PR1_PIF2_Pos        (2U)
4032 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
4033 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
4034 #define EXTI_PR1_PIF3_Pos        (3U)
4035 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
4036 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
4037 #define EXTI_PR1_PIF4_Pos        (4U)
4038 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
4039 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
4040 #define EXTI_PR1_PIF5_Pos        (5U)
4041 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
4042 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
4043 #define EXTI_PR1_PIF6_Pos        (6U)
4044 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
4045 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
4046 #define EXTI_PR1_PIF7_Pos        (7U)
4047 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
4048 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
4049 #define EXTI_PR1_PIF8_Pos        (8U)
4050 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
4051 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
4052 #define EXTI_PR1_PIF9_Pos        (9U)
4053 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
4054 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
4055 #define EXTI_PR1_PIF10_Pos       (10U)
4056 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
4057 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
4058 #define EXTI_PR1_PIF11_Pos       (11U)
4059 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
4060 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
4061 #define EXTI_PR1_PIF12_Pos       (12U)
4062 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
4063 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
4064 #define EXTI_PR1_PIF13_Pos       (13U)
4065 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
4066 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
4067 #define EXTI_PR1_PIF14_Pos       (14U)
4068 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
4069 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
4070 #define EXTI_PR1_PIF15_Pos       (15U)
4071 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
4072 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
4073 #define EXTI_PR1_PIF16_Pos       (16U)
4074 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
4075 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
4076 #define EXTI_PR1_PIF17_Pos       (17U)
4077 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
4078 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
4079 #define EXTI_PR1_PIF19_Pos       (19U)
4080 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
4081 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
4082 #define EXTI_PR1_PIF20_Pos       (20U)
4083 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
4084 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
4085 #define EXTI_PR1_PIF21_Pos       (21U)
4086 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
4087 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
4088 #define EXTI_PR1_PIF22_Pos       (22U)
4089 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
4090 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
4091 #define EXTI_PR1_PIF29_Pos       (29U)
4092 #define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
4093 #define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
4094 #define EXTI_PR1_PIF30_Pos       (30U)
4095 #define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
4096 #define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
4097 
4098 /*******************  Bit definition for EXTI_IMR2 register  ******************/
4099 #define EXTI_IMR2_IM34_Pos       (2U)
4100 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
4101 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
4102 #define EXTI_IMR2_IM35_Pos       (3U)
4103 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
4104 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
4105 #define EXTI_IMR2_IM36_Pos       (4U)
4106 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
4107 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
4108 #define EXTI_IMR2_IM37_Pos       (5U)
4109 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
4110 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
4111 #define EXTI_IMR2_IM38_Pos       (6U)
4112 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
4113 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
4114 #define EXTI_IMR2_IM39_Pos       (7U)
4115 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
4116 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
4117 #define EXTI_IMR2_IM40_Pos       (8U)
4118 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
4119 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
4120 #define EXTI_IMR2_IM41_Pos       (9U)
4121 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
4122 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
4123 #define EXTI_IMR2_IM42_Pos       (10U)
4124 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
4125 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< Interrupt Mask on line 42 */
4126 #define EXTI_IMR2_IM_Pos         (0U)
4127 #define EXTI_IMR2_IM_Msk         (0x7FFUL << EXTI_IMR2_IM_Pos)                 /*!< 0x000007FF */
4128 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
4129 
4130 /*******************  Bit definition for EXTI_EMR2 register  ******************/
4131 #define EXTI_EMR2_EM34_Pos       (2U)
4132 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
4133 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
4134 #define EXTI_EMR2_EM35_Pos       (3U)
4135 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
4136 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
4137 #define EXTI_EMR2_EM36_Pos       (4U)
4138 #define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
4139 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
4140 #define EXTI_EMR2_EM37_Pos       (5U)
4141 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
4142 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
4143 #define EXTI_EMR2_EM38_Pos       (6U)
4144 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
4145 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
4146 #define EXTI_EMR2_EM39_Pos       (7U)
4147 #define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
4148 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
4149 #define EXTI_EMR2_EM40_Pos       (8U)
4150 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
4151 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
4152 #define EXTI_EMR2_EM41_Pos       (9U)
4153 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
4154 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
4155 #define EXTI_EMR2_EM42_Pos       (10U)
4156 #define EXTI_EMR2_EM42_Msk       (0x1UL << EXTI_EMR2_EM42_Pos)                 /*!< 0x00000400 */
4157 #define EXTI_EMR2_EM42           EXTI_EMR2_EM42_Msk                            /*!< Event Mask on line 42 */
4158 #define EXTI_EMR2_EM_Pos         (0U)
4159 #define EXTI_EMR2_EM_Msk         (0x7FFUL << EXTI_EMR2_EM_Pos)                 /*!< 0x000007FF */
4160 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
4161 
4162 /******************  Bit definition for EXTI_RTSR2 register  ******************/
4163 #define EXTI_RTSR2_RT38_Pos      (6U)
4164 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
4165 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
4166 #define EXTI_RTSR2_RT39_Pos      (7U)
4167 #define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
4168 #define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
4169 #define EXTI_RTSR2_RT40_Pos      (8U)
4170 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
4171 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
4172 #define EXTI_RTSR2_RT41_Pos      (9U)
4173 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
4174 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
4175 
4176 /******************  Bit definition for EXTI_FTSR2 register  ******************/
4177 #define EXTI_FTSR2_FT38_Pos      (6U)
4178 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
4179 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
4180 #define EXTI_FTSR2_FT39_Pos      (7U)
4181 #define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
4182 #define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
4183 #define EXTI_FTSR2_FT40_Pos      (8U)
4184 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
4185 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
4186 #define EXTI_FTSR2_FT41_Pos      (9U)
4187 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
4188 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
4189 
4190 /******************  Bit definition for EXTI_SWIER2 register  *****************/
4191 #define EXTI_SWIER2_SWI38_Pos    (6U)
4192 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
4193 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
4194 #define EXTI_SWIER2_SWI39_Pos    (7U)
4195 #define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
4196 #define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
4197 #define EXTI_SWIER2_SWI40_Pos    (8U)
4198 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
4199 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
4200 #define EXTI_SWIER2_SWI41_Pos    (9U)
4201 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
4202 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
4203 
4204 /*******************  Bit definition for EXTI_PR2 register  *******************/
4205 #define EXTI_PR2_PIF38_Pos       (6U)
4206 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
4207 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
4208 #define EXTI_PR2_PIF39_Pos       (7U)
4209 #define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
4210 #define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
4211 #define EXTI_PR2_PIF40_Pos       (8U)
4212 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
4213 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
4214 #define EXTI_PR2_PIF41_Pos       (9U)
4215 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
4216 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
4217 
4218 /******************************************************************************/
4219 /*                                                                            */
4220 /*                 Flexible Datarate Controller Area Network                  */
4221 /*                                                                            */
4222 /******************************************************************************/
4223 /*!<FDCAN control and status registers */
4224 /*****************  Bit definition for FDCAN_CREL register  *******************/
4225 #define FDCAN_CREL_DAY_Pos        (0U)
4226 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
4227 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4228 #define FDCAN_CREL_MON_Pos        (8U)
4229 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
4230 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4231 #define FDCAN_CREL_YEAR_Pos       (16U)
4232 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
4233 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4234 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
4235 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
4236 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
4237 #define FDCAN_CREL_STEP_Pos       (24U)
4238 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
4239 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
4240 #define FDCAN_CREL_REL_Pos        (28U)
4241 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
4242 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
4243 
4244 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4245 #define FDCAN_ENDN_ETV_Pos        (0U)
4246 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
4247 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                    */
4248 
4249 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4250 #define FDCAN_DBTP_DSJW_Pos       (0U)
4251 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
4252 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
4253 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
4254 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
4255 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
4256 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
4257 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
4258 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
4259 #define FDCAN_DBTP_DBRP_Pos       (16U)
4260 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
4261 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
4262 #define FDCAN_DBTP_TDC_Pos        (23U)
4263 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
4264 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
4265 
4266 /*****************  Bit definition for FDCAN_TEST register  *******************/
4267 #define FDCAN_TEST_LBCK_Pos       (4U)
4268 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
4269 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
4270 #define FDCAN_TEST_TX_Pos         (5U)
4271 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
4272 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
4273 #define FDCAN_TEST_RX_Pos         (7U)
4274 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
4275 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
4276 
4277 /*****************  Bit definition for FDCAN_RWD register  ********************/
4278 #define FDCAN_RWD_WDC_Pos         (0U)
4279 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
4280 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
4281 #define FDCAN_RWD_WDV_Pos         (8U)
4282 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
4283 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
4284 
4285 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4286 #define FDCAN_CCCR_INIT_Pos       (0U)
4287 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
4288 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
4289 #define FDCAN_CCCR_CCE_Pos        (1U)
4290 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
4291 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
4292 #define FDCAN_CCCR_ASM_Pos        (2U)
4293 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
4294 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
4295 #define FDCAN_CCCR_CSA_Pos        (3U)
4296 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
4297 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
4298 #define FDCAN_CCCR_CSR_Pos        (4U)
4299 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
4300 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
4301 #define FDCAN_CCCR_MON_Pos        (5U)
4302 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
4303 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
4304 #define FDCAN_CCCR_DAR_Pos        (6U)
4305 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
4306 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
4307 #define FDCAN_CCCR_TEST_Pos       (7U)
4308 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4309 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4310 #define FDCAN_CCCR_FDOE_Pos       (8U)
4311 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4312 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4313 #define FDCAN_CCCR_BRSE_Pos       (9U)
4314 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4315 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4316 #define FDCAN_CCCR_PXHD_Pos       (12U)
4317 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4318 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4319 #define FDCAN_CCCR_EFBI_Pos       (13U)
4320 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4321 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4322 #define FDCAN_CCCR_TXP_Pos        (14U)
4323 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4324 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4325 #define FDCAN_CCCR_NISO_Pos       (15U)
4326 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4327 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4328 
4329 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4330 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4331 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4332 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4333 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4334 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4335 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4336 #define FDCAN_NBTP_NBRP_Pos       (16U)
4337 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4338 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4339 #define FDCAN_NBTP_NSJW_Pos       (25U)
4340 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4341 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4342 
4343 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4344 #define FDCAN_TSCC_TSS_Pos        (0U)
4345 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4346 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4347 #define FDCAN_TSCC_TCP_Pos        (16U)
4348 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4349 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4350 
4351 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4352 #define FDCAN_TSCV_TSC_Pos        (0U)
4353 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4354 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4355 
4356 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4357 #define FDCAN_TOCC_ETOC_Pos       (0U)
4358 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4359 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4360 #define FDCAN_TOCC_TOS_Pos        (1U)
4361 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4362 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4363 #define FDCAN_TOCC_TOP_Pos        (16U)
4364 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4365 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4366 
4367 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4368 #define FDCAN_TOCV_TOC_Pos        (0U)
4369 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4370 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4371 
4372 /*****************  Bit definition for FDCAN_ECR register  *********************/
4373 #define FDCAN_ECR_TEC_Pos         (0U)
4374 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
4375 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4376 #define FDCAN_ECR_REC_Pos         (8U)
4377 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4378 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4379 #define FDCAN_ECR_RP_Pos          (15U)
4380 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4381 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4382 #define FDCAN_ECR_CEL_Pos         (16U)
4383 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4384 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4385 
4386 /*****************  Bit definition for FDCAN_PSR register  *********************/
4387 #define FDCAN_PSR_LEC_Pos         (0U)
4388 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4389 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4390 #define FDCAN_PSR_ACT_Pos         (3U)
4391 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4392 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4393 #define FDCAN_PSR_EP_Pos          (5U)
4394 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4395 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4396 #define FDCAN_PSR_EW_Pos          (6U)
4397 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4398 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4399 #define FDCAN_PSR_BO_Pos          (7U)
4400 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4401 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4402 #define FDCAN_PSR_DLEC_Pos        (8U)
4403 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4404 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4405 #define FDCAN_PSR_RESI_Pos        (11U)
4406 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4407 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4408 #define FDCAN_PSR_RBRS_Pos        (12U)
4409 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4410 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4411 #define FDCAN_PSR_REDL_Pos        (13U)
4412 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4413 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4414 #define FDCAN_PSR_PXE_Pos         (14U)
4415 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4416 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4417 #define FDCAN_PSR_TDCV_Pos        (16U)
4418 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4419 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4420 
4421 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4422 #define FDCAN_TDCR_TDCF_Pos       (0U)
4423 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4424 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4425 #define FDCAN_TDCR_TDCO_Pos       (8U)
4426 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4427 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4428 
4429 /*****************  Bit definition for FDCAN_IR register  **********************/
4430 #define FDCAN_IR_RF0N_Pos         (0U)
4431 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4432 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4433 #define FDCAN_IR_RF0F_Pos         (1U)
4434 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
4435 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4436 #define FDCAN_IR_RF0L_Pos         (2U)
4437 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
4438 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4439 #define FDCAN_IR_RF1N_Pos         (3U)
4440 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
4441 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4442 #define FDCAN_IR_RF1F_Pos         (4U)
4443 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
4444 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4445 #define FDCAN_IR_RF1L_Pos         (5U)
4446 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
4447 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4448 #define FDCAN_IR_HPM_Pos          (6U)
4449 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
4450 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4451 #define FDCAN_IR_TC_Pos           (7U)
4452 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
4453 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4454 #define FDCAN_IR_TCF_Pos          (8U)
4455 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
4456 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4457 #define FDCAN_IR_TFE_Pos          (9U)
4458 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
4459 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4460 #define FDCAN_IR_TEFN_Pos         (10U)
4461 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
4462 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4463 #define FDCAN_IR_TEFF_Pos         (11U)
4464 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
4465 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4466 #define FDCAN_IR_TEFL_Pos         (12U)
4467 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
4468 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4469 #define FDCAN_IR_TSW_Pos          (13U)
4470 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
4471 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4472 #define FDCAN_IR_MRAF_Pos         (14U)
4473 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
4474 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4475 #define FDCAN_IR_TOO_Pos          (15U)
4476 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
4477 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4478 #define FDCAN_IR_ELO_Pos          (16U)
4479 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
4480 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4481 #define FDCAN_IR_EP_Pos           (17U)
4482 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
4483 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4484 #define FDCAN_IR_EW_Pos           (18U)
4485 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
4486 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4487 #define FDCAN_IR_BO_Pos           (19U)
4488 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
4489 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4490 #define FDCAN_IR_WDI_Pos          (20U)
4491 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
4492 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4493 #define FDCAN_IR_PEA_Pos          (21U)
4494 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
4495 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4496 #define FDCAN_IR_PED_Pos          (22U)
4497 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
4498 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4499 #define FDCAN_IR_ARA_Pos          (23U)
4500 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
4501 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4502 
4503 /*****************  Bit definition for FDCAN_IE register  **********************/
4504 #define FDCAN_IE_RF0NE_Pos        (0U)
4505 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4506 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
4507 #define FDCAN_IE_RF0FE_Pos        (1U)
4508 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
4509 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
4510 #define FDCAN_IE_RF0LE_Pos        (2U)
4511 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
4512 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
4513 #define FDCAN_IE_RF1NE_Pos        (3U)
4514 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
4515 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
4516 #define FDCAN_IE_RF1FE_Pos        (4U)
4517 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
4518 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
4519 #define FDCAN_IE_RF1LE_Pos        (5U)
4520 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
4521 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
4522 #define FDCAN_IE_HPME_Pos         (6U)
4523 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
4524 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
4525 #define FDCAN_IE_TCE_Pos          (7U)
4526 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
4527 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
4528 #define FDCAN_IE_TCFE_Pos         (8U)
4529 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
4530 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
4531 #define FDCAN_IE_TFEE_Pos         (9U)
4532 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
4533 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
4534 #define FDCAN_IE_TEFNE_Pos        (10U)
4535 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
4536 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
4537 #define FDCAN_IE_TEFFE_Pos        (11U)
4538 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
4539 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
4540 #define FDCAN_IE_TEFLE_Pos        (12U)
4541 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
4542 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
4543 #define FDCAN_IE_TSWE_Pos         (13U)
4544 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
4545 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
4546 #define FDCAN_IE_MRAFE_Pos        (14U)
4547 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
4548 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
4549 #define FDCAN_IE_TOOE_Pos         (15U)
4550 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
4551 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
4552 #define FDCAN_IE_ELOE_Pos         (16U)
4553 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
4554 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
4555 #define FDCAN_IE_EPE_Pos          (17U)
4556 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
4557 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
4558 #define FDCAN_IE_EWE_Pos          (18U)
4559 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
4560 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
4561 #define FDCAN_IE_BOE_Pos          (19U)
4562 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
4563 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
4564 #define FDCAN_IE_WDIE_Pos         (20U)
4565 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
4566 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
4567 #define FDCAN_IE_PEAE_Pos         (21U)
4568 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
4569 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
4570 #define FDCAN_IE_PEDE_Pos         (22U)
4571 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
4572 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
4573 #define FDCAN_IE_ARAE_Pos         (23U)
4574 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
4575 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
4576 
4577 /*****************  Bit definition for FDCAN_ILS register  **********************/
4578 #define FDCAN_ILS_RXFIFO0_Pos     (0U)
4579 #define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
4580 #define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
4581                                                                                    Rx FIFO 0 is Full
4582                                                                                    Rx FIFO 0 Has New Message                */
4583 #define FDCAN_ILS_RXFIFO1_Pos     (1U)
4584 #define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
4585 #define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
4586                                                                                    Rx FIFO 1 is Full
4587                                                                                    Rx FIFO 1 Has New Message                */
4588 #define FDCAN_ILS_SMSG_Pos        (2U)
4589 #define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
4590 #define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
4591                                                                                    Transmission Completed
4592                                                                                    High Priority Message                    */
4593 #define FDCAN_ILS_TFERR_Pos       (3U)
4594 #define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
4595 #define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
4596                                                                                    Tx Event FIFO Full
4597                                                                                    Tx Event FIFO New Entry
4598                                                                                    Tx FIFO Empty Interrupt Line             */
4599 #define FDCAN_ILS_MISC_Pos        (4U)
4600 #define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
4601 #define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
4602                                                                                     Message RAM Access Failure
4603                                                                                     Timestamp Wraparound                    */
4604 #define FDCAN_ILS_BERR_Pos        (5U)
4605 #define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
4606 #define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
4607                                                                                    Error Logging Overflow                   */
4608 #define FDCAN_ILS_PERR_Pos        (6U)
4609 #define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
4610 #define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
4611                                                                                    Protocol Error in Data Phase Line
4612                                                                                    Protocol Error in Arbitration Phase Line
4613                                                                                    Watchdog Interrupt Line
4614                                                                                    Bus_Off Status
4615                                                                                    Warning Status                           */
4616 
4617 /*****************  Bit definition for FDCAN_ILE register  **********************/
4618 #define FDCAN_ILE_EINT0_Pos       (0U)
4619 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4620 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
4621 #define FDCAN_ILE_EINT1_Pos       (1U)
4622 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4623 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
4624 
4625 /*****************  Bit definition for FDCAN_RXGFC register  ********************/
4626 #define FDCAN_RXGFC_RRFE_Pos      (0U)
4627 #define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
4628 #define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
4629 #define FDCAN_RXGFC_RRFS_Pos      (1U)
4630 #define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
4631 #define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
4632 #define FDCAN_RXGFC_ANFE_Pos      (2U)
4633 #define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
4634 #define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
4635 #define FDCAN_RXGFC_ANFS_Pos      (4U)
4636 #define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
4637 #define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
4638 #define FDCAN_RXGFC_F1OM_Pos      (8U)
4639 #define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
4640 #define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
4641 #define FDCAN_RXGFC_F0OM_Pos      (9U)
4642 #define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
4643 #define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
4644 #define FDCAN_RXGFC_LSS_Pos       (16U)
4645 #define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
4646 #define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
4647 #define FDCAN_RXGFC_LSE_Pos       (24U)
4648 #define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
4649 #define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
4650 
4651 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4652 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4653 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4654 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
4655 
4656 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4657 #define FDCAN_HPMS_BIDX_Pos       (0U)
4658 #define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
4659 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
4660 #define FDCAN_HPMS_MSI_Pos        (6U)
4661 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4662 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
4663 #define FDCAN_HPMS_FIDX_Pos       (8U)
4664 #define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
4665 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
4666 #define FDCAN_HPMS_FLST_Pos       (15U)
4667 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4668 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
4669 
4670 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4671 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4672 #define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
4673 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
4674 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4675 #define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
4676 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
4677 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4678 #define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
4679 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
4680 #define FDCAN_RXF0S_F0F_Pos       (24U)
4681 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4682 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
4683 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4684 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4685 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
4686 
4687 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4688 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4689 #define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
4690 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
4691 
4692 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4693 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4694 #define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
4695 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
4696 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4697 #define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
4698 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
4699 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4700 #define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
4701 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
4702 #define FDCAN_RXF1S_F1F_Pos       (24U)
4703 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4704 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
4705 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4706 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4707 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
4708 
4709 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4710 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4711 #define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
4712 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
4713 
4714 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4715 #define FDCAN_TXBC_TFQM_Pos       (24U)
4716 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
4717 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
4718 
4719 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4720 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4721 #define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
4722 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
4723 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4724 #define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
4725 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
4726 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4727 #define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
4728 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
4729 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4730 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4731 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
4732 
4733 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
4734 #define FDCAN_TXBRP_TRP_Pos       (0U)
4735 #define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
4736 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
4737 
4738 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
4739 #define FDCAN_TXBAR_AR_Pos        (0U)
4740 #define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
4741 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
4742 
4743 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
4744 #define FDCAN_TXBCR_CR_Pos        (0U)
4745 #define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
4746 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
4747 
4748 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
4749 #define FDCAN_TXBTO_TO_Pos        (0U)
4750 #define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
4751 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
4752 
4753 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
4754 #define FDCAN_TXBCF_CF_Pos        (0U)
4755 #define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
4756 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
4757 
4758 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
4759 #define FDCAN_TXBTIE_TIE_Pos      (0U)
4760 #define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
4761 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
4762 
4763 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
4764 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
4765 #define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
4766 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
4767 
4768 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
4769 #define FDCAN_TXEFS_EFFL_Pos      (0U)
4770 #define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
4771 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
4772 #define FDCAN_TXEFS_EFGI_Pos      (8U)
4773 #define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
4774 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
4775 #define FDCAN_TXEFS_EFPI_Pos      (16U)
4776 #define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
4777 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
4778 #define FDCAN_TXEFS_EFF_Pos       (24U)
4779 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
4780 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
4781 #define FDCAN_TXEFS_TEFL_Pos      (25U)
4782 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
4783 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
4784 
4785 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
4786 #define FDCAN_TXEFA_EFAI_Pos      (0U)
4787 #define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
4788 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
4789 
4790 
4791 /*!<FDCAN config registers */
4792 /*****************  Bit definition for FDCAN_CKDIV register  *********************/
4793 #define FDCAN_CKDIV_PDIV_Pos      (0U)
4794 #define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
4795 #define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
4796 
4797 /******************************************************************************/
4798 /*                                                                            */
4799 /*                                    FLASH                                   */
4800 /*                                                                            */
4801 /******************************************************************************/
4802 /*******************  Bits definition for FLASH_ACR register  *****************/
4803 #define FLASH_ACR_LATENCY_Pos             (0U)
4804 #define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
4805 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
4806 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
4807 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
4808 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
4809 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
4810 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
4811 #define FLASH_ACR_LATENCY_5WS             (0x00000005U)
4812 #define FLASH_ACR_LATENCY_6WS             (0x00000006U)
4813 #define FLASH_ACR_LATENCY_7WS             (0x00000007U)
4814 #define FLASH_ACR_LATENCY_8WS             (0x00000008U)
4815 #define FLASH_ACR_LATENCY_9WS             (0x00000009U)
4816 #define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
4817 #define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
4818 #define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
4819 #define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
4820 #define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
4821 #define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
4822 #define FLASH_ACR_PRFTEN_Pos              (8U)
4823 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
4824 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
4825 #define FLASH_ACR_ICEN_Pos                (9U)
4826 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
4827 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
4828 #define FLASH_ACR_DCEN_Pos                (10U)
4829 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
4830 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
4831 #define FLASH_ACR_ICRST_Pos               (11U)
4832 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
4833 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
4834 #define FLASH_ACR_DCRST_Pos               (12U)
4835 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
4836 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
4837 #define FLASH_ACR_RUN_PD_Pos              (13U)
4838 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
4839 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
4840 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
4841 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
4842 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
4843 #define FLASH_ACR_DBG_SWEN_Pos            (18U)
4844 #define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
4845 #define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
4846 
4847 /*******************  Bits definition for FLASH_SR register  ******************/
4848 #define FLASH_SR_EOP_Pos                  (0U)
4849 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
4850 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
4851 #define FLASH_SR_OPERR_Pos                (1U)
4852 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
4853 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
4854 #define FLASH_SR_PROGERR_Pos              (3U)
4855 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
4856 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
4857 #define FLASH_SR_WRPERR_Pos               (4U)
4858 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
4859 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
4860 #define FLASH_SR_PGAERR_Pos               (5U)
4861 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
4862 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
4863 #define FLASH_SR_SIZERR_Pos               (6U)
4864 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
4865 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
4866 #define FLASH_SR_PGSERR_Pos               (7U)
4867 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
4868 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
4869 #define FLASH_SR_MISERR_Pos               (8U)
4870 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
4871 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
4872 #define FLASH_SR_FASTERR_Pos              (9U)
4873 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
4874 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
4875 #define FLASH_SR_RDERR_Pos                (14U)
4876 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
4877 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
4878 #define FLASH_SR_OPTVERR_Pos              (15U)
4879 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
4880 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
4881 #define FLASH_SR_BSY_Pos                  (16U)
4882 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
4883 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
4884 
4885 /*******************  Bits definition for FLASH_CR register  ******************/
4886 #define FLASH_CR_PG_Pos                   (0U)
4887 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
4888 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
4889 #define FLASH_CR_PER_Pos                  (1U)
4890 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
4891 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
4892 #define FLASH_CR_MER1_Pos                 (2U)
4893 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
4894 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
4895 #define FLASH_CR_PNB_Pos                  (3U)
4896 #define FLASH_CR_PNB_Msk                  (0x7FUL << FLASH_CR_PNB_Pos)         /*!< 0x000003F8 */
4897 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
4898 #define FLASH_CR_BKER_Pos                 (11U)
4899 #define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */
4900 #define FLASH_CR_BKER                     FLASH_CR_BKER_Msk
4901 #define FLASH_CR_MER2_Pos                 (15U)
4902 #define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */
4903 #define FLASH_CR_MER2                     FLASH_CR_MER2_Msk
4904 #define FLASH_CR_STRT_Pos                 (16U)
4905 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
4906 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
4907 #define FLASH_CR_OPTSTRT_Pos              (17U)
4908 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
4909 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
4910 #define FLASH_CR_FSTPG_Pos                (18U)
4911 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
4912 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
4913 #define FLASH_CR_EOPIE_Pos                (24U)
4914 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
4915 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
4916 #define FLASH_CR_ERRIE_Pos                (25U)
4917 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
4918 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
4919 #define FLASH_CR_RDERRIE_Pos              (26U)
4920 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
4921 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
4922 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
4923 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
4924 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
4925 #define FLASH_CR_SEC_PROT1_Pos            (28U)
4926 #define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
4927 #define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
4928 #define FLASH_CR_SEC_PROT2_Pos            (29U)
4929 #define FLASH_CR_SEC_PROT2_Msk            (0x1UL << FLASH_CR_SEC_PROT2_Pos)    /*!< 0x20000000 */
4930 #define FLASH_CR_SEC_PROT2                FLASH_CR_SEC_PROT2_Msk
4931 #define FLASH_CR_OPTLOCK_Pos              (30U)
4932 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
4933 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
4934 #define FLASH_CR_LOCK_Pos                 (31U)
4935 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
4936 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
4937 
4938 /*******************  Bits definition for FLASH_ECCR register  ***************/
4939 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
4940 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
4941 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
4942 #define FLASH_ECCR_BK_ECC_Pos             (21U)
4943 #define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00200000 */
4944 #define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk
4945 #define FLASH_ECCR_SYSF_ECC_Pos           (22U)
4946 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
4947 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
4948 #define FLASH_ECCR_ECCIE_Pos              (24U)
4949 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
4950 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
4951 #define FLASH_ECCR_ECCC2_Pos              (28U)
4952 #define FLASH_ECCR_ECCC2_Msk              (0x1UL << FLASH_ECCR_ECCC2_Pos)      /*!< 0x10000000 */
4953 #define FLASH_ECCR_ECCC2                  FLASH_ECCR_ECCC2_Msk
4954 #define FLASH_ECCR_ECCD2_Pos              (29U)
4955 #define FLASH_ECCR_ECCD2_Msk              (0x1UL << FLASH_ECCR_ECCD2_Pos)      /*!< 0x20000000 */
4956 #define FLASH_ECCR_ECCD2                  FLASH_ECCR_ECCD2_Msk
4957 #define FLASH_ECCR_ECCC_Pos               (30U)
4958 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
4959 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
4960 #define FLASH_ECCR_ECCD_Pos               (31U)
4961 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
4962 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
4963 
4964 /*******************  Bits definition for FLASH_OPTR register  ***************/
4965 #define FLASH_OPTR_RDP_Pos                (0U)
4966 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
4967 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
4968 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
4969 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
4970 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
4971 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
4972 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
4973 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
4974 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
4975 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
4976 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
4977 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
4978 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
4979 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
4980 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
4981 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
4982 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
4983 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
4984 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
4985 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
4986 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
4987 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
4988 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
4989 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
4990 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
4991 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
4992 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
4993 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
4994 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
4995 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
4996 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
4997 #define FLASH_OPTR_BFB2_Pos               (20U)
4998 #define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */
4999 #define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk
5000 #define FLASH_OPTR_DBANK_Pos              (22U)
5001 #define FLASH_OPTR_DBANK_Msk              (0x1UL << FLASH_OPTR_DBANK_Pos)      /*!< 0x00400000 */
5002 #define FLASH_OPTR_DBANK                  FLASH_OPTR_DBANK_Msk
5003 #define FLASH_OPTR_nBOOT1_Pos             (23U)
5004 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
5005 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
5006 #define FLASH_OPTR_SRAM_PE_Pos            (24U)
5007 #define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
5008 #define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
5009 #define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
5010 #define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
5011 #define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
5012 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
5013 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
5014 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
5015 #define FLASH_OPTR_nBOOT0_Pos             (27U)
5016 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
5017 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
5018 #define FLASH_OPTR_NRST_MODE_Pos          (28U)
5019 #define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
5020 #define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
5021 #define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
5022 #define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
5023 #define FLASH_OPTR_IRHEN_Pos              (30U)
5024 #define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
5025 #define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
5026 
5027 /******************  Bits definition for FLASH_PCROP1SR register  **********/
5028 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
5029 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
5030 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
5031 
5032 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
5033 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
5034 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
5035 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
5036 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
5037 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
5038 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
5039 
5040 /******************  Bits definition for FLASH_WRP1AR register  ***************/
5041 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
5042 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
5043 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
5044 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
5045 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
5046 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
5047 
5048 /******************  Bits definition for FLASH_WRPB1R register  ***************/
5049 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
5050 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
5051 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
5052 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
5053 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5054 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
5055 
5056 /******************  Bits definition for FLASH_PCROP2SR register  **********/
5057 #define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)
5058 #define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
5059 #define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk
5060 
5061 /******************  Bits definition for FLASH_PCROP2ER register  ***********/
5062 #define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)
5063 #define FLASH_PCROP2ER_PCROP2_END_Msk     (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
5064 #define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk
5065 
5066 /******************  Bits definition for FLASH_WRP2AR register  ***************/
5067 #define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)
5068 #define FLASH_WRP2AR_WRP2A_STRT_Msk       (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
5069 #define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk
5070 #define FLASH_WRP2AR_WRP2A_END_Pos        (16U)
5071 #define FLASH_WRP2AR_WRP2A_END_Msk        (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
5072 #define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk
5073 
5074 /******************  Bits definition for FLASH_WRP2BR register  ***************/
5075 #define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)
5076 #define FLASH_WRP2BR_WRP2B_STRT_Msk       (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
5077 #define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk
5078 #define FLASH_WRP2BR_WRP2B_END_Pos        (16U)
5079 #define FLASH_WRP2BR_WRP2B_END_Msk        (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
5080 #define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk
5081 
5082 /******************  Bits definition for FLASH_SEC1R register  **************/
5083 #define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
5084 #define FLASH_SEC1R_SEC_SIZE1_Msk         (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5085 #define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
5086 #define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
5087 #define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5088 #define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
5089 
5090 /******************  Bits definition for FLASH_SEC2R register  **************/
5091 #define FLASH_SEC2R_SEC_SIZE2_Pos         (0U)
5092 #define FLASH_SEC2R_SEC_SIZE2_Msk         (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
5093 #define FLASH_SEC2R_SEC_SIZE2             FLASH_SEC2R_SEC_SIZE2_Msk
5094 
5095 /******************************************************************************/
5096 /*                                                                            */
5097 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
5098 /*                                                                            */
5099 /******************************************************************************/
5100 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
5101 #define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
5102 #define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
5103 #define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
5104 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5105 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5106 #define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
5107 #define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
5108 #define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
5109 #define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
5110 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
5111 #define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
5112 #define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
5113 #define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
5114 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5115 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5116 #define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
5117 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
5118 #define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
5119 #define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
5120 #define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
5121 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
5122 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
5123 #define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
5124 #define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
5125 #define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
5126 #define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
5127 /******************  Bit definition for FMAC_PARAM register  ******************/
5128 #define FMAC_PARAM_P_Pos              (0U)
5129 #define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
5130 #define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
5131 #define FMAC_PARAM_Q_Pos              (8U)
5132 #define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
5133 #define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
5134 #define FMAC_PARAM_R_Pos              (16U)
5135 #define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
5136 #define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
5137 #define FMAC_PARAM_FUNC_Pos           (24U)
5138 #define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
5139 #define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
5140 #define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
5141 #define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
5142 #define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
5143 #define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
5144 #define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
5145 #define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
5146 #define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
5147 #define FMAC_PARAM_START_Pos          (31U)
5148 #define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
5149 #define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
5150 /********************  Bit definition for FMAC_CR register  *******************/
5151 #define FMAC_CR_RIEN_Pos              (0U)
5152 #define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
5153 #define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
5154 #define FMAC_CR_WIEN_Pos              (1U)
5155 #define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
5156 #define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
5157 #define FMAC_CR_OVFLIEN_Pos           (2U)
5158 #define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
5159 #define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
5160 #define FMAC_CR_UNFLIEN_Pos           (3U)
5161 #define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
5162 #define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
5163 #define FMAC_CR_SATIEN_Pos            (4U)
5164 #define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
5165 #define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
5166 #define FMAC_CR_DMAREN_Pos            (8U)
5167 #define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
5168 #define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
5169 #define FMAC_CR_DMAWEN_Pos            (9U)
5170 #define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
5171 #define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
5172 #define FMAC_CR_CLIPEN_Pos            (15U)
5173 #define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
5174 #define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
5175 #define FMAC_CR_RESET_Pos             (16U)
5176 #define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
5177 #define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
5178 /*******************  Bit definition for FMAC_SR register  ********************/
5179 #define FMAC_SR_YEMPTY_Pos            (0U)
5180 #define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
5181 #define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
5182 #define FMAC_SR_X1FULL_Pos            (1U)
5183 #define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
5184 #define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
5185 #define FMAC_SR_OVFL_Pos              (8U)
5186 #define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
5187 #define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
5188 #define FMAC_SR_UNFL_Pos              (9U)
5189 #define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
5190 #define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
5191 #define FMAC_SR_SAT_Pos               (10U)
5192 #define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
5193 #define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
5194 /******************  Bit definition for FMAC_WDATA register  ******************/
5195 #define FMAC_WDATA_WDATA_Pos          (0U)
5196 #define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
5197 #define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
5198 /******************  Bit definition for FMACX_RDATA register  *****************/
5199 #define FMAC_RDATA_RDATA_Pos          (0U)
5200 #define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
5201 #define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
5202 
5203 
5204 /******************************************************************************/
5205 /*                                                                            */
5206 /*                       General Purpose IOs (GPIO)                           */
5207 /*                                                                            */
5208 /******************************************************************************/
5209 /******************  Bits definition for GPIO_MODER register  *****************/
5210 #define GPIO_MODER_MODE0_Pos           (0U)
5211 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
5212 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
5213 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
5214 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
5215 #define GPIO_MODER_MODE1_Pos           (2U)
5216 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
5217 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
5218 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
5219 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
5220 #define GPIO_MODER_MODE2_Pos           (4U)
5221 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
5222 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
5223 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
5224 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
5225 #define GPIO_MODER_MODE3_Pos           (6U)
5226 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
5227 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
5228 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
5229 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
5230 #define GPIO_MODER_MODE4_Pos           (8U)
5231 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
5232 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
5233 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
5234 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
5235 #define GPIO_MODER_MODE5_Pos           (10U)
5236 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
5237 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
5238 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
5239 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
5240 #define GPIO_MODER_MODE6_Pos           (12U)
5241 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
5242 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
5243 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
5244 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
5245 #define GPIO_MODER_MODE7_Pos           (14U)
5246 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
5247 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
5248 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
5249 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
5250 #define GPIO_MODER_MODE8_Pos           (16U)
5251 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
5252 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
5253 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
5254 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
5255 #define GPIO_MODER_MODE9_Pos           (18U)
5256 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
5257 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
5258 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
5259 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
5260 #define GPIO_MODER_MODE10_Pos          (20U)
5261 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
5262 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
5263 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
5264 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
5265 #define GPIO_MODER_MODE11_Pos          (22U)
5266 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
5267 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
5268 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
5269 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
5270 #define GPIO_MODER_MODE12_Pos          (24U)
5271 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
5272 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
5273 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
5274 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
5275 #define GPIO_MODER_MODE13_Pos          (26U)
5276 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
5277 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
5278 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
5279 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
5280 #define GPIO_MODER_MODE14_Pos          (28U)
5281 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
5282 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
5283 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
5284 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
5285 #define GPIO_MODER_MODE15_Pos          (30U)
5286 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
5287 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
5288 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
5289 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
5290 
5291 /* Legacy defines */
5292 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
5293 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
5294 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
5295 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
5296 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
5297 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
5298 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
5299 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
5300 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
5301 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
5302 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
5303 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
5304 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
5305 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
5306 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
5307 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
5308 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
5309 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
5310 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
5311 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
5312 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
5313 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
5314 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
5315 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
5316 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
5317 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
5318 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
5319 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
5320 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
5321 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
5322 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
5323 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
5324 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
5325 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
5326 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
5327 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
5328 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
5329 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
5330 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
5331 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
5332 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
5333 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
5334 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
5335 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
5336 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
5337 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
5338 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
5339 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
5340 
5341 /******************  Bits definition for GPIO_OTYPER register  ****************/
5342 #define GPIO_OTYPER_OT0_Pos            (0U)
5343 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
5344 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
5345 #define GPIO_OTYPER_OT1_Pos            (1U)
5346 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
5347 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
5348 #define GPIO_OTYPER_OT2_Pos            (2U)
5349 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
5350 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
5351 #define GPIO_OTYPER_OT3_Pos            (3U)
5352 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
5353 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
5354 #define GPIO_OTYPER_OT4_Pos            (4U)
5355 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
5356 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
5357 #define GPIO_OTYPER_OT5_Pos            (5U)
5358 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
5359 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
5360 #define GPIO_OTYPER_OT6_Pos            (6U)
5361 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
5362 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
5363 #define GPIO_OTYPER_OT7_Pos            (7U)
5364 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
5365 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
5366 #define GPIO_OTYPER_OT8_Pos            (8U)
5367 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
5368 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
5369 #define GPIO_OTYPER_OT9_Pos            (9U)
5370 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
5371 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
5372 #define GPIO_OTYPER_OT10_Pos           (10U)
5373 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
5374 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
5375 #define GPIO_OTYPER_OT11_Pos           (11U)
5376 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
5377 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
5378 #define GPIO_OTYPER_OT12_Pos           (12U)
5379 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
5380 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
5381 #define GPIO_OTYPER_OT13_Pos           (13U)
5382 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
5383 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
5384 #define GPIO_OTYPER_OT14_Pos           (14U)
5385 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
5386 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
5387 #define GPIO_OTYPER_OT15_Pos           (15U)
5388 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
5389 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
5390 
5391 /* Legacy defines */
5392 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
5393 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
5394 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
5395 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
5396 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
5397 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
5398 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
5399 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
5400 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
5401 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
5402 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
5403 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
5404 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
5405 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
5406 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
5407 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
5408 
5409 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
5410 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
5411 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
5412 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
5413 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
5414 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
5415 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
5416 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
5417 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
5418 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
5419 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
5420 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
5421 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
5422 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
5423 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
5424 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
5425 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
5426 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
5427 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
5428 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
5429 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
5430 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
5431 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
5432 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
5433 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
5434 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
5435 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
5436 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
5437 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
5438 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
5439 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
5440 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
5441 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
5442 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
5443 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
5444 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
5445 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
5446 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
5447 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
5448 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
5449 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
5450 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
5451 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
5452 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
5453 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
5454 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
5455 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
5456 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
5457 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
5458 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
5459 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
5460 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
5461 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
5462 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
5463 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
5464 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
5465 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
5466 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
5467 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
5468 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
5469 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
5470 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
5471 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
5472 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
5473 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
5474 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
5475 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
5476 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
5477 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
5478 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
5479 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
5480 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
5481 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
5482 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
5483 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
5484 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
5485 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
5486 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
5487 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
5488 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
5489 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
5490 
5491 /* Legacy defines */
5492 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
5493 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
5494 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
5495 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
5496 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
5497 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
5498 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
5499 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
5500 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
5501 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
5502 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
5503 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
5504 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
5505 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
5506 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
5507 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
5508 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
5509 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
5510 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
5511 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
5512 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
5513 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
5514 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
5515 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
5516 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
5517 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
5518 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
5519 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
5520 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
5521 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
5522 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
5523 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
5524 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
5525 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
5526 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
5527 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
5528 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
5529 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
5530 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
5531 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
5532 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
5533 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
5534 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
5535 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
5536 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
5537 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
5538 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
5539 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
5540 
5541 /******************  Bits definition for GPIO_PUPDR register  *****************/
5542 #define GPIO_PUPDR_PUPD0_Pos           (0U)
5543 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
5544 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
5545 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
5546 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
5547 #define GPIO_PUPDR_PUPD1_Pos           (2U)
5548 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
5549 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
5550 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
5551 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
5552 #define GPIO_PUPDR_PUPD2_Pos           (4U)
5553 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
5554 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
5555 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
5556 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
5557 #define GPIO_PUPDR_PUPD3_Pos           (6U)
5558 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
5559 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
5560 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
5561 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
5562 #define GPIO_PUPDR_PUPD4_Pos           (8U)
5563 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
5564 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
5565 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
5566 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
5567 #define GPIO_PUPDR_PUPD5_Pos           (10U)
5568 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
5569 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
5570 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
5571 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
5572 #define GPIO_PUPDR_PUPD6_Pos           (12U)
5573 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
5574 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
5575 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
5576 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
5577 #define GPIO_PUPDR_PUPD7_Pos           (14U)
5578 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
5579 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
5580 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
5581 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
5582 #define GPIO_PUPDR_PUPD8_Pos           (16U)
5583 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
5584 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
5585 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
5586 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
5587 #define GPIO_PUPDR_PUPD9_Pos           (18U)
5588 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
5589 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
5590 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
5591 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
5592 #define GPIO_PUPDR_PUPD10_Pos          (20U)
5593 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
5594 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
5595 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
5596 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
5597 #define GPIO_PUPDR_PUPD11_Pos          (22U)
5598 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
5599 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
5600 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
5601 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
5602 #define GPIO_PUPDR_PUPD12_Pos          (24U)
5603 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
5604 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
5605 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
5606 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
5607 #define GPIO_PUPDR_PUPD13_Pos          (26U)
5608 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
5609 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
5610 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
5611 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
5612 #define GPIO_PUPDR_PUPD14_Pos          (28U)
5613 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
5614 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
5615 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
5616 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
5617 #define GPIO_PUPDR_PUPD15_Pos          (30U)
5618 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
5619 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
5620 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
5621 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
5622 
5623 /* Legacy defines */
5624 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
5625 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
5626 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
5627 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
5628 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
5629 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
5630 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
5631 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
5632 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
5633 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
5634 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
5635 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
5636 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
5637 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
5638 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
5639 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
5640 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
5641 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
5642 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
5643 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
5644 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
5645 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
5646 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
5647 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
5648 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
5649 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
5650 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
5651 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
5652 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
5653 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
5654 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
5655 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
5656 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
5657 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
5658 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
5659 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
5660 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
5661 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
5662 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
5663 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
5664 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
5665 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
5666 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
5667 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
5668 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
5669 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
5670 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
5671 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
5672 
5673 /******************  Bits definition for GPIO_IDR register  *******************/
5674 #define GPIO_IDR_ID0_Pos               (0U)
5675 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
5676 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
5677 #define GPIO_IDR_ID1_Pos               (1U)
5678 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
5679 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
5680 #define GPIO_IDR_ID2_Pos               (2U)
5681 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
5682 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
5683 #define GPIO_IDR_ID3_Pos               (3U)
5684 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
5685 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
5686 #define GPIO_IDR_ID4_Pos               (4U)
5687 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
5688 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
5689 #define GPIO_IDR_ID5_Pos               (5U)
5690 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
5691 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
5692 #define GPIO_IDR_ID6_Pos               (6U)
5693 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
5694 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
5695 #define GPIO_IDR_ID7_Pos               (7U)
5696 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
5697 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
5698 #define GPIO_IDR_ID8_Pos               (8U)
5699 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
5700 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
5701 #define GPIO_IDR_ID9_Pos               (9U)
5702 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
5703 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
5704 #define GPIO_IDR_ID10_Pos              (10U)
5705 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
5706 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
5707 #define GPIO_IDR_ID11_Pos              (11U)
5708 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
5709 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
5710 #define GPIO_IDR_ID12_Pos              (12U)
5711 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
5712 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
5713 #define GPIO_IDR_ID13_Pos              (13U)
5714 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
5715 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
5716 #define GPIO_IDR_ID14_Pos              (14U)
5717 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
5718 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
5719 #define GPIO_IDR_ID15_Pos              (15U)
5720 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
5721 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
5722 
5723 /* Legacy defines */
5724 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
5725 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
5726 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
5727 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
5728 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
5729 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
5730 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
5731 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
5732 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
5733 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
5734 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
5735 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
5736 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
5737 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
5738 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
5739 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
5740 
5741 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5742 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
5743 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
5744 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
5745 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
5746 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
5747 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
5748 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
5749 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
5750 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
5751 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
5752 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
5753 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
5754 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
5755 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
5756 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
5757 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
5758 
5759 /******************  Bits definition for GPIO_ODR register  *******************/
5760 #define GPIO_ODR_OD0_Pos               (0U)
5761 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
5762 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
5763 #define GPIO_ODR_OD1_Pos               (1U)
5764 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
5765 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
5766 #define GPIO_ODR_OD2_Pos               (2U)
5767 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
5768 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
5769 #define GPIO_ODR_OD3_Pos               (3U)
5770 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
5771 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
5772 #define GPIO_ODR_OD4_Pos               (4U)
5773 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
5774 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
5775 #define GPIO_ODR_OD5_Pos               (5U)
5776 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
5777 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
5778 #define GPIO_ODR_OD6_Pos               (6U)
5779 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
5780 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
5781 #define GPIO_ODR_OD7_Pos               (7U)
5782 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
5783 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
5784 #define GPIO_ODR_OD8_Pos               (8U)
5785 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
5786 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
5787 #define GPIO_ODR_OD9_Pos               (9U)
5788 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
5789 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
5790 #define GPIO_ODR_OD10_Pos              (10U)
5791 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
5792 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
5793 #define GPIO_ODR_OD11_Pos              (11U)
5794 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
5795 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
5796 #define GPIO_ODR_OD12_Pos              (12U)
5797 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
5798 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
5799 #define GPIO_ODR_OD13_Pos              (13U)
5800 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
5801 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
5802 #define GPIO_ODR_OD14_Pos              (14U)
5803 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
5804 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
5805 #define GPIO_ODR_OD15_Pos              (15U)
5806 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
5807 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
5808 
5809 /* Legacy defines */
5810 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
5811 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
5812 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
5813 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
5814 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
5815 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
5816 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
5817 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
5818 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
5819 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
5820 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
5821 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
5822 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
5823 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
5824 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
5825 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
5826 
5827 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5828 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
5829 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
5830 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
5831 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
5832 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
5833 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
5834 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
5835 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
5836 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
5837 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
5838 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
5839 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
5840 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
5841 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
5842 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
5843 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
5844 
5845 /******************  Bits definition for GPIO_BSRR register  ******************/
5846 #define GPIO_BSRR_BS0_Pos              (0U)
5847 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
5848 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
5849 #define GPIO_BSRR_BS1_Pos              (1U)
5850 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
5851 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
5852 #define GPIO_BSRR_BS2_Pos              (2U)
5853 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
5854 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
5855 #define GPIO_BSRR_BS3_Pos              (3U)
5856 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
5857 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
5858 #define GPIO_BSRR_BS4_Pos              (4U)
5859 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
5860 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
5861 #define GPIO_BSRR_BS5_Pos              (5U)
5862 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
5863 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
5864 #define GPIO_BSRR_BS6_Pos              (6U)
5865 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
5866 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
5867 #define GPIO_BSRR_BS7_Pos              (7U)
5868 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
5869 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
5870 #define GPIO_BSRR_BS8_Pos              (8U)
5871 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
5872 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
5873 #define GPIO_BSRR_BS9_Pos              (9U)
5874 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
5875 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
5876 #define GPIO_BSRR_BS10_Pos             (10U)
5877 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
5878 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
5879 #define GPIO_BSRR_BS11_Pos             (11U)
5880 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
5881 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
5882 #define GPIO_BSRR_BS12_Pos             (12U)
5883 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
5884 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
5885 #define GPIO_BSRR_BS13_Pos             (13U)
5886 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
5887 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
5888 #define GPIO_BSRR_BS14_Pos             (14U)
5889 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
5890 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
5891 #define GPIO_BSRR_BS15_Pos             (15U)
5892 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
5893 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
5894 #define GPIO_BSRR_BR0_Pos              (16U)
5895 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
5896 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
5897 #define GPIO_BSRR_BR1_Pos              (17U)
5898 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
5899 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
5900 #define GPIO_BSRR_BR2_Pos              (18U)
5901 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
5902 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
5903 #define GPIO_BSRR_BR3_Pos              (19U)
5904 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
5905 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
5906 #define GPIO_BSRR_BR4_Pos              (20U)
5907 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
5908 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
5909 #define GPIO_BSRR_BR5_Pos              (21U)
5910 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
5911 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
5912 #define GPIO_BSRR_BR6_Pos              (22U)
5913 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
5914 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
5915 #define GPIO_BSRR_BR7_Pos              (23U)
5916 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
5917 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
5918 #define GPIO_BSRR_BR8_Pos              (24U)
5919 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
5920 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
5921 #define GPIO_BSRR_BR9_Pos              (25U)
5922 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
5923 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
5924 #define GPIO_BSRR_BR10_Pos             (26U)
5925 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
5926 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
5927 #define GPIO_BSRR_BR11_Pos             (27U)
5928 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
5929 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
5930 #define GPIO_BSRR_BR12_Pos             (28U)
5931 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
5932 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
5933 #define GPIO_BSRR_BR13_Pos             (29U)
5934 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
5935 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
5936 #define GPIO_BSRR_BR14_Pos             (30U)
5937 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
5938 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
5939 #define GPIO_BSRR_BR15_Pos             (31U)
5940 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
5941 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
5942 
5943 /* Legacy defines */
5944 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
5945 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
5946 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
5947 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
5948 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
5949 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
5950 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
5951 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
5952 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
5953 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
5954 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
5955 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
5956 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
5957 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
5958 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
5959 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
5960 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
5961 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
5962 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
5963 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
5964 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
5965 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
5966 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
5967 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
5968 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
5969 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
5970 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
5971 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
5972 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
5973 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
5974 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
5975 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
5976 
5977 /****************** Bit definition for GPIO_LCKR register *********************/
5978 #define GPIO_LCKR_LCK0_Pos             (0U)
5979 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
5980 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
5981 #define GPIO_LCKR_LCK1_Pos             (1U)
5982 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
5983 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
5984 #define GPIO_LCKR_LCK2_Pos             (2U)
5985 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
5986 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
5987 #define GPIO_LCKR_LCK3_Pos             (3U)
5988 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
5989 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
5990 #define GPIO_LCKR_LCK4_Pos             (4U)
5991 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
5992 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
5993 #define GPIO_LCKR_LCK5_Pos             (5U)
5994 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
5995 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
5996 #define GPIO_LCKR_LCK6_Pos             (6U)
5997 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
5998 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
5999 #define GPIO_LCKR_LCK7_Pos             (7U)
6000 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6001 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
6002 #define GPIO_LCKR_LCK8_Pos             (8U)
6003 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6004 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
6005 #define GPIO_LCKR_LCK9_Pos             (9U)
6006 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6007 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
6008 #define GPIO_LCKR_LCK10_Pos            (10U)
6009 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6010 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
6011 #define GPIO_LCKR_LCK11_Pos            (11U)
6012 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6013 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
6014 #define GPIO_LCKR_LCK12_Pos            (12U)
6015 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6016 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
6017 #define GPIO_LCKR_LCK13_Pos            (13U)
6018 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6019 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
6020 #define GPIO_LCKR_LCK14_Pos            (14U)
6021 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6022 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
6023 #define GPIO_LCKR_LCK15_Pos            (15U)
6024 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6025 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
6026 #define GPIO_LCKR_LCKK_Pos             (16U)
6027 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6028 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
6029 
6030 /****************** Bit definition for GPIO_AFRL register *********************/
6031 #define GPIO_AFRL_AFSEL0_Pos           (0U)
6032 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6033 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
6034 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6035 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6036 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6037 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6038 #define GPIO_AFRL_AFSEL1_Pos           (4U)
6039 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6040 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
6041 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6042 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6043 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6044 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6045 #define GPIO_AFRL_AFSEL2_Pos           (8U)
6046 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6047 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
6048 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6049 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6050 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6051 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6052 #define GPIO_AFRL_AFSEL3_Pos           (12U)
6053 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6054 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
6055 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6056 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6057 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6058 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6059 #define GPIO_AFRL_AFSEL4_Pos           (16U)
6060 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6061 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
6062 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6063 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6064 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6065 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6066 #define GPIO_AFRL_AFSEL5_Pos           (20U)
6067 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6068 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
6069 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6070 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6071 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6072 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6073 #define GPIO_AFRL_AFSEL6_Pos           (24U)
6074 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6075 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
6076 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6077 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6078 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6079 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6080 #define GPIO_AFRL_AFSEL7_Pos           (28U)
6081 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6082 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
6083 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6084 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6085 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6086 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6087 
6088 /* Legacy defines */
6089 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
6090 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
6091 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
6092 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
6093 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
6094 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
6095 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
6096 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
6097 
6098 /****************** Bit definition for GPIO_AFRH register *********************/
6099 #define GPIO_AFRH_AFSEL8_Pos           (0U)
6100 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6101 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
6102 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6103 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6104 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6105 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6106 #define GPIO_AFRH_AFSEL9_Pos           (4U)
6107 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6108 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
6109 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6110 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6111 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6112 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6113 #define GPIO_AFRH_AFSEL10_Pos          (8U)
6114 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6115 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
6116 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6117 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6118 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6119 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6120 #define GPIO_AFRH_AFSEL11_Pos          (12U)
6121 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6122 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
6123 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6124 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6125 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6126 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6127 #define GPIO_AFRH_AFSEL12_Pos          (16U)
6128 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6129 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
6130 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6131 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6132 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6133 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6134 #define GPIO_AFRH_AFSEL13_Pos          (20U)
6135 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6136 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
6137 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6138 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6139 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6140 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6141 #define GPIO_AFRH_AFSEL14_Pos          (24U)
6142 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6143 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
6144 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6145 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6146 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6147 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6148 #define GPIO_AFRH_AFSEL15_Pos          (28U)
6149 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6150 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
6151 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6152 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6153 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6154 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6155 
6156 /* Legacy defines */
6157 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
6158 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
6159 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
6160 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
6161 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
6162 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
6163 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
6164 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
6165 
6166 /******************  Bits definition for GPIO_BRR register  ******************/
6167 #define GPIO_BRR_BR0_Pos               (0U)
6168 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6169 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
6170 #define GPIO_BRR_BR1_Pos               (1U)
6171 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6172 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
6173 #define GPIO_BRR_BR2_Pos               (2U)
6174 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6175 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
6176 #define GPIO_BRR_BR3_Pos               (3U)
6177 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6178 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
6179 #define GPIO_BRR_BR4_Pos               (4U)
6180 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6181 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
6182 #define GPIO_BRR_BR5_Pos               (5U)
6183 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6184 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
6185 #define GPIO_BRR_BR6_Pos               (6U)
6186 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6187 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
6188 #define GPIO_BRR_BR7_Pos               (7U)
6189 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6190 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
6191 #define GPIO_BRR_BR8_Pos               (8U)
6192 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6193 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
6194 #define GPIO_BRR_BR9_Pos               (9U)
6195 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6196 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
6197 #define GPIO_BRR_BR10_Pos              (10U)
6198 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6199 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
6200 #define GPIO_BRR_BR11_Pos              (11U)
6201 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6202 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
6203 #define GPIO_BRR_BR12_Pos              (12U)
6204 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6205 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
6206 #define GPIO_BRR_BR13_Pos              (13U)
6207 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6208 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
6209 #define GPIO_BRR_BR14_Pos              (14U)
6210 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6211 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
6212 #define GPIO_BRR_BR15_Pos              (15U)
6213 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6214 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
6215 
6216 /* Legacy defines */
6217 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
6218 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
6219 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
6220 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
6221 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
6222 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
6223 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
6224 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
6225 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
6226 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
6227 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
6228 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
6229 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
6230 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
6231 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
6232 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
6233 
6234 
6235 /******************************************************************************/
6236 /*                                                                            */
6237 /*                      Inter-integrated Circuit Interface (I2C)              */
6238 /*                                                                            */
6239 /******************************************************************************/
6240 /*******************  Bit definition for I2C_CR1 register  *******************/
6241 #define I2C_CR1_PE_Pos               (0U)
6242 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
6243 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
6244 #define I2C_CR1_TXIE_Pos             (1U)
6245 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
6246 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
6247 #define I2C_CR1_RXIE_Pos             (2U)
6248 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
6249 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
6250 #define I2C_CR1_ADDRIE_Pos           (3U)
6251 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
6252 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
6253 #define I2C_CR1_NACKIE_Pos           (4U)
6254 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
6255 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
6256 #define I2C_CR1_STOPIE_Pos           (5U)
6257 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
6258 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
6259 #define I2C_CR1_TCIE_Pos             (6U)
6260 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
6261 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
6262 #define I2C_CR1_ERRIE_Pos            (7U)
6263 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
6264 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
6265 #define I2C_CR1_DNF_Pos              (8U)
6266 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
6267 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
6268 #define I2C_CR1_ANFOFF_Pos           (12U)
6269 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
6270 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
6271 #define I2C_CR1_SWRST_Pos            (13U)
6272 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
6273 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
6274 #define I2C_CR1_TXDMAEN_Pos          (14U)
6275 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
6276 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
6277 #define I2C_CR1_RXDMAEN_Pos          (15U)
6278 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
6279 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
6280 #define I2C_CR1_SBC_Pos              (16U)
6281 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
6282 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
6283 #define I2C_CR1_NOSTRETCH_Pos        (17U)
6284 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
6285 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
6286 #define I2C_CR1_WUPEN_Pos            (18U)
6287 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
6288 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
6289 #define I2C_CR1_GCEN_Pos             (19U)
6290 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
6291 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
6292 #define I2C_CR1_SMBHEN_Pos           (20U)
6293 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
6294 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
6295 #define I2C_CR1_SMBDEN_Pos           (21U)
6296 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
6297 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
6298 #define I2C_CR1_ALERTEN_Pos          (22U)
6299 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
6300 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
6301 #define I2C_CR1_PECEN_Pos            (23U)
6302 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
6303 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
6304 
6305 /******************  Bit definition for I2C_CR2 register  ********************/
6306 #define I2C_CR2_SADD_Pos             (0U)
6307 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
6308 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
6309 #define I2C_CR2_RD_WRN_Pos           (10U)
6310 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
6311 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
6312 #define I2C_CR2_ADD10_Pos            (11U)
6313 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
6314 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
6315 #define I2C_CR2_HEAD10R_Pos          (12U)
6316 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
6317 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
6318 #define I2C_CR2_START_Pos            (13U)
6319 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
6320 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
6321 #define I2C_CR2_STOP_Pos             (14U)
6322 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
6323 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
6324 #define I2C_CR2_NACK_Pos             (15U)
6325 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
6326 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
6327 #define I2C_CR2_NBYTES_Pos           (16U)
6328 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
6329 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
6330 #define I2C_CR2_RELOAD_Pos           (24U)
6331 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
6332 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
6333 #define I2C_CR2_AUTOEND_Pos          (25U)
6334 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
6335 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
6336 #define I2C_CR2_PECBYTE_Pos          (26U)
6337 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
6338 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
6339 
6340 /*******************  Bit definition for I2C_OAR1 register  ******************/
6341 #define I2C_OAR1_OA1_Pos             (0U)
6342 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
6343 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
6344 #define I2C_OAR1_OA1MODE_Pos         (10U)
6345 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
6346 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
6347 #define I2C_OAR1_OA1EN_Pos           (15U)
6348 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
6349 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
6350 
6351 /*******************  Bit definition for I2C_OAR2 register  ******************/
6352 #define I2C_OAR2_OA2_Pos             (1U)
6353 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
6354 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
6355 #define I2C_OAR2_OA2MSK_Pos          (8U)
6356 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
6357 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
6358 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
6359 #define I2C_OAR2_OA2MASK01_Pos       (8U)
6360 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
6361 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
6362 #define I2C_OAR2_OA2MASK02_Pos       (9U)
6363 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
6364 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
6365 #define I2C_OAR2_OA2MASK03_Pos       (8U)
6366 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
6367 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
6368 #define I2C_OAR2_OA2MASK04_Pos       (10U)
6369 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
6370 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
6371 #define I2C_OAR2_OA2MASK05_Pos       (8U)
6372 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
6373 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
6374 #define I2C_OAR2_OA2MASK06_Pos       (9U)
6375 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
6376 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
6377 #define I2C_OAR2_OA2MASK07_Pos       (8U)
6378 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
6379 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
6380 #define I2C_OAR2_OA2EN_Pos           (15U)
6381 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
6382 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
6383 
6384 /*******************  Bit definition for I2C_TIMINGR register *******************/
6385 #define I2C_TIMINGR_SCLL_Pos         (0U)
6386 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
6387 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
6388 #define I2C_TIMINGR_SCLH_Pos         (8U)
6389 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
6390 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
6391 #define I2C_TIMINGR_SDADEL_Pos       (16U)
6392 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
6393 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
6394 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
6395 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
6396 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
6397 #define I2C_TIMINGR_PRESC_Pos        (28U)
6398 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
6399 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
6400 
6401 /******************* Bit definition for I2C_TIMEOUTR register *******************/
6402 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
6403 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
6404 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
6405 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
6406 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
6407 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
6408 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
6409 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
6410 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
6411 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
6412 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
6413 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
6414 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
6415 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
6416 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
6417 
6418 /******************  Bit definition for I2C_ISR register  *********************/
6419 #define I2C_ISR_TXE_Pos              (0U)
6420 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
6421 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
6422 #define I2C_ISR_TXIS_Pos             (1U)
6423 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
6424 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
6425 #define I2C_ISR_RXNE_Pos             (2U)
6426 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
6427 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
6428 #define I2C_ISR_ADDR_Pos             (3U)
6429 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
6430 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
6431 #define I2C_ISR_NACKF_Pos            (4U)
6432 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
6433 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
6434 #define I2C_ISR_STOPF_Pos            (5U)
6435 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
6436 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
6437 #define I2C_ISR_TC_Pos               (6U)
6438 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
6439 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
6440 #define I2C_ISR_TCR_Pos              (7U)
6441 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
6442 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
6443 #define I2C_ISR_BERR_Pos             (8U)
6444 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
6445 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
6446 #define I2C_ISR_ARLO_Pos             (9U)
6447 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
6448 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
6449 #define I2C_ISR_OVR_Pos              (10U)
6450 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
6451 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
6452 #define I2C_ISR_PECERR_Pos           (11U)
6453 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
6454 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
6455 #define I2C_ISR_TIMEOUT_Pos          (12U)
6456 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
6457 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
6458 #define I2C_ISR_ALERT_Pos            (13U)
6459 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
6460 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
6461 #define I2C_ISR_BUSY_Pos             (15U)
6462 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
6463 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
6464 #define I2C_ISR_DIR_Pos              (16U)
6465 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
6466 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
6467 #define I2C_ISR_ADDCODE_Pos          (17U)
6468 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
6469 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
6470 
6471 /******************  Bit definition for I2C_ICR register  *********************/
6472 #define I2C_ICR_ADDRCF_Pos           (3U)
6473 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
6474 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
6475 #define I2C_ICR_NACKCF_Pos           (4U)
6476 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
6477 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
6478 #define I2C_ICR_STOPCF_Pos           (5U)
6479 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
6480 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
6481 #define I2C_ICR_BERRCF_Pos           (8U)
6482 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
6483 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
6484 #define I2C_ICR_ARLOCF_Pos           (9U)
6485 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
6486 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
6487 #define I2C_ICR_OVRCF_Pos            (10U)
6488 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
6489 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
6490 #define I2C_ICR_PECCF_Pos            (11U)
6491 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
6492 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
6493 #define I2C_ICR_TIMOUTCF_Pos         (12U)
6494 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
6495 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
6496 #define I2C_ICR_ALERTCF_Pos          (13U)
6497 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
6498 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
6499 
6500 /******************  Bit definition for I2C_PECR register  *********************/
6501 #define I2C_PECR_PEC_Pos             (0U)
6502 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
6503 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
6504 
6505 /******************  Bit definition for I2C_RXDR register  *********************/
6506 #define I2C_RXDR_RXDATA_Pos          (0U)
6507 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
6508 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
6509 
6510 /******************  Bit definition for I2C_TXDR register  *********************/
6511 #define I2C_TXDR_TXDATA_Pos          (0U)
6512 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
6513 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
6514 
6515 /******************************************************************************/
6516 /*                                                                            */
6517 /*                           Independent WATCHDOG                             */
6518 /*                                                                            */
6519 /******************************************************************************/
6520 /*******************  Bit definition for IWDG_KR register  ********************/
6521 #define IWDG_KR_KEY_Pos      (0U)
6522 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
6523 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
6524 
6525 /*******************  Bit definition for IWDG_PR register  ********************/
6526 #define IWDG_PR_PR_Pos       (0U)
6527 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
6528 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
6529 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
6530 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
6531 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
6532 
6533 /*******************  Bit definition for IWDG_RLR register  *******************/
6534 #define IWDG_RLR_RL_Pos      (0U)
6535 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
6536 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
6537 
6538 /*******************  Bit definition for IWDG_SR register  ********************/
6539 #define IWDG_SR_PVU_Pos      (0U)
6540 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
6541 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
6542 #define IWDG_SR_RVU_Pos      (1U)
6543 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
6544 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
6545 #define IWDG_SR_WVU_Pos      (2U)
6546 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
6547 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
6548 
6549 /*******************  Bit definition for IWDG_KR register  ********************/
6550 #define IWDG_WINR_WIN_Pos    (0U)
6551 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
6552 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
6553 
6554 /******************************************************************************/
6555 /*                                                                            */
6556 /*                         Operational Amplifier (OPAMP)                      */
6557 /*                                                                            */
6558 /******************************************************************************/
6559 /*********************  Bit definition for OPAMPx_CSR register  ***************/
6560 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
6561 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)         /*!< 0x00000001 */
6562 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
6563 #define OPAMP_CSR_FORCEVP_Pos        (1U)
6564 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)          /*!< 0x00000002 */
6565 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
6566 #define OPAMP_CSR_VPSEL_Pos          (2U)
6567 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x0000000C */
6568 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
6569 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000004 */
6570 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000008 */
6571 #define OPAMP_CSR_USERTRIM_Pos       (4U)
6572 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00000010 */
6573 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
6574 #define OPAMP_CSR_VMSEL_Pos          (5U)
6575 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000060 */
6576 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
6577 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000020 */
6578 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000040 */
6579 #define OPAMP_CSR_HIGHSPEEDEN_Pos    (7U)
6580 #define OPAMP_CSR_HIGHSPEEDEN_Msk    (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)      /*!< 0x00000080 */
6581 #define OPAMP_CSR_HIGHSPEEDEN        OPAMP_CSR_HIGHSPEEDEN_Msk                 /*!< High speed mode enable */
6582 #define OPAMP_CSR_OPAMPINTEN_Pos     (8U)
6583 #define OPAMP_CSR_OPAMPINTEN_Msk     (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)       /*!< 0x00000100 */
6584 #define OPAMP_CSR_OPAMPINTEN         OPAMP_CSR_OPAMPINTEN_Msk                  /*!< Internal output enable */
6585 #define OPAMP_CSR_CALON_Pos          (11U)
6586 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00000800 */
6587 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
6588 #define OPAMP_CSR_CALSEL_Pos         (12U)
6589 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00003000 */
6590 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
6591 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00001000 */
6592 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
6593 #define OPAMP_CSR_PGGAIN_Pos         (14U)
6594 #define OPAMP_CSR_PGGAIN_Msk         (0x1FUL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x0007C000 */
6595 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
6596 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00004000 */
6597 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00008000 */
6598 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00010000 */
6599 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00020000 */
6600 #define OPAMP_CSR_PGGAIN_4           (0x10UL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x00040000 */
6601 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
6602 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)     /*!< 0x00F80000 */
6603 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
6604 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
6605 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)     /*!< 0x1F000000 */
6606 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
6607 #define OPAMP_CSR_OUTCAL_Pos         (30U)
6608 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)           /*!< 0x40000000 */
6609 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP output status flag */
6610 #define OPAMP_CSR_LOCK_Pos           (31U)
6611 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
6612 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP control/status register lock */
6613 
6614 /*********************  Bit definition for OPAMPx_TCMR register  ***************/
6615 
6616 #define OPAMP_TCMR_VMSSEL_Pos        (0U)
6617 #define OPAMP_TCMR_VMSSEL_Msk        (0x1UL << OPAMP_TCMR_VMSSEL_Pos)          /*!< 0x00000001 */
6618 #define OPAMP_TCMR_VMSSEL            OPAMP_TCMR_VMSSEL_Msk                     /*!< Secondary inverting input selection */
6619 #define OPAMP_TCMR_VPSSEL_Pos        (1U)
6620 #define OPAMP_TCMR_VPSSEL_Msk        (0x3UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000006 */
6621 #define OPAMP_TCMR_VPSSEL            OPAMP_TCMR_VPSSEL_Msk                     /*!< Secondary non inverting input selection */
6622 #define OPAMP_TCMR_VPSSEL_0          (0x1UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000002 */
6623 #define OPAMP_TCMR_VPSSEL_1          (0x2UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000004 */
6624 #define OPAMP_TCMR_T1CMEN_Pos        (3U)
6625 #define OPAMP_TCMR_T1CMEN_Msk        (0x1UL << OPAMP_TCMR_T1CMEN_Pos)          /*!< 0x00000008 */
6626 #define OPAMP_TCMR_T1CMEN            OPAMP_TCMR_T1CMEN_Msk                     /*!< Timer 1 controlled mux mode enable */
6627 #define OPAMP_TCMR_T8CMEN_Pos        (4U)
6628 #define OPAMP_TCMR_T8CMEN_Msk        (0x1UL << OPAMP_TCMR_T8CMEN_Pos)          /*!< 0x00000010 */
6629 #define OPAMP_TCMR_T8CMEN            OPAMP_TCMR_T8CMEN_Msk                     /*!< Timer 8 controlled mux mode enable */
6630 #define OPAMP_TCMR_T20CMEN_Pos       (5U)
6631 #define OPAMP_TCMR_T20CMEN_Msk       (0x1UL << OPAMP_TCMR_T20CMEN_Pos)         /*!< 0x00000020 */
6632 #define OPAMP_TCMR_T20CMEN           OPAMP_TCMR_T20CMEN_Msk                    /*!< Timer 20 controlled mux mode enable */
6633 #define OPAMP_TCMR_LOCK_Pos          (31U)
6634 #define OPAMP_TCMR_LOCK_Msk          (0x1UL << OPAMP_TCMR_LOCK_Pos)            /*!< 0x80000000 */
6635 #define OPAMP_TCMR_LOCK              OPAMP_TCMR_LOCK_Msk                       /*!< OPAMP SW control register lock */
6636 
6637 
6638 /******************************************************************************/
6639 /*                                                                            */
6640 /*                             Power Control                                  */
6641 /*                                                                            */
6642 /******************************************************************************/
6643 
6644 /********************  Bit definition for PWR_CR1 register  ********************/
6645 
6646 #define PWR_CR1_LPR_Pos              (14U)
6647 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
6648 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
6649 #define PWR_CR1_VOS_Pos              (9U)
6650 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
6651 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
6652 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
6653 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
6654 #define PWR_CR1_DBP_Pos              (8U)
6655 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
6656 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
6657 #define PWR_CR1_LPMS_Pos             (0U)
6658 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
6659 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
6660 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
6661 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
6662 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
6663 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
6664 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
6665 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
6666 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
6667 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
6668 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
6669 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
6670 
6671 
6672 /********************  Bit definition for PWR_CR2 register  ********************/
6673 
6674 /*!< PVME  Peripheral Voltage Monitor Enable */
6675 #define PWR_CR2_PVME_Pos             (4U)
6676 #define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
6677 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
6678 #define PWR_CR2_PVME4_Pos            (7U)
6679 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
6680 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
6681 #define PWR_CR2_PVME3_Pos            (6U)
6682 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
6683 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
6684 #define PWR_CR2_PVME2_Pos            (5U)
6685 #define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
6686 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
6687 #define PWR_CR2_PVME1_Pos            (4U)
6688 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
6689 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
6690 
6691 /*!< PVD level configuration */
6692 #define PWR_CR2_PLS_Pos              (1U)
6693 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
6694 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
6695 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
6696 #define PWR_CR2_PLS_LEV1_Pos         (1U)
6697 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
6698 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
6699 #define PWR_CR2_PLS_LEV2_Pos         (2U)
6700 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
6701 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
6702 #define PWR_CR2_PLS_LEV3_Pos         (1U)
6703 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
6704 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
6705 #define PWR_CR2_PLS_LEV4_Pos         (3U)
6706 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
6707 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
6708 #define PWR_CR2_PLS_LEV5_Pos         (1U)
6709 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
6710 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
6711 #define PWR_CR2_PLS_LEV6_Pos         (2U)
6712 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
6713 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
6714 #define PWR_CR2_PLS_LEV7_Pos         (1U)
6715 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
6716 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
6717 #define PWR_CR2_PVDE_Pos             (0U)
6718 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
6719 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
6720 
6721 /********************  Bit definition for PWR_CR3 register  ********************/
6722 #define PWR_CR3_EIWF_Pos             (15U)
6723 #define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
6724 #define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
6725 #define PWR_CR3_UCPD_DBDIS_Pos       (14U)
6726 #define PWR_CR3_UCPD_DBDIS_Msk       (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)         /*!< 0x00004000 */
6727 #define PWR_CR3_UCPD_DBDIS           PWR_CR3_UCPD_DBDIS_Msk                    /*!< USB Type-C and Power Delivery Dead Battery disable. */
6728 #define PWR_CR3_UCPD_STDBY_Pos       (13U)
6729 #define PWR_CR3_UCPD_STDBY_Msk       (0x1UL << PWR_CR3_UCPD_STDBY_Pos)         /*!< 0x00002000 */
6730 #define PWR_CR3_UCPD_STDBY           PWR_CR3_UCPD_STDBY_Msk                    /*!< USB Type-C and Power Delivery standby mode. */
6731 #define PWR_CR3_APC_Pos              (10U)
6732 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
6733 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
6734 #define PWR_CR3_RRS_Pos              (8U)
6735 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
6736 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
6737 #define PWR_CR3_EWUP5_Pos            (4U)
6738 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
6739 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
6740 #define PWR_CR3_EWUP4_Pos            (3U)
6741 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
6742 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
6743 #define PWR_CR3_EWUP3_Pos            (2U)
6744 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
6745 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
6746 #define PWR_CR3_EWUP2_Pos            (1U)
6747 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
6748 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
6749 #define PWR_CR3_EWUP1_Pos            (0U)
6750 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
6751 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
6752 #define PWR_CR3_EWUP_Pos             (0U)
6753 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
6754 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
6755 
6756 /********************  Bit definition for PWR_CR4 register  ********************/
6757 #define PWR_CR4_VBRS_Pos             (9U)
6758 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
6759 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
6760 #define PWR_CR4_VBE_Pos              (8U)
6761 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
6762 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
6763 #define PWR_CR4_WP5_Pos              (4U)
6764 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
6765 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
6766 #define PWR_CR4_WP4_Pos              (3U)
6767 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
6768 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
6769 #define PWR_CR4_WP3_Pos              (2U)
6770 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
6771 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
6772 #define PWR_CR4_WP2_Pos              (1U)
6773 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
6774 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
6775 #define PWR_CR4_WP1_Pos              (0U)
6776 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
6777 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
6778 
6779 /********************  Bit definition for PWR_SR1 register  ********************/
6780 #define PWR_SR1_WUFI_Pos             (15U)
6781 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
6782 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
6783 #define PWR_SR1_SBF_Pos              (8U)
6784 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
6785 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
6786 #define PWR_SR1_WUF_Pos              (0U)
6787 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
6788 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
6789 #define PWR_SR1_WUF5_Pos             (4U)
6790 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
6791 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
6792 #define PWR_SR1_WUF4_Pos             (3U)
6793 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
6794 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
6795 #define PWR_SR1_WUF3_Pos             (2U)
6796 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
6797 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
6798 #define PWR_SR1_WUF2_Pos             (1U)
6799 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
6800 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
6801 #define PWR_SR1_WUF1_Pos             (0U)
6802 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
6803 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
6804 
6805 /********************  Bit definition for PWR_SR2 register  ********************/
6806 #define PWR_SR2_PVMO4_Pos            (15U)
6807 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
6808 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
6809 #define PWR_SR2_PVMO3_Pos            (14U)
6810 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
6811 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
6812 #define PWR_SR2_PVMO2_Pos            (13U)
6813 #define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
6814 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
6815 #define PWR_SR2_PVMO1_Pos            (12U)
6816 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
6817 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
6818 #define PWR_SR2_PVDO_Pos             (11U)
6819 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
6820 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
6821 #define PWR_SR2_VOSF_Pos             (10U)
6822 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
6823 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
6824 #define PWR_SR2_REGLPF_Pos           (9U)
6825 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
6826 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
6827 #define PWR_SR2_REGLPS_Pos           (8U)
6828 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
6829 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
6830 
6831 /********************  Bit definition for PWR_SCR register  ********************/
6832 #define PWR_SCR_CSBF_Pos             (8U)
6833 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
6834 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
6835 #define PWR_SCR_CWUF_Pos             (0U)
6836 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
6837 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
6838 #define PWR_SCR_CWUF5_Pos            (4U)
6839 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
6840 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
6841 #define PWR_SCR_CWUF4_Pos            (3U)
6842 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
6843 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
6844 #define PWR_SCR_CWUF3_Pos            (2U)
6845 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
6846 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
6847 #define PWR_SCR_CWUF2_Pos            (1U)
6848 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
6849 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
6850 #define PWR_SCR_CWUF1_Pos            (0U)
6851 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
6852 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
6853 
6854 /********************  Bit definition for PWR_PUCRA register  ********************/
6855 #define PWR_PUCRA_PA15_Pos           (15U)
6856 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
6857 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
6858 #define PWR_PUCRA_PA13_Pos           (13U)
6859 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
6860 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
6861 #define PWR_PUCRA_PA12_Pos           (12U)
6862 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
6863 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
6864 #define PWR_PUCRA_PA11_Pos           (11U)
6865 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
6866 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
6867 #define PWR_PUCRA_PA10_Pos           (10U)
6868 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
6869 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
6870 #define PWR_PUCRA_PA9_Pos            (9U)
6871 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
6872 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
6873 #define PWR_PUCRA_PA8_Pos            (8U)
6874 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
6875 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
6876 #define PWR_PUCRA_PA7_Pos            (7U)
6877 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
6878 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
6879 #define PWR_PUCRA_PA6_Pos            (6U)
6880 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
6881 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
6882 #define PWR_PUCRA_PA5_Pos            (5U)
6883 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
6884 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
6885 #define PWR_PUCRA_PA4_Pos            (4U)
6886 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
6887 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
6888 #define PWR_PUCRA_PA3_Pos            (3U)
6889 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
6890 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
6891 #define PWR_PUCRA_PA2_Pos            (2U)
6892 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
6893 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
6894 #define PWR_PUCRA_PA1_Pos            (1U)
6895 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
6896 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
6897 #define PWR_PUCRA_PA0_Pos            (0U)
6898 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
6899 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
6900 
6901 /********************  Bit definition for PWR_PDCRA register  ********************/
6902 #define PWR_PDCRA_PA14_Pos           (14U)
6903 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
6904 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
6905 #define PWR_PDCRA_PA12_Pos           (12U)
6906 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
6907 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
6908 #define PWR_PDCRA_PA11_Pos           (11U)
6909 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
6910 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
6911 #define PWR_PDCRA_PA10_Pos           (10U)
6912 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
6913 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
6914 #define PWR_PDCRA_PA9_Pos            (9U)
6915 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
6916 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
6917 #define PWR_PDCRA_PA8_Pos            (8U)
6918 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
6919 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
6920 #define PWR_PDCRA_PA7_Pos            (7U)
6921 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
6922 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
6923 #define PWR_PDCRA_PA6_Pos            (6U)
6924 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
6925 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
6926 #define PWR_PDCRA_PA5_Pos            (5U)
6927 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
6928 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
6929 #define PWR_PDCRA_PA4_Pos            (4U)
6930 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
6931 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
6932 #define PWR_PDCRA_PA3_Pos            (3U)
6933 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
6934 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
6935 #define PWR_PDCRA_PA2_Pos            (2U)
6936 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
6937 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
6938 #define PWR_PDCRA_PA1_Pos            (1U)
6939 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
6940 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
6941 #define PWR_PDCRA_PA0_Pos            (0U)
6942 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
6943 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
6944 
6945 /********************  Bit definition for PWR_PUCRB register  ********************/
6946 
6947 #define PWR_PUCRB_PB15_Pos           (15U)
6948 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
6949 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
6950 #define PWR_PUCRB_PB14_Pos           (14U)
6951 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
6952 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
6953 #define PWR_PUCRB_PB13_Pos           (13U)
6954 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
6955 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
6956 #define PWR_PUCRB_PB12_Pos           (12U)
6957 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
6958 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
6959 #define PWR_PUCRB_PB11_Pos           (11U)
6960 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
6961 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
6962 #define PWR_PUCRB_PB10_Pos           (10U)
6963 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
6964 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
6965 #define PWR_PUCRB_PB9_Pos            (9U)
6966 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
6967 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
6968 #define PWR_PUCRB_PB8_Pos            (8U)
6969 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
6970 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
6971 #define PWR_PUCRB_PB7_Pos            (7U)
6972 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
6973 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
6974 #define PWR_PUCRB_PB6_Pos            (6U)
6975 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
6976 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
6977 #define PWR_PUCRB_PB5_Pos            (5U)
6978 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
6979 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
6980 #define PWR_PUCRB_PB4_Pos            (4U)
6981 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
6982 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
6983 #define PWR_PUCRB_PB3_Pos            (3U)
6984 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
6985 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
6986 #define PWR_PUCRB_PB2_Pos            (2U)
6987 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
6988 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
6989 #define PWR_PUCRB_PB1_Pos            (1U)
6990 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
6991 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
6992 #define PWR_PUCRB_PB0_Pos            (0U)
6993 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
6994 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
6995 
6996 /********************  Bit definition for PWR_PDCRB register  ********************/
6997 #define PWR_PDCRB_PB15_Pos           (15U)
6998 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
6999 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
7000 #define PWR_PDCRB_PB14_Pos           (14U)
7001 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
7002 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
7003 #define PWR_PDCRB_PB13_Pos           (13U)
7004 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
7005 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
7006 #define PWR_PDCRB_PB12_Pos           (12U)
7007 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
7008 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
7009 #define PWR_PDCRB_PB11_Pos           (11U)
7010 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
7011 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
7012 #define PWR_PDCRB_PB10_Pos           (10U)
7013 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
7014 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
7015 #define PWR_PDCRB_PB9_Pos            (9U)
7016 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
7017 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
7018 #define PWR_PDCRB_PB8_Pos            (8U)
7019 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
7020 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
7021 #define PWR_PDCRB_PB7_Pos            (7U)
7022 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
7023 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
7024 #define PWR_PDCRB_PB6_Pos            (6U)
7025 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
7026 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
7027 #define PWR_PDCRB_PB5_Pos            (5U)
7028 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
7029 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
7030 #define PWR_PDCRB_PB3_Pos            (3U)
7031 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
7032 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
7033 #define PWR_PDCRB_PB2_Pos            (2U)
7034 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
7035 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
7036 #define PWR_PDCRB_PB1_Pos            (1U)
7037 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
7038 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
7039 #define PWR_PDCRB_PB0_Pos            (0U)
7040 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
7041 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
7042 
7043 /********************  Bit definition for PWR_PUCRC register  ********************/
7044 #define PWR_PUCRC_PC15_Pos           (15U)
7045 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
7046 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
7047 #define PWR_PUCRC_PC14_Pos           (14U)
7048 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
7049 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
7050 #define PWR_PUCRC_PC13_Pos           (13U)
7051 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
7052 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
7053 #define PWR_PUCRC_PC12_Pos           (12U)
7054 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
7055 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
7056 #define PWR_PUCRC_PC11_Pos           (11U)
7057 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
7058 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
7059 #define PWR_PUCRC_PC10_Pos           (10U)
7060 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
7061 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
7062 #define PWR_PUCRC_PC9_Pos            (9U)
7063 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
7064 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
7065 #define PWR_PUCRC_PC8_Pos            (8U)
7066 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
7067 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
7068 #define PWR_PUCRC_PC7_Pos            (7U)
7069 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
7070 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
7071 #define PWR_PUCRC_PC6_Pos            (6U)
7072 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
7073 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
7074 #define PWR_PUCRC_PC5_Pos            (5U)
7075 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
7076 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
7077 #define PWR_PUCRC_PC4_Pos            (4U)
7078 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
7079 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
7080 #define PWR_PUCRC_PC3_Pos            (3U)
7081 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
7082 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
7083 #define PWR_PUCRC_PC2_Pos            (2U)
7084 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
7085 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
7086 #define PWR_PUCRC_PC1_Pos            (1U)
7087 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
7088 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
7089 #define PWR_PUCRC_PC0_Pos            (0U)
7090 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
7091 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
7092 
7093 /********************  Bit definition for PWR_PDCRC register  ********************/
7094 #define PWR_PDCRC_PC15_Pos           (15U)
7095 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
7096 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
7097 #define PWR_PDCRC_PC14_Pos           (14U)
7098 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
7099 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
7100 #define PWR_PDCRC_PC13_Pos           (13U)
7101 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
7102 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
7103 #define PWR_PDCRC_PC12_Pos           (12U)
7104 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
7105 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
7106 #define PWR_PDCRC_PC11_Pos           (11U)
7107 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
7108 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
7109 #define PWR_PDCRC_PC10_Pos           (10U)
7110 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
7111 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
7112 #define PWR_PDCRC_PC9_Pos            (9U)
7113 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
7114 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
7115 #define PWR_PDCRC_PC8_Pos            (8U)
7116 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
7117 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
7118 #define PWR_PDCRC_PC7_Pos            (7U)
7119 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
7120 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
7121 #define PWR_PDCRC_PC6_Pos            (6U)
7122 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
7123 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
7124 #define PWR_PDCRC_PC5_Pos            (5U)
7125 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
7126 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
7127 #define PWR_PDCRC_PC4_Pos            (4U)
7128 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
7129 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
7130 #define PWR_PDCRC_PC3_Pos            (3U)
7131 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
7132 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
7133 #define PWR_PDCRC_PC2_Pos            (2U)
7134 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
7135 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
7136 #define PWR_PDCRC_PC1_Pos            (1U)
7137 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
7138 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
7139 #define PWR_PDCRC_PC0_Pos            (0U)
7140 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
7141 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
7142 
7143 /********************  Bit definition for PWR_PUCRD register  ********************/
7144 #define PWR_PUCRD_PD15_Pos           (15U)
7145 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
7146 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
7147 #define PWR_PUCRD_PD14_Pos           (14U)
7148 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
7149 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
7150 #define PWR_PUCRD_PD13_Pos           (13U)
7151 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
7152 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
7153 #define PWR_PUCRD_PD12_Pos           (12U)
7154 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
7155 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
7156 #define PWR_PUCRD_PD11_Pos           (11U)
7157 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
7158 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
7159 #define PWR_PUCRD_PD10_Pos           (10U)
7160 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
7161 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
7162 #define PWR_PUCRD_PD9_Pos            (9U)
7163 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
7164 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
7165 #define PWR_PUCRD_PD8_Pos            (8U)
7166 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
7167 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
7168 #define PWR_PUCRD_PD7_Pos            (7U)
7169 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
7170 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
7171 #define PWR_PUCRD_PD6_Pos            (6U)
7172 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
7173 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
7174 #define PWR_PUCRD_PD5_Pos            (5U)
7175 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
7176 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
7177 #define PWR_PUCRD_PD4_Pos            (4U)
7178 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
7179 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
7180 #define PWR_PUCRD_PD3_Pos            (3U)
7181 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
7182 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
7183 #define PWR_PUCRD_PD2_Pos            (2U)
7184 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
7185 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
7186 #define PWR_PUCRD_PD1_Pos            (1U)
7187 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
7188 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
7189 #define PWR_PUCRD_PD0_Pos            (0U)
7190 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
7191 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
7192 
7193 /********************  Bit definition for PWR_PDCRD register  ********************/
7194 #define PWR_PDCRD_PD15_Pos           (15U)
7195 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
7196 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
7197 #define PWR_PDCRD_PD14_Pos           (14U)
7198 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
7199 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
7200 #define PWR_PDCRD_PD13_Pos           (13U)
7201 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
7202 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
7203 #define PWR_PDCRD_PD12_Pos           (12U)
7204 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
7205 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
7206 #define PWR_PDCRD_PD11_Pos           (11U)
7207 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
7208 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
7209 #define PWR_PDCRD_PD10_Pos           (10U)
7210 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
7211 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
7212 #define PWR_PDCRD_PD9_Pos            (9U)
7213 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
7214 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
7215 #define PWR_PDCRD_PD8_Pos            (8U)
7216 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
7217 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
7218 #define PWR_PDCRD_PD7_Pos            (7U)
7219 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
7220 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
7221 #define PWR_PDCRD_PD6_Pos            (6U)
7222 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
7223 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
7224 #define PWR_PDCRD_PD5_Pos            (5U)
7225 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
7226 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
7227 #define PWR_PDCRD_PD4_Pos            (4U)
7228 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
7229 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
7230 #define PWR_PDCRD_PD3_Pos            (3U)
7231 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
7232 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
7233 #define PWR_PDCRD_PD2_Pos            (2U)
7234 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
7235 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
7236 #define PWR_PDCRD_PD1_Pos            (1U)
7237 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
7238 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
7239 #define PWR_PDCRD_PD0_Pos            (0U)
7240 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
7241 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
7242 
7243 /********************  Bit definition for PWR_PUCRE register  ********************/
7244 #define PWR_PUCRE_PE15_Pos           (15U)
7245 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
7246 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
7247 #define PWR_PUCRE_PE14_Pos           (14U)
7248 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
7249 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
7250 #define PWR_PUCRE_PE13_Pos           (13U)
7251 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
7252 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
7253 #define PWR_PUCRE_PE12_Pos           (12U)
7254 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
7255 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
7256 #define PWR_PUCRE_PE11_Pos           (11U)
7257 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
7258 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
7259 #define PWR_PUCRE_PE10_Pos           (10U)
7260 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
7261 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
7262 #define PWR_PUCRE_PE9_Pos            (9U)
7263 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
7264 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
7265 #define PWR_PUCRE_PE8_Pos            (8U)
7266 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
7267 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
7268 #define PWR_PUCRE_PE7_Pos            (7U)
7269 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
7270 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
7271 #define PWR_PUCRE_PE6_Pos            (6U)
7272 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
7273 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
7274 #define PWR_PUCRE_PE5_Pos            (5U)
7275 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
7276 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
7277 #define PWR_PUCRE_PE4_Pos            (4U)
7278 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
7279 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
7280 #define PWR_PUCRE_PE3_Pos            (3U)
7281 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
7282 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
7283 #define PWR_PUCRE_PE2_Pos            (2U)
7284 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
7285 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
7286 #define PWR_PUCRE_PE1_Pos            (1U)
7287 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
7288 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
7289 #define PWR_PUCRE_PE0_Pos            (0U)
7290 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
7291 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
7292 
7293 /********************  Bit definition for PWR_PDCRE register  ********************/
7294 #define PWR_PDCRE_PE15_Pos           (15U)
7295 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
7296 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
7297 #define PWR_PDCRE_PE14_Pos           (14U)
7298 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
7299 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
7300 #define PWR_PDCRE_PE13_Pos           (13U)
7301 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
7302 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
7303 #define PWR_PDCRE_PE12_Pos           (12U)
7304 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
7305 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
7306 #define PWR_PDCRE_PE11_Pos           (11U)
7307 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
7308 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
7309 #define PWR_PDCRE_PE10_Pos           (10U)
7310 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
7311 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
7312 #define PWR_PDCRE_PE9_Pos            (9U)
7313 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
7314 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
7315 #define PWR_PDCRE_PE8_Pos            (8U)
7316 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
7317 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
7318 #define PWR_PDCRE_PE7_Pos            (7U)
7319 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
7320 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
7321 #define PWR_PDCRE_PE6_Pos            (6U)
7322 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
7323 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
7324 #define PWR_PDCRE_PE5_Pos            (5U)
7325 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
7326 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
7327 #define PWR_PDCRE_PE4_Pos            (4U)
7328 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
7329 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
7330 #define PWR_PDCRE_PE3_Pos            (3U)
7331 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
7332 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
7333 #define PWR_PDCRE_PE2_Pos            (2U)
7334 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
7335 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
7336 #define PWR_PDCRE_PE1_Pos            (1U)
7337 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
7338 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
7339 #define PWR_PDCRE_PE0_Pos            (0U)
7340 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
7341 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
7342 
7343 /********************  Bit definition for PWR_PUCRF register  ********************/
7344 #define PWR_PUCRF_PF15_Pos           (15U)
7345 #define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
7346 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
7347 #define PWR_PUCRF_PF14_Pos           (14U)
7348 #define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
7349 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
7350 #define PWR_PUCRF_PF13_Pos           (13U)
7351 #define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
7352 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
7353 #define PWR_PUCRF_PF12_Pos           (12U)
7354 #define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
7355 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
7356 #define PWR_PUCRF_PF11_Pos           (11U)
7357 #define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
7358 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
7359 #define PWR_PUCRF_PF10_Pos           (10U)
7360 #define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
7361 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
7362 #define PWR_PUCRF_PF9_Pos            (9U)
7363 #define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
7364 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
7365 #define PWR_PUCRF_PF8_Pos            (8U)
7366 #define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
7367 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
7368 #define PWR_PUCRF_PF7_Pos            (7U)
7369 #define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
7370 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
7371 #define PWR_PUCRF_PF6_Pos            (6U)
7372 #define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
7373 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
7374 #define PWR_PUCRF_PF5_Pos            (5U)
7375 #define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
7376 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
7377 #define PWR_PUCRF_PF4_Pos            (4U)
7378 #define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
7379 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
7380 #define PWR_PUCRF_PF3_Pos            (3U)
7381 #define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
7382 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
7383 #define PWR_PUCRF_PF2_Pos            (2U)
7384 #define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
7385 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
7386 #define PWR_PUCRF_PF1_Pos            (1U)
7387 #define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
7388 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
7389 #define PWR_PUCRF_PF0_Pos            (0U)
7390 #define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
7391 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
7392 
7393 /********************  Bit definition for PWR_PDCRF register  ********************/
7394 #define PWR_PDCRF_PF15_Pos           (15U)
7395 #define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */
7396 #define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
7397 #define PWR_PDCRF_PF14_Pos           (14U)
7398 #define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */
7399 #define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
7400 #define PWR_PDCRF_PF13_Pos           (13U)
7401 #define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */
7402 #define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
7403 #define PWR_PDCRF_PF12_Pos           (12U)
7404 #define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */
7405 #define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
7406 #define PWR_PDCRF_PF11_Pos           (11U)
7407 #define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */
7408 #define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
7409 #define PWR_PDCRF_PF10_Pos           (10U)
7410 #define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
7411 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
7412 #define PWR_PDCRF_PF9_Pos            (9U)
7413 #define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
7414 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
7415 #define PWR_PDCRF_PF8_Pos            (8U)
7416 #define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */
7417 #define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
7418 #define PWR_PDCRF_PF7_Pos            (7U)
7419 #define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */
7420 #define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
7421 #define PWR_PDCRF_PF6_Pos            (6U)
7422 #define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */
7423 #define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
7424 #define PWR_PDCRF_PF5_Pos            (5U)
7425 #define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */
7426 #define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
7427 #define PWR_PDCRF_PF4_Pos            (4U)
7428 #define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */
7429 #define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
7430 #define PWR_PDCRF_PF3_Pos            (3U)
7431 #define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */
7432 #define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
7433 #define PWR_PDCRF_PF2_Pos            (2U)
7434 #define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
7435 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
7436 #define PWR_PDCRF_PF1_Pos            (1U)
7437 #define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
7438 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
7439 #define PWR_PDCRF_PF0_Pos            (0U)
7440 #define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
7441 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
7442 
7443 /********************  Bit definition for PWR_PUCRG register  ********************/
7444 #define PWR_PUCRG_PG15_Pos           (15U)
7445 #define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */
7446 #define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
7447 #define PWR_PUCRG_PG14_Pos           (14U)
7448 #define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */
7449 #define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
7450 #define PWR_PUCRG_PG13_Pos           (13U)
7451 #define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */
7452 #define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
7453 #define PWR_PUCRG_PG12_Pos           (12U)
7454 #define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */
7455 #define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
7456 #define PWR_PUCRG_PG11_Pos           (11U)
7457 #define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */
7458 #define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
7459 #define PWR_PUCRG_PG10_Pos           (10U)
7460 #define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
7461 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
7462 #define PWR_PUCRG_PG9_Pos            (9U)
7463 #define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */
7464 #define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
7465 #define PWR_PUCRG_PG8_Pos            (8U)
7466 #define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */
7467 #define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
7468 #define PWR_PUCRG_PG7_Pos            (7U)
7469 #define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */
7470 #define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
7471 #define PWR_PUCRG_PG6_Pos            (6U)
7472 #define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */
7473 #define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
7474 #define PWR_PUCRG_PG5_Pos            (5U)
7475 #define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */
7476 #define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
7477 #define PWR_PUCRG_PG4_Pos            (4U)
7478 #define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */
7479 #define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
7480 #define PWR_PUCRG_PG3_Pos            (3U)
7481 #define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */
7482 #define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
7483 #define PWR_PUCRG_PG2_Pos            (2U)
7484 #define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */
7485 #define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
7486 #define PWR_PUCRG_PG1_Pos            (1U)
7487 #define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */
7488 #define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
7489 #define PWR_PUCRG_PG0_Pos            (0U)
7490 #define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */
7491 #define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
7492 
7493 /********************  Bit definition for PWR_PDCRG register  ********************/
7494 #define PWR_PDCRG_PG10_Pos           (10U)
7495 #define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
7496 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
7497 #define PWR_PDCRG_PG9_Pos            (9U)
7498 #define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
7499 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
7500 #define PWR_PDCRG_PG8_Pos            (8U)
7501 #define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
7502 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
7503 #define PWR_PDCRG_PG7_Pos            (7U)
7504 #define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
7505 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
7506 #define PWR_PDCRG_PG6_Pos            (6U)
7507 #define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
7508 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
7509 #define PWR_PDCRG_PG5_Pos            (5U)
7510 #define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
7511 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
7512 #define PWR_PDCRG_PG4_Pos            (4U)
7513 #define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
7514 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
7515 #define PWR_PDCRG_PG3_Pos            (3U)
7516 #define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
7517 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
7518 #define PWR_PDCRG_PG2_Pos            (2U)
7519 #define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
7520 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
7521 #define PWR_PDCRG_PG1_Pos            (1U)
7522 #define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
7523 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
7524 #define PWR_PDCRG_PG0_Pos            (0U)
7525 #define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
7526 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
7527 
7528 /********************  Bit definition for PWR_CR5 register  ********************/
7529 #define PWR_CR5_R1MODE_Pos           (8U)
7530 #define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
7531 #define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
7532 
7533 /******************************************************************************/
7534 /*                                                                            */
7535 /*                                    QUADSPI                                 */
7536 /*                                                                            */
7537 /******************************************************************************/
7538 /*****************  Bit definition for QUADSPI_CR register  *******************/
7539 #define QUADSPI_CR_EN_Pos              (0U)
7540 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
7541 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
7542 #define QUADSPI_CR_ABORT_Pos           (1U)
7543 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
7544 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
7545 #define QUADSPI_CR_DMAEN_Pos           (2U)
7546 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
7547 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
7548 #define QUADSPI_CR_TCEN_Pos            (3U)
7549 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
7550 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
7551 #define QUADSPI_CR_SSHIFT_Pos          (4U)
7552 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
7553 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
7554 #define QUADSPI_CR_DFM_Pos             (6U)
7555 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
7556 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
7557 #define QUADSPI_CR_FSEL_Pos            (7U)
7558 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
7559 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
7560 #define QUADSPI_CR_FTHRES_Pos          (8U)
7561 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
7562 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
7563 #define QUADSPI_CR_TEIE_Pos            (16U)
7564 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
7565 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
7566 #define QUADSPI_CR_TCIE_Pos            (17U)
7567 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
7568 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
7569 #define QUADSPI_CR_FTIE_Pos            (18U)
7570 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
7571 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
7572 #define QUADSPI_CR_SMIE_Pos            (19U)
7573 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
7574 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
7575 #define QUADSPI_CR_TOIE_Pos            (20U)
7576 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
7577 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
7578 #define QUADSPI_CR_APMS_Pos            (22U)
7579 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
7580 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
7581 #define QUADSPI_CR_PMM_Pos             (23U)
7582 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
7583 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
7584 #define QUADSPI_CR_PRESCALER_Pos       (24U)
7585 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
7586 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
7587 
7588 /*****************  Bit definition for QUADSPI_DCR register  ******************/
7589 #define QUADSPI_DCR_CKMODE_Pos         (0U)
7590 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
7591 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
7592 #define QUADSPI_DCR_CSHT_Pos           (8U)
7593 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
7594 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
7595 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
7596 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
7597 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
7598 #define QUADSPI_DCR_FSIZE_Pos          (16U)
7599 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
7600 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
7601 
7602 /******************  Bit definition for QUADSPI_SR register  *******************/
7603 #define QUADSPI_SR_TEF_Pos             (0U)
7604 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
7605 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
7606 #define QUADSPI_SR_TCF_Pos             (1U)
7607 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
7608 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
7609 #define QUADSPI_SR_FTF_Pos             (2U)
7610 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
7611 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
7612 #define QUADSPI_SR_SMF_Pos             (3U)
7613 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
7614 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
7615 #define QUADSPI_SR_TOF_Pos             (4U)
7616 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
7617 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
7618 #define QUADSPI_SR_BUSY_Pos            (5U)
7619 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
7620 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
7621 #define QUADSPI_SR_FLEVEL_Pos          (8U)
7622 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
7623 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
7624 
7625 /******************  Bit definition for QUADSPI_FCR register  ******************/
7626 #define QUADSPI_FCR_CTEF_Pos           (0U)
7627 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
7628 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
7629 #define QUADSPI_FCR_CTCF_Pos           (1U)
7630 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
7631 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
7632 #define QUADSPI_FCR_CSMF_Pos           (3U)
7633 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
7634 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
7635 #define QUADSPI_FCR_CTOF_Pos           (4U)
7636 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
7637 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
7638 
7639 /******************  Bit definition for QUADSPI_DLR register  ******************/
7640 #define QUADSPI_DLR_DL_Pos             (0U)
7641 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
7642 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
7643 
7644 /******************  Bit definition for QUADSPI_CCR register  ******************/
7645 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
7646 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
7647 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
7648 #define QUADSPI_CCR_IMODE_Pos          (8U)
7649 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
7650 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
7651 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
7652 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
7653 #define QUADSPI_CCR_ADMODE_Pos         (10U)
7654 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
7655 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
7656 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
7657 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
7658 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
7659 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
7660 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
7661 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
7662 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
7663 #define QUADSPI_CCR_ABMODE_Pos         (14U)
7664 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
7665 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
7666 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
7667 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
7668 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
7669 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
7670 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
7671 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
7672 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
7673 #define QUADSPI_CCR_DCYC_Pos           (18U)
7674 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
7675 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
7676 #define QUADSPI_CCR_DMODE_Pos          (24U)
7677 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
7678 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
7679 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
7680 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
7681 #define QUADSPI_CCR_FMODE_Pos          (26U)
7682 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
7683 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
7684 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
7685 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
7686 #define QUADSPI_CCR_SIOO_Pos           (28U)
7687 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
7688 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
7689 #define QUADSPI_CCR_DHHC_Pos           (30U)
7690 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
7691 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
7692 #define QUADSPI_CCR_DDRM_Pos           (31U)
7693 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
7694 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
7695 
7696 /******************  Bit definition for QUADSPI_AR register  *******************/
7697 #define QUADSPI_AR_ADDRESS_Pos         (0U)
7698 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
7699 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
7700 
7701 /******************  Bit definition for QUADSPI_ABR register  ******************/
7702 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
7703 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
7704 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
7705 
7706 /******************  Bit definition for QUADSPI_DR register  *******************/
7707 #define QUADSPI_DR_DATA_Pos            (0U)
7708 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
7709 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
7710 
7711 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
7712 #define QUADSPI_PSMKR_MASK_Pos         (0U)
7713 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
7714 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
7715 
7716 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
7717 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
7718 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
7719 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
7720 
7721 /******************  Bit definition for QUADSPI_PIR register  *****************/
7722 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
7723 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
7724 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
7725 
7726 /******************  Bit definition for QUADSPI_LPTR register  *****************/
7727 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
7728 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
7729 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
7730 
7731 /******************************************************************************/
7732 /*                                                                            */
7733 /*                         Reset and Clock Control                            */
7734 /*                                                                            */
7735 /******************************************************************************/
7736 /*
7737 * @brief Specific device feature definitions  (not present on all devices in the STM32G4 series)
7738 */
7739 
7740 #define RCC_HSI48_SUPPORT
7741 #define RCC_PLLP_DIV_2_31_SUPPORT
7742 
7743 /********************  Bit definition for RCC_CR register  ********************/
7744 #define RCC_CR_HSION_Pos                     (8U)
7745 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
7746 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
7747 #define RCC_CR_HSIKERON_Pos                  (9U)
7748 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
7749 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
7750 #define RCC_CR_HSIRDY_Pos                    (10U)
7751 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
7752 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
7753 
7754 #define RCC_CR_HSEON_Pos                     (16U)
7755 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
7756 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
7757 #define RCC_CR_HSERDY_Pos                    (17U)
7758 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
7759 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
7760 #define RCC_CR_HSEBYP_Pos                    (18U)
7761 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
7762 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
7763 #define RCC_CR_CSSON_Pos                     (19U)
7764 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
7765 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
7766 
7767 #define RCC_CR_PLLON_Pos                     (24U)
7768 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
7769 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
7770 #define RCC_CR_PLLRDY_Pos                    (25U)
7771 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
7772 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
7773 
7774 /********************  Bit definition for RCC_ICSCR register  ***************/
7775 /*!< HSICAL configuration */
7776 #define RCC_ICSCR_HSICAL_Pos                 (16U)
7777 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
7778 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
7779 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
7780 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
7781 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
7782 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
7783 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
7784 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
7785 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
7786 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
7787 
7788 /*!< HSITRIM configuration */
7789 #define RCC_ICSCR_HSITRIM_Pos                (24U)
7790 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
7791 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
7792 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
7793 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
7794 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
7795 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
7796 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
7797 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
7798 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
7799 
7800 /********************  Bit definition for RCC_CFGR register  ******************/
7801 /*!< SW configuration */
7802 #define RCC_CFGR_SW_Pos                      (0U)
7803 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
7804 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
7805 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
7806 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
7807 
7808 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
7809 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
7810 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
7811 
7812 /*!< SWS configuration */
7813 #define RCC_CFGR_SWS_Pos                     (2U)
7814 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
7815 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
7816 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
7817 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
7818 
7819 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
7820 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
7821 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
7822 
7823 /*!< HPRE configuration */
7824 #define RCC_CFGR_HPRE_Pos                    (4U)
7825 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
7826 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
7827 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
7828 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
7829 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
7830 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
7831 
7832 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
7833 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
7834 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
7835 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
7836 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
7837 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
7838 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
7839 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
7840 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
7841 
7842 /*!< PPRE1 configuration */
7843 #define RCC_CFGR_PPRE1_Pos                   (8U)
7844 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
7845 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
7846 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
7847 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
7848 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
7849 
7850 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
7851 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
7852 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
7853 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
7854 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
7855 
7856 /*!< PPRE2 configuration */
7857 #define RCC_CFGR_PPRE2_Pos                   (11U)
7858 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
7859 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
7860 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
7861 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
7862 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
7863 
7864 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
7865 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
7866 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
7867 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
7868 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
7869 
7870 /*!< MCOSEL configuration */
7871 #define RCC_CFGR_MCOSEL_Pos                  (24U)
7872 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
7873 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
7874 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
7875 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
7876 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
7877 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
7878 
7879 #define RCC_CFGR_MCOPRE_Pos                  (28U)
7880 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
7881 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
7882 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
7883 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
7884 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
7885 
7886 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
7887 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
7888 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
7889 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
7890 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
7891 
7892 /* Legacy aliases */
7893 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
7894 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
7895 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
7896 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
7897 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
7898 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
7899 
7900 /********************  Bit definition for RCC_PLLCFGR register  ***************/
7901 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
7902 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
7903 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
7904 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
7905 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
7906 
7907 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
7908 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
7909 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
7910 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
7911 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
7912 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
7913 
7914 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
7915 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
7916 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
7917 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
7918 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
7919 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
7920 #define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
7921 
7922 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
7923 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
7924 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
7925 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
7926 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
7927 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
7928 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
7929 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
7930 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
7931 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
7932 
7933 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
7934 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
7935 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
7936 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
7937 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
7938 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
7939 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
7940 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
7941 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
7942 
7943 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
7944 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
7945 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
7946 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
7947 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
7948 
7949 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
7950 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
7951 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
7952 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
7953 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
7954 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
7955 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
7956 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
7957 
7958 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
7959 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
7960 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
7961 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
7962 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
7963 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
7964 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
7965 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
7966 
7967 /********************  Bit definition for RCC_CIER register  ******************/
7968 #define RCC_CIER_LSIRDYIE_Pos                (0U)
7969 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
7970 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
7971 #define RCC_CIER_LSERDYIE_Pos                (1U)
7972 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
7973 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
7974 #define RCC_CIER_HSIRDYIE_Pos                (3U)
7975 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
7976 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
7977 #define RCC_CIER_HSERDYIE_Pos                (4U)
7978 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
7979 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
7980 #define RCC_CIER_PLLRDYIE_Pos                (5U)
7981 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
7982 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
7983 #define RCC_CIER_LSECSSIE_Pos                (9U)
7984 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
7985 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
7986 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
7987 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
7988 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
7989 
7990 /********************  Bit definition for RCC_CIFR register  ******************/
7991 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
7992 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
7993 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
7994 #define RCC_CIFR_LSERDYF_Pos                 (1U)
7995 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
7996 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
7997 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
7998 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
7999 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
8000 #define RCC_CIFR_HSERDYF_Pos                 (4U)
8001 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
8002 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
8003 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
8004 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
8005 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
8006 #define RCC_CIFR_CSSF_Pos                    (8U)
8007 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
8008 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
8009 #define RCC_CIFR_LSECSSF_Pos                 (9U)
8010 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
8011 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
8012 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
8013 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
8014 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
8015 
8016 /********************  Bit definition for RCC_CICR register  ******************/
8017 #define RCC_CICR_LSIRDYC_Pos                 (0U)
8018 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
8019 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
8020 #define RCC_CICR_LSERDYC_Pos                 (1U)
8021 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
8022 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
8023 #define RCC_CICR_HSIRDYC_Pos                 (3U)
8024 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
8025 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
8026 #define RCC_CICR_HSERDYC_Pos                 (4U)
8027 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
8028 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
8029 #define RCC_CICR_PLLRDYC_Pos                 (5U)
8030 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
8031 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
8032 #define RCC_CICR_CSSC_Pos                    (8U)
8033 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
8034 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
8035 #define RCC_CICR_LSECSSC_Pos                 (9U)
8036 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
8037 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
8038 #define RCC_CICR_HSI48RDYC_Pos               (10U)
8039 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
8040 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
8041 
8042 /********************  Bit definition for RCC_AHB1RSTR register  **************/
8043 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
8044 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
8045 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
8046 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
8047 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
8048 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
8049 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
8050 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
8051 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
8052 #define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
8053 #define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
8054 #define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
8055 #define RCC_AHB1RSTR_FMACRST_Pos             (4U)
8056 #define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
8057 #define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
8058 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
8059 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
8060 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
8061 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
8062 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
8063 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
8064 
8065 /********************  Bit definition for RCC_AHB2RSTR register  **************/
8066 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
8067 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
8068 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
8069 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
8070 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
8071 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
8072 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
8073 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
8074 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
8075 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
8076 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
8077 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
8078 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
8079 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
8080 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
8081 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
8082 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
8083 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
8084 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
8085 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
8086 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
8087 #define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
8088 #define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
8089 #define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
8090 #define RCC_AHB2RSTR_ADC345RST_Pos           (14U)
8091 #define RCC_AHB2RSTR_ADC345RST_Msk           (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
8092 #define RCC_AHB2RSTR_ADC345RST               RCC_AHB2RSTR_ADC345RST_Msk
8093 #define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
8094 #define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
8095 #define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
8096 #define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
8097 #define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
8098 #define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
8099 #define RCC_AHB2RSTR_RNGRST_Pos              (26U)
8100 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
8101 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
8102 
8103 /********************  Bit definition for RCC_AHB3RSTR register  **************/
8104 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
8105 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
8106 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
8107 
8108 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
8109 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
8110 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
8111 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
8112 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
8113 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
8114 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
8115 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
8116 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
8117 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
8118 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
8119 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
8120 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
8121 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
8122 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
8123 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
8124 #define RCC_APB1RSTR1_CRSRST_Pos             (8U)
8125 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
8126 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
8127 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
8128 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
8129 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
8130 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
8131 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
8132 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
8133 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
8134 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
8135 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
8136 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
8137 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
8138 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
8139 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
8140 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
8141 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
8142 #define RCC_APB1RSTR1_UART5RST_Pos           (20U)
8143 #define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
8144 #define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk
8145 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
8146 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
8147 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
8148 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
8149 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
8150 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
8151 #define RCC_APB1RSTR1_USBRST_Pos             (23U)
8152 #define RCC_APB1RSTR1_USBRST_Msk             (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
8153 #define RCC_APB1RSTR1_USBRST                 RCC_APB1RSTR1_USBRST_Msk
8154 #define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
8155 #define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
8156 #define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
8157 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
8158 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
8159 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
8160 #define RCC_APB1RSTR1_I2C3RST_Pos            (30U)
8161 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
8162 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
8163 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
8164 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
8165 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
8166 
8167 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
8168 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
8169 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
8170 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
8171 #define RCC_APB1RSTR2_I2C4RST_Pos            (1U)
8172 #define RCC_APB1RSTR2_I2C4RST_Msk            (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
8173 #define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk
8174 #define RCC_APB1RSTR2_UCPD1RST_Pos           (8U)
8175 #define RCC_APB1RSTR2_UCPD1RST_Msk           (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
8176 #define RCC_APB1RSTR2_UCPD1RST               RCC_APB1RSTR2_UCPD1RST_Msk
8177 
8178 /********************  Bit definition for RCC_APB2RSTR register  **************/
8179 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
8180 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
8181 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
8182 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
8183 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
8184 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
8185 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
8186 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
8187 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
8188 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
8189 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
8190 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
8191 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
8192 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
8193 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
8194 #define RCC_APB2RSTR_SPI4RST_Pos             (15U)
8195 #define RCC_APB2RSTR_SPI4RST_Msk             (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
8196 #define RCC_APB2RSTR_SPI4RST                 RCC_APB2RSTR_SPI4RST_Msk
8197 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
8198 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
8199 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
8200 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
8201 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
8202 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
8203 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
8204 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
8205 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
8206 #define RCC_APB2RSTR_TIM20RST_Pos            (20U)
8207 #define RCC_APB2RSTR_TIM20RST_Msk            (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
8208 #define RCC_APB2RSTR_TIM20RST                RCC_APB2RSTR_TIM20RST_Msk
8209 #define RCC_APB2RSTR_SAI1RST_Pos             (21U)
8210 #define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
8211 #define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
8212 
8213 /********************  Bit definition for RCC_AHB1ENR register  ***************/
8214 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
8215 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
8216 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
8217 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
8218 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
8219 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
8220 #define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
8221 #define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
8222 #define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
8223 #define RCC_AHB1ENR_CORDICEN_Pos             (3U)
8224 #define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
8225 #define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
8226 #define RCC_AHB1ENR_FMACEN_Pos               (4U)
8227 #define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
8228 #define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
8229 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
8230 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
8231 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
8232 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
8233 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
8234 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
8235 
8236 /********************  Bit definition for RCC_AHB2ENR register  ***************/
8237 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
8238 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
8239 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
8240 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
8241 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
8242 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
8243 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
8244 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
8245 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
8246 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
8247 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
8248 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
8249 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
8250 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
8251 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
8252 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
8253 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
8254 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
8255 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
8256 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
8257 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
8258 #define RCC_AHB2ENR_ADC12EN_Pos              (13U)
8259 #define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
8260 #define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
8261 #define RCC_AHB2ENR_ADC345EN_Pos             (14U)
8262 #define RCC_AHB2ENR_ADC345EN_Msk             (0x1UL << RCC_AHB2ENR_ADC345EN_Pos)  /*!< 0x00004000 */
8263 #define RCC_AHB2ENR_ADC345EN                 RCC_AHB2ENR_ADC345EN_Msk
8264 #define RCC_AHB2ENR_DAC1EN_Pos               (16U)
8265 #define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
8266 #define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
8267 #define RCC_AHB2ENR_DAC3EN_Pos               (18U)
8268 #define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
8269 #define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
8270 #define RCC_AHB2ENR_RNGEN_Pos                (26U)
8271 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
8272 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
8273 
8274 /********************  Bit definition for RCC_AHB3ENR register  ***************/
8275 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
8276 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
8277 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
8278 
8279 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
8280 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
8281 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
8282 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
8283 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
8284 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
8285 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
8286 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
8287 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
8288 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
8289 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
8290 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
8291 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
8292 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
8293 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
8294 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
8295 #define RCC_APB1ENR1_CRSEN_Pos               (8U)
8296 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
8297 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
8298 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
8299 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
8300 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
8301 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
8302 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
8303 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
8304 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
8305 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
8306 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
8307 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
8308 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
8309 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
8310 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
8311 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
8312 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
8313 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
8314 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
8315 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
8316 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
8317 #define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
8318 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
8319 #define RCC_APB1ENR1_UART5EN_Pos             (20U)
8320 #define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
8321 #define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk
8322 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
8323 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
8324 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
8325 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
8326 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
8327 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
8328 #define RCC_APB1ENR1_USBEN_Pos               (23U)
8329 #define RCC_APB1ENR1_USBEN_Msk               (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
8330 #define RCC_APB1ENR1_USBEN                   RCC_APB1ENR1_USBEN_Msk
8331 #define RCC_APB1ENR1_FDCANEN_Pos             (25U)
8332 #define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
8333 #define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
8334 #define RCC_APB1ENR1_PWREN_Pos               (28U)
8335 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
8336 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
8337 #define RCC_APB1ENR1_I2C3EN_Pos              (30U)
8338 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
8339 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
8340 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
8341 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
8342 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
8343 
8344 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
8345 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
8346 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
8347 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
8348 #define RCC_APB1ENR2_I2C4EN_Pos              (1U)
8349 #define RCC_APB1ENR2_I2C4EN_Msk              (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
8350 #define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk
8351 #define RCC_APB1ENR2_UCPD1EN_Pos             (8U)
8352 #define RCC_APB1ENR2_UCPD1EN_Msk             (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
8353 #define RCC_APB1ENR2_UCPD1EN                 RCC_APB1ENR2_UCPD1EN_Msk
8354 
8355 /********************  Bit definition for RCC_APB2ENR register  ***************/
8356 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
8357 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
8358 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
8359 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
8360 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
8361 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
8362 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
8363 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
8364 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
8365 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
8366 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
8367 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
8368 #define RCC_APB2ENR_USART1EN_Pos             (14U)
8369 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
8370 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
8371 #define RCC_APB2ENR_SPI4EN_Pos               (15U)
8372 #define RCC_APB2ENR_SPI4EN_Msk               (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
8373 #define RCC_APB2ENR_SPI4EN                   RCC_APB2ENR_SPI4EN_Msk
8374 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
8375 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
8376 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
8377 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
8378 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
8379 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
8380 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
8381 #define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
8382 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
8383 #define RCC_APB2ENR_TIM20EN_Pos              (20U)
8384 #define RCC_APB2ENR_TIM20EN_Msk              (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
8385 #define RCC_APB2ENR_TIM20EN                  RCC_APB2ENR_TIM20EN_Msk
8386 #define RCC_APB2ENR_SAI1EN_Pos               (21U)
8387 #define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
8388 #define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
8389 
8390 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
8391 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
8392 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
8393 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
8394 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
8395 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
8396 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
8397 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
8398 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
8399 #define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
8400 #define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
8401 #define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
8402 #define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
8403 #define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
8404 #define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
8405 #define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
8406 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
8407 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
8408 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
8409 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
8410 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
8411 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
8412 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
8413 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
8414 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
8415 
8416 /********************  Bit definition for RCC_AHB2SMENR register  *************/
8417 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
8418 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
8419 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
8420 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
8421 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
8422 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
8423 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
8424 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
8425 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
8426 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
8427 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
8428 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
8429 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
8430 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
8431 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
8432 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
8433 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
8434 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
8435 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
8436 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
8437 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
8438 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
8439 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
8440 #define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
8441 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (10U)
8442 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
8443 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
8444 #define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
8445 #define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
8446 #define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
8447 #define RCC_AHB2SMENR_ADC345SMEN_Pos         (14U)
8448 #define RCC_AHB2SMENR_ADC345SMEN_Msk         (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
8449 #define RCC_AHB2SMENR_ADC345SMEN             RCC_AHB2SMENR_ADC345SMEN_Msk
8450 #define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
8451 #define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
8452 #define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
8453 #define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
8454 #define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
8455 #define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
8456 #define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
8457 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
8458 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
8459 
8460 /********************  Bit definition for RCC_AHB3SMENR register  *************/
8461 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
8462 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
8463 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
8464 
8465 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
8466 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
8467 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
8468 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
8469 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
8470 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
8471 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
8472 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
8473 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
8474 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
8475 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
8476 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
8477 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
8478 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
8479 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
8480 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
8481 #define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
8482 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
8483 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
8484 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
8485 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
8486 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
8487 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
8488 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
8489 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
8490 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
8491 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
8492 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
8493 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
8494 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
8495 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
8496 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
8497 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
8498 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
8499 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
8500 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
8501 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
8502 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
8503 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
8504 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
8505 #define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)
8506 #define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
8507 #define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk
8508 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
8509 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
8510 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
8511 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
8512 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
8513 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
8514 #define RCC_APB1SMENR1_USBSMEN_Pos           (23U)
8515 #define RCC_APB1SMENR1_USBSMEN_Msk           (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
8516 #define RCC_APB1SMENR1_USBSMEN               RCC_APB1SMENR1_USBSMEN_Msk
8517 #define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
8518 #define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
8519 #define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
8520 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
8521 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
8522 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
8523 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (30U)
8524 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
8525 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
8526 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
8527 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
8528 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
8529 
8530 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
8531 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
8532 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
8533 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
8534 #define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)
8535 #define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
8536 #define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk
8537 #define RCC_APB1SMENR2_UCPD1SMEN_Pos         (8U)
8538 #define RCC_APB1SMENR2_UCPD1SMEN_Msk         (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
8539 #define RCC_APB1SMENR2_UCPD1SMEN             RCC_APB1SMENR2_UCPD1SMEN_Msk
8540 
8541 /********************  Bit definition for RCC_APB2SMENR register  *************/
8542 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
8543 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
8544 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
8545 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
8546 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
8547 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
8548 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
8549 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
8550 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
8551 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
8552 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
8553 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
8554 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
8555 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
8556 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
8557 #define RCC_APB2SMENR_SPI4SMEN_Pos           (15U)
8558 #define RCC_APB2SMENR_SPI4SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
8559 #define RCC_APB2SMENR_SPI4SMEN               RCC_APB2SMENR_SPI4SMEN_Msk
8560 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
8561 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
8562 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
8563 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
8564 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
8565 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
8566 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
8567 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
8568 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
8569 #define RCC_APB2SMENR_TIM20SMEN_Pos          (20U)
8570 #define RCC_APB2SMENR_TIM20SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
8571 #define RCC_APB2SMENR_TIM20SMEN              RCC_APB2SMENR_TIM20SMEN_Msk
8572 #define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
8573 #define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
8574 #define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
8575 
8576 /********************  Bit definition for RCC_CCIPR register  ******************/
8577 #define RCC_CCIPR_USART1SEL_Pos              (0U)
8578 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
8579 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
8580 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
8581 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
8582 
8583 #define RCC_CCIPR_USART2SEL_Pos              (2U)
8584 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
8585 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
8586 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
8587 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
8588 
8589 #define RCC_CCIPR_USART3SEL_Pos              (4U)
8590 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
8591 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
8592 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
8593 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
8594 
8595 #define RCC_CCIPR_UART4SEL_Pos               (6U)
8596 #define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
8597 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
8598 #define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
8599 #define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
8600 
8601 #define RCC_CCIPR_UART5SEL_Pos               (8U)
8602 #define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
8603 #define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk
8604 #define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
8605 #define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
8606 
8607 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
8608 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
8609 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
8610 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
8611 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
8612 
8613 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
8614 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
8615 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
8616 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
8617 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
8618 
8619 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
8620 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
8621 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
8622 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
8623 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
8624 
8625 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
8626 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
8627 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
8628 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
8629 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
8630 
8631 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
8632 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
8633 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
8634 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
8635 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
8636 
8637 #define RCC_CCIPR_SAI1SEL_Pos                (20U)
8638 #define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
8639 #define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
8640 #define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
8641 #define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
8642 
8643 #define RCC_CCIPR_I2S23SEL_Pos               (22U)
8644 #define RCC_CCIPR_I2S23SEL_Msk               (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
8645 #define RCC_CCIPR_I2S23SEL                   RCC_CCIPR_I2S23SEL_Msk
8646 #define RCC_CCIPR_I2S23SEL_0                 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
8647 #define RCC_CCIPR_I2S23SEL_1                 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
8648 
8649 #define RCC_CCIPR_FDCANSEL_Pos               (24U)
8650 #define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
8651 #define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
8652 #define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
8653 #define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
8654 
8655 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
8656 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
8657 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
8658 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
8659 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
8660 
8661 #define RCC_CCIPR_ADC12SEL_Pos               (28U)
8662 #define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
8663 #define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
8664 #define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
8665 #define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
8666 
8667 #define RCC_CCIPR_ADC345SEL_Pos              (30U)
8668 #define RCC_CCIPR_ADC345SEL_Msk              (0x3UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
8669 #define RCC_CCIPR_ADC345SEL                  RCC_CCIPR_ADC345SEL_Msk
8670 #define RCC_CCIPR_ADC345SEL_0                (0x1UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x40000000 */
8671 #define RCC_CCIPR_ADC345SEL_1                (0x2UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
8672 
8673 /********************  Bit definition for RCC_BDCR register  ******************/
8674 #define RCC_BDCR_LSEON_Pos                   (0U)
8675 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
8676 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
8677 #define RCC_BDCR_LSERDY_Pos                  (1U)
8678 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
8679 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
8680 #define RCC_BDCR_LSEBYP_Pos                  (2U)
8681 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
8682 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
8683 
8684 #define RCC_BDCR_LSEDRV_Pos                  (3U)
8685 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
8686 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
8687 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
8688 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
8689 
8690 #define RCC_BDCR_LSECSSON_Pos                (5U)
8691 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
8692 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
8693 #define RCC_BDCR_LSECSSD_Pos                 (6U)
8694 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
8695 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
8696 
8697 #define RCC_BDCR_RTCSEL_Pos                  (8U)
8698 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
8699 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
8700 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
8701 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
8702 
8703 #define RCC_BDCR_RTCEN_Pos                   (15U)
8704 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
8705 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
8706 #define RCC_BDCR_BDRST_Pos                   (16U)
8707 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
8708 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
8709 #define RCC_BDCR_LSCOEN_Pos                  (24U)
8710 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
8711 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
8712 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
8713 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
8714 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
8715 
8716 /********************  Bit definition for RCC_CSR register  *******************/
8717 #define RCC_CSR_LSION_Pos                    (0U)
8718 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
8719 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
8720 #define RCC_CSR_LSIRDY_Pos                   (1U)
8721 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
8722 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
8723 
8724 #define RCC_CSR_RMVF_Pos                     (23U)
8725 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
8726 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
8727 #define RCC_CSR_OBLRSTF_Pos                  (25U)
8728 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
8729 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
8730 #define RCC_CSR_PINRSTF_Pos                  (26U)
8731 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
8732 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
8733 #define RCC_CSR_BORRSTF_Pos                  (27U)
8734 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
8735 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
8736 #define RCC_CSR_SFTRSTF_Pos                  (28U)
8737 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
8738 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
8739 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
8740 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
8741 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
8742 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
8743 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
8744 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
8745 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
8746 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
8747 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
8748 
8749 /********************  Bit definition for RCC_CRRCR register  *****************/
8750 #define RCC_CRRCR_HSI48ON_Pos                (0U)
8751 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
8752 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
8753 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
8754 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
8755 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
8756 
8757 /*!< HSI48CAL configuration */
8758 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
8759 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
8760 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
8761 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
8762 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
8763 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
8764 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
8765 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
8766 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
8767 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
8768 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
8769 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
8770 
8771 /********************  Bit definition for RCC_CCIPR2 register  ******************/
8772 #define RCC_CCIPR2_I2C4SEL_Pos               (0U)
8773 #define RCC_CCIPR2_I2C4SEL_Msk               (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
8774 #define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk
8775 #define RCC_CCIPR2_I2C4SEL_0                 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
8776 #define RCC_CCIPR2_I2C4SEL_1                 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
8777 
8778 #define RCC_CCIPR2_QSPISEL_Pos               (20U)
8779 #define RCC_CCIPR2_QSPISEL_Msk               (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
8780 #define RCC_CCIPR2_QSPISEL                   RCC_CCIPR2_QSPISEL_Msk
8781 #define RCC_CCIPR2_QSPISEL_0                 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
8782 #define RCC_CCIPR2_QSPISEL_1                 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
8783 
8784 /******************************************************************************/
8785 /*                                                                            */
8786 /*                                    RNG                                     */
8787 /*                                                                            */
8788 /******************************************************************************/
8789 /********************  Bits definition for RNG_CR register  *******************/
8790 #define RNG_CR_RNGEN_Pos    (2U)
8791 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
8792 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
8793 #define RNG_CR_IE_Pos       (3U)
8794 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
8795 #define RNG_CR_IE           RNG_CR_IE_Msk
8796 #define RNG_CR_CED_Pos      (5U)
8797 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
8798 #define RNG_CR_CED          RNG_CR_IE_Msk
8799 
8800 /********************  Bits definition for RNG_SR register  *******************/
8801 #define RNG_SR_DRDY_Pos     (0U)
8802 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
8803 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
8804 #define RNG_SR_CECS_Pos     (1U)
8805 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
8806 #define RNG_SR_CECS         RNG_SR_CECS_Msk
8807 #define RNG_SR_SECS_Pos     (2U)
8808 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
8809 #define RNG_SR_SECS         RNG_SR_SECS_Msk
8810 #define RNG_SR_CEIS_Pos     (5U)
8811 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
8812 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
8813 #define RNG_SR_SEIS_Pos     (6U)
8814 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
8815 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
8816 
8817 /******************************************************************************/
8818 /*                                                                            */
8819 /*                           Real-Time Clock (RTC)                            */
8820 /*                                                                            */
8821 /******************************************************************************/
8822 
8823 /********************  Bits definition for RTC_TR register  *******************/
8824 #define RTC_TR_PM_Pos                (22U)
8825 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
8826 #define RTC_TR_PM                    RTC_TR_PM_Msk
8827 #define RTC_TR_HT_Pos                (20U)
8828 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
8829 #define RTC_TR_HT                    RTC_TR_HT_Msk
8830 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
8831 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
8832 #define RTC_TR_HU_Pos                (16U)
8833 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
8834 #define RTC_TR_HU                    RTC_TR_HU_Msk
8835 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
8836 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
8837 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
8838 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
8839 #define RTC_TR_MNT_Pos               (12U)
8840 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
8841 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
8842 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
8843 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
8844 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
8845 #define RTC_TR_MNU_Pos               (8U)
8846 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
8847 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
8848 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
8849 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
8850 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
8851 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
8852 #define RTC_TR_ST_Pos                (4U)
8853 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
8854 #define RTC_TR_ST                    RTC_TR_ST_Msk
8855 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
8856 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
8857 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
8858 #define RTC_TR_SU_Pos                (0U)
8859 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
8860 #define RTC_TR_SU                    RTC_TR_SU_Msk
8861 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
8862 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
8863 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
8864 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
8865 
8866 /********************  Bits definition for RTC_DR register  *******************/
8867 #define RTC_DR_YT_Pos                (20U)
8868 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
8869 #define RTC_DR_YT                    RTC_DR_YT_Msk
8870 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
8871 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
8872 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
8873 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
8874 #define RTC_DR_YU_Pos                (16U)
8875 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
8876 #define RTC_DR_YU                    RTC_DR_YU_Msk
8877 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
8878 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
8879 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
8880 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
8881 #define RTC_DR_WDU_Pos               (13U)
8882 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
8883 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
8884 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
8885 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
8886 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
8887 #define RTC_DR_MT_Pos                (12U)
8888 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
8889 #define RTC_DR_MT                    RTC_DR_MT_Msk
8890 #define RTC_DR_MU_Pos                (8U)
8891 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
8892 #define RTC_DR_MU                    RTC_DR_MU_Msk
8893 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
8894 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
8895 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
8896 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
8897 #define RTC_DR_DT_Pos                (4U)
8898 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
8899 #define RTC_DR_DT                    RTC_DR_DT_Msk
8900 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
8901 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
8902 #define RTC_DR_DU_Pos                (0U)
8903 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
8904 #define RTC_DR_DU                    RTC_DR_DU_Msk
8905 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
8906 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
8907 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
8908 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
8909 
8910 /********************  Bits definition for RTC_SSR register  ******************/
8911 #define RTC_SSR_SS_Pos               (0U)
8912 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
8913 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
8914 
8915 /********************  Bits definition for RTC_ICSR register  ******************/
8916 #define RTC_ICSR_RECALPF_Pos         (16U)
8917 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
8918 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
8919 #define RTC_ICSR_INIT_Pos            (7U)
8920 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
8921 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
8922 #define RTC_ICSR_INITF_Pos           (6U)
8923 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
8924 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
8925 #define RTC_ICSR_RSF_Pos             (5U)
8926 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
8927 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
8928 #define RTC_ICSR_INITS_Pos           (4U)
8929 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
8930 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
8931 #define RTC_ICSR_SHPF_Pos            (3U)
8932 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
8933 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
8934 #define RTC_ICSR_WUTWF_Pos           (2U)
8935 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
8936 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
8937 #define RTC_ICSR_ALRBWF_Pos          (1U)
8938 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
8939 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
8940 #define RTC_ICSR_ALRAWF_Pos          (0U)
8941 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
8942 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
8943 
8944 /********************  Bits definition for RTC_PRER register  *****************/
8945 #define RTC_PRER_PREDIV_A_Pos        (16U)
8946 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
8947 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
8948 #define RTC_PRER_PREDIV_S_Pos        (0U)
8949 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
8950 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
8951 
8952 /********************  Bits definition for RTC_WUTR register  *****************/
8953 #define RTC_WUTR_WUT_Pos             (0U)
8954 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
8955 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
8956 
8957 /********************  Bits definition for RTC_CR register  *******************/
8958 #define RTC_CR_OUT2EN_Pos            (31U)
8959 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
8960 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
8961 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
8962 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
8963 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
8964 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
8965 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
8966 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
8967 #define RTC_CR_TAMPOE_Pos            (26U)
8968 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
8969 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
8970 #define RTC_CR_TAMPTS_Pos            (25U)
8971 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
8972 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
8973 #define RTC_CR_ITSE_Pos              (24U)
8974 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
8975 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
8976 #define RTC_CR_COE_Pos               (23U)
8977 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
8978 #define RTC_CR_COE                   RTC_CR_COE_Msk
8979 #define RTC_CR_OSEL_Pos              (21U)
8980 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
8981 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
8982 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
8983 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
8984 #define RTC_CR_POL_Pos               (20U)
8985 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
8986 #define RTC_CR_POL                   RTC_CR_POL_Msk
8987 #define RTC_CR_COSEL_Pos             (19U)
8988 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
8989 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
8990 #define RTC_CR_BKP_Pos               (18U)
8991 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
8992 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
8993 #define RTC_CR_SUB1H_Pos             (17U)
8994 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
8995 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
8996 #define RTC_CR_ADD1H_Pos             (16U)
8997 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
8998 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
8999 #define RTC_CR_TSIE_Pos              (15U)
9000 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
9001 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
9002 #define RTC_CR_WUTIE_Pos             (14U)
9003 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
9004 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
9005 #define RTC_CR_ALRBIE_Pos            (13U)
9006 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
9007 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
9008 #define RTC_CR_ALRAIE_Pos            (12U)
9009 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
9010 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
9011 #define RTC_CR_TSE_Pos               (11U)
9012 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
9013 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
9014 #define RTC_CR_WUTE_Pos              (10U)
9015 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
9016 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
9017 #define RTC_CR_ALRBE_Pos             (9U)
9018 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
9019 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
9020 #define RTC_CR_ALRAE_Pos             (8U)
9021 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
9022 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
9023 #define RTC_CR_FMT_Pos               (6U)
9024 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
9025 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
9026 #define RTC_CR_BYPSHAD_Pos           (5U)
9027 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
9028 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
9029 #define RTC_CR_REFCKON_Pos           (4U)
9030 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
9031 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
9032 #define RTC_CR_TSEDGE_Pos            (3U)
9033 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
9034 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
9035 #define RTC_CR_WUCKSEL_Pos           (0U)
9036 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
9037 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
9038 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
9039 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
9040 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
9041 
9042 /********************  Bits definition for RTC_WPR register  ******************/
9043 #define RTC_WPR_KEY_Pos              (0U)
9044 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
9045 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
9046 
9047 /********************  Bits definition for RTC_CALR register  *****************/
9048 #define RTC_CALR_CALP_Pos            (15U)
9049 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
9050 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
9051 #define RTC_CALR_CALW8_Pos           (14U)
9052 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
9053 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
9054 #define RTC_CALR_CALW16_Pos          (13U)
9055 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
9056 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
9057 #define RTC_CALR_CALM_Pos            (0U)
9058 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
9059 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
9060 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
9061 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
9062 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
9063 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
9064 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
9065 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
9066 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
9067 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
9068 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
9069 
9070 /********************  Bits definition for RTC_SHIFTR register  ***************/
9071 #define RTC_SHIFTR_SUBFS_Pos         (0U)
9072 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
9073 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
9074 #define RTC_SHIFTR_ADD1S_Pos         (31U)
9075 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
9076 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
9077 
9078 /********************  Bits definition for RTC_TSTR register  *****************/
9079 #define RTC_TSTR_PM_Pos              (22U)
9080 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
9081 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
9082 #define RTC_TSTR_HT_Pos              (20U)
9083 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
9084 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
9085 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
9086 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
9087 #define RTC_TSTR_HU_Pos              (16U)
9088 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
9089 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
9090 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
9091 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
9092 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
9093 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
9094 #define RTC_TSTR_MNT_Pos             (12U)
9095 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
9096 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
9097 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
9098 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
9099 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
9100 #define RTC_TSTR_MNU_Pos             (8U)
9101 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
9102 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
9103 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
9104 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
9105 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
9106 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
9107 #define RTC_TSTR_ST_Pos              (4U)
9108 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
9109 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
9110 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
9111 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
9112 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
9113 #define RTC_TSTR_SU_Pos              (0U)
9114 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
9115 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
9116 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
9117 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
9118 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
9119 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
9120 
9121 /********************  Bits definition for RTC_TSDR register  *****************/
9122 #define RTC_TSDR_WDU_Pos             (13U)
9123 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
9124 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
9125 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
9126 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
9127 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
9128 #define RTC_TSDR_MT_Pos              (12U)
9129 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
9130 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
9131 #define RTC_TSDR_MU_Pos              (8U)
9132 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
9133 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
9134 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
9135 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
9136 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
9137 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
9138 #define RTC_TSDR_DT_Pos              (4U)
9139 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
9140 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
9141 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
9142 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
9143 #define RTC_TSDR_DU_Pos              (0U)
9144 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
9145 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
9146 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
9147 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
9148 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
9149 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
9150 
9151 /********************  Bits definition for RTC_TSSSR register  ****************/
9152 #define RTC_TSSSR_SS_Pos             (0U)
9153 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
9154 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
9155 
9156 /********************  Bits definition for RTC_ALRMAR register  ***************/
9157 #define RTC_ALRMAR_MSK4_Pos          (31U)
9158 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
9159 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
9160 #define RTC_ALRMAR_WDSEL_Pos         (30U)
9161 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
9162 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
9163 #define RTC_ALRMAR_DT_Pos            (28U)
9164 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
9165 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
9166 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
9167 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
9168 #define RTC_ALRMAR_DU_Pos            (24U)
9169 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
9170 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
9171 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
9172 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
9173 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
9174 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
9175 #define RTC_ALRMAR_MSK3_Pos          (23U)
9176 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
9177 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
9178 #define RTC_ALRMAR_PM_Pos            (22U)
9179 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
9180 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
9181 #define RTC_ALRMAR_HT_Pos            (20U)
9182 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
9183 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
9184 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
9185 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
9186 #define RTC_ALRMAR_HU_Pos            (16U)
9187 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
9188 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
9189 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
9190 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
9191 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
9192 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
9193 #define RTC_ALRMAR_MSK2_Pos          (15U)
9194 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
9195 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
9196 #define RTC_ALRMAR_MNT_Pos           (12U)
9197 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
9198 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
9199 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
9200 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
9201 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
9202 #define RTC_ALRMAR_MNU_Pos           (8U)
9203 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
9204 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
9205 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
9206 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
9207 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
9208 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
9209 #define RTC_ALRMAR_MSK1_Pos          (7U)
9210 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
9211 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
9212 #define RTC_ALRMAR_ST_Pos            (4U)
9213 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
9214 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
9215 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
9216 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
9217 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
9218 #define RTC_ALRMAR_SU_Pos            (0U)
9219 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
9220 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
9221 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
9222 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
9223 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
9224 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
9225 
9226 /********************  Bits definition for RTC_ALRMASSR register  *************/
9227 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
9228 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
9229 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
9230 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
9231 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
9232 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
9233 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
9234 #define RTC_ALRMASSR_SS_Pos          (0U)
9235 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
9236 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
9237 
9238 /********************  Bits definition for RTC_ALRMBR register  ***************/
9239 #define RTC_ALRMBR_MSK4_Pos          (31U)
9240 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
9241 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
9242 #define RTC_ALRMBR_WDSEL_Pos         (30U)
9243 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
9244 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
9245 #define RTC_ALRMBR_DT_Pos            (28U)
9246 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
9247 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
9248 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
9249 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
9250 #define RTC_ALRMBR_DU_Pos            (24U)
9251 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
9252 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
9253 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
9254 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
9255 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
9256 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
9257 #define RTC_ALRMBR_MSK3_Pos          (23U)
9258 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
9259 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
9260 #define RTC_ALRMBR_PM_Pos            (22U)
9261 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
9262 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
9263 #define RTC_ALRMBR_HT_Pos            (20U)
9264 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
9265 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
9266 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
9267 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
9268 #define RTC_ALRMBR_HU_Pos            (16U)
9269 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
9270 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
9271 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
9272 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
9273 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
9274 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
9275 #define RTC_ALRMBR_MSK2_Pos          (15U)
9276 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
9277 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
9278 #define RTC_ALRMBR_MNT_Pos           (12U)
9279 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
9280 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
9281 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
9282 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
9283 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
9284 #define RTC_ALRMBR_MNU_Pos           (8U)
9285 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
9286 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
9287 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
9288 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
9289 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
9290 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
9291 #define RTC_ALRMBR_MSK1_Pos          (7U)
9292 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
9293 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
9294 #define RTC_ALRMBR_ST_Pos            (4U)
9295 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
9296 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
9297 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
9298 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
9299 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
9300 #define RTC_ALRMBR_SU_Pos            (0U)
9301 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
9302 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
9303 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
9304 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
9305 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
9306 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
9307 
9308 /********************  Bits definition for RTC_ALRMASSR register  *************/
9309 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
9310 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
9311 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
9312 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
9313 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
9314 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
9315 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
9316 #define RTC_ALRMBSSR_SS_Pos          (0U)
9317 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
9318 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
9319 
9320 /********************  Bits definition for RTC_SR register  *******************/
9321 #define RTC_SR_ITSF_Pos              (5U)
9322 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
9323 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
9324 #define RTC_SR_TSOVF_Pos             (4U)
9325 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
9326 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
9327 #define RTC_SR_TSF_Pos               (3U)
9328 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
9329 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
9330 #define RTC_SR_WUTF_Pos              (2U)
9331 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
9332 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
9333 #define RTC_SR_ALRBF_Pos             (1U)
9334 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
9335 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
9336 #define RTC_SR_ALRAF_Pos             (0U)
9337 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
9338 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
9339 
9340 /********************  Bits definition for RTC_MISR register  *****************/
9341 #define RTC_MISR_ITSMF_Pos           (5U)
9342 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
9343 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
9344 #define RTC_MISR_TSOVMF_Pos          (4U)
9345 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
9346 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
9347 #define RTC_MISR_TSMF_Pos            (3U)
9348 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
9349 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
9350 #define RTC_MISR_WUTMF_Pos           (2U)
9351 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
9352 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
9353 #define RTC_MISR_ALRBMF_Pos          (1U)
9354 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
9355 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
9356 #define RTC_MISR_ALRAMF_Pos          (0U)
9357 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
9358 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
9359 
9360 /********************  Bits definition for RTC_SCR register  ******************/
9361 #define RTC_SCR_CITSF_Pos            (5U)
9362 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
9363 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
9364 #define RTC_SCR_CTSOVF_Pos           (4U)
9365 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
9366 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
9367 #define RTC_SCR_CTSF_Pos             (3U)
9368 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
9369 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
9370 #define RTC_SCR_CWUTF_Pos            (2U)
9371 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
9372 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
9373 #define RTC_SCR_CALRBF_Pos           (1U)
9374 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
9375 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
9376 #define RTC_SCR_CALRAF_Pos           (0U)
9377 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
9378 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
9379 
9380 /******************************************************************************/
9381 /*                                                                            */
9382 /*                     Tamper and backup register (TAMP)                      */
9383 /*                                                                            */
9384 /******************************************************************************/
9385 /********************  Bits definition for TAMP_CR1 register  *****************/
9386 #define TAMP_CR1_TAMP1E_Pos          (0U)
9387 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
9388 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
9389 #define TAMP_CR1_TAMP2E_Pos          (1U)
9390 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
9391 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
9392 #define TAMP_CR1_TAMP3E_Pos          (2U)
9393 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
9394 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
9395 #define TAMP_CR1_ITAMP3E_Pos         (18U)
9396 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
9397 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
9398 #define TAMP_CR1_ITAMP4E_Pos         (19U)
9399 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
9400 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
9401 #define TAMP_CR1_ITAMP5E_Pos         (20U)
9402 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
9403 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
9404 #define TAMP_CR1_ITAMP6E_Pos         (21U)
9405 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
9406 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
9407 
9408 /********************  Bits definition for TAMP_CR2 register  *****************/
9409 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
9410 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
9411 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
9412 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
9413 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
9414 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
9415 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
9416 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
9417 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
9418 #define TAMP_CR2_TAMP1MSK_Pos         (16U)
9419 #define TAMP_CR2_TAMP1MSK_Msk         (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
9420 #define TAMP_CR2_TAMP1MSK             TAMP_CR2_TAMP1MSK_Msk
9421 #define TAMP_CR2_TAMP2MSK_Pos         (17U)
9422 #define TAMP_CR2_TAMP2MSK_Msk         (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
9423 #define TAMP_CR2_TAMP2MSK             TAMP_CR2_TAMP2MSK_Msk
9424 #define TAMP_CR2_TAMP3MSK_Pos         (18U)
9425 #define TAMP_CR2_TAMP3MSK_Msk         (0x1UL << TAMP_CR2_TAMP3MSK_Pos)           /*!< 0x00040000 */
9426 #define TAMP_CR2_TAMP3MSK             TAMP_CR2_TAMP3MSK_Msk
9427 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
9428 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
9429 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
9430 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
9431 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
9432 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
9433 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
9434 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
9435 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
9436 
9437 /* Legacy aliases */
9438 #define TAMP_CR2_TAMP1MF_Pos            TAMP_CR2_TAMP1MSK_Pos
9439 #define TAMP_CR2_TAMP1MF_Msk            TAMP_CR2_TAMP1MSK_Msk
9440 #define TAMP_CR2_TAMP1MF                TAMP_CR2_TAMP1MSK
9441 #define TAMP_CR2_TAMP2MF_Pos            TAMP_CR2_TAMP2MSK_Pos
9442 #define TAMP_CR2_TAMP2MF_Msk            TAMP_CR2_TAMP2MSK_Msk
9443 #define TAMP_CR2_TAMP2MF                TAMP_CR2_TAMP2MSK
9444 #define TAMP_CR2_TAMP3MF_Pos            TAMP_CR2_TAMP3MSK_Pos
9445 #define TAMP_CR2_TAMP3MF_Msk            TAMP_CR2_TAMP3MSK_Msk
9446 #define TAMP_CR2_TAMP3MF                TAMP_CR2_TAMP3MSK
9447 
9448 /********************  Bits definition for TAMP_FLTCR register  ***************/
9449 #define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
9450 #define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
9451 #define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
9452 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
9453 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
9454 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
9455 #define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
9456 #define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
9457 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
9458 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
9459 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
9460 #define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
9461 #define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
9462 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
9463 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
9464 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
9465 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
9466 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
9467 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
9468 
9469 /********************  Bits definition for TAMP_IER register  *****************/
9470 #define TAMP_IER_TAMP1IE_Pos         (0U)
9471 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
9472 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
9473 #define TAMP_IER_TAMP2IE_Pos         (1U)
9474 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
9475 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
9476 #define TAMP_IER_TAMP3IE_Pos         (2U)
9477 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
9478 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
9479 #define TAMP_IER_ITAMP3IE_Pos        (18U)
9480 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
9481 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
9482 #define TAMP_IER_ITAMP4IE_Pos        (19U)
9483 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
9484 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
9485 #define TAMP_IER_ITAMP5IE_Pos        (20U)
9486 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
9487 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
9488 #define TAMP_IER_ITAMP6IE_Pos        (21U)
9489 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
9490 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
9491 
9492 /********************  Bits definition for TAMP_SR register  ******************/
9493 #define TAMP_SR_TAMP1F_Pos           (0U)
9494 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
9495 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
9496 #define TAMP_SR_TAMP2F_Pos           (1U)
9497 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
9498 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
9499 #define TAMP_SR_TAMP3F_Pos           (2U)
9500 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
9501 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
9502 #define TAMP_SR_ITAMP3F_Pos          (18U)
9503 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
9504 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
9505 #define TAMP_SR_ITAMP4F_Pos          (19U)
9506 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
9507 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
9508 #define TAMP_SR_ITAMP5F_Pos          (20U)
9509 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
9510 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
9511 #define TAMP_SR_ITAMP6F_Pos          (21U)
9512 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
9513 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
9514 
9515 /********************  Bits definition for TAMP_MISR register  ****************/
9516 #define TAMP_MISR_TAMP1MF_Pos        (0U)
9517 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
9518 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
9519 #define TAMP_MISR_TAMP2MF_Pos        (1U)
9520 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
9521 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
9522 #define TAMP_MISR_TAMP3MF_Pos        (2U)
9523 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
9524 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
9525 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
9526 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
9527 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
9528 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
9529 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
9530 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
9531 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
9532 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
9533 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
9534 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
9535 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
9536 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
9537 
9538 /********************  Bits definition for TAMP_SCR register  *****************/
9539 #define TAMP_SCR_CTAMP1F_Pos         (0U)
9540 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
9541 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
9542 #define TAMP_SCR_CTAMP2F_Pos         (1U)
9543 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
9544 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
9545 #define TAMP_SCR_CTAMP3F_Pos         (2U)
9546 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
9547 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
9548 #define TAMP_SCR_CITAMP3F_Pos        (18U)
9549 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
9550 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
9551 #define TAMP_SCR_CITAMP4F_Pos        (19U)
9552 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
9553 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
9554 #define TAMP_SCR_CITAMP5F_Pos        (20U)
9555 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
9556 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
9557 #define TAMP_SCR_CITAMP6F_Pos        (21U)
9558 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
9559 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
9560 
9561 /********************  Bits definition for TAMP_BKP0R register  ***************/
9562 #define TAMP_BKP0R_Pos               (0U)
9563 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
9564 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
9565 
9566 /********************  Bits definition for TAMP_BKP1R register  ***************/
9567 #define TAMP_BKP1R_Pos               (0U)
9568 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
9569 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
9570 
9571 /********************  Bits definition for TAMP_BKP2R register  ***************/
9572 #define TAMP_BKP2R_Pos               (0U)
9573 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
9574 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
9575 
9576 /********************  Bits definition for TAMP_BKP3R register  ***************/
9577 #define TAMP_BKP3R_Pos               (0U)
9578 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
9579 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
9580 
9581 /********************  Bits definition for TAMP_BKP4R register  ***************/
9582 #define TAMP_BKP4R_Pos               (0U)
9583 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
9584 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
9585 
9586 /********************  Bits definition for TAMP_BKP5R register  ***************/
9587 #define TAMP_BKP5R_Pos               (0U)
9588 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
9589 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
9590 
9591 /********************  Bits definition for TAMP_BKP6R register  ***************/
9592 #define TAMP_BKP6R_Pos               (0U)
9593 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
9594 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
9595 
9596 /********************  Bits definition for TAMP_BKP7R register  ***************/
9597 #define TAMP_BKP7R_Pos               (0U)
9598 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
9599 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
9600 
9601 /********************  Bits definition for TAMP_BKP8R register  ***************/
9602 #define TAMP_BKP8R_Pos               (0U)
9603 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
9604 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
9605 
9606 /********************  Bits definition for TAMP_BKP9R register  ***************/
9607 #define TAMP_BKP9R_Pos               (0U)
9608 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
9609 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
9610 
9611 /********************  Bits definition for TAMP_BKP10R register  ***************/
9612 #define TAMP_BKP10R_Pos               (0U)
9613 #define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
9614 #define TAMP_BKP10R                   TAMP_BKP10R_Msk
9615 
9616 /********************  Bits definition for TAMP_BKP11R register  ***************/
9617 #define TAMP_BKP11R_Pos               (0U)
9618 #define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
9619 #define TAMP_BKP11R                   TAMP_BKP11R_Msk
9620 
9621 /********************  Bits definition for TAMP_BKP12R register  ***************/
9622 #define TAMP_BKP12R_Pos               (0U)
9623 #define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
9624 #define TAMP_BKP12R                   TAMP_BKP12R_Msk
9625 
9626 /********************  Bits definition for TAMP_BKP13R register  ***************/
9627 #define TAMP_BKP13R_Pos               (0U)
9628 #define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
9629 #define TAMP_BKP13R                   TAMP_BKP13R_Msk
9630 
9631 /********************  Bits definition for TAMP_BKP14R register  ***************/
9632 #define TAMP_BKP14R_Pos               (0U)
9633 #define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
9634 #define TAMP_BKP14R                   TAMP_BKP14R_Msk
9635 
9636 /********************  Bits definition for TAMP_BKP15R register  ***************/
9637 #define TAMP_BKP15R_Pos               (0U)
9638 #define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
9639 #define TAMP_BKP15R                   TAMP_BKP15R_Msk
9640 
9641 /********************  Bits definition for TAMP_BKP16R register  ***************/
9642 #define TAMP_BKP16R_Pos               (0U)
9643 #define TAMP_BKP16R_Msk               (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
9644 #define TAMP_BKP16R                   TAMP_BKP16R_Msk
9645 
9646 /********************  Bits definition for TAMP_BKP17R register  ***************/
9647 #define TAMP_BKP17R_Pos               (0U)
9648 #define TAMP_BKP17R_Msk               (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
9649 #define TAMP_BKP17R                   TAMP_BKP17R_Msk
9650 
9651 /********************  Bits definition for TAMP_BKP18R register  ***************/
9652 #define TAMP_BKP18R_Pos               (0U)
9653 #define TAMP_BKP18R_Msk               (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
9654 #define TAMP_BKP18R                   TAMP_BKP18R_Msk
9655 
9656 /********************  Bits definition for TAMP_BKP19R register  ***************/
9657 #define TAMP_BKP19R_Pos               (0U)
9658 #define TAMP_BKP19R_Msk               (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
9659 #define TAMP_BKP19R                   TAMP_BKP19R_Msk
9660 
9661 /********************  Bits definition for TAMP_BKP20R register  ***************/
9662 #define TAMP_BKP20R_Pos               (0U)
9663 #define TAMP_BKP20R_Msk               (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
9664 #define TAMP_BKP20R                   TAMP_BKP20R_Msk
9665 
9666 /********************  Bits definition for TAMP_BKP21R register  ***************/
9667 #define TAMP_BKP21R_Pos               (0U)
9668 #define TAMP_BKP21R_Msk               (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
9669 #define TAMP_BKP21R                   TAMP_BKP21R_Msk
9670 
9671 /********************  Bits definition for TAMP_BKP22R register  ***************/
9672 #define TAMP_BKP22R_Pos               (0U)
9673 #define TAMP_BKP22R_Msk               (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
9674 #define TAMP_BKP22R                   TAMP_BKP22R_Msk
9675 
9676 /********************  Bits definition for TAMP_BKP23R register  ***************/
9677 #define TAMP_BKP23R_Pos               (0U)
9678 #define TAMP_BKP23R_Msk               (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
9679 #define TAMP_BKP23R                   TAMP_BKP23R_Msk
9680 
9681 /********************  Bits definition for TAMP_BKP24R register  ***************/
9682 #define TAMP_BKP24R_Pos               (0U)
9683 #define TAMP_BKP24R_Msk               (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
9684 #define TAMP_BKP24R                   TAMP_BKP24R_Msk
9685 
9686 /********************  Bits definition for TAMP_BKP25R register  ***************/
9687 #define TAMP_BKP25R_Pos               (0U)
9688 #define TAMP_BKP25R_Msk               (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
9689 #define TAMP_BKP25R                   TAMP_BKP25R_Msk
9690 
9691 /********************  Bits definition for TAMP_BKP26R register  ***************/
9692 #define TAMP_BKP26R_Pos               (0U)
9693 #define TAMP_BKP26R_Msk               (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
9694 #define TAMP_BKP26R                   TAMP_BKP26R_Msk
9695 
9696 /********************  Bits definition for TAMP_BKP27R register  ***************/
9697 #define TAMP_BKP27R_Pos               (0U)
9698 #define TAMP_BKP27R_Msk               (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
9699 #define TAMP_BKP27R                   TAMP_BKP27R_Msk
9700 
9701 /********************  Bits definition for TAMP_BKP28R register  ***************/
9702 #define TAMP_BKP28R_Pos               (0U)
9703 #define TAMP_BKP28R_Msk               (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
9704 #define TAMP_BKP28R                   TAMP_BKP28R_Msk
9705 
9706 /********************  Bits definition for TAMP_BKP29R register  ***************/
9707 #define TAMP_BKP29R_Pos               (0U)
9708 #define TAMP_BKP29R_Msk               (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
9709 #define TAMP_BKP29R                   TAMP_BKP29R_Msk
9710 
9711 /********************  Bits definition for TAMP_BKP30R register  ***************/
9712 #define TAMP_BKP30R_Pos               (0U)
9713 #define TAMP_BKP30R_Msk               (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
9714 #define TAMP_BKP30R                   TAMP_BKP30R_Msk
9715 
9716 /********************  Bits definition for TAMP_BKP31R register  ***************/
9717 #define TAMP_BKP31R_Pos               (0U)
9718 #define TAMP_BKP31R_Msk               (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
9719 #define TAMP_BKP31R                   TAMP_BKP31R_Msk
9720 
9721 
9722 /******************************************************************************/
9723 /*                                                                            */
9724 /*                          Serial Audio Interface                            */
9725 /*                                                                            */
9726 /******************************************************************************/
9727 /*******************  Bit definition for SAI_xCR1 register  *******************/
9728 #define SAI_xCR1_MODE_Pos          (0U)
9729 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
9730 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
9731 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */
9732 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */
9733 
9734 #define SAI_xCR1_PRTCFG_Pos        (2U)
9735 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
9736 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
9737 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */
9738 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */
9739 
9740 #define SAI_xCR1_DS_Pos            (5U)
9741 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
9742 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
9743 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */
9744 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */
9745 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */
9746 
9747 #define SAI_xCR1_LSBFIRST_Pos      (8U)
9748 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
9749 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
9750 #define SAI_xCR1_CKSTR_Pos         (9U)
9751 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
9752 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
9753 
9754 #define SAI_xCR1_SYNCEN_Pos        (10U)
9755 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
9756 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
9757 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */
9758 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */
9759 
9760 #define SAI_xCR1_MONO_Pos          (12U)
9761 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
9762 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
9763 #define SAI_xCR1_OUTDRIV_Pos       (13U)
9764 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
9765 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
9766 #define SAI_xCR1_SAIEN_Pos         (16U)
9767 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
9768 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
9769 #define SAI_xCR1_DMAEN_Pos         (17U)
9770 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
9771 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
9772 #define SAI_xCR1_NODIV_Pos         (19U)
9773 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
9774 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
9775 
9776 #define SAI_xCR1_MCKDIV_Pos        (20U)
9777 #define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
9778 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
9779 #define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
9780 #define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
9781 #define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
9782 #define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
9783 #define SAI_xCR1_MCKDIV_4          (0x01000000U)                               /*!<Bit 4  */
9784 #define SAI_xCR1_MCKDIV_5          (0x02000000U)                               /*!<Bit 5  */
9785 
9786 #define SAI_xCR1_OSR_Pos           (26U)
9787 #define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
9788 #define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<Oversampling ratio for master clock */
9789 
9790 #define SAI_xCR1_MCKEN_Pos         (27U)
9791 #define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
9792 #define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master clock generation enable */
9793 
9794 /*******************  Bit definition for SAI_xCR2 register  *******************/
9795 #define SAI_xCR2_FTH_Pos           (0U)
9796 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
9797 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
9798 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */
9799 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */
9800 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */
9801 
9802 #define SAI_xCR2_FFLUSH_Pos        (3U)
9803 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
9804 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
9805 #define SAI_xCR2_TRIS_Pos          (4U)
9806 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
9807 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
9808 #define SAI_xCR2_MUTE_Pos          (5U)
9809 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
9810 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
9811 #define SAI_xCR2_MUTEVAL_Pos       (6U)
9812 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
9813 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
9814 
9815 
9816 #define SAI_xCR2_MUTECNT_Pos       (7U)
9817 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
9818 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
9819 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */
9820 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */
9821 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */
9822 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */
9823 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */
9824 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */
9825 
9826 #define SAI_xCR2_CPL_Pos           (13U)
9827 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
9828 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
9829 #define SAI_xCR2_COMP_Pos          (14U)
9830 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
9831 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
9832 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */
9833 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */
9834 
9835 
9836 /******************  Bit definition for SAI_xFRCR register  *******************/
9837 #define SAI_xFRCR_FRL_Pos          (0U)
9838 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
9839 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
9840 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */
9841 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */
9842 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */
9843 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */
9844 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */
9845 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */
9846 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */
9847 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */
9848 
9849 #define SAI_xFRCR_FSALL_Pos        (8U)
9850 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
9851 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
9852 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */
9853 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */
9854 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */
9855 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */
9856 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */
9857 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */
9858 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */
9859 
9860 #define SAI_xFRCR_FSDEF_Pos        (16U)
9861 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
9862 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
9863 #define SAI_xFRCR_FSPOL_Pos        (17U)
9864 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
9865 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
9866 #define SAI_xFRCR_FSOFF_Pos        (18U)
9867 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
9868 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
9869 
9870 /******************  Bit definition for SAI_xSLOTR register  *******************/
9871 #define SAI_xSLOTR_FBOFF_Pos       (0U)
9872 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
9873 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
9874 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */
9875 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */
9876 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */
9877 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */
9878 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */
9879 
9880 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
9881 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
9882 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
9883 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */
9884 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */
9885 
9886 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
9887 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
9888 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
9889 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */
9890 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */
9891 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */
9892 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */
9893 
9894 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
9895 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
9896 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
9897 
9898 /*******************  Bit definition for SAI_xIMR register  *******************/
9899 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
9900 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
9901 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
9902 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
9903 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
9904 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
9905 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
9906 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
9907 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
9908 #define SAI_xIMR_FREQIE_Pos        (3U)
9909 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
9910 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
9911 #define SAI_xIMR_CNRDYIE_Pos       (4U)
9912 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
9913 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
9914 #define SAI_xIMR_AFSDETIE_Pos      (5U)
9915 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
9916 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
9917 #define SAI_xIMR_LFSDETIE_Pos      (6U)
9918 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
9919 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
9920 
9921 /********************  Bit definition for SAI_xSR register  *******************/
9922 #define SAI_xSR_OVRUDR_Pos         (0U)
9923 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
9924 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
9925 #define SAI_xSR_MUTEDET_Pos        (1U)
9926 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
9927 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
9928 #define SAI_xSR_WCKCFG_Pos         (2U)
9929 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
9930 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
9931 #define SAI_xSR_FREQ_Pos           (3U)
9932 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
9933 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
9934 #define SAI_xSR_CNRDY_Pos          (4U)
9935 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
9936 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
9937 #define SAI_xSR_AFSDET_Pos         (5U)
9938 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
9939 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
9940 #define SAI_xSR_LFSDET_Pos         (6U)
9941 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
9942 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
9943 
9944 #define SAI_xSR_FLVL_Pos           (16U)
9945 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
9946 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
9947 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */
9948 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */
9949 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */
9950 
9951 /******************  Bit definition for SAI_xCLRFR register  ******************/
9952 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
9953 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
9954 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
9955 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
9956 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
9957 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
9958 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
9959 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
9960 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
9961 #define SAI_xCLRFR_CFREQ_Pos       (3U)
9962 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
9963 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
9964 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
9965 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
9966 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
9967 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
9968 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
9969 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
9970 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
9971 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
9972 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
9973 
9974 /******************  Bit definition for SAI_xDR register  ******************/
9975 #define SAI_xDR_DATA_Pos           (0U)
9976 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
9977 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
9978 
9979 /******************  Bit definition for SAI_PDMCR register  *******************/
9980 #define SAI_PDMCR_PDMEN_Pos        (0U)
9981 #define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
9982 #define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM enable */
9983 
9984 #define SAI_PDMCR_MICNBR_Pos       (4U)
9985 #define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
9986 #define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<MICNBR[1:0] (Number of microphones) */
9987 #define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000010 */
9988 #define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000020 */
9989 
9990 #define SAI_PDMCR_CKEN1_Pos        (8U)
9991 #define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
9992 #define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock 1 enable */
9993 #define SAI_PDMCR_CKEN2_Pos        (9U)
9994 #define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
9995 #define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock 2 enable */
9996 #define SAI_PDMCR_CKEN3_Pos        (10U)
9997 #define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
9998 #define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock 3 enable */
9999 #define SAI_PDMCR_CKEN4_Pos        (11U)
10000 #define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
10001 #define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock 4 enable */
10002 
10003 /******************  Bit definition for SAI_PDMDLY register  ******************/
10004 #define SAI_PDMDLY_DLYM1L_Pos      (0U)
10005 #define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
10006 #define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
10007 #define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000001 */
10008 #define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000002 */
10009 #define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000004 */
10010 
10011 #define SAI_PDMDLY_DLYM1R_Pos      (4U)
10012 #define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
10013 #define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
10014 #define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000010 */
10015 #define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000020 */
10016 #define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000040 */
10017 
10018 #define SAI_PDMDLY_DLYM2L_Pos      (8U)
10019 #define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
10020 #define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
10021 #define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000100 */
10022 #define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000200 */
10023 #define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000400 */
10024 
10025 #define SAI_PDMDLY_DLYM2R_Pos      (12U)
10026 #define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
10027 #define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
10028 #define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00001000 */
10029 #define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00002000 */
10030 #define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00004000 */
10031 
10032 #define SAI_PDMDLY_DLYM3L_Pos      (16U)
10033 #define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
10034 #define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
10035 #define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00010000 */
10036 #define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00020000 */
10037 #define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00040000 */
10038 
10039 #define SAI_PDMDLY_DLYM3R_Pos      (20U)
10040 #define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
10041 #define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
10042 #define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00100000 */
10043 #define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00200000 */
10044 #define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00400000 */
10045 
10046 #define SAI_PDMDLY_DLYM4L_Pos      (24U)
10047 #define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
10048 #define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
10049 #define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x01000000 */
10050 #define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x02000000 */
10051 #define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x04000000 */
10052 
10053 #define SAI_PDMDLY_DLYM4R_Pos      (28U)
10054 #define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
10055 #define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
10056 #define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x10000000 */
10057 #define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x20000000 */
10058 #define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x40000000 */
10059 
10060 
10061 /******************************************************************************/
10062 /*                                                                            */
10063 /*                        Serial Peripheral Interface (SPI)                   */
10064 /*                                                                            */
10065 /******************************************************************************/
10066 /*
10067  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
10068  */
10069 #define SPI_I2S_SUPPORT                       /*!< I2S support */
10070 
10071 /*******************  Bit definition for SPI_CR1 register  ********************/
10072 #define SPI_CR1_CPHA_Pos            (0U)
10073 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
10074 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
10075 #define SPI_CR1_CPOL_Pos            (1U)
10076 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
10077 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
10078 #define SPI_CR1_MSTR_Pos            (2U)
10079 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
10080 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
10081 
10082 #define SPI_CR1_BR_Pos              (3U)
10083 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
10084 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
10085 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
10086 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
10087 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
10088 
10089 #define SPI_CR1_SPE_Pos             (6U)
10090 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
10091 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
10092 #define SPI_CR1_LSBFIRST_Pos        (7U)
10093 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
10094 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
10095 #define SPI_CR1_SSI_Pos             (8U)
10096 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
10097 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
10098 #define SPI_CR1_SSM_Pos             (9U)
10099 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
10100 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
10101 #define SPI_CR1_RXONLY_Pos          (10U)
10102 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
10103 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
10104 #define SPI_CR1_CRCL_Pos            (11U)
10105 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
10106 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
10107 #define SPI_CR1_CRCNEXT_Pos         (12U)
10108 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
10109 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
10110 #define SPI_CR1_CRCEN_Pos           (13U)
10111 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
10112 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
10113 #define SPI_CR1_BIDIOE_Pos          (14U)
10114 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
10115 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
10116 #define SPI_CR1_BIDIMODE_Pos        (15U)
10117 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
10118 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
10119 
10120 /*******************  Bit definition for SPI_CR2 register  ********************/
10121 #define SPI_CR2_RXDMAEN_Pos         (0U)
10122 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
10123 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
10124 #define SPI_CR2_TXDMAEN_Pos         (1U)
10125 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
10126 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
10127 #define SPI_CR2_SSOE_Pos            (2U)
10128 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
10129 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
10130 #define SPI_CR2_NSSP_Pos            (3U)
10131 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
10132 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
10133 #define SPI_CR2_FRF_Pos             (4U)
10134 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
10135 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
10136 #define SPI_CR2_ERRIE_Pos           (5U)
10137 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
10138 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
10139 #define SPI_CR2_RXNEIE_Pos          (6U)
10140 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
10141 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
10142 #define SPI_CR2_TXEIE_Pos           (7U)
10143 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
10144 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
10145 #define SPI_CR2_DS_Pos              (8U)
10146 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
10147 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
10148 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
10149 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
10150 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
10151 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
10152 #define SPI_CR2_FRXTH_Pos           (12U)
10153 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
10154 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
10155 #define SPI_CR2_LDMARX_Pos          (13U)
10156 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
10157 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
10158 #define SPI_CR2_LDMATX_Pos          (14U)
10159 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
10160 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
10161 
10162 /********************  Bit definition for SPI_SR register  ********************/
10163 #define SPI_SR_RXNE_Pos             (0U)
10164 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
10165 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
10166 #define SPI_SR_TXE_Pos              (1U)
10167 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
10168 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
10169 #define SPI_SR_CHSIDE_Pos           (2U)
10170 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
10171 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
10172 #define SPI_SR_UDR_Pos              (3U)
10173 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
10174 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
10175 #define SPI_SR_CRCERR_Pos           (4U)
10176 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
10177 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
10178 #define SPI_SR_MODF_Pos             (5U)
10179 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
10180 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
10181 #define SPI_SR_OVR_Pos              (6U)
10182 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
10183 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
10184 #define SPI_SR_BSY_Pos              (7U)
10185 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
10186 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
10187 #define SPI_SR_FRE_Pos              (8U)
10188 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
10189 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
10190 #define SPI_SR_FRLVL_Pos            (9U)
10191 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
10192 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
10193 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
10194 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
10195 #define SPI_SR_FTLVL_Pos            (11U)
10196 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
10197 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
10198 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
10199 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
10200 
10201 /********************  Bit definition for SPI_DR register  ********************/
10202 #define SPI_DR_DR_Pos               (0U)
10203 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
10204 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
10205 
10206 /*******************  Bit definition for SPI_CRCPR register  ******************/
10207 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
10208 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
10209 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
10210 
10211 /******************  Bit definition for SPI_RXCRCR register  ******************/
10212 #define SPI_RXCRCR_RXCRC_Pos        (0U)
10213 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
10214 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
10215 
10216 /******************  Bit definition for SPI_TXCRCR register  ******************/
10217 #define SPI_TXCRCR_TXCRC_Pos        (0U)
10218 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
10219 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
10220 
10221 /******************  Bit definition for SPI_I2SCFGR register  *****************/
10222 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
10223 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
10224 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
10225 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
10226 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
10227 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
10228 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
10229 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
10230 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
10231 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
10232 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
10233 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
10234 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
10235 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
10236 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
10237 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
10238 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
10239 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
10240 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
10241 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
10242 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
10243 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
10244 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
10245 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
10246 #define SPI_I2SCFGR_I2SE_Pos        (10U)
10247 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
10248 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
10249 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
10250 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
10251 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
10252 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
10253 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
10254 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
10255 
10256 /******************  Bit definition for SPI_I2SPR register  *******************/
10257 #define SPI_I2SPR_I2SDIV_Pos        (0U)
10258 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
10259 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
10260 #define SPI_I2SPR_ODD_Pos           (8U)
10261 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
10262 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
10263 #define SPI_I2SPR_MCKOE_Pos         (9U)
10264 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
10265 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
10266 
10267 /******************************************************************************/
10268 /*                                                                            */
10269 /*                                 SYSCFG                                     */
10270 /*                                                                            */
10271 /******************************************************************************/
10272 /******************  Bit definition for SYSCFG_MEMRMP register ***************/
10273 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
10274 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
10275 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
10276 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
10277 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
10278 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
10279 
10280 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
10281 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
10282 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
10283 
10284 /******************  Bit definition for SYSCFG_CFGR1 register ******************/
10285 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
10286 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
10287 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
10288 #define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
10289 #define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
10290 #define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
10291 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
10292 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
10293 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
10294 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
10295 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
10296 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
10297 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
10298 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
10299 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
10300 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
10301 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
10302 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
10303 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
10304 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
10305 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
10306 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
10307 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
10308 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
10309 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
10310 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
10311 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
10312 #define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)
10313 #define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos)   /*!< 0x00800000 */
10314 #define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */
10315 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
10316 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
10317 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
10318 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
10319 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
10320 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
10321 
10322 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
10323 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
10324 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
10325 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
10326 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
10327 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
10328 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
10329 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
10330 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
10331 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
10332 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
10333 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
10334 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
10335 
10336 /**
10337   * @brief   EXTI0 configuration
10338   */
10339 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
10340 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
10341 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
10342 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
10343 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
10344 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
10345 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
10346 
10347 /**
10348   * @brief   EXTI1 configuration
10349   */
10350 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
10351 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
10352 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
10353 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
10354 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
10355 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
10356 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
10357 
10358 /**
10359   * @brief   EXTI2 configuration
10360   */
10361 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
10362 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
10363 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
10364 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
10365 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
10366 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
10367 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
10368 
10369 /**
10370   * @brief   EXTI3 configuration
10371   */
10372 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
10373 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
10374 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
10375 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
10376 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
10377 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
10378 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
10379 
10380 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
10381 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
10382 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
10383 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
10384 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
10385 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
10386 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
10387 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
10388 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
10389 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
10390 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
10391 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
10392 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
10393 
10394 /**
10395   * @brief   EXTI4 configuration
10396   */
10397 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
10398 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
10399 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
10400 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
10401 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
10402 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
10403 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
10404 
10405 /**
10406   * @brief   EXTI5 configuration
10407   */
10408 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
10409 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
10410 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
10411 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
10412 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
10413 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
10414 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
10415 
10416 /**
10417   * @brief   EXTI6 configuration
10418   */
10419 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
10420 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
10421 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
10422 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
10423 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
10424 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
10425 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
10426 
10427 /**
10428   * @brief   EXTI7 configuration
10429   */
10430 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
10431 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
10432 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
10433 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
10434 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
10435 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
10436 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
10437 
10438 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
10439 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
10440 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
10441 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
10442 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
10443 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
10444 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
10445 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
10446 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
10447 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
10448 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
10449 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
10450 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
10451 
10452 /**
10453   * @brief   EXTI8 configuration
10454   */
10455 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
10456 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
10457 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
10458 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
10459 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
10460 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
10461 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
10462 
10463 /**
10464   * @brief   EXTI9 configuration
10465   */
10466 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
10467 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
10468 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
10469 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
10470 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
10471 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
10472 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
10473 
10474 /**
10475   * @brief   EXTI10 configuration
10476   */
10477 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
10478 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
10479 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
10480 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
10481 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
10482 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
10483 
10484 /**
10485   * @brief   EXTI11 configuration
10486   */
10487 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
10488 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
10489 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
10490 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
10491 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
10492 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
10493 
10494 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
10495 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
10496 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
10497 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
10498 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
10499 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
10500 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
10501 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
10502 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
10503 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
10504 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
10505 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
10506 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
10507 
10508 /**
10509   * @brief   EXTI12 configuration
10510   */
10511 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
10512 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
10513 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
10514 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
10515 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
10516 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
10517 
10518 /**
10519   * @brief   EXTI13 configuration
10520   */
10521 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
10522 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
10523 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
10524 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
10525 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
10526 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
10527 
10528 /**
10529   * @brief   EXTI14 configuration
10530   */
10531 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
10532 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
10533 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
10534 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
10535 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
10536 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
10537 
10538 /**
10539   * @brief   EXTI15 configuration
10540   */
10541 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
10542 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
10543 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
10544 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
10545 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
10546 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
10547 
10548 /******************  Bit definition for SYSCFG_SCSR register  ****************/
10549 #define SYSCFG_SCSR_CCMER_Pos         (0U)
10550 #define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
10551 #define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
10552 #define SYSCFG_SCSR_CCMBSY_Pos        (1U)
10553 #define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
10554 #define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
10555 
10556 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
10557 #define SYSCFG_CFGR2_CLL_Pos            (0U)
10558 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
10559 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
10560 #define SYSCFG_CFGR2_SPL_Pos            (1U)
10561 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
10562 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
10563 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
10564 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
10565 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
10566 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
10567 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
10568 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
10569 #define SYSCFG_CFGR2_SPF_Pos            (8U)
10570 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
10571 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
10572 
10573 /******************  Bit definition for SYSCFG_SWPR register  ****************/
10574 #define SYSCFG_SWPR_PAGE0_Pos          (0U)
10575 #define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
10576 #define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
10577 #define SYSCFG_SWPR_PAGE1_Pos          (1U)
10578 #define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
10579 #define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
10580 #define SYSCFG_SWPR_PAGE2_Pos          (2U)
10581 #define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
10582 #define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
10583 #define SYSCFG_SWPR_PAGE3_Pos          (3U)
10584 #define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
10585 #define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
10586 #define SYSCFG_SWPR_PAGE4_Pos          (4U)
10587 #define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
10588 #define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
10589 #define SYSCFG_SWPR_PAGE5_Pos          (5U)
10590 #define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
10591 #define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
10592 #define SYSCFG_SWPR_PAGE6_Pos          (6U)
10593 #define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
10594 #define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
10595 #define SYSCFG_SWPR_PAGE7_Pos          (7U)
10596 #define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
10597 #define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
10598 #define SYSCFG_SWPR_PAGE8_Pos          (8U)
10599 #define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
10600 #define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
10601 #define SYSCFG_SWPR_PAGE9_Pos          (9U)
10602 #define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
10603 #define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
10604 #define SYSCFG_SWPR_PAGE10_Pos         (10U)
10605 #define SYSCFG_SWPR_PAGE10_Msk         (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
10606 #define SYSCFG_SWPR_PAGE10             (SYSCFG_SWPR_PAGE10_Msk)               /*!< CCMSRAM  Write protection page 10*/
10607 #define SYSCFG_SWPR_PAGE11_Pos         (11U)
10608 #define SYSCFG_SWPR_PAGE11_Msk         (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
10609 #define SYSCFG_SWPR_PAGE11             (SYSCFG_SWPR_PAGE11_Msk)               /*!< CCMSRAM  Write protection page 11*/
10610 #define SYSCFG_SWPR_PAGE12_Pos         (12U)
10611 #define SYSCFG_SWPR_PAGE12_Msk         (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
10612 #define SYSCFG_SWPR_PAGE12             (SYSCFG_SWPR_PAGE12_Msk)               /*!< CCMSRAM  Write protection page 12*/
10613 #define SYSCFG_SWPR_PAGE13_Pos         (13U)
10614 #define SYSCFG_SWPR_PAGE13_Msk         (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
10615 #define SYSCFG_SWPR_PAGE13             (SYSCFG_SWPR_PAGE13_Msk)               /*!< CCMSRAM  Write protection page 13*/
10616 #define SYSCFG_SWPR_PAGE14_Pos         (14U)
10617 #define SYSCFG_SWPR_PAGE14_Msk         (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
10618 #define SYSCFG_SWPR_PAGE14             (SYSCFG_SWPR_PAGE14_Msk)               /*!< CCMSRAM  Write protection page 14*/
10619 #define SYSCFG_SWPR_PAGE15_Pos         (15U)
10620 #define SYSCFG_SWPR_PAGE15_Msk         (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
10621 #define SYSCFG_SWPR_PAGE15             (SYSCFG_SWPR_PAGE15_Msk)               /*!< CCMSRAM  Write protection page 15*/
10622 #define SYSCFG_SWPR_PAGE16_Pos         (16U)
10623 #define SYSCFG_SWPR_PAGE16_Msk         (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */
10624 #define SYSCFG_SWPR_PAGE16             (SYSCFG_SWPR_PAGE16_Msk)               /*!< CCMSRAM  Write protection page 16*/
10625 #define SYSCFG_SWPR_PAGE17_Pos         (17U)
10626 #define SYSCFG_SWPR_PAGE17_Msk         (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */
10627 #define SYSCFG_SWPR_PAGE17             (SYSCFG_SWPR_PAGE17_Msk)               /*!< CCMSRAM  Write protection page 17*/
10628 #define SYSCFG_SWPR_PAGE18_Pos         (18U)
10629 #define SYSCFG_SWPR_PAGE18_Msk         (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */
10630 #define SYSCFG_SWPR_PAGE18             (SYSCFG_SWPR_PAGE18_Msk)               /*!< CCMSRAM  Write protection page 18*/
10631 #define SYSCFG_SWPR_PAGE19_Pos         (19U)
10632 #define SYSCFG_SWPR_PAGE19_Msk         (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */
10633 #define SYSCFG_SWPR_PAGE19             (SYSCFG_SWPR_PAGE19_Msk)               /*!< CCMSRAM  Write protection page 19*/
10634 #define SYSCFG_SWPR_PAGE20_Pos         (20U)
10635 #define SYSCFG_SWPR_PAGE20_Msk         (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */
10636 #define SYSCFG_SWPR_PAGE20             (SYSCFG_SWPR_PAGE20_Msk)               /*!< CCMSRAM  Write protection page 20*/
10637 #define SYSCFG_SWPR_PAGE21_Pos         (21U)
10638 #define SYSCFG_SWPR_PAGE21_Msk         (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */
10639 #define SYSCFG_SWPR_PAGE21             (SYSCFG_SWPR_PAGE21_Msk)               /*!< CCMSRAM  Write protection page 21*/
10640 #define SYSCFG_SWPR_PAGE22_Pos         (22U)
10641 #define SYSCFG_SWPR_PAGE22_Msk         (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */
10642 #define SYSCFG_SWPR_PAGE22             (SYSCFG_SWPR_PAGE22_Msk)               /*!< CCMSRAM  Write protection page 22*/
10643 #define SYSCFG_SWPR_PAGE23_Pos         (23U)
10644 #define SYSCFG_SWPR_PAGE23_Msk         (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */
10645 #define SYSCFG_SWPR_PAGE23             (SYSCFG_SWPR_PAGE23_Msk)               /*!< CCMSRAM  Write protection page 23*/
10646 #define SYSCFG_SWPR_PAGE24_Pos         (24U)
10647 #define SYSCFG_SWPR_PAGE24_Msk         (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */
10648 #define SYSCFG_SWPR_PAGE24             (SYSCFG_SWPR_PAGE24_Msk)               /*!< CCMSRAM  Write protection page 24*/
10649 #define SYSCFG_SWPR_PAGE25_Pos         (25U)
10650 #define SYSCFG_SWPR_PAGE25_Msk         (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */
10651 #define SYSCFG_SWPR_PAGE25             (SYSCFG_SWPR_PAGE25_Msk)               /*!< CCMSRAM  Write protection page 25*/
10652 #define SYSCFG_SWPR_PAGE26_Pos         (26U)
10653 #define SYSCFG_SWPR_PAGE26_Msk         (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */
10654 #define SYSCFG_SWPR_PAGE26             (SYSCFG_SWPR_PAGE26_Msk)               /*!< CCMSRAM  Write protection page 26*/
10655 #define SYSCFG_SWPR_PAGE27_Pos         (27U)
10656 #define SYSCFG_SWPR_PAGE27_Msk         (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */
10657 #define SYSCFG_SWPR_PAGE27             (SYSCFG_SWPR_PAGE27_Msk)               /*!< CCMSRAM  Write protection page 27*/
10658 #define SYSCFG_SWPR_PAGE28_Pos         (28U)
10659 #define SYSCFG_SWPR_PAGE28_Msk         (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */
10660 #define SYSCFG_SWPR_PAGE28             (SYSCFG_SWPR_PAGE28_Msk)               /*!< CCMSRAM  Write protection page 28*/
10661 #define SYSCFG_SWPR_PAGE29_Pos         (29U)
10662 #define SYSCFG_SWPR_PAGE29_Msk         (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */
10663 #define SYSCFG_SWPR_PAGE29             (SYSCFG_SWPR_PAGE29_Msk)               /*!< CCMSRAM  Write protection page 29*/
10664 #define SYSCFG_SWPR_PAGE30_Pos         (30U)
10665 #define SYSCFG_SWPR_PAGE30_Msk         (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */
10666 #define SYSCFG_SWPR_PAGE30             (SYSCFG_SWPR_PAGE30_Msk)               /*!< CCMSRAM  Write protection page 30*/
10667 #define SYSCFG_SWPR_PAGE31_Pos         (31U)
10668 #define SYSCFG_SWPR_PAGE31_Msk         (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */
10669 #define SYSCFG_SWPR_PAGE31             (SYSCFG_SWPR_PAGE31_Msk)               /*!< CCMSRAM  Write protection page 31*/
10670 
10671 /******************  Bit definition for SYSCFG_SKR register  ****************/
10672 #define SYSCFG_SKR_KEY_Pos              (0U)
10673 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
10674 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
10675 
10676 /******************************************************************************/
10677 /*                                                                            */
10678 /*                                    TIM                                     */
10679 /*                                                                            */
10680 /******************************************************************************/
10681 /*******************  Bit definition for TIM_CR1 register  ********************/
10682 #define TIM_CR1_CEN_Pos           (0U)
10683 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
10684 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
10685 #define TIM_CR1_UDIS_Pos          (1U)
10686 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
10687 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
10688 #define TIM_CR1_URS_Pos           (2U)
10689 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
10690 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
10691 #define TIM_CR1_OPM_Pos           (3U)
10692 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
10693 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
10694 #define TIM_CR1_DIR_Pos           (4U)
10695 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
10696 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
10697 
10698 #define TIM_CR1_CMS_Pos           (5U)
10699 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
10700 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
10701 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
10702 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
10703 
10704 #define TIM_CR1_ARPE_Pos          (7U)
10705 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
10706 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
10707 
10708 #define TIM_CR1_CKD_Pos           (8U)
10709 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
10710 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
10711 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
10712 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
10713 
10714 #define TIM_CR1_UIFREMAP_Pos      (11U)
10715 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
10716 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
10717 
10718 #define TIM_CR1_DITHEN_Pos      (12U)
10719 #define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
10720 #define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
10721 
10722 /*******************  Bit definition for TIM_CR2 register  ********************/
10723 #define TIM_CR2_CCPC_Pos          (0U)
10724 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
10725 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
10726 #define TIM_CR2_CCUS_Pos          (2U)
10727 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
10728 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
10729 #define TIM_CR2_CCDS_Pos          (3U)
10730 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
10731 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
10732 
10733 #define TIM_CR2_MMS_Pos           (4U)
10734 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
10735 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
10736 #define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
10737 #define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
10738 #define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
10739 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
10740 
10741 #define TIM_CR2_TI1S_Pos          (7U)
10742 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
10743 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
10744 #define TIM_CR2_OIS1_Pos          (8U)
10745 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
10746 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
10747 #define TIM_CR2_OIS1N_Pos         (9U)
10748 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
10749 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
10750 #define TIM_CR2_OIS2_Pos          (10U)
10751 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
10752 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
10753 #define TIM_CR2_OIS2N_Pos         (11U)
10754 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
10755 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
10756 #define TIM_CR2_OIS3_Pos          (12U)
10757 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
10758 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
10759 #define TIM_CR2_OIS3N_Pos         (13U)
10760 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
10761 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
10762 #define TIM_CR2_OIS4_Pos          (14U)
10763 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
10764 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
10765 #define TIM_CR2_OIS4N_Pos         (15U)
10766 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
10767 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
10768 #define TIM_CR2_OIS5_Pos          (16U)
10769 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
10770 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
10771 #define TIM_CR2_OIS6_Pos          (18U)
10772 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
10773 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
10774 
10775 #define TIM_CR2_MMS2_Pos          (20U)
10776 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
10777 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
10778 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
10779 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
10780 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
10781 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
10782 
10783 /*******************  Bit definition for TIM_SMCR register  *******************/
10784 #define TIM_SMCR_SMS_Pos          (0U)
10785 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
10786 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
10787 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
10788 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
10789 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
10790 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
10791 
10792 #define TIM_SMCR_OCCS_Pos         (3U)
10793 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
10794 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
10795 
10796 #define TIM_SMCR_TS_Pos           (4U)
10797 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
10798 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
10799 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
10800 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
10801 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
10802 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
10803 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
10804 
10805 #define TIM_SMCR_MSM_Pos          (7U)
10806 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
10807 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
10808 
10809 #define TIM_SMCR_ETF_Pos          (8U)
10810 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
10811 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
10812 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
10813 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
10814 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
10815 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
10816 
10817 #define TIM_SMCR_ETPS_Pos         (12U)
10818 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
10819 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
10820 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
10821 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
10822 
10823 #define TIM_SMCR_ECE_Pos          (14U)
10824 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
10825 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
10826 #define TIM_SMCR_ETP_Pos          (15U)
10827 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
10828 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
10829 
10830 #define TIM_SMCR_SMSPE_Pos        (24U)
10831 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
10832 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
10833 
10834 #define TIM_SMCR_SMSPS_Pos        (25U)
10835 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
10836 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
10837 
10838 /*******************  Bit definition for TIM_DIER register  *******************/
10839 #define TIM_DIER_UIE_Pos          (0U)
10840 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
10841 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
10842 #define TIM_DIER_CC1IE_Pos        (1U)
10843 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
10844 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
10845 #define TIM_DIER_CC2IE_Pos        (2U)
10846 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
10847 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
10848 #define TIM_DIER_CC3IE_Pos        (3U)
10849 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
10850 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
10851 #define TIM_DIER_CC4IE_Pos        (4U)
10852 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
10853 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
10854 #define TIM_DIER_COMIE_Pos        (5U)
10855 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
10856 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
10857 #define TIM_DIER_TIE_Pos          (6U)
10858 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
10859 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
10860 #define TIM_DIER_BIE_Pos          (7U)
10861 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
10862 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
10863 #define TIM_DIER_UDE_Pos          (8U)
10864 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
10865 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
10866 #define TIM_DIER_CC1DE_Pos        (9U)
10867 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
10868 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
10869 #define TIM_DIER_CC2DE_Pos        (10U)
10870 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
10871 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
10872 #define TIM_DIER_CC3DE_Pos        (11U)
10873 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
10874 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
10875 #define TIM_DIER_CC4DE_Pos        (12U)
10876 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
10877 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
10878 #define TIM_DIER_COMDE_Pos        (13U)
10879 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
10880 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
10881 #define TIM_DIER_TDE_Pos          (14U)
10882 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
10883 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
10884 #define TIM_DIER_IDXIE_Pos        (20U)
10885 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
10886 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
10887 #define TIM_DIER_DIRIE_Pos        (21U)
10888 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
10889 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
10890 #define TIM_DIER_IERRIE_Pos       (22U)
10891 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
10892 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
10893 #define TIM_DIER_TERRIE_Pos       (23U)
10894 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
10895 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
10896 
10897 /********************  Bit definition for TIM_SR register  ********************/
10898 #define TIM_SR_UIF_Pos            (0U)
10899 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
10900 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
10901 #define TIM_SR_CC1IF_Pos          (1U)
10902 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
10903 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
10904 #define TIM_SR_CC2IF_Pos          (2U)
10905 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
10906 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
10907 #define TIM_SR_CC3IF_Pos          (3U)
10908 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
10909 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
10910 #define TIM_SR_CC4IF_Pos          (4U)
10911 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
10912 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
10913 #define TIM_SR_COMIF_Pos          (5U)
10914 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
10915 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
10916 #define TIM_SR_TIF_Pos            (6U)
10917 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
10918 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
10919 #define TIM_SR_BIF_Pos            (7U)
10920 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
10921 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
10922 #define TIM_SR_B2IF_Pos           (8U)
10923 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
10924 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
10925 #define TIM_SR_CC1OF_Pos          (9U)
10926 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
10927 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
10928 #define TIM_SR_CC2OF_Pos          (10U)
10929 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
10930 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
10931 #define TIM_SR_CC3OF_Pos          (11U)
10932 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
10933 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
10934 #define TIM_SR_CC4OF_Pos          (12U)
10935 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
10936 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
10937 #define TIM_SR_SBIF_Pos           (13U)
10938 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
10939 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
10940 #define TIM_SR_CC5IF_Pos          (16U)
10941 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
10942 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
10943 #define TIM_SR_CC6IF_Pos          (17U)
10944 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
10945 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
10946 #define TIM_SR_IDXF_Pos           (20U)
10947 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
10948 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
10949 #define TIM_SR_DIRF_Pos           (21U)
10950 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
10951 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
10952 #define TIM_SR_IERRF_Pos          (22U)
10953 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
10954 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
10955 #define TIM_SR_TERRF_Pos          (23U)
10956 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
10957 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
10958 
10959 /*******************  Bit definition for TIM_EGR register  ********************/
10960 #define TIM_EGR_UG_Pos            (0U)
10961 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
10962 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
10963 #define TIM_EGR_CC1G_Pos          (1U)
10964 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
10965 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
10966 #define TIM_EGR_CC2G_Pos          (2U)
10967 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
10968 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
10969 #define TIM_EGR_CC3G_Pos          (3U)
10970 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
10971 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
10972 #define TIM_EGR_CC4G_Pos          (4U)
10973 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
10974 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
10975 #define TIM_EGR_COMG_Pos          (5U)
10976 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
10977 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
10978 #define TIM_EGR_TG_Pos            (6U)
10979 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
10980 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
10981 #define TIM_EGR_BG_Pos            (7U)
10982 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
10983 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
10984 #define TIM_EGR_B2G_Pos           (8U)
10985 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
10986 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
10987 
10988 
10989 /******************  Bit definition for TIM_CCMR1 register  *******************/
10990 #define TIM_CCMR1_CC1S_Pos        (0U)
10991 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
10992 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
10993 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
10994 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
10995 
10996 #define TIM_CCMR1_OC1FE_Pos       (2U)
10997 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
10998 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
10999 #define TIM_CCMR1_OC1PE_Pos       (3U)
11000 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
11001 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
11002 
11003 #define TIM_CCMR1_OC1M_Pos        (4U)
11004 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
11005 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
11006 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
11007 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
11008 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
11009 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
11010 
11011 #define TIM_CCMR1_OC1CE_Pos       (7U)
11012 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
11013 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
11014 
11015 #define TIM_CCMR1_CC2S_Pos        (8U)
11016 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
11017 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
11018 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
11019 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
11020 
11021 #define TIM_CCMR1_OC2FE_Pos       (10U)
11022 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
11023 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
11024 #define TIM_CCMR1_OC2PE_Pos       (11U)
11025 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
11026 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
11027 
11028 #define TIM_CCMR1_OC2M_Pos        (12U)
11029 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
11030 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
11031 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
11032 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
11033 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
11034 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
11035 
11036 #define TIM_CCMR1_OC2CE_Pos       (15U)
11037 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
11038 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
11039 
11040 /*----------------------------------------------------------------------------*/
11041 #define TIM_CCMR1_IC1PSC_Pos      (2U)
11042 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
11043 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
11044 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
11045 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
11046 
11047 #define TIM_CCMR1_IC1F_Pos        (4U)
11048 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
11049 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
11050 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
11051 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
11052 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
11053 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
11054 
11055 #define TIM_CCMR1_IC2PSC_Pos      (10U)
11056 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
11057 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
11058 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
11059 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
11060 
11061 #define TIM_CCMR1_IC2F_Pos        (12U)
11062 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
11063 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
11064 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
11065 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
11066 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
11067 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
11068 
11069 /******************  Bit definition for TIM_CCMR2 register  *******************/
11070 #define TIM_CCMR2_CC3S_Pos        (0U)
11071 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
11072 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
11073 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
11074 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
11075 
11076 #define TIM_CCMR2_OC3FE_Pos       (2U)
11077 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
11078 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
11079 #define TIM_CCMR2_OC3PE_Pos       (3U)
11080 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
11081 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
11082 
11083 #define TIM_CCMR2_OC3M_Pos        (4U)
11084 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
11085 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
11086 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
11087 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
11088 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
11089 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
11090 
11091 #define TIM_CCMR2_OC3CE_Pos       (7U)
11092 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
11093 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
11094 
11095 #define TIM_CCMR2_CC4S_Pos        (8U)
11096 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
11097 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
11098 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
11099 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
11100 
11101 #define TIM_CCMR2_OC4FE_Pos       (10U)
11102 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
11103 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
11104 #define TIM_CCMR2_OC4PE_Pos       (11U)
11105 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
11106 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
11107 
11108 #define TIM_CCMR2_OC4M_Pos        (12U)
11109 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
11110 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
11111 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
11112 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
11113 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
11114 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
11115 
11116 #define TIM_CCMR2_OC4CE_Pos       (15U)
11117 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
11118 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
11119 
11120 /*----------------------------------------------------------------------------*/
11121 #define TIM_CCMR2_IC3PSC_Pos      (2U)
11122 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
11123 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
11124 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
11125 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
11126 
11127 #define TIM_CCMR2_IC3F_Pos        (4U)
11128 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
11129 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
11130 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
11131 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
11132 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
11133 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
11134 
11135 #define TIM_CCMR2_IC4PSC_Pos      (10U)
11136 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
11137 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
11138 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
11139 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
11140 
11141 #define TIM_CCMR2_IC4F_Pos        (12U)
11142 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
11143 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
11144 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
11145 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
11146 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
11147 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
11148 
11149 /******************  Bit definition for TIM_CCMR3 register  *******************/
11150 #define TIM_CCMR3_OC5FE_Pos       (2U)
11151 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
11152 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
11153 #define TIM_CCMR3_OC5PE_Pos       (3U)
11154 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
11155 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
11156 
11157 #define TIM_CCMR3_OC5M_Pos        (4U)
11158 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
11159 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
11160 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
11161 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
11162 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
11163 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
11164 
11165 #define TIM_CCMR3_OC5CE_Pos       (7U)
11166 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
11167 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
11168 
11169 #define TIM_CCMR3_OC6FE_Pos       (10U)
11170 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
11171 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
11172 #define TIM_CCMR3_OC6PE_Pos       (11U)
11173 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
11174 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
11175 
11176 #define TIM_CCMR3_OC6M_Pos        (12U)
11177 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
11178 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
11179 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
11180 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
11181 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
11182 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
11183 
11184 #define TIM_CCMR3_OC6CE_Pos       (15U)
11185 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
11186 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
11187 
11188 /*******************  Bit definition for TIM_CCER register  *******************/
11189 #define TIM_CCER_CC1E_Pos         (0U)
11190 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
11191 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
11192 #define TIM_CCER_CC1P_Pos         (1U)
11193 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
11194 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
11195 #define TIM_CCER_CC1NE_Pos        (2U)
11196 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
11197 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
11198 #define TIM_CCER_CC1NP_Pos        (3U)
11199 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
11200 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
11201 #define TIM_CCER_CC2E_Pos         (4U)
11202 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
11203 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
11204 #define TIM_CCER_CC2P_Pos         (5U)
11205 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
11206 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
11207 #define TIM_CCER_CC2NE_Pos        (6U)
11208 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
11209 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
11210 #define TIM_CCER_CC2NP_Pos        (7U)
11211 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
11212 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
11213 #define TIM_CCER_CC3E_Pos         (8U)
11214 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
11215 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
11216 #define TIM_CCER_CC3P_Pos         (9U)
11217 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
11218 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
11219 #define TIM_CCER_CC3NE_Pos        (10U)
11220 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
11221 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
11222 #define TIM_CCER_CC3NP_Pos        (11U)
11223 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
11224 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
11225 #define TIM_CCER_CC4E_Pos         (12U)
11226 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
11227 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
11228 #define TIM_CCER_CC4P_Pos         (13U)
11229 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
11230 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
11231 #define TIM_CCER_CC4NE_Pos        (14U)
11232 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
11233 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
11234 #define TIM_CCER_CC4NP_Pos        (15U)
11235 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
11236 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
11237 #define TIM_CCER_CC5E_Pos         (16U)
11238 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
11239 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
11240 #define TIM_CCER_CC5P_Pos         (17U)
11241 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
11242 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
11243 #define TIM_CCER_CC6E_Pos         (20U)
11244 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
11245 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
11246 #define TIM_CCER_CC6P_Pos         (21U)
11247 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
11248 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
11249 
11250 /*******************  Bit definition for TIM_CNT register  ********************/
11251 #define TIM_CNT_CNT_Pos           (0U)
11252 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
11253 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
11254 #define TIM_CNT_UIFCPY_Pos        (31U)
11255 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
11256 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
11257 
11258 /*******************  Bit definition for TIM_PSC register  ********************/
11259 #define TIM_PSC_PSC_Pos           (0U)
11260 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
11261 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
11262 
11263 /*******************  Bit definition for TIM_ARR register  ********************/
11264 #define TIM_ARR_ARR_Pos           (0U)
11265 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
11266 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
11267 
11268 /*******************  Bit definition for TIM_RCR register  ********************/
11269 #define TIM_RCR_REP_Pos           (0U)
11270 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
11271 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
11272 
11273 /*******************  Bit definition for TIM_CCR1 register  *******************/
11274 #define TIM_CCR1_CCR1_Pos         (0U)
11275 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
11276 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
11277 
11278 /*******************  Bit definition for TIM_CCR2 register  *******************/
11279 #define TIM_CCR2_CCR2_Pos         (0U)
11280 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
11281 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
11282 
11283 /*******************  Bit definition for TIM_CCR3 register  *******************/
11284 #define TIM_CCR3_CCR3_Pos         (0U)
11285 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
11286 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
11287 
11288 /*******************  Bit definition for TIM_CCR4 register  *******************/
11289 #define TIM_CCR4_CCR4_Pos         (0U)
11290 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
11291 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
11292 
11293 /*******************  Bit definition for TIM_CCR5 register  *******************/
11294 #define TIM_CCR5_CCR5_Pos         (0U)
11295 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
11296 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
11297 #define TIM_CCR5_GC5C1_Pos        (29U)
11298 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
11299 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
11300 #define TIM_CCR5_GC5C2_Pos        (30U)
11301 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
11302 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
11303 #define TIM_CCR5_GC5C3_Pos        (31U)
11304 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
11305 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
11306 
11307 /*******************  Bit definition for TIM_CCR6 register  *******************/
11308 #define TIM_CCR6_CCR6_Pos         (0U)
11309 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
11310 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
11311 
11312 /*******************  Bit definition for TIM_BDTR register  *******************/
11313 #define TIM_BDTR_DTG_Pos          (0U)
11314 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
11315 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
11316 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
11317 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
11318 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
11319 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
11320 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
11321 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
11322 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
11323 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
11324 
11325 #define TIM_BDTR_LOCK_Pos         (8U)
11326 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
11327 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
11328 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
11329 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
11330 
11331 #define TIM_BDTR_OSSI_Pos         (10U)
11332 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
11333 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
11334 #define TIM_BDTR_OSSR_Pos         (11U)
11335 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
11336 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
11337 #define TIM_BDTR_BKE_Pos          (12U)
11338 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
11339 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
11340 #define TIM_BDTR_BKP_Pos          (13U)
11341 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
11342 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
11343 #define TIM_BDTR_AOE_Pos          (14U)
11344 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
11345 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
11346 #define TIM_BDTR_MOE_Pos          (15U)
11347 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
11348 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
11349 
11350 #define TIM_BDTR_BKF_Pos          (16U)
11351 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
11352 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
11353 #define TIM_BDTR_BK2F_Pos         (20U)
11354 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
11355 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
11356 
11357 #define TIM_BDTR_BK2E_Pos         (24U)
11358 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
11359 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
11360 #define TIM_BDTR_BK2P_Pos         (25U)
11361 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
11362 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
11363 
11364 #define TIM_BDTR_BKDSRM_Pos       (26U)
11365 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
11366 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
11367 #define TIM_BDTR_BK2DSRM_Pos      (27U)
11368 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
11369 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
11370 
11371 #define TIM_BDTR_BKBID_Pos        (28U)
11372 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
11373 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
11374 #define TIM_BDTR_BK2BID_Pos       (29U)
11375 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
11376 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
11377 
11378 /*******************  Bit definition for TIM_DCR register  ********************/
11379 #define TIM_DCR_DBA_Pos           (0U)
11380 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
11381 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
11382 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
11383 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
11384 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
11385 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
11386 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
11387 
11388 #define TIM_DCR_DBL_Pos           (8U)
11389 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
11390 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
11391 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
11392 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
11393 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
11394 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
11395 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
11396 
11397 /*******************  Bit definition for TIM1_AF1 register  *******************/
11398 #define TIM1_AF1_BKINE_Pos        (0U)
11399 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
11400 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
11401 #define TIM1_AF1_BKCMP1E_Pos      (1U)
11402 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
11403 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
11404 #define TIM1_AF1_BKCMP2E_Pos      (2U)
11405 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
11406 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
11407 #define TIM1_AF1_BKCMP3E_Pos      (3U)
11408 #define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
11409 #define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
11410 #define TIM1_AF1_BKCMP4E_Pos      (4U)
11411 #define TIM1_AF1_BKCMP4E_Msk      (0x1UL << TIM1_AF1_BKCMP4E_Pos)              /*!< 0x00000010 */
11412 #define TIM1_AF1_BKCMP4E          TIM1_AF1_BKCMP4E_Msk                         /*!<BRK COMP4 enable */
11413 #define TIM1_AF1_BKINP_Pos        (9U)
11414 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
11415 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
11416 #define TIM1_AF1_BKCMP1P_Pos      (10U)
11417 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
11418 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
11419 #define TIM1_AF1_BKCMP2P_Pos      (11U)
11420 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
11421 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
11422 #define TIM1_AF1_BKCMP3P_Pos      (12U)
11423 #define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
11424 #define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
11425 #define TIM1_AF1_BKCMP4P_Pos      (13U)
11426 #define TIM1_AF1_BKCMP4P_Msk      (0x1UL << TIM1_AF1_BKCMP4P_Pos)              /*!< 0x00002000 */
11427 #define TIM1_AF1_BKCMP4P          TIM1_AF1_BKCMP4P_Msk                         /*!<BRK COMP4 input polarity */
11428 #define TIM1_AF1_ETRSEL_Pos       (14U)
11429 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
11430 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
11431 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
11432 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
11433 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
11434 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
11435 
11436 /*******************  Bit definition for TIM1_AF2 register  *********************/
11437 #define TIM1_AF2_BK2INE_Pos        (0U)
11438 #define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
11439 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
11440 #define TIM1_AF2_BK2CMP1E_Pos      (1U)
11441 #define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
11442 #define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
11443 #define TIM1_AF2_BK2CMP2E_Pos      (2U)
11444 #define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
11445 #define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
11446 #define TIM1_AF2_BK2CMP3E_Pos      (3U)
11447 #define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
11448 #define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
11449 #define TIM1_AF2_BK2CMP4E_Pos      (4U)
11450 #define TIM1_AF2_BK2CMP4E_Msk      (0x1UL << TIM1_AF2_BK2CMP4E_Pos)              /*!< 0x00000010 */
11451 #define TIM1_AF2_BK2CMP4E          TIM1_AF2_BK2CMP4E_Msk                         /*!<BRK2 COMP4 enable */
11452 #define TIM1_AF2_BK2INP_Pos        (9U)
11453 #define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
11454 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
11455 #define TIM1_AF2_BK2CMP1P_Pos      (10U)
11456 #define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
11457 #define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
11458 #define TIM1_AF2_BK2CMP2P_Pos      (11U)
11459 #define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
11460 #define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
11461 #define TIM1_AF2_BK2CMP3P_Pos      (12U)
11462 #define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
11463 #define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
11464 #define TIM1_AF2_BK2CMP4P_Pos      (13U)
11465 #define TIM1_AF2_BK2CMP4P_Msk      (0x1UL << TIM1_AF2_BK2CMP4P_Pos)              /*!< 0x00000800 */
11466 #define TIM1_AF2_BK2CMP4P          TIM1_AF2_BK2CMP4P_Msk                         /*!<BRK2 COMP4 input polarity */
11467 #define TIM1_AF2_OCRSEL_Pos        (16U)
11468 #define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
11469 #define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
11470 #define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
11471 #define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
11472 #define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
11473 
11474 /*******************  Bit definition for TIM_OR register  *********************/
11475 #define TIM_OR_HSE32EN_Pos       (0U)
11476 #define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
11477 #define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
11478 
11479 /*******************  Bit definition for TIM_TISEL register  *********************/
11480 #define TIM_TISEL_TI1SEL_Pos      (0U)
11481 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
11482 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
11483 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
11484 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
11485 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
11486 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
11487 
11488 #define TIM_TISEL_TI2SEL_Pos      (8U)
11489 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
11490 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
11491 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
11492 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
11493 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
11494 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
11495 
11496 #define TIM_TISEL_TI3SEL_Pos      (16U)
11497 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
11498 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
11499 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
11500 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
11501 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
11502 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
11503 
11504 #define TIM_TISEL_TI4SEL_Pos      (24U)
11505 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
11506 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
11507 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
11508 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
11509 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
11510 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
11511 
11512 /*******************  Bit definition for TIM_DTR2 register  *********************/
11513 #define TIM_DTR2_DTGF_Pos      (0U)
11514 #define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
11515 #define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
11516 #define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
11517 #define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
11518 #define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
11519 #define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
11520 #define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
11521 #define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
11522 #define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
11523 #define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
11524 
11525 #define TIM_DTR2_DTAE_Pos      (16U)
11526 #define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
11527 #define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
11528 #define TIM_DTR2_DTPE_Pos      (17U)
11529 #define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
11530 #define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
11531 
11532 /*******************  Bit definition for TIM_ECR register  *********************/
11533 #define TIM_ECR_IE_Pos       (0U)
11534 #define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
11535 #define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
11536 
11537 #define TIM_ECR_IDIR_Pos      (1U)
11538 #define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
11539 #define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
11540 #define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
11541 #define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
11542 
11543 #define TIM_ECR_FIDX_Pos      (5U)
11544 #define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
11545 #define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
11546 
11547 #define TIM_ECR_IPOS_Pos      (6U)
11548 #define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
11549 #define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
11550 #define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
11551 #define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
11552 
11553 #define TIM_ECR_PW_Pos        (16U)
11554 #define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
11555 #define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
11556 #define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
11557 #define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
11558 #define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
11559 #define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
11560 #define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
11561 #define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
11562 #define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
11563 #define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
11564 
11565 #define TIM_ECR_PWPRSC_Pos    (24U)
11566 #define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
11567 #define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
11568 #define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
11569 #define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
11570 #define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
11571 
11572 /*******************  Bit definition for TIM_DMAR register  *******************/
11573 #define TIM_DMAR_DMAB_Pos         (0U)
11574 #define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
11575 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
11576 
11577 /******************************************************************************/
11578 /*                                                                            */
11579 /*                         Low Power Timer (LPTIM)                           */
11580 /*                                                                            */
11581 /******************************************************************************/
11582 /******************  Bit definition for LPTIM_ISR register  *******************/
11583 #define LPTIM_ISR_CMPM_Pos          (0U)
11584 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
11585 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
11586 #define LPTIM_ISR_ARRM_Pos          (1U)
11587 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
11588 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
11589 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
11590 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
11591 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
11592 #define LPTIM_ISR_CMPOK_Pos         (3U)
11593 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
11594 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
11595 #define LPTIM_ISR_ARROK_Pos         (4U)
11596 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
11597 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
11598 #define LPTIM_ISR_UP_Pos            (5U)
11599 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
11600 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
11601 #define LPTIM_ISR_DOWN_Pos          (6U)
11602 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
11603 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
11604 
11605 /******************  Bit definition for LPTIM_ICR register  *******************/
11606 #define LPTIM_ICR_CMPMCF_Pos        (0U)
11607 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
11608 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
11609 #define LPTIM_ICR_ARRMCF_Pos        (1U)
11610 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
11611 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
11612 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
11613 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
11614 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
11615 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
11616 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
11617 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
11618 #define LPTIM_ICR_ARROKCF_Pos       (4U)
11619 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
11620 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
11621 #define LPTIM_ICR_UPCF_Pos          (5U)
11622 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
11623 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
11624 #define LPTIM_ICR_DOWNCF_Pos        (6U)
11625 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
11626 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
11627 
11628 /******************  Bit definition for LPTIM_IER register ********************/
11629 #define LPTIM_IER_CMPMIE_Pos        (0U)
11630 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
11631 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
11632 #define LPTIM_IER_ARRMIE_Pos        (1U)
11633 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
11634 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
11635 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
11636 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
11637 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
11638 #define LPTIM_IER_CMPOKIE_Pos       (3U)
11639 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
11640 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
11641 #define LPTIM_IER_ARROKIE_Pos       (4U)
11642 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
11643 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
11644 #define LPTIM_IER_UPIE_Pos          (5U)
11645 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
11646 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
11647 #define LPTIM_IER_DOWNIE_Pos        (6U)
11648 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
11649 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
11650 
11651 /******************  Bit definition for LPTIM_CFGR register *******************/
11652 #define LPTIM_CFGR_CKSEL_Pos        (0U)
11653 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
11654 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
11655 
11656 #define LPTIM_CFGR_CKPOL_Pos        (1U)
11657 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
11658 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
11659 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
11660 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
11661 
11662 #define LPTIM_CFGR_CKFLT_Pos        (3U)
11663 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
11664 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
11665 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
11666 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
11667 
11668 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
11669 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
11670 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
11671 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
11672 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
11673 
11674 #define LPTIM_CFGR_PRESC_Pos        (9U)
11675 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
11676 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
11677 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
11678 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
11679 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
11680 
11681 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
11682 #define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
11683 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
11684 #define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
11685 #define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
11686 #define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
11687 #define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
11688 
11689 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
11690 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
11691 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
11692 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
11693 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
11694 
11695 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
11696 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
11697 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
11698 #define LPTIM_CFGR_WAVE_Pos         (20U)
11699 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
11700 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
11701 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
11702 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
11703 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
11704 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
11705 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
11706 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
11707 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
11708 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
11709 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
11710 #define LPTIM_CFGR_ENC_Pos          (24U)
11711 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
11712 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
11713 
11714 /******************  Bit definition for LPTIM_CR register  ********************/
11715 #define LPTIM_CR_ENABLE_Pos         (0U)
11716 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
11717 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
11718 #define LPTIM_CR_SNGSTRT_Pos        (1U)
11719 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
11720 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
11721 #define LPTIM_CR_CNTSTRT_Pos        (2U)
11722 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
11723 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
11724 #define LPTIM_CR_COUNTRST_Pos       (3U)
11725 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
11726 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
11727 #define LPTIM_CR_RSTARE_Pos         (4U)
11728 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
11729 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
11730 
11731 /******************  Bit definition for LPTIM_CMP register  *******************/
11732 #define LPTIM_CMP_CMP_Pos           (0U)
11733 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
11734 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
11735 
11736 /******************  Bit definition for LPTIM_ARR register  *******************/
11737 #define LPTIM_ARR_ARR_Pos           (0U)
11738 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
11739 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
11740 
11741 /******************  Bit definition for LPTIM_CNT register  *******************/
11742 #define LPTIM_CNT_CNT_Pos           (0U)
11743 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
11744 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
11745 
11746 /******************  Bit definition for LPTIM_OR register  *******************/
11747 #define LPTIM_OR_IN1_Pos             (0U)
11748 #define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
11749 #define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
11750 #define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
11751 #define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
11752 #define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
11753 
11754 #define LPTIM_OR_IN2_Pos             (1U)
11755 #define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
11756 #define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
11757 #define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
11758 #define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
11759 #define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
11760 /******************************************************************************/
11761 /*                                                                            */
11762 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
11763 /*                                                                            */
11764 /******************************************************************************/
11765 /******************  Bit definition for USART_CR1 register  *******************/
11766 #define USART_CR1_UE_Pos             (0U)
11767 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
11768 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
11769 #define USART_CR1_UESM_Pos           (1U)
11770 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
11771 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
11772 #define USART_CR1_RE_Pos             (2U)
11773 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
11774 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
11775 #define USART_CR1_TE_Pos             (3U)
11776 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
11777 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
11778 #define USART_CR1_IDLEIE_Pos         (4U)
11779 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
11780 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
11781 #define USART_CR1_RXNEIE_Pos         (5U)
11782 #define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
11783 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
11784 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
11785 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
11786 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
11787 #define USART_CR1_TCIE_Pos           (6U)
11788 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
11789 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
11790 #define USART_CR1_TXEIE_Pos          (7U)
11791 #define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
11792 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
11793 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
11794 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
11795 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
11796 #define USART_CR1_PEIE_Pos           (8U)
11797 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
11798 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
11799 #define USART_CR1_PS_Pos             (9U)
11800 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
11801 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
11802 #define USART_CR1_PCE_Pos            (10U)
11803 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
11804 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
11805 #define USART_CR1_WAKE_Pos           (11U)
11806 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
11807 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
11808 #define USART_CR1_M_Pos              (12U)
11809 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
11810 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
11811 #define USART_CR1_M0_Pos             (12U)
11812 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
11813 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
11814 #define USART_CR1_MME_Pos            (13U)
11815 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
11816 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
11817 #define USART_CR1_CMIE_Pos           (14U)
11818 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
11819 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
11820 #define USART_CR1_OVER8_Pos          (15U)
11821 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
11822 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
11823 #define USART_CR1_DEDT_Pos           (16U)
11824 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
11825 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
11826 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
11827 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
11828 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
11829 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
11830 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
11831 #define USART_CR1_DEAT_Pos           (21U)
11832 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
11833 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
11834 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
11835 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
11836 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
11837 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
11838 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
11839 #define USART_CR1_RTOIE_Pos          (26U)
11840 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
11841 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
11842 #define USART_CR1_EOBIE_Pos          (27U)
11843 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
11844 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
11845 #define USART_CR1_M1_Pos             (28U)
11846 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
11847 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
11848 #define USART_CR1_FIFOEN_Pos         (29U)
11849 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
11850 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
11851 #define USART_CR1_TXFEIE_Pos         (30U)
11852 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
11853 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
11854 #define USART_CR1_RXFFIE_Pos         (31U)
11855 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
11856 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
11857 
11858 /******************  Bit definition for USART_CR2 register  *******************/
11859 #define USART_CR2_SLVEN_Pos          (0U)
11860 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
11861 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
11862 #define USART_CR2_DIS_NSS_Pos        (3U)
11863 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
11864 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
11865 #define USART_CR2_ADDM7_Pos          (4U)
11866 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
11867 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
11868 #define USART_CR2_LBDL_Pos           (5U)
11869 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
11870 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
11871 #define USART_CR2_LBDIE_Pos          (6U)
11872 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
11873 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
11874 #define USART_CR2_LBCL_Pos           (8U)
11875 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
11876 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
11877 #define USART_CR2_CPHA_Pos           (9U)
11878 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
11879 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
11880 #define USART_CR2_CPOL_Pos           (10U)
11881 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
11882 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
11883 #define USART_CR2_CLKEN_Pos          (11U)
11884 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
11885 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
11886 #define USART_CR2_STOP_Pos           (12U)
11887 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
11888 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
11889 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
11890 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
11891 #define USART_CR2_LINEN_Pos          (14U)
11892 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
11893 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
11894 #define USART_CR2_SWAP_Pos           (15U)
11895 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
11896 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
11897 #define USART_CR2_RXINV_Pos          (16U)
11898 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
11899 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
11900 #define USART_CR2_TXINV_Pos          (17U)
11901 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
11902 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
11903 #define USART_CR2_DATAINV_Pos        (18U)
11904 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
11905 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
11906 #define USART_CR2_MSBFIRST_Pos       (19U)
11907 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
11908 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
11909 #define USART_CR2_ABREN_Pos          (20U)
11910 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
11911 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
11912 #define USART_CR2_ABRMODE_Pos        (21U)
11913 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
11914 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11915 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
11916 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
11917 #define USART_CR2_RTOEN_Pos          (23U)
11918 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
11919 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
11920 #define USART_CR2_ADD_Pos            (24U)
11921 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
11922 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
11923 
11924 /******************  Bit definition for USART_CR3 register  *******************/
11925 #define USART_CR3_EIE_Pos            (0U)
11926 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
11927 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
11928 #define USART_CR3_IREN_Pos           (1U)
11929 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
11930 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
11931 #define USART_CR3_IRLP_Pos           (2U)
11932 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
11933 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
11934 #define USART_CR3_HDSEL_Pos          (3U)
11935 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
11936 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
11937 #define USART_CR3_NACK_Pos           (4U)
11938 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
11939 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
11940 #define USART_CR3_SCEN_Pos           (5U)
11941 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
11942 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
11943 #define USART_CR3_DMAR_Pos           (6U)
11944 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
11945 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
11946 #define USART_CR3_DMAT_Pos           (7U)
11947 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
11948 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
11949 #define USART_CR3_RTSE_Pos           (8U)
11950 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
11951 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
11952 #define USART_CR3_CTSE_Pos           (9U)
11953 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
11954 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
11955 #define USART_CR3_CTSIE_Pos          (10U)
11956 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
11957 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
11958 #define USART_CR3_ONEBIT_Pos         (11U)
11959 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
11960 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
11961 #define USART_CR3_OVRDIS_Pos         (12U)
11962 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
11963 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
11964 #define USART_CR3_DDRE_Pos           (13U)
11965 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
11966 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
11967 #define USART_CR3_DEM_Pos            (14U)
11968 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
11969 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
11970 #define USART_CR3_DEP_Pos            (15U)
11971 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
11972 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
11973 #define USART_CR3_SCARCNT_Pos        (17U)
11974 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
11975 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11976 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
11977 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
11978 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
11979 #define USART_CR3_WUS_Pos            (20U)
11980 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
11981 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
11982 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
11983 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
11984 #define USART_CR3_WUFIE_Pos          (22U)
11985 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
11986 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
11987 #define USART_CR3_TXFTIE_Pos         (23U)
11988 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
11989 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
11990 #define USART_CR3_TCBGTIE_Pos        (24U)
11991 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
11992 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
11993 #define USART_CR3_RXFTCFG_Pos        (25U)
11994 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
11995 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
11996 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
11997 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
11998 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
11999 #define USART_CR3_RXFTIE_Pos         (28U)
12000 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
12001 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
12002 #define USART_CR3_TXFTCFG_Pos        (29U)
12003 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
12004 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
12005 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
12006 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
12007 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
12008 
12009 /******************  Bit definition for USART_BRR register  *******************/
12010 #define USART_BRR_LPUART_Pos         (0U)
12011 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
12012 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
12013 #define USART_BRR_BRR_Pos            (0U)
12014 #define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
12015 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
12016 
12017 /******************  Bit definition for USART_GTPR register  ******************/
12018 #define USART_GTPR_PSC_Pos           (0U)
12019 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
12020 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
12021 #define USART_GTPR_GT_Pos            (8U)
12022 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
12023 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
12024 
12025 /*******************  Bit definition for USART_RTOR register  *****************/
12026 #define USART_RTOR_RTO_Pos           (0U)
12027 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
12028 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
12029 #define USART_RTOR_BLEN_Pos          (24U)
12030 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
12031 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
12032 
12033 /*******************  Bit definition for USART_RQR register  ******************/
12034 #define USART_RQR_ABRRQ_Pos          (0U)
12035 #define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
12036 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
12037 #define USART_RQR_SBKRQ_Pos          (1U)
12038 #define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
12039 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
12040 #define USART_RQR_MMRQ_Pos           (2U)
12041 #define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
12042 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
12043 #define USART_RQR_RXFRQ_Pos          (3U)
12044 #define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
12045 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
12046 #define USART_RQR_TXFRQ_Pos          (4U)
12047 #define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
12048 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
12049 
12050 /*******************  Bit definition for USART_ISR register  ******************/
12051 #define USART_ISR_PE_Pos             (0U)
12052 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
12053 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
12054 #define USART_ISR_FE_Pos             (1U)
12055 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
12056 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
12057 #define USART_ISR_NE_Pos             (2U)
12058 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
12059 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
12060 #define USART_ISR_ORE_Pos            (3U)
12061 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
12062 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
12063 #define USART_ISR_IDLE_Pos           (4U)
12064 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
12065 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
12066 #define USART_ISR_RXNE_Pos           (5U)
12067 #define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
12068 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
12069 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
12070 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
12071 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
12072 #define USART_ISR_TC_Pos             (6U)
12073 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
12074 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
12075 #define USART_ISR_TXE_Pos            (7U)
12076 #define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
12077 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
12078 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
12079 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
12080 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
12081 #define USART_ISR_LBDF_Pos           (8U)
12082 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
12083 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
12084 #define USART_ISR_CTSIF_Pos          (9U)
12085 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
12086 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
12087 #define USART_ISR_CTS_Pos            (10U)
12088 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
12089 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
12090 #define USART_ISR_RTOF_Pos           (11U)
12091 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
12092 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
12093 #define USART_ISR_EOBF_Pos           (12U)
12094 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
12095 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
12096 #define USART_ISR_UDR_Pos            (13U)
12097 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
12098 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
12099 #define USART_ISR_ABRE_Pos           (14U)
12100 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
12101 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
12102 #define USART_ISR_ABRF_Pos           (15U)
12103 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
12104 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
12105 #define USART_ISR_BUSY_Pos           (16U)
12106 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
12107 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
12108 #define USART_ISR_CMF_Pos            (17U)
12109 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
12110 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
12111 #define USART_ISR_SBKF_Pos           (18U)
12112 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
12113 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
12114 #define USART_ISR_RWU_Pos            (19U)
12115 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
12116 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
12117 #define USART_ISR_WUF_Pos            (20U)
12118 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
12119 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
12120 #define USART_ISR_TEACK_Pos          (21U)
12121 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
12122 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
12123 #define USART_ISR_REACK_Pos          (22U)
12124 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
12125 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
12126 #define USART_ISR_TXFE_Pos           (23U)
12127 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
12128 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
12129 #define USART_ISR_RXFF_Pos           (24U)
12130 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
12131 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
12132 #define USART_ISR_TCBGT_Pos          (25U)
12133 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
12134 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
12135 #define USART_ISR_RXFT_Pos           (26U)
12136 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
12137 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
12138 #define USART_ISR_TXFT_Pos           (27U)
12139 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
12140 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
12141 
12142 /*******************  Bit definition for USART_ICR register  ******************/
12143 #define USART_ICR_PECF_Pos           (0U)
12144 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
12145 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
12146 #define USART_ICR_FECF_Pos           (1U)
12147 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
12148 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
12149 #define USART_ICR_NECF_Pos           (2U)
12150 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
12151 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
12152 #define USART_ICR_ORECF_Pos          (3U)
12153 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
12154 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
12155 #define USART_ICR_IDLECF_Pos         (4U)
12156 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
12157 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
12158 #define USART_ICR_TXFECF_Pos         (5U)
12159 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
12160 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
12161 #define USART_ICR_TCCF_Pos           (6U)
12162 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
12163 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
12164 #define USART_ICR_TCBGTCF_Pos        (7U)
12165 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
12166 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
12167 #define USART_ICR_LBDCF_Pos          (8U)
12168 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
12169 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
12170 #define USART_ICR_CTSCF_Pos          (9U)
12171 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
12172 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
12173 #define USART_ICR_RTOCF_Pos          (11U)
12174 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
12175 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
12176 #define USART_ICR_EOBCF_Pos          (12U)
12177 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
12178 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
12179 #define USART_ICR_UDRCF_Pos          (13U)
12180 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
12181 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
12182 #define USART_ICR_CMCF_Pos           (17U)
12183 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
12184 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
12185 #define USART_ICR_WUCF_Pos           (20U)
12186 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
12187 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
12188 
12189 /*******************  Bit definition for USART_RDR register  ******************/
12190 #define USART_RDR_RDR_Pos            (0U)
12191 #define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
12192 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
12193 
12194 /*******************  Bit definition for USART_TDR register  ******************/
12195 #define USART_TDR_TDR_Pos            (0U)
12196 #define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
12197 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
12198 
12199 /*******************  Bit definition for USART_PRESC register  ****************/
12200 #define USART_PRESC_PRESCALER_Pos    (0U)
12201 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
12202 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
12203 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
12204 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
12205 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
12206 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
12207 
12208 /******************************************************************************/
12209 /*                                                                            */
12210 /*                                 VREFBUF                                    */
12211 /*                                                                            */
12212 /******************************************************************************/
12213 /*******************  Bit definition for VREFBUF_CSR register  ****************/
12214 #define VREFBUF_CSR_ENVR_Pos    (0U)
12215 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
12216 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
12217 #define VREFBUF_CSR_HIZ_Pos     (1U)
12218 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
12219 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
12220 #define VREFBUF_CSR_VRR_Pos     (3U)
12221 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
12222 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
12223 #define VREFBUF_CSR_VRS_Pos     (4U)
12224 #define VREFBUF_CSR_VRS_Msk     (0x3UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000030 */
12225 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<VRS[5:0] bits (Voltage reference scale) */
12226 #define VREFBUF_CSR_VRS_0       (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000010 */
12227 #define VREFBUF_CSR_VRS_1       (0x2UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000020 */
12228 
12229 /*******************  Bit definition for VREFBUF_CCR register  ******************/
12230 #define VREFBUF_CCR_TRIM_Pos    (0U)
12231 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
12232 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
12233 
12234 /******************************************************************************/
12235 /*                                                                            */
12236 /*                         USB Device FS Endpoint registers                   */
12237 /*                                                                            */
12238 /******************************************************************************/
12239 #define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
12240 #define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
12241 #define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
12242 #define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
12243 #define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
12244 #define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
12245 #define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
12246 #define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
12247 
12248 /* bit positions */
12249 #define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
12250 #define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
12251 #define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
12252 #define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
12253 #define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
12254 #define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
12255 #define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
12256 #define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
12257 #define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
12258 #define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
12259 
12260 /* EndPoint REGister MASK (no toggle fields) */
12261 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
12262                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
12263 #define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
12264 #define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
12265 #define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
12266 #define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
12267 #define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
12268 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
12269 
12270 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
12271                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
12272 #define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
12273 #define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
12274 #define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
12275 #define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
12276 #define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
12277 #define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
12278 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
12279                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
12280 #define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
12281 #define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
12282 #define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
12283 #define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
12284 #define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
12285 #define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
12286 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
12287 
12288 /******************************************************************************/
12289 /*                                                                            */
12290 /*                         USB Device FS General registers                    */
12291 /*                                                                            */
12292 /******************************************************************************/
12293 #define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
12294 #define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
12295 #define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
12296 #define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
12297 #define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
12298 #define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
12299 #define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
12300 
12301 /******************  Bits definition for USB_CNTR register  *******************/
12302 #define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
12303 #define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
12304 #define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
12305 #define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
12306 #define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
12307 #define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
12308 #define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
12309 #define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
12310 #define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
12311 #define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
12312 #define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
12313 #define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
12314 #define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
12315 #define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
12316 #define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
12317 
12318 /******************  Bits definition for USB_ISTR register  *******************/
12319 #define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
12320 #define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
12321 #define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
12322 #define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
12323 #define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
12324 #define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
12325 #define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
12326 #define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
12327 #define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
12328 #define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
12329 #define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
12330 
12331 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
12332 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
12333 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
12334 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
12335 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
12336 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
12337 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
12338 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
12339 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
12340 
12341 /******************  Bits definition for USB_FNR register  ********************/
12342 #define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
12343 #define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
12344 #define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
12345 #define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
12346 #define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
12347 
12348 /******************  Bits definition for USB_DADDR register    ****************/
12349 #define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
12350 #define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
12351 #define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
12352 #define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
12353 #define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
12354 #define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
12355 #define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
12356 #define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
12357 
12358 #define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
12359 
12360 /******************  Bit definition for USB_BTABLE register  ******************/
12361 #define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
12362 
12363 /******************  Bits definition for USB_BCDR register  *******************/
12364 #define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
12365 #define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
12366 #define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
12367 #define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
12368 #define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
12369 #define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
12370 #define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
12371 #define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
12372 #define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
12373 
12374 /*******************  Bit definition for LPMCSR register  *********************/
12375 #define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
12376 #define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
12377 #define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
12378 #define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
12379 
12380 /*!< Buffer descriptor table */
12381 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
12382 #define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
12383 #define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
12384 #define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
12385 
12386 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
12387 #define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
12388 #define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
12389 #define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
12390 
12391 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
12392 #define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
12393 #define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
12394 #define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
12395 
12396 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
12397 #define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
12398 #define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
12399 #define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
12400 
12401 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
12402 #define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
12403 #define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
12404 #define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
12405 
12406 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
12407 #define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
12408 #define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
12409 #define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
12410 
12411 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
12412 #define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
12413 #define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
12414 #define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
12415 
12416 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
12417 #define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
12418 #define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
12419 #define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
12420 
12421 /*----------------------------------------------------------------------------*/
12422 
12423 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
12424 #define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
12425 #define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
12426 #define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
12427 
12428 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
12429 #define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
12430 #define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
12431 #define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
12432 
12433 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
12434 #define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
12435 #define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
12436 #define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
12437 
12438 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
12439 #define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
12440 #define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
12441 #define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
12442 
12443 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
12444 #define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
12445 #define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
12446 #define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
12447 
12448 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
12449 #define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
12450 #define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
12451 #define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
12452 
12453 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
12454 #define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
12455 #define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
12456 #define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
12457 
12458 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
12459 #define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
12460 #define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
12461 #define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
12462 
12463 /*----------------------------------------------------------------------------*/
12464 
12465 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
12466 #define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
12467 
12468 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
12469 #define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
12470 
12471 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
12472 #define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
12473 
12474 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
12475 #define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
12476 
12477 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
12478 #define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
12479 
12480 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
12481 #define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
12482 
12483 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
12484 #define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
12485 
12486 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
12487 #define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
12488 
12489 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
12490 #define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
12491 
12492 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
12493 #define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
12494 
12495 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
12496 #define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
12497 
12498 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
12499 #define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
12500 
12501 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
12502 #define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
12503 
12504 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
12505 #define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
12506 
12507 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
12508 #define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
12509 
12510 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
12511 #define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
12512 
12513 /*----------------------------------------------------------------------------*/
12514 
12515 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
12516 #define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
12517 #define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
12518 #define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
12519 
12520 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
12521 #define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
12522 #define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
12523 #define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
12524 
12525 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
12526 #define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
12527 #define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
12528 #define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
12529 
12530 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
12531 #define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
12532 #define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
12533 #define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
12534 
12535 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
12536 #define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
12537 #define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
12538 #define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
12539 
12540 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
12541 #define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
12542 #define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
12543 #define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
12544 
12545 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
12546 #define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
12547 #define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
12548 #define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
12549 
12550 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
12551 #define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
12552 #define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
12553 #define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
12554 
12555 /*----------------------------------------------------------------------------*/
12556 
12557 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
12558 #define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
12559 #define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
12560 #define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
12561 
12562 #define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
12563 #define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12564 #define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12565 #define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12566 #define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12567 #define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12568 #define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12569 #define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12570 
12571 #define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
12572 #define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
12573 #define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
12574 
12575 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
12576 #define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
12577 #define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
12578 #define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
12579 
12580 #define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
12581 #define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12582 #define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12583 #define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12584 #define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12585 #define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12586 #define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12587 #define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12588 
12589 #define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
12590 #define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
12591 #define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
12592 
12593 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
12594 #define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
12595 #define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
12596 #define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
12597 
12598 #define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
12599 #define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12600 #define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12601 #define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12602 #define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12603 #define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12604 #define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12605 #define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12606 
12607 #define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
12608 #define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
12609 #define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
12610 
12611 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
12612 #define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
12613 #define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
12614 #define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
12615 
12616 #define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
12617 #define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12618 #define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12619 #define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12620 #define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12621 #define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12622 #define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12623 #define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12624 
12625 #define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
12626 #define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
12627 #define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
12628 
12629 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
12630 #define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
12631 #define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
12632 #define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
12633 
12634 #define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
12635 #define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12636 #define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12637 #define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12638 #define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12639 #define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12640 #define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12641 #define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12642 
12643 #define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
12644 #define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
12645 #define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
12646 
12647 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
12648 #define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
12649 #define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
12650 #define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
12651 
12652 #define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
12653 #define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12654 #define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12655 #define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12656 #define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12657 #define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12658 #define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12659 #define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12660 
12661 #define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
12662 #define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
12663 #define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
12664 
12665 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
12666 #define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
12667 #define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
12668 #define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
12669 
12670 #define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
12671 #define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12672 #define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12673 #define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12674 #define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12675 #define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12676 #define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12677 #define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12678 
12679 #define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
12680 #define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
12681 #define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
12682 
12683 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
12684 #define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
12685 #define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
12686 #define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
12687 
12688 #define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
12689 #define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
12690 #define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
12691 #define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
12692 #define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
12693 #define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
12694 #define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
12695 #define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
12696 
12697 #define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
12698 #define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
12699 #define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
12700 
12701 /*----------------------------------------------------------------------------*/
12702 
12703 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
12704 #define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12705 
12706 #define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12707 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12708 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12709 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12710 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12711 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12712 
12713 #define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12714 
12715 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
12716 #define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12717 
12718 #define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12719 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
12720 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12721 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12722 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12723 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12724 
12725 #define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12726 
12727 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
12728 #define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12729 
12730 #define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12731 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12732 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12733 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12734 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12735 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12736 
12737 #define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12738 
12739 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
12740 #define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12741 
12742 #define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12743 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12744 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12745 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12746 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12747 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12748 
12749 #define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12750 
12751 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
12752 #define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12753 
12754 #define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12755 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12756 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12757 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12758 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12759 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12760 
12761 #define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12762 
12763 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
12764 #define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12765 
12766 #define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12767 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12768 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12769 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12770 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12771 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12772 
12773 #define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12774 
12775 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
12776 #define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12777 
12778 #define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12779 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12780 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12781 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12782 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12783 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12784 
12785 #define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12786 
12787 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
12788 #define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12789 
12790 #define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12791 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12792 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12793 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12794 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12795 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12796 
12797 #define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12798 
12799 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
12800 #define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12801 
12802 #define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12803 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12804 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12805 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12806 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12807 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12808 
12809 #define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12810 
12811 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
12812 #define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12813 
12814 #define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12815 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12816 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12817 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12818 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12819 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12820 
12821 #define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12822 
12823 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
12824 #define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12825 
12826 #define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12827 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12828 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12829 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12830 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12831 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12832 
12833 #define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12834 
12835 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
12836 #define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12837 
12838 #define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12839 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12840 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12841 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12842 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12843 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12844 
12845 #define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12846 
12847 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
12848 #define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12849 
12850 #define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12851 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12852 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12853 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12854 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12855 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12856 
12857 #define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12858 
12859 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
12860 #define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12861 
12862 #define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12863 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12864 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12865 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12866 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12867 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12868 
12869 #define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12870 
12871 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
12872 #define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
12873 
12874 #define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
12875 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
12876 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
12877 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
12878 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
12879 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
12880 
12881 #define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
12882 
12883 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
12884 #define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
12885 
12886 #define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
12887 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
12888 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
12889 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
12890 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
12891 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
12892 
12893 #define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
12894 
12895 /******************************************************************************/
12896 /*                                                                            */
12897 /*                                    UCPD                                    */
12898 /*                                                                            */
12899 /******************************************************************************/
12900 /********************  Bits definition for UCPD_CFG1 register  *******************/
12901 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
12902 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
12903 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
12904 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
12905 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
12906 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
12907 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
12908 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
12909 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
12910 #define UCPD_CFG1_IFRGAP_Pos                (6U)
12911 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
12912 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
12913 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
12914 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
12915 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
12916 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
12917 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
12918 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
12919 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
12920 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
12921 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
12922 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
12923 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
12924 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
12925 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
12926 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
12927 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
12928 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
12929 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
12930 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
12931 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
12932 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
12933 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
12934 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
12935 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
12936 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
12937 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
12938 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
12939 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
12940 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
12941 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
12942 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
12943 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
12944 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
12945 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
12946 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
12947 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
12948 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
12949 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
12950 #define UCPD_CFG1_UCPDEN_Pos                (31U)
12951 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
12952 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
12953 
12954 /********************  Bits definition for UCPD_CFG2 register  *******************/
12955 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
12956 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
12957 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
12958 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
12959 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
12960 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
12961 #define UCPD_CFG2_FORCECLK_Pos              (2U)
12962 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
12963 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
12964 #define UCPD_CFG2_WUPEN_Pos                 (3U)
12965 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
12966 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
12967 
12968 /********************  Bits definition for UCPD_CR register  ********************/
12969 #define UCPD_CR_TXMODE_Pos                  (0U)
12970 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
12971 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
12972 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
12973 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
12974 #define UCPD_CR_TXSEND_Pos                  (2U)
12975 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
12976 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
12977 #define UCPD_CR_TXHRST_Pos                  (3U)
12978 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
12979 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
12980 #define UCPD_CR_RXMODE_Pos                  (4U)
12981 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
12982 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
12983 #define UCPD_CR_PHYRXEN_Pos                 (5U)
12984 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
12985 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
12986 #define UCPD_CR_PHYCCSEL_Pos                (6U)
12987 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
12988 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
12989 #define UCPD_CR_ANASUBMODE_Pos              (7U)
12990 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
12991 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
12992 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
12993 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
12994 #define UCPD_CR_ANAMODE_Pos                 (9U)
12995 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
12996 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
12997 #define UCPD_CR_CCENABLE_Pos                (10U)
12998 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
12999 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
13000 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
13001 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
13002 #define UCPD_CR_FRSRXEN_Pos                 (16U)
13003 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)       /*!< 0x00010000 */
13004 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                  /*!< Enable FRS request detection function */
13005 #define UCPD_CR_FRSTX_Pos                   (17U)
13006 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
13007 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
13008 #define UCPD_CR_RDCH_Pos                    (18U)
13009 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
13010 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
13011 #define UCPD_CR_CC1TCDIS_Pos                (20U)
13012 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
13013 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
13014 #define UCPD_CR_CC2TCDIS_Pos                (21U)
13015 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
13016 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
13017 
13018 /********************  Bits definition for UCPD_IMR register  *******************/
13019 #define UCPD_IMR_TXISIE_Pos                 (0U)
13020 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
13021 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
13022 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
13023 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
13024 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
13025 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
13026 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
13027 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
13028 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
13029 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
13030 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
13031 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
13032 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
13033 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
13034 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
13035 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
13036 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
13037 #define UCPD_IMR_TXUNDIE_Pos                (6U)
13038 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
13039 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
13040 #define UCPD_IMR_RXNEIE_Pos                 (8U)
13041 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
13042 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
13043 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
13044 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
13045 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
13046 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
13047 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
13048 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
13049 #define UCPD_IMR_RXOVRIE_Pos                (11U)
13050 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
13051 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
13052 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
13053 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
13054 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
13055 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
13056 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
13057 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
13058 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
13059 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
13060 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
13061 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
13062 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)     /*!< 0x00100000 */
13063 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                /*!< Fast Role Swap interrupt  */
13064 
13065 /********************  Bits definition for UCPD_SR register  ********************/
13066 #define UCPD_SR_TXIS_Pos                    (0U)
13067 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
13068 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
13069 #define UCPD_SR_TXMSGDISC_Pos               (1U)
13070 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
13071 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
13072 #define UCPD_SR_TXMSGSENT_Pos               (2U)
13073 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
13074 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
13075 #define UCPD_SR_TXMSGABT_Pos                (3U)
13076 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
13077 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
13078 #define UCPD_SR_HRSTDISC_Pos                (4U)
13079 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
13080 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
13081 #define UCPD_SR_HRSTSENT_Pos                (5U)
13082 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
13083 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
13084 #define UCPD_SR_TXUND_Pos                   (6U)
13085 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
13086 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
13087 #define UCPD_SR_RXNE_Pos                    (8U)
13088 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
13089 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
13090 #define UCPD_SR_RXORDDET_Pos                (9U)
13091 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
13092 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
13093 #define UCPD_SR_RXHRSTDET_Pos               (10U)
13094 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
13095 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
13096 #define UCPD_SR_RXOVR_Pos                   (11U)
13097 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
13098 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
13099 #define UCPD_SR_RXMSGEND_Pos                (12U)
13100 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
13101 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
13102 #define UCPD_SR_RXERR_Pos                   (13U)
13103 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
13104 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
13105 #define UCPD_SR_TYPECEVT1_Pos               (14U)
13106 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
13107 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
13108 #define UCPD_SR_TYPECEVT2_Pos               (15U)
13109 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
13110 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
13111 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
13112 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
13113 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
13114 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
13115 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
13116 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
13117 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
13118 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
13119 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
13120 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
13121 #define UCPD_SR_FRSEVT_Pos                  (20U)
13122 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)        /*!< 0x00100000 */
13123 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                   /*!< Fast Role Swap detection event  */
13124 
13125 /********************  Bits definition for UCPD_ICR register  *******************/
13126 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
13127 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
13128 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
13129 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
13130 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
13131 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
13132 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
13133 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
13134 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
13135 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
13136 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
13137 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
13138 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
13139 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
13140 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
13141 #define UCPD_ICR_TXUNDCF_Pos                (6U)
13142 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
13143 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
13144 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
13145 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
13146 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
13147 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
13148 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
13149 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
13150 #define UCPD_ICR_RXOVRCF_Pos                (11U)
13151 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
13152 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
13153 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
13154 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
13155 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
13156 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
13157 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
13158 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
13159 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
13160 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
13161 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
13162 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
13163 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)     /*!< 0x00100000 */
13164 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                /*!< Fast Role Swap event flag clear  */
13165 
13166 /********************  Bits definition for UCPD_TXORDSET register  **************/
13167 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
13168 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
13169 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
13170 
13171 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
13172 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
13173 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
13174 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
13175 
13176 /********************  Bits definition for UCPD_TXDR register  *******************/
13177 #define UCPD_TXDR_TXDATA_Pos                (0U)
13178 #define UCPD_TXDR_TXDATA_Msk                 (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
13179 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                  /*!< Tx Data Register */
13180 
13181 /********************  Bits definition for UCPD_RXORDSET register  **************/
13182 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
13183 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
13184 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
13185 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
13186 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
13187 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
13188 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
13189 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
13190 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
13191 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
13192 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
13193 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
13194 
13195 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
13196 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
13197 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
13198 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
13199 
13200 /********************  Bits definition for UCPD_RXDR register  *******************/
13201 #define UCPD_RXDR_RXDATA_Pos                (0U)
13202 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
13203 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
13204 
13205 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
13206 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
13207 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
13208 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
13209 
13210 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
13211 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
13212 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
13213 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
13214 
13215 /******************************************************************************/
13216 /*                                                                            */
13217 /*                            Window WATCHDOG                                 */
13218 /*                                                                            */
13219 /******************************************************************************/
13220 /*******************  Bit definition for WWDG_CR register  ********************/
13221 #define WWDG_CR_T_Pos           (0U)
13222 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
13223 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13224 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
13225 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
13226 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
13227 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
13228 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
13229 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
13230 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
13231 
13232 #define WWDG_CR_WDGA_Pos        (7U)
13233 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
13234 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
13235 
13236 /*******************  Bit definition for WWDG_CFR register  *******************/
13237 #define WWDG_CFR_W_Pos          (0U)
13238 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
13239 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
13240 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
13241 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
13242 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
13243 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
13244 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
13245 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
13246 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
13247 
13248 #define WWDG_CFR_WDGTB_Pos      (11U)
13249 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
13250 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
13251 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
13252 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
13253 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
13254 
13255 #define WWDG_CFR_EWI_Pos        (9U)
13256 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
13257 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
13258 
13259 /*******************  Bit definition for WWDG_SR register  ********************/
13260 #define WWDG_SR_EWIF_Pos        (0U)
13261 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
13262 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
13263 
13264 /**
13265   * @}
13266   */
13267 
13268 /**
13269   * @}
13270   */
13271 
13272 /** @addtogroup Exported_macros
13273   * @{
13274   */
13275 
13276 /******************************* ADC Instances ********************************/
13277 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
13278                                        ((INSTANCE) == ADC2) || \
13279                                        ((INSTANCE) == ADC3))
13280 
13281 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
13282 
13283 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
13284                                           ((INSTANCE) == ADC345_COMMON) )
13285 
13286 
13287 /******************************** FDCAN Instances ******************************/
13288 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
13289                                          ((INSTANCE) == FDCAN2))
13290 
13291 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
13292 /******************************** COMP Instances ******************************/
13293 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
13294                                         ((INSTANCE) == COMP2) || \
13295                                         ((INSTANCE) == COMP3) || \
13296                                         ((INSTANCE) == COMP4))
13297 
13298 /******************************* CORDIC Instances *****************************/
13299 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
13300 
13301 /******************************* CRC Instances ********************************/
13302 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
13303 
13304 /******************************* DAC Instances ********************************/
13305 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
13306                                        ((INSTANCE) == DAC3))
13307 
13308 
13309 /******************************** DMA Instances *******************************/
13310 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
13311                                        ((INSTANCE) == DMA1_Channel2) || \
13312                                        ((INSTANCE) == DMA1_Channel3) || \
13313                                        ((INSTANCE) == DMA1_Channel4) || \
13314                                        ((INSTANCE) == DMA1_Channel5) || \
13315                                        ((INSTANCE) == DMA1_Channel6) || \
13316                                        ((INSTANCE) == DMA1_Channel7) || \
13317                                        ((INSTANCE) == DMA1_Channel8) || \
13318                                        ((INSTANCE) == DMA2_Channel1) || \
13319                                        ((INSTANCE) == DMA2_Channel2) || \
13320                                        ((INSTANCE) == DMA2_Channel3) || \
13321                                        ((INSTANCE) == DMA2_Channel4) || \
13322                                        ((INSTANCE) == DMA2_Channel5) || \
13323                                        ((INSTANCE) == DMA2_Channel6) || \
13324                                        ((INSTANCE) == DMA2_Channel7) || \
13325                                        ((INSTANCE) == DMA2_Channel8))
13326 
13327 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
13328                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
13329                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
13330                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
13331 
13332 /******************************* FMAC Instances *******************************/
13333 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
13334 
13335 /******************************* GPIO Instances *******************************/
13336 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
13337                                         ((INSTANCE) == GPIOB) || \
13338                                         ((INSTANCE) == GPIOC) || \
13339                                         ((INSTANCE) == GPIOD) || \
13340                                         ((INSTANCE) == GPIOE) || \
13341                                         ((INSTANCE) == GPIOF) || \
13342                                         ((INSTANCE) == GPIOG))
13343 
13344 /******************************* GPIO AF Instances ****************************/
13345 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
13346 
13347 /**************************** GPIO Lock Instances *****************************/
13348 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
13349 
13350 /******************************** I2C Instances *******************************/
13351 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
13352                                        ((INSTANCE) == I2C2) || \
13353                                        ((INSTANCE) == I2C3) || \
13354                                        ((INSTANCE) == I2C4))
13355 
13356 /****************** I2C Instances : wakeup capability from stop modes *********/
13357 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
13358 
13359 /****************************** OPAMP Instances *******************************/
13360 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
13361                                          ((INSTANCE) == OPAMP2) || \
13362                                          ((INSTANCE) == OPAMP3))
13363 
13364 /******************************** PCD Instances *******************************/
13365 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
13366 
13367 /******************************* QSPI Instances *******************************/
13368 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
13369 
13370 /******************************* RNG Instances ********************************/
13371 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
13372 
13373 /****************************** RTC Instances *********************************/
13374 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
13375 
13376 #define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
13377 
13378 /****************************** SMBUS Instances *******************************/
13379 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
13380                                          ((INSTANCE) == I2C2) || \
13381                                          ((INSTANCE) == I2C3) || \
13382                                          ((INSTANCE) == I2C4))
13383 
13384 /******************************** SAI Instances *******************************/
13385 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
13386 
13387 /******************************** SPI Instances *******************************/
13388 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
13389                                        ((INSTANCE) == SPI2) || \
13390                                        ((INSTANCE) == SPI3) || \
13391                                        ((INSTANCE) == SPI4))
13392 
13393 /******************************** I2S Instances *******************************/
13394 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI2) || \
13395                                             ((__INSTANCE__) == SPI3))
13396 
13397 /****************** LPTIM Instances : All supported instances *****************/
13398 #define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
13399 
13400 /****************** LPTIM Instances : supporting encoder interface **************/
13401 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
13402 
13403 /****************** LPTIM Instances : All supported instances *****************/
13404 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
13405 
13406 /****************** TIM Instances : All supported instances *******************/
13407 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
13408                                          ((INSTANCE) == TIM2)   || \
13409                                          ((INSTANCE) == TIM3)   || \
13410                                          ((INSTANCE) == TIM4)   || \
13411                                          ((INSTANCE) == TIM6)   || \
13412                                          ((INSTANCE) == TIM7)   || \
13413                                          ((INSTANCE) == TIM8)   || \
13414                                          ((INSTANCE) == TIM15)  || \
13415                                          ((INSTANCE) == TIM16)  || \
13416                                          ((INSTANCE) == TIM17)  || \
13417                                          ((INSTANCE) == TIM20))
13418 
13419 /****************** TIM Instances : supporting 32 bits counter ****************/
13420 
13421 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
13422 
13423 /****************** TIM Instances : supporting the break function *************/
13424 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
13425                                             ((INSTANCE) == TIM8)    || \
13426                                             ((INSTANCE) == TIM15)   || \
13427                                             ((INSTANCE) == TIM16)   || \
13428                                             ((INSTANCE) == TIM17)   || \
13429                                             ((INSTANCE) == TIM20))
13430 
13431 /************** TIM Instances : supporting Break source selection *************/
13432 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13433                                                ((INSTANCE) == TIM8)   || \
13434                                                ((INSTANCE) == TIM15)  || \
13435                                                ((INSTANCE) == TIM16)  || \
13436                                                ((INSTANCE) == TIM17)  || \
13437                                                ((INSTANCE) == TIM20))
13438 
13439 /****************** TIM Instances : supporting 2 break inputs *****************/
13440 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
13441                                             ((INSTANCE) == TIM8)    || \
13442                                             ((INSTANCE) == TIM20))
13443 
13444 /************* TIM Instances : at least 1 capture/compare channel *************/
13445 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13446                                          ((INSTANCE) == TIM2)   || \
13447                                          ((INSTANCE) == TIM3)   || \
13448                                          ((INSTANCE) == TIM4)   || \
13449                                          ((INSTANCE) == TIM8)   || \
13450                                          ((INSTANCE) == TIM15)  || \
13451                                          ((INSTANCE) == TIM16)  || \
13452                                          ((INSTANCE) == TIM17)  || \
13453                                          ((INSTANCE) == TIM20))
13454 
13455 /************ TIM Instances : at least 2 capture/compare channels *************/
13456 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13457                                          ((INSTANCE) == TIM2)   || \
13458                                          ((INSTANCE) == TIM3)   || \
13459                                          ((INSTANCE) == TIM4)   || \
13460                                          ((INSTANCE) == TIM8)   || \
13461                                          ((INSTANCE) == TIM15)  || \
13462                                          ((INSTANCE) == TIM20))
13463 
13464 /************ TIM Instances : at least 3 capture/compare channels *************/
13465 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13466                                          ((INSTANCE) == TIM2)   || \
13467                                          ((INSTANCE) == TIM3)   || \
13468                                          ((INSTANCE) == TIM4)   || \
13469                                          ((INSTANCE) == TIM8)   || \
13470                                          ((INSTANCE) == TIM20))
13471 
13472 /************ TIM Instances : at least 4 capture/compare channels *************/
13473 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13474                                          ((INSTANCE) == TIM2)   || \
13475                                          ((INSTANCE) == TIM3)   || \
13476                                          ((INSTANCE) == TIM4)   || \
13477                                          ((INSTANCE) == TIM8)   || \
13478                                          ((INSTANCE) == TIM20))
13479 
13480 /****************** TIM Instances : at least 5 capture/compare channels *******/
13481 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13482                                          ((INSTANCE) == TIM8)   || \
13483                                          ((INSTANCE) == TIM20))
13484 
13485 /****************** TIM Instances : at least 6 capture/compare channels *******/
13486 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13487                                          ((INSTANCE) == TIM8)   || \
13488                                          ((INSTANCE) == TIM20))
13489 
13490 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
13491 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
13492                                             ((INSTANCE) == TIM8)   || \
13493                                             ((INSTANCE) == TIM15)  || \
13494                                             ((INSTANCE) == TIM16)  || \
13495                                             ((INSTANCE) == TIM17)  || \
13496                                             ((INSTANCE) == TIM20))
13497 
13498 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
13499 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
13500                                             ((INSTANCE) == TIM2)   || \
13501                                             ((INSTANCE) == TIM3)   || \
13502                                             ((INSTANCE) == TIM4)   || \
13503                                             ((INSTANCE) == TIM6)   || \
13504                                             ((INSTANCE) == TIM7)   || \
13505                                             ((INSTANCE) == TIM8)   || \
13506                                             ((INSTANCE) == TIM15)  || \
13507                                             ((INSTANCE) == TIM16)  || \
13508                                             ((INSTANCE) == TIM17)  || \
13509                                             ((INSTANCE) == TIM20))
13510 
13511 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
13512 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
13513                                             ((INSTANCE) == TIM2)   || \
13514                                             ((INSTANCE) == TIM3)   || \
13515                                             ((INSTANCE) == TIM4)   || \
13516                                             ((INSTANCE) == TIM8)   || \
13517                                             ((INSTANCE) == TIM15)  || \
13518                                             ((INSTANCE) == TIM16)  || \
13519                                             ((INSTANCE) == TIM17)  || \
13520                                             ((INSTANCE) == TIM20))
13521 
13522 /******************** TIM Instances : DMA burst feature ***********************/
13523 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13524                                             ((INSTANCE) == TIM2)   || \
13525                                             ((INSTANCE) == TIM3)   || \
13526                                             ((INSTANCE) == TIM4)   || \
13527                                             ((INSTANCE) == TIM8)   || \
13528                                             ((INSTANCE) == TIM15)  || \
13529                                             ((INSTANCE) == TIM16)  || \
13530                                             ((INSTANCE) == TIM17)  || \
13531                                             ((INSTANCE) == TIM20))
13532 
13533 /******************* TIM Instances : output(s) available **********************/
13534 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
13535     ((((INSTANCE) == TIM1) &&                  \
13536      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13537       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13538       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13539       ((CHANNEL) == TIM_CHANNEL_4) ||          \
13540       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13541       ((CHANNEL) == TIM_CHANNEL_6)))           \
13542      ||                                        \
13543      (((INSTANCE) == TIM2) &&                  \
13544      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13545       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13546       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13547       ((CHANNEL) == TIM_CHANNEL_4)))           \
13548      ||                                        \
13549      (((INSTANCE) == TIM3) &&                  \
13550      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13551       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13552       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13553       ((CHANNEL) == TIM_CHANNEL_4)))           \
13554      ||                                        \
13555      (((INSTANCE) == TIM4) &&                  \
13556      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13557       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13558       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13559       ((CHANNEL) == TIM_CHANNEL_4)))           \
13560      ||                                        \
13561      (((INSTANCE) == TIM8) &&                  \
13562      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13563       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13564       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13565       ((CHANNEL) == TIM_CHANNEL_4) ||          \
13566       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13567       ((CHANNEL) == TIM_CHANNEL_6)))           \
13568      ||                                        \
13569      (((INSTANCE) == TIM15) &&                 \
13570      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13571       ((CHANNEL) == TIM_CHANNEL_2)))           \
13572      ||                                        \
13573      (((INSTANCE) == TIM16) &&                 \
13574      (((CHANNEL) == TIM_CHANNEL_1)))           \
13575      ||                                        \
13576      (((INSTANCE) == TIM17) &&                 \
13577       (((CHANNEL) == TIM_CHANNEL_1)))          \
13578      ||                                        \
13579      (((INSTANCE) == TIM20) &&                 \
13580      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13581       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13582       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13583       ((CHANNEL) == TIM_CHANNEL_4) ||          \
13584       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13585       ((CHANNEL) == TIM_CHANNEL_6))))
13586 
13587 /****************** TIM Instances : supporting complementary output(s) ********/
13588 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
13589    ((((INSTANCE) == TIM1) &&                    \
13590      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13591       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13592       ((CHANNEL) == TIM_CHANNEL_3) ||           \
13593       ((CHANNEL) == TIM_CHANNEL_4)))            \
13594     ||                                          \
13595     (((INSTANCE) == TIM8) &&                    \
13596      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13597       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13598       ((CHANNEL) == TIM_CHANNEL_3) ||           \
13599       ((CHANNEL) == TIM_CHANNEL_4)))            \
13600     ||                                          \
13601     (((INSTANCE) == TIM15) &&                   \
13602      ((CHANNEL) == TIM_CHANNEL_1))              \
13603     ||                                          \
13604     (((INSTANCE) == TIM16) &&                   \
13605      ((CHANNEL) == TIM_CHANNEL_1))              \
13606     ||                                          \
13607     (((INSTANCE) == TIM17) &&                   \
13608      ((CHANNEL) == TIM_CHANNEL_1))              \
13609     ||                                          \
13610     (((INSTANCE) == TIM20) &&                   \
13611      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13612       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13613       ((CHANNEL) == TIM_CHANNEL_3) ||           \
13614       ((CHANNEL) == TIM_CHANNEL_4))))
13615 
13616 /****************** TIM Instances : supporting clock division *****************/
13617 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
13618                                                     ((INSTANCE) == TIM2)    || \
13619                                                     ((INSTANCE) == TIM3)    || \
13620                                                     ((INSTANCE) == TIM4)    || \
13621                                                     ((INSTANCE) == TIM8)    || \
13622                                                     ((INSTANCE) == TIM15)   || \
13623                                                     ((INSTANCE) == TIM16)   || \
13624                                                     ((INSTANCE) == TIM17)   || \
13625                                                     ((INSTANCE) == TIM20))
13626 
13627 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
13628 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13629                                                         ((INSTANCE) == TIM2) || \
13630                                                         ((INSTANCE) == TIM3) || \
13631                                                         ((INSTANCE) == TIM4) || \
13632                                                         ((INSTANCE) == TIM8) || \
13633                                                         ((INSTANCE) == TIM20))
13634 
13635 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
13636 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13637                                                         ((INSTANCE) == TIM2) || \
13638                                                         ((INSTANCE) == TIM3) || \
13639                                                         ((INSTANCE) == TIM4) || \
13640                                                         ((INSTANCE) == TIM8) || \
13641                                                         ((INSTANCE) == TIM20))
13642 
13643 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
13644 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
13645                                                         ((INSTANCE) == TIM2) || \
13646                                                         ((INSTANCE) == TIM3) || \
13647                                                         ((INSTANCE) == TIM4) || \
13648                                                         ((INSTANCE) == TIM8) || \
13649                                                         ((INSTANCE) == TIM15)|| \
13650                                                         ((INSTANCE) == TIM20))
13651 
13652 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
13653 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
13654                                                         ((INSTANCE) == TIM2) || \
13655                                                         ((INSTANCE) == TIM3) || \
13656                                                         ((INSTANCE) == TIM4) || \
13657                                                         ((INSTANCE) == TIM8) || \
13658                                                         ((INSTANCE) == TIM15)|| \
13659                                                         ((INSTANCE) == TIM20))
13660 
13661 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
13662 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13663                                                      ((INSTANCE) == TIM8)   || \
13664                                                      ((INSTANCE) == TIM20))
13665 
13666 /****************** TIM Instances : supporting commutation event generation ***/
13667 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13668                                                      ((INSTANCE) == TIM8)   || \
13669                                                      ((INSTANCE) == TIM15)  || \
13670                                                      ((INSTANCE) == TIM16)  || \
13671                                                      ((INSTANCE) == TIM17)  || \
13672                                                      ((INSTANCE) == TIM20))
13673 
13674 /****************** TIM Instances : supporting counting mode selection ********/
13675 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
13676                                                         ((INSTANCE) == TIM2) || \
13677                                                         ((INSTANCE) == TIM3) || \
13678                                                         ((INSTANCE) == TIM4) || \
13679                                                         ((INSTANCE) == TIM8) || \
13680                                                         ((INSTANCE) == TIM20))
13681 
13682 /****************** TIM Instances : supporting encoder interface **************/
13683 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
13684                                                       ((INSTANCE) == TIM2)  || \
13685                                                       ((INSTANCE) == TIM3)  || \
13686                                                       ((INSTANCE) == TIM4)  || \
13687                                                       ((INSTANCE) == TIM8)  || \
13688                                                       ((INSTANCE) == TIM20))
13689 
13690 /****************** TIM Instances : supporting Hall sensor interface **********/
13691 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13692                                                          ((INSTANCE) == TIM2)   || \
13693                                                          ((INSTANCE) == TIM3)   || \
13694                                                          ((INSTANCE) == TIM4)   || \
13695                                                          ((INSTANCE) == TIM8)   || \
13696                                                          ((INSTANCE) == TIM15)  || \
13697                                                          ((INSTANCE) == TIM20))
13698 
13699 /**************** TIM Instances : external trigger input available ************/
13700 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
13701                                             ((INSTANCE) == TIM2)  || \
13702                                             ((INSTANCE) == TIM3)  || \
13703                                             ((INSTANCE) == TIM4)  || \
13704                                             ((INSTANCE) == TIM8)  || \
13705                                             ((INSTANCE) == TIM20))
13706 
13707 /************* TIM Instances : supporting ETR source selection ***************/
13708 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
13709                                              ((INSTANCE) == TIM2)  || \
13710                                              ((INSTANCE) == TIM3)  || \
13711                                              ((INSTANCE) == TIM4)  || \
13712                                              ((INSTANCE) == TIM8)  || \
13713                                              ((INSTANCE) == TIM20))
13714 
13715 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
13716 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
13717                                             ((INSTANCE) == TIM2)  || \
13718                                             ((INSTANCE) == TIM3)  || \
13719                                             ((INSTANCE) == TIM4)  || \
13720                                             ((INSTANCE) == TIM6)  || \
13721                                             ((INSTANCE) == TIM7)  || \
13722                                             ((INSTANCE) == TIM8)  || \
13723                                             ((INSTANCE) == TIM15) || \
13724                                             ((INSTANCE) == TIM20))
13725 
13726 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
13727 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
13728                                             ((INSTANCE) == TIM2)  || \
13729                                             ((INSTANCE) == TIM3)  || \
13730                                             ((INSTANCE) == TIM4)  || \
13731                                             ((INSTANCE) == TIM8)  || \
13732                                             ((INSTANCE) == TIM15) || \
13733                                             ((INSTANCE) == TIM20))
13734 
13735 /****************** TIM Instances : supporting OCxREF clear *******************/
13736 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1)  || \
13737                                                        ((INSTANCE) == TIM2)  || \
13738                                                        ((INSTANCE) == TIM3)  || \
13739                                                        ((INSTANCE) == TIM4)  || \
13740                                                        ((INSTANCE) == TIM8)  || \
13741                                                        ((INSTANCE) == TIM15) || \
13742                                                        ((INSTANCE) == TIM16) || \
13743                                                        ((INSTANCE) == TIM17) || \
13744                                                        ((INSTANCE) == TIM20))
13745 
13746 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
13747 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
13748                                                        ((INSTANCE) == TIM2)  || \
13749                                                        ((INSTANCE) == TIM3)  || \
13750                                                        ((INSTANCE) == TIM8)  || \
13751                                                        ((INSTANCE) == TIM15) || \
13752                                                        ((INSTANCE) == TIM16) || \
13753                                                        ((INSTANCE) == TIM17) || \
13754                                                        ((INSTANCE) == TIM20))
13755 
13756 /****************** TIM Instances : remapping capability **********************/
13757 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
13758                                             ((INSTANCE) == TIM2)  || \
13759                                             ((INSTANCE) == TIM3)  || \
13760                                             ((INSTANCE) == TIM4)  || \
13761                                             ((INSTANCE) == TIM8)  || \
13762                                             ((INSTANCE) == TIM20))
13763 
13764 /****************** TIM Instances : supporting repetition counter *************/
13765 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
13766                                                        ((INSTANCE) == TIM8)  || \
13767                                                        ((INSTANCE) == TIM15) || \
13768                                                        ((INSTANCE) == TIM16) || \
13769                                                        ((INSTANCE) == TIM17) || \
13770                                                        ((INSTANCE) == TIM20))
13771 
13772 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
13773 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
13774                                             ((INSTANCE) == TIM8)    || \
13775                                             ((INSTANCE) == TIM20))
13776 
13777 /******************* TIM Instances : Timer input XOR function *****************/
13778 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
13779                                             ((INSTANCE) == TIM2)   || \
13780                                             ((INSTANCE) == TIM3)   || \
13781                                             ((INSTANCE) == TIM4)   || \
13782                                             ((INSTANCE) == TIM8)   || \
13783                                             ((INSTANCE) == TIM15)  || \
13784                                             ((INSTANCE) == TIM20))
13785 
13786 /******************* TIM Instances : Timer input selection ********************/
13787 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
13788                                          ((INSTANCE) == TIM2)   || \
13789                                          ((INSTANCE) == TIM3)   || \
13790                                          ((INSTANCE) == TIM4)   || \
13791                                          ((INSTANCE) == TIM8)   || \
13792                                          ((INSTANCE) == TIM15)  || \
13793                                          ((INSTANCE) == TIM16)  || \
13794                                          ((INSTANCE) == TIM17)  || \
13795                                          ((INSTANCE) == TIM20))
13796 
13797 /****************** TIM Instances : Advanced timer instances *******************/
13798 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
13799                                                   ((INSTANCE) == TIM8)   || \
13800                                                   ((INSTANCE) == TIM20))
13801 
13802 /****************** TIM Instances : supporting HSE/32 request instances *******************/
13803 #define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
13804                                                  ((INSTANCE) == TIM17))
13805 
13806 
13807 /******************** USART Instances : Synchronous mode **********************/
13808 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13809                                      ((INSTANCE) == USART2) || \
13810                                      ((INSTANCE) == USART3))
13811 
13812 /******************** UART Instances : Asynchronous mode **********************/
13813 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13814                                     ((INSTANCE) == USART2) || \
13815                                     ((INSTANCE) == USART3) || \
13816                                     ((INSTANCE) == UART4) || \
13817                                     ((INSTANCE) == UART5))
13818 
13819 /*********************** UART Instances : FIFO mode ***************************/
13820 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13821                                          ((INSTANCE) == USART2) || \
13822                                          ((INSTANCE) == USART3) || \
13823                                          ((INSTANCE) == UART4) || \
13824                                          ((INSTANCE) == UART5) || \
13825                                          ((INSTANCE) == LPUART1))
13826 
13827 /*********************** UART Instances : SPI Slave mode **********************/
13828 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13829                                               ((INSTANCE) == USART2) || \
13830                                               ((INSTANCE) == USART3))
13831 
13832 /****************** UART Instances : Auto Baud Rate detection ****************/
13833 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13834                                                             ((INSTANCE) == USART2) || \
13835                                                             ((INSTANCE) == USART3) || \
13836                                                             ((INSTANCE) == UART4)  || \
13837                                                             ((INSTANCE) == UART5))
13838 
13839 /****************** UART Instances : Driver Enable *****************/
13840 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
13841                                                       ((INSTANCE) == USART2) || \
13842                                                       ((INSTANCE) == USART3) || \
13843                                                       ((INSTANCE) == UART4)  || \
13844                                                       ((INSTANCE) == UART5)  || \
13845                                                       ((INSTANCE) == LPUART1))
13846 
13847 /******************** UART Instances : Half-Duplex mode **********************/
13848 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13849                                                  ((INSTANCE) == USART2) || \
13850                                                  ((INSTANCE) == USART3) || \
13851                                                  ((INSTANCE) == UART4)  || \
13852                                                  ((INSTANCE) == UART5)  || \
13853                                                  ((INSTANCE) == LPUART1))
13854 
13855 /****************** UART Instances : Hardware Flow control ********************/
13856 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13857                                            ((INSTANCE) == USART2) || \
13858                                            ((INSTANCE) == USART3) || \
13859                                            ((INSTANCE) == UART4)  || \
13860                                            ((INSTANCE) == UART5)  || \
13861                                            ((INSTANCE) == LPUART1))
13862 
13863 /******************** UART Instances : LIN mode **********************/
13864 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13865                                           ((INSTANCE) == USART2) || \
13866                                           ((INSTANCE) == USART3) || \
13867                                           ((INSTANCE) == UART4)  || \
13868                                           ((INSTANCE) == UART5))
13869 
13870 /******************** UART Instances : Wake-up from Stop mode **********************/
13871 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13872                                                       ((INSTANCE) == USART2) || \
13873                                                       ((INSTANCE) == USART3) || \
13874                                                       ((INSTANCE) == UART4)  || \
13875                                                       ((INSTANCE) == UART5)  || \
13876                                                       ((INSTANCE) == LPUART1))
13877 
13878 /*********************** UART Instances : IRDA mode ***************************/
13879 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13880                                     ((INSTANCE) == USART2) || \
13881                                     ((INSTANCE) == USART3) || \
13882                                     ((INSTANCE) == UART4)  || \
13883                                     ((INSTANCE) == UART5))
13884 
13885 /********************* USART Instances : Smard card mode ***********************/
13886 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13887                                          ((INSTANCE) == USART2) || \
13888                                          ((INSTANCE) == USART3))
13889 
13890 /******************** LPUART Instance *****************************************/
13891 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
13892 
13893 /****************************** IWDG Instances ********************************/
13894 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
13895 
13896 /****************************** WWDG Instances ********************************/
13897 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
13898 
13899 /****************************** UCPD Instances ********************************/
13900 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == UCPD1)
13901 
13902 /******************************* USB Instances *******************************/
13903 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
13904 
13905 /**
13906   * @}
13907   */
13908 
13909 
13910 /******************************************************************************/
13911 /*  For a painless codes migration between the STM32G4xx device product       */
13912 /*  lines, the aliases defined below are put in place to overcome the         */
13913 /*  differences in the interrupt handlers and IRQn definitions.               */
13914 /*  No need to update developed interrupt code when moving across             */
13915 /*  product lines within the same STM32G4 Family                              */
13916 /******************************************************************************/
13917 
13918 /* Aliases for __IRQn */
13919 #define TIM7_DAC_IRQn     TIM7_IRQn
13920 #define COMP4_5_6_IRQn    COMP4_IRQn
13921 
13922 /* Aliases for __IRQHandler */
13923 #define TIM7_DAC_IRQHandler     TIM7_IRQHandler
13924 #define COMP4_5_6_IRQHandler    COMP4_IRQHandler
13925 
13926 #ifdef __cplusplus
13927 }
13928 #endif /* __cplusplus */
13929 
13930 #endif /* __STM32G471xx_H */
13931 
13932 /**
13933   * @}
13934   */
13935 
13936   /**
13937   * @}
13938   */
13939 
13940