1 /**
2   ******************************************************************************
3   * @file    stm32g411xb.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32G411xB Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32g411xb
30   * @{
31   */
32 
33 #ifndef __STM32G411xB_H
34 #define __STM32G411xB_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32G4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
77 /******  STM32 specific Interrupt Numbers ***************************************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
80   RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
95   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
96   FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
97   FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
98   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
99   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
100   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
101   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
102   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
103   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
104   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
105   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
106   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
107   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
108   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
109   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
110   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
111   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
112   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
113   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
114   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
115   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
116   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
117   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
118   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
119   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
120   LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
121   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
122   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
123   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupts                                                             */
124   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
125   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
126   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
127   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
128   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
129   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
130   COMP4_IRQn                  = 65,     /*!< COMP4                                                                              */
131   CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
132   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
133   RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
134   LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
135   DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
136   DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
137   CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
138   FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
139 } IRQn_Type;
140 
141 /**
142   * @}
143   */
144 
145 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
146 #include "system_stm32g4xx.h"
147 #include <stdint.h>
148 
149 /** @addtogroup Peripheral_registers_structures
150   * @{
151   */
152 
153 /**
154   * @brief Analog to Digital Converter
155   */
156 
157 typedef struct
158 {
159   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
160   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
161   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
162   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
163   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
164   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
165   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
166        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
167   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
168   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
169   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
170        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
171   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
172   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
173   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
174   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
175   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
176        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
177        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
178   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
179        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
180   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
181   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
182   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
183   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
184        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
185   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
186   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
187   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
188   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
189        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
190   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
191   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
192        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
193        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
194   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
195   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
196        uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
197   __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
198 } ADC_TypeDef;
199 
200 typedef struct
201 {
202   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
203   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
204   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
205   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
206 } ADC_Common_TypeDef;
207 
208 /**
209   * @brief FD Controller Area Network
210   */
211 
212 typedef struct
213 {
214   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
215   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
216        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
217   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
218   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
219   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
220   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
221   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
222   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
223   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
224   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
225   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
226        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
227   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
228   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
229   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
230        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
231   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
232   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
233   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
234   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
235        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
236   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
237   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
238   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
239        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
240   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
241   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
242   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
243   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
244        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
245   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
246   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
247   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
248   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
249   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
250   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
251   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
252   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
253   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
254   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
255   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
256 } FDCAN_GlobalTypeDef;
257 
258 /**
259   * @brief FD Controller Area Network Configuration
260   */
261 
262 typedef struct
263 {
264   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
265 } FDCAN_Config_TypeDef;
266 
267 /**
268   * @brief Comparator
269   */
270 
271 typedef struct
272 {
273   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
274 } COMP_TypeDef;
275 
276 /**
277   * @brief CRC calculation unit
278   */
279 
280 typedef struct
281 {
282   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
283   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
284   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
285   uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
286   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
287   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
288 } CRC_TypeDef;
289 
290 /**
291   * @brief Clock Recovery System
292   */
293 typedef struct
294 {
295   __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
296   __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
297   __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
298   __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
299 } CRS_TypeDef;
300 
301 /**
302   * @brief Digital to Analog Converter
303   */
304 
305 typedef struct
306 {
307   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
308   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
309   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
310   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
311   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
312   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
313   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
314   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
315   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
316   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
317   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
318   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
319   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
320   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
321   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
322   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
323   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
324   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
325   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
326   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
327   __IO uint32_t RESERVED[2];
328   __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
329   __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
330   __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
331 } DAC_TypeDef;
332 
333 /**
334   * @brief Debug MCU
335   */
336 
337 typedef struct
338 {
339   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
340   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
341   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
342   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
343   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
344 } DBGMCU_TypeDef;
345 
346 /**
347   * @brief DMA Controller
348   */
349 
350 typedef struct
351 {
352   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
353   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
354   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
355   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
356 } DMA_Channel_TypeDef;
357 
358 typedef struct
359 {
360   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
361   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
362 } DMA_TypeDef;
363 
364 /**
365   * @brief DMA Multiplexer
366   */
367 
368 typedef struct
369 {
370   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
371 }DMAMUX_Channel_TypeDef;
372 
373 typedef struct
374 {
375   __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
376   __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
377 }DMAMUX_ChannelStatus_TypeDef;
378 
379 typedef struct
380 {
381   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
382 }DMAMUX_RequestGen_TypeDef;
383 
384 typedef struct
385 {
386   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
387   __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
388 }DMAMUX_RequestGenStatus_TypeDef;
389 
390 /**
391   * @brief External Interrupt/Event Controller
392   */
393 
394 typedef struct
395 {
396   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
397   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
398   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
399   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
400   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
401   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
402   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
403   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
404   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
405   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
406   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
407   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
408   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
409   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
410 } EXTI_TypeDef;
411 
412 /**
413   * @brief FLASH Registers
414   */
415 
416 typedef struct
417 {
418   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
419   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
420   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
421   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
422   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
423   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
424   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
425        uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
426   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
427   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
428   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
429   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
430   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
431        uint32_t RESERVED2[15];    /*!< Reserved2,                                Address offset: 0x34 */
432   __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
433 } FLASH_TypeDef;
434 
435 /**
436   * @brief FMAC
437   */
438 typedef struct
439 {
440   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
441   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
442   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
443   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
444   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
445   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
446   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
447   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
448 } FMAC_TypeDef;
449 
450 
451 /**
452   * @brief General Purpose I/O
453   */
454 
455 typedef struct
456 {
457   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
458   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
459   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
460   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
461   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
462   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
463   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
464   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
465   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
466   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
467 } GPIO_TypeDef;
468 
469 /**
470   * @brief Inter-integrated Circuit Interface
471   */
472 
473 typedef struct
474 {
475   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
476   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
477   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
478   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
479   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
480   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
481   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
482   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
483   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
484   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
485   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
486 } I2C_TypeDef;
487 
488 /**
489   * @brief Independent WATCHDOG
490   */
491 
492 typedef struct
493 {
494   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
495   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
496   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
497   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
498   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
499 } IWDG_TypeDef;
500 
501 /**
502   * @brief LPTIMER
503   */
504 
505 typedef struct
506 {
507   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
508   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
509   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
510   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
511   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
512   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
513   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
514   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
515   __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
516 } LPTIM_TypeDef;
517 
518 /**
519   * @brief Operational Amplifier (OPAMP)
520   */
521 
522 typedef struct
523 {
524   __IO uint32_t CSR;           /*!< OPAMP control/status register,                     Address offset: 0x00 */
525   __IO uint32_t RESERVED[5];   /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
526   __IO uint32_t TCMR;          /*!< OPAMP timer controlled mux mode register,          Address offset: 0x18 */
527 } OPAMP_TypeDef;
528 
529 /**
530   * @brief Power Control
531   */
532 
533 typedef struct
534 {
535   __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
536   __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
537   __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
538   __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
539   __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
540   __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
541   __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
542   uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
543   __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
544   __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
545   __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
546   __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
547   __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
548   __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
549   __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
550   __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
551   __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
552   __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
553   __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
554   __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
555   __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
556   __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
557   uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
558   __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
559 } PWR_TypeDef;
560 
561 
562 /**
563   * @brief Reset and Clock Control
564   */
565 
566 typedef struct
567 {
568   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
569   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
570   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
571   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
572   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
573   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
574   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
575   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
576   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
577   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
578   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
579   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
580   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
581   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
582   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
583   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
584   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
585   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
586   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
587   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
588   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
589   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
590   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
591   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
592   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
593   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
594   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
595   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
596   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
597   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
598   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
599   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
600   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
601   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
602   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
603   uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
604   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
605   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
606   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
607   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
608 } RCC_TypeDef;
609 
610 /**
611   * @brief Real-Time Clock
612   */
613 /*
614 * @brief Specific device feature definitions
615 */
616 #define RTC_TAMP_INT_6_SUPPORT
617 #define RTC_TAMP_INT_NB        4u
618 
619 #define RTC_TAMP_NB            3u
620 #define RTC_BACKUP_NB          16u
621 
622 
623 typedef struct
624 {
625   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
626   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
627   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
628   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
629   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
630   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
631   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
632        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
633        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
634   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
635   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
636   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
637   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
638   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
639   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
640        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
641   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
642   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
643   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
644   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
645   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
646   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
647        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
648   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
649 } RTC_TypeDef;
650 
651 /**
652   * @brief Tamper and backup registers
653   */
654 
655 typedef struct
656 {
657   __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
658   __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
659        uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
660   __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
661        uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
662        uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
663   __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
664   __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
665   __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
666        uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
667   __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
668        uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
669   __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
670   __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
671   __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
672   __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
673   __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
674   __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
675   __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
676   __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
677   __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
678   __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
679   __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
680   __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
681   __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
682   __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
683   __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
684   __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
685 } TAMP_TypeDef;
686 
687 
688 /**
689   * @brief Serial Peripheral Interface
690   */
691 
692 typedef struct
693 {
694   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
695   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
696   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
697   __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
698   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
699   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
700   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
701   __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
702   __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
703 } SPI_TypeDef;
704 
705 /**
706   * @brief System configuration controller
707   */
708 
709 typedef struct
710 {
711   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
712   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
713   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
714   __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
715   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
716   __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
717   __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
718 } SYSCFG_TypeDef;
719 
720 /**
721   * @brief TIM
722   */
723 
724 typedef struct
725 {
726   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
727   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
728   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
729   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
730   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
731   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
732   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
733   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
734   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
735   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
736   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
737   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
738   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
739   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
740   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
741   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
742   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
743   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
744   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
745   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
746   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
747   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
748   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
749   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
750   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
751   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
752   __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
753        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
754   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
755   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
756 } TIM_TypeDef;
757 
758 /**
759   * @brief Universal Synchronous Asynchronous Receiver Transmitter
760   */
761 typedef struct
762 {
763   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
764   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
765   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
766   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
767   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
768   __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
769   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
770   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
771   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
772   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
773   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
774   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
775 } USART_TypeDef;
776 
777 
778 
779 /**
780   * @brief Window WATCHDOG
781   */
782 
783 typedef struct
784 {
785   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
786   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
787   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
788 } WWDG_TypeDef;
789 
790 
791 /**
792   * @brief RNG
793   */
794 typedef struct
795 {
796   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
797   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
798   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
799 } RNG_TypeDef;
800 
801 /**
802   * @brief CORDIC
803   */
804 
805 typedef struct
806 {
807   __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
808   __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
809   __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
810 } CORDIC_TypeDef;
811 
812 
813 
814 /**
815   * @}
816   */
817 
818 /** @addtogroup Peripheral_memory_map
819   * @{
820   */
821 
822 #define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 128 kB) base address */
823 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */
824 #define SRAM2_BASE            (0x20004000UL) /*!< SRAM2(6 KB) base address */
825 #define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(10 KB) base address */
826 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
827 
828 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */
829 #define SRAM2_BB_BASE         (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */
830 #define CCMSRAM_BB_BASE       (0x22300000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */
831 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
832 /* Legacy defines */
833 #define SRAM_BASE             SRAM1_BASE
834 #define SRAM_BB_BASE          SRAM1_BB_BASE
835 
836 #define SRAM1_SIZE_MAX        (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */
837 #define SRAM2_SIZE            (0x00001800UL) /*!< SRAM2 size (6 KBytes) */
838 #define CCMSRAM_SIZE          (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */
839 
840 /*!< Peripheral memory map */
841 #define APB1PERIPH_BASE        PERIPH_BASE
842 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
843 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
844 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
845 
846 
847 /*!< APB1 peripherals */
848 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
849 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
850 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
851 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
852 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
853 #define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
854 #define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
855 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
856 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
857 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
858 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
859 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
860 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
861 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
862 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
863 #define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
864 #define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
865 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
866 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
867 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
868 #define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
869 
870 /*!< APB2 peripherals */
871 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
872 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
873 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
874 #define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
875 #define OPAMP_BASE            (APB2PERIPH_BASE + 0x0300UL)
876 #define OPAMP1_BASE           (APB2PERIPH_BASE + 0x0300UL)
877 
878 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
879 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
880 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
881 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
882 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
883 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
884 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
885 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
886 
887 /*!< AHB1 peripherals */
888 #define DMA1_BASE             (AHB1PERIPH_BASE)
889 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
890 #define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
891 #define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
892 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
893 #define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
894 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
895 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
896 
897 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
898 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
899 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
900 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
901 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
902 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
903 
904 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
905 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
906 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
907 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
908 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
909 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
910 
911 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
912 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
913 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
914 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
915 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
916 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
917 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0020UL)
918 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0024UL)
919 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0028UL)
920 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x002CUL)
921 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0030UL)
922 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0034UL)
923 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
924 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
925 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
926 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
927 
928 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
929 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
930 
931 /*!< AHB2 peripherals */
932 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
933 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
934 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
935 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
936 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
937 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
938 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
939 
940 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
941 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
942 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
943 
944 #define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
945 #define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
946 #define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
947 
948 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
949 /* Debug MCU registers base address */
950 #define DBGMCU_BASE           (0xE0042000UL)
951 
952 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
953 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
954 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
955 /**
956   * @}
957   */
958 
959 /** @addtogroup Peripheral_declaration
960   * @{
961   */
962 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
963 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
964 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
965 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
966 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
967 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
968 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
969 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
970 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
971 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
972 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
973 #define USART2              ((USART_TypeDef *) USART2_BASE)
974 #define UART4               ((USART_TypeDef *) UART4_BASE)
975 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
976 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
977 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
978 #define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
979 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
980 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
981 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
982 
983 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
984 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
985 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
986 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
987 
988 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
989 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
990 
991 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
992 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
993 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
994 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
995 #define USART1              ((USART_TypeDef *) USART1_BASE)
996 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
997 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
998 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
999 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1000 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1001 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1002 #define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
1003 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1004 #define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
1005 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1006 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1007 
1008 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1009 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1010 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1011 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1012 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1013 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1014 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1015 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1016 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1017 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1018 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1019 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1020 #define DAC3                ((DAC_TypeDef *) DAC3_BASE)
1021 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1022 
1023 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1024 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1025 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1026 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1027 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1028 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1029 
1030 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1031 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1032 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1033 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1034 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1035 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1036 
1037 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1038 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1039 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1040 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1041 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1042 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1043 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1044 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1045 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1046 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1047 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1048 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1049 
1050 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1051 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1052 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1053 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1054 
1055 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1056 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1057 
1058 
1059 
1060 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1061 
1062 /**
1063   * @}
1064   */
1065 
1066 /** @addtogroup Exported_constants
1067   * @{
1068   */
1069 
1070   /** @addtogroup Hardware_Constant_Definition
1071     * @{
1072     */
1073 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1074 
1075   /**
1076     * @}
1077     */
1078 
1079 /** @addtogroup Peripheral_Registers_Bits_Definition
1080   * @{
1081   */
1082 
1083 /******************************************************************************/
1084 /*                         Peripheral Registers_Bits_Definition               */
1085 /******************************************************************************/
1086 
1087 /******************************************************************************/
1088 /*                                                                            */
1089 /*                        Analog to Digital Converter                         */
1090 /*                                                                            */
1091 /******************************************************************************/
1092 
1093 /*
1094  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
1095  */
1096 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1097 
1098 /********************  Bit definition for ADC_ISR register  *******************/
1099 #define ADC_ISR_ADRDY_Pos              (0U)
1100 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1101 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1102 #define ADC_ISR_EOSMP_Pos              (1U)
1103 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1104 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1105 #define ADC_ISR_EOC_Pos                (2U)
1106 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1107 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1108 #define ADC_ISR_EOS_Pos                (3U)
1109 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1110 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1111 #define ADC_ISR_OVR_Pos                (4U)
1112 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1113 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1114 #define ADC_ISR_JEOC_Pos               (5U)
1115 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1116 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1117 #define ADC_ISR_JEOS_Pos               (6U)
1118 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1119 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1120 #define ADC_ISR_AWD1_Pos               (7U)
1121 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1122 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1123 #define ADC_ISR_AWD2_Pos               (8U)
1124 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1125 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1126 #define ADC_ISR_AWD3_Pos               (9U)
1127 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1128 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1129 #define ADC_ISR_JQOVF_Pos              (10U)
1130 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1131 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1132 
1133 /********************  Bit definition for ADC_IER register  *******************/
1134 #define ADC_IER_ADRDYIE_Pos            (0U)
1135 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1136 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1137 #define ADC_IER_EOSMPIE_Pos            (1U)
1138 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1139 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1140 #define ADC_IER_EOCIE_Pos              (2U)
1141 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1142 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1143 #define ADC_IER_EOSIE_Pos              (3U)
1144 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1145 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1146 #define ADC_IER_OVRIE_Pos              (4U)
1147 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1148 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1149 #define ADC_IER_JEOCIE_Pos             (5U)
1150 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1151 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1152 #define ADC_IER_JEOSIE_Pos             (6U)
1153 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1154 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1155 #define ADC_IER_AWD1IE_Pos             (7U)
1156 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1157 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1158 #define ADC_IER_AWD2IE_Pos             (8U)
1159 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1160 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1161 #define ADC_IER_AWD3IE_Pos             (9U)
1162 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1163 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1164 #define ADC_IER_JQOVFIE_Pos            (10U)
1165 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1166 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1167 
1168 /********************  Bit definition for ADC_CR register  ********************/
1169 #define ADC_CR_ADEN_Pos                (0U)
1170 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1171 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1172 #define ADC_CR_ADDIS_Pos               (1U)
1173 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1174 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1175 #define ADC_CR_ADSTART_Pos             (2U)
1176 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1177 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1178 #define ADC_CR_JADSTART_Pos            (3U)
1179 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1180 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1181 #define ADC_CR_ADSTP_Pos               (4U)
1182 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1183 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1184 #define ADC_CR_JADSTP_Pos              (5U)
1185 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1186 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1187 #define ADC_CR_ADVREGEN_Pos            (28U)
1188 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1189 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1190 #define ADC_CR_DEEPPWD_Pos             (29U)
1191 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1192 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1193 #define ADC_CR_ADCALDIF_Pos            (30U)
1194 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1195 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1196 #define ADC_CR_ADCAL_Pos               (31U)
1197 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1198 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1199 
1200 /********************  Bit definition for ADC_CFGR register  ******************/
1201 #define ADC_CFGR_DMAEN_Pos             (0U)
1202 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1203 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1204 #define ADC_CFGR_DMACFG_Pos            (1U)
1205 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1206 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1207 
1208 #define ADC_CFGR_RES_Pos               (3U)
1209 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1210 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1211 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1212 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1213 
1214 #define ADC_CFGR_EXTSEL_Pos            (5U)
1215 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1216 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1217 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1218 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1219 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1220 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1221 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1222 
1223 #define ADC_CFGR_EXTEN_Pos             (10U)
1224 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1225 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1226 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1227 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1228 
1229 #define ADC_CFGR_OVRMOD_Pos            (12U)
1230 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1231 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1232 #define ADC_CFGR_CONT_Pos              (13U)
1233 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1234 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1235 #define ADC_CFGR_AUTDLY_Pos            (14U)
1236 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1237 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1238 #define ADC_CFGR_ALIGN_Pos             (15U)
1239 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1240 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1241 #define ADC_CFGR_DISCEN_Pos            (16U)
1242 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1243 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1244 
1245 #define ADC_CFGR_DISCNUM_Pos           (17U)
1246 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1247 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1248 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1249 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1250 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1251 
1252 #define ADC_CFGR_JDISCEN_Pos           (20U)
1253 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1254 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1255 #define ADC_CFGR_JQM_Pos               (21U)
1256 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1257 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1258 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1259 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1260 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1261 #define ADC_CFGR_AWD1EN_Pos            (23U)
1262 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1263 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1264 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1265 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1266 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1267 #define ADC_CFGR_JAUTO_Pos             (25U)
1268 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1269 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1270 
1271 #define ADC_CFGR_AWD1CH_Pos            (26U)
1272 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1273 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1274 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1275 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1276 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1277 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1278 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1279 
1280 #define ADC_CFGR_JQDIS_Pos             (31U)
1281 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1282 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1283 
1284 /********************  Bit definition for ADC_CFGR2 register  *****************/
1285 #define ADC_CFGR2_ROVSE_Pos            (0U)
1286 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1287 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1288 #define ADC_CFGR2_JOVSE_Pos            (1U)
1289 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1290 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1291 
1292 #define ADC_CFGR2_OVSR_Pos             (2U)
1293 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1294 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1295 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1296 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1297 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1298 
1299 #define ADC_CFGR2_OVSS_Pos             (5U)
1300 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1301 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1302 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1303 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1304 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1305 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1306 
1307 #define ADC_CFGR2_TROVS_Pos            (9U)
1308 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1309 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1310 #define ADC_CFGR2_ROVSM_Pos            (10U)
1311 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1312 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1313 
1314 #define ADC_CFGR2_GCOMP_Pos            (16U)
1315 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1316 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1317 
1318 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1319 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1320 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1321 #define ADC_CFGR2_BULB_Pos             (26U)
1322 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1323 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1324 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1325 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1326 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1327 
1328 /********************  Bit definition for ADC_SMPR1 register  *****************/
1329 #define ADC_SMPR1_SMP0_Pos             (0U)
1330 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1331 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1332 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1333 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1334 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1335 
1336 #define ADC_SMPR1_SMP1_Pos             (3U)
1337 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1338 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1339 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1340 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1341 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1342 
1343 #define ADC_SMPR1_SMP2_Pos             (6U)
1344 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1345 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1346 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1347 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1348 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1349 
1350 #define ADC_SMPR1_SMP3_Pos             (9U)
1351 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1352 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1353 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1354 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1355 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1356 
1357 #define ADC_SMPR1_SMP4_Pos             (12U)
1358 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1359 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1360 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1361 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1362 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1363 
1364 #define ADC_SMPR1_SMP5_Pos             (15U)
1365 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1366 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1367 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1368 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1369 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1370 
1371 #define ADC_SMPR1_SMP6_Pos             (18U)
1372 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1373 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1374 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1375 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1376 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1377 
1378 #define ADC_SMPR1_SMP7_Pos             (21U)
1379 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1380 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1381 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1382 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1383 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1384 
1385 #define ADC_SMPR1_SMP8_Pos             (24U)
1386 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1387 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1388 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1389 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1390 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1391 
1392 #define ADC_SMPR1_SMP9_Pos             (27U)
1393 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1394 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1395 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1396 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1397 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1398 
1399 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1400 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1401 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1402 
1403 /********************  Bit definition for ADC_SMPR2 register  *****************/
1404 #define ADC_SMPR2_SMP10_Pos            (0U)
1405 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1406 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1407 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1408 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1409 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1410 
1411 #define ADC_SMPR2_SMP11_Pos            (3U)
1412 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1413 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1414 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1415 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1416 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1417 
1418 #define ADC_SMPR2_SMP12_Pos            (6U)
1419 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1420 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1421 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1422 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1423 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1424 
1425 #define ADC_SMPR2_SMP13_Pos            (9U)
1426 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1427 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1428 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1429 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1430 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1431 
1432 #define ADC_SMPR2_SMP14_Pos            (12U)
1433 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1434 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1435 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1436 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1437 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1438 
1439 #define ADC_SMPR2_SMP15_Pos            (15U)
1440 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1441 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1442 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1443 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1444 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1445 
1446 #define ADC_SMPR2_SMP16_Pos            (18U)
1447 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1448 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1449 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1450 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1451 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1452 
1453 #define ADC_SMPR2_SMP17_Pos            (21U)
1454 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1455 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1456 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1457 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1458 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1459 
1460 #define ADC_SMPR2_SMP18_Pos            (24U)
1461 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1462 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1463 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1464 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1465 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1466 
1467 /********************  Bit definition for ADC_TR1 register  *******************/
1468 #define ADC_TR1_LT1_Pos                (0U)
1469 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1470 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1471 
1472 #define ADC_TR1_AWDFILT_Pos            (12U)
1473 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
1474 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
1475 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
1476 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
1477 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
1478 
1479 #define ADC_TR1_HT1_Pos                (16U)
1480 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1481 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
1482 
1483 /********************  Bit definition for ADC_TR2 register  *******************/
1484 #define ADC_TR2_LT2_Pos                (0U)
1485 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1486 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1487 
1488 #define ADC_TR2_HT2_Pos                (16U)
1489 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1490 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1491 
1492 /********************  Bit definition for ADC_TR3 register  *******************/
1493 #define ADC_TR3_LT3_Pos                (0U)
1494 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1495 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1496 
1497 #define ADC_TR3_HT3_Pos                (16U)
1498 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1499 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1500 
1501 /********************  Bit definition for ADC_SQR1 register  ******************/
1502 #define ADC_SQR1_L_Pos                 (0U)
1503 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1504 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1505 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1506 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1507 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1508 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1509 
1510 #define ADC_SQR1_SQ1_Pos               (6U)
1511 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1512 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1513 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1514 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1515 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1516 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1517 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1518 
1519 #define ADC_SQR1_SQ2_Pos               (12U)
1520 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1521 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1522 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1523 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1524 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1525 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1526 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1527 
1528 #define ADC_SQR1_SQ3_Pos               (18U)
1529 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1530 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1531 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1532 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1533 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1534 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1535 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1536 
1537 #define ADC_SQR1_SQ4_Pos               (24U)
1538 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1539 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1540 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1541 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1542 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1543 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1544 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1545 
1546 /********************  Bit definition for ADC_SQR2 register  ******************/
1547 #define ADC_SQR2_SQ5_Pos               (0U)
1548 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1549 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1550 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1551 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1552 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1553 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1554 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1555 
1556 #define ADC_SQR2_SQ6_Pos               (6U)
1557 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1558 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1559 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1560 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1561 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1562 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1563 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1564 
1565 #define ADC_SQR2_SQ7_Pos               (12U)
1566 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1567 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1568 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1569 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1570 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1571 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1572 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1573 
1574 #define ADC_SQR2_SQ8_Pos               (18U)
1575 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1576 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1577 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1578 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1579 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1580 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1581 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1582 
1583 #define ADC_SQR2_SQ9_Pos               (24U)
1584 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1585 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1586 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1587 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1588 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1589 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1590 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1591 
1592 /********************  Bit definition for ADC_SQR3 register  ******************/
1593 #define ADC_SQR3_SQ10_Pos              (0U)
1594 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1595 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1596 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1597 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1598 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1599 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1600 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1601 
1602 #define ADC_SQR3_SQ11_Pos              (6U)
1603 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1604 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1605 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1606 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1607 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1608 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1609 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1610 
1611 #define ADC_SQR3_SQ12_Pos              (12U)
1612 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1613 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1614 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1615 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1616 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1617 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1618 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1619 
1620 #define ADC_SQR3_SQ13_Pos              (18U)
1621 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1622 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1623 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1624 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1625 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1626 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1627 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1628 
1629 #define ADC_SQR3_SQ14_Pos              (24U)
1630 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1631 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1632 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1633 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1634 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1635 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1636 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1637 
1638 /********************  Bit definition for ADC_SQR4 register  ******************/
1639 #define ADC_SQR4_SQ15_Pos              (0U)
1640 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1641 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1642 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1643 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1644 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1645 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1646 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1647 
1648 #define ADC_SQR4_SQ16_Pos              (6U)
1649 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1650 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1651 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1652 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1653 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1654 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1655 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1656 
1657 /********************  Bit definition for ADC_DR register  ********************/
1658 #define ADC_DR_RDATA_Pos               (0U)
1659 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1660 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1661 
1662 /********************  Bit definition for ADC_JSQR register  ******************/
1663 #define ADC_JSQR_JL_Pos                (0U)
1664 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1665 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1666 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1667 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1668 
1669 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1670 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
1671 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1672 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1673 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1674 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1675 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1676 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
1677 
1678 #define ADC_JSQR_JEXTEN_Pos            (7U)
1679 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
1680 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1681 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1682 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
1683 
1684 #define ADC_JSQR_JSQ1_Pos              (9U)
1685 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
1686 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1687 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1688 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1689 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1690 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1691 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
1692 
1693 #define ADC_JSQR_JSQ2_Pos              (15U)
1694 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1695 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1696 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1697 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1698 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1699 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1700 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1701 
1702 #define ADC_JSQR_JSQ3_Pos              (21U)
1703 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
1704 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1705 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1706 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1707 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1708 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1709 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
1710 
1711 #define ADC_JSQR_JSQ4_Pos              (27U)
1712 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
1713 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1714 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1715 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1716 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1717 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1718 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
1719 
1720 /********************  Bit definition for ADC_OFR1 register  ******************/
1721 #define ADC_OFR1_OFFSET1_Pos           (0U)
1722 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1723 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1724 
1725 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
1726 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
1727 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
1728 #define ADC_OFR1_SATEN_Pos             (25U)
1729 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
1730 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
1731 
1732 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1733 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1734 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1735 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1736 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1737 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1738 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1739 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1740 
1741 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1742 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1743 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1744 
1745 /********************  Bit definition for ADC_OFR2 register  ******************/
1746 #define ADC_OFR2_OFFSET2_Pos           (0U)
1747 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1748 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1749 
1750 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
1751 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
1752 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
1753 #define ADC_OFR2_SATEN_Pos             (25U)
1754 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
1755 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
1756 
1757 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1758 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1759 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1760 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1761 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1762 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1763 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1764 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1765 
1766 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1767 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1768 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1769 
1770 /********************  Bit definition for ADC_OFR3 register  ******************/
1771 #define ADC_OFR3_OFFSET3_Pos           (0U)
1772 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1773 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1774 
1775 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
1776 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
1777 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
1778 #define ADC_OFR3_SATEN_Pos             (25U)
1779 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
1780 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
1781 
1782 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1783 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1784 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1785 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
1786 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
1787 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
1788 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
1789 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
1790 
1791 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1792 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
1793 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1794 
1795 /********************  Bit definition for ADC_OFR4 register  ******************/
1796 #define ADC_OFR4_OFFSET4_Pos           (0U)
1797 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
1798 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1799 
1800 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
1801 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
1802 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
1803 #define ADC_OFR4_SATEN_Pos             (25U)
1804 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
1805 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
1806 
1807 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1808 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
1809 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1810 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
1811 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
1812 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
1813 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
1814 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
1815 
1816 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1817 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
1818 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1819 
1820 /********************  Bit definition for ADC_JDR1 register  ******************/
1821 #define ADC_JDR1_JDATA_Pos             (0U)
1822 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
1823 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1824 
1825 /********************  Bit definition for ADC_JDR2 register  ******************/
1826 #define ADC_JDR2_JDATA_Pos             (0U)
1827 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
1828 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1829 
1830 /********************  Bit definition for ADC_JDR3 register  ******************/
1831 #define ADC_JDR3_JDATA_Pos             (0U)
1832 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
1833 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
1834 
1835 /********************  Bit definition for ADC_JDR4 register  ******************/
1836 #define ADC_JDR4_JDATA_Pos             (0U)
1837 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
1838 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
1839 
1840 /********************  Bit definition for ADC_AWD2CR register  ****************/
1841 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1842 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1843 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1844 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1845 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1846 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1847 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1848 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1849 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1850 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1851 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1852 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1853 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1854 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1855 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1856 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1857 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1858 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1859 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1860 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1861 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1862 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1863 
1864 /********************  Bit definition for ADC_AWD3CR register  ****************/
1865 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1866 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1867 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1868 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1869 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1870 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1871 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1872 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1873 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1874 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1875 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1876 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1877 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1878 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1879 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1880 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1881 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1882 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1883 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1884 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1885 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1886 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1887 
1888 /********************  Bit definition for ADC_DIFSEL register  ****************/
1889 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
1890 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
1891 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
1892 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
1893 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
1894 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
1895 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
1896 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
1897 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
1898 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
1899 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
1900 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
1901 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
1902 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
1903 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
1904 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
1905 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
1906 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
1907 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
1908 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
1909 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
1910 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
1911 
1912 /********************  Bit definition for ADC_CALFACT register  ***************/
1913 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
1914 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
1915 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
1916 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
1917 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
1918 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
1919 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
1920 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
1921 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
1922 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
1923 
1924 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
1925 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
1926 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
1927 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
1928 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
1929 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
1930 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
1931 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
1932 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
1933 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
1934 
1935 /********************  Bit definition for ADC_GCOMP register  *****************/
1936 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
1937 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
1938 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
1939 
1940 /*************************  ADC Common registers  *****************************/
1941 /********************  Bit definition for ADC_CSR register  *******************/
1942 #define ADC_CSR_ADRDY_MST_Pos          (0U)
1943 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
1944 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
1945 #define ADC_CSR_EOSMP_MST_Pos          (1U)
1946 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
1947 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
1948 #define ADC_CSR_EOC_MST_Pos            (2U)
1949 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
1950 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
1951 #define ADC_CSR_EOS_MST_Pos            (3U)
1952 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
1953 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
1954 #define ADC_CSR_OVR_MST_Pos            (4U)
1955 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
1956 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
1957 #define ADC_CSR_JEOC_MST_Pos           (5U)
1958 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
1959 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
1960 #define ADC_CSR_JEOS_MST_Pos           (6U)
1961 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
1962 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
1963 #define ADC_CSR_AWD1_MST_Pos           (7U)
1964 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
1965 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
1966 #define ADC_CSR_AWD2_MST_Pos           (8U)
1967 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
1968 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
1969 #define ADC_CSR_AWD3_MST_Pos           (9U)
1970 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
1971 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
1972 #define ADC_CSR_JQOVF_MST_Pos          (10U)
1973 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
1974 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
1975 
1976 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
1977 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
1978 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
1979 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
1980 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
1981 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
1982 #define ADC_CSR_EOC_SLV_Pos            (18U)
1983 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
1984 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
1985 #define ADC_CSR_EOS_SLV_Pos            (19U)
1986 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
1987 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
1988 #define ADC_CSR_OVR_SLV_Pos            (20U)
1989 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
1990 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
1991 #define ADC_CSR_JEOC_SLV_Pos           (21U)
1992 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
1993 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
1994 #define ADC_CSR_JEOS_SLV_Pos           (22U)
1995 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
1996 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
1997 #define ADC_CSR_AWD1_SLV_Pos           (23U)
1998 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
1999 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2000 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2001 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2002 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2003 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2004 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2005 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2006 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2007 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2008 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2009 
2010 /********************  Bit definition for ADC_CCR register  *******************/
2011 #define ADC_CCR_DUAL_Pos               (0U)
2012 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2013 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2014 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2015 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2016 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2017 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2018 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2019 
2020 #define ADC_CCR_DELAY_Pos              (8U)
2021 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2022 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2023 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2024 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2025 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2026 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2027 
2028 #define ADC_CCR_DMACFG_Pos             (13U)
2029 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2030 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2031 
2032 #define ADC_CCR_MDMA_Pos               (14U)
2033 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2034 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2035 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2036 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2037 
2038 #define ADC_CCR_CKMODE_Pos             (16U)
2039 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2040 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2041 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2042 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2043 
2044 #define ADC_CCR_PRESC_Pos              (18U)
2045 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2046 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2047 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2048 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2049 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2050 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2051 
2052 #define ADC_CCR_VREFEN_Pos             (22U)
2053 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2054 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2055 #define ADC_CCR_VSENSESEL_Pos          (23U)
2056 #define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
2057 #define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
2058 #define ADC_CCR_VBATSEL_Pos            (24U)
2059 #define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
2060 #define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
2061 
2062 /********************  Bit definition for ADC_CDR register  *******************/
2063 #define ADC_CDR_RDATA_MST_Pos          (0U)
2064 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2065 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2066 
2067 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2068 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2069 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2070 
2071 
2072 /******************************************************************************/
2073 /*                                                                            */
2074 /*                      Analog Comparators (COMP)                             */
2075 /*                                                                            */
2076 /******************************************************************************/
2077 /**********************  Bit definition for COMP_CSR register  ****************/
2078 #define COMP_CSR_EN_Pos            (0U)
2079 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
2080 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
2081 
2082 #define COMP_CSR_INMSEL_Pos        (4U)
2083 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
2084 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
2085 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
2086 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
2087 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
2088 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
2089 
2090 #define COMP_CSR_INPSEL_Pos        (8U)
2091 #define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
2092 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
2093 
2094 #define COMP_CSR_POLARITY_Pos      (15U)
2095 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
2096 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
2097 
2098 #define COMP_CSR_HYST_Pos          (16U)
2099 #define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
2100 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
2101 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
2102 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
2103 #define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
2104 
2105 #define COMP_CSR_BLANKING_Pos      (19U)
2106 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
2107 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
2108 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
2109 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
2110 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
2111 
2112 #define COMP_CSR_BRGEN_Pos         (22U)
2113 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
2114 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
2115 
2116 #define COMP_CSR_SCALEN_Pos        (23U)
2117 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
2118 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
2119 
2120 #define COMP_CSR_VALUE_Pos         (30U)
2121 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
2122 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
2123 
2124 #define COMP_CSR_LOCK_Pos          (31U)
2125 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
2126 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
2127 
2128 /******************************************************************************/
2129 /*                                                                            */
2130 /*                          CORDIC calculation unit                           */
2131 /*                                                                            */
2132 /******************************************************************************/
2133 /*******************  Bit definition for CORDIC_CSR register  *****************/
2134 #define CORDIC_CSR_FUNC_Pos      (0U)
2135 #define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
2136 #define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
2137 #define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
2138 #define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
2139 #define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
2140 #define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
2141 #define CORDIC_CSR_PRECISION_Pos (4U)
2142 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
2143 #define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
2144 #define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
2145 #define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
2146 #define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
2147 #define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
2148 #define CORDIC_CSR_SCALE_Pos     (8U)
2149 #define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
2150 #define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
2151 #define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
2152 #define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
2153 #define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
2154 #define CORDIC_CSR_IEN_Pos       (16U)
2155 #define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
2156 #define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
2157 #define CORDIC_CSR_DMAREN_Pos    (17U)
2158 #define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
2159 #define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
2160 #define CORDIC_CSR_DMAWEN_Pos    (18U)
2161 #define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
2162 #define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
2163 #define CORDIC_CSR_NRES_Pos      (19U)
2164 #define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
2165 #define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
2166 #define CORDIC_CSR_NARGS_Pos     (20U)
2167 #define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
2168 #define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
2169 #define CORDIC_CSR_RESSIZE_Pos   (21U)
2170 #define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
2171 #define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
2172 #define CORDIC_CSR_ARGSIZE_Pos   (22U)
2173 #define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
2174 #define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
2175 #define CORDIC_CSR_RRDY_Pos      (31U)
2176 #define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
2177 #define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
2178 
2179 /*******************  Bit definition for CORDIC_WDATA register  ***************/
2180 #define CORDIC_WDATA_ARG_Pos     (0U)
2181 #define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
2182 #define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
2183 
2184 /*******************  Bit definition for CORDIC_RDATA register  ***************/
2185 #define CORDIC_RDATA_RES_Pos     (0U)
2186 #define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
2187 #define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
2188 
2189 /******************************************************************************/
2190 /*                                                                            */
2191 /*                          CRC calculation unit                              */
2192 /*                                                                            */
2193 /******************************************************************************/
2194 /*******************  Bit definition for CRC_DR register  *********************/
2195 #define CRC_DR_DR_Pos            (0U)
2196 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2197 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2198 
2199 /*******************  Bit definition for CRC_IDR register  ********************/
2200 #define CRC_IDR_IDR_Pos          (0U)
2201 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
2202 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
2203 
2204 /********************  Bit definition for CRC_CR register  ********************/
2205 #define CRC_CR_RESET_Pos         (0U)
2206 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2207 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2208 #define CRC_CR_POLYSIZE_Pos      (3U)
2209 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2210 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2211 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2212 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2213 #define CRC_CR_REV_IN_Pos        (5U)
2214 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2215 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2216 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2217 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2218 #define CRC_CR_REV_OUT_Pos       (7U)
2219 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2220 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2221 
2222 /*******************  Bit definition for CRC_INIT register  *******************/
2223 #define CRC_INIT_INIT_Pos        (0U)
2224 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2225 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2226 
2227 /*******************  Bit definition for CRC_POL register  ********************/
2228 #define CRC_POL_POL_Pos          (0U)
2229 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2230 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2231 
2232 /******************************************************************************/
2233 /*                                                                            */
2234 /*                          CRS Clock Recovery System                         */
2235 /******************************************************************************/
2236 
2237 /*******************  Bit definition for CRS_CR register  *********************/
2238 #define CRS_CR_SYNCOKIE_Pos       (0U)
2239 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2240 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2241 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2242 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2243 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2244 #define CRS_CR_ERRIE_Pos          (2U)
2245 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2246 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2247 #define CRS_CR_ESYNCIE_Pos        (3U)
2248 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2249 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2250 #define CRS_CR_CEN_Pos            (5U)
2251 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2252 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2253 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2254 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2255 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2256 #define CRS_CR_SWSYNC_Pos         (7U)
2257 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2258 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2259 #define CRS_CR_TRIM_Pos           (8U)
2260 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2261 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2262 
2263 /*******************  Bit definition for CRS_CFGR register  *********************/
2264 #define CRS_CFGR_RELOAD_Pos       (0U)
2265 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2266 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2267 #define CRS_CFGR_FELIM_Pos        (16U)
2268 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2269 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2270 
2271 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2272 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2273 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2274 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2275 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2276 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2277 
2278 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2279 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2280 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2281 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2282 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2283 
2284 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2285 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2286 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2287 
2288 /*******************  Bit definition for CRS_ISR register  *********************/
2289 #define CRS_ISR_SYNCOKF_Pos       (0U)
2290 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2291 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2292 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2293 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2294 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2295 #define CRS_ISR_ERRF_Pos          (2U)
2296 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2297 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2298 #define CRS_ISR_ESYNCF_Pos        (3U)
2299 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2300 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2301 #define CRS_ISR_SYNCERR_Pos       (8U)
2302 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2303 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2304 #define CRS_ISR_SYNCMISS_Pos      (9U)
2305 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2306 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2307 #define CRS_ISR_TRIMOVF_Pos       (10U)
2308 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2309 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2310 #define CRS_ISR_FEDIR_Pos         (15U)
2311 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2312 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2313 #define CRS_ISR_FECAP_Pos         (16U)
2314 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2315 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2316 
2317 /*******************  Bit definition for CRS_ICR register  *********************/
2318 #define CRS_ICR_SYNCOKC_Pos       (0U)
2319 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2320 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2321 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2322 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2323 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2324 #define CRS_ICR_ERRC_Pos          (2U)
2325 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2326 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2327 #define CRS_ICR_ESYNCC_Pos        (3U)
2328 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2329 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2330 
2331 /******************************************************************************/
2332 /*                                                                            */
2333 /*                      Digital to Analog Converter                           */
2334 /*                                                                            */
2335 /******************************************************************************/
2336 /*
2337  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2338  */
2339 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
2340 
2341 /********************  Bit definition for DAC_CR register  ********************/
2342 #define DAC_CR_EN1_Pos              (0U)
2343 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2344 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2345 #define DAC_CR_TEN1_Pos             (1U)
2346 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2347 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2348 
2349 #define DAC_CR_TSEL1_Pos            (2U)
2350 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2351 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2352 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
2353 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
2354 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
2355 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
2356 
2357 #define DAC_CR_WAVE1_Pos            (6U)
2358 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2359 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2360 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
2361 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
2362 
2363 #define DAC_CR_MAMP1_Pos            (8U)
2364 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2365 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2366 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
2367 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
2368 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
2369 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
2370 
2371 #define DAC_CR_DMAEN1_Pos           (12U)
2372 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2373 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2374 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2375 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2376 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2377 #define DAC_CR_CEN1_Pos             (14U)
2378 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2379 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2380 
2381 #define DAC_CR_HFSEL_Pos            (15U)
2382 #define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
2383 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
2384 
2385 #define DAC_CR_EN2_Pos              (16U)
2386 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2387 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2388 #define DAC_CR_TEN2_Pos             (17U)
2389 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2390 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2391 
2392 #define DAC_CR_TSEL2_Pos            (18U)
2393 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2394 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2395 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
2396 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
2397 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
2398 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
2399 
2400 #define DAC_CR_WAVE2_Pos            (22U)
2401 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2402 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2403 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
2404 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
2405 
2406 #define DAC_CR_MAMP2_Pos            (24U)
2407 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2408 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2409 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
2410 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
2411 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
2412 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
2413 
2414 #define DAC_CR_DMAEN2_Pos           (28U)
2415 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2416 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2417 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2418 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2419 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2420 #define DAC_CR_CEN2_Pos             (30U)
2421 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2422 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2423 
2424 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2425 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2426 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2427 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2428 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2429 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2430 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2431 #define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
2432 #define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
2433 #define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
2434 #define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
2435 #define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
2436 #define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
2437 
2438 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2439 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2440 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2441 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2442 #define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
2443 #define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
2444 #define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
2445 
2446 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2447 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2448 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2449 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2450 #define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
2451 #define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
2452 #define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
2453 
2454 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2455 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2456 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2457 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2458 #define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
2459 #define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
2460 #define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
2461 
2462 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2463 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2464 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2465 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2466 #define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
2467 #define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
2468 #define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
2469 
2470 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2471 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2472 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2473 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2474 #define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
2475 #define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
2476 #define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
2477 
2478 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2479 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2480 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2481 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2482 #define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
2483 #define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
2484 #define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
2485 
2486 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2487 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2488 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2489 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2490 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2491 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2492 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2493 
2494 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2495 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2496 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2497 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2498 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2499 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2500 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2501 
2502 /******************  Bit definition for DAC_DHR8RD register  ******************/
2503 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2504 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2505 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2506 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2507 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2508 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2509 
2510 /*******************  Bit definition for DAC_DOR1 register  *******************/
2511 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2512 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2513 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2514 #define DAC_DOR1_DACC1DORB_Pos      (16U)
2515 #define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
2516 #define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
2517 
2518 /*******************  Bit definition for DAC_DOR2 register  *******************/
2519 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2520 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2521 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2522 #define DAC_DOR2_DACC2DORB_Pos      (16U)
2523 #define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
2524 #define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
2525 
2526 /********************  Bit definition for DAC_SR register  ********************/
2527 #define DAC_SR_DAC1RDY_Pos          (11U)
2528 #define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
2529 #define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
2530 #define DAC_SR_DORSTAT1_Pos         (12U)
2531 #define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
2532 #define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
2533 #define DAC_SR_DMAUDR1_Pos          (13U)
2534 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2535 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2536 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2537 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2538 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2539 #define DAC_SR_BWST1_Pos            (15U)
2540 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
2541 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2542 
2543 #define DAC_SR_DAC2RDY_Pos          (27U)
2544 #define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
2545 #define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
2546 #define DAC_SR_DORSTAT2_Pos         (28U)
2547 #define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
2548 #define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
2549 #define DAC_SR_DMAUDR2_Pos          (29U)
2550 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2551 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2552 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2553 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2554 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2555 #define DAC_SR_BWST2_Pos            (31U)
2556 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2557 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2558 
2559 /*******************  Bit definition for DAC_CCR register  ********************/
2560 #define DAC_CCR_OTRIM1_Pos          (0U)
2561 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2562 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2563 #define DAC_CCR_OTRIM2_Pos          (16U)
2564 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2565 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2566 
2567 /*******************  Bit definition for DAC_MCR register  *******************/
2568 #define DAC_MCR_MODE1_Pos           (0U)
2569 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2570 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2571 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
2572 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
2573 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
2574 
2575 #define DAC_MCR_DMADOUBLE1_Pos      (8U)
2576 #define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
2577 #define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
2578 
2579 #define DAC_MCR_SINFORMAT1_Pos      (9U)
2580 #define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
2581 #define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
2582 
2583 #define DAC_MCR_HFSEL_Pos           (14U)
2584 #define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
2585 #define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2586 #define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
2587 #define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
2588 
2589 #define DAC_MCR_MODE2_Pos           (16U)
2590 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
2591 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
2592 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
2593 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
2594 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
2595 
2596 #define DAC_MCR_DMADOUBLE2_Pos      (24U)
2597 #define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
2598 #define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
2599 
2600 #define DAC_MCR_SINFORMAT2_Pos      (25U)
2601 #define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
2602 #define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
2603 
2604 /******************  Bit definition for DAC_SHSR1 register  ******************/
2605 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
2606 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
2607 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
2608 
2609 /******************  Bit definition for DAC_SHSR2 register  ******************/
2610 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
2611 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
2612 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
2613 
2614 /******************  Bit definition for DAC_SHHR register  ******************/
2615 #define DAC_SHHR_THOLD1_Pos         (0U)
2616 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
2617 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
2618 #define DAC_SHHR_THOLD2_Pos         (16U)
2619 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
2620 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
2621 
2622 /******************  Bit definition for DAC_SHRR register  ******************/
2623 #define DAC_SHRR_TREFRESH1_Pos      (0U)
2624 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
2625 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
2626 #define DAC_SHRR_TREFRESH2_Pos      (16U)
2627 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
2628 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
2629 
2630 /******************  Bit definition for DAC_STR1 register  ******************/
2631 #define DAC_STR1_STRSTDATA1_Pos     (0U)
2632 #define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
2633 #define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
2634 #define DAC_STR1_STDIR1_Pos         (12U)
2635 #define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
2636 #define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
2637 
2638 #define DAC_STR1_STINCDATA1_Pos     (16U)
2639 #define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
2640 #define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
2641 
2642 /******************  Bit definition for DAC_STR2 register  ******************/
2643 #define DAC_STR2_STRSTDATA2_Pos     (0U)
2644 #define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
2645 #define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
2646 #define DAC_STR2_STDIR2_Pos         (12U)
2647 #define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
2648 #define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
2649 
2650 #define DAC_STR2_STINCDATA2_Pos     (16U)
2651 #define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
2652 #define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
2653 
2654 /******************  Bit definition for DAC_STMODR register  ****************/
2655 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
2656 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
2657 #define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2658 #define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
2659 #define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
2660 #define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
2661 #define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
2662 
2663 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
2664 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
2665 #define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2666 #define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
2667 #define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
2668 #define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
2669 #define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
2670 
2671 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
2672 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
2673 #define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2674 #define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
2675 #define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
2676 #define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
2677 #define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
2678 
2679 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
2680 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
2681 #define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2682 #define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
2683 #define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
2684 #define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
2685 #define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
2686 
2687 /******************************************************************************/
2688 /*                                                                            */
2689 /*                                 Debug MCU                                  */
2690 /*                                                                            */
2691 /******************************************************************************/
2692 /********************  Bit definition for DBGMCU_IDCODE register  *************/
2693 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
2694 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
2695 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
2696 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
2697 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
2698 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
2699 
2700 /********************  Bit definition for DBGMCU_CR register  *****************/
2701 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
2702 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
2703 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
2704 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
2705 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
2706 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
2707 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
2708 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
2709 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
2710 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
2711 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
2712 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
2713 
2714 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
2715 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
2716 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
2717 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
2718 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
2719 
2720 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
2721 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
2722 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
2723 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
2724 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
2725 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
2726 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
2727 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
2728 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
2729 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
2730 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
2731 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
2732 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
2733 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
2734 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
2735 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
2736 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
2737 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
2738 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
2739 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
2740 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
2741 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
2742 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
2743 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
2744 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
2745 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
2746 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
2747 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
2748 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
2749 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
2750 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
2751 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
2752 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
2753 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
2754 
2755 
2756 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
2757 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
2758 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
2759 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
2760 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
2761 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
2762 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
2763 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
2764 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
2765 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
2766 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
2767 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
2768 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
2769 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
2770 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
2771 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
2772 
2773 /******************************************************************************/
2774 /*                                                                            */
2775 /*                           DMA Controller (DMA)                             */
2776 /*                                                                            */
2777 /******************************************************************************/
2778 
2779 /*******************  Bit definition for DMA_ISR register  ********************/
2780 #define DMA_ISR_GIF1_Pos       (0U)
2781 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
2782 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
2783 #define DMA_ISR_TCIF1_Pos      (1U)
2784 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
2785 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
2786 #define DMA_ISR_HTIF1_Pos      (2U)
2787 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
2788 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
2789 #define DMA_ISR_TEIF1_Pos      (3U)
2790 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
2791 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
2792 #define DMA_ISR_GIF2_Pos       (4U)
2793 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
2794 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
2795 #define DMA_ISR_TCIF2_Pos      (5U)
2796 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
2797 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
2798 #define DMA_ISR_HTIF2_Pos      (6U)
2799 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
2800 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
2801 #define DMA_ISR_TEIF2_Pos      (7U)
2802 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
2803 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
2804 #define DMA_ISR_GIF3_Pos       (8U)
2805 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
2806 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
2807 #define DMA_ISR_TCIF3_Pos      (9U)
2808 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
2809 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
2810 #define DMA_ISR_HTIF3_Pos      (10U)
2811 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
2812 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
2813 #define DMA_ISR_TEIF3_Pos      (11U)
2814 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
2815 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
2816 #define DMA_ISR_GIF4_Pos       (12U)
2817 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
2818 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
2819 #define DMA_ISR_TCIF4_Pos      (13U)
2820 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
2821 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
2822 #define DMA_ISR_HTIF4_Pos      (14U)
2823 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
2824 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
2825 #define DMA_ISR_TEIF4_Pos      (15U)
2826 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
2827 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
2828 #define DMA_ISR_GIF5_Pos       (16U)
2829 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
2830 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
2831 #define DMA_ISR_TCIF5_Pos      (17U)
2832 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
2833 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
2834 #define DMA_ISR_HTIF5_Pos      (18U)
2835 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
2836 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
2837 #define DMA_ISR_TEIF5_Pos      (19U)
2838 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
2839 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
2840 #define DMA_ISR_GIF6_Pos       (20U)
2841 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
2842 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
2843 #define DMA_ISR_TCIF6_Pos      (21U)
2844 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
2845 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
2846 #define DMA_ISR_HTIF6_Pos      (22U)
2847 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
2848 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
2849 #define DMA_ISR_TEIF6_Pos      (23U)
2850 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
2851 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
2852 
2853 /*******************  Bit definition for DMA_IFCR register  *******************/
2854 #define DMA_IFCR_CGIF1_Pos     (0U)
2855 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
2856 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
2857 #define DMA_IFCR_CTCIF1_Pos    (1U)
2858 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
2859 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
2860 #define DMA_IFCR_CHTIF1_Pos    (2U)
2861 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
2862 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
2863 #define DMA_IFCR_CTEIF1_Pos    (3U)
2864 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
2865 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
2866 #define DMA_IFCR_CGIF2_Pos     (4U)
2867 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
2868 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
2869 #define DMA_IFCR_CTCIF2_Pos    (5U)
2870 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
2871 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
2872 #define DMA_IFCR_CHTIF2_Pos    (6U)
2873 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
2874 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
2875 #define DMA_IFCR_CTEIF2_Pos    (7U)
2876 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
2877 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
2878 #define DMA_IFCR_CGIF3_Pos     (8U)
2879 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
2880 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
2881 #define DMA_IFCR_CTCIF3_Pos    (9U)
2882 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
2883 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
2884 #define DMA_IFCR_CHTIF3_Pos    (10U)
2885 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
2886 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
2887 #define DMA_IFCR_CTEIF3_Pos    (11U)
2888 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
2889 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
2890 #define DMA_IFCR_CGIF4_Pos     (12U)
2891 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
2892 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
2893 #define DMA_IFCR_CTCIF4_Pos    (13U)
2894 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
2895 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
2896 #define DMA_IFCR_CHTIF4_Pos    (14U)
2897 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
2898 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
2899 #define DMA_IFCR_CTEIF4_Pos    (15U)
2900 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
2901 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
2902 #define DMA_IFCR_CGIF5_Pos     (16U)
2903 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
2904 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
2905 #define DMA_IFCR_CTCIF5_Pos    (17U)
2906 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2907 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2908 #define DMA_IFCR_CHTIF5_Pos    (18U)
2909 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2910 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2911 #define DMA_IFCR_CTEIF5_Pos    (19U)
2912 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2913 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2914 #define DMA_IFCR_CGIF6_Pos     (20U)
2915 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2916 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2917 #define DMA_IFCR_CTCIF6_Pos    (21U)
2918 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2919 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2920 #define DMA_IFCR_CHTIF6_Pos    (22U)
2921 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2922 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2923 #define DMA_IFCR_CTEIF6_Pos    (23U)
2924 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2925 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2926 
2927 /*******************  Bit definition for DMA_CCR register  ********************/
2928 #define DMA_CCR_EN_Pos         (0U)
2929 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2930 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2931 #define DMA_CCR_TCIE_Pos       (1U)
2932 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2933 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2934 #define DMA_CCR_HTIE_Pos       (2U)
2935 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2936 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2937 #define DMA_CCR_TEIE_Pos       (3U)
2938 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2939 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2940 #define DMA_CCR_DIR_Pos        (4U)
2941 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2942 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2943 #define DMA_CCR_CIRC_Pos       (5U)
2944 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2945 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2946 #define DMA_CCR_PINC_Pos       (6U)
2947 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2948 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2949 #define DMA_CCR_MINC_Pos       (7U)
2950 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2951 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2952 
2953 #define DMA_CCR_PSIZE_Pos      (8U)
2954 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2955 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2956 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2957 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2958 
2959 #define DMA_CCR_MSIZE_Pos      (10U)
2960 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2961 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2962 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2963 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2964 
2965 #define DMA_CCR_PL_Pos         (12U)
2966 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2967 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2968 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2969 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
2970 
2971 #define DMA_CCR_MEM2MEM_Pos    (14U)
2972 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2973 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2974 
2975 /******************  Bit definition for DMA_CNDTR register  *******************/
2976 #define DMA_CNDTR_NDT_Pos      (0U)
2977 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2978 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2979 
2980 /******************  Bit definition for DMA_CPAR register  ********************/
2981 #define DMA_CPAR_PA_Pos        (0U)
2982 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2983 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2984 
2985 /******************  Bit definition for DMA_CMAR register  ********************/
2986 #define DMA_CMAR_MA_Pos        (0U)
2987 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2988 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2989 
2990 /******************************************************************************/
2991 /*                                                                            */
2992 /*                             DMAMUX Controller                              */
2993 /*                                                                            */
2994 /******************************************************************************/
2995 
2996 /********************  Bits definition for DMAMUX_CxCR register  **************/
2997 #define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
2998 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
2999 #define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
3000 #define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3001 #define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3002 #define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3003 #define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3004 #define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3005 #define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3006 #define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3007 #define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3008 
3009 #define DMAMUX_CxCR_SOIE_Pos                         (8U)
3010 #define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3011 #define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
3012 
3013 #define DMAMUX_CxCR_EGE_Pos                          (9U)
3014 #define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3015 #define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
3016 
3017 #define DMAMUX_CxCR_SE_Pos                           (16U)
3018 #define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3019 #define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
3020 
3021 #define DMAMUX_CxCR_SPOL_Pos                         (17U)
3022 #define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3023 #define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
3024 #define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3025 #define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3026 
3027 #define DMAMUX_CxCR_NBREQ_Pos                        (19U)
3028 #define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3029 #define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
3030 #define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3031 #define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3032 #define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3033 #define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3034 #define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3035 
3036 #define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
3037 #define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3038 #define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
3039 #define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3040 #define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3041 #define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3042 #define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3043 #define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3044 
3045 /********************  Bits definition for DMAMUX_CSR register  ****************/
3046 #define DMAMUX_CSR_SOF0_Pos                          (0U)
3047 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3048 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
3049 #define DMAMUX_CSR_SOF1_Pos                          (1U)
3050 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3051 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
3052 #define DMAMUX_CSR_SOF2_Pos                          (2U)
3053 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3054 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
3055 #define DMAMUX_CSR_SOF3_Pos                          (3U)
3056 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3057 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
3058 #define DMAMUX_CSR_SOF4_Pos                          (4U)
3059 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3060 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
3061 #define DMAMUX_CSR_SOF5_Pos                          (5U)
3062 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3063 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
3064 #define DMAMUX_CSR_SOF6_Pos                          (6U)
3065 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3066 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
3067 #define DMAMUX_CSR_SOF7_Pos                          (7U)
3068 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3069 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
3070 #define DMAMUX_CSR_SOF8_Pos                          (8U)
3071 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3072 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
3073 #define DMAMUX_CSR_SOF9_Pos                          (9U)
3074 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3075 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
3076 #define DMAMUX_CSR_SOF10_Pos                         (10U)
3077 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3078 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
3079 #define DMAMUX_CSR_SOF11_Pos                         (11U)
3080 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3081 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
3082 
3083 /********************  Bits definition for DMAMUX_CFR register  ****************/
3084 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
3085 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3086 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
3087 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
3088 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3089 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
3090 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
3091 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3092 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
3093 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
3094 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3095 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
3096 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
3097 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3098 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
3099 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
3100 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3101 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
3102 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
3103 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3104 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
3105 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
3106 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3107 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
3108 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
3109 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3110 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
3111 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
3112 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3113 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
3114 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
3115 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3116 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
3117 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
3118 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3119 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
3120 
3121 /********************  Bits definition for DMAMUX_RGxCR register  ************/
3122 #define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
3123 #define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3124 #define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
3125 #define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3126 #define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3127 #define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3128 #define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3129 #define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3130 
3131 #define DMAMUX_RGxCR_OIE_Pos                         (8U)
3132 #define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3133 #define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
3134 
3135 #define DMAMUX_RGxCR_GE_Pos                          (16U)
3136 #define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3137 #define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
3138 
3139 #define DMAMUX_RGxCR_GPOL_Pos                        (17U)
3140 #define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3141 #define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
3142 #define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3143 #define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3144 
3145 #define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
3146 #define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3147 #define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
3148 #define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3149 #define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3150 #define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3151 #define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3152 #define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3153 
3154 /********************  Bits definition for DMAMUX_RGSR register  **************/
3155 #define DMAMUX_RGSR_OF0_Pos                          (0U)
3156 #define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3157 #define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
3158 #define DMAMUX_RGSR_OF1_Pos                          (1U)
3159 #define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3160 #define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
3161 #define DMAMUX_RGSR_OF2_Pos                          (2U)
3162 #define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3163 #define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
3164 #define DMAMUX_RGSR_OF3_Pos                          (3U)
3165 #define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3166 #define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
3167 
3168 /********************  Bits definition for DMAMUX_RGCFR register  ************/
3169 #define DMAMUX_RGCFR_COF0_Pos                        (0U)
3170 #define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3171 #define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
3172 #define DMAMUX_RGCFR_COF1_Pos                        (1U)
3173 #define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3174 #define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
3175 #define DMAMUX_RGCFR_COF2_Pos                        (2U)
3176 #define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3177 #define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
3178 #define DMAMUX_RGCFR_COF3_Pos                        (3U)
3179 #define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3180 #define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
3181 
3182 /******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
3183 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
3184 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3185 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3186 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
3187 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3188 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3189 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
3190 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3191 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3192 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
3193 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3194 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3195 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
3196 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3197 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3198 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
3199 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3200 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3201 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
3202 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3203 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3204 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
3205 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3206 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3207 
3208 /******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
3209 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
3210 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3211 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3212 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
3213 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3214 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3215 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
3216 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3217 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3218 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
3219 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3220 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3221 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
3222 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3223 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3224 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
3225 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3226 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3227 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
3228 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3229 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3230 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
3231 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3232 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3233 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
3234 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3235 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3236 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
3237 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3238 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3239 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
3240 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3241 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3242 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
3243 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3244 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3245 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
3246 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3247 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3248 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
3249 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3250 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3251 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
3252 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3253 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3254 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
3255 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3256 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3257 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
3258 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3259 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3260 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
3261 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3262 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3263 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
3264 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3265 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3266 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
3267 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3268 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3269 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
3270 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3271 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3272 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
3273 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3274 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3275 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
3276 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3277 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3278 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
3279 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3280 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3281 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
3282 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3283 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3284 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
3285 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3286 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3287 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
3288 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3289 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3290 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
3291 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3292 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3293 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
3294 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3295 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3296 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
3297 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3298 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3299 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
3300 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3301 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3302 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
3303 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3304 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3305 
3306 
3307 /******************************************************************************/
3308 /*                                                                            */
3309 /*                    External Interrupt/Event Controller                     */
3310 /*                                                                            */
3311 /******************************************************************************/
3312 /*******************  Bit definition for EXTI_IMR1 register  ******************/
3313 #define EXTI_IMR1_IM0_Pos        (0U)
3314 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
3315 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
3316 #define EXTI_IMR1_IM1_Pos        (1U)
3317 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
3318 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
3319 #define EXTI_IMR1_IM2_Pos        (2U)
3320 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
3321 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
3322 #define EXTI_IMR1_IM3_Pos        (3U)
3323 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
3324 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
3325 #define EXTI_IMR1_IM4_Pos        (4U)
3326 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
3327 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
3328 #define EXTI_IMR1_IM5_Pos        (5U)
3329 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
3330 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
3331 #define EXTI_IMR1_IM6_Pos        (6U)
3332 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
3333 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
3334 #define EXTI_IMR1_IM7_Pos        (7U)
3335 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
3336 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
3337 #define EXTI_IMR1_IM8_Pos        (8U)
3338 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
3339 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
3340 #define EXTI_IMR1_IM9_Pos        (9U)
3341 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
3342 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
3343 #define EXTI_IMR1_IM10_Pos       (10U)
3344 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
3345 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
3346 #define EXTI_IMR1_IM11_Pos       (11U)
3347 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
3348 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
3349 #define EXTI_IMR1_IM12_Pos       (12U)
3350 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
3351 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
3352 #define EXTI_IMR1_IM13_Pos       (13U)
3353 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
3354 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
3355 #define EXTI_IMR1_IM14_Pos       (14U)
3356 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
3357 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
3358 #define EXTI_IMR1_IM15_Pos       (15U)
3359 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
3360 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
3361 #define EXTI_IMR1_IM16_Pos       (16U)
3362 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
3363 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
3364 #define EXTI_IMR1_IM17_Pos       (17U)
3365 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
3366 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
3367 #define EXTI_IMR1_IM18_Pos       (18U)
3368 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
3369 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
3370 #define EXTI_IMR1_IM19_Pos       (19U)
3371 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
3372 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
3373 #define EXTI_IMR1_IM20_Pos       (20U)
3374 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
3375 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
3376 #define EXTI_IMR1_IM21_Pos       (21U)
3377 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
3378 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
3379 #define EXTI_IMR1_IM22_Pos       (22U)
3380 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
3381 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
3382 #define EXTI_IMR1_IM23_Pos       (23U)
3383 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
3384 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
3385 #define EXTI_IMR1_IM24_Pos       (24U)
3386 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
3387 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
3388 #define EXTI_IMR1_IM25_Pos       (25U)
3389 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
3390 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
3391 #define EXTI_IMR1_IM26_Pos       (26U)
3392 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
3393 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
3394 #define EXTI_IMR1_IM27_Pos       (27U)
3395 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
3396 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
3397 #define EXTI_IMR1_IM28_Pos       (28U)
3398 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
3399 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
3400 #define EXTI_IMR1_IM29_Pos       (29U)
3401 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
3402 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
3403 #define EXTI_IMR1_IM30_Pos       (30U)
3404 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
3405 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
3406 #define EXTI_IMR1_IM_Pos         (0U)
3407 #define EXTI_IMR1_IM_Msk         (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0x7FFFFFFF */
3408 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
3409 
3410 /*******************  Bit definition for EXTI_EMR1 register  ******************/
3411 #define EXTI_EMR1_EM0_Pos        (0U)
3412 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
3413 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
3414 #define EXTI_EMR1_EM1_Pos        (1U)
3415 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
3416 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
3417 #define EXTI_EMR1_EM2_Pos        (2U)
3418 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
3419 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
3420 #define EXTI_EMR1_EM3_Pos        (3U)
3421 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
3422 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
3423 #define EXTI_EMR1_EM4_Pos        (4U)
3424 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
3425 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
3426 #define EXTI_EMR1_EM5_Pos        (5U)
3427 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
3428 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
3429 #define EXTI_EMR1_EM6_Pos        (6U)
3430 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
3431 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
3432 #define EXTI_EMR1_EM7_Pos        (7U)
3433 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
3434 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
3435 #define EXTI_EMR1_EM8_Pos        (8U)
3436 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
3437 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
3438 #define EXTI_EMR1_EM9_Pos        (9U)
3439 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
3440 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
3441 #define EXTI_EMR1_EM10_Pos       (10U)
3442 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
3443 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
3444 #define EXTI_EMR1_EM11_Pos       (11U)
3445 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
3446 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
3447 #define EXTI_EMR1_EM12_Pos       (12U)
3448 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
3449 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
3450 #define EXTI_EMR1_EM13_Pos       (13U)
3451 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
3452 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
3453 #define EXTI_EMR1_EM14_Pos       (14U)
3454 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
3455 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
3456 #define EXTI_EMR1_EM15_Pos       (15U)
3457 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
3458 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
3459 #define EXTI_EMR1_EM16_Pos       (16U)
3460 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
3461 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
3462 #define EXTI_EMR1_EM17_Pos       (17U)
3463 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
3464 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
3465 #define EXTI_EMR1_EM18_Pos       (18U)
3466 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
3467 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
3468 #define EXTI_EMR1_EM19_Pos       (19U)
3469 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
3470 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
3471 #define EXTI_EMR1_EM20_Pos       (20U)
3472 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
3473 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
3474 #define EXTI_EMR1_EM21_Pos       (21U)
3475 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
3476 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
3477 #define EXTI_EMR1_EM22_Pos       (22U)
3478 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
3479 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
3480 #define EXTI_EMR1_EM23_Pos       (23U)
3481 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
3482 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
3483 #define EXTI_EMR1_EM24_Pos       (24U)
3484 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
3485 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
3486 #define EXTI_EMR1_EM25_Pos       (25U)
3487 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
3488 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
3489 #define EXTI_EMR1_EM26_Pos       (26U)
3490 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
3491 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
3492 #define EXTI_EMR1_EM27_Pos       (27U)
3493 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
3494 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
3495 #define EXTI_EMR1_EM28_Pos       (28U)
3496 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
3497 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
3498 #define EXTI_EMR1_EM29_Pos       (29U)
3499 #define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
3500 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
3501 #define EXTI_EMR1_EM30_Pos       (30U)
3502 #define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
3503 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
3504 
3505 /******************  Bit definition for EXTI_RTSR1 register  ******************/
3506 #define EXTI_RTSR1_RT0_Pos       (0U)
3507 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
3508 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
3509 #define EXTI_RTSR1_RT1_Pos       (1U)
3510 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
3511 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
3512 #define EXTI_RTSR1_RT2_Pos       (2U)
3513 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
3514 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
3515 #define EXTI_RTSR1_RT3_Pos       (3U)
3516 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
3517 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
3518 #define EXTI_RTSR1_RT4_Pos       (4U)
3519 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
3520 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
3521 #define EXTI_RTSR1_RT5_Pos       (5U)
3522 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
3523 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
3524 #define EXTI_RTSR1_RT6_Pos       (6U)
3525 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
3526 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
3527 #define EXTI_RTSR1_RT7_Pos       (7U)
3528 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
3529 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
3530 #define EXTI_RTSR1_RT8_Pos       (8U)
3531 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
3532 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
3533 #define EXTI_RTSR1_RT9_Pos       (9U)
3534 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
3535 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
3536 #define EXTI_RTSR1_RT10_Pos      (10U)
3537 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
3538 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
3539 #define EXTI_RTSR1_RT11_Pos      (11U)
3540 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
3541 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
3542 #define EXTI_RTSR1_RT12_Pos      (12U)
3543 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
3544 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
3545 #define EXTI_RTSR1_RT13_Pos      (13U)
3546 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
3547 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
3548 #define EXTI_RTSR1_RT14_Pos      (14U)
3549 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
3550 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
3551 #define EXTI_RTSR1_RT15_Pos      (15U)
3552 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
3553 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
3554 #define EXTI_RTSR1_RT16_Pos      (16U)
3555 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
3556 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
3557 #define EXTI_RTSR1_RT17_Pos      (17U)
3558 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
3559 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
3560 #define EXTI_RTSR1_RT19_Pos      (19U)
3561 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
3562 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
3563 #define EXTI_RTSR1_RT20_Pos      (20U)
3564 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
3565 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
3566 #define EXTI_RTSR1_RT21_Pos      (21U)
3567 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
3568 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
3569 #define EXTI_RTSR1_RT22_Pos      (22U)
3570 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
3571 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
3572 #define EXTI_RTSR1_RT29_Pos      (29U)
3573 #define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
3574 #define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
3575 #define EXTI_RTSR1_RT30_Pos      (30U)
3576 #define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
3577 #define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
3578 
3579 /******************  Bit definition for EXTI_FTSR1 register  ******************/
3580 #define EXTI_FTSR1_FT0_Pos       (0U)
3581 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
3582 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
3583 #define EXTI_FTSR1_FT1_Pos       (1U)
3584 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
3585 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
3586 #define EXTI_FTSR1_FT2_Pos       (2U)
3587 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
3588 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
3589 #define EXTI_FTSR1_FT3_Pos       (3U)
3590 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
3591 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
3592 #define EXTI_FTSR1_FT4_Pos       (4U)
3593 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
3594 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
3595 #define EXTI_FTSR1_FT5_Pos       (5U)
3596 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
3597 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
3598 #define EXTI_FTSR1_FT6_Pos       (6U)
3599 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
3600 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
3601 #define EXTI_FTSR1_FT7_Pos       (7U)
3602 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
3603 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
3604 #define EXTI_FTSR1_FT8_Pos       (8U)
3605 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
3606 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
3607 #define EXTI_FTSR1_FT9_Pos       (9U)
3608 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
3609 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
3610 #define EXTI_FTSR1_FT10_Pos      (10U)
3611 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
3612 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
3613 #define EXTI_FTSR1_FT11_Pos      (11U)
3614 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
3615 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
3616 #define EXTI_FTSR1_FT12_Pos      (12U)
3617 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
3618 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
3619 #define EXTI_FTSR1_FT13_Pos      (13U)
3620 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
3621 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
3622 #define EXTI_FTSR1_FT14_Pos      (14U)
3623 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
3624 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
3625 #define EXTI_FTSR1_FT15_Pos      (15U)
3626 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
3627 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
3628 #define EXTI_FTSR1_FT16_Pos      (16U)
3629 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
3630 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
3631 #define EXTI_FTSR1_FT17_Pos      (17U)
3632 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
3633 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
3634 #define EXTI_FTSR1_FT19_Pos      (19U)
3635 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
3636 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
3637 #define EXTI_FTSR1_FT20_Pos      (20U)
3638 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
3639 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
3640 #define EXTI_FTSR1_FT21_Pos      (21U)
3641 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
3642 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
3643 #define EXTI_FTSR1_FT22_Pos      (22U)
3644 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
3645 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
3646 #define EXTI_FTSR1_FT29_Pos      (29U)
3647 #define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
3648 #define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
3649 #define EXTI_FTSR1_FT30_Pos      (30U)
3650 #define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
3651 #define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
3652 
3653 /******************  Bit definition for EXTI_SWIER1 register  *****************/
3654 #define EXTI_SWIER1_SWI0_Pos     (0U)
3655 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
3656 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
3657 #define EXTI_SWIER1_SWI1_Pos     (1U)
3658 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
3659 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
3660 #define EXTI_SWIER1_SWI2_Pos     (2U)
3661 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
3662 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
3663 #define EXTI_SWIER1_SWI3_Pos     (3U)
3664 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
3665 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
3666 #define EXTI_SWIER1_SWI4_Pos     (4U)
3667 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
3668 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
3669 #define EXTI_SWIER1_SWI5_Pos     (5U)
3670 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
3671 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
3672 #define EXTI_SWIER1_SWI6_Pos     (6U)
3673 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
3674 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
3675 #define EXTI_SWIER1_SWI7_Pos     (7U)
3676 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
3677 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
3678 #define EXTI_SWIER1_SWI8_Pos     (8U)
3679 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
3680 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
3681 #define EXTI_SWIER1_SWI9_Pos     (9U)
3682 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
3683 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
3684 #define EXTI_SWIER1_SWI10_Pos    (10U)
3685 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
3686 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
3687 #define EXTI_SWIER1_SWI11_Pos    (11U)
3688 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
3689 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
3690 #define EXTI_SWIER1_SWI12_Pos    (12U)
3691 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
3692 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
3693 #define EXTI_SWIER1_SWI13_Pos    (13U)
3694 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
3695 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
3696 #define EXTI_SWIER1_SWI14_Pos    (14U)
3697 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
3698 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
3699 #define EXTI_SWIER1_SWI15_Pos    (15U)
3700 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
3701 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
3702 #define EXTI_SWIER1_SWI16_Pos    (16U)
3703 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
3704 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
3705 #define EXTI_SWIER1_SWI17_Pos    (17U)
3706 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
3707 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
3708 #define EXTI_SWIER1_SWI19_Pos    (19U)
3709 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
3710 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
3711 #define EXTI_SWIER1_SWI20_Pos    (20U)
3712 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
3713 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
3714 #define EXTI_SWIER1_SWI21_Pos    (21U)
3715 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
3716 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
3717 #define EXTI_SWIER1_SWI22_Pos    (22U)
3718 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
3719 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
3720 #define EXTI_SWIER1_SWI29_Pos    (29U)
3721 #define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
3722 #define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
3723 #define EXTI_SWIER1_SWI30_Pos    (30U)
3724 #define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
3725 #define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
3726 
3727 /*******************  Bit definition for EXTI_PR1 register  *******************/
3728 #define EXTI_PR1_PIF0_Pos        (0U)
3729 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
3730 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
3731 #define EXTI_PR1_PIF1_Pos        (1U)
3732 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
3733 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
3734 #define EXTI_PR1_PIF2_Pos        (2U)
3735 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
3736 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
3737 #define EXTI_PR1_PIF3_Pos        (3U)
3738 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
3739 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
3740 #define EXTI_PR1_PIF4_Pos        (4U)
3741 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
3742 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
3743 #define EXTI_PR1_PIF5_Pos        (5U)
3744 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
3745 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
3746 #define EXTI_PR1_PIF6_Pos        (6U)
3747 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
3748 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
3749 #define EXTI_PR1_PIF7_Pos        (7U)
3750 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
3751 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
3752 #define EXTI_PR1_PIF8_Pos        (8U)
3753 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
3754 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
3755 #define EXTI_PR1_PIF9_Pos        (9U)
3756 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
3757 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
3758 #define EXTI_PR1_PIF10_Pos       (10U)
3759 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
3760 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
3761 #define EXTI_PR1_PIF11_Pos       (11U)
3762 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
3763 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
3764 #define EXTI_PR1_PIF12_Pos       (12U)
3765 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
3766 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
3767 #define EXTI_PR1_PIF13_Pos       (13U)
3768 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
3769 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
3770 #define EXTI_PR1_PIF14_Pos       (14U)
3771 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
3772 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
3773 #define EXTI_PR1_PIF15_Pos       (15U)
3774 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
3775 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
3776 #define EXTI_PR1_PIF16_Pos       (16U)
3777 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
3778 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
3779 #define EXTI_PR1_PIF17_Pos       (17U)
3780 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
3781 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
3782 #define EXTI_PR1_PIF19_Pos       (19U)
3783 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
3784 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
3785 #define EXTI_PR1_PIF20_Pos       (20U)
3786 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
3787 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
3788 #define EXTI_PR1_PIF21_Pos       (21U)
3789 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
3790 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
3791 #define EXTI_PR1_PIF22_Pos       (22U)
3792 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
3793 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
3794 #define EXTI_PR1_PIF29_Pos       (29U)
3795 #define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
3796 #define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
3797 #define EXTI_PR1_PIF30_Pos       (30U)
3798 #define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
3799 #define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
3800 
3801 /*******************  Bit definition for EXTI_IMR2 register  ******************/
3802 #define EXTI_IMR2_IM34_Pos       (2U)
3803 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
3804 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
3805 #define EXTI_IMR2_IM36_Pos       (4U)
3806 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
3807 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
3808 #define EXTI_IMR2_IM37_Pos       (5U)
3809 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
3810 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
3811 #define EXTI_IMR2_IM38_Pos       (6U)
3812 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
3813 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
3814 #define EXTI_IMR2_IM39_Pos       (7U)
3815 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
3816 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
3817 #define EXTI_IMR2_IM40_Pos       (8U)
3818 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
3819 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
3820 #define EXTI_IMR2_IM41_Pos       (9U)
3821 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
3822 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
3823 #define EXTI_IMR2_IM_Pos         (0U)
3824 #define EXTI_IMR2_IM_Msk         (0x3F4UL << EXTI_IMR2_IM_Pos)                 /*!< 0x000003F4 */
3825 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
3826 
3827 /*******************  Bit definition for EXTI_EMR2 register  ******************/
3828 #define EXTI_EMR2_EM34_Pos       (2U)
3829 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
3830 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
3831 #define EXTI_EMR2_EM36_Pos       (4U)
3832 #define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
3833 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
3834 #define EXTI_EMR2_EM37_Pos       (5U)
3835 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
3836 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
3837 #define EXTI_EMR2_EM38_Pos       (6U)
3838 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
3839 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
3840 #define EXTI_EMR2_EM39_Pos       (7U)
3841 #define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
3842 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
3843 #define EXTI_EMR2_EM40_Pos       (8U)
3844 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
3845 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
3846 #define EXTI_EMR2_EM41_Pos       (9U)
3847 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
3848 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
3849 #define EXTI_EMR2_EM_Pos         (0U)
3850 #define EXTI_EMR2_EM_Msk         (0x3F4UL << EXTI_EMR2_EM_Pos)                 /*!< 0x000003F4 */
3851 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
3852 
3853 /******************  Bit definition for EXTI_RTSR2 register  ******************/
3854 #define EXTI_RTSR2_RT38_Pos      (6U)
3855 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
3856 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
3857 #define EXTI_RTSR2_RT39_Pos      (7U)
3858 #define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
3859 #define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
3860 #define EXTI_RTSR2_RT40_Pos      (8U)
3861 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
3862 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
3863 #define EXTI_RTSR2_RT41_Pos      (9U)
3864 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
3865 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
3866 
3867 /******************  Bit definition for EXTI_FTSR2 register  ******************/
3868 #define EXTI_FTSR2_FT38_Pos      (6U)
3869 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
3870 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
3871 #define EXTI_FTSR2_FT39_Pos      (7U)
3872 #define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
3873 #define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
3874 #define EXTI_FTSR2_FT40_Pos      (8U)
3875 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
3876 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
3877 #define EXTI_FTSR2_FT41_Pos      (9U)
3878 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
3879 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
3880 
3881 /******************  Bit definition for EXTI_SWIER2 register  *****************/
3882 #define EXTI_SWIER2_SWI38_Pos    (6U)
3883 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
3884 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
3885 #define EXTI_SWIER2_SWI39_Pos    (7U)
3886 #define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
3887 #define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
3888 #define EXTI_SWIER2_SWI40_Pos    (8U)
3889 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
3890 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
3891 #define EXTI_SWIER2_SWI41_Pos    (9U)
3892 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
3893 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
3894 
3895 /*******************  Bit definition for EXTI_PR2 register  *******************/
3896 #define EXTI_PR2_PIF38_Pos       (6U)
3897 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
3898 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
3899 #define EXTI_PR2_PIF39_Pos       (7U)
3900 #define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
3901 #define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
3902 #define EXTI_PR2_PIF40_Pos       (8U)
3903 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
3904 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
3905 #define EXTI_PR2_PIF41_Pos       (9U)
3906 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
3907 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
3908 
3909 /******************************************************************************/
3910 /*                                                                            */
3911 /*                 Flexible Datarate Controller Area Network                  */
3912 /*                                                                            */
3913 /******************************************************************************/
3914 /*!<FDCAN control and status registers */
3915 /*****************  Bit definition for FDCAN_CREL register  *******************/
3916 #define FDCAN_CREL_DAY_Pos        (0U)
3917 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
3918 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
3919 #define FDCAN_CREL_MON_Pos        (8U)
3920 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
3921 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
3922 #define FDCAN_CREL_YEAR_Pos       (16U)
3923 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
3924 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
3925 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
3926 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
3927 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
3928 #define FDCAN_CREL_STEP_Pos       (24U)
3929 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
3930 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
3931 #define FDCAN_CREL_REL_Pos        (28U)
3932 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
3933 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
3934 
3935 /*****************  Bit definition for FDCAN_ENDN register  *******************/
3936 #define FDCAN_ENDN_ETV_Pos        (0U)
3937 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
3938 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                    */
3939 
3940 /*****************  Bit definition for FDCAN_DBTP register  *******************/
3941 #define FDCAN_DBTP_DSJW_Pos       (0U)
3942 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
3943 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
3944 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
3945 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
3946 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
3947 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
3948 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
3949 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
3950 #define FDCAN_DBTP_DBRP_Pos       (16U)
3951 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
3952 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
3953 #define FDCAN_DBTP_TDC_Pos        (23U)
3954 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
3955 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
3956 
3957 /*****************  Bit definition for FDCAN_TEST register  *******************/
3958 #define FDCAN_TEST_LBCK_Pos       (4U)
3959 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
3960 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
3961 #define FDCAN_TEST_TX_Pos         (5U)
3962 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
3963 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
3964 #define FDCAN_TEST_RX_Pos         (7U)
3965 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
3966 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
3967 
3968 /*****************  Bit definition for FDCAN_RWD register  ********************/
3969 #define FDCAN_RWD_WDC_Pos         (0U)
3970 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
3971 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
3972 #define FDCAN_RWD_WDV_Pos         (8U)
3973 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
3974 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
3975 
3976 /*****************  Bit definition for FDCAN_CCCR register  ********************/
3977 #define FDCAN_CCCR_INIT_Pos       (0U)
3978 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
3979 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
3980 #define FDCAN_CCCR_CCE_Pos        (1U)
3981 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
3982 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
3983 #define FDCAN_CCCR_ASM_Pos        (2U)
3984 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
3985 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
3986 #define FDCAN_CCCR_CSA_Pos        (3U)
3987 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
3988 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
3989 #define FDCAN_CCCR_CSR_Pos        (4U)
3990 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
3991 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
3992 #define FDCAN_CCCR_MON_Pos        (5U)
3993 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
3994 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
3995 #define FDCAN_CCCR_DAR_Pos        (6U)
3996 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
3997 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
3998 #define FDCAN_CCCR_TEST_Pos       (7U)
3999 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4000 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4001 #define FDCAN_CCCR_FDOE_Pos       (8U)
4002 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4003 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4004 #define FDCAN_CCCR_BRSE_Pos       (9U)
4005 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4006 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4007 #define FDCAN_CCCR_PXHD_Pos       (12U)
4008 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4009 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4010 #define FDCAN_CCCR_EFBI_Pos       (13U)
4011 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4012 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4013 #define FDCAN_CCCR_TXP_Pos        (14U)
4014 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4015 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4016 #define FDCAN_CCCR_NISO_Pos       (15U)
4017 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4018 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4019 
4020 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4021 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4022 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4023 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4024 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4025 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4026 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4027 #define FDCAN_NBTP_NBRP_Pos       (16U)
4028 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4029 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4030 #define FDCAN_NBTP_NSJW_Pos       (25U)
4031 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4032 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4033 
4034 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4035 #define FDCAN_TSCC_TSS_Pos        (0U)
4036 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4037 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4038 #define FDCAN_TSCC_TCP_Pos        (16U)
4039 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4040 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4041 
4042 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4043 #define FDCAN_TSCV_TSC_Pos        (0U)
4044 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4045 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4046 
4047 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4048 #define FDCAN_TOCC_ETOC_Pos       (0U)
4049 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4050 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4051 #define FDCAN_TOCC_TOS_Pos        (1U)
4052 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4053 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4054 #define FDCAN_TOCC_TOP_Pos        (16U)
4055 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4056 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4057 
4058 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4059 #define FDCAN_TOCV_TOC_Pos        (0U)
4060 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4061 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4062 
4063 /*****************  Bit definition for FDCAN_ECR register  *********************/
4064 #define FDCAN_ECR_TEC_Pos         (0U)
4065 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
4066 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4067 #define FDCAN_ECR_REC_Pos         (8U)
4068 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4069 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4070 #define FDCAN_ECR_RP_Pos          (15U)
4071 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4072 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4073 #define FDCAN_ECR_CEL_Pos         (16U)
4074 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4075 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4076 
4077 /*****************  Bit definition for FDCAN_PSR register  *********************/
4078 #define FDCAN_PSR_LEC_Pos         (0U)
4079 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4080 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4081 #define FDCAN_PSR_ACT_Pos         (3U)
4082 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4083 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4084 #define FDCAN_PSR_EP_Pos          (5U)
4085 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4086 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4087 #define FDCAN_PSR_EW_Pos          (6U)
4088 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4089 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4090 #define FDCAN_PSR_BO_Pos          (7U)
4091 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4092 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4093 #define FDCAN_PSR_DLEC_Pos        (8U)
4094 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4095 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4096 #define FDCAN_PSR_RESI_Pos        (11U)
4097 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4098 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4099 #define FDCAN_PSR_RBRS_Pos        (12U)
4100 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4101 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4102 #define FDCAN_PSR_REDL_Pos        (13U)
4103 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4104 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4105 #define FDCAN_PSR_PXE_Pos         (14U)
4106 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4107 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4108 #define FDCAN_PSR_TDCV_Pos        (16U)
4109 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4110 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4111 
4112 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4113 #define FDCAN_TDCR_TDCF_Pos       (0U)
4114 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4115 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4116 #define FDCAN_TDCR_TDCO_Pos       (8U)
4117 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4118 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4119 
4120 /*****************  Bit definition for FDCAN_IR register  **********************/
4121 #define FDCAN_IR_RF0N_Pos         (0U)
4122 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4123 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4124 #define FDCAN_IR_RF0F_Pos         (1U)
4125 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
4126 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4127 #define FDCAN_IR_RF0L_Pos         (2U)
4128 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
4129 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4130 #define FDCAN_IR_RF1N_Pos         (3U)
4131 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
4132 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4133 #define FDCAN_IR_RF1F_Pos         (4U)
4134 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
4135 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4136 #define FDCAN_IR_RF1L_Pos         (5U)
4137 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
4138 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4139 #define FDCAN_IR_HPM_Pos          (6U)
4140 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
4141 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4142 #define FDCAN_IR_TC_Pos           (7U)
4143 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
4144 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4145 #define FDCAN_IR_TCF_Pos          (8U)
4146 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
4147 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4148 #define FDCAN_IR_TFE_Pos          (9U)
4149 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
4150 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4151 #define FDCAN_IR_TEFN_Pos         (10U)
4152 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
4153 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4154 #define FDCAN_IR_TEFF_Pos         (11U)
4155 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
4156 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4157 #define FDCAN_IR_TEFL_Pos         (12U)
4158 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
4159 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4160 #define FDCAN_IR_TSW_Pos          (13U)
4161 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
4162 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4163 #define FDCAN_IR_MRAF_Pos         (14U)
4164 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
4165 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4166 #define FDCAN_IR_TOO_Pos          (15U)
4167 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
4168 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4169 #define FDCAN_IR_ELO_Pos          (16U)
4170 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
4171 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4172 #define FDCAN_IR_EP_Pos           (17U)
4173 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
4174 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4175 #define FDCAN_IR_EW_Pos           (18U)
4176 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
4177 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4178 #define FDCAN_IR_BO_Pos           (19U)
4179 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
4180 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4181 #define FDCAN_IR_WDI_Pos          (20U)
4182 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
4183 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4184 #define FDCAN_IR_PEA_Pos          (21U)
4185 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
4186 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4187 #define FDCAN_IR_PED_Pos          (22U)
4188 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
4189 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4190 #define FDCAN_IR_ARA_Pos          (23U)
4191 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
4192 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4193 
4194 /*****************  Bit definition for FDCAN_IE register  **********************/
4195 #define FDCAN_IE_RF0NE_Pos        (0U)
4196 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4197 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
4198 #define FDCAN_IE_RF0FE_Pos        (1U)
4199 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
4200 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
4201 #define FDCAN_IE_RF0LE_Pos        (2U)
4202 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
4203 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
4204 #define FDCAN_IE_RF1NE_Pos        (3U)
4205 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
4206 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
4207 #define FDCAN_IE_RF1FE_Pos        (4U)
4208 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
4209 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
4210 #define FDCAN_IE_RF1LE_Pos        (5U)
4211 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
4212 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
4213 #define FDCAN_IE_HPME_Pos         (6U)
4214 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
4215 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
4216 #define FDCAN_IE_TCE_Pos          (7U)
4217 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
4218 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
4219 #define FDCAN_IE_TCFE_Pos         (8U)
4220 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
4221 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
4222 #define FDCAN_IE_TFEE_Pos         (9U)
4223 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
4224 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
4225 #define FDCAN_IE_TEFNE_Pos        (10U)
4226 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
4227 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
4228 #define FDCAN_IE_TEFFE_Pos        (11U)
4229 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
4230 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
4231 #define FDCAN_IE_TEFLE_Pos        (12U)
4232 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
4233 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
4234 #define FDCAN_IE_TSWE_Pos         (13U)
4235 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
4236 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
4237 #define FDCAN_IE_MRAFE_Pos        (14U)
4238 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
4239 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
4240 #define FDCAN_IE_TOOE_Pos         (15U)
4241 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
4242 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
4243 #define FDCAN_IE_ELOE_Pos         (16U)
4244 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
4245 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
4246 #define FDCAN_IE_EPE_Pos          (17U)
4247 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
4248 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
4249 #define FDCAN_IE_EWE_Pos          (18U)
4250 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
4251 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
4252 #define FDCAN_IE_BOE_Pos          (19U)
4253 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
4254 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
4255 #define FDCAN_IE_WDIE_Pos         (20U)
4256 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
4257 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
4258 #define FDCAN_IE_PEAE_Pos         (21U)
4259 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
4260 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
4261 #define FDCAN_IE_PEDE_Pos         (22U)
4262 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
4263 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
4264 #define FDCAN_IE_ARAE_Pos         (23U)
4265 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
4266 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
4267 
4268 /*****************  Bit definition for FDCAN_ILS register  **********************/
4269 #define FDCAN_ILS_RXFIFO0_Pos     (0U)
4270 #define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
4271 #define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
4272                                                                                    Rx FIFO 0 is Full
4273                                                                                    Rx FIFO 0 Has New Message                */
4274 #define FDCAN_ILS_RXFIFO1_Pos     (1U)
4275 #define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
4276 #define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
4277                                                                                    Rx FIFO 1 is Full
4278                                                                                    Rx FIFO 1 Has New Message                */
4279 #define FDCAN_ILS_SMSG_Pos        (2U)
4280 #define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
4281 #define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
4282                                                                                    Transmission Completed
4283                                                                                    High Priority Message                    */
4284 #define FDCAN_ILS_TFERR_Pos       (3U)
4285 #define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
4286 #define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
4287                                                                                    Tx Event FIFO Full
4288                                                                                    Tx Event FIFO New Entry
4289                                                                                    Tx FIFO Empty Interrupt Line             */
4290 #define FDCAN_ILS_MISC_Pos        (4U)
4291 #define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
4292 #define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
4293                                                                                     Message RAM Access Failure
4294                                                                                     Timestamp Wraparound                    */
4295 #define FDCAN_ILS_BERR_Pos        (5U)
4296 #define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
4297 #define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
4298                                                                                    Error Logging Overflow                   */
4299 #define FDCAN_ILS_PERR_Pos        (6U)
4300 #define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
4301 #define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
4302                                                                                    Protocol Error in Data Phase Line
4303                                                                                    Protocol Error in Arbitration Phase Line
4304                                                                                    Watchdog Interrupt Line
4305                                                                                    Bus_Off Status
4306                                                                                    Warning Status                           */
4307 
4308 /*****************  Bit definition for FDCAN_ILE register  **********************/
4309 #define FDCAN_ILE_EINT0_Pos       (0U)
4310 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4311 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
4312 #define FDCAN_ILE_EINT1_Pos       (1U)
4313 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4314 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
4315 
4316 /*****************  Bit definition for FDCAN_RXGFC register  ********************/
4317 #define FDCAN_RXGFC_RRFE_Pos      (0U)
4318 #define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
4319 #define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
4320 #define FDCAN_RXGFC_RRFS_Pos      (1U)
4321 #define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
4322 #define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
4323 #define FDCAN_RXGFC_ANFE_Pos      (2U)
4324 #define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
4325 #define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
4326 #define FDCAN_RXGFC_ANFS_Pos      (4U)
4327 #define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
4328 #define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
4329 #define FDCAN_RXGFC_F1OM_Pos      (8U)
4330 #define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
4331 #define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
4332 #define FDCAN_RXGFC_F0OM_Pos      (9U)
4333 #define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
4334 #define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
4335 #define FDCAN_RXGFC_LSS_Pos       (16U)
4336 #define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
4337 #define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
4338 #define FDCAN_RXGFC_LSE_Pos       (24U)
4339 #define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
4340 #define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
4341 
4342 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4343 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4344 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4345 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
4346 
4347 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4348 #define FDCAN_HPMS_BIDX_Pos       (0U)
4349 #define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
4350 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
4351 #define FDCAN_HPMS_MSI_Pos        (6U)
4352 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4353 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
4354 #define FDCAN_HPMS_FIDX_Pos       (8U)
4355 #define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
4356 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
4357 #define FDCAN_HPMS_FLST_Pos       (15U)
4358 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4359 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
4360 
4361 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4362 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4363 #define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
4364 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
4365 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4366 #define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
4367 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
4368 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4369 #define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
4370 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
4371 #define FDCAN_RXF0S_F0F_Pos       (24U)
4372 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4373 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
4374 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4375 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4376 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
4377 
4378 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4379 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4380 #define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
4381 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
4382 
4383 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4384 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4385 #define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
4386 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
4387 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4388 #define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
4389 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
4390 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4391 #define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
4392 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
4393 #define FDCAN_RXF1S_F1F_Pos       (24U)
4394 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4395 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
4396 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4397 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4398 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
4399 
4400 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4401 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4402 #define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
4403 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
4404 
4405 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4406 #define FDCAN_TXBC_TFQM_Pos       (24U)
4407 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
4408 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
4409 
4410 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4411 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4412 #define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
4413 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
4414 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4415 #define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
4416 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
4417 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4418 #define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
4419 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
4420 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4421 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4422 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
4423 
4424 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
4425 #define FDCAN_TXBRP_TRP_Pos       (0U)
4426 #define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
4427 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
4428 
4429 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
4430 #define FDCAN_TXBAR_AR_Pos        (0U)
4431 #define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
4432 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
4433 
4434 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
4435 #define FDCAN_TXBCR_CR_Pos        (0U)
4436 #define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
4437 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
4438 
4439 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
4440 #define FDCAN_TXBTO_TO_Pos        (0U)
4441 #define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
4442 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
4443 
4444 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
4445 #define FDCAN_TXBCF_CF_Pos        (0U)
4446 #define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
4447 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
4448 
4449 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
4450 #define FDCAN_TXBTIE_TIE_Pos      (0U)
4451 #define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
4452 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
4453 
4454 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
4455 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
4456 #define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
4457 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
4458 
4459 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
4460 #define FDCAN_TXEFS_EFFL_Pos      (0U)
4461 #define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
4462 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
4463 #define FDCAN_TXEFS_EFGI_Pos      (8U)
4464 #define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
4465 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
4466 #define FDCAN_TXEFS_EFPI_Pos      (16U)
4467 #define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
4468 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
4469 #define FDCAN_TXEFS_EFF_Pos       (24U)
4470 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
4471 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
4472 #define FDCAN_TXEFS_TEFL_Pos      (25U)
4473 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
4474 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
4475 
4476 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
4477 #define FDCAN_TXEFA_EFAI_Pos      (0U)
4478 #define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
4479 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
4480 
4481 
4482 /*!<FDCAN config registers */
4483 /*****************  Bit definition for FDCAN_CKDIV register  *********************/
4484 #define FDCAN_CKDIV_PDIV_Pos      (0U)
4485 #define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
4486 #define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
4487 
4488 /******************************************************************************/
4489 /*                                                                            */
4490 /*                                    FLASH                                   */
4491 /*                                                                            */
4492 /******************************************************************************/
4493 /*******************  Bits definition for FLASH_ACR register  *****************/
4494 #define FLASH_ACR_LATENCY_Pos             (0U)
4495 #define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
4496 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
4497 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
4498 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
4499 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
4500 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
4501 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
4502 #define FLASH_ACR_LATENCY_5WS             (0x00000005U)
4503 #define FLASH_ACR_LATENCY_6WS             (0x00000006U)
4504 #define FLASH_ACR_LATENCY_7WS             (0x00000007U)
4505 #define FLASH_ACR_LATENCY_8WS             (0x00000008U)
4506 #define FLASH_ACR_LATENCY_9WS             (0x00000009U)
4507 #define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
4508 #define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
4509 #define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
4510 #define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
4511 #define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
4512 #define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
4513 #define FLASH_ACR_PRFTEN_Pos              (8U)
4514 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
4515 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
4516 #define FLASH_ACR_ICEN_Pos                (9U)
4517 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
4518 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
4519 #define FLASH_ACR_DCEN_Pos                (10U)
4520 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
4521 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
4522 #define FLASH_ACR_ICRST_Pos               (11U)
4523 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
4524 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
4525 #define FLASH_ACR_DCRST_Pos               (12U)
4526 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
4527 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
4528 #define FLASH_ACR_RUN_PD_Pos              (13U)
4529 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
4530 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
4531 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
4532 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
4533 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
4534 #define FLASH_ACR_DBG_SWEN_Pos            (18U)
4535 #define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
4536 #define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
4537 
4538 /*******************  Bits definition for FLASH_SR register  ******************/
4539 #define FLASH_SR_EOP_Pos                  (0U)
4540 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
4541 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
4542 #define FLASH_SR_OPERR_Pos                (1U)
4543 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
4544 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
4545 #define FLASH_SR_PROGERR_Pos              (3U)
4546 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
4547 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
4548 #define FLASH_SR_WRPERR_Pos               (4U)
4549 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
4550 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
4551 #define FLASH_SR_PGAERR_Pos               (5U)
4552 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
4553 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
4554 #define FLASH_SR_SIZERR_Pos               (6U)
4555 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
4556 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
4557 #define FLASH_SR_PGSERR_Pos               (7U)
4558 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
4559 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
4560 #define FLASH_SR_MISERR_Pos               (8U)
4561 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
4562 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
4563 #define FLASH_SR_FASTERR_Pos              (9U)
4564 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
4565 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
4566 #define FLASH_SR_RDERR_Pos                (14U)
4567 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
4568 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
4569 #define FLASH_SR_OPTVERR_Pos              (15U)
4570 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
4571 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
4572 #define FLASH_SR_BSY_Pos                  (16U)
4573 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
4574 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
4575 
4576 /*******************  Bits definition for FLASH_CR register  ******************/
4577 #define FLASH_CR_PG_Pos                   (0U)
4578 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
4579 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
4580 #define FLASH_CR_PER_Pos                  (1U)
4581 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
4582 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
4583 #define FLASH_CR_MER1_Pos                 (2U)
4584 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
4585 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
4586 #define FLASH_CR_PNB_Pos                  (3U)
4587 #define FLASH_CR_PNB_Msk                  (0x3FUL << FLASH_CR_PNB_Pos)         /*!< 0x000001F8 */
4588 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
4589 #define FLASH_CR_STRT_Pos                 (16U)
4590 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
4591 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
4592 #define FLASH_CR_OPTSTRT_Pos              (17U)
4593 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
4594 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
4595 #define FLASH_CR_FSTPG_Pos                (18U)
4596 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
4597 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
4598 #define FLASH_CR_EOPIE_Pos                (24U)
4599 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
4600 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
4601 #define FLASH_CR_ERRIE_Pos                (25U)
4602 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
4603 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
4604 #define FLASH_CR_RDERRIE_Pos              (26U)
4605 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
4606 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
4607 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
4608 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
4609 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
4610 #define FLASH_CR_SEC_PROT1_Pos            (28U)
4611 #define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
4612 #define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
4613 #define FLASH_CR_OPTLOCK_Pos              (30U)
4614 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
4615 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
4616 #define FLASH_CR_LOCK_Pos                 (31U)
4617 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
4618 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
4619 
4620 /*******************  Bits definition for FLASH_ECCR register  ***************/
4621 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
4622 #define FLASH_ECCR_ADDR_ECC_Msk           (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */
4623 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
4624 #define FLASH_ECCR_SYSF_ECC_Pos           (22U)
4625 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
4626 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
4627 #define FLASH_ECCR_ECCIE_Pos              (24U)
4628 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
4629 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
4630 #define FLASH_ECCR_ECCC_Pos               (30U)
4631 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
4632 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
4633 #define FLASH_ECCR_ECCD_Pos               (31U)
4634 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
4635 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
4636 
4637 /*******************  Bits definition for FLASH_OPTR register  ***************/
4638 #define FLASH_OPTR_RDP_Pos                (0U)
4639 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
4640 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
4641 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
4642 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
4643 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
4644 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
4645 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
4646 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
4647 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
4648 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
4649 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
4650 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
4651 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
4652 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
4653 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
4654 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
4655 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
4656 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
4657 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
4658 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
4659 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
4660 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
4661 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
4662 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
4663 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
4664 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
4665 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
4666 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
4667 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
4668 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
4669 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
4670 #define FLASH_OPTR_nBOOT1_Pos             (23U)
4671 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
4672 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
4673 #define FLASH_OPTR_SRAM_PE_Pos            (24U)
4674 #define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
4675 #define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
4676 #define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
4677 #define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
4678 #define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
4679 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
4680 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
4681 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
4682 #define FLASH_OPTR_nBOOT0_Pos             (27U)
4683 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
4684 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
4685 #define FLASH_OPTR_NRST_MODE_Pos          (28U)
4686 #define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
4687 #define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
4688 #define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
4689 #define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
4690 #define FLASH_OPTR_IRHEN_Pos              (30U)
4691 #define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
4692 #define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
4693 
4694 /******************  Bits definition for FLASH_PCROP1SR register  **********/
4695 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
4696 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */
4697 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
4698 
4699 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
4700 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
4701 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */
4702 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
4703 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
4704 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
4705 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
4706 
4707 /******************  Bits definition for FLASH_WRP1AR register  ***************/
4708 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
4709 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */
4710 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
4711 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
4712 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */
4713 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
4714 
4715 /******************  Bits definition for FLASH_WRPB1R register  ***************/
4716 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
4717 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */
4718 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
4719 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
4720 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */
4721 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
4722 
4723 
4724 /******************  Bits definition for FLASH_SEC1R register  **************/
4725 #define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
4726 #define FLASH_SEC1R_SEC_SIZE1_Msk         (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */
4727 #define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
4728 #define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
4729 #define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
4730 #define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
4731 
4732 
4733 /******************************************************************************/
4734 /*                                                                            */
4735 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
4736 /*                                                                            */
4737 /******************************************************************************/
4738 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
4739 #define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
4740 #define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
4741 #define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
4742 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
4743 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
4744 #define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
4745 #define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
4746 #define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
4747 #define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
4748 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
4749 #define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
4750 #define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
4751 #define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
4752 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
4753 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
4754 #define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
4755 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
4756 #define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
4757 #define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
4758 #define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
4759 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
4760 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
4761 #define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
4762 #define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
4763 #define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
4764 #define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
4765 /******************  Bit definition for FMAC_PARAM register  ******************/
4766 #define FMAC_PARAM_P_Pos              (0U)
4767 #define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
4768 #define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
4769 #define FMAC_PARAM_Q_Pos              (8U)
4770 #define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
4771 #define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
4772 #define FMAC_PARAM_R_Pos              (16U)
4773 #define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
4774 #define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
4775 #define FMAC_PARAM_FUNC_Pos           (24U)
4776 #define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
4777 #define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
4778 #define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
4779 #define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
4780 #define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
4781 #define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
4782 #define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
4783 #define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
4784 #define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
4785 #define FMAC_PARAM_START_Pos          (31U)
4786 #define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
4787 #define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
4788 /********************  Bit definition for FMAC_CR register  *******************/
4789 #define FMAC_CR_RIEN_Pos              (0U)
4790 #define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
4791 #define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
4792 #define FMAC_CR_WIEN_Pos              (1U)
4793 #define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
4794 #define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
4795 #define FMAC_CR_OVFLIEN_Pos           (2U)
4796 #define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
4797 #define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
4798 #define FMAC_CR_UNFLIEN_Pos           (3U)
4799 #define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
4800 #define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
4801 #define FMAC_CR_SATIEN_Pos            (4U)
4802 #define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
4803 #define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
4804 #define FMAC_CR_DMAREN_Pos            (8U)
4805 #define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
4806 #define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
4807 #define FMAC_CR_DMAWEN_Pos            (9U)
4808 #define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
4809 #define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
4810 #define FMAC_CR_CLIPEN_Pos            (15U)
4811 #define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
4812 #define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
4813 #define FMAC_CR_RESET_Pos             (16U)
4814 #define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
4815 #define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
4816 /*******************  Bit definition for FMAC_SR register  ********************/
4817 #define FMAC_SR_YEMPTY_Pos            (0U)
4818 #define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
4819 #define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
4820 #define FMAC_SR_X1FULL_Pos            (1U)
4821 #define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
4822 #define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
4823 #define FMAC_SR_OVFL_Pos              (8U)
4824 #define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
4825 #define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
4826 #define FMAC_SR_UNFL_Pos              (9U)
4827 #define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
4828 #define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
4829 #define FMAC_SR_SAT_Pos               (10U)
4830 #define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
4831 #define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
4832 /******************  Bit definition for FMAC_WDATA register  ******************/
4833 #define FMAC_WDATA_WDATA_Pos          (0U)
4834 #define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
4835 #define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
4836 /******************  Bit definition for FMACX_RDATA register  *****************/
4837 #define FMAC_RDATA_RDATA_Pos          (0U)
4838 #define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
4839 #define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
4840 
4841 
4842 /******************************************************************************/
4843 /*                                                                            */
4844 /*                       General Purpose IOs (GPIO)                           */
4845 /*                                                                            */
4846 /******************************************************************************/
4847 /******************  Bits definition for GPIO_MODER register  *****************/
4848 #define GPIO_MODER_MODE0_Pos           (0U)
4849 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
4850 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
4851 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
4852 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
4853 #define GPIO_MODER_MODE1_Pos           (2U)
4854 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
4855 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
4856 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
4857 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
4858 #define GPIO_MODER_MODE2_Pos           (4U)
4859 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
4860 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
4861 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
4862 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
4863 #define GPIO_MODER_MODE3_Pos           (6U)
4864 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
4865 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
4866 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
4867 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
4868 #define GPIO_MODER_MODE4_Pos           (8U)
4869 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
4870 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
4871 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
4872 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
4873 #define GPIO_MODER_MODE5_Pos           (10U)
4874 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
4875 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
4876 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
4877 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
4878 #define GPIO_MODER_MODE6_Pos           (12U)
4879 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
4880 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
4881 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
4882 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
4883 #define GPIO_MODER_MODE7_Pos           (14U)
4884 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
4885 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
4886 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
4887 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
4888 #define GPIO_MODER_MODE8_Pos           (16U)
4889 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
4890 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
4891 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
4892 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
4893 #define GPIO_MODER_MODE9_Pos           (18U)
4894 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
4895 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
4896 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
4897 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
4898 #define GPIO_MODER_MODE10_Pos          (20U)
4899 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
4900 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
4901 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
4902 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
4903 #define GPIO_MODER_MODE11_Pos          (22U)
4904 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
4905 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
4906 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
4907 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
4908 #define GPIO_MODER_MODE12_Pos          (24U)
4909 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
4910 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
4911 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
4912 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
4913 #define GPIO_MODER_MODE13_Pos          (26U)
4914 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
4915 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
4916 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
4917 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
4918 #define GPIO_MODER_MODE14_Pos          (28U)
4919 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
4920 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
4921 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
4922 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
4923 #define GPIO_MODER_MODE15_Pos          (30U)
4924 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
4925 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
4926 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
4927 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
4928 
4929 /* Legacy defines */
4930 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
4931 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
4932 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
4933 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
4934 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
4935 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
4936 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
4937 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
4938 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
4939 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
4940 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
4941 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
4942 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
4943 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
4944 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
4945 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
4946 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
4947 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
4948 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
4949 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
4950 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
4951 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
4952 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
4953 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
4954 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
4955 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
4956 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
4957 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
4958 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
4959 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
4960 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
4961 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
4962 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
4963 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
4964 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
4965 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
4966 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
4967 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
4968 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
4969 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
4970 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
4971 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
4972 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
4973 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
4974 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
4975 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
4976 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
4977 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
4978 
4979 /******************  Bits definition for GPIO_OTYPER register  ****************/
4980 #define GPIO_OTYPER_OT0_Pos            (0U)
4981 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
4982 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
4983 #define GPIO_OTYPER_OT1_Pos            (1U)
4984 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
4985 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
4986 #define GPIO_OTYPER_OT2_Pos            (2U)
4987 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
4988 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
4989 #define GPIO_OTYPER_OT3_Pos            (3U)
4990 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
4991 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
4992 #define GPIO_OTYPER_OT4_Pos            (4U)
4993 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
4994 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
4995 #define GPIO_OTYPER_OT5_Pos            (5U)
4996 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
4997 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
4998 #define GPIO_OTYPER_OT6_Pos            (6U)
4999 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
5000 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
5001 #define GPIO_OTYPER_OT7_Pos            (7U)
5002 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
5003 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
5004 #define GPIO_OTYPER_OT8_Pos            (8U)
5005 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
5006 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
5007 #define GPIO_OTYPER_OT9_Pos            (9U)
5008 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
5009 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
5010 #define GPIO_OTYPER_OT10_Pos           (10U)
5011 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
5012 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
5013 #define GPIO_OTYPER_OT11_Pos           (11U)
5014 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
5015 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
5016 #define GPIO_OTYPER_OT12_Pos           (12U)
5017 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
5018 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
5019 #define GPIO_OTYPER_OT13_Pos           (13U)
5020 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
5021 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
5022 #define GPIO_OTYPER_OT14_Pos           (14U)
5023 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
5024 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
5025 #define GPIO_OTYPER_OT15_Pos           (15U)
5026 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
5027 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
5028 
5029 /* Legacy defines */
5030 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
5031 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
5032 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
5033 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
5034 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
5035 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
5036 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
5037 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
5038 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
5039 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
5040 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
5041 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
5042 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
5043 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
5044 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
5045 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
5046 
5047 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
5048 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
5049 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
5050 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
5051 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
5052 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
5053 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
5054 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
5055 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
5056 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
5057 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
5058 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
5059 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
5060 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
5061 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
5062 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
5063 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
5064 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
5065 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
5066 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
5067 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
5068 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
5069 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
5070 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
5071 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
5072 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
5073 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
5074 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
5075 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
5076 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
5077 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
5078 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
5079 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
5080 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
5081 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
5082 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
5083 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
5084 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
5085 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
5086 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
5087 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
5088 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
5089 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
5090 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
5091 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
5092 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
5093 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
5094 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
5095 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
5096 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
5097 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
5098 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
5099 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
5100 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
5101 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
5102 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
5103 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
5104 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
5105 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
5106 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
5107 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
5108 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
5109 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
5110 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
5111 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
5112 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
5113 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
5114 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
5115 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
5116 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
5117 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
5118 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
5119 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
5120 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
5121 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
5122 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
5123 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
5124 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
5125 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
5126 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
5127 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
5128 
5129 /* Legacy defines */
5130 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
5131 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
5132 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
5133 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
5134 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
5135 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
5136 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
5137 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
5138 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
5139 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
5140 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
5141 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
5142 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
5143 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
5144 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
5145 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
5146 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
5147 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
5148 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
5149 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
5150 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
5151 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
5152 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
5153 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
5154 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
5155 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
5156 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
5157 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
5158 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
5159 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
5160 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
5161 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
5162 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
5163 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
5164 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
5165 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
5166 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
5167 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
5168 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
5169 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
5170 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
5171 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
5172 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
5173 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
5174 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
5175 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
5176 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
5177 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
5178 
5179 /******************  Bits definition for GPIO_PUPDR register  *****************/
5180 #define GPIO_PUPDR_PUPD0_Pos           (0U)
5181 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
5182 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
5183 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
5184 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
5185 #define GPIO_PUPDR_PUPD1_Pos           (2U)
5186 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
5187 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
5188 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
5189 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
5190 #define GPIO_PUPDR_PUPD2_Pos           (4U)
5191 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
5192 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
5193 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
5194 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
5195 #define GPIO_PUPDR_PUPD3_Pos           (6U)
5196 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
5197 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
5198 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
5199 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
5200 #define GPIO_PUPDR_PUPD4_Pos           (8U)
5201 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
5202 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
5203 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
5204 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
5205 #define GPIO_PUPDR_PUPD5_Pos           (10U)
5206 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
5207 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
5208 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
5209 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
5210 #define GPIO_PUPDR_PUPD6_Pos           (12U)
5211 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
5212 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
5213 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
5214 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
5215 #define GPIO_PUPDR_PUPD7_Pos           (14U)
5216 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
5217 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
5218 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
5219 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
5220 #define GPIO_PUPDR_PUPD8_Pos           (16U)
5221 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
5222 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
5223 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
5224 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
5225 #define GPIO_PUPDR_PUPD9_Pos           (18U)
5226 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
5227 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
5228 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
5229 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
5230 #define GPIO_PUPDR_PUPD10_Pos          (20U)
5231 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
5232 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
5233 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
5234 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
5235 #define GPIO_PUPDR_PUPD11_Pos          (22U)
5236 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
5237 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
5238 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
5239 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
5240 #define GPIO_PUPDR_PUPD12_Pos          (24U)
5241 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
5242 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
5243 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
5244 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
5245 #define GPIO_PUPDR_PUPD13_Pos          (26U)
5246 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
5247 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
5248 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
5249 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
5250 #define GPIO_PUPDR_PUPD14_Pos          (28U)
5251 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
5252 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
5253 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
5254 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
5255 #define GPIO_PUPDR_PUPD15_Pos          (30U)
5256 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
5257 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
5258 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
5259 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
5260 
5261 /* Legacy defines */
5262 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
5263 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
5264 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
5265 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
5266 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
5267 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
5268 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
5269 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
5270 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
5271 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
5272 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
5273 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
5274 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
5275 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
5276 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
5277 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
5278 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
5279 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
5280 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
5281 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
5282 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
5283 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
5284 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
5285 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
5286 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
5287 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
5288 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
5289 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
5290 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
5291 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
5292 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
5293 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
5294 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
5295 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
5296 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
5297 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
5298 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
5299 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
5300 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
5301 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
5302 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
5303 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
5304 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
5305 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
5306 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
5307 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
5308 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
5309 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
5310 
5311 /******************  Bits definition for GPIO_IDR register  *******************/
5312 #define GPIO_IDR_ID0_Pos               (0U)
5313 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
5314 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
5315 #define GPIO_IDR_ID1_Pos               (1U)
5316 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
5317 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
5318 #define GPIO_IDR_ID2_Pos               (2U)
5319 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
5320 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
5321 #define GPIO_IDR_ID3_Pos               (3U)
5322 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
5323 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
5324 #define GPIO_IDR_ID4_Pos               (4U)
5325 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
5326 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
5327 #define GPIO_IDR_ID5_Pos               (5U)
5328 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
5329 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
5330 #define GPIO_IDR_ID6_Pos               (6U)
5331 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
5332 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
5333 #define GPIO_IDR_ID7_Pos               (7U)
5334 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
5335 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
5336 #define GPIO_IDR_ID8_Pos               (8U)
5337 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
5338 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
5339 #define GPIO_IDR_ID9_Pos               (9U)
5340 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
5341 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
5342 #define GPIO_IDR_ID10_Pos              (10U)
5343 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
5344 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
5345 #define GPIO_IDR_ID11_Pos              (11U)
5346 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
5347 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
5348 #define GPIO_IDR_ID12_Pos              (12U)
5349 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
5350 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
5351 #define GPIO_IDR_ID13_Pos              (13U)
5352 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
5353 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
5354 #define GPIO_IDR_ID14_Pos              (14U)
5355 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
5356 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
5357 #define GPIO_IDR_ID15_Pos              (15U)
5358 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
5359 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
5360 
5361 /* Legacy defines */
5362 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
5363 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
5364 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
5365 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
5366 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
5367 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
5368 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
5369 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
5370 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
5371 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
5372 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
5373 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
5374 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
5375 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
5376 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
5377 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
5378 
5379 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5380 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
5381 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
5382 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
5383 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
5384 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
5385 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
5386 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
5387 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
5388 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
5389 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
5390 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
5391 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
5392 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
5393 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
5394 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
5395 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
5396 
5397 /******************  Bits definition for GPIO_ODR register  *******************/
5398 #define GPIO_ODR_OD0_Pos               (0U)
5399 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
5400 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
5401 #define GPIO_ODR_OD1_Pos               (1U)
5402 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
5403 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
5404 #define GPIO_ODR_OD2_Pos               (2U)
5405 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
5406 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
5407 #define GPIO_ODR_OD3_Pos               (3U)
5408 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
5409 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
5410 #define GPIO_ODR_OD4_Pos               (4U)
5411 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
5412 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
5413 #define GPIO_ODR_OD5_Pos               (5U)
5414 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
5415 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
5416 #define GPIO_ODR_OD6_Pos               (6U)
5417 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
5418 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
5419 #define GPIO_ODR_OD7_Pos               (7U)
5420 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
5421 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
5422 #define GPIO_ODR_OD8_Pos               (8U)
5423 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
5424 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
5425 #define GPIO_ODR_OD9_Pos               (9U)
5426 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
5427 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
5428 #define GPIO_ODR_OD10_Pos              (10U)
5429 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
5430 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
5431 #define GPIO_ODR_OD11_Pos              (11U)
5432 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
5433 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
5434 #define GPIO_ODR_OD12_Pos              (12U)
5435 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
5436 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
5437 #define GPIO_ODR_OD13_Pos              (13U)
5438 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
5439 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
5440 #define GPIO_ODR_OD14_Pos              (14U)
5441 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
5442 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
5443 #define GPIO_ODR_OD15_Pos              (15U)
5444 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
5445 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
5446 
5447 /* Legacy defines */
5448 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
5449 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
5450 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
5451 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
5452 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
5453 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
5454 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
5455 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
5456 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
5457 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
5458 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
5459 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
5460 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
5461 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
5462 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
5463 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
5464 
5465 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5466 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
5467 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
5468 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
5469 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
5470 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
5471 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
5472 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
5473 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
5474 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
5475 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
5476 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
5477 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
5478 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
5479 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
5480 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
5481 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
5482 
5483 /******************  Bits definition for GPIO_BSRR register  ******************/
5484 #define GPIO_BSRR_BS0_Pos              (0U)
5485 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
5486 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
5487 #define GPIO_BSRR_BS1_Pos              (1U)
5488 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
5489 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
5490 #define GPIO_BSRR_BS2_Pos              (2U)
5491 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
5492 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
5493 #define GPIO_BSRR_BS3_Pos              (3U)
5494 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
5495 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
5496 #define GPIO_BSRR_BS4_Pos              (4U)
5497 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
5498 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
5499 #define GPIO_BSRR_BS5_Pos              (5U)
5500 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
5501 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
5502 #define GPIO_BSRR_BS6_Pos              (6U)
5503 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
5504 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
5505 #define GPIO_BSRR_BS7_Pos              (7U)
5506 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
5507 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
5508 #define GPIO_BSRR_BS8_Pos              (8U)
5509 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
5510 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
5511 #define GPIO_BSRR_BS9_Pos              (9U)
5512 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
5513 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
5514 #define GPIO_BSRR_BS10_Pos             (10U)
5515 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
5516 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
5517 #define GPIO_BSRR_BS11_Pos             (11U)
5518 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
5519 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
5520 #define GPIO_BSRR_BS12_Pos             (12U)
5521 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
5522 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
5523 #define GPIO_BSRR_BS13_Pos             (13U)
5524 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
5525 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
5526 #define GPIO_BSRR_BS14_Pos             (14U)
5527 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
5528 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
5529 #define GPIO_BSRR_BS15_Pos             (15U)
5530 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
5531 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
5532 #define GPIO_BSRR_BR0_Pos              (16U)
5533 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
5534 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
5535 #define GPIO_BSRR_BR1_Pos              (17U)
5536 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
5537 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
5538 #define GPIO_BSRR_BR2_Pos              (18U)
5539 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
5540 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
5541 #define GPIO_BSRR_BR3_Pos              (19U)
5542 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
5543 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
5544 #define GPIO_BSRR_BR4_Pos              (20U)
5545 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
5546 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
5547 #define GPIO_BSRR_BR5_Pos              (21U)
5548 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
5549 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
5550 #define GPIO_BSRR_BR6_Pos              (22U)
5551 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
5552 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
5553 #define GPIO_BSRR_BR7_Pos              (23U)
5554 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
5555 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
5556 #define GPIO_BSRR_BR8_Pos              (24U)
5557 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
5558 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
5559 #define GPIO_BSRR_BR9_Pos              (25U)
5560 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
5561 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
5562 #define GPIO_BSRR_BR10_Pos             (26U)
5563 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
5564 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
5565 #define GPIO_BSRR_BR11_Pos             (27U)
5566 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
5567 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
5568 #define GPIO_BSRR_BR12_Pos             (28U)
5569 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
5570 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
5571 #define GPIO_BSRR_BR13_Pos             (29U)
5572 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
5573 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
5574 #define GPIO_BSRR_BR14_Pos             (30U)
5575 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
5576 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
5577 #define GPIO_BSRR_BR15_Pos             (31U)
5578 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
5579 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
5580 
5581 /* Legacy defines */
5582 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
5583 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
5584 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
5585 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
5586 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
5587 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
5588 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
5589 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
5590 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
5591 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
5592 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
5593 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
5594 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
5595 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
5596 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
5597 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
5598 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
5599 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
5600 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
5601 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
5602 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
5603 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
5604 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
5605 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
5606 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
5607 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
5608 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
5609 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
5610 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
5611 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
5612 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
5613 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
5614 
5615 /****************** Bit definition for GPIO_LCKR register *********************/
5616 #define GPIO_LCKR_LCK0_Pos             (0U)
5617 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
5618 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
5619 #define GPIO_LCKR_LCK1_Pos             (1U)
5620 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
5621 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
5622 #define GPIO_LCKR_LCK2_Pos             (2U)
5623 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
5624 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
5625 #define GPIO_LCKR_LCK3_Pos             (3U)
5626 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
5627 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
5628 #define GPIO_LCKR_LCK4_Pos             (4U)
5629 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
5630 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
5631 #define GPIO_LCKR_LCK5_Pos             (5U)
5632 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
5633 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
5634 #define GPIO_LCKR_LCK6_Pos             (6U)
5635 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
5636 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
5637 #define GPIO_LCKR_LCK7_Pos             (7U)
5638 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
5639 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
5640 #define GPIO_LCKR_LCK8_Pos             (8U)
5641 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
5642 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
5643 #define GPIO_LCKR_LCK9_Pos             (9U)
5644 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
5645 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
5646 #define GPIO_LCKR_LCK10_Pos            (10U)
5647 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
5648 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
5649 #define GPIO_LCKR_LCK11_Pos            (11U)
5650 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
5651 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
5652 #define GPIO_LCKR_LCK12_Pos            (12U)
5653 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
5654 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
5655 #define GPIO_LCKR_LCK13_Pos            (13U)
5656 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
5657 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
5658 #define GPIO_LCKR_LCK14_Pos            (14U)
5659 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
5660 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
5661 #define GPIO_LCKR_LCK15_Pos            (15U)
5662 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
5663 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
5664 #define GPIO_LCKR_LCKK_Pos             (16U)
5665 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
5666 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
5667 
5668 /****************** Bit definition for GPIO_AFRL register *********************/
5669 #define GPIO_AFRL_AFSEL0_Pos           (0U)
5670 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
5671 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
5672 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
5673 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
5674 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
5675 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
5676 #define GPIO_AFRL_AFSEL1_Pos           (4U)
5677 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
5678 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
5679 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
5680 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
5681 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
5682 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
5683 #define GPIO_AFRL_AFSEL2_Pos           (8U)
5684 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
5685 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
5686 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
5687 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
5688 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
5689 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
5690 #define GPIO_AFRL_AFSEL3_Pos           (12U)
5691 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
5692 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
5693 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
5694 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
5695 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
5696 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
5697 #define GPIO_AFRL_AFSEL4_Pos           (16U)
5698 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
5699 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
5700 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
5701 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
5702 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
5703 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
5704 #define GPIO_AFRL_AFSEL5_Pos           (20U)
5705 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
5706 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
5707 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
5708 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
5709 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
5710 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
5711 #define GPIO_AFRL_AFSEL6_Pos           (24U)
5712 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
5713 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
5714 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
5715 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
5716 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
5717 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
5718 #define GPIO_AFRL_AFSEL7_Pos           (28U)
5719 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
5720 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
5721 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
5722 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
5723 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
5724 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
5725 
5726 /* Legacy defines */
5727 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
5728 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
5729 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
5730 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
5731 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
5732 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
5733 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
5734 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
5735 
5736 /****************** Bit definition for GPIO_AFRH register *********************/
5737 #define GPIO_AFRH_AFSEL8_Pos           (0U)
5738 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
5739 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
5740 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
5741 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
5742 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
5743 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
5744 #define GPIO_AFRH_AFSEL9_Pos           (4U)
5745 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
5746 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
5747 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
5748 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
5749 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
5750 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
5751 #define GPIO_AFRH_AFSEL10_Pos          (8U)
5752 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
5753 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
5754 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
5755 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
5756 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
5757 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
5758 #define GPIO_AFRH_AFSEL11_Pos          (12U)
5759 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
5760 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
5761 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
5762 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
5763 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
5764 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
5765 #define GPIO_AFRH_AFSEL12_Pos          (16U)
5766 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
5767 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
5768 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
5769 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
5770 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
5771 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
5772 #define GPIO_AFRH_AFSEL13_Pos          (20U)
5773 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
5774 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
5775 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
5776 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
5777 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
5778 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
5779 #define GPIO_AFRH_AFSEL14_Pos          (24U)
5780 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
5781 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
5782 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
5783 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
5784 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
5785 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
5786 #define GPIO_AFRH_AFSEL15_Pos          (28U)
5787 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
5788 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
5789 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
5790 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
5791 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
5792 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
5793 
5794 /* Legacy defines */
5795 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
5796 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
5797 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
5798 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
5799 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
5800 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
5801 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
5802 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
5803 
5804 /******************  Bits definition for GPIO_BRR register  ******************/
5805 #define GPIO_BRR_BR0_Pos               (0U)
5806 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
5807 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
5808 #define GPIO_BRR_BR1_Pos               (1U)
5809 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
5810 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
5811 #define GPIO_BRR_BR2_Pos               (2U)
5812 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
5813 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
5814 #define GPIO_BRR_BR3_Pos               (3U)
5815 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
5816 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
5817 #define GPIO_BRR_BR4_Pos               (4U)
5818 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
5819 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
5820 #define GPIO_BRR_BR5_Pos               (5U)
5821 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
5822 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
5823 #define GPIO_BRR_BR6_Pos               (6U)
5824 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
5825 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
5826 #define GPIO_BRR_BR7_Pos               (7U)
5827 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
5828 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
5829 #define GPIO_BRR_BR8_Pos               (8U)
5830 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
5831 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
5832 #define GPIO_BRR_BR9_Pos               (9U)
5833 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
5834 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
5835 #define GPIO_BRR_BR10_Pos              (10U)
5836 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
5837 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
5838 #define GPIO_BRR_BR11_Pos              (11U)
5839 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
5840 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
5841 #define GPIO_BRR_BR12_Pos              (12U)
5842 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
5843 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
5844 #define GPIO_BRR_BR13_Pos              (13U)
5845 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
5846 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
5847 #define GPIO_BRR_BR14_Pos              (14U)
5848 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
5849 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
5850 #define GPIO_BRR_BR15_Pos              (15U)
5851 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
5852 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
5853 
5854 /* Legacy defines */
5855 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
5856 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
5857 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
5858 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
5859 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
5860 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
5861 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
5862 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
5863 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
5864 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
5865 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
5866 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
5867 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
5868 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
5869 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
5870 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
5871 
5872 
5873 /******************************************************************************/
5874 /*                                                                            */
5875 /*                      Inter-integrated Circuit Interface (I2C)              */
5876 /*                                                                            */
5877 /******************************************************************************/
5878 /*******************  Bit definition for I2C_CR1 register  *******************/
5879 #define I2C_CR1_PE_Pos               (0U)
5880 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
5881 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
5882 #define I2C_CR1_TXIE_Pos             (1U)
5883 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
5884 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
5885 #define I2C_CR1_RXIE_Pos             (2U)
5886 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
5887 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
5888 #define I2C_CR1_ADDRIE_Pos           (3U)
5889 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
5890 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
5891 #define I2C_CR1_NACKIE_Pos           (4U)
5892 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
5893 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
5894 #define I2C_CR1_STOPIE_Pos           (5U)
5895 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
5896 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
5897 #define I2C_CR1_TCIE_Pos             (6U)
5898 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
5899 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
5900 #define I2C_CR1_ERRIE_Pos            (7U)
5901 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
5902 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
5903 #define I2C_CR1_DNF_Pos              (8U)
5904 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
5905 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
5906 #define I2C_CR1_ANFOFF_Pos           (12U)
5907 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
5908 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
5909 #define I2C_CR1_SWRST_Pos            (13U)
5910 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
5911 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
5912 #define I2C_CR1_TXDMAEN_Pos          (14U)
5913 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
5914 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
5915 #define I2C_CR1_RXDMAEN_Pos          (15U)
5916 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
5917 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
5918 #define I2C_CR1_SBC_Pos              (16U)
5919 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
5920 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
5921 #define I2C_CR1_NOSTRETCH_Pos        (17U)
5922 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
5923 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
5924 #define I2C_CR1_WUPEN_Pos            (18U)
5925 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
5926 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
5927 #define I2C_CR1_GCEN_Pos             (19U)
5928 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
5929 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
5930 #define I2C_CR1_SMBHEN_Pos           (20U)
5931 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
5932 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
5933 #define I2C_CR1_SMBDEN_Pos           (21U)
5934 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
5935 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
5936 #define I2C_CR1_ALERTEN_Pos          (22U)
5937 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
5938 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
5939 #define I2C_CR1_PECEN_Pos            (23U)
5940 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
5941 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
5942 
5943 /******************  Bit definition for I2C_CR2 register  ********************/
5944 #define I2C_CR2_SADD_Pos             (0U)
5945 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
5946 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
5947 #define I2C_CR2_RD_WRN_Pos           (10U)
5948 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
5949 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
5950 #define I2C_CR2_ADD10_Pos            (11U)
5951 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
5952 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
5953 #define I2C_CR2_HEAD10R_Pos          (12U)
5954 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
5955 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
5956 #define I2C_CR2_START_Pos            (13U)
5957 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
5958 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
5959 #define I2C_CR2_STOP_Pos             (14U)
5960 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
5961 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
5962 #define I2C_CR2_NACK_Pos             (15U)
5963 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
5964 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
5965 #define I2C_CR2_NBYTES_Pos           (16U)
5966 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
5967 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
5968 #define I2C_CR2_RELOAD_Pos           (24U)
5969 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
5970 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
5971 #define I2C_CR2_AUTOEND_Pos          (25U)
5972 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
5973 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
5974 #define I2C_CR2_PECBYTE_Pos          (26U)
5975 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
5976 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
5977 
5978 /*******************  Bit definition for I2C_OAR1 register  ******************/
5979 #define I2C_OAR1_OA1_Pos             (0U)
5980 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
5981 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
5982 #define I2C_OAR1_OA1MODE_Pos         (10U)
5983 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
5984 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
5985 #define I2C_OAR1_OA1EN_Pos           (15U)
5986 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
5987 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
5988 
5989 /*******************  Bit definition for I2C_OAR2 register  ******************/
5990 #define I2C_OAR2_OA2_Pos             (1U)
5991 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
5992 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
5993 #define I2C_OAR2_OA2MSK_Pos          (8U)
5994 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
5995 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
5996 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
5997 #define I2C_OAR2_OA2MASK01_Pos       (8U)
5998 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
5999 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
6000 #define I2C_OAR2_OA2MASK02_Pos       (9U)
6001 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
6002 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
6003 #define I2C_OAR2_OA2MASK03_Pos       (8U)
6004 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
6005 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
6006 #define I2C_OAR2_OA2MASK04_Pos       (10U)
6007 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
6008 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
6009 #define I2C_OAR2_OA2MASK05_Pos       (8U)
6010 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
6011 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
6012 #define I2C_OAR2_OA2MASK06_Pos       (9U)
6013 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
6014 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
6015 #define I2C_OAR2_OA2MASK07_Pos       (8U)
6016 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
6017 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
6018 #define I2C_OAR2_OA2EN_Pos           (15U)
6019 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
6020 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
6021 
6022 /*******************  Bit definition for I2C_TIMINGR register *******************/
6023 #define I2C_TIMINGR_SCLL_Pos         (0U)
6024 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
6025 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
6026 #define I2C_TIMINGR_SCLH_Pos         (8U)
6027 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
6028 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
6029 #define I2C_TIMINGR_SDADEL_Pos       (16U)
6030 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
6031 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
6032 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
6033 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
6034 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
6035 #define I2C_TIMINGR_PRESC_Pos        (28U)
6036 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
6037 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
6038 
6039 /******************* Bit definition for I2C_TIMEOUTR register *******************/
6040 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
6041 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
6042 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
6043 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
6044 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
6045 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
6046 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
6047 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
6048 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
6049 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
6050 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
6051 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
6052 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
6053 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
6054 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
6055 
6056 /******************  Bit definition for I2C_ISR register  *********************/
6057 #define I2C_ISR_TXE_Pos              (0U)
6058 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
6059 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
6060 #define I2C_ISR_TXIS_Pos             (1U)
6061 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
6062 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
6063 #define I2C_ISR_RXNE_Pos             (2U)
6064 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
6065 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
6066 #define I2C_ISR_ADDR_Pos             (3U)
6067 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
6068 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
6069 #define I2C_ISR_NACKF_Pos            (4U)
6070 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
6071 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
6072 #define I2C_ISR_STOPF_Pos            (5U)
6073 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
6074 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
6075 #define I2C_ISR_TC_Pos               (6U)
6076 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
6077 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
6078 #define I2C_ISR_TCR_Pos              (7U)
6079 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
6080 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
6081 #define I2C_ISR_BERR_Pos             (8U)
6082 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
6083 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
6084 #define I2C_ISR_ARLO_Pos             (9U)
6085 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
6086 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
6087 #define I2C_ISR_OVR_Pos              (10U)
6088 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
6089 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
6090 #define I2C_ISR_PECERR_Pos           (11U)
6091 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
6092 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
6093 #define I2C_ISR_TIMEOUT_Pos          (12U)
6094 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
6095 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
6096 #define I2C_ISR_ALERT_Pos            (13U)
6097 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
6098 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
6099 #define I2C_ISR_BUSY_Pos             (15U)
6100 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
6101 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
6102 #define I2C_ISR_DIR_Pos              (16U)
6103 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
6104 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
6105 #define I2C_ISR_ADDCODE_Pos          (17U)
6106 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
6107 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
6108 
6109 /******************  Bit definition for I2C_ICR register  *********************/
6110 #define I2C_ICR_ADDRCF_Pos           (3U)
6111 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
6112 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
6113 #define I2C_ICR_NACKCF_Pos           (4U)
6114 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
6115 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
6116 #define I2C_ICR_STOPCF_Pos           (5U)
6117 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
6118 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
6119 #define I2C_ICR_BERRCF_Pos           (8U)
6120 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
6121 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
6122 #define I2C_ICR_ARLOCF_Pos           (9U)
6123 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
6124 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
6125 #define I2C_ICR_OVRCF_Pos            (10U)
6126 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
6127 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
6128 #define I2C_ICR_PECCF_Pos            (11U)
6129 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
6130 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
6131 #define I2C_ICR_TIMOUTCF_Pos         (12U)
6132 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
6133 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
6134 #define I2C_ICR_ALERTCF_Pos          (13U)
6135 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
6136 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
6137 
6138 /******************  Bit definition for I2C_PECR register  *********************/
6139 #define I2C_PECR_PEC_Pos             (0U)
6140 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
6141 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
6142 
6143 /******************  Bit definition for I2C_RXDR register  *********************/
6144 #define I2C_RXDR_RXDATA_Pos          (0U)
6145 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
6146 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
6147 
6148 /******************  Bit definition for I2C_TXDR register  *********************/
6149 #define I2C_TXDR_TXDATA_Pos          (0U)
6150 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
6151 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
6152 
6153 /******************************************************************************/
6154 /*                                                                            */
6155 /*                           Independent WATCHDOG                             */
6156 /*                                                                            */
6157 /******************************************************************************/
6158 /*******************  Bit definition for IWDG_KR register  ********************/
6159 #define IWDG_KR_KEY_Pos      (0U)
6160 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
6161 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
6162 
6163 /*******************  Bit definition for IWDG_PR register  ********************/
6164 #define IWDG_PR_PR_Pos       (0U)
6165 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
6166 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
6167 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
6168 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
6169 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
6170 
6171 /*******************  Bit definition for IWDG_RLR register  *******************/
6172 #define IWDG_RLR_RL_Pos      (0U)
6173 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
6174 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
6175 
6176 /*******************  Bit definition for IWDG_SR register  ********************/
6177 #define IWDG_SR_PVU_Pos      (0U)
6178 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
6179 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
6180 #define IWDG_SR_RVU_Pos      (1U)
6181 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
6182 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
6183 #define IWDG_SR_WVU_Pos      (2U)
6184 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
6185 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
6186 
6187 /*******************  Bit definition for IWDG_KR register  ********************/
6188 #define IWDG_WINR_WIN_Pos    (0U)
6189 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
6190 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
6191 
6192 /******************************************************************************/
6193 /*                                                                            */
6194 /*                         Operational Amplifier (OPAMP)                      */
6195 /*                                                                            */
6196 /******************************************************************************/
6197 /*********************  Bit definition for OPAMPx_CSR register  ***************/
6198 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
6199 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)         /*!< 0x00000001 */
6200 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
6201 #define OPAMP_CSR_FORCEVP_Pos        (1U)
6202 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)          /*!< 0x00000002 */
6203 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
6204 #define OPAMP_CSR_VPSEL_Pos          (2U)
6205 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x0000000C */
6206 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
6207 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000004 */
6208 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000008 */
6209 #define OPAMP_CSR_USERTRIM_Pos       (4U)
6210 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00000010 */
6211 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
6212 #define OPAMP_CSR_VMSEL_Pos          (5U)
6213 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000060 */
6214 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
6215 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000020 */
6216 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000040 */
6217 #define OPAMP_CSR_HIGHSPEEDEN_Pos    (7U)
6218 #define OPAMP_CSR_HIGHSPEEDEN_Msk    (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)      /*!< 0x00000080 */
6219 #define OPAMP_CSR_HIGHSPEEDEN        OPAMP_CSR_HIGHSPEEDEN_Msk                 /*!< High speed mode enable */
6220 #define OPAMP_CSR_OPAMPINTEN_Pos     (8U)
6221 #define OPAMP_CSR_OPAMPINTEN_Msk     (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)       /*!< 0x00000100 */
6222 #define OPAMP_CSR_OPAMPINTEN         OPAMP_CSR_OPAMPINTEN_Msk                  /*!< Internal output enable */
6223 #define OPAMP_CSR_CALON_Pos          (11U)
6224 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00000800 */
6225 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
6226 #define OPAMP_CSR_CALSEL_Pos         (12U)
6227 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00003000 */
6228 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
6229 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00001000 */
6230 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
6231 #define OPAMP_CSR_PGGAIN_Pos         (14U)
6232 #define OPAMP_CSR_PGGAIN_Msk         (0x1FUL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x0007C000 */
6233 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
6234 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00004000 */
6235 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00008000 */
6236 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00010000 */
6237 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00020000 */
6238 #define OPAMP_CSR_PGGAIN_4           (0x10UL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x00040000 */
6239 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
6240 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)     /*!< 0x00F80000 */
6241 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
6242 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
6243 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)     /*!< 0x1F000000 */
6244 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
6245 #define OPAMP_CSR_OUTCAL_Pos         (30U)
6246 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)           /*!< 0x40000000 */
6247 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP output status flag */
6248 #define OPAMP_CSR_LOCK_Pos           (31U)
6249 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
6250 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP control/status register lock */
6251 
6252 /*********************  Bit definition for OPAMPx_TCMR register  ***************/
6253 
6254 #define OPAMP_TCMR_VMSSEL_Pos        (0U)
6255 #define OPAMP_TCMR_VMSSEL_Msk        (0x1UL << OPAMP_TCMR_VMSSEL_Pos)          /*!< 0x00000001 */
6256 #define OPAMP_TCMR_VMSSEL            OPAMP_TCMR_VMSSEL_Msk                     /*!< Secondary inverting input selection */
6257 #define OPAMP_TCMR_VPSSEL_Pos        (1U)
6258 #define OPAMP_TCMR_VPSSEL_Msk        (0x3UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000006 */
6259 #define OPAMP_TCMR_VPSSEL            OPAMP_TCMR_VPSSEL_Msk                     /*!< Secondary non inverting input selection */
6260 #define OPAMP_TCMR_VPSSEL_0          (0x1UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000002 */
6261 #define OPAMP_TCMR_VPSSEL_1          (0x2UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000004 */
6262 #define OPAMP_TCMR_T1CMEN_Pos        (3U)
6263 #define OPAMP_TCMR_T1CMEN_Msk        (0x1UL << OPAMP_TCMR_T1CMEN_Pos)          /*!< 0x00000008 */
6264 #define OPAMP_TCMR_T1CMEN            OPAMP_TCMR_T1CMEN_Msk                     /*!< Timer 1 controlled mux mode enable */
6265 #define OPAMP_TCMR_T8CMEN_Pos        (4U)
6266 #define OPAMP_TCMR_T8CMEN_Msk        (0x1UL << OPAMP_TCMR_T8CMEN_Pos)          /*!< 0x00000010 */
6267 #define OPAMP_TCMR_T8CMEN            OPAMP_TCMR_T8CMEN_Msk                     /*!< Timer 8 controlled mux mode enable */
6268 #define OPAMP_TCMR_T20CMEN_Pos       (5U)
6269 #define OPAMP_TCMR_T20CMEN_Msk       (0x1UL << OPAMP_TCMR_T20CMEN_Pos)         /*!< 0x00000020 */
6270 #define OPAMP_TCMR_T20CMEN           OPAMP_TCMR_T20CMEN_Msk                    /*!< Timer 20 controlled mux mode enable */
6271 #define OPAMP_TCMR_LOCK_Pos          (31U)
6272 #define OPAMP_TCMR_LOCK_Msk          (0x1UL << OPAMP_TCMR_LOCK_Pos)            /*!< 0x80000000 */
6273 #define OPAMP_TCMR_LOCK              OPAMP_TCMR_LOCK_Msk                       /*!< OPAMP SW control register lock */
6274 
6275 
6276 /******************************************************************************/
6277 /*                                                                            */
6278 /*                             Power Control                                  */
6279 /*                                                                            */
6280 /******************************************************************************/
6281 
6282 /********************  Bit definition for PWR_CR1 register  ********************/
6283 
6284 #define PWR_CR1_LPR_Pos              (14U)
6285 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
6286 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
6287 #define PWR_CR1_VOS_Pos              (9U)
6288 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
6289 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
6290 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
6291 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
6292 #define PWR_CR1_DBP_Pos              (8U)
6293 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
6294 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
6295 #define PWR_CR1_LPMS_Pos             (0U)
6296 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
6297 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
6298 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
6299 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
6300 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
6301 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
6302 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
6303 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
6304 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
6305 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
6306 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
6307 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
6308 
6309 
6310 /********************  Bit definition for PWR_CR2 register  ********************/
6311 
6312 /*!< PVME  Peripheral Voltage Monitor Enable */
6313 #define PWR_CR2_PVME_Pos             (4U)
6314 #define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
6315 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
6316 #define PWR_CR2_PVME4_Pos            (7U)
6317 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
6318 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
6319 #define PWR_CR2_PVME3_Pos            (6U)
6320 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
6321 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
6322 #define PWR_CR2_PVME2_Pos            (5U)
6323 #define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
6324 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
6325 #define PWR_CR2_PVME1_Pos            (4U)
6326 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
6327 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
6328 
6329 /*!< PVD level configuration */
6330 #define PWR_CR2_PLS_Pos              (1U)
6331 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
6332 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
6333 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
6334 #define PWR_CR2_PLS_LEV1_Pos         (1U)
6335 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
6336 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
6337 #define PWR_CR2_PLS_LEV2_Pos         (2U)
6338 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
6339 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
6340 #define PWR_CR2_PLS_LEV3_Pos         (1U)
6341 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
6342 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
6343 #define PWR_CR2_PLS_LEV4_Pos         (3U)
6344 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
6345 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
6346 #define PWR_CR2_PLS_LEV5_Pos         (1U)
6347 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
6348 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
6349 #define PWR_CR2_PLS_LEV6_Pos         (2U)
6350 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
6351 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
6352 #define PWR_CR2_PLS_LEV7_Pos         (1U)
6353 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
6354 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
6355 #define PWR_CR2_PVDE_Pos             (0U)
6356 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
6357 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
6358 
6359 /********************  Bit definition for PWR_CR3 register  ********************/
6360 #define PWR_CR3_EIWF_Pos             (15U)
6361 #define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
6362 #define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
6363 #define PWR_CR3_APC_Pos              (10U)
6364 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
6365 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
6366 #define PWR_CR3_RRS_Pos              (8U)
6367 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
6368 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
6369 #define PWR_CR3_EWUP5_Pos            (4U)
6370 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
6371 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
6372 #define PWR_CR3_EWUP4_Pos            (3U)
6373 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
6374 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
6375 #define PWR_CR3_EWUP3_Pos            (2U)
6376 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
6377 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
6378 #define PWR_CR3_EWUP2_Pos            (1U)
6379 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
6380 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
6381 #define PWR_CR3_EWUP1_Pos            (0U)
6382 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
6383 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
6384 #define PWR_CR3_EWUP_Pos             (0U)
6385 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
6386 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
6387 
6388 /********************  Bit definition for PWR_CR4 register  ********************/
6389 #define PWR_CR4_VBRS_Pos             (9U)
6390 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
6391 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
6392 #define PWR_CR4_VBE_Pos              (8U)
6393 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
6394 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
6395 #define PWR_CR4_WP5_Pos              (4U)
6396 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
6397 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
6398 #define PWR_CR4_WP4_Pos              (3U)
6399 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
6400 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
6401 #define PWR_CR4_WP3_Pos              (2U)
6402 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
6403 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
6404 #define PWR_CR4_WP2_Pos              (1U)
6405 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
6406 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
6407 #define PWR_CR4_WP1_Pos              (0U)
6408 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
6409 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
6410 
6411 /********************  Bit definition for PWR_SR1 register  ********************/
6412 #define PWR_SR1_WUFI_Pos             (15U)
6413 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
6414 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
6415 #define PWR_SR1_SBF_Pos              (8U)
6416 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
6417 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
6418 #define PWR_SR1_WUF_Pos              (0U)
6419 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
6420 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
6421 #define PWR_SR1_WUF5_Pos             (4U)
6422 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
6423 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
6424 #define PWR_SR1_WUF4_Pos             (3U)
6425 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
6426 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
6427 #define PWR_SR1_WUF3_Pos             (2U)
6428 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
6429 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
6430 #define PWR_SR1_WUF2_Pos             (1U)
6431 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
6432 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
6433 #define PWR_SR1_WUF1_Pos             (0U)
6434 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
6435 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
6436 
6437 /********************  Bit definition for PWR_SR2 register  ********************/
6438 #define PWR_SR2_PVMO4_Pos            (15U)
6439 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
6440 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
6441 #define PWR_SR2_PVMO3_Pos            (14U)
6442 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
6443 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
6444 #define PWR_SR2_PVMO2_Pos            (13U)
6445 #define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
6446 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
6447 #define PWR_SR2_PVMO1_Pos            (12U)
6448 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
6449 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
6450 #define PWR_SR2_PVDO_Pos             (11U)
6451 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
6452 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
6453 #define PWR_SR2_VOSF_Pos             (10U)
6454 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
6455 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
6456 #define PWR_SR2_REGLPF_Pos           (9U)
6457 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
6458 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
6459 #define PWR_SR2_REGLPS_Pos           (8U)
6460 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
6461 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
6462 
6463 /********************  Bit definition for PWR_SCR register  ********************/
6464 #define PWR_SCR_CSBF_Pos             (8U)
6465 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
6466 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
6467 #define PWR_SCR_CWUF_Pos             (0U)
6468 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
6469 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
6470 #define PWR_SCR_CWUF5_Pos            (4U)
6471 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
6472 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
6473 #define PWR_SCR_CWUF4_Pos            (3U)
6474 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
6475 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
6476 #define PWR_SCR_CWUF3_Pos            (2U)
6477 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
6478 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
6479 #define PWR_SCR_CWUF2_Pos            (1U)
6480 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
6481 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
6482 #define PWR_SCR_CWUF1_Pos            (0U)
6483 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
6484 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
6485 
6486 /********************  Bit definition for PWR_PUCRA register  ********************/
6487 #define PWR_PUCRA_PA15_Pos           (15U)
6488 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
6489 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
6490 #define PWR_PUCRA_PA13_Pos           (13U)
6491 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
6492 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
6493 #define PWR_PUCRA_PA12_Pos           (12U)
6494 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
6495 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
6496 #define PWR_PUCRA_PA11_Pos           (11U)
6497 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
6498 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
6499 #define PWR_PUCRA_PA10_Pos           (10U)
6500 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
6501 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
6502 #define PWR_PUCRA_PA9_Pos            (9U)
6503 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
6504 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
6505 #define PWR_PUCRA_PA8_Pos            (8U)
6506 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
6507 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
6508 #define PWR_PUCRA_PA7_Pos            (7U)
6509 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
6510 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
6511 #define PWR_PUCRA_PA6_Pos            (6U)
6512 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
6513 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
6514 #define PWR_PUCRA_PA5_Pos            (5U)
6515 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
6516 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
6517 #define PWR_PUCRA_PA4_Pos            (4U)
6518 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
6519 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
6520 #define PWR_PUCRA_PA3_Pos            (3U)
6521 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
6522 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
6523 #define PWR_PUCRA_PA2_Pos            (2U)
6524 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
6525 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
6526 #define PWR_PUCRA_PA1_Pos            (1U)
6527 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
6528 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
6529 #define PWR_PUCRA_PA0_Pos            (0U)
6530 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
6531 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
6532 
6533 /********************  Bit definition for PWR_PDCRA register  ********************/
6534 #define PWR_PDCRA_PA14_Pos           (14U)
6535 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
6536 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
6537 #define PWR_PDCRA_PA12_Pos           (12U)
6538 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
6539 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
6540 #define PWR_PDCRA_PA11_Pos           (11U)
6541 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
6542 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
6543 #define PWR_PDCRA_PA10_Pos           (10U)
6544 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
6545 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
6546 #define PWR_PDCRA_PA9_Pos            (9U)
6547 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
6548 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
6549 #define PWR_PDCRA_PA8_Pos            (8U)
6550 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
6551 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
6552 #define PWR_PDCRA_PA7_Pos            (7U)
6553 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
6554 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
6555 #define PWR_PDCRA_PA6_Pos            (6U)
6556 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
6557 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
6558 #define PWR_PDCRA_PA5_Pos            (5U)
6559 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
6560 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
6561 #define PWR_PDCRA_PA4_Pos            (4U)
6562 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
6563 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
6564 #define PWR_PDCRA_PA3_Pos            (3U)
6565 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
6566 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
6567 #define PWR_PDCRA_PA2_Pos            (2U)
6568 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
6569 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
6570 #define PWR_PDCRA_PA1_Pos            (1U)
6571 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
6572 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
6573 #define PWR_PDCRA_PA0_Pos            (0U)
6574 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
6575 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
6576 
6577 /********************  Bit definition for PWR_PUCRB register  ********************/
6578 
6579 #define PWR_PUCRB_PB15_Pos           (15U)
6580 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
6581 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
6582 #define PWR_PUCRB_PB14_Pos           (14U)
6583 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
6584 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
6585 #define PWR_PUCRB_PB13_Pos           (13U)
6586 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
6587 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
6588 #define PWR_PUCRB_PB12_Pos           (12U)
6589 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
6590 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
6591 #define PWR_PUCRB_PB11_Pos           (11U)
6592 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
6593 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
6594 #define PWR_PUCRB_PB10_Pos           (10U)
6595 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
6596 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
6597 #define PWR_PUCRB_PB9_Pos            (9U)
6598 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
6599 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
6600 #define PWR_PUCRB_PB8_Pos            (8U)
6601 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
6602 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
6603 #define PWR_PUCRB_PB7_Pos            (7U)
6604 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
6605 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
6606 #define PWR_PUCRB_PB6_Pos            (6U)
6607 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
6608 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
6609 #define PWR_PUCRB_PB5_Pos            (5U)
6610 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
6611 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
6612 #define PWR_PUCRB_PB4_Pos            (4U)
6613 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
6614 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
6615 #define PWR_PUCRB_PB3_Pos            (3U)
6616 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
6617 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
6618 #define PWR_PUCRB_PB2_Pos            (2U)
6619 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
6620 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
6621 #define PWR_PUCRB_PB1_Pos            (1U)
6622 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
6623 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
6624 #define PWR_PUCRB_PB0_Pos            (0U)
6625 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
6626 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
6627 
6628 /********************  Bit definition for PWR_PDCRB register  ********************/
6629 #define PWR_PDCRB_PB15_Pos           (15U)
6630 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
6631 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
6632 #define PWR_PDCRB_PB14_Pos           (14U)
6633 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
6634 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
6635 #define PWR_PDCRB_PB13_Pos           (13U)
6636 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
6637 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
6638 #define PWR_PDCRB_PB12_Pos           (12U)
6639 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
6640 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
6641 #define PWR_PDCRB_PB11_Pos           (11U)
6642 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
6643 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
6644 #define PWR_PDCRB_PB10_Pos           (10U)
6645 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
6646 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
6647 #define PWR_PDCRB_PB9_Pos            (9U)
6648 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
6649 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
6650 #define PWR_PDCRB_PB8_Pos            (8U)
6651 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
6652 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
6653 #define PWR_PDCRB_PB7_Pos            (7U)
6654 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
6655 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
6656 #define PWR_PDCRB_PB6_Pos            (6U)
6657 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
6658 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
6659 #define PWR_PDCRB_PB5_Pos            (5U)
6660 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
6661 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
6662 #define PWR_PDCRB_PB3_Pos            (3U)
6663 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
6664 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
6665 #define PWR_PDCRB_PB2_Pos            (2U)
6666 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
6667 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
6668 #define PWR_PDCRB_PB1_Pos            (1U)
6669 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
6670 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
6671 #define PWR_PDCRB_PB0_Pos            (0U)
6672 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
6673 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
6674 
6675 /********************  Bit definition for PWR_PUCRC register  ********************/
6676 #define PWR_PUCRC_PC15_Pos           (15U)
6677 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
6678 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
6679 #define PWR_PUCRC_PC14_Pos           (14U)
6680 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
6681 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
6682 #define PWR_PUCRC_PC13_Pos           (13U)
6683 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
6684 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
6685 #define PWR_PUCRC_PC12_Pos           (12U)
6686 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
6687 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
6688 #define PWR_PUCRC_PC11_Pos           (11U)
6689 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
6690 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
6691 #define PWR_PUCRC_PC10_Pos           (10U)
6692 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
6693 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
6694 #define PWR_PUCRC_PC9_Pos            (9U)
6695 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
6696 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
6697 #define PWR_PUCRC_PC8_Pos            (8U)
6698 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
6699 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
6700 #define PWR_PUCRC_PC7_Pos            (7U)
6701 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
6702 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
6703 #define PWR_PUCRC_PC6_Pos            (6U)
6704 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
6705 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
6706 #define PWR_PUCRC_PC5_Pos            (5U)
6707 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
6708 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
6709 #define PWR_PUCRC_PC4_Pos            (4U)
6710 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
6711 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
6712 #define PWR_PUCRC_PC3_Pos            (3U)
6713 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
6714 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
6715 #define PWR_PUCRC_PC2_Pos            (2U)
6716 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
6717 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
6718 #define PWR_PUCRC_PC1_Pos            (1U)
6719 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
6720 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
6721 #define PWR_PUCRC_PC0_Pos            (0U)
6722 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
6723 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
6724 
6725 /********************  Bit definition for PWR_PDCRC register  ********************/
6726 #define PWR_PDCRC_PC15_Pos           (15U)
6727 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
6728 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
6729 #define PWR_PDCRC_PC14_Pos           (14U)
6730 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
6731 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
6732 #define PWR_PDCRC_PC13_Pos           (13U)
6733 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
6734 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
6735 #define PWR_PDCRC_PC12_Pos           (12U)
6736 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
6737 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
6738 #define PWR_PDCRC_PC11_Pos           (11U)
6739 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
6740 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
6741 #define PWR_PDCRC_PC10_Pos           (10U)
6742 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
6743 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
6744 #define PWR_PDCRC_PC9_Pos            (9U)
6745 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
6746 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
6747 #define PWR_PDCRC_PC8_Pos            (8U)
6748 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
6749 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
6750 #define PWR_PDCRC_PC7_Pos            (7U)
6751 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
6752 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
6753 #define PWR_PDCRC_PC6_Pos            (6U)
6754 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
6755 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
6756 #define PWR_PDCRC_PC5_Pos            (5U)
6757 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
6758 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
6759 #define PWR_PDCRC_PC4_Pos            (4U)
6760 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
6761 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
6762 #define PWR_PDCRC_PC3_Pos            (3U)
6763 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
6764 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
6765 #define PWR_PDCRC_PC2_Pos            (2U)
6766 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
6767 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
6768 #define PWR_PDCRC_PC1_Pos            (1U)
6769 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
6770 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
6771 #define PWR_PDCRC_PC0_Pos            (0U)
6772 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
6773 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
6774 
6775 /********************  Bit definition for PWR_PUCRD register  ********************/
6776 #define PWR_PUCRD_PD15_Pos           (15U)
6777 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
6778 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
6779 #define PWR_PUCRD_PD14_Pos           (14U)
6780 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
6781 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
6782 #define PWR_PUCRD_PD13_Pos           (13U)
6783 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
6784 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
6785 #define PWR_PUCRD_PD12_Pos           (12U)
6786 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
6787 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
6788 #define PWR_PUCRD_PD11_Pos           (11U)
6789 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
6790 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
6791 #define PWR_PUCRD_PD10_Pos           (10U)
6792 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
6793 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
6794 #define PWR_PUCRD_PD9_Pos            (9U)
6795 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
6796 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
6797 #define PWR_PUCRD_PD8_Pos            (8U)
6798 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
6799 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
6800 #define PWR_PUCRD_PD7_Pos            (7U)
6801 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
6802 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
6803 #define PWR_PUCRD_PD6_Pos            (6U)
6804 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
6805 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
6806 #define PWR_PUCRD_PD5_Pos            (5U)
6807 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
6808 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
6809 #define PWR_PUCRD_PD4_Pos            (4U)
6810 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
6811 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
6812 #define PWR_PUCRD_PD3_Pos            (3U)
6813 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
6814 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
6815 #define PWR_PUCRD_PD2_Pos            (2U)
6816 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
6817 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
6818 #define PWR_PUCRD_PD1_Pos            (1U)
6819 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
6820 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
6821 #define PWR_PUCRD_PD0_Pos            (0U)
6822 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
6823 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
6824 
6825 /********************  Bit definition for PWR_PDCRD register  ********************/
6826 #define PWR_PDCRD_PD15_Pos           (15U)
6827 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
6828 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
6829 #define PWR_PDCRD_PD14_Pos           (14U)
6830 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
6831 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
6832 #define PWR_PDCRD_PD13_Pos           (13U)
6833 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
6834 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
6835 #define PWR_PDCRD_PD12_Pos           (12U)
6836 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
6837 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
6838 #define PWR_PDCRD_PD11_Pos           (11U)
6839 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
6840 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
6841 #define PWR_PDCRD_PD10_Pos           (10U)
6842 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
6843 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
6844 #define PWR_PDCRD_PD9_Pos            (9U)
6845 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
6846 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
6847 #define PWR_PDCRD_PD8_Pos            (8U)
6848 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
6849 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
6850 #define PWR_PDCRD_PD7_Pos            (7U)
6851 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
6852 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
6853 #define PWR_PDCRD_PD6_Pos            (6U)
6854 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
6855 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
6856 #define PWR_PDCRD_PD5_Pos            (5U)
6857 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
6858 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
6859 #define PWR_PDCRD_PD4_Pos            (4U)
6860 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
6861 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
6862 #define PWR_PDCRD_PD3_Pos            (3U)
6863 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
6864 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
6865 #define PWR_PDCRD_PD2_Pos            (2U)
6866 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
6867 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
6868 #define PWR_PDCRD_PD1_Pos            (1U)
6869 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
6870 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
6871 #define PWR_PDCRD_PD0_Pos            (0U)
6872 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
6873 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
6874 
6875 /********************  Bit definition for PWR_PUCRE register  ********************/
6876 #define PWR_PUCRE_PE15_Pos           (15U)
6877 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
6878 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
6879 #define PWR_PUCRE_PE14_Pos           (14U)
6880 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
6881 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
6882 #define PWR_PUCRE_PE13_Pos           (13U)
6883 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
6884 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
6885 #define PWR_PUCRE_PE12_Pos           (12U)
6886 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
6887 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
6888 #define PWR_PUCRE_PE11_Pos           (11U)
6889 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
6890 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
6891 #define PWR_PUCRE_PE10_Pos           (10U)
6892 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
6893 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
6894 #define PWR_PUCRE_PE9_Pos            (9U)
6895 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
6896 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
6897 #define PWR_PUCRE_PE8_Pos            (8U)
6898 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
6899 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
6900 #define PWR_PUCRE_PE7_Pos            (7U)
6901 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
6902 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
6903 #define PWR_PUCRE_PE6_Pos            (6U)
6904 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
6905 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
6906 #define PWR_PUCRE_PE5_Pos            (5U)
6907 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
6908 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
6909 #define PWR_PUCRE_PE4_Pos            (4U)
6910 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
6911 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
6912 #define PWR_PUCRE_PE3_Pos            (3U)
6913 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
6914 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
6915 #define PWR_PUCRE_PE2_Pos            (2U)
6916 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
6917 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
6918 #define PWR_PUCRE_PE1_Pos            (1U)
6919 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
6920 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
6921 #define PWR_PUCRE_PE0_Pos            (0U)
6922 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
6923 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
6924 
6925 /********************  Bit definition for PWR_PDCRE register  ********************/
6926 #define PWR_PDCRE_PE15_Pos           (15U)
6927 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
6928 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
6929 #define PWR_PDCRE_PE14_Pos           (14U)
6930 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
6931 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
6932 #define PWR_PDCRE_PE13_Pos           (13U)
6933 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
6934 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
6935 #define PWR_PDCRE_PE12_Pos           (12U)
6936 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
6937 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
6938 #define PWR_PDCRE_PE11_Pos           (11U)
6939 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
6940 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
6941 #define PWR_PDCRE_PE10_Pos           (10U)
6942 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
6943 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
6944 #define PWR_PDCRE_PE9_Pos            (9U)
6945 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
6946 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
6947 #define PWR_PDCRE_PE8_Pos            (8U)
6948 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
6949 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
6950 #define PWR_PDCRE_PE7_Pos            (7U)
6951 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
6952 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
6953 #define PWR_PDCRE_PE6_Pos            (6U)
6954 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
6955 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
6956 #define PWR_PDCRE_PE5_Pos            (5U)
6957 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
6958 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
6959 #define PWR_PDCRE_PE4_Pos            (4U)
6960 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
6961 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
6962 #define PWR_PDCRE_PE3_Pos            (3U)
6963 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
6964 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
6965 #define PWR_PDCRE_PE2_Pos            (2U)
6966 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
6967 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
6968 #define PWR_PDCRE_PE1_Pos            (1U)
6969 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
6970 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
6971 #define PWR_PDCRE_PE0_Pos            (0U)
6972 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
6973 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
6974 
6975 /********************  Bit definition for PWR_PUCRF register  ********************/
6976 #define PWR_PUCRF_PF15_Pos           (15U)
6977 #define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
6978 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
6979 #define PWR_PUCRF_PF14_Pos           (14U)
6980 #define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
6981 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
6982 #define PWR_PUCRF_PF13_Pos           (13U)
6983 #define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
6984 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
6985 #define PWR_PUCRF_PF12_Pos           (12U)
6986 #define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
6987 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
6988 #define PWR_PUCRF_PF11_Pos           (11U)
6989 #define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
6990 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
6991 #define PWR_PUCRF_PF10_Pos           (10U)
6992 #define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
6993 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
6994 #define PWR_PUCRF_PF9_Pos            (9U)
6995 #define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
6996 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
6997 #define PWR_PUCRF_PF8_Pos            (8U)
6998 #define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
6999 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
7000 #define PWR_PUCRF_PF7_Pos            (7U)
7001 #define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
7002 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
7003 #define PWR_PUCRF_PF6_Pos            (6U)
7004 #define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
7005 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
7006 #define PWR_PUCRF_PF5_Pos            (5U)
7007 #define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
7008 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
7009 #define PWR_PUCRF_PF4_Pos            (4U)
7010 #define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
7011 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
7012 #define PWR_PUCRF_PF3_Pos            (3U)
7013 #define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
7014 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
7015 #define PWR_PUCRF_PF2_Pos            (2U)
7016 #define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
7017 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
7018 #define PWR_PUCRF_PF1_Pos            (1U)
7019 #define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
7020 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
7021 #define PWR_PUCRF_PF0_Pos            (0U)
7022 #define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
7023 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
7024 
7025 /********************  Bit definition for PWR_PDCRF register  ********************/
7026 #define PWR_PDCRF_PF10_Pos           (10U)
7027 #define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
7028 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
7029 #define PWR_PDCRF_PF9_Pos            (9U)
7030 #define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
7031 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
7032 #define PWR_PDCRF_PF2_Pos            (2U)
7033 #define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
7034 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
7035 #define PWR_PDCRF_PF1_Pos            (1U)
7036 #define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
7037 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
7038 #define PWR_PDCRF_PF0_Pos            (0U)
7039 #define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
7040 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
7041 
7042 /********************  Bit definition for PWR_PUCRG register  ********************/
7043 #define PWR_PUCRG_PG10_Pos           (10U)
7044 #define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
7045 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
7046 
7047 /********************  Bit definition for PWR_PDCRG register  ********************/
7048 #define PWR_PDCRG_PG10_Pos           (10U)
7049 #define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
7050 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
7051 #define PWR_PDCRG_PG9_Pos            (9U)
7052 #define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
7053 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
7054 #define PWR_PDCRG_PG8_Pos            (8U)
7055 #define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
7056 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
7057 #define PWR_PDCRG_PG7_Pos            (7U)
7058 #define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
7059 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
7060 #define PWR_PDCRG_PG6_Pos            (6U)
7061 #define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
7062 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
7063 #define PWR_PDCRG_PG5_Pos            (5U)
7064 #define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
7065 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
7066 #define PWR_PDCRG_PG4_Pos            (4U)
7067 #define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
7068 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
7069 #define PWR_PDCRG_PG3_Pos            (3U)
7070 #define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
7071 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
7072 #define PWR_PDCRG_PG2_Pos            (2U)
7073 #define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
7074 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
7075 #define PWR_PDCRG_PG1_Pos            (1U)
7076 #define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
7077 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
7078 #define PWR_PDCRG_PG0_Pos            (0U)
7079 #define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
7080 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
7081 
7082 /********************  Bit definition for PWR_CR5 register  ********************/
7083 #define PWR_CR5_R1MODE_Pos           (8U)
7084 #define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
7085 #define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
7086 
7087 
7088 /******************************************************************************/
7089 /*                                                                            */
7090 /*                         Reset and Clock Control                            */
7091 /*                                                                            */
7092 /******************************************************************************/
7093 /*
7094 * @brief Specific device feature definitions  (not present on all devices in the STM32G4 series)
7095 */
7096 
7097 #define RCC_HSI48_SUPPORT
7098 #define RCC_PLLP_DIV_2_31_SUPPORT
7099 
7100 /********************  Bit definition for RCC_CR register  ********************/
7101 #define RCC_CR_HSION_Pos                     (8U)
7102 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
7103 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
7104 #define RCC_CR_HSIKERON_Pos                  (9U)
7105 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
7106 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
7107 #define RCC_CR_HSIRDY_Pos                    (10U)
7108 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
7109 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
7110 
7111 #define RCC_CR_HSEON_Pos                     (16U)
7112 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
7113 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
7114 #define RCC_CR_HSERDY_Pos                    (17U)
7115 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
7116 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
7117 #define RCC_CR_HSEBYP_Pos                    (18U)
7118 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
7119 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
7120 #define RCC_CR_CSSON_Pos                     (19U)
7121 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
7122 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
7123 
7124 #define RCC_CR_PLLON_Pos                     (24U)
7125 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
7126 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
7127 #define RCC_CR_PLLRDY_Pos                    (25U)
7128 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
7129 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
7130 
7131 /********************  Bit definition for RCC_ICSCR register  ***************/
7132 /*!< HSICAL configuration */
7133 #define RCC_ICSCR_HSICAL_Pos                 (16U)
7134 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
7135 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
7136 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
7137 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
7138 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
7139 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
7140 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
7141 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
7142 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
7143 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
7144 
7145 /*!< HSITRIM configuration */
7146 #define RCC_ICSCR_HSITRIM_Pos                (24U)
7147 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
7148 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
7149 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
7150 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
7151 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
7152 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
7153 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
7154 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
7155 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
7156 
7157 /********************  Bit definition for RCC_CFGR register  ******************/
7158 /*!< SW configuration */
7159 #define RCC_CFGR_SW_Pos                      (0U)
7160 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
7161 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
7162 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
7163 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
7164 
7165 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
7166 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
7167 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
7168 
7169 /*!< SWS configuration */
7170 #define RCC_CFGR_SWS_Pos                     (2U)
7171 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
7172 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
7173 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
7174 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
7175 
7176 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
7177 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
7178 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
7179 
7180 /*!< HPRE configuration */
7181 #define RCC_CFGR_HPRE_Pos                    (4U)
7182 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
7183 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
7184 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
7185 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
7186 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
7187 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
7188 
7189 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
7190 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
7191 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
7192 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
7193 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
7194 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
7195 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
7196 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
7197 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
7198 
7199 /*!< PPRE1 configuration */
7200 #define RCC_CFGR_PPRE1_Pos                   (8U)
7201 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
7202 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
7203 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
7204 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
7205 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
7206 
7207 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
7208 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
7209 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
7210 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
7211 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
7212 
7213 /*!< PPRE2 configuration */
7214 #define RCC_CFGR_PPRE2_Pos                   (11U)
7215 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
7216 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
7217 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
7218 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
7219 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
7220 
7221 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
7222 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
7223 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
7224 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
7225 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
7226 
7227 /*!< MCOSEL configuration */
7228 #define RCC_CFGR_MCOSEL_Pos                  (24U)
7229 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
7230 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
7231 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
7232 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
7233 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
7234 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
7235 
7236 #define RCC_CFGR_MCOPRE_Pos                  (28U)
7237 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
7238 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
7239 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
7240 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
7241 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
7242 
7243 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
7244 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
7245 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
7246 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
7247 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
7248 
7249 /* Legacy aliases */
7250 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
7251 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
7252 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
7253 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
7254 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
7255 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
7256 
7257 /********************  Bit definition for RCC_PLLCFGR register  ***************/
7258 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
7259 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
7260 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
7261 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
7262 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
7263 
7264 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
7265 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
7266 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
7267 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
7268 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
7269 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
7270 
7271 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
7272 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
7273 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
7274 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
7275 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
7276 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
7277 #define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
7278 
7279 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
7280 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
7281 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
7282 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
7283 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
7284 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
7285 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
7286 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
7287 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
7288 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
7289 
7290 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
7291 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
7292 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
7293 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
7294 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
7295 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
7296 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
7297 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
7298 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
7299 
7300 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
7301 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
7302 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
7303 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
7304 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
7305 
7306 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
7307 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
7308 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
7309 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
7310 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
7311 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
7312 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
7313 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
7314 
7315 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
7316 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
7317 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
7318 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
7319 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
7320 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
7321 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
7322 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
7323 
7324 /********************  Bit definition for RCC_CIER register  ******************/
7325 #define RCC_CIER_LSIRDYIE_Pos                (0U)
7326 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
7327 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
7328 #define RCC_CIER_LSERDYIE_Pos                (1U)
7329 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
7330 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
7331 #define RCC_CIER_HSIRDYIE_Pos                (3U)
7332 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
7333 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
7334 #define RCC_CIER_HSERDYIE_Pos                (4U)
7335 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
7336 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
7337 #define RCC_CIER_PLLRDYIE_Pos                (5U)
7338 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
7339 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
7340 #define RCC_CIER_LSECSSIE_Pos                (9U)
7341 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
7342 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
7343 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
7344 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
7345 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
7346 
7347 /********************  Bit definition for RCC_CIFR register  ******************/
7348 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
7349 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
7350 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
7351 #define RCC_CIFR_LSERDYF_Pos                 (1U)
7352 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
7353 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
7354 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
7355 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
7356 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
7357 #define RCC_CIFR_HSERDYF_Pos                 (4U)
7358 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
7359 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
7360 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
7361 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
7362 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
7363 #define RCC_CIFR_CSSF_Pos                    (8U)
7364 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
7365 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
7366 #define RCC_CIFR_LSECSSF_Pos                 (9U)
7367 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
7368 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
7369 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
7370 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
7371 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
7372 
7373 /********************  Bit definition for RCC_CICR register  ******************/
7374 #define RCC_CICR_LSIRDYC_Pos                 (0U)
7375 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
7376 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
7377 #define RCC_CICR_LSERDYC_Pos                 (1U)
7378 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
7379 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
7380 #define RCC_CICR_HSIRDYC_Pos                 (3U)
7381 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
7382 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
7383 #define RCC_CICR_HSERDYC_Pos                 (4U)
7384 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
7385 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
7386 #define RCC_CICR_PLLRDYC_Pos                 (5U)
7387 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
7388 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
7389 #define RCC_CICR_CSSC_Pos                    (8U)
7390 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
7391 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
7392 #define RCC_CICR_LSECSSC_Pos                 (9U)
7393 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
7394 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
7395 #define RCC_CICR_HSI48RDYC_Pos               (10U)
7396 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
7397 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
7398 
7399 /********************  Bit definition for RCC_AHB1RSTR register  **************/
7400 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
7401 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
7402 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
7403 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
7404 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
7405 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
7406 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
7407 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
7408 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
7409 #define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
7410 #define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
7411 #define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
7412 #define RCC_AHB1RSTR_FMACRST_Pos             (4U)
7413 #define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
7414 #define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
7415 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
7416 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
7417 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
7418 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
7419 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
7420 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
7421 
7422 /********************  Bit definition for RCC_AHB2RSTR register  **************/
7423 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
7424 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
7425 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
7426 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
7427 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
7428 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
7429 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
7430 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
7431 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
7432 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
7433 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
7434 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
7435 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
7436 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
7437 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
7438 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
7439 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
7440 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
7441 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
7442 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
7443 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
7444 #define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
7445 #define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
7446 #define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
7447 #define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
7448 #define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
7449 #define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
7450 #define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
7451 #define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
7452 #define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
7453 #define RCC_AHB2RSTR_RNGRST_Pos              (26U)
7454 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
7455 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
7456 
7457 /********************  Bit definition for RCC_AHB3RSTR register  **************/
7458 
7459 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
7460 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
7461 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
7462 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
7463 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
7464 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
7465 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
7466 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
7467 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
7468 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
7469 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
7470 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
7471 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
7472 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
7473 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
7474 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
7475 #define RCC_APB1RSTR1_CRSRST_Pos             (8U)
7476 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
7477 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
7478 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
7479 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
7480 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
7481 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
7482 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
7483 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
7484 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
7485 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
7486 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
7487 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
7488 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
7489 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
7490 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
7491 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
7492 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
7493 #define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
7494 #define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
7495 #define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
7496 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
7497 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
7498 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
7499 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
7500 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
7501 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
7502 
7503 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
7504 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
7505 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
7506 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
7507 
7508 /********************  Bit definition for RCC_APB2RSTR register  **************/
7509 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
7510 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
7511 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
7512 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
7513 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
7514 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
7515 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
7516 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
7517 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
7518 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
7519 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
7520 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
7521 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
7522 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
7523 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
7524 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
7525 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
7526 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
7527 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
7528 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
7529 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
7530 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
7531 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
7532 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
7533 
7534 /********************  Bit definition for RCC_AHB1ENR register  ***************/
7535 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
7536 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
7537 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
7538 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
7539 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
7540 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
7541 #define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
7542 #define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
7543 #define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
7544 #define RCC_AHB1ENR_CORDICEN_Pos             (3U)
7545 #define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
7546 #define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
7547 #define RCC_AHB1ENR_FMACEN_Pos               (4U)
7548 #define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
7549 #define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
7550 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
7551 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
7552 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
7553 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
7554 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
7555 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
7556 
7557 /********************  Bit definition for RCC_AHB2ENR register  ***************/
7558 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
7559 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
7560 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
7561 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
7562 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
7563 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
7564 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
7565 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
7566 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
7567 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
7568 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
7569 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
7570 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
7571 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
7572 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
7573 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
7574 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
7575 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
7576 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
7577 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
7578 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
7579 #define RCC_AHB2ENR_ADC12EN_Pos              (13U)
7580 #define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
7581 #define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
7582 #define RCC_AHB2ENR_DAC1EN_Pos               (16U)
7583 #define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
7584 #define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
7585 #define RCC_AHB2ENR_DAC3EN_Pos               (18U)
7586 #define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
7587 #define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
7588 #define RCC_AHB2ENR_RNGEN_Pos                (26U)
7589 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
7590 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
7591 
7592 /********************  Bit definition for RCC_AHB3ENR register  ***************/
7593 
7594 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
7595 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
7596 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
7597 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
7598 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
7599 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
7600 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
7601 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
7602 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
7603 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
7604 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
7605 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
7606 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
7607 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
7608 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
7609 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
7610 #define RCC_APB1ENR1_CRSEN_Pos               (8U)
7611 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
7612 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
7613 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
7614 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
7615 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
7616 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
7617 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
7618 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
7619 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
7620 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
7621 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
7622 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
7623 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
7624 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
7625 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
7626 #define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
7627 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
7628 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
7629 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
7630 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
7631 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
7632 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
7633 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
7634 #define RCC_APB1ENR1_FDCANEN_Pos             (25U)
7635 #define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
7636 #define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
7637 #define RCC_APB1ENR1_PWREN_Pos               (28U)
7638 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
7639 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
7640 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
7641 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
7642 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
7643 
7644 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
7645 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
7646 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
7647 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
7648 
7649 /********************  Bit definition for RCC_APB2ENR register  ***************/
7650 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
7651 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
7652 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
7653 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
7654 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
7655 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
7656 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
7657 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
7658 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
7659 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
7660 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
7661 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
7662 #define RCC_APB2ENR_USART1EN_Pos             (14U)
7663 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
7664 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
7665 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
7666 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
7667 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
7668 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
7669 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
7670 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
7671 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
7672 #define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
7673 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
7674 
7675 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
7676 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
7677 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
7678 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
7679 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
7680 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
7681 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
7682 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
7683 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
7684 #define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
7685 #define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
7686 #define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
7687 #define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
7688 #define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
7689 #define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
7690 #define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
7691 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
7692 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
7693 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
7694 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
7695 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
7696 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
7697 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
7698 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
7699 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
7700 
7701 /********************  Bit definition for RCC_AHB2SMENR register  *************/
7702 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
7703 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
7704 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
7705 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
7706 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
7707 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
7708 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
7709 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
7710 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
7711 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
7712 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
7713 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
7714 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
7715 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
7716 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
7717 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
7718 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
7719 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
7720 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
7721 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
7722 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
7723 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
7724 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
7725 #define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
7726 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (10U)
7727 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
7728 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
7729 #define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
7730 #define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
7731 #define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
7732 #define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
7733 #define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
7734 #define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
7735 #define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
7736 #define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
7737 #define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
7738 #define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
7739 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
7740 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
7741 
7742 /********************  Bit definition for RCC_AHB3SMENR register  *************/
7743 
7744 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
7745 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
7746 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
7747 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
7748 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
7749 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
7750 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
7751 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
7752 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
7753 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
7754 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
7755 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
7756 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
7757 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
7758 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
7759 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
7760 #define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
7761 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
7762 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
7763 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
7764 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
7765 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
7766 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
7767 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
7768 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
7769 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
7770 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
7771 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
7772 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
7773 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
7774 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
7775 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
7776 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
7777 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
7778 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
7779 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
7780 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
7781 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
7782 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
7783 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
7784 #define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
7785 #define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
7786 #define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
7787 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
7788 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
7789 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
7790 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
7791 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
7792 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
7793 
7794 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
7795 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
7796 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
7797 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
7798 
7799 /********************  Bit definition for RCC_APB2SMENR register  *************/
7800 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
7801 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
7802 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
7803 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
7804 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
7805 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
7806 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
7807 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
7808 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
7809 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
7810 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
7811 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
7812 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
7813 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
7814 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
7815 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
7816 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
7817 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
7818 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
7819 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
7820 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
7821 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
7822 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
7823 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
7824 
7825 /********************  Bit definition for RCC_CCIPR register  ******************/
7826 #define RCC_CCIPR_USART1SEL_Pos              (0U)
7827 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
7828 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
7829 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
7830 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
7831 
7832 #define RCC_CCIPR_USART2SEL_Pos              (2U)
7833 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
7834 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
7835 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
7836 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
7837 
7838 
7839 #define RCC_CCIPR_UART4SEL_Pos               (6U)
7840 #define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
7841 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
7842 #define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
7843 #define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
7844 
7845 
7846 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
7847 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
7848 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
7849 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
7850 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
7851 
7852 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
7853 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
7854 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
7855 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
7856 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
7857 
7858 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
7859 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
7860 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
7861 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
7862 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
7863 
7864 
7865 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
7866 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
7867 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
7868 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
7869 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
7870 
7871 
7872 #define RCC_CCIPR_I2S23SEL_Pos               (22U)
7873 #define RCC_CCIPR_I2S23SEL_Msk               (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
7874 #define RCC_CCIPR_I2S23SEL                   RCC_CCIPR_I2S23SEL_Msk
7875 #define RCC_CCIPR_I2S23SEL_0                 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
7876 #define RCC_CCIPR_I2S23SEL_1                 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
7877 
7878 #define RCC_CCIPR_FDCANSEL_Pos               (24U)
7879 #define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
7880 #define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
7881 #define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
7882 #define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
7883 
7884 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
7885 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
7886 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
7887 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
7888 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
7889 
7890 #define RCC_CCIPR_ADC12SEL_Pos               (28U)
7891 #define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
7892 #define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
7893 #define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
7894 #define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
7895 
7896 
7897 /********************  Bit definition for RCC_BDCR register  ******************/
7898 #define RCC_BDCR_LSEON_Pos                   (0U)
7899 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
7900 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
7901 #define RCC_BDCR_LSERDY_Pos                  (1U)
7902 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
7903 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
7904 #define RCC_BDCR_LSEBYP_Pos                  (2U)
7905 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
7906 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
7907 
7908 #define RCC_BDCR_LSEDRV_Pos                  (3U)
7909 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
7910 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
7911 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
7912 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
7913 
7914 #define RCC_BDCR_LSECSSON_Pos                (5U)
7915 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
7916 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
7917 #define RCC_BDCR_LSECSSD_Pos                 (6U)
7918 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
7919 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
7920 
7921 #define RCC_BDCR_RTCSEL_Pos                  (8U)
7922 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
7923 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
7924 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
7925 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
7926 
7927 #define RCC_BDCR_RTCEN_Pos                   (15U)
7928 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
7929 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
7930 #define RCC_BDCR_BDRST_Pos                   (16U)
7931 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
7932 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
7933 #define RCC_BDCR_LSCOEN_Pos                  (24U)
7934 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
7935 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
7936 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
7937 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
7938 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
7939 
7940 /********************  Bit definition for RCC_CSR register  *******************/
7941 #define RCC_CSR_LSION_Pos                    (0U)
7942 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
7943 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
7944 #define RCC_CSR_LSIRDY_Pos                   (1U)
7945 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
7946 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
7947 
7948 #define RCC_CSR_RMVF_Pos                     (23U)
7949 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
7950 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
7951 #define RCC_CSR_OBLRSTF_Pos                  (25U)
7952 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
7953 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
7954 #define RCC_CSR_PINRSTF_Pos                  (26U)
7955 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
7956 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
7957 #define RCC_CSR_BORRSTF_Pos                  (27U)
7958 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
7959 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
7960 #define RCC_CSR_SFTRSTF_Pos                  (28U)
7961 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
7962 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
7963 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
7964 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
7965 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
7966 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
7967 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
7968 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
7969 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
7970 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
7971 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
7972 
7973 /********************  Bit definition for RCC_CRRCR register  *****************/
7974 #define RCC_CRRCR_HSI48ON_Pos                (0U)
7975 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
7976 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
7977 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
7978 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
7979 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
7980 
7981 /*!< HSI48CAL configuration */
7982 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
7983 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
7984 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
7985 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
7986 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
7987 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
7988 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
7989 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
7990 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
7991 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
7992 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
7993 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
7994 
7995 /********************  Bit definition for RCC_CCIPR2 register  ******************/
7996 
7997 
7998 /******************************************************************************/
7999 /*                                                                            */
8000 /*                                    RNG                                     */
8001 /*                                                                            */
8002 /******************************************************************************/
8003 /********************  Bits definition for RNG_CR register  *******************/
8004 #define RNG_CR_RNGEN_Pos    (2U)
8005 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
8006 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
8007 #define RNG_CR_IE_Pos       (3U)
8008 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
8009 #define RNG_CR_IE           RNG_CR_IE_Msk
8010 #define RNG_CR_CED_Pos      (5U)
8011 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
8012 #define RNG_CR_CED          RNG_CR_IE_Msk
8013 
8014 /********************  Bits definition for RNG_SR register  *******************/
8015 #define RNG_SR_DRDY_Pos     (0U)
8016 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
8017 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
8018 #define RNG_SR_CECS_Pos     (1U)
8019 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
8020 #define RNG_SR_CECS         RNG_SR_CECS_Msk
8021 #define RNG_SR_SECS_Pos     (2U)
8022 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
8023 #define RNG_SR_SECS         RNG_SR_SECS_Msk
8024 #define RNG_SR_CEIS_Pos     (5U)
8025 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
8026 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
8027 #define RNG_SR_SEIS_Pos     (6U)
8028 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
8029 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
8030 
8031 /******************************************************************************/
8032 /*                                                                            */
8033 /*                           Real-Time Clock (RTC)                            */
8034 /*                                                                            */
8035 /******************************************************************************/
8036 
8037 /********************  Bits definition for RTC_TR register  *******************/
8038 #define RTC_TR_PM_Pos                (22U)
8039 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
8040 #define RTC_TR_PM                    RTC_TR_PM_Msk
8041 #define RTC_TR_HT_Pos                (20U)
8042 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
8043 #define RTC_TR_HT                    RTC_TR_HT_Msk
8044 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
8045 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
8046 #define RTC_TR_HU_Pos                (16U)
8047 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
8048 #define RTC_TR_HU                    RTC_TR_HU_Msk
8049 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
8050 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
8051 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
8052 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
8053 #define RTC_TR_MNT_Pos               (12U)
8054 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
8055 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
8056 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
8057 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
8058 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
8059 #define RTC_TR_MNU_Pos               (8U)
8060 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
8061 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
8062 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
8063 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
8064 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
8065 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
8066 #define RTC_TR_ST_Pos                (4U)
8067 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
8068 #define RTC_TR_ST                    RTC_TR_ST_Msk
8069 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
8070 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
8071 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
8072 #define RTC_TR_SU_Pos                (0U)
8073 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
8074 #define RTC_TR_SU                    RTC_TR_SU_Msk
8075 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
8076 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
8077 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
8078 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
8079 
8080 /********************  Bits definition for RTC_DR register  *******************/
8081 #define RTC_DR_YT_Pos                (20U)
8082 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
8083 #define RTC_DR_YT                    RTC_DR_YT_Msk
8084 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
8085 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
8086 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
8087 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
8088 #define RTC_DR_YU_Pos                (16U)
8089 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
8090 #define RTC_DR_YU                    RTC_DR_YU_Msk
8091 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
8092 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
8093 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
8094 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
8095 #define RTC_DR_WDU_Pos               (13U)
8096 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
8097 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
8098 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
8099 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
8100 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
8101 #define RTC_DR_MT_Pos                (12U)
8102 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
8103 #define RTC_DR_MT                    RTC_DR_MT_Msk
8104 #define RTC_DR_MU_Pos                (8U)
8105 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
8106 #define RTC_DR_MU                    RTC_DR_MU_Msk
8107 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
8108 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
8109 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
8110 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
8111 #define RTC_DR_DT_Pos                (4U)
8112 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
8113 #define RTC_DR_DT                    RTC_DR_DT_Msk
8114 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
8115 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
8116 #define RTC_DR_DU_Pos                (0U)
8117 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
8118 #define RTC_DR_DU                    RTC_DR_DU_Msk
8119 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
8120 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
8121 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
8122 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
8123 
8124 /********************  Bits definition for RTC_SSR register  ******************/
8125 #define RTC_SSR_SS_Pos               (0U)
8126 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
8127 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
8128 
8129 /********************  Bits definition for RTC_ICSR register  ******************/
8130 #define RTC_ICSR_RECALPF_Pos         (16U)
8131 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
8132 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
8133 #define RTC_ICSR_INIT_Pos            (7U)
8134 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
8135 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
8136 #define RTC_ICSR_INITF_Pos           (6U)
8137 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
8138 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
8139 #define RTC_ICSR_RSF_Pos             (5U)
8140 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
8141 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
8142 #define RTC_ICSR_INITS_Pos           (4U)
8143 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
8144 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
8145 #define RTC_ICSR_SHPF_Pos            (3U)
8146 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
8147 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
8148 #define RTC_ICSR_WUTWF_Pos           (2U)
8149 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
8150 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
8151 #define RTC_ICSR_ALRBWF_Pos          (1U)
8152 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
8153 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
8154 #define RTC_ICSR_ALRAWF_Pos          (0U)
8155 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
8156 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
8157 
8158 /********************  Bits definition for RTC_PRER register  *****************/
8159 #define RTC_PRER_PREDIV_A_Pos        (16U)
8160 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
8161 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
8162 #define RTC_PRER_PREDIV_S_Pos        (0U)
8163 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
8164 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
8165 
8166 /********************  Bits definition for RTC_WUTR register  *****************/
8167 #define RTC_WUTR_WUT_Pos             (0U)
8168 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
8169 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
8170 
8171 /********************  Bits definition for RTC_CR register  *******************/
8172 #define RTC_CR_OUT2EN_Pos            (31U)
8173 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
8174 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
8175 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
8176 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
8177 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
8178 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
8179 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
8180 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
8181 #define RTC_CR_TAMPOE_Pos            (26U)
8182 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
8183 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
8184 #define RTC_CR_TAMPTS_Pos            (25U)
8185 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
8186 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
8187 #define RTC_CR_ITSE_Pos              (24U)
8188 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
8189 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
8190 #define RTC_CR_COE_Pos               (23U)
8191 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
8192 #define RTC_CR_COE                   RTC_CR_COE_Msk
8193 #define RTC_CR_OSEL_Pos              (21U)
8194 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
8195 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
8196 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
8197 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
8198 #define RTC_CR_POL_Pos               (20U)
8199 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
8200 #define RTC_CR_POL                   RTC_CR_POL_Msk
8201 #define RTC_CR_COSEL_Pos             (19U)
8202 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
8203 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
8204 #define RTC_CR_BKP_Pos               (18U)
8205 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
8206 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
8207 #define RTC_CR_SUB1H_Pos             (17U)
8208 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
8209 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
8210 #define RTC_CR_ADD1H_Pos             (16U)
8211 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
8212 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
8213 #define RTC_CR_TSIE_Pos              (15U)
8214 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
8215 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
8216 #define RTC_CR_WUTIE_Pos             (14U)
8217 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
8218 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
8219 #define RTC_CR_ALRBIE_Pos            (13U)
8220 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
8221 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
8222 #define RTC_CR_ALRAIE_Pos            (12U)
8223 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
8224 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
8225 #define RTC_CR_TSE_Pos               (11U)
8226 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
8227 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
8228 #define RTC_CR_WUTE_Pos              (10U)
8229 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
8230 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
8231 #define RTC_CR_ALRBE_Pos             (9U)
8232 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
8233 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
8234 #define RTC_CR_ALRAE_Pos             (8U)
8235 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
8236 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
8237 #define RTC_CR_FMT_Pos               (6U)
8238 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
8239 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
8240 #define RTC_CR_BYPSHAD_Pos           (5U)
8241 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
8242 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
8243 #define RTC_CR_REFCKON_Pos           (4U)
8244 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
8245 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
8246 #define RTC_CR_TSEDGE_Pos            (3U)
8247 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
8248 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
8249 #define RTC_CR_WUCKSEL_Pos           (0U)
8250 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
8251 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
8252 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
8253 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
8254 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
8255 
8256 /********************  Bits definition for RTC_WPR register  ******************/
8257 #define RTC_WPR_KEY_Pos              (0U)
8258 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
8259 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
8260 
8261 /********************  Bits definition for RTC_CALR register  *****************/
8262 #define RTC_CALR_CALP_Pos            (15U)
8263 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
8264 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
8265 #define RTC_CALR_CALW8_Pos           (14U)
8266 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
8267 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
8268 #define RTC_CALR_CALW16_Pos          (13U)
8269 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
8270 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
8271 #define RTC_CALR_CALM_Pos            (0U)
8272 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
8273 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
8274 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
8275 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
8276 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
8277 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
8278 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
8279 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
8280 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
8281 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
8282 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
8283 
8284 /********************  Bits definition for RTC_SHIFTR register  ***************/
8285 #define RTC_SHIFTR_SUBFS_Pos         (0U)
8286 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
8287 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
8288 #define RTC_SHIFTR_ADD1S_Pos         (31U)
8289 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
8290 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
8291 
8292 /********************  Bits definition for RTC_TSTR register  *****************/
8293 #define RTC_TSTR_PM_Pos              (22U)
8294 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
8295 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
8296 #define RTC_TSTR_HT_Pos              (20U)
8297 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
8298 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
8299 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
8300 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
8301 #define RTC_TSTR_HU_Pos              (16U)
8302 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
8303 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
8304 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
8305 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
8306 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
8307 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
8308 #define RTC_TSTR_MNT_Pos             (12U)
8309 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
8310 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
8311 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
8312 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
8313 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
8314 #define RTC_TSTR_MNU_Pos             (8U)
8315 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
8316 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
8317 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
8318 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
8319 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
8320 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
8321 #define RTC_TSTR_ST_Pos              (4U)
8322 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
8323 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
8324 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
8325 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
8326 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
8327 #define RTC_TSTR_SU_Pos              (0U)
8328 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
8329 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
8330 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
8331 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
8332 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
8333 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
8334 
8335 /********************  Bits definition for RTC_TSDR register  *****************/
8336 #define RTC_TSDR_WDU_Pos             (13U)
8337 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
8338 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
8339 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
8340 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
8341 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
8342 #define RTC_TSDR_MT_Pos              (12U)
8343 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
8344 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
8345 #define RTC_TSDR_MU_Pos              (8U)
8346 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
8347 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
8348 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
8349 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
8350 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
8351 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
8352 #define RTC_TSDR_DT_Pos              (4U)
8353 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
8354 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
8355 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
8356 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
8357 #define RTC_TSDR_DU_Pos              (0U)
8358 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
8359 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
8360 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
8361 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
8362 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
8363 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
8364 
8365 /********************  Bits definition for RTC_TSSSR register  ****************/
8366 #define RTC_TSSSR_SS_Pos             (0U)
8367 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
8368 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
8369 
8370 /********************  Bits definition for RTC_ALRMAR register  ***************/
8371 #define RTC_ALRMAR_MSK4_Pos          (31U)
8372 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
8373 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
8374 #define RTC_ALRMAR_WDSEL_Pos         (30U)
8375 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
8376 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
8377 #define RTC_ALRMAR_DT_Pos            (28U)
8378 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
8379 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
8380 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
8381 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
8382 #define RTC_ALRMAR_DU_Pos            (24U)
8383 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
8384 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
8385 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
8386 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
8387 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
8388 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
8389 #define RTC_ALRMAR_MSK3_Pos          (23U)
8390 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
8391 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
8392 #define RTC_ALRMAR_PM_Pos            (22U)
8393 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
8394 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
8395 #define RTC_ALRMAR_HT_Pos            (20U)
8396 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
8397 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
8398 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
8399 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
8400 #define RTC_ALRMAR_HU_Pos            (16U)
8401 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
8402 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
8403 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
8404 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
8405 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
8406 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
8407 #define RTC_ALRMAR_MSK2_Pos          (15U)
8408 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
8409 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
8410 #define RTC_ALRMAR_MNT_Pos           (12U)
8411 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
8412 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
8413 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
8414 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
8415 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
8416 #define RTC_ALRMAR_MNU_Pos           (8U)
8417 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
8418 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
8419 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
8420 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
8421 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
8422 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
8423 #define RTC_ALRMAR_MSK1_Pos          (7U)
8424 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
8425 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
8426 #define RTC_ALRMAR_ST_Pos            (4U)
8427 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
8428 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
8429 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
8430 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
8431 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
8432 #define RTC_ALRMAR_SU_Pos            (0U)
8433 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
8434 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
8435 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
8436 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
8437 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
8438 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
8439 
8440 /********************  Bits definition for RTC_ALRMASSR register  *************/
8441 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
8442 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
8443 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
8444 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
8445 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
8446 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
8447 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
8448 #define RTC_ALRMASSR_SS_Pos          (0U)
8449 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
8450 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
8451 
8452 /********************  Bits definition for RTC_ALRMBR register  ***************/
8453 #define RTC_ALRMBR_MSK4_Pos          (31U)
8454 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
8455 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
8456 #define RTC_ALRMBR_WDSEL_Pos         (30U)
8457 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
8458 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
8459 #define RTC_ALRMBR_DT_Pos            (28U)
8460 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
8461 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
8462 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
8463 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
8464 #define RTC_ALRMBR_DU_Pos            (24U)
8465 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
8466 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
8467 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
8468 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
8469 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
8470 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
8471 #define RTC_ALRMBR_MSK3_Pos          (23U)
8472 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
8473 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
8474 #define RTC_ALRMBR_PM_Pos            (22U)
8475 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
8476 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
8477 #define RTC_ALRMBR_HT_Pos            (20U)
8478 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
8479 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
8480 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
8481 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
8482 #define RTC_ALRMBR_HU_Pos            (16U)
8483 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
8484 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
8485 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
8486 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
8487 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
8488 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
8489 #define RTC_ALRMBR_MSK2_Pos          (15U)
8490 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
8491 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
8492 #define RTC_ALRMBR_MNT_Pos           (12U)
8493 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
8494 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
8495 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
8496 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
8497 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
8498 #define RTC_ALRMBR_MNU_Pos           (8U)
8499 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
8500 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
8501 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
8502 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
8503 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
8504 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
8505 #define RTC_ALRMBR_MSK1_Pos          (7U)
8506 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
8507 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
8508 #define RTC_ALRMBR_ST_Pos            (4U)
8509 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
8510 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
8511 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
8512 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
8513 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
8514 #define RTC_ALRMBR_SU_Pos            (0U)
8515 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
8516 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
8517 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
8518 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
8519 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
8520 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
8521 
8522 /********************  Bits definition for RTC_ALRMASSR register  *************/
8523 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
8524 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
8525 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
8526 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
8527 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
8528 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
8529 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
8530 #define RTC_ALRMBSSR_SS_Pos          (0U)
8531 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
8532 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
8533 
8534 /********************  Bits definition for RTC_SR register  *******************/
8535 #define RTC_SR_ITSF_Pos              (5U)
8536 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
8537 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
8538 #define RTC_SR_TSOVF_Pos             (4U)
8539 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
8540 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
8541 #define RTC_SR_TSF_Pos               (3U)
8542 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
8543 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
8544 #define RTC_SR_WUTF_Pos              (2U)
8545 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
8546 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
8547 #define RTC_SR_ALRBF_Pos             (1U)
8548 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
8549 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
8550 #define RTC_SR_ALRAF_Pos             (0U)
8551 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
8552 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
8553 
8554 /********************  Bits definition for RTC_MISR register  *****************/
8555 #define RTC_MISR_ITSMF_Pos           (5U)
8556 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
8557 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
8558 #define RTC_MISR_TSOVMF_Pos          (4U)
8559 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
8560 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
8561 #define RTC_MISR_TSMF_Pos            (3U)
8562 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
8563 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
8564 #define RTC_MISR_WUTMF_Pos           (2U)
8565 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
8566 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
8567 #define RTC_MISR_ALRBMF_Pos          (1U)
8568 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
8569 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
8570 #define RTC_MISR_ALRAMF_Pos          (0U)
8571 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
8572 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
8573 
8574 /********************  Bits definition for RTC_SCR register  ******************/
8575 #define RTC_SCR_CITSF_Pos            (5U)
8576 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
8577 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
8578 #define RTC_SCR_CTSOVF_Pos           (4U)
8579 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
8580 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
8581 #define RTC_SCR_CTSF_Pos             (3U)
8582 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
8583 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
8584 #define RTC_SCR_CWUTF_Pos            (2U)
8585 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
8586 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
8587 #define RTC_SCR_CALRBF_Pos           (1U)
8588 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
8589 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
8590 #define RTC_SCR_CALRAF_Pos           (0U)
8591 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
8592 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
8593 
8594 /******************************************************************************/
8595 /*                                                                            */
8596 /*                     Tamper and backup register (TAMP)                      */
8597 /*                                                                            */
8598 /******************************************************************************/
8599 /********************  Bits definition for TAMP_CR1 register  *****************/
8600 #define TAMP_CR1_TAMP1E_Pos          (0U)
8601 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
8602 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
8603 #define TAMP_CR1_TAMP2E_Pos          (1U)
8604 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
8605 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
8606 #define TAMP_CR1_TAMP3E_Pos          (2U)
8607 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
8608 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
8609 #define TAMP_CR1_ITAMP3E_Pos         (18U)
8610 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
8611 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
8612 #define TAMP_CR1_ITAMP4E_Pos         (19U)
8613 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
8614 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
8615 #define TAMP_CR1_ITAMP5E_Pos         (20U)
8616 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
8617 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
8618 #define TAMP_CR1_ITAMP6E_Pos         (21U)
8619 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
8620 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
8621 
8622 /********************  Bits definition for TAMP_CR2 register  *****************/
8623 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
8624 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
8625 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
8626 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
8627 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
8628 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
8629 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
8630 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
8631 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
8632 #define TAMP_CR2_TAMP1MSK_Pos         (16U)
8633 #define TAMP_CR2_TAMP1MSK_Msk         (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
8634 #define TAMP_CR2_TAMP1MSK             TAMP_CR2_TAMP1MSK_Msk
8635 #define TAMP_CR2_TAMP2MSK_Pos         (17U)
8636 #define TAMP_CR2_TAMP2MSK_Msk         (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
8637 #define TAMP_CR2_TAMP2MSK             TAMP_CR2_TAMP2MSK_Msk
8638 #define TAMP_CR2_TAMP3MSK_Pos         (18U)
8639 #define TAMP_CR2_TAMP3MSK_Msk         (0x1UL << TAMP_CR2_TAMP3MSK_Pos)           /*!< 0x00040000 */
8640 #define TAMP_CR2_TAMP3MSK             TAMP_CR2_TAMP3MSK_Msk
8641 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
8642 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
8643 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
8644 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
8645 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
8646 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
8647 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
8648 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
8649 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
8650 
8651 /* Legacy aliases */
8652 #define TAMP_CR2_TAMP1MF_Pos            TAMP_CR2_TAMP1MSK_Pos
8653 #define TAMP_CR2_TAMP1MF_Msk            TAMP_CR2_TAMP1MSK_Msk
8654 #define TAMP_CR2_TAMP1MF                TAMP_CR2_TAMP1MSK
8655 #define TAMP_CR2_TAMP2MF_Pos            TAMP_CR2_TAMP2MSK_Pos
8656 #define TAMP_CR2_TAMP2MF_Msk            TAMP_CR2_TAMP2MSK_Msk
8657 #define TAMP_CR2_TAMP2MF                TAMP_CR2_TAMP2MSK
8658 #define TAMP_CR2_TAMP3MF_Pos            TAMP_CR2_TAMP3MSK_Pos
8659 #define TAMP_CR2_TAMP3MF_Msk            TAMP_CR2_TAMP3MSK_Msk
8660 #define TAMP_CR2_TAMP3MF                TAMP_CR2_TAMP3MSK
8661 
8662 /********************  Bits definition for TAMP_FLTCR register  ***************/
8663 #define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
8664 #define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
8665 #define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
8666 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
8667 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
8668 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
8669 #define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
8670 #define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
8671 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
8672 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
8673 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
8674 #define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
8675 #define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
8676 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
8677 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
8678 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
8679 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
8680 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
8681 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
8682 
8683 /********************  Bits definition for TAMP_IER register  *****************/
8684 #define TAMP_IER_TAMP1IE_Pos         (0U)
8685 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
8686 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
8687 #define TAMP_IER_TAMP2IE_Pos         (1U)
8688 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
8689 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
8690 #define TAMP_IER_TAMP3IE_Pos         (2U)
8691 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
8692 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
8693 #define TAMP_IER_ITAMP3IE_Pos        (18U)
8694 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
8695 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
8696 #define TAMP_IER_ITAMP4IE_Pos        (19U)
8697 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
8698 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
8699 #define TAMP_IER_ITAMP5IE_Pos        (20U)
8700 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
8701 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
8702 #define TAMP_IER_ITAMP6IE_Pos        (21U)
8703 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
8704 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
8705 
8706 /********************  Bits definition for TAMP_SR register  ******************/
8707 #define TAMP_SR_TAMP1F_Pos           (0U)
8708 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
8709 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
8710 #define TAMP_SR_TAMP2F_Pos           (1U)
8711 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
8712 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
8713 #define TAMP_SR_TAMP3F_Pos           (2U)
8714 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
8715 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
8716 #define TAMP_SR_ITAMP3F_Pos          (18U)
8717 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
8718 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
8719 #define TAMP_SR_ITAMP4F_Pos          (19U)
8720 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
8721 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
8722 #define TAMP_SR_ITAMP5F_Pos          (20U)
8723 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
8724 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
8725 #define TAMP_SR_ITAMP6F_Pos          (21U)
8726 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
8727 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
8728 
8729 /********************  Bits definition for TAMP_MISR register  ****************/
8730 #define TAMP_MISR_TAMP1MF_Pos        (0U)
8731 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
8732 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
8733 #define TAMP_MISR_TAMP2MF_Pos        (1U)
8734 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
8735 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
8736 #define TAMP_MISR_TAMP3MF_Pos        (2U)
8737 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
8738 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
8739 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
8740 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
8741 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
8742 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
8743 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
8744 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
8745 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
8746 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
8747 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
8748 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
8749 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
8750 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
8751 
8752 /********************  Bits definition for TAMP_SCR register  *****************/
8753 #define TAMP_SCR_CTAMP1F_Pos         (0U)
8754 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
8755 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
8756 #define TAMP_SCR_CTAMP2F_Pos         (1U)
8757 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
8758 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
8759 #define TAMP_SCR_CTAMP3F_Pos         (2U)
8760 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
8761 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
8762 #define TAMP_SCR_CITAMP3F_Pos        (18U)
8763 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
8764 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
8765 #define TAMP_SCR_CITAMP4F_Pos        (19U)
8766 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
8767 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
8768 #define TAMP_SCR_CITAMP5F_Pos        (20U)
8769 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
8770 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
8771 #define TAMP_SCR_CITAMP6F_Pos        (21U)
8772 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
8773 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
8774 
8775 /********************  Bits definition for TAMP_BKP0R register  ***************/
8776 #define TAMP_BKP0R_Pos               (0U)
8777 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
8778 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
8779 
8780 /********************  Bits definition for TAMP_BKP1R register  ***************/
8781 #define TAMP_BKP1R_Pos               (0U)
8782 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
8783 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
8784 
8785 /********************  Bits definition for TAMP_BKP2R register  ***************/
8786 #define TAMP_BKP2R_Pos               (0U)
8787 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
8788 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
8789 
8790 /********************  Bits definition for TAMP_BKP3R register  ***************/
8791 #define TAMP_BKP3R_Pos               (0U)
8792 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
8793 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
8794 
8795 /********************  Bits definition for TAMP_BKP4R register  ***************/
8796 #define TAMP_BKP4R_Pos               (0U)
8797 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
8798 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
8799 
8800 /********************  Bits definition for TAMP_BKP5R register  ***************/
8801 #define TAMP_BKP5R_Pos               (0U)
8802 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
8803 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
8804 
8805 /********************  Bits definition for TAMP_BKP6R register  ***************/
8806 #define TAMP_BKP6R_Pos               (0U)
8807 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
8808 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
8809 
8810 /********************  Bits definition for TAMP_BKP7R register  ***************/
8811 #define TAMP_BKP7R_Pos               (0U)
8812 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
8813 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
8814 
8815 /********************  Bits definition for TAMP_BKP8R register  ***************/
8816 #define TAMP_BKP8R_Pos               (0U)
8817 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
8818 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
8819 
8820 /********************  Bits definition for TAMP_BKP9R register  ***************/
8821 #define TAMP_BKP9R_Pos               (0U)
8822 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
8823 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
8824 
8825 /********************  Bits definition for TAMP_BKP10R register  ***************/
8826 #define TAMP_BKP10R_Pos               (0U)
8827 #define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
8828 #define TAMP_BKP10R                   TAMP_BKP10R_Msk
8829 
8830 /********************  Bits definition for TAMP_BKP11R register  ***************/
8831 #define TAMP_BKP11R_Pos               (0U)
8832 #define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
8833 #define TAMP_BKP11R                   TAMP_BKP11R_Msk
8834 
8835 /********************  Bits definition for TAMP_BKP12R register  ***************/
8836 #define TAMP_BKP12R_Pos               (0U)
8837 #define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
8838 #define TAMP_BKP12R                   TAMP_BKP12R_Msk
8839 
8840 /********************  Bits definition for TAMP_BKP13R register  ***************/
8841 #define TAMP_BKP13R_Pos               (0U)
8842 #define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
8843 #define TAMP_BKP13R                   TAMP_BKP13R_Msk
8844 
8845 /********************  Bits definition for TAMP_BKP14R register  ***************/
8846 #define TAMP_BKP14R_Pos               (0U)
8847 #define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
8848 #define TAMP_BKP14R                   TAMP_BKP14R_Msk
8849 
8850 /********************  Bits definition for TAMP_BKP15R register  ***************/
8851 #define TAMP_BKP15R_Pos               (0U)
8852 #define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
8853 #define TAMP_BKP15R                   TAMP_BKP15R_Msk
8854 
8855 
8856 
8857 
8858 /******************************************************************************/
8859 /*                                                                            */
8860 /*                        Serial Peripheral Interface (SPI)                   */
8861 /*                                                                            */
8862 /******************************************************************************/
8863 /*
8864  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
8865  */
8866 #define SPI_I2S_SUPPORT                       /*!< I2S support */
8867 
8868 /*******************  Bit definition for SPI_CR1 register  ********************/
8869 #define SPI_CR1_CPHA_Pos            (0U)
8870 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
8871 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
8872 #define SPI_CR1_CPOL_Pos            (1U)
8873 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
8874 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
8875 #define SPI_CR1_MSTR_Pos            (2U)
8876 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
8877 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
8878 
8879 #define SPI_CR1_BR_Pos              (3U)
8880 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
8881 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
8882 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
8883 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
8884 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
8885 
8886 #define SPI_CR1_SPE_Pos             (6U)
8887 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
8888 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
8889 #define SPI_CR1_LSBFIRST_Pos        (7U)
8890 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
8891 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
8892 #define SPI_CR1_SSI_Pos             (8U)
8893 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
8894 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
8895 #define SPI_CR1_SSM_Pos             (9U)
8896 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
8897 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
8898 #define SPI_CR1_RXONLY_Pos          (10U)
8899 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
8900 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
8901 #define SPI_CR1_CRCL_Pos            (11U)
8902 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
8903 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
8904 #define SPI_CR1_CRCNEXT_Pos         (12U)
8905 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
8906 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
8907 #define SPI_CR1_CRCEN_Pos           (13U)
8908 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
8909 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
8910 #define SPI_CR1_BIDIOE_Pos          (14U)
8911 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
8912 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
8913 #define SPI_CR1_BIDIMODE_Pos        (15U)
8914 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
8915 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
8916 
8917 /*******************  Bit definition for SPI_CR2 register  ********************/
8918 #define SPI_CR2_RXDMAEN_Pos         (0U)
8919 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
8920 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
8921 #define SPI_CR2_TXDMAEN_Pos         (1U)
8922 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
8923 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
8924 #define SPI_CR2_SSOE_Pos            (2U)
8925 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
8926 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
8927 #define SPI_CR2_NSSP_Pos            (3U)
8928 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
8929 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
8930 #define SPI_CR2_FRF_Pos             (4U)
8931 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
8932 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
8933 #define SPI_CR2_ERRIE_Pos           (5U)
8934 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
8935 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
8936 #define SPI_CR2_RXNEIE_Pos          (6U)
8937 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
8938 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
8939 #define SPI_CR2_TXEIE_Pos           (7U)
8940 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
8941 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
8942 #define SPI_CR2_DS_Pos              (8U)
8943 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
8944 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
8945 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
8946 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
8947 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
8948 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
8949 #define SPI_CR2_FRXTH_Pos           (12U)
8950 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
8951 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
8952 #define SPI_CR2_LDMARX_Pos          (13U)
8953 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
8954 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
8955 #define SPI_CR2_LDMATX_Pos          (14U)
8956 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
8957 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
8958 
8959 /********************  Bit definition for SPI_SR register  ********************/
8960 #define SPI_SR_RXNE_Pos             (0U)
8961 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
8962 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
8963 #define SPI_SR_TXE_Pos              (1U)
8964 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
8965 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
8966 #define SPI_SR_CHSIDE_Pos           (2U)
8967 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
8968 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
8969 #define SPI_SR_UDR_Pos              (3U)
8970 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
8971 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
8972 #define SPI_SR_CRCERR_Pos           (4U)
8973 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
8974 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
8975 #define SPI_SR_MODF_Pos             (5U)
8976 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
8977 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
8978 #define SPI_SR_OVR_Pos              (6U)
8979 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
8980 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
8981 #define SPI_SR_BSY_Pos              (7U)
8982 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
8983 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
8984 #define SPI_SR_FRE_Pos              (8U)
8985 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
8986 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
8987 #define SPI_SR_FRLVL_Pos            (9U)
8988 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
8989 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
8990 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
8991 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
8992 #define SPI_SR_FTLVL_Pos            (11U)
8993 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
8994 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
8995 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
8996 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
8997 
8998 /********************  Bit definition for SPI_DR register  ********************/
8999 #define SPI_DR_DR_Pos               (0U)
9000 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
9001 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
9002 
9003 /*******************  Bit definition for SPI_CRCPR register  ******************/
9004 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
9005 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
9006 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
9007 
9008 /******************  Bit definition for SPI_RXCRCR register  ******************/
9009 #define SPI_RXCRCR_RXCRC_Pos        (0U)
9010 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
9011 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
9012 
9013 /******************  Bit definition for SPI_TXCRCR register  ******************/
9014 #define SPI_TXCRCR_TXCRC_Pos        (0U)
9015 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
9016 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
9017 
9018 /******************  Bit definition for SPI_I2SCFGR register  *****************/
9019 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
9020 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
9021 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
9022 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
9023 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
9024 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
9025 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
9026 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
9027 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
9028 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
9029 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
9030 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
9031 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
9032 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
9033 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
9034 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
9035 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
9036 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
9037 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
9038 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
9039 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
9040 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
9041 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
9042 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
9043 #define SPI_I2SCFGR_I2SE_Pos        (10U)
9044 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
9045 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
9046 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
9047 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
9048 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
9049 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
9050 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
9051 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
9052 
9053 /******************  Bit definition for SPI_I2SPR register  *******************/
9054 #define SPI_I2SPR_I2SDIV_Pos        (0U)
9055 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
9056 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
9057 #define SPI_I2SPR_ODD_Pos           (8U)
9058 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
9059 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
9060 #define SPI_I2SPR_MCKOE_Pos         (9U)
9061 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
9062 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
9063 
9064 /******************************************************************************/
9065 /*                                                                            */
9066 /*                                 SYSCFG                                     */
9067 /*                                                                            */
9068 /******************************************************************************/
9069 /******************  Bit definition for SYSCFG_MEMRMP register ***************/
9070 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
9071 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
9072 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
9073 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
9074 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
9075 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
9076 
9077 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
9078 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
9079 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
9080 
9081 /******************  Bit definition for SYSCFG_CFGR1 register ******************/
9082 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
9083 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
9084 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
9085 #define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
9086 #define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
9087 #define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
9088 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
9089 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
9090 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
9091 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
9092 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
9093 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
9094 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
9095 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
9096 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
9097 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
9098 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
9099 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
9100 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
9101 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
9102 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
9103 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
9104 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
9105 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
9106 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
9107 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
9108 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
9109 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
9110 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
9111 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
9112 
9113 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
9114 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
9115 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
9116 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
9117 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
9118 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
9119 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
9120 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
9121 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
9122 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
9123 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
9124 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
9125 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
9126 
9127 /**
9128   * @brief   EXTI0 configuration
9129   */
9130 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
9131 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
9132 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
9133 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
9134 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
9135 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
9136 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
9137 
9138 /**
9139   * @brief   EXTI1 configuration
9140   */
9141 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
9142 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
9143 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
9144 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
9145 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
9146 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
9147 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
9148 
9149 /**
9150   * @brief   EXTI2 configuration
9151   */
9152 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
9153 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
9154 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
9155 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
9156 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
9157 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
9158 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
9159 
9160 /**
9161   * @brief   EXTI3 configuration
9162   */
9163 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
9164 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
9165 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
9166 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
9167 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
9168 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
9169 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
9170 
9171 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
9172 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
9173 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
9174 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
9175 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
9176 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
9177 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
9178 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
9179 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
9180 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
9181 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
9182 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
9183 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
9184 
9185 /**
9186   * @brief   EXTI4 configuration
9187   */
9188 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
9189 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
9190 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
9191 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
9192 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
9193 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
9194 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
9195 
9196 /**
9197   * @brief   EXTI5 configuration
9198   */
9199 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
9200 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
9201 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
9202 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
9203 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
9204 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
9205 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
9206 
9207 /**
9208   * @brief   EXTI6 configuration
9209   */
9210 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
9211 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
9212 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
9213 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
9214 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
9215 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
9216 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
9217 
9218 /**
9219   * @brief   EXTI7 configuration
9220   */
9221 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
9222 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
9223 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
9224 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
9225 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
9226 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
9227 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
9228 
9229 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
9230 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
9231 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
9232 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
9233 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
9234 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
9235 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
9236 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
9237 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
9238 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
9239 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
9240 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
9241 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
9242 
9243 /**
9244   * @brief   EXTI8 configuration
9245   */
9246 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
9247 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
9248 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
9249 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
9250 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
9251 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
9252 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
9253 
9254 /**
9255   * @brief   EXTI9 configuration
9256   */
9257 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
9258 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
9259 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
9260 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
9261 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
9262 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
9263 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
9264 
9265 /**
9266   * @brief   EXTI10 configuration
9267   */
9268 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
9269 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
9270 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
9271 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
9272 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
9273 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
9274 
9275 /**
9276   * @brief   EXTI11 configuration
9277   */
9278 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
9279 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
9280 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
9281 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
9282 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
9283 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
9284 
9285 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
9286 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
9287 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
9288 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
9289 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
9290 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
9291 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
9292 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
9293 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
9294 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
9295 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
9296 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
9297 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
9298 
9299 /**
9300   * @brief   EXTI12 configuration
9301   */
9302 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
9303 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
9304 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
9305 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
9306 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
9307 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
9308 
9309 /**
9310   * @brief   EXTI13 configuration
9311   */
9312 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
9313 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
9314 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
9315 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
9316 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
9317 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
9318 
9319 /**
9320   * @brief   EXTI14 configuration
9321   */
9322 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
9323 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
9324 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
9325 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
9326 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
9327 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
9328 
9329 /**
9330   * @brief   EXTI15 configuration
9331   */
9332 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
9333 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
9334 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
9335 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
9336 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
9337 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
9338 
9339 /******************  Bit definition for SYSCFG_SCSR register  ****************/
9340 #define SYSCFG_SCSR_CCMER_Pos         (0U)
9341 #define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
9342 #define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
9343 #define SYSCFG_SCSR_CCMBSY_Pos        (1U)
9344 #define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
9345 #define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
9346 
9347 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
9348 #define SYSCFG_CFGR2_CLL_Pos            (0U)
9349 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
9350 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
9351 #define SYSCFG_CFGR2_SPL_Pos            (1U)
9352 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
9353 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
9354 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
9355 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
9356 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
9357 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
9358 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
9359 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
9360 #define SYSCFG_CFGR2_SPF_Pos            (8U)
9361 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
9362 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
9363 
9364 /******************  Bit definition for SYSCFG_SWPR register  ****************/
9365 #define SYSCFG_SWPR_PAGE0_Pos          (0U)
9366 #define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
9367 #define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
9368 #define SYSCFG_SWPR_PAGE1_Pos          (1U)
9369 #define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
9370 #define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
9371 #define SYSCFG_SWPR_PAGE2_Pos          (2U)
9372 #define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
9373 #define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
9374 #define SYSCFG_SWPR_PAGE3_Pos          (3U)
9375 #define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
9376 #define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
9377 #define SYSCFG_SWPR_PAGE4_Pos          (4U)
9378 #define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
9379 #define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
9380 #define SYSCFG_SWPR_PAGE5_Pos          (5U)
9381 #define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
9382 #define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
9383 #define SYSCFG_SWPR_PAGE6_Pos          (6U)
9384 #define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
9385 #define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
9386 #define SYSCFG_SWPR_PAGE7_Pos          (7U)
9387 #define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
9388 #define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
9389 #define SYSCFG_SWPR_PAGE8_Pos          (8U)
9390 #define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
9391 #define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
9392 #define SYSCFG_SWPR_PAGE9_Pos          (9U)
9393 #define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
9394 #define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
9395 
9396 /******************  Bit definition for SYSCFG_SKR register  ****************/
9397 #define SYSCFG_SKR_KEY_Pos              (0U)
9398 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
9399 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
9400 
9401 /******************************************************************************/
9402 /*                                                                            */
9403 /*                                    TIM                                     */
9404 /*                                                                            */
9405 /******************************************************************************/
9406 /*******************  Bit definition for TIM_CR1 register  ********************/
9407 #define TIM_CR1_CEN_Pos           (0U)
9408 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
9409 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
9410 #define TIM_CR1_UDIS_Pos          (1U)
9411 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
9412 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
9413 #define TIM_CR1_URS_Pos           (2U)
9414 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
9415 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
9416 #define TIM_CR1_OPM_Pos           (3U)
9417 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
9418 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
9419 #define TIM_CR1_DIR_Pos           (4U)
9420 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
9421 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
9422 
9423 #define TIM_CR1_CMS_Pos           (5U)
9424 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
9425 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
9426 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
9427 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
9428 
9429 #define TIM_CR1_ARPE_Pos          (7U)
9430 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
9431 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
9432 
9433 #define TIM_CR1_CKD_Pos           (8U)
9434 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
9435 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
9436 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
9437 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
9438 
9439 #define TIM_CR1_UIFREMAP_Pos      (11U)
9440 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
9441 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
9442 
9443 #define TIM_CR1_DITHEN_Pos      (12U)
9444 #define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
9445 #define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
9446 
9447 /*******************  Bit definition for TIM_CR2 register  ********************/
9448 #define TIM_CR2_CCPC_Pos          (0U)
9449 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
9450 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
9451 #define TIM_CR2_CCUS_Pos          (2U)
9452 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
9453 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
9454 #define TIM_CR2_CCDS_Pos          (3U)
9455 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
9456 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
9457 
9458 #define TIM_CR2_MMS_Pos           (4U)
9459 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
9460 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
9461 #define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
9462 #define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
9463 #define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
9464 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
9465 
9466 #define TIM_CR2_TI1S_Pos          (7U)
9467 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
9468 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
9469 #define TIM_CR2_OIS1_Pos          (8U)
9470 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
9471 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
9472 #define TIM_CR2_OIS1N_Pos         (9U)
9473 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
9474 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
9475 #define TIM_CR2_OIS2_Pos          (10U)
9476 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
9477 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
9478 #define TIM_CR2_OIS2N_Pos         (11U)
9479 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
9480 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
9481 #define TIM_CR2_OIS3_Pos          (12U)
9482 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
9483 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
9484 #define TIM_CR2_OIS3N_Pos         (13U)
9485 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
9486 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
9487 #define TIM_CR2_OIS4_Pos          (14U)
9488 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
9489 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
9490 #define TIM_CR2_OIS4N_Pos         (15U)
9491 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
9492 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
9493 #define TIM_CR2_OIS5_Pos          (16U)
9494 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
9495 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
9496 #define TIM_CR2_OIS6_Pos          (18U)
9497 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
9498 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
9499 
9500 #define TIM_CR2_MMS2_Pos          (20U)
9501 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
9502 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
9503 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
9504 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
9505 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
9506 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
9507 
9508 /*******************  Bit definition for TIM_SMCR register  *******************/
9509 #define TIM_SMCR_SMS_Pos          (0U)
9510 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
9511 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
9512 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
9513 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
9514 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
9515 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
9516 
9517 #define TIM_SMCR_OCCS_Pos         (3U)
9518 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
9519 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
9520 
9521 #define TIM_SMCR_TS_Pos           (4U)
9522 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
9523 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
9524 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
9525 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
9526 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
9527 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
9528 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
9529 
9530 #define TIM_SMCR_MSM_Pos          (7U)
9531 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
9532 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
9533 
9534 #define TIM_SMCR_ETF_Pos          (8U)
9535 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
9536 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
9537 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
9538 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
9539 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
9540 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
9541 
9542 #define TIM_SMCR_ETPS_Pos         (12U)
9543 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
9544 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
9545 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
9546 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
9547 
9548 #define TIM_SMCR_ECE_Pos          (14U)
9549 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
9550 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
9551 #define TIM_SMCR_ETP_Pos          (15U)
9552 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
9553 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
9554 
9555 #define TIM_SMCR_SMSPE_Pos        (24U)
9556 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
9557 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
9558 
9559 #define TIM_SMCR_SMSPS_Pos        (25U)
9560 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
9561 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
9562 
9563 /*******************  Bit definition for TIM_DIER register  *******************/
9564 #define TIM_DIER_UIE_Pos          (0U)
9565 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
9566 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
9567 #define TIM_DIER_CC1IE_Pos        (1U)
9568 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
9569 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
9570 #define TIM_DIER_CC2IE_Pos        (2U)
9571 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
9572 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
9573 #define TIM_DIER_CC3IE_Pos        (3U)
9574 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
9575 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
9576 #define TIM_DIER_CC4IE_Pos        (4U)
9577 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
9578 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
9579 #define TIM_DIER_COMIE_Pos        (5U)
9580 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
9581 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
9582 #define TIM_DIER_TIE_Pos          (6U)
9583 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
9584 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
9585 #define TIM_DIER_BIE_Pos          (7U)
9586 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
9587 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
9588 #define TIM_DIER_UDE_Pos          (8U)
9589 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
9590 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
9591 #define TIM_DIER_CC1DE_Pos        (9U)
9592 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
9593 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
9594 #define TIM_DIER_CC2DE_Pos        (10U)
9595 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
9596 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
9597 #define TIM_DIER_CC3DE_Pos        (11U)
9598 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
9599 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
9600 #define TIM_DIER_CC4DE_Pos        (12U)
9601 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
9602 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
9603 #define TIM_DIER_COMDE_Pos        (13U)
9604 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
9605 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
9606 #define TIM_DIER_TDE_Pos          (14U)
9607 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
9608 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
9609 #define TIM_DIER_IDXIE_Pos        (20U)
9610 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
9611 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
9612 #define TIM_DIER_DIRIE_Pos        (21U)
9613 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
9614 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
9615 #define TIM_DIER_IERRIE_Pos       (22U)
9616 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
9617 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
9618 #define TIM_DIER_TERRIE_Pos       (23U)
9619 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
9620 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
9621 
9622 /********************  Bit definition for TIM_SR register  ********************/
9623 #define TIM_SR_UIF_Pos            (0U)
9624 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
9625 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
9626 #define TIM_SR_CC1IF_Pos          (1U)
9627 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
9628 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
9629 #define TIM_SR_CC2IF_Pos          (2U)
9630 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
9631 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
9632 #define TIM_SR_CC3IF_Pos          (3U)
9633 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
9634 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
9635 #define TIM_SR_CC4IF_Pos          (4U)
9636 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
9637 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
9638 #define TIM_SR_COMIF_Pos          (5U)
9639 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
9640 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
9641 #define TIM_SR_TIF_Pos            (6U)
9642 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
9643 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
9644 #define TIM_SR_BIF_Pos            (7U)
9645 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
9646 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
9647 #define TIM_SR_B2IF_Pos           (8U)
9648 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
9649 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
9650 #define TIM_SR_CC1OF_Pos          (9U)
9651 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
9652 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
9653 #define TIM_SR_CC2OF_Pos          (10U)
9654 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
9655 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
9656 #define TIM_SR_CC3OF_Pos          (11U)
9657 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
9658 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
9659 #define TIM_SR_CC4OF_Pos          (12U)
9660 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
9661 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
9662 #define TIM_SR_SBIF_Pos           (13U)
9663 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
9664 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
9665 #define TIM_SR_CC5IF_Pos          (16U)
9666 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
9667 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
9668 #define TIM_SR_CC6IF_Pos          (17U)
9669 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
9670 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
9671 #define TIM_SR_IDXF_Pos           (20U)
9672 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
9673 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
9674 #define TIM_SR_DIRF_Pos           (21U)
9675 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
9676 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
9677 #define TIM_SR_IERRF_Pos          (22U)
9678 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
9679 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
9680 #define TIM_SR_TERRF_Pos          (23U)
9681 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
9682 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
9683 
9684 /*******************  Bit definition for TIM_EGR register  ********************/
9685 #define TIM_EGR_UG_Pos            (0U)
9686 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
9687 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
9688 #define TIM_EGR_CC1G_Pos          (1U)
9689 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
9690 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
9691 #define TIM_EGR_CC2G_Pos          (2U)
9692 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
9693 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
9694 #define TIM_EGR_CC3G_Pos          (3U)
9695 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
9696 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
9697 #define TIM_EGR_CC4G_Pos          (4U)
9698 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
9699 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
9700 #define TIM_EGR_COMG_Pos          (5U)
9701 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
9702 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
9703 #define TIM_EGR_TG_Pos            (6U)
9704 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
9705 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
9706 #define TIM_EGR_BG_Pos            (7U)
9707 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
9708 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
9709 #define TIM_EGR_B2G_Pos           (8U)
9710 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
9711 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
9712 
9713 
9714 /******************  Bit definition for TIM_CCMR1 register  *******************/
9715 #define TIM_CCMR1_CC1S_Pos        (0U)
9716 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
9717 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
9718 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
9719 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
9720 
9721 #define TIM_CCMR1_OC1FE_Pos       (2U)
9722 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
9723 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
9724 #define TIM_CCMR1_OC1PE_Pos       (3U)
9725 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
9726 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
9727 
9728 #define TIM_CCMR1_OC1M_Pos        (4U)
9729 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
9730 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
9731 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
9732 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
9733 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
9734 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
9735 
9736 #define TIM_CCMR1_OC1CE_Pos       (7U)
9737 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
9738 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
9739 
9740 #define TIM_CCMR1_CC2S_Pos        (8U)
9741 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
9742 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
9743 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
9744 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
9745 
9746 #define TIM_CCMR1_OC2FE_Pos       (10U)
9747 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
9748 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
9749 #define TIM_CCMR1_OC2PE_Pos       (11U)
9750 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
9751 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
9752 
9753 #define TIM_CCMR1_OC2M_Pos        (12U)
9754 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
9755 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
9756 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
9757 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
9758 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
9759 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
9760 
9761 #define TIM_CCMR1_OC2CE_Pos       (15U)
9762 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
9763 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
9764 
9765 /*----------------------------------------------------------------------------*/
9766 #define TIM_CCMR1_IC1PSC_Pos      (2U)
9767 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
9768 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
9769 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
9770 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
9771 
9772 #define TIM_CCMR1_IC1F_Pos        (4U)
9773 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
9774 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
9775 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
9776 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
9777 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
9778 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
9779 
9780 #define TIM_CCMR1_IC2PSC_Pos      (10U)
9781 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
9782 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
9783 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
9784 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
9785 
9786 #define TIM_CCMR1_IC2F_Pos        (12U)
9787 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
9788 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
9789 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
9790 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
9791 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
9792 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
9793 
9794 /******************  Bit definition for TIM_CCMR2 register  *******************/
9795 #define TIM_CCMR2_CC3S_Pos        (0U)
9796 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
9797 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
9798 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
9799 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
9800 
9801 #define TIM_CCMR2_OC3FE_Pos       (2U)
9802 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
9803 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
9804 #define TIM_CCMR2_OC3PE_Pos       (3U)
9805 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
9806 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
9807 
9808 #define TIM_CCMR2_OC3M_Pos        (4U)
9809 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
9810 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
9811 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
9812 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
9813 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
9814 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
9815 
9816 #define TIM_CCMR2_OC3CE_Pos       (7U)
9817 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
9818 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
9819 
9820 #define TIM_CCMR2_CC4S_Pos        (8U)
9821 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
9822 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
9823 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
9824 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
9825 
9826 #define TIM_CCMR2_OC4FE_Pos       (10U)
9827 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
9828 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
9829 #define TIM_CCMR2_OC4PE_Pos       (11U)
9830 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
9831 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
9832 
9833 #define TIM_CCMR2_OC4M_Pos        (12U)
9834 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
9835 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
9836 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
9837 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
9838 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
9839 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
9840 
9841 #define TIM_CCMR2_OC4CE_Pos       (15U)
9842 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
9843 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
9844 
9845 /*----------------------------------------------------------------------------*/
9846 #define TIM_CCMR2_IC3PSC_Pos      (2U)
9847 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
9848 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
9849 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
9850 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
9851 
9852 #define TIM_CCMR2_IC3F_Pos        (4U)
9853 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
9854 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
9855 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
9856 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
9857 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
9858 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
9859 
9860 #define TIM_CCMR2_IC4PSC_Pos      (10U)
9861 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
9862 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
9863 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
9864 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
9865 
9866 #define TIM_CCMR2_IC4F_Pos        (12U)
9867 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
9868 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
9869 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
9870 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
9871 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
9872 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
9873 
9874 /******************  Bit definition for TIM_CCMR3 register  *******************/
9875 #define TIM_CCMR3_OC5FE_Pos       (2U)
9876 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
9877 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
9878 #define TIM_CCMR3_OC5PE_Pos       (3U)
9879 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
9880 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
9881 
9882 #define TIM_CCMR3_OC5M_Pos        (4U)
9883 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
9884 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
9885 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
9886 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
9887 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
9888 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
9889 
9890 #define TIM_CCMR3_OC5CE_Pos       (7U)
9891 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
9892 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
9893 
9894 #define TIM_CCMR3_OC6FE_Pos       (10U)
9895 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
9896 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
9897 #define TIM_CCMR3_OC6PE_Pos       (11U)
9898 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
9899 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
9900 
9901 #define TIM_CCMR3_OC6M_Pos        (12U)
9902 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
9903 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
9904 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
9905 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
9906 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
9907 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
9908 
9909 #define TIM_CCMR3_OC6CE_Pos       (15U)
9910 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
9911 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
9912 
9913 /*******************  Bit definition for TIM_CCER register  *******************/
9914 #define TIM_CCER_CC1E_Pos         (0U)
9915 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
9916 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
9917 #define TIM_CCER_CC1P_Pos         (1U)
9918 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
9919 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
9920 #define TIM_CCER_CC1NE_Pos        (2U)
9921 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
9922 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
9923 #define TIM_CCER_CC1NP_Pos        (3U)
9924 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
9925 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
9926 #define TIM_CCER_CC2E_Pos         (4U)
9927 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
9928 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
9929 #define TIM_CCER_CC2P_Pos         (5U)
9930 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
9931 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
9932 #define TIM_CCER_CC2NE_Pos        (6U)
9933 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
9934 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
9935 #define TIM_CCER_CC2NP_Pos        (7U)
9936 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
9937 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
9938 #define TIM_CCER_CC3E_Pos         (8U)
9939 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
9940 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
9941 #define TIM_CCER_CC3P_Pos         (9U)
9942 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
9943 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
9944 #define TIM_CCER_CC3NE_Pos        (10U)
9945 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
9946 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
9947 #define TIM_CCER_CC3NP_Pos        (11U)
9948 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
9949 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
9950 #define TIM_CCER_CC4E_Pos         (12U)
9951 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
9952 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
9953 #define TIM_CCER_CC4P_Pos         (13U)
9954 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
9955 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
9956 #define TIM_CCER_CC4NE_Pos        (14U)
9957 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
9958 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
9959 #define TIM_CCER_CC4NP_Pos        (15U)
9960 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
9961 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
9962 #define TIM_CCER_CC5E_Pos         (16U)
9963 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
9964 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
9965 #define TIM_CCER_CC5P_Pos         (17U)
9966 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
9967 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
9968 #define TIM_CCER_CC6E_Pos         (20U)
9969 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
9970 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
9971 #define TIM_CCER_CC6P_Pos         (21U)
9972 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
9973 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
9974 
9975 /*******************  Bit definition for TIM_CNT register  ********************/
9976 #define TIM_CNT_CNT_Pos           (0U)
9977 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
9978 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
9979 #define TIM_CNT_UIFCPY_Pos        (31U)
9980 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
9981 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
9982 
9983 /*******************  Bit definition for TIM_PSC register  ********************/
9984 #define TIM_PSC_PSC_Pos           (0U)
9985 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
9986 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
9987 
9988 /*******************  Bit definition for TIM_ARR register  ********************/
9989 #define TIM_ARR_ARR_Pos           (0U)
9990 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
9991 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
9992 
9993 /*******************  Bit definition for TIM_RCR register  ********************/
9994 #define TIM_RCR_REP_Pos           (0U)
9995 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
9996 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
9997 
9998 /*******************  Bit definition for TIM_CCR1 register  *******************/
9999 #define TIM_CCR1_CCR1_Pos         (0U)
10000 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
10001 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
10002 
10003 /*******************  Bit definition for TIM_CCR2 register  *******************/
10004 #define TIM_CCR2_CCR2_Pos         (0U)
10005 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
10006 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
10007 
10008 /*******************  Bit definition for TIM_CCR3 register  *******************/
10009 #define TIM_CCR3_CCR3_Pos         (0U)
10010 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
10011 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
10012 
10013 /*******************  Bit definition for TIM_CCR4 register  *******************/
10014 #define TIM_CCR4_CCR4_Pos         (0U)
10015 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
10016 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
10017 
10018 /*******************  Bit definition for TIM_CCR5 register  *******************/
10019 #define TIM_CCR5_CCR5_Pos         (0U)
10020 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
10021 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
10022 #define TIM_CCR5_GC5C1_Pos        (29U)
10023 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
10024 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
10025 #define TIM_CCR5_GC5C2_Pos        (30U)
10026 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
10027 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
10028 #define TIM_CCR5_GC5C3_Pos        (31U)
10029 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
10030 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
10031 
10032 /*******************  Bit definition for TIM_CCR6 register  *******************/
10033 #define TIM_CCR6_CCR6_Pos         (0U)
10034 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
10035 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
10036 
10037 /*******************  Bit definition for TIM_BDTR register  *******************/
10038 #define TIM_BDTR_DTG_Pos          (0U)
10039 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
10040 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10041 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
10042 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
10043 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
10044 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
10045 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
10046 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
10047 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
10048 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
10049 
10050 #define TIM_BDTR_LOCK_Pos         (8U)
10051 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
10052 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
10053 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
10054 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
10055 
10056 #define TIM_BDTR_OSSI_Pos         (10U)
10057 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
10058 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
10059 #define TIM_BDTR_OSSR_Pos         (11U)
10060 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
10061 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
10062 #define TIM_BDTR_BKE_Pos          (12U)
10063 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
10064 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
10065 #define TIM_BDTR_BKP_Pos          (13U)
10066 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
10067 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
10068 #define TIM_BDTR_AOE_Pos          (14U)
10069 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
10070 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
10071 #define TIM_BDTR_MOE_Pos          (15U)
10072 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
10073 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
10074 
10075 #define TIM_BDTR_BKF_Pos          (16U)
10076 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
10077 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
10078 #define TIM_BDTR_BK2F_Pos         (20U)
10079 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
10080 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
10081 
10082 #define TIM_BDTR_BK2E_Pos         (24U)
10083 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
10084 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
10085 #define TIM_BDTR_BK2P_Pos         (25U)
10086 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
10087 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
10088 
10089 #define TIM_BDTR_BKDSRM_Pos       (26U)
10090 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
10091 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
10092 #define TIM_BDTR_BK2DSRM_Pos      (27U)
10093 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
10094 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
10095 
10096 #define TIM_BDTR_BKBID_Pos        (28U)
10097 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
10098 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
10099 #define TIM_BDTR_BK2BID_Pos       (29U)
10100 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
10101 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
10102 
10103 /*******************  Bit definition for TIM_DCR register  ********************/
10104 #define TIM_DCR_DBA_Pos           (0U)
10105 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
10106 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
10107 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
10108 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
10109 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
10110 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
10111 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
10112 
10113 #define TIM_DCR_DBL_Pos           (8U)
10114 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
10115 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
10116 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
10117 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
10118 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
10119 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
10120 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
10121 
10122 /*******************  Bit definition for TIM1_AF1 register  *******************/
10123 #define TIM1_AF1_BKINE_Pos        (0U)
10124 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
10125 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
10126 #define TIM1_AF1_BKCMP1E_Pos      (1U)
10127 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
10128 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
10129 #define TIM1_AF1_BKCMP2E_Pos      (2U)
10130 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
10131 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
10132 #define TIM1_AF1_BKCMP3E_Pos      (3U)
10133 #define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
10134 #define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
10135 #define TIM1_AF1_BKINP_Pos        (9U)
10136 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
10137 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
10138 #define TIM1_AF1_BKCMP1P_Pos      (10U)
10139 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
10140 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
10141 #define TIM1_AF1_BKCMP2P_Pos      (11U)
10142 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
10143 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
10144 #define TIM1_AF1_BKCMP3P_Pos      (12U)
10145 #define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
10146 #define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
10147 #define TIM1_AF1_ETRSEL_Pos       (14U)
10148 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
10149 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
10150 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
10151 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
10152 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
10153 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
10154 
10155 /*******************  Bit definition for TIM1_AF2 register  *********************/
10156 #define TIM1_AF2_BK2INE_Pos        (0U)
10157 #define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
10158 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
10159 #define TIM1_AF2_BK2CMP1E_Pos      (1U)
10160 #define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
10161 #define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
10162 #define TIM1_AF2_BK2CMP2E_Pos      (2U)
10163 #define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
10164 #define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
10165 #define TIM1_AF2_BK2CMP3E_Pos      (3U)
10166 #define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
10167 #define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
10168 #define TIM1_AF2_BK2INP_Pos        (9U)
10169 #define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
10170 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
10171 #define TIM1_AF2_BK2CMP1P_Pos      (10U)
10172 #define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
10173 #define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
10174 #define TIM1_AF2_BK2CMP2P_Pos      (11U)
10175 #define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
10176 #define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
10177 #define TIM1_AF2_BK2CMP3P_Pos      (12U)
10178 #define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
10179 #define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
10180 #define TIM1_AF2_OCRSEL_Pos        (16U)
10181 #define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
10182 #define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
10183 #define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
10184 #define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
10185 #define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
10186 
10187 /*******************  Bit definition for TIM_OR register  *********************/
10188 #define TIM_OR_HSE32EN_Pos       (0U)
10189 #define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
10190 #define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
10191 
10192 /*******************  Bit definition for TIM_TISEL register  *********************/
10193 #define TIM_TISEL_TI1SEL_Pos      (0U)
10194 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
10195 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
10196 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
10197 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
10198 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
10199 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
10200 
10201 #define TIM_TISEL_TI2SEL_Pos      (8U)
10202 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
10203 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
10204 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
10205 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
10206 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
10207 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
10208 
10209 #define TIM_TISEL_TI3SEL_Pos      (16U)
10210 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
10211 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
10212 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
10213 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
10214 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
10215 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
10216 
10217 #define TIM_TISEL_TI4SEL_Pos      (24U)
10218 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
10219 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
10220 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
10221 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
10222 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
10223 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
10224 
10225 /*******************  Bit definition for TIM_DTR2 register  *********************/
10226 #define TIM_DTR2_DTGF_Pos      (0U)
10227 #define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
10228 #define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
10229 #define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
10230 #define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
10231 #define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
10232 #define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
10233 #define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
10234 #define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
10235 #define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
10236 #define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
10237 
10238 #define TIM_DTR2_DTAE_Pos      (16U)
10239 #define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
10240 #define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
10241 #define TIM_DTR2_DTPE_Pos      (17U)
10242 #define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
10243 #define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
10244 
10245 /*******************  Bit definition for TIM_ECR register  *********************/
10246 #define TIM_ECR_IE_Pos       (0U)
10247 #define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
10248 #define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
10249 
10250 #define TIM_ECR_IDIR_Pos      (1U)
10251 #define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
10252 #define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
10253 #define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
10254 #define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
10255 
10256 #define TIM_ECR_FIDX_Pos      (5U)
10257 #define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
10258 #define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
10259 
10260 #define TIM_ECR_IPOS_Pos      (6U)
10261 #define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
10262 #define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
10263 #define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
10264 #define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
10265 
10266 #define TIM_ECR_PW_Pos        (16U)
10267 #define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
10268 #define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
10269 #define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
10270 #define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
10271 #define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
10272 #define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
10273 #define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
10274 #define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
10275 #define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
10276 #define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
10277 
10278 #define TIM_ECR_PWPRSC_Pos    (24U)
10279 #define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
10280 #define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
10281 #define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
10282 #define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
10283 #define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
10284 
10285 /*******************  Bit definition for TIM_DMAR register  *******************/
10286 #define TIM_DMAR_DMAB_Pos         (0U)
10287 #define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
10288 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
10289 
10290 /******************************************************************************/
10291 /*                                                                            */
10292 /*                         Low Power Timer (LPTIM)                           */
10293 /*                                                                            */
10294 /******************************************************************************/
10295 /******************  Bit definition for LPTIM_ISR register  *******************/
10296 #define LPTIM_ISR_CMPM_Pos          (0U)
10297 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
10298 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
10299 #define LPTIM_ISR_ARRM_Pos          (1U)
10300 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
10301 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
10302 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
10303 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
10304 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
10305 #define LPTIM_ISR_CMPOK_Pos         (3U)
10306 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
10307 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
10308 #define LPTIM_ISR_ARROK_Pos         (4U)
10309 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
10310 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
10311 #define LPTIM_ISR_UP_Pos            (5U)
10312 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
10313 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
10314 #define LPTIM_ISR_DOWN_Pos          (6U)
10315 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
10316 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
10317 
10318 /******************  Bit definition for LPTIM_ICR register  *******************/
10319 #define LPTIM_ICR_CMPMCF_Pos        (0U)
10320 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
10321 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
10322 #define LPTIM_ICR_ARRMCF_Pos        (1U)
10323 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
10324 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
10325 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
10326 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
10327 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
10328 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
10329 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
10330 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
10331 #define LPTIM_ICR_ARROKCF_Pos       (4U)
10332 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
10333 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
10334 #define LPTIM_ICR_UPCF_Pos          (5U)
10335 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
10336 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
10337 #define LPTIM_ICR_DOWNCF_Pos        (6U)
10338 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
10339 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
10340 
10341 /******************  Bit definition for LPTIM_IER register ********************/
10342 #define LPTIM_IER_CMPMIE_Pos        (0U)
10343 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
10344 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
10345 #define LPTIM_IER_ARRMIE_Pos        (1U)
10346 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
10347 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
10348 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
10349 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
10350 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
10351 #define LPTIM_IER_CMPOKIE_Pos       (3U)
10352 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
10353 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
10354 #define LPTIM_IER_ARROKIE_Pos       (4U)
10355 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
10356 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
10357 #define LPTIM_IER_UPIE_Pos          (5U)
10358 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
10359 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
10360 #define LPTIM_IER_DOWNIE_Pos        (6U)
10361 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
10362 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
10363 
10364 /******************  Bit definition for LPTIM_CFGR register *******************/
10365 #define LPTIM_CFGR_CKSEL_Pos        (0U)
10366 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
10367 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
10368 
10369 #define LPTIM_CFGR_CKPOL_Pos        (1U)
10370 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
10371 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
10372 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
10373 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
10374 
10375 #define LPTIM_CFGR_CKFLT_Pos        (3U)
10376 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
10377 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
10378 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
10379 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
10380 
10381 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
10382 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
10383 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
10384 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
10385 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
10386 
10387 #define LPTIM_CFGR_PRESC_Pos        (9U)
10388 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
10389 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
10390 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
10391 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
10392 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
10393 
10394 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
10395 #define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
10396 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
10397 #define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
10398 #define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
10399 #define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
10400 #define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
10401 
10402 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
10403 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
10404 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
10405 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
10406 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
10407 
10408 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
10409 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
10410 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
10411 #define LPTIM_CFGR_WAVE_Pos         (20U)
10412 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
10413 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
10414 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
10415 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
10416 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
10417 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
10418 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
10419 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
10420 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
10421 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
10422 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
10423 #define LPTIM_CFGR_ENC_Pos          (24U)
10424 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
10425 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
10426 
10427 /******************  Bit definition for LPTIM_CR register  ********************/
10428 #define LPTIM_CR_ENABLE_Pos         (0U)
10429 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
10430 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
10431 #define LPTIM_CR_SNGSTRT_Pos        (1U)
10432 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
10433 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
10434 #define LPTIM_CR_CNTSTRT_Pos        (2U)
10435 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
10436 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
10437 #define LPTIM_CR_COUNTRST_Pos       (3U)
10438 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
10439 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
10440 #define LPTIM_CR_RSTARE_Pos         (4U)
10441 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
10442 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
10443 
10444 /******************  Bit definition for LPTIM_CMP register  *******************/
10445 #define LPTIM_CMP_CMP_Pos           (0U)
10446 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
10447 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
10448 
10449 /******************  Bit definition for LPTIM_ARR register  *******************/
10450 #define LPTIM_ARR_ARR_Pos           (0U)
10451 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
10452 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
10453 
10454 /******************  Bit definition for LPTIM_CNT register  *******************/
10455 #define LPTIM_CNT_CNT_Pos           (0U)
10456 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
10457 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
10458 
10459 /******************  Bit definition for LPTIM_OR register  *******************/
10460 #define LPTIM_OR_IN1_Pos             (0U)
10461 #define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
10462 #define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
10463 #define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
10464 #define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
10465 #define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
10466 
10467 #define LPTIM_OR_IN2_Pos             (1U)
10468 #define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
10469 #define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
10470 #define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
10471 #define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
10472 #define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
10473 /******************************************************************************/
10474 /*                                                                            */
10475 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
10476 /*                                                                            */
10477 /******************************************************************************/
10478 /******************  Bit definition for USART_CR1 register  *******************/
10479 #define USART_CR1_UE_Pos             (0U)
10480 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
10481 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
10482 #define USART_CR1_UESM_Pos           (1U)
10483 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
10484 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
10485 #define USART_CR1_RE_Pos             (2U)
10486 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
10487 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
10488 #define USART_CR1_TE_Pos             (3U)
10489 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
10490 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
10491 #define USART_CR1_IDLEIE_Pos         (4U)
10492 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
10493 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
10494 #define USART_CR1_RXNEIE_Pos         (5U)
10495 #define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
10496 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
10497 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
10498 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
10499 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
10500 #define USART_CR1_TCIE_Pos           (6U)
10501 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
10502 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
10503 #define USART_CR1_TXEIE_Pos          (7U)
10504 #define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
10505 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
10506 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
10507 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
10508 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
10509 #define USART_CR1_PEIE_Pos           (8U)
10510 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
10511 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
10512 #define USART_CR1_PS_Pos             (9U)
10513 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
10514 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
10515 #define USART_CR1_PCE_Pos            (10U)
10516 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
10517 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
10518 #define USART_CR1_WAKE_Pos           (11U)
10519 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
10520 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
10521 #define USART_CR1_M_Pos              (12U)
10522 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
10523 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
10524 #define USART_CR1_M0_Pos             (12U)
10525 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
10526 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
10527 #define USART_CR1_MME_Pos            (13U)
10528 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
10529 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
10530 #define USART_CR1_CMIE_Pos           (14U)
10531 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
10532 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
10533 #define USART_CR1_OVER8_Pos          (15U)
10534 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
10535 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
10536 #define USART_CR1_DEDT_Pos           (16U)
10537 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
10538 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
10539 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
10540 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
10541 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
10542 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
10543 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
10544 #define USART_CR1_DEAT_Pos           (21U)
10545 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
10546 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
10547 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
10548 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
10549 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
10550 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
10551 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
10552 #define USART_CR1_RTOIE_Pos          (26U)
10553 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
10554 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
10555 #define USART_CR1_EOBIE_Pos          (27U)
10556 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
10557 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
10558 #define USART_CR1_M1_Pos             (28U)
10559 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
10560 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
10561 #define USART_CR1_FIFOEN_Pos         (29U)
10562 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
10563 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
10564 #define USART_CR1_TXFEIE_Pos         (30U)
10565 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
10566 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
10567 #define USART_CR1_RXFFIE_Pos         (31U)
10568 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
10569 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
10570 
10571 /******************  Bit definition for USART_CR2 register  *******************/
10572 #define USART_CR2_SLVEN_Pos          (0U)
10573 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
10574 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
10575 #define USART_CR2_DIS_NSS_Pos        (3U)
10576 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
10577 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
10578 #define USART_CR2_ADDM7_Pos          (4U)
10579 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
10580 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
10581 #define USART_CR2_LBDL_Pos           (5U)
10582 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
10583 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
10584 #define USART_CR2_LBDIE_Pos          (6U)
10585 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
10586 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
10587 #define USART_CR2_LBCL_Pos           (8U)
10588 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
10589 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
10590 #define USART_CR2_CPHA_Pos           (9U)
10591 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
10592 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
10593 #define USART_CR2_CPOL_Pos           (10U)
10594 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
10595 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
10596 #define USART_CR2_CLKEN_Pos          (11U)
10597 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
10598 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
10599 #define USART_CR2_STOP_Pos           (12U)
10600 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
10601 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
10602 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
10603 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
10604 #define USART_CR2_LINEN_Pos          (14U)
10605 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
10606 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
10607 #define USART_CR2_SWAP_Pos           (15U)
10608 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
10609 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
10610 #define USART_CR2_RXINV_Pos          (16U)
10611 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
10612 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
10613 #define USART_CR2_TXINV_Pos          (17U)
10614 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
10615 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
10616 #define USART_CR2_DATAINV_Pos        (18U)
10617 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
10618 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
10619 #define USART_CR2_MSBFIRST_Pos       (19U)
10620 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
10621 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
10622 #define USART_CR2_ABREN_Pos          (20U)
10623 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
10624 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
10625 #define USART_CR2_ABRMODE_Pos        (21U)
10626 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
10627 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10628 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
10629 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
10630 #define USART_CR2_RTOEN_Pos          (23U)
10631 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
10632 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
10633 #define USART_CR2_ADD_Pos            (24U)
10634 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
10635 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
10636 
10637 /******************  Bit definition for USART_CR3 register  *******************/
10638 #define USART_CR3_EIE_Pos            (0U)
10639 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
10640 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
10641 #define USART_CR3_IREN_Pos           (1U)
10642 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
10643 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
10644 #define USART_CR3_IRLP_Pos           (2U)
10645 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
10646 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
10647 #define USART_CR3_HDSEL_Pos          (3U)
10648 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
10649 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
10650 #define USART_CR3_NACK_Pos           (4U)
10651 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
10652 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
10653 #define USART_CR3_SCEN_Pos           (5U)
10654 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
10655 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
10656 #define USART_CR3_DMAR_Pos           (6U)
10657 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
10658 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
10659 #define USART_CR3_DMAT_Pos           (7U)
10660 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
10661 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
10662 #define USART_CR3_RTSE_Pos           (8U)
10663 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
10664 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
10665 #define USART_CR3_CTSE_Pos           (9U)
10666 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
10667 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
10668 #define USART_CR3_CTSIE_Pos          (10U)
10669 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
10670 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
10671 #define USART_CR3_ONEBIT_Pos         (11U)
10672 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
10673 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
10674 #define USART_CR3_OVRDIS_Pos         (12U)
10675 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
10676 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
10677 #define USART_CR3_DDRE_Pos           (13U)
10678 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
10679 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
10680 #define USART_CR3_DEM_Pos            (14U)
10681 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
10682 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
10683 #define USART_CR3_DEP_Pos            (15U)
10684 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
10685 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
10686 #define USART_CR3_SCARCNT_Pos        (17U)
10687 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
10688 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10689 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
10690 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
10691 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
10692 #define USART_CR3_WUS_Pos            (20U)
10693 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
10694 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
10695 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
10696 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
10697 #define USART_CR3_WUFIE_Pos          (22U)
10698 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
10699 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
10700 #define USART_CR3_TXFTIE_Pos         (23U)
10701 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
10702 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
10703 #define USART_CR3_TCBGTIE_Pos        (24U)
10704 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
10705 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
10706 #define USART_CR3_RXFTCFG_Pos        (25U)
10707 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
10708 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
10709 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
10710 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
10711 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
10712 #define USART_CR3_RXFTIE_Pos         (28U)
10713 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
10714 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
10715 #define USART_CR3_TXFTCFG_Pos        (29U)
10716 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
10717 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
10718 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
10719 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
10720 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
10721 
10722 /******************  Bit definition for USART_BRR register  *******************/
10723 #define USART_BRR_LPUART_Pos         (0U)
10724 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
10725 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
10726 #define USART_BRR_BRR_Pos            (0U)
10727 #define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
10728 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
10729 
10730 /******************  Bit definition for USART_GTPR register  ******************/
10731 #define USART_GTPR_PSC_Pos           (0U)
10732 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
10733 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
10734 #define USART_GTPR_GT_Pos            (8U)
10735 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
10736 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
10737 
10738 /*******************  Bit definition for USART_RTOR register  *****************/
10739 #define USART_RTOR_RTO_Pos           (0U)
10740 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
10741 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
10742 #define USART_RTOR_BLEN_Pos          (24U)
10743 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
10744 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
10745 
10746 /*******************  Bit definition for USART_RQR register  ******************/
10747 #define USART_RQR_ABRRQ_Pos          (0U)
10748 #define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
10749 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
10750 #define USART_RQR_SBKRQ_Pos          (1U)
10751 #define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
10752 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
10753 #define USART_RQR_MMRQ_Pos           (2U)
10754 #define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
10755 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
10756 #define USART_RQR_RXFRQ_Pos          (3U)
10757 #define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
10758 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
10759 #define USART_RQR_TXFRQ_Pos          (4U)
10760 #define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
10761 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
10762 
10763 /*******************  Bit definition for USART_ISR register  ******************/
10764 #define USART_ISR_PE_Pos             (0U)
10765 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
10766 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
10767 #define USART_ISR_FE_Pos             (1U)
10768 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
10769 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
10770 #define USART_ISR_NE_Pos             (2U)
10771 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
10772 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
10773 #define USART_ISR_ORE_Pos            (3U)
10774 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
10775 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
10776 #define USART_ISR_IDLE_Pos           (4U)
10777 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
10778 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
10779 #define USART_ISR_RXNE_Pos           (5U)
10780 #define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
10781 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
10782 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
10783 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
10784 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
10785 #define USART_ISR_TC_Pos             (6U)
10786 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
10787 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
10788 #define USART_ISR_TXE_Pos            (7U)
10789 #define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
10790 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
10791 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
10792 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
10793 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
10794 #define USART_ISR_LBDF_Pos           (8U)
10795 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
10796 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
10797 #define USART_ISR_CTSIF_Pos          (9U)
10798 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
10799 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
10800 #define USART_ISR_CTS_Pos            (10U)
10801 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
10802 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
10803 #define USART_ISR_RTOF_Pos           (11U)
10804 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
10805 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
10806 #define USART_ISR_EOBF_Pos           (12U)
10807 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
10808 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
10809 #define USART_ISR_UDR_Pos            (13U)
10810 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
10811 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
10812 #define USART_ISR_ABRE_Pos           (14U)
10813 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
10814 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
10815 #define USART_ISR_ABRF_Pos           (15U)
10816 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
10817 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
10818 #define USART_ISR_BUSY_Pos           (16U)
10819 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
10820 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
10821 #define USART_ISR_CMF_Pos            (17U)
10822 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
10823 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
10824 #define USART_ISR_SBKF_Pos           (18U)
10825 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
10826 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
10827 #define USART_ISR_RWU_Pos            (19U)
10828 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
10829 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
10830 #define USART_ISR_WUF_Pos            (20U)
10831 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
10832 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
10833 #define USART_ISR_TEACK_Pos          (21U)
10834 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
10835 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
10836 #define USART_ISR_REACK_Pos          (22U)
10837 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
10838 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
10839 #define USART_ISR_TXFE_Pos           (23U)
10840 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
10841 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
10842 #define USART_ISR_RXFF_Pos           (24U)
10843 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
10844 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
10845 #define USART_ISR_TCBGT_Pos          (25U)
10846 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
10847 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
10848 #define USART_ISR_RXFT_Pos           (26U)
10849 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
10850 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
10851 #define USART_ISR_TXFT_Pos           (27U)
10852 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
10853 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
10854 
10855 /*******************  Bit definition for USART_ICR register  ******************/
10856 #define USART_ICR_PECF_Pos           (0U)
10857 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
10858 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
10859 #define USART_ICR_FECF_Pos           (1U)
10860 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
10861 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
10862 #define USART_ICR_NECF_Pos           (2U)
10863 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
10864 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
10865 #define USART_ICR_ORECF_Pos          (3U)
10866 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
10867 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
10868 #define USART_ICR_IDLECF_Pos         (4U)
10869 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
10870 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
10871 #define USART_ICR_TXFECF_Pos         (5U)
10872 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
10873 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
10874 #define USART_ICR_TCCF_Pos           (6U)
10875 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
10876 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
10877 #define USART_ICR_TCBGTCF_Pos        (7U)
10878 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
10879 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
10880 #define USART_ICR_LBDCF_Pos          (8U)
10881 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
10882 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
10883 #define USART_ICR_CTSCF_Pos          (9U)
10884 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
10885 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
10886 #define USART_ICR_RTOCF_Pos          (11U)
10887 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
10888 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
10889 #define USART_ICR_EOBCF_Pos          (12U)
10890 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
10891 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
10892 #define USART_ICR_UDRCF_Pos          (13U)
10893 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
10894 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
10895 #define USART_ICR_CMCF_Pos           (17U)
10896 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
10897 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
10898 #define USART_ICR_WUCF_Pos           (20U)
10899 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
10900 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
10901 
10902 /*******************  Bit definition for USART_RDR register  ******************/
10903 #define USART_RDR_RDR_Pos            (0U)
10904 #define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
10905 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
10906 
10907 /*******************  Bit definition for USART_TDR register  ******************/
10908 #define USART_TDR_TDR_Pos            (0U)
10909 #define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
10910 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
10911 
10912 /*******************  Bit definition for USART_PRESC register  ****************/
10913 #define USART_PRESC_PRESCALER_Pos    (0U)
10914 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
10915 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
10916 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
10917 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
10918 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
10919 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
10920 
10921 
10922 
10923 
10924 /******************************************************************************/
10925 /*                                                                            */
10926 /*                            Window WATCHDOG                                 */
10927 /*                                                                            */
10928 /******************************************************************************/
10929 /*******************  Bit definition for WWDG_CR register  ********************/
10930 #define WWDG_CR_T_Pos           (0U)
10931 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
10932 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
10933 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
10934 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
10935 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
10936 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
10937 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
10938 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
10939 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
10940 
10941 #define WWDG_CR_WDGA_Pos        (7U)
10942 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
10943 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
10944 
10945 /*******************  Bit definition for WWDG_CFR register  *******************/
10946 #define WWDG_CFR_W_Pos          (0U)
10947 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
10948 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
10949 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
10950 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
10951 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
10952 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
10953 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
10954 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
10955 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
10956 
10957 #define WWDG_CFR_WDGTB_Pos      (11U)
10958 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
10959 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
10960 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
10961 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
10962 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
10963 
10964 #define WWDG_CFR_EWI_Pos        (9U)
10965 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
10966 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
10967 
10968 /*******************  Bit definition for WWDG_SR register  ********************/
10969 #define WWDG_SR_EWIF_Pos        (0U)
10970 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
10971 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
10972 
10973 /**
10974   * @}
10975   */
10976 
10977 /**
10978   * @}
10979   */
10980 
10981 /** @addtogroup Exported_macros
10982   * @{
10983   */
10984 
10985 /******************************* ADC Instances ********************************/
10986 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
10987                                        ((INSTANCE) == ADC2))
10988 
10989 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10990 
10991 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
10992 
10993 
10994 /******************************** FDCAN Instances ******************************/
10995 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
10996 
10997 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
10998 /******************************** COMP Instances ******************************/
10999 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
11000                                         ((INSTANCE) == COMP2) || \
11001                                         ((INSTANCE) == COMP3))
11002 
11003 /******************************* CORDIC Instances *****************************/
11004 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
11005 
11006 /******************************* CRC Instances ********************************/
11007 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
11008 
11009 /******************************* DAC Instances ********************************/
11010 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
11011                                        ((INSTANCE) == DAC3))
11012 
11013 
11014 /******************************** DMA Instances *******************************/
11015 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
11016                                        ((INSTANCE) == DMA1_Channel2) || \
11017                                        ((INSTANCE) == DMA1_Channel3) || \
11018                                        ((INSTANCE) == DMA1_Channel4) || \
11019                                        ((INSTANCE) == DMA1_Channel5) || \
11020                                        ((INSTANCE) == DMA1_Channel6) || \
11021                                        ((INSTANCE) == DMA2_Channel1) || \
11022                                        ((INSTANCE) == DMA2_Channel2) || \
11023                                        ((INSTANCE) == DMA2_Channel3) || \
11024                                        ((INSTANCE) == DMA2_Channel4) || \
11025                                        ((INSTANCE) == DMA2_Channel5) || \
11026                                        ((INSTANCE) == DMA2_Channel6))
11027 
11028 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
11029                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
11030                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
11031                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
11032 
11033 /******************************* FMAC Instances *******************************/
11034 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
11035 
11036 /******************************* GPIO Instances *******************************/
11037 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
11038                                         ((INSTANCE) == GPIOB) || \
11039                                         ((INSTANCE) == GPIOC) || \
11040                                         ((INSTANCE) == GPIOD) || \
11041                                         ((INSTANCE) == GPIOE) || \
11042                                         ((INSTANCE) == GPIOF) || \
11043                                         ((INSTANCE) == GPIOG))
11044 
11045 /******************************* GPIO AF Instances ****************************/
11046 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
11047 
11048 /**************************** GPIO Lock Instances *****************************/
11049 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11050 
11051 /******************************** I2C Instances *******************************/
11052 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11053                                        ((INSTANCE) == I2C2))
11054 
11055 /****************** I2C Instances : wakeup capability from stop modes *********/
11056 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
11057 
11058 /****************************** OPAMP Instances *******************************/
11059 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
11060 
11061 
11062 
11063 /******************************* RNG Instances ********************************/
11064 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
11065 
11066 /****************************** RTC Instances *********************************/
11067 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
11068 
11069 #define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
11070 
11071 /****************************** SMBUS Instances *******************************/
11072 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11073                                          ((INSTANCE) == I2C2))
11074 
11075 
11076 /******************************** SPI Instances *******************************/
11077 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11078                                        ((INSTANCE) == SPI2))
11079 
11080 /******************************** I2S Instances *******************************/
11081 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == SPI2)
11082 
11083 /****************** LPTIM Instances : All supported instances *****************/
11084 #define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
11085 
11086 /****************** LPTIM Instances : supporting encoder interface **************/
11087 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
11088 
11089 /****************** LPTIM Instances : All supported instances *****************/
11090 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
11091 
11092 /****************** TIM Instances : All supported instances *******************/
11093 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
11094                                          ((INSTANCE) == TIM2)   || \
11095                                          ((INSTANCE) == TIM3)   || \
11096                                          ((INSTANCE) == TIM4)   || \
11097                                          ((INSTANCE) == TIM6)   || \
11098                                          ((INSTANCE) == TIM7)   || \
11099                                          ((INSTANCE) == TIM8)   || \
11100                                          ((INSTANCE) == TIM15)  || \
11101                                          ((INSTANCE) == TIM16)  || \
11102                                          ((INSTANCE) == TIM17))
11103 
11104 /****************** TIM Instances : supporting 32 bits counter ****************/
11105 
11106 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
11107 
11108 /****************** TIM Instances : supporting the break function *************/
11109 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
11110                                             ((INSTANCE) == TIM8)    || \
11111                                             ((INSTANCE) == TIM15)   || \
11112                                             ((INSTANCE) == TIM16)   || \
11113                                             ((INSTANCE) == TIM17))
11114 
11115 /************** TIM Instances : supporting Break source selection *************/
11116 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11117                                                ((INSTANCE) == TIM8)   || \
11118                                                ((INSTANCE) == TIM15)  || \
11119                                                ((INSTANCE) == TIM16)  || \
11120                                                ((INSTANCE) == TIM17))
11121 
11122 /****************** TIM Instances : supporting 2 break inputs *****************/
11123 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
11124                                             ((INSTANCE) == TIM8))
11125 
11126 /************* TIM Instances : at least 1 capture/compare channel *************/
11127 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11128                                          ((INSTANCE) == TIM2)   || \
11129                                          ((INSTANCE) == TIM3)   || \
11130                                          ((INSTANCE) == TIM4)   || \
11131                                          ((INSTANCE) == TIM8)   || \
11132                                          ((INSTANCE) == TIM15)  || \
11133                                          ((INSTANCE) == TIM16)  || \
11134                                          ((INSTANCE) == TIM17))
11135 
11136 /************ TIM Instances : at least 2 capture/compare channels *************/
11137 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11138                                          ((INSTANCE) == TIM2)   || \
11139                                          ((INSTANCE) == TIM3)   || \
11140                                          ((INSTANCE) == TIM4)   || \
11141                                          ((INSTANCE) == TIM8)   || \
11142                                          ((INSTANCE) == TIM15))
11143 
11144 /************ TIM Instances : at least 3 capture/compare channels *************/
11145 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11146                                          ((INSTANCE) == TIM2)   || \
11147                                          ((INSTANCE) == TIM3)   || \
11148                                          ((INSTANCE) == TIM4)   || \
11149                                          ((INSTANCE) == TIM8))
11150 
11151 /************ TIM Instances : at least 4 capture/compare channels *************/
11152 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11153                                          ((INSTANCE) == TIM2)   || \
11154                                          ((INSTANCE) == TIM3)   || \
11155                                          ((INSTANCE) == TIM4)   || \
11156                                          ((INSTANCE) == TIM8))
11157 
11158 /****************** TIM Instances : at least 5 capture/compare channels *******/
11159 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11160                                          ((INSTANCE) == TIM8))
11161 
11162 /****************** TIM Instances : at least 6 capture/compare channels *******/
11163 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11164                                          ((INSTANCE) == TIM8))
11165 
11166 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
11167 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
11168                                             ((INSTANCE) == TIM8)   || \
11169                                             ((INSTANCE) == TIM15)  || \
11170                                             ((INSTANCE) == TIM16)  || \
11171                                             ((INSTANCE) == TIM17))
11172 
11173 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
11174 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
11175                                             ((INSTANCE) == TIM2)   || \
11176                                             ((INSTANCE) == TIM3)   || \
11177                                             ((INSTANCE) == TIM4)   || \
11178                                             ((INSTANCE) == TIM6)   || \
11179                                             ((INSTANCE) == TIM7)   || \
11180                                             ((INSTANCE) == TIM8)   || \
11181                                             ((INSTANCE) == TIM15)  || \
11182                                             ((INSTANCE) == TIM16)  || \
11183                                             ((INSTANCE) == TIM17))
11184 
11185 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
11186 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
11187                                             ((INSTANCE) == TIM2)   || \
11188                                             ((INSTANCE) == TIM3)   || \
11189                                             ((INSTANCE) == TIM4)   || \
11190                                             ((INSTANCE) == TIM8)   || \
11191                                             ((INSTANCE) == TIM15)  || \
11192                                             ((INSTANCE) == TIM16)  || \
11193                                             ((INSTANCE) == TIM17))
11194 
11195 /******************** TIM Instances : DMA burst feature ***********************/
11196 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11197                                             ((INSTANCE) == TIM2)   || \
11198                                             ((INSTANCE) == TIM3)   || \
11199                                             ((INSTANCE) == TIM4)   || \
11200                                             ((INSTANCE) == TIM8)   || \
11201                                             ((INSTANCE) == TIM15)  || \
11202                                             ((INSTANCE) == TIM16)  || \
11203                                             ((INSTANCE) == TIM17))
11204 
11205 /******************* TIM Instances : output(s) available **********************/
11206 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
11207     ((((INSTANCE) == TIM1) &&                  \
11208      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11209       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11210       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11211       ((CHANNEL) == TIM_CHANNEL_4) ||          \
11212       ((CHANNEL) == TIM_CHANNEL_5) ||          \
11213       ((CHANNEL) == TIM_CHANNEL_6)))           \
11214      ||                                        \
11215      (((INSTANCE) == TIM2) &&                  \
11216      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11217       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11218       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11219       ((CHANNEL) == TIM_CHANNEL_4)))           \
11220      ||                                        \
11221      (((INSTANCE) == TIM3) &&                  \
11222      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11223       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11224       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11225       ((CHANNEL) == TIM_CHANNEL_4)))           \
11226      ||                                        \
11227      (((INSTANCE) == TIM4) &&                  \
11228      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11229       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11230       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11231       ((CHANNEL) == TIM_CHANNEL_4)))           \
11232      ||                                        \
11233      (((INSTANCE) == TIM8) &&                  \
11234      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11235       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11236       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11237       ((CHANNEL) == TIM_CHANNEL_4) ||          \
11238       ((CHANNEL) == TIM_CHANNEL_5) ||          \
11239       ((CHANNEL) == TIM_CHANNEL_6)))           \
11240      ||                                        \
11241      (((INSTANCE) == TIM15) &&                 \
11242      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11243       ((CHANNEL) == TIM_CHANNEL_2)))           \
11244      ||                                        \
11245      (((INSTANCE) == TIM16) &&                 \
11246      (((CHANNEL) == TIM_CHANNEL_1)))           \
11247      ||                                        \
11248      (((INSTANCE) == TIM17) &&                 \
11249       (((CHANNEL) == TIM_CHANNEL_1))))
11250 
11251 /****************** TIM Instances : supporting complementary output(s) ********/
11252 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
11253    ((((INSTANCE) == TIM1) &&                    \
11254      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11255       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11256       ((CHANNEL) == TIM_CHANNEL_3) ||           \
11257       ((CHANNEL) == TIM_CHANNEL_4)))            \
11258     ||                                          \
11259     (((INSTANCE) == TIM8) &&                    \
11260      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11261       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11262       ((CHANNEL) == TIM_CHANNEL_3) ||           \
11263       ((CHANNEL) == TIM_CHANNEL_4)))            \
11264     ||                                          \
11265     (((INSTANCE) == TIM15) &&                   \
11266      ((CHANNEL) == TIM_CHANNEL_1))              \
11267     ||                                          \
11268     (((INSTANCE) == TIM16) &&                   \
11269      ((CHANNEL) == TIM_CHANNEL_1))              \
11270     ||                                          \
11271     (((INSTANCE) == TIM17) &&                   \
11272      ((CHANNEL) == TIM_CHANNEL_1)))
11273 
11274 /****************** TIM Instances : supporting clock division *****************/
11275 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
11276                                                     ((INSTANCE) == TIM2)    || \
11277                                                     ((INSTANCE) == TIM3)    || \
11278                                                     ((INSTANCE) == TIM4)    || \
11279                                                     ((INSTANCE) == TIM8)    || \
11280                                                     ((INSTANCE) == TIM15)   || \
11281                                                     ((INSTANCE) == TIM16)   || \
11282                                                     ((INSTANCE) == TIM17))
11283 
11284 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
11285 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
11286                                                         ((INSTANCE) == TIM2) || \
11287                                                         ((INSTANCE) == TIM3) || \
11288                                                         ((INSTANCE) == TIM4) || \
11289                                                         ((INSTANCE) == TIM8))
11290 
11291 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
11292 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
11293                                                         ((INSTANCE) == TIM2) || \
11294                                                         ((INSTANCE) == TIM3) || \
11295                                                         ((INSTANCE) == TIM4) || \
11296                                                         ((INSTANCE) == TIM8))
11297 
11298 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
11299 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
11300                                                         ((INSTANCE) == TIM2) || \
11301                                                         ((INSTANCE) == TIM3) || \
11302                                                         ((INSTANCE) == TIM4) || \
11303                                                         ((INSTANCE) == TIM8) || \
11304                                                         ((INSTANCE) == TIM15))
11305 
11306 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
11307 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
11308                                                         ((INSTANCE) == TIM2) || \
11309                                                         ((INSTANCE) == TIM3) || \
11310                                                         ((INSTANCE) == TIM4) || \
11311                                                         ((INSTANCE) == TIM8) || \
11312                                                         ((INSTANCE) == TIM15))
11313 
11314 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
11315 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11316                                                      ((INSTANCE) == TIM8))
11317 
11318 /****************** TIM Instances : supporting commutation event generation ***/
11319 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11320                                                      ((INSTANCE) == TIM8)   || \
11321                                                      ((INSTANCE) == TIM15)  || \
11322                                                      ((INSTANCE) == TIM16)  || \
11323                                                      ((INSTANCE) == TIM17))
11324 
11325 /****************** TIM Instances : supporting counting mode selection ********/
11326 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
11327                                                         ((INSTANCE) == TIM2) || \
11328                                                         ((INSTANCE) == TIM3) || \
11329                                                         ((INSTANCE) == TIM4) || \
11330                                                         ((INSTANCE) == TIM8))
11331 
11332 /****************** TIM Instances : supporting encoder interface **************/
11333 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
11334                                                       ((INSTANCE) == TIM2)  || \
11335                                                       ((INSTANCE) == TIM3)  || \
11336                                                       ((INSTANCE) == TIM4)  || \
11337                                                       ((INSTANCE) == TIM8))
11338 
11339 /****************** TIM Instances : supporting Hall sensor interface **********/
11340 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11341                                                          ((INSTANCE) == TIM2)   || \
11342                                                          ((INSTANCE) == TIM3)   || \
11343                                                          ((INSTANCE) == TIM4)   || \
11344                                                          ((INSTANCE) == TIM8)   || \
11345                                                          ((INSTANCE) == TIM15))
11346 
11347 /**************** TIM Instances : external trigger input available ************/
11348 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
11349                                             ((INSTANCE) == TIM2)  || \
11350                                             ((INSTANCE) == TIM3)  || \
11351                                             ((INSTANCE) == TIM4)  || \
11352                                             ((INSTANCE) == TIM8))
11353 
11354 /************* TIM Instances : supporting ETR source selection ***************/
11355 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11356                                              ((INSTANCE) == TIM2)  || \
11357                                              ((INSTANCE) == TIM3)  || \
11358                                              ((INSTANCE) == TIM4)  || \
11359                                              ((INSTANCE) == TIM8))
11360 
11361 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
11362 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
11363                                             ((INSTANCE) == TIM2)  || \
11364                                             ((INSTANCE) == TIM3)  || \
11365                                             ((INSTANCE) == TIM4)  || \
11366                                             ((INSTANCE) == TIM6)  || \
11367                                             ((INSTANCE) == TIM7)  || \
11368                                             ((INSTANCE) == TIM8)  || \
11369                                             ((INSTANCE) == TIM15))
11370 
11371 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
11372 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11373                                             ((INSTANCE) == TIM2)  || \
11374                                             ((INSTANCE) == TIM3)  || \
11375                                             ((INSTANCE) == TIM4)  || \
11376                                             ((INSTANCE) == TIM8)  || \
11377                                             ((INSTANCE) == TIM15))
11378 
11379 /****************** TIM Instances : supporting OCxREF clear *******************/
11380 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
11381                                                        ((INSTANCE) == TIM2) || \
11382                                                        ((INSTANCE) == TIM3) || \
11383                                                        ((INSTANCE) == TIM4)  || \
11384                                                        ((INSTANCE) == TIM8)  || \
11385                                                        ((INSTANCE) == TIM15) || \
11386                                                        ((INSTANCE) == TIM16) || \
11387                                                        ((INSTANCE) == TIM17))
11388 
11389 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
11390 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
11391                                                        ((INSTANCE) == TIM2)  || \
11392                                                        ((INSTANCE) == TIM3)  || \
11393                                                        ((INSTANCE) == TIM8)  || \
11394                                                        ((INSTANCE) == TIM15) || \
11395                                                        ((INSTANCE) == TIM16) || \
11396                                                        ((INSTANCE) == TIM17))
11397 
11398 /****************** TIM Instances : remapping capability **********************/
11399 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11400                                             ((INSTANCE) == TIM2)  || \
11401                                             ((INSTANCE) == TIM3)  || \
11402                                             ((INSTANCE) == TIM4)  || \
11403                                             ((INSTANCE) == TIM8))
11404 
11405 /****************** TIM Instances : supporting repetition counter *************/
11406 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
11407                                                        ((INSTANCE) == TIM8)  || \
11408                                                        ((INSTANCE) == TIM15) || \
11409                                                        ((INSTANCE) == TIM16) || \
11410                                                        ((INSTANCE) == TIM17))
11411 
11412 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
11413 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
11414                                             ((INSTANCE) == TIM8))
11415 
11416 /******************* TIM Instances : Timer input XOR function *****************/
11417 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
11418                                             ((INSTANCE) == TIM2)   || \
11419                                             ((INSTANCE) == TIM3)   || \
11420                                             ((INSTANCE) == TIM4)   || \
11421                                             ((INSTANCE) == TIM8)   || \
11422                                             ((INSTANCE) == TIM15))
11423 
11424 /******************* TIM Instances : Timer input selection ********************/
11425 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
11426                                          ((INSTANCE) == TIM2)   || \
11427                                          ((INSTANCE) == TIM3)   || \
11428                                          ((INSTANCE) == TIM4)   || \
11429                                          ((INSTANCE) == TIM8)   || \
11430                                          ((INSTANCE) == TIM15)  || \
11431                                          ((INSTANCE) == TIM16)  || \
11432                                          ((INSTANCE) == TIM17))
11433 
11434 /****************** TIM Instances : Advanced timer instances *******************/
11435 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
11436                                                   ((INSTANCE) == TIM8))
11437 
11438 
11439 /****************** TIM Instances : supporting HSE/32 request instances *******************/
11440 #define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
11441                                                  ((INSTANCE) == TIM17))
11442 
11443 
11444 /******************** USART Instances : Synchronous mode **********************/
11445 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11446                                      ((INSTANCE) == USART2))
11447 
11448 /******************** UART Instances : Asynchronous mode **********************/
11449 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11450                                     ((INSTANCE) == USART2) || \
11451                                     ((INSTANCE) == UART4))
11452 
11453 /*********************** UART Instances : FIFO mode ***************************/
11454 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11455                                          ((INSTANCE) == USART2) || \
11456                                          ((INSTANCE) == UART4) || \
11457                                          ((INSTANCE) == LPUART1))
11458 
11459 /*********************** UART Instances : SPI Slave mode **********************/
11460 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11461                                               ((INSTANCE) == USART2))
11462 
11463 /****************** UART Instances : Auto Baud Rate detection ****************/
11464 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11465                                                             ((INSTANCE) == USART2) || \
11466                                                             ((INSTANCE) == UART4))
11467 
11468 /****************** UART Instances : Driver Enable *****************/
11469 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
11470                                                       ((INSTANCE) == USART2) || \
11471                                                       ((INSTANCE) == UART4)  || \
11472                                                       ((INSTANCE) == LPUART1))
11473 
11474 /******************** UART Instances : Half-Duplex mode **********************/
11475 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11476                                                  ((INSTANCE) == USART2) || \
11477                                                  ((INSTANCE) == UART4)  || \
11478                                                  ((INSTANCE) == LPUART1))
11479 
11480 /****************** UART Instances : Hardware Flow control ********************/
11481 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11482                                            ((INSTANCE) == USART2) || \
11483                                            ((INSTANCE) == UART4)  || \
11484                                            ((INSTANCE) == LPUART1))
11485 
11486 /******************** UART Instances : LIN mode **********************/
11487 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11488                                           ((INSTANCE) == USART2) || \
11489                                           ((INSTANCE) == UART4))
11490 
11491 /******************** UART Instances : Wake-up from Stop mode **********************/
11492 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11493                                                       ((INSTANCE) == USART2) || \
11494                                                       ((INSTANCE) == UART4)  || \
11495                                                       ((INSTANCE) == LPUART1))
11496 
11497 /*********************** UART Instances : IRDA mode ***************************/
11498 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11499                                     ((INSTANCE) == USART2) || \
11500                                     ((INSTANCE) == UART4))
11501 
11502 /********************* USART Instances : Smard card mode ***********************/
11503 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11504                                          ((INSTANCE) == USART2))
11505 
11506 /******************** LPUART Instance *****************************************/
11507 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
11508 
11509 /****************************** IWDG Instances ********************************/
11510 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11511 
11512 /****************************** WWDG Instances ********************************/
11513 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11514 
11515 
11516 
11517 /**
11518   * @}
11519   */
11520 
11521 
11522 /******************************************************************************/
11523 /*  For a painless codes migration between the STM32G4xx device product       */
11524 /*  lines, the aliases defined below are put in place to overcome the         */
11525 /*  differences in the interrupt handlers and IRQn definitions.               */
11526 /*  No need to update developed interrupt code when moving across             */
11527 /*  product lines within the same STM32G4 Family                              */
11528 /******************************************************************************/
11529 
11530 /* Aliases for __IRQn */
11531 #define TIM7_DAC_IRQn     TIM7_IRQn
11532 #define COMP4_5_6_IRQn    COMP4_IRQn
11533 
11534 /* Aliases for __IRQHandler */
11535 #define TIM7_DAC_IRQHandler     TIM7_IRQHandler
11536 #define COMP4_5_6_IRQHandler    COMP4_IRQHandler
11537 
11538 #ifdef __cplusplus
11539 }
11540 #endif /* __cplusplus */
11541 
11542 #endif /* __STM32G411xB_H */
11543 
11544 /**
11545   * @}
11546   */
11547 
11548   /**
11549   * @}
11550   */
11551