1 /**
2   ******************************************************************************
3   * @file    stm32g474xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32G474xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32g474xx
30   * @{
31   */
32 
33 #ifndef __STM32G474xx_H
34 #define __STM32G474xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32G4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
77 /******  STM32 specific Interrupt Numbers ***************************************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
80   RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                                    */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
97   USB_HP_IRQn                 = 19,     /*!< USB HP Interrupt                                                                   */
98   USB_LP_IRQn                 = 20,     /*!< USB LP  Interrupt                                                                  */
99   FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
100   FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
102   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
103   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
104   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                                            */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
120   USBWakeUp_IRQn              = 42,     /*!< USB Wakeup through EXTI line Interrupt                                             */
121   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
122   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
123   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
125   ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                                             */
126   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                                               */
127   LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
128   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                                              */
129   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                                              */
130   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
131   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                                             */
132   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
133   TIM7_DAC_IRQn               = 55,     /*!< TIM7 global and DAC2&4 underrun error  interrupts                                  */
134   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
135   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
136   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
137   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
138   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
139   ADC4_IRQn                   = 61,     /*!< ADC4 global Interrupt                                                              */
140   ADC5_IRQn                   = 62,     /*!< ADC5 global Interrupt                                                              */
141   UCPD1_IRQn                  = 63,     /*!< UCPD global Interrupt                                                              */
142   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
143   COMP4_5_6_IRQn              = 65,     /*!< COMP4, COMP5 and COMP6                                                             */
144   COMP7_IRQn                  = 66,     /*!< COMP7 Interrupt                                                                    */
145   HRTIM1_Master_IRQn          = 67,     /*!< HRTIM Master Timer global Interrupt                                                */
146   HRTIM1_TIMA_IRQn            = 68,     /*!< HRTIM Timer A global Interrupt                                                     */
147   HRTIM1_TIMB_IRQn            = 69,     /*!< HRTIM Timer B global Interrupt                                                     */
148   HRTIM1_TIMC_IRQn            = 70,     /*!< HRTIM Timer C global Interrupt                                                     */
149   HRTIM1_TIMD_IRQn            = 71,     /*!< HRTIM Timer D global Interrupt                                                     */
150   HRTIM1_TIME_IRQn            = 72,     /*!< HRTIM Timer E global Interrupt                                                     */
151   HRTIM1_FLT_IRQn             = 73,     /*!< HRTIM Fault global Interrupt                                                       */
152   HRTIM1_TIMF_IRQn            = 74,     /*!< HRTIM Timer F global Interrupt                                                     */
153   CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
154   SAI1_IRQn                   = 76,     /*!< Serial Audio Interface global interrupt                                            */
155   TIM20_BRK_IRQn              = 77,     /*!< TIM20 Break, Transition error and Index error Interrupt                            */
156   TIM20_UP_IRQn               = 78,     /*!< TIM20 Update interrupt                                                             */
157   TIM20_TRG_COM_IRQn          = 79,     /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt                   */
158   TIM20_CC_IRQn               = 80,     /*!< TIM20 Capture Compare interrupt                                                    */
159   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
160   I2C4_EV_IRQn                = 82,     /*!< I2C4 Event interrupt                                                               */
161   I2C4_ER_IRQn                = 83,     /*!< I2C4 Error interrupt                                                               */
162   SPI4_IRQn                   = 84,     /*!< SPI4 Event interrupt                                                               */
163   FDCAN2_IT0_IRQn             = 86,     /*!< FDCAN2 interrupt line 0 interrupt                                                  */
164   FDCAN2_IT1_IRQn             = 87,     /*!< FDCAN2 interrupt line 1 interrupt                                                  */
165   FDCAN3_IT0_IRQn             = 88,     /*!< FDCAN3 interrupt line 0 interrupt                                                  */
166   FDCAN3_IT1_IRQn             = 89,     /*!< FDCAN3 interrupt line 1 interrupt                                                  */
167   RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
168   LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
169   I2C3_EV_IRQn                = 92,     /*!< I2C3 Event Interrupt                                                               */
170   I2C3_ER_IRQn                = 93,     /*!< I2C3 Error interrupt                                                               */
171   DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
172   QUADSPI_IRQn                = 95,     /*!< QUADSPI interrupt                                                                  */
173   DMA1_Channel8_IRQn          = 96,     /*!< DMA1 Channel 8 interrupt                                                           */
174   DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
175   DMA2_Channel7_IRQn          = 98,     /*!< DMA2 Channel 7 interrupt                                                           */
176   DMA2_Channel8_IRQn          = 99,     /*!< DMA2 Channel 8 interrupt                                                           */
177   CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
178   FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
179 } IRQn_Type;
180 
181 /**
182   * @}
183   */
184 
185 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
186 #include "system_stm32g4xx.h"
187 #include <stdint.h>
188 
189 /** @addtogroup Peripheral_registers_structures
190   * @{
191   */
192 
193 /**
194   * @brief Analog to Digital Converter
195   */
196 
197 typedef struct
198 {
199   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
200   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
201   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
202   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
203   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
204   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
205   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
206        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
207   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
208   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
209   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
210        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
211   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
212   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
213   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
214   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
215   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
216        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
217        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
218   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
219        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
220   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
221   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
222   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
223   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
224        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
225   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
226   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
227   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
228   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
229        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
230   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
231   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
232        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
233        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
234   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
235   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
236        uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
237   __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
238 } ADC_TypeDef;
239 
240 typedef struct
241 {
242   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
243   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
244   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
245   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
246 } ADC_Common_TypeDef;
247 
248 /**
249   * @brief FD Controller Area Network
250   */
251 
252 typedef struct
253 {
254   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
255   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
256        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
257   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
258   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
259   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
260   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
261   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
262   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
263   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
264   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
265   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
266        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
267   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
268   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
269   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
270        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
271   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
272   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
273   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
274   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
275        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
276   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
277   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
278   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
279        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
280   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
281   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
282   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
283   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
284        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
285   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
286   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
287   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
288   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
289   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
290   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
291   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
292   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
293   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
294   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
295   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
296 } FDCAN_GlobalTypeDef;
297 
298 /**
299   * @brief FD Controller Area Network Configuration
300   */
301 
302 typedef struct
303 {
304   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
305 } FDCAN_Config_TypeDef;
306 
307 /**
308   * @brief Comparator
309   */
310 
311 typedef struct
312 {
313   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
314 } COMP_TypeDef;
315 
316 /**
317   * @brief CRC calculation unit
318   */
319 
320 typedef struct
321 {
322   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
323   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
324   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
325   uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
326   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
327   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
328 } CRC_TypeDef;
329 
330 /**
331   * @brief Clock Recovery System
332   */
333 typedef struct
334 {
335   __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
336   __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
337   __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
338   __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
339 } CRS_TypeDef;
340 
341 /**
342   * @brief Digital to Analog Converter
343   */
344 
345 typedef struct
346 {
347   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
348   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
349   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
350   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
351   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
352   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
353   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
354   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
355   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
356   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
357   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
358   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
359   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
360   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
361   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
362   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
363   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
364   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
365   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
366   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
367   __IO uint32_t RESERVED[2];
368   __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
369   __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
370   __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
371 } DAC_TypeDef;
372 
373 /**
374   * @brief Debug MCU
375   */
376 
377 typedef struct
378 {
379   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
380   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
381   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
382   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
383   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
384 } DBGMCU_TypeDef;
385 
386 /**
387   * @brief DMA Controller
388   */
389 
390 typedef struct
391 {
392   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
393   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
394   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
395   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
396 } DMA_Channel_TypeDef;
397 
398 typedef struct
399 {
400   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
401   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
402 } DMA_TypeDef;
403 
404 /**
405   * @brief DMA Multiplexer
406   */
407 
408 typedef struct
409 {
410   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
411 }DMAMUX_Channel_TypeDef;
412 
413 typedef struct
414 {
415   __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
416   __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
417 }DMAMUX_ChannelStatus_TypeDef;
418 
419 typedef struct
420 {
421   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
422 }DMAMUX_RequestGen_TypeDef;
423 
424 typedef struct
425 {
426   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
427   __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
428 }DMAMUX_RequestGenStatus_TypeDef;
429 
430 /**
431   * @brief External Interrupt/Event Controller
432   */
433 
434 typedef struct
435 {
436   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
437   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
438   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
439   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
440   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
441   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
442   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
443   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
444   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
445   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
446   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
447   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
448   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
449   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
450 } EXTI_TypeDef;
451 
452 /**
453   * @brief FLASH Registers
454   */
455 
456 typedef struct
457 {
458   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
459   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
460   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
461   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
462   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
463   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
464   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
465        uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
466   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
467   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
468   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
469   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
470   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
471        uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
472   __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
473   __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
474   __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
475   __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
476        uint32_t RESERVED3[7];     /*!< Reserved3,                                Address offset: 0x54 */
477   __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
478   __IO uint32_t SEC2R;            /*!< FLASH Securable memory register bank2,    Address offset: 0x74 */
479 } FLASH_TypeDef;
480 
481 /**
482   * @brief FMAC
483   */
484 typedef struct
485 {
486   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
487   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
488   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
489   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
490   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
491   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
492   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
493   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
494 } FMAC_TypeDef;
495 
496 /**
497   * @brief Flexible Memory Controller
498   */
499 
500 typedef struct
501 {
502   __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
503   __IO uint32_t PCSCNTR;     /*!< PSRAM chip-select counter register,                                               Address offset:    0x20 */
504 } FMC_Bank1_TypeDef;
505 
506 /**
507   * @brief Flexible Memory Controller Bank1E
508   */
509 
510 typedef struct
511 {
512   __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
513 } FMC_Bank1E_TypeDef;
514 
515 /**
516   * @brief Flexible Memory Controller Bank3
517   */
518 
519 typedef struct
520 {
521   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
522   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
523   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
524   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
525   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
526   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
527 } FMC_Bank3_TypeDef;
528 
529 /**
530   * @brief General Purpose I/O
531   */
532 
533 typedef struct
534 {
535   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
536   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
537   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
538   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
539   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
540   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
541   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
542   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
543   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
544   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
545 } GPIO_TypeDef;
546 
547 /**
548   * @brief Inter-integrated Circuit Interface
549   */
550 
551 typedef struct
552 {
553   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
554   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
555   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
556   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
557   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
558   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
559   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
560   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
561   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
562   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
563   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
564 } I2C_TypeDef;
565 
566 /**
567   * @brief Independent WATCHDOG
568   */
569 
570 typedef struct
571 {
572   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
573   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
574   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
575   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
576   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
577 } IWDG_TypeDef;
578 
579 /**
580   * @brief LPTIMER
581   */
582 
583 typedef struct
584 {
585   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
586   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
587   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
588   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
589   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
590   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
591   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
592   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
593   __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
594 } LPTIM_TypeDef;
595 
596 /**
597   * @brief Operational Amplifier (OPAMP)
598   */
599 
600 typedef struct
601 {
602   __IO uint32_t CSR;           /*!< OPAMP control/status register,                     Address offset: 0x00 */
603   __IO uint32_t RESERVED[5];   /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
604   __IO uint32_t TCMR;          /*!< OPAMP timer controlled mux mode register,          Address offset: 0x18 */
605 } OPAMP_TypeDef;
606 
607 /**
608   * @brief Power Control
609   */
610 
611 typedef struct
612 {
613   __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
614   __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
615   __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
616   __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
617   __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
618   __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
619   __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
620   uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
621   __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
622   __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
623   __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
624   __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
625   __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
626   __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
627   __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
628   __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
629   __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
630   __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
631   __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
632   __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
633   __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
634   __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
635   uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
636   __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
637 } PWR_TypeDef;
638 
639 /**
640   * @brief QUAD Serial Peripheral Interface
641   */
642 
643 typedef struct
644 {
645   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
646   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
647   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
648   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
649   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
650   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
651   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
652   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
653   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
654   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
655   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
656   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
657   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
658 } QUADSPI_TypeDef;
659 
660 /**
661   * @brief Reset and Clock Control
662   */
663 
664 typedef struct
665 {
666   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
667   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
668   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
669   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
670   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
671   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
672   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
673   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
674   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
675   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
676   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
677   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
678   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
679   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
680   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
681   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
682   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
683   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
684   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
685   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
686   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
687   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
688   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
689   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
690   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
691   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
692   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
693   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
694   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
695   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
696   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
697   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
698   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
699   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
700   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
701   uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
702   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
703   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
704   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
705   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
706 } RCC_TypeDef;
707 
708 /**
709   * @brief Real-Time Clock
710   */
711 /*
712 * @brief Specific device feature definitions
713 */
714 #define RTC_TAMP_INT_6_SUPPORT
715 #define RTC_TAMP_INT_NB        4u
716 
717 #define RTC_TAMP_NB            3u
718 #define RTC_BACKUP_NB          32u
719 
720 
721 typedef struct
722 {
723   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
724   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
725   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
726   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
727   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
728   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
729   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
730        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
731        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
732   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
733   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
734   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
735   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
736   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
737   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
738        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
739   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
740   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
741   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
742   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
743   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
744   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
745        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
746   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
747 } RTC_TypeDef;
748 
749 /**
750   * @brief Tamper and backup registers
751   */
752 
753 typedef struct
754 {
755   __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
756   __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
757        uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
758   __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
759        uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
760        uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
761   __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
762   __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
763   __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
764        uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
765   __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
766        uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
767   __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
768   __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
769   __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
770   __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
771   __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
772   __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
773   __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
774   __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
775   __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
776   __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
777   __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
778   __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
779   __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
780   __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
781   __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
782   __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
783   __IO uint32_t BKP16R;                  /*!< TAMP backup register 16,                Address offset: 0x140 */
784   __IO uint32_t BKP17R;                  /*!< TAMP backup register 17,                Address offset: 0x144 */
785   __IO uint32_t BKP18R;                  /*!< TAMP backup register 18,                Address offset: 0x148 */
786   __IO uint32_t BKP19R;                  /*!< TAMP backup register 19,                Address offset: 0x14C */
787   __IO uint32_t BKP20R;                  /*!< TAMP backup register 20,                Address offset: 0x150 */
788   __IO uint32_t BKP21R;                  /*!< TAMP backup register 21,                Address offset: 0x154 */
789   __IO uint32_t BKP22R;                  /*!< TAMP backup register 22,                Address offset: 0x158 */
790   __IO uint32_t BKP23R;                  /*!< TAMP backup register 23,                Address offset: 0x15C */
791   __IO uint32_t BKP24R;                  /*!< TAMP backup register 24,                Address offset: 0x160 */
792   __IO uint32_t BKP25R;                  /*!< TAMP backup register 25,                Address offset: 0x164 */
793   __IO uint32_t BKP26R;                  /*!< TAMP backup register 26,                Address offset: 0x168 */
794   __IO uint32_t BKP27R;                  /*!< TAMP backup register 27,                Address offset: 0x16C */
795   __IO uint32_t BKP28R;                  /*!< TAMP backup register 28,                Address offset: 0x170 */
796   __IO uint32_t BKP29R;                  /*!< TAMP backup register 29,                Address offset: 0x174 */
797   __IO uint32_t BKP30R;                  /*!< TAMP backup register 30,                Address offset: 0x178 */
798   __IO uint32_t BKP31R;                  /*!< TAMP backup register 31,                Address offset: 0x17C */
799 } TAMP_TypeDef;
800 
801 /**
802   * @brief Serial Audio Interface
803   */
804 
805 typedef struct
806 {
807   uint32_t      RESERVED[17]; /*!< Reserved,                                 Address offset: 0x00 to 0x40 */
808   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
809   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
810 } SAI_TypeDef;
811 
812 typedef struct
813 {
814   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
815   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
816   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
817   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
818   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
819   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
820   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
821   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
822 } SAI_Block_TypeDef;
823 
824 /**
825   * @brief Serial Peripheral Interface
826   */
827 
828 typedef struct
829 {
830   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
831   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
832   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
833   __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
834   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
835   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
836   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
837   __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
838   __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
839 } SPI_TypeDef;
840 
841 /**
842   * @brief System configuration controller
843   */
844 
845 typedef struct
846 {
847   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
848   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
849   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
850   __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
851   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
852   __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
853   __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
854 } SYSCFG_TypeDef;
855 
856 /**
857   * @brief TIM
858   */
859 
860 typedef struct
861 {
862   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
863   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
864   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
865   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
866   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
867   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
868   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
869   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
870   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
871   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
872   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
873   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
874   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
875   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
876   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
877   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
878   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
879   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
880   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
881   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
882   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
883   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
884   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
885   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
886   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
887   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
888   __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
889        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
890   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
891   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
892 } TIM_TypeDef;
893 
894 /**
895   * @brief Universal Synchronous Asynchronous Receiver Transmitter
896   */
897 typedef struct
898 {
899   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
900   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
901   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
902   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
903   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
904   __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
905   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
906   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
907   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
908   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
909   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
910   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
911 } USART_TypeDef;
912 
913 /**
914   * @brief Universal Serial Bus Full Speed Device
915   */
916 
917 typedef struct
918 {
919   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
920   __IO uint16_t RESERVED0;       /*!< Reserved */
921   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
922   __IO uint16_t RESERVED1;       /*!< Reserved */
923   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
924   __IO uint16_t RESERVED2;       /*!< Reserved */
925   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
926   __IO uint16_t RESERVED3;       /*!< Reserved */
927   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
928   __IO uint16_t RESERVED4;       /*!< Reserved */
929   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
930   __IO uint16_t RESERVED5;       /*!< Reserved */
931   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
932   __IO uint16_t RESERVED6;       /*!< Reserved */
933   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
934   __IO uint16_t RESERVED7[17];   /*!< Reserved */
935   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
936   __IO uint16_t RESERVED8;       /*!< Reserved */
937   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
938   __IO uint16_t RESERVED9;       /*!< Reserved */
939   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
940   __IO uint16_t RESERVEDA;       /*!< Reserved */
941   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
942   __IO uint16_t RESERVEDB;       /*!< Reserved */
943   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
944   __IO uint16_t RESERVEDC;       /*!< Reserved */
945   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
946   __IO uint16_t RESERVEDD;       /*!< Reserved */
947   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
948   __IO uint16_t RESERVEDE;       /*!< Reserved */
949 } USB_TypeDef;
950 
951 /**
952   * @brief VREFBUF
953   */
954 
955 typedef struct
956 {
957   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
958   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
959 } VREFBUF_TypeDef;
960 
961 /**
962   * @brief Window WATCHDOG
963   */
964 
965 typedef struct
966 {
967   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
968   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
969   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
970 } WWDG_TypeDef;
971 
972 
973 /**
974   * @brief RNG
975   */
976 typedef struct
977 {
978   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
979   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
980   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
981 } RNG_TypeDef;
982 
983 /**
984   * @brief CORDIC
985   */
986 
987 typedef struct
988 {
989   __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
990   __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
991   __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
992 } CORDIC_TypeDef;
993 
994 /**
995   * @brief UCPD
996   */
997 
998 typedef struct
999 {
1000   __IO uint32_t CFG1;          /*!< UCPD configuration register 1,             Address offset: 0x00 */
1001   __IO uint32_t CFG2;          /*!< UCPD configuration register 2,             Address offset: 0x04 */
1002   __IO uint32_t RESERVED0;     /*!< UCPD reserved register,                    Address offset: 0x08 */
1003   __IO uint32_t CR;            /*!< UCPD control register,                     Address offset: 0x0C */
1004   __IO uint32_t IMR;           /*!< UCPD interrupt mask register,              Address offset: 0x10 */
1005   __IO uint32_t SR;            /*!< UCPD status register,                      Address offset: 0x14 */
1006   __IO uint32_t ICR;           /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
1007   __IO uint32_t TX_ORDSET;     /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
1008   __IO uint32_t TX_PAYSZ;      /*!< UCPD Tx payload size register,             Address offset: 0x20 */
1009   __IO uint32_t TXDR;          /*!< UCPD Tx data register,                     Address offset: 0x24 */
1010   __IO uint32_t RX_ORDSET;     /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
1011   __IO uint32_t RX_PAYSZ;      /*!< UCPD Rx payload size register,             Address offset: 0x2C */
1012   __IO uint32_t RXDR;          /*!< UCPD Rx data register,                     Address offset: 0x30 */
1013   __IO uint32_t RX_ORDEXT1;    /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
1014   __IO uint32_t RX_ORDEXT2;    /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
1015 } UCPD_TypeDef;
1016 
1017 /**
1018   * @brief High resolution Timer (HRTIM)
1019   */
1020 
1021 #define c7amba_hrtim1_v2_0
1022 
1023 /* HRTIM master registers definition */
1024 typedef struct
1025 {
1026   __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
1027   __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
1028   __IO uint32_t MICR;           /*!< HRTIM Master Timer interrupt clear register,              Address offset: 0x08 */
1029   __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
1030   __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
1031   __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
1032   __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
1033   __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
1034   uint32_t      RESERVED0;     /*!< Reserved,                                                                0x20 */
1035   __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
1036   __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
1037   __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
1038   uint32_t      RESERVED1[20];  /*!< Reserved,                                                0x30..0x7C */
1039 }HRTIM_Master_TypeDef;
1040 
1041 /* HRTIM Timer A to F registers definition */
1042 typedef struct
1043 {
1044   __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00  */
1045   __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04  */
1046   __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08  */
1047   __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C  */
1048   __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10  */
1049   __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14  */
1050   __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18  */
1051   __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C  */
1052   __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20  */
1053   __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24  */
1054   __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28  */
1055   __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C  */
1056   __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30  */
1057   __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
1058   __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
1059   __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
1060   __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
1061   __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
1062   __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
1063   __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
1064   __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
1065   __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
1066   __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
1067   __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
1068   __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
1069   __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
1070   __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
1071   __IO uint32_t TIMxCR2;    /*!< HRTIM Timerx Control register 2,                            Address offset: 0x6C */
1072   __IO uint32_t EEFxR3;     /*!< HRTIM Timerx external event filtering 3 register,           Address offset: 0x70 */
1073   uint32_t   RESERVED0[3];  /*!< Reserved,                                                   0x74..0x7C */
1074 }HRTIM_Timerx_TypeDef;
1075 
1076 /* HRTIM common register definition */
1077 typedef struct
1078 {
1079   __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
1080   __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
1081   __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
1082   __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
1083   __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
1084   __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
1085   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
1086   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
1087   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
1088   __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
1089   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
1090   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
1091   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
1092   __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
1093   __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
1094   __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
1095   __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
1096   __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
1097   __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
1098   __IO uint32_t DLLCR;      /*!< HRTIM DLL control register,                                 Address offset: 0x4C */
1099   __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
1100   __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
1101   __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
1102   __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
1103   __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
1104   __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
1105   __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
1106   __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
1107   __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
1108   __IO uint32_t BDTFUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x74 */
1109   __IO uint32_t ADCER;      /*!< HRTIM ADC Extended Trigger register,                        Address offset: 0x78 */
1110   __IO uint32_t ADCUR;      /*!< HRTIM ADC Trigger Update register,                          Address offset: 0x7C */
1111   __IO uint32_t ADCPS1;     /*!< HRTIM ADC Post Scaler Register 1,                           Address offset: 0x80 */
1112   __IO uint32_t ADCPS2;     /*!< HRTIM ADC Post Scaler Register 2,                           Address offset: 0x84 */
1113   __IO uint32_t FLTINR3;    /*!< HRTIM Fault input register3,                                Address offset: 0x88 */
1114   __IO uint32_t FLTINR4;    /*!< HRTIM Fault input register4,                                Address offset: 0x8C */
1115 }HRTIM_Common_TypeDef;
1116 
1117 /* HRTIM  register definition */
1118 typedef struct {
1119   HRTIM_Master_TypeDef sMasterRegs;
1120   HRTIM_Timerx_TypeDef sTimerxRegs[6];
1121   HRTIM_Common_TypeDef sCommonRegs;
1122 }HRTIM_TypeDef;
1123 
1124 /**
1125   * @}
1126   */
1127 
1128 /** @addtogroup Peripheral_memory_map
1129   * @{
1130   */
1131 
1132 #define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
1133 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
1134 #define SRAM2_BASE            (0x20014000UL) /*!< SRAM2(16 KB) base address */
1135 #define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
1136 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
1137 #define FMC_BASE              (0x60000000UL) /*!< FMC base address */
1138 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
1139 
1140 #define FMC_R_BASE            (0xA0000000UL) /*!< FMC  control registers base address */
1141 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
1142 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
1143 #define SRAM2_BB_BASE         (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
1144 #define CCMSRAM_BB_BASE       (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
1145 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
1146 /* Legacy defines */
1147 #define SRAM_BASE             SRAM1_BASE
1148 #define SRAM_BB_BASE          SRAM1_BB_BASE
1149 
1150 #define SRAM1_SIZE_MAX        (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
1151 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
1152 #define CCMSRAM_SIZE          (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
1153 
1154 /*!< Peripheral memory map */
1155 #define APB1PERIPH_BASE        PERIPH_BASE
1156 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1157 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1158 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
1159 
1160 #define FMC_BANK1             FMC_BASE
1161 #define FMC_BANK1_1           FMC_BANK1
1162 #define FMC_BANK1_2           (FMC_BANK1 + 0x04000000UL)
1163 #define FMC_BANK1_3           (FMC_BANK1 + 0x08000000UL)
1164 #define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000UL)
1165 #define FMC_BANK3             (FMC_BASE  + 0x20000000UL)
1166 
1167 /*!< APB1 peripherals */
1168 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1169 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1170 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1171 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1172 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1173 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1174 #define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
1175 #define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
1176 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1177 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1178 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1179 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1180 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1181 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1182 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1183 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1184 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1185 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1186 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1187 #define USB_BASE              (APB1PERIPH_BASE + 0x5C00UL)  /*!< USB_IP Peripheral Registers base address */
1188 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x6000UL)  /*!< USB_IP Packet Memory Area base address */
1189 #define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
1190 #define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
1191 #define FDCAN2_BASE           (APB1PERIPH_BASE + 0x6800UL)
1192 #define FDCAN3_BASE           (APB1PERIPH_BASE + 0x6C00UL)
1193 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1194 #define I2C3_BASE             (APB1PERIPH_BASE + 0x7800UL)
1195 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
1196 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
1197 #define I2C4_BASE             (APB1PERIPH_BASE + 0x8400UL)
1198 #define UCPD1_BASE            (APB1PERIPH_BASE + 0xA000UL)
1199 #define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
1200 
1201 /*!< APB2 peripherals */
1202 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
1203 #define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
1204 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
1205 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
1206 #define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
1207 #define COMP4_BASE            (APB2PERIPH_BASE + 0x020CUL)
1208 #define COMP5_BASE            (APB2PERIPH_BASE + 0x0210UL)
1209 #define COMP6_BASE            (APB2PERIPH_BASE + 0x0214UL)
1210 #define COMP7_BASE            (APB2PERIPH_BASE + 0x0218UL)
1211 #define OPAMP_BASE            (APB2PERIPH_BASE + 0x0300UL)
1212 #define OPAMP1_BASE           (APB2PERIPH_BASE + 0x0300UL)
1213 #define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0304UL)
1214 #define OPAMP3_BASE           (APB2PERIPH_BASE + 0x0308UL)
1215 #define OPAMP4_BASE           (APB2PERIPH_BASE + 0x030CUL)
1216 #define OPAMP5_BASE           (APB2PERIPH_BASE + 0x0310UL)
1217 #define OPAMP6_BASE           (APB2PERIPH_BASE + 0x0314UL)
1218 
1219 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
1220 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1221 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1222 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
1223 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
1224 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1225 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
1226 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
1227 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
1228 #define TIM20_BASE            (APB2PERIPH_BASE + 0x5000UL)
1229 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
1230 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
1231 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
1232 #define HRTIM1_BASE           (APB2PERIPH_BASE + 0x6800UL)
1233 #define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x0080UL)
1234 #define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x0100UL)
1235 #define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x0180UL)
1236 #define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x0200UL)
1237 #define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x0280UL)
1238 #define HRTIM1_TIMF_BASE      (HRTIM1_BASE + 0x0300UL)
1239 #define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x0380UL)
1240 
1241 /*!< AHB1 peripherals */
1242 #define DMA1_BASE             (AHB1PERIPH_BASE)
1243 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
1244 #define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
1245 #define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
1246 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
1247 #define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
1248 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
1249 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1250 
1251 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
1252 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
1253 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
1254 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
1255 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
1256 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
1257 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
1258 #define DMA1_Channel8_BASE    (DMA1_BASE + 0x0094UL)
1259 
1260 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
1261 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
1262 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
1263 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
1264 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
1265 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
1266 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
1267 #define DMA2_Channel8_BASE    (DMA2_BASE + 0x0094UL)
1268 
1269 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
1270 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
1271 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
1272 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
1273 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
1274 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
1275 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
1276 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
1277 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
1278 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
1279 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
1280 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
1281 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
1282 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
1283 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
1284 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
1285 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
1286 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
1287 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
1288 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
1289 
1290 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
1291 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
1292 
1293 /*!< AHB2 peripherals */
1294 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
1295 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
1296 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
1297 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
1298 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
1299 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
1300 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
1301 
1302 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
1303 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
1304 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
1305 #define ADC3_BASE             (AHB2PERIPH_BASE + 0x08000400UL)
1306 #define ADC4_BASE             (AHB2PERIPH_BASE + 0x08000500UL)
1307 #define ADC5_BASE             (AHB2PERIPH_BASE + 0x08000600UL)
1308 #define ADC345_COMMON_BASE    (AHB2PERIPH_BASE + 0x08000700UL)
1309 
1310 #define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
1311 #define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
1312 #define DAC2_BASE             (AHB2PERIPH_BASE + 0x08000C00UL)
1313 #define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
1314 #define DAC4_BASE             (AHB2PERIPH_BASE + 0x08001400UL)
1315 
1316 /*!< FMC Banks registers base  address */
1317 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1318 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1319 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
1320 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
1321 /* Debug MCU registers base address */
1322 #define DBGMCU_BASE           (0xE0042000UL)
1323 
1324 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
1325 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
1326 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
1327 /**
1328   * @}
1329   */
1330 
1331 /** @addtogroup Peripheral_declaration
1332   * @{
1333   */
1334 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1335 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1336 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1337 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1338 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1339 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1340 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1341 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
1342 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1343 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1344 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1345 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1346 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1347 #define USART2              ((USART_TypeDef *) USART2_BASE)
1348 #define USART3              ((USART_TypeDef *) USART3_BASE)
1349 #define UART4               ((USART_TypeDef *) UART4_BASE)
1350 #define UART5               ((USART_TypeDef *) UART5_BASE)
1351 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1352 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1353 #define USB                 ((USB_TypeDef *) USB_BASE)
1354 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1355 #define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1356 #define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1357 #define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
1358 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1359 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1360 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1361 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1362 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1363 #define UCPD1              ((UCPD_TypeDef *) UCPD1_BASE)
1364 
1365 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1366 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1367 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1368 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1369 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
1370 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
1371 #define COMP5               ((COMP_TypeDef *) COMP5_BASE)
1372 #define COMP6               ((COMP_TypeDef *) COMP6_BASE)
1373 #define COMP7               ((COMP_TypeDef *) COMP7_BASE)
1374 
1375 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
1376 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1377 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
1378 #define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
1379 #define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
1380 #define OPAMP5              ((OPAMP_TypeDef *) OPAMP5_BASE)
1381 #define OPAMP6              ((OPAMP_TypeDef *) OPAMP6_BASE)
1382 
1383 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1384 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1385 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1386 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1387 #define USART1              ((USART_TypeDef *) USART1_BASE)
1388 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1389 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1390 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1391 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
1392 #define TIM20               ((TIM_TypeDef *) TIM20_BASE)
1393 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1394 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1395 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1396 #define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
1397 #define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
1398 #define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
1399 #define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
1400 #define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
1401 #define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
1402 #define HRTIM1_TIMF         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE)
1403 #define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
1404 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1405 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1406 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1407 #define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
1408 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1409 #define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
1410 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1411 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1412 
1413 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1414 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1415 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1416 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1417 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1418 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1419 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1420 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1421 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1422 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1423 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1424 #define ADC4                ((ADC_TypeDef *) ADC4_BASE)
1425 #define ADC5                ((ADC_TypeDef *) ADC5_BASE)
1426 #define ADC345_COMMON       ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1427 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1428 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1429 #define DAC2                ((DAC_TypeDef *) DAC2_BASE)
1430 #define DAC3                ((DAC_TypeDef *) DAC3_BASE)
1431 #define DAC4                ((DAC_TypeDef *) DAC4_BASE)
1432 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1433 
1434 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1435 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1436 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1437 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1438 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1439 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1440 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1441 #define DMA1_Channel8       ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1442 
1443 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1444 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1445 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1446 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1447 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1448 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1449 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1450 #define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1451 
1452 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1453 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1454 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1455 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1456 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1457 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1458 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1459 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1460 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1461 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1462 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1463 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1464 #define DMAMUX1_Channel12   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1465 #define DMAMUX1_Channel13   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1466 #define DMAMUX1_Channel14   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1467 #define DMAMUX1_Channel15   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1468 
1469 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1470 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1471 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1472 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1473 
1474 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1475 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1476 
1477 #define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1478 #define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1479 #define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1480 
1481 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1482 
1483 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1484 
1485 /**
1486   * @}
1487   */
1488 
1489 /** @addtogroup Exported_constants
1490   * @{
1491   */
1492 
1493   /** @addtogroup Hardware_Constant_Definition
1494     * @{
1495     */
1496 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1497 
1498   /**
1499     * @}
1500     */
1501 
1502 /** @addtogroup Peripheral_Registers_Bits_Definition
1503   * @{
1504   */
1505 
1506 /******************************************************************************/
1507 /*                         Peripheral Registers_Bits_Definition               */
1508 /******************************************************************************/
1509 
1510 /******************************************************************************/
1511 /*                                                                            */
1512 /*                        Analog to Digital Converter                         */
1513 /*                                                                            */
1514 /******************************************************************************/
1515 
1516 /*
1517  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
1518  */
1519 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1520 
1521 /********************  Bit definition for ADC_ISR register  *******************/
1522 #define ADC_ISR_ADRDY_Pos              (0U)
1523 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1524 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1525 #define ADC_ISR_EOSMP_Pos              (1U)
1526 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1527 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1528 #define ADC_ISR_EOC_Pos                (2U)
1529 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1530 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1531 #define ADC_ISR_EOS_Pos                (3U)
1532 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1533 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1534 #define ADC_ISR_OVR_Pos                (4U)
1535 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1536 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1537 #define ADC_ISR_JEOC_Pos               (5U)
1538 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1539 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1540 #define ADC_ISR_JEOS_Pos               (6U)
1541 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1542 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1543 #define ADC_ISR_AWD1_Pos               (7U)
1544 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1545 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1546 #define ADC_ISR_AWD2_Pos               (8U)
1547 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1548 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1549 #define ADC_ISR_AWD3_Pos               (9U)
1550 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1551 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1552 #define ADC_ISR_JQOVF_Pos              (10U)
1553 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1554 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1555 
1556 /********************  Bit definition for ADC_IER register  *******************/
1557 #define ADC_IER_ADRDYIE_Pos            (0U)
1558 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1559 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1560 #define ADC_IER_EOSMPIE_Pos            (1U)
1561 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1562 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1563 #define ADC_IER_EOCIE_Pos              (2U)
1564 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1565 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1566 #define ADC_IER_EOSIE_Pos              (3U)
1567 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1568 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1569 #define ADC_IER_OVRIE_Pos              (4U)
1570 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1571 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1572 #define ADC_IER_JEOCIE_Pos             (5U)
1573 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1574 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1575 #define ADC_IER_JEOSIE_Pos             (6U)
1576 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1577 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1578 #define ADC_IER_AWD1IE_Pos             (7U)
1579 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1580 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1581 #define ADC_IER_AWD2IE_Pos             (8U)
1582 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1583 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1584 #define ADC_IER_AWD3IE_Pos             (9U)
1585 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1586 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1587 #define ADC_IER_JQOVFIE_Pos            (10U)
1588 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1589 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1590 
1591 /********************  Bit definition for ADC_CR register  ********************/
1592 #define ADC_CR_ADEN_Pos                (0U)
1593 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1594 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1595 #define ADC_CR_ADDIS_Pos               (1U)
1596 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1597 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1598 #define ADC_CR_ADSTART_Pos             (2U)
1599 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1600 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1601 #define ADC_CR_JADSTART_Pos            (3U)
1602 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1603 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1604 #define ADC_CR_ADSTP_Pos               (4U)
1605 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1606 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1607 #define ADC_CR_JADSTP_Pos              (5U)
1608 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1609 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1610 #define ADC_CR_ADVREGEN_Pos            (28U)
1611 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1612 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1613 #define ADC_CR_DEEPPWD_Pos             (29U)
1614 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1615 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1616 #define ADC_CR_ADCALDIF_Pos            (30U)
1617 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1618 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1619 #define ADC_CR_ADCAL_Pos               (31U)
1620 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1621 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1622 
1623 /********************  Bit definition for ADC_CFGR register  ******************/
1624 #define ADC_CFGR_DMAEN_Pos             (0U)
1625 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1626 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1627 #define ADC_CFGR_DMACFG_Pos            (1U)
1628 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1629 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1630 
1631 #define ADC_CFGR_RES_Pos               (3U)
1632 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1633 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1634 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1635 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1636 
1637 #define ADC_CFGR_EXTSEL_Pos            (5U)
1638 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1639 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1640 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1641 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1642 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1643 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1644 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1645 
1646 #define ADC_CFGR_EXTEN_Pos             (10U)
1647 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1648 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1649 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1650 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1651 
1652 #define ADC_CFGR_OVRMOD_Pos            (12U)
1653 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1654 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1655 #define ADC_CFGR_CONT_Pos              (13U)
1656 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1657 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1658 #define ADC_CFGR_AUTDLY_Pos            (14U)
1659 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1660 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1661 #define ADC_CFGR_ALIGN_Pos             (15U)
1662 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1663 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1664 #define ADC_CFGR_DISCEN_Pos            (16U)
1665 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1666 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1667 
1668 #define ADC_CFGR_DISCNUM_Pos           (17U)
1669 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1670 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1671 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1672 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1673 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1674 
1675 #define ADC_CFGR_JDISCEN_Pos           (20U)
1676 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1677 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1678 #define ADC_CFGR_JQM_Pos               (21U)
1679 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1680 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1681 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1682 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1683 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1684 #define ADC_CFGR_AWD1EN_Pos            (23U)
1685 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1686 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1687 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1688 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1689 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1690 #define ADC_CFGR_JAUTO_Pos             (25U)
1691 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1692 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1693 
1694 #define ADC_CFGR_AWD1CH_Pos            (26U)
1695 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1696 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1697 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1698 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1699 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1700 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1701 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1702 
1703 #define ADC_CFGR_JQDIS_Pos             (31U)
1704 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1705 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1706 
1707 /********************  Bit definition for ADC_CFGR2 register  *****************/
1708 #define ADC_CFGR2_ROVSE_Pos            (0U)
1709 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1710 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1711 #define ADC_CFGR2_JOVSE_Pos            (1U)
1712 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1713 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1714 
1715 #define ADC_CFGR2_OVSR_Pos             (2U)
1716 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1717 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1718 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1719 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1720 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1721 
1722 #define ADC_CFGR2_OVSS_Pos             (5U)
1723 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1724 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1725 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1726 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1727 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1728 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1729 
1730 #define ADC_CFGR2_TROVS_Pos            (9U)
1731 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1732 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1733 #define ADC_CFGR2_ROVSM_Pos            (10U)
1734 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1735 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1736 
1737 #define ADC_CFGR2_GCOMP_Pos            (16U)
1738 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1739 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1740 
1741 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1742 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1743 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1744 #define ADC_CFGR2_BULB_Pos             (26U)
1745 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1746 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1747 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1748 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1749 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1750 
1751 /********************  Bit definition for ADC_SMPR1 register  *****************/
1752 #define ADC_SMPR1_SMP0_Pos             (0U)
1753 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1754 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1755 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1756 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1757 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1758 
1759 #define ADC_SMPR1_SMP1_Pos             (3U)
1760 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1761 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1762 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1763 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1764 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1765 
1766 #define ADC_SMPR1_SMP2_Pos             (6U)
1767 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1768 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1769 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1770 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1771 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1772 
1773 #define ADC_SMPR1_SMP3_Pos             (9U)
1774 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1775 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1776 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1777 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1778 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1779 
1780 #define ADC_SMPR1_SMP4_Pos             (12U)
1781 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1782 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1783 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1784 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1785 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1786 
1787 #define ADC_SMPR1_SMP5_Pos             (15U)
1788 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1789 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1790 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1791 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1792 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1793 
1794 #define ADC_SMPR1_SMP6_Pos             (18U)
1795 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1796 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1797 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1798 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1799 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1800 
1801 #define ADC_SMPR1_SMP7_Pos             (21U)
1802 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1803 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1804 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1805 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1806 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1807 
1808 #define ADC_SMPR1_SMP8_Pos             (24U)
1809 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1810 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1811 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1812 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1813 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1814 
1815 #define ADC_SMPR1_SMP9_Pos             (27U)
1816 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1817 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1818 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1819 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1820 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1821 
1822 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1823 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1824 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1825 
1826 /********************  Bit definition for ADC_SMPR2 register  *****************/
1827 #define ADC_SMPR2_SMP10_Pos            (0U)
1828 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1829 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1830 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1831 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1832 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1833 
1834 #define ADC_SMPR2_SMP11_Pos            (3U)
1835 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1836 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1837 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1838 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1839 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1840 
1841 #define ADC_SMPR2_SMP12_Pos            (6U)
1842 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1843 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1844 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1845 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1846 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1847 
1848 #define ADC_SMPR2_SMP13_Pos            (9U)
1849 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1850 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1851 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1852 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1853 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1854 
1855 #define ADC_SMPR2_SMP14_Pos            (12U)
1856 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1857 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1858 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1859 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1860 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1861 
1862 #define ADC_SMPR2_SMP15_Pos            (15U)
1863 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1864 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1865 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1866 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1867 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1868 
1869 #define ADC_SMPR2_SMP16_Pos            (18U)
1870 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1871 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1872 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1873 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1874 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1875 
1876 #define ADC_SMPR2_SMP17_Pos            (21U)
1877 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1878 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1879 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1880 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1881 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1882 
1883 #define ADC_SMPR2_SMP18_Pos            (24U)
1884 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1885 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1886 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1887 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1888 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1889 
1890 /********************  Bit definition for ADC_TR1 register  *******************/
1891 #define ADC_TR1_LT1_Pos                (0U)
1892 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1893 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1894 
1895 #define ADC_TR1_AWDFILT_Pos            (12U)
1896 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
1897 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
1898 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
1899 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
1900 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
1901 
1902 #define ADC_TR1_HT1_Pos                (16U)
1903 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1904 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
1905 
1906 /********************  Bit definition for ADC_TR2 register  *******************/
1907 #define ADC_TR2_LT2_Pos                (0U)
1908 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1909 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1910 
1911 #define ADC_TR2_HT2_Pos                (16U)
1912 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1913 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1914 
1915 /********************  Bit definition for ADC_TR3 register  *******************/
1916 #define ADC_TR3_LT3_Pos                (0U)
1917 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1918 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1919 
1920 #define ADC_TR3_HT3_Pos                (16U)
1921 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1922 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1923 
1924 /********************  Bit definition for ADC_SQR1 register  ******************/
1925 #define ADC_SQR1_L_Pos                 (0U)
1926 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1927 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1928 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1929 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1930 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1931 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1932 
1933 #define ADC_SQR1_SQ1_Pos               (6U)
1934 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1935 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1936 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1937 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1938 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1939 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1940 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1941 
1942 #define ADC_SQR1_SQ2_Pos               (12U)
1943 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1944 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1945 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1946 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1947 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1948 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1949 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1950 
1951 #define ADC_SQR1_SQ3_Pos               (18U)
1952 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1953 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1954 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1955 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1956 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1957 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1958 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1959 
1960 #define ADC_SQR1_SQ4_Pos               (24U)
1961 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1962 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1963 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1964 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1965 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1966 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1967 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1968 
1969 /********************  Bit definition for ADC_SQR2 register  ******************/
1970 #define ADC_SQR2_SQ5_Pos               (0U)
1971 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1972 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1973 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1974 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1975 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1976 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1977 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1978 
1979 #define ADC_SQR2_SQ6_Pos               (6U)
1980 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1981 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1982 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1983 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1984 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1985 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1986 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1987 
1988 #define ADC_SQR2_SQ7_Pos               (12U)
1989 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1990 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1991 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1992 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1993 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1994 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1995 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1996 
1997 #define ADC_SQR2_SQ8_Pos               (18U)
1998 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1999 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
2000 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
2001 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
2002 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
2003 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
2004 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
2005 
2006 #define ADC_SQR2_SQ9_Pos               (24U)
2007 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
2008 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
2009 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
2010 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
2011 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
2012 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
2013 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
2014 
2015 /********************  Bit definition for ADC_SQR3 register  ******************/
2016 #define ADC_SQR3_SQ10_Pos              (0U)
2017 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
2018 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
2019 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
2020 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
2021 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
2022 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
2023 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
2024 
2025 #define ADC_SQR3_SQ11_Pos              (6U)
2026 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
2027 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
2028 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
2029 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
2030 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
2031 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
2032 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
2033 
2034 #define ADC_SQR3_SQ12_Pos              (12U)
2035 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
2036 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
2037 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
2038 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
2039 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
2040 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
2041 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
2042 
2043 #define ADC_SQR3_SQ13_Pos              (18U)
2044 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
2045 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
2046 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
2047 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
2048 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
2049 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
2050 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
2051 
2052 #define ADC_SQR3_SQ14_Pos              (24U)
2053 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
2054 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
2055 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
2056 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
2057 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
2058 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
2059 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
2060 
2061 /********************  Bit definition for ADC_SQR4 register  ******************/
2062 #define ADC_SQR4_SQ15_Pos              (0U)
2063 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
2064 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
2065 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
2066 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
2067 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
2068 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
2069 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
2070 
2071 #define ADC_SQR4_SQ16_Pos              (6U)
2072 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
2073 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
2074 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
2075 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
2076 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
2077 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
2078 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
2079 
2080 /********************  Bit definition for ADC_DR register  ********************/
2081 #define ADC_DR_RDATA_Pos               (0U)
2082 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
2083 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
2084 
2085 /********************  Bit definition for ADC_JSQR register  ******************/
2086 #define ADC_JSQR_JL_Pos                (0U)
2087 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
2088 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
2089 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
2090 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
2091 
2092 #define ADC_JSQR_JEXTSEL_Pos           (2U)
2093 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
2094 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
2095 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
2096 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
2097 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
2098 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
2099 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
2100 
2101 #define ADC_JSQR_JEXTEN_Pos            (7U)
2102 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
2103 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
2104 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
2105 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
2106 
2107 #define ADC_JSQR_JSQ1_Pos              (9U)
2108 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
2109 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
2110 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
2111 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
2112 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
2113 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
2114 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
2115 
2116 #define ADC_JSQR_JSQ2_Pos              (15U)
2117 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
2118 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
2119 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
2120 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
2121 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
2122 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
2123 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
2124 
2125 #define ADC_JSQR_JSQ3_Pos              (21U)
2126 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
2127 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
2128 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
2129 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
2130 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
2131 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
2132 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
2133 
2134 #define ADC_JSQR_JSQ4_Pos              (27U)
2135 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
2136 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
2137 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
2138 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
2139 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
2140 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
2141 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
2142 
2143 /********************  Bit definition for ADC_OFR1 register  ******************/
2144 #define ADC_OFR1_OFFSET1_Pos           (0U)
2145 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
2146 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
2147 
2148 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
2149 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
2150 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
2151 #define ADC_OFR1_SATEN_Pos             (25U)
2152 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
2153 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
2154 
2155 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
2156 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
2157 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
2158 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
2159 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
2160 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
2161 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
2162 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
2163 
2164 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
2165 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
2166 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
2167 
2168 /********************  Bit definition for ADC_OFR2 register  ******************/
2169 #define ADC_OFR2_OFFSET2_Pos           (0U)
2170 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
2171 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
2172 
2173 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
2174 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
2175 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
2176 #define ADC_OFR2_SATEN_Pos             (25U)
2177 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
2178 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
2179 
2180 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
2181 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
2182 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
2183 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
2184 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
2185 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
2186 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
2187 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
2188 
2189 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
2190 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
2191 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
2192 
2193 /********************  Bit definition for ADC_OFR3 register  ******************/
2194 #define ADC_OFR3_OFFSET3_Pos           (0U)
2195 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
2196 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
2197 
2198 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
2199 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
2200 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
2201 #define ADC_OFR3_SATEN_Pos             (25U)
2202 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
2203 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
2204 
2205 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
2206 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
2207 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2208 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
2209 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
2210 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2211 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2212 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2213 
2214 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2215 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2216 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2217 
2218 /********************  Bit definition for ADC_OFR4 register  ******************/
2219 #define ADC_OFR4_OFFSET4_Pos           (0U)
2220 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2221 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2222 
2223 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2224 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2225 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2226 #define ADC_OFR4_SATEN_Pos             (25U)
2227 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2228 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2229 
2230 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2231 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2232 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2233 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2234 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2235 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2236 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2237 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2238 
2239 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2240 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2241 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2242 
2243 /********************  Bit definition for ADC_JDR1 register  ******************/
2244 #define ADC_JDR1_JDATA_Pos             (0U)
2245 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2246 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2247 
2248 /********************  Bit definition for ADC_JDR2 register  ******************/
2249 #define ADC_JDR2_JDATA_Pos             (0U)
2250 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2251 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2252 
2253 /********************  Bit definition for ADC_JDR3 register  ******************/
2254 #define ADC_JDR3_JDATA_Pos             (0U)
2255 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2256 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2257 
2258 /********************  Bit definition for ADC_JDR4 register  ******************/
2259 #define ADC_JDR4_JDATA_Pos             (0U)
2260 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2261 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2262 
2263 /********************  Bit definition for ADC_AWD2CR register  ****************/
2264 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2265 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2266 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2267 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2268 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2269 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2270 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2271 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2272 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2273 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2274 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2275 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2276 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2277 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2278 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2279 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2280 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2281 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2282 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2283 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2284 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2285 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2286 
2287 /********************  Bit definition for ADC_AWD3CR register  ****************/
2288 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2289 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2290 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2291 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2292 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2293 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2294 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2295 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2296 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2297 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2298 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2299 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2300 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2301 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2302 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2303 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2304 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2305 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2306 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2307 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2308 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2309 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2310 
2311 /********************  Bit definition for ADC_DIFSEL register  ****************/
2312 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2313 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2314 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2315 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2316 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2317 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2318 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2319 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2320 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2321 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2322 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2323 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2324 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2325 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2326 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2327 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2328 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2329 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2330 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2331 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2332 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2333 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2334 
2335 /********************  Bit definition for ADC_CALFACT register  ***************/
2336 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2337 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2338 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2339 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2340 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2341 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2342 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2343 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2344 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2345 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2346 
2347 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2348 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2349 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2350 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2351 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2352 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2353 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2354 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2355 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2356 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2357 
2358 /********************  Bit definition for ADC_GCOMP register  *****************/
2359 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
2360 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
2361 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
2362 
2363 /*************************  ADC Common registers  *****************************/
2364 /********************  Bit definition for ADC_CSR register  *******************/
2365 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2366 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2367 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2368 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2369 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2370 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2371 #define ADC_CSR_EOC_MST_Pos            (2U)
2372 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2373 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2374 #define ADC_CSR_EOS_MST_Pos            (3U)
2375 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2376 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2377 #define ADC_CSR_OVR_MST_Pos            (4U)
2378 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2379 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2380 #define ADC_CSR_JEOC_MST_Pos           (5U)
2381 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2382 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2383 #define ADC_CSR_JEOS_MST_Pos           (6U)
2384 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2385 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2386 #define ADC_CSR_AWD1_MST_Pos           (7U)
2387 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2388 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2389 #define ADC_CSR_AWD2_MST_Pos           (8U)
2390 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2391 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2392 #define ADC_CSR_AWD3_MST_Pos           (9U)
2393 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2394 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2395 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2396 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2397 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2398 
2399 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2400 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2401 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2402 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2403 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2404 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2405 #define ADC_CSR_EOC_SLV_Pos            (18U)
2406 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2407 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2408 #define ADC_CSR_EOS_SLV_Pos            (19U)
2409 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2410 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2411 #define ADC_CSR_OVR_SLV_Pos            (20U)
2412 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2413 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2414 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2415 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2416 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2417 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2418 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2419 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2420 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2421 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2422 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2423 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2424 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2425 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2426 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2427 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2428 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2429 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2430 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2431 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2432 
2433 /********************  Bit definition for ADC_CCR register  *******************/
2434 #define ADC_CCR_DUAL_Pos               (0U)
2435 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2436 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2437 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2438 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2439 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2440 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2441 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2442 
2443 #define ADC_CCR_DELAY_Pos              (8U)
2444 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2445 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2446 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2447 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2448 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2449 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2450 
2451 #define ADC_CCR_DMACFG_Pos             (13U)
2452 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2453 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2454 
2455 #define ADC_CCR_MDMA_Pos               (14U)
2456 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2457 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2458 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2459 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2460 
2461 #define ADC_CCR_CKMODE_Pos             (16U)
2462 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2463 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2464 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2465 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2466 
2467 #define ADC_CCR_PRESC_Pos              (18U)
2468 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2469 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2470 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2471 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2472 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2473 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2474 
2475 #define ADC_CCR_VREFEN_Pos             (22U)
2476 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2477 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2478 #define ADC_CCR_VSENSESEL_Pos          (23U)
2479 #define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
2480 #define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
2481 #define ADC_CCR_VBATSEL_Pos            (24U)
2482 #define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
2483 #define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
2484 
2485 /********************  Bit definition for ADC_CDR register  *******************/
2486 #define ADC_CDR_RDATA_MST_Pos          (0U)
2487 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2488 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2489 
2490 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2491 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2492 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2493 
2494 
2495 /******************************************************************************/
2496 /*                                                                            */
2497 /*                      Analog Comparators (COMP)                             */
2498 /*                                                                            */
2499 /******************************************************************************/
2500 /**********************  Bit definition for COMP_CSR register  ****************/
2501 #define COMP_CSR_EN_Pos            (0U)
2502 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
2503 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
2504 
2505 #define COMP_CSR_INMSEL_Pos        (4U)
2506 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
2507 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
2508 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
2509 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
2510 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
2511 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
2512 
2513 #define COMP_CSR_INPSEL_Pos        (8U)
2514 #define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
2515 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
2516 
2517 #define COMP_CSR_POLARITY_Pos      (15U)
2518 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
2519 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
2520 
2521 #define COMP_CSR_HYST_Pos          (16U)
2522 #define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
2523 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
2524 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
2525 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
2526 #define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
2527 
2528 #define COMP_CSR_BLANKING_Pos      (19U)
2529 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
2530 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
2531 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
2532 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
2533 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
2534 
2535 #define COMP_CSR_BRGEN_Pos         (22U)
2536 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
2537 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
2538 
2539 #define COMP_CSR_SCALEN_Pos        (23U)
2540 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
2541 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
2542 
2543 #define COMP_CSR_VALUE_Pos         (30U)
2544 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
2545 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
2546 
2547 #define COMP_CSR_LOCK_Pos          (31U)
2548 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
2549 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
2550 
2551 /******************************************************************************/
2552 /*                                                                            */
2553 /*                          CORDIC calculation unit                           */
2554 /*                                                                            */
2555 /******************************************************************************/
2556 /*******************  Bit definition for CORDIC_CSR register  *****************/
2557 #define CORDIC_CSR_FUNC_Pos      (0U)
2558 #define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
2559 #define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
2560 #define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
2561 #define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
2562 #define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
2563 #define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
2564 #define CORDIC_CSR_PRECISION_Pos (4U)
2565 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
2566 #define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
2567 #define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
2568 #define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
2569 #define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
2570 #define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
2571 #define CORDIC_CSR_SCALE_Pos     (8U)
2572 #define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
2573 #define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
2574 #define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
2575 #define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
2576 #define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
2577 #define CORDIC_CSR_IEN_Pos       (16U)
2578 #define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
2579 #define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
2580 #define CORDIC_CSR_DMAREN_Pos    (17U)
2581 #define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
2582 #define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
2583 #define CORDIC_CSR_DMAWEN_Pos    (18U)
2584 #define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
2585 #define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
2586 #define CORDIC_CSR_NRES_Pos      (19U)
2587 #define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
2588 #define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
2589 #define CORDIC_CSR_NARGS_Pos     (20U)
2590 #define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
2591 #define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
2592 #define CORDIC_CSR_RESSIZE_Pos   (21U)
2593 #define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
2594 #define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
2595 #define CORDIC_CSR_ARGSIZE_Pos   (22U)
2596 #define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
2597 #define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
2598 #define CORDIC_CSR_RRDY_Pos      (31U)
2599 #define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
2600 #define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
2601 
2602 /*******************  Bit definition for CORDIC_WDATA register  ***************/
2603 #define CORDIC_WDATA_ARG_Pos     (0U)
2604 #define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
2605 #define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
2606 
2607 /*******************  Bit definition for CORDIC_RDATA register  ***************/
2608 #define CORDIC_RDATA_RES_Pos     (0U)
2609 #define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
2610 #define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
2611 
2612 /******************************************************************************/
2613 /*                                                                            */
2614 /*                          CRC calculation unit                              */
2615 /*                                                                            */
2616 /******************************************************************************/
2617 /*******************  Bit definition for CRC_DR register  *********************/
2618 #define CRC_DR_DR_Pos            (0U)
2619 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2620 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2621 
2622 /*******************  Bit definition for CRC_IDR register  ********************/
2623 #define CRC_IDR_IDR_Pos          (0U)
2624 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
2625 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
2626 
2627 /********************  Bit definition for CRC_CR register  ********************/
2628 #define CRC_CR_RESET_Pos         (0U)
2629 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2630 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2631 #define CRC_CR_POLYSIZE_Pos      (3U)
2632 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2633 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2634 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2635 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2636 #define CRC_CR_REV_IN_Pos        (5U)
2637 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2638 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2639 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2640 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2641 #define CRC_CR_REV_OUT_Pos       (7U)
2642 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2643 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2644 
2645 /*******************  Bit definition for CRC_INIT register  *******************/
2646 #define CRC_INIT_INIT_Pos        (0U)
2647 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2648 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2649 
2650 /*******************  Bit definition for CRC_POL register  ********************/
2651 #define CRC_POL_POL_Pos          (0U)
2652 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2653 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2654 
2655 /******************************************************************************/
2656 /*                                                                            */
2657 /*                          CRS Clock Recovery System                         */
2658 /******************************************************************************/
2659 
2660 /*******************  Bit definition for CRS_CR register  *********************/
2661 #define CRS_CR_SYNCOKIE_Pos       (0U)
2662 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2663 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2664 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2665 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2666 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2667 #define CRS_CR_ERRIE_Pos          (2U)
2668 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2669 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2670 #define CRS_CR_ESYNCIE_Pos        (3U)
2671 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2672 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2673 #define CRS_CR_CEN_Pos            (5U)
2674 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2675 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2676 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2677 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2678 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2679 #define CRS_CR_SWSYNC_Pos         (7U)
2680 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2681 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2682 #define CRS_CR_TRIM_Pos           (8U)
2683 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2684 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2685 
2686 /*******************  Bit definition for CRS_CFGR register  *********************/
2687 #define CRS_CFGR_RELOAD_Pos       (0U)
2688 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2689 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2690 #define CRS_CFGR_FELIM_Pos        (16U)
2691 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2692 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2693 
2694 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2695 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2696 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2697 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2698 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2699 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2700 
2701 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2702 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2703 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2704 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2705 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2706 
2707 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2708 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2709 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2710 
2711 /*******************  Bit definition for CRS_ISR register  *********************/
2712 #define CRS_ISR_SYNCOKF_Pos       (0U)
2713 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2714 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2715 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2716 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2717 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2718 #define CRS_ISR_ERRF_Pos          (2U)
2719 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2720 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2721 #define CRS_ISR_ESYNCF_Pos        (3U)
2722 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2723 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2724 #define CRS_ISR_SYNCERR_Pos       (8U)
2725 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2726 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2727 #define CRS_ISR_SYNCMISS_Pos      (9U)
2728 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2729 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2730 #define CRS_ISR_TRIMOVF_Pos       (10U)
2731 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2732 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2733 #define CRS_ISR_FEDIR_Pos         (15U)
2734 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2735 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2736 #define CRS_ISR_FECAP_Pos         (16U)
2737 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2738 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2739 
2740 /*******************  Bit definition for CRS_ICR register  *********************/
2741 #define CRS_ICR_SYNCOKC_Pos       (0U)
2742 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2743 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2744 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2745 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2746 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2747 #define CRS_ICR_ERRC_Pos          (2U)
2748 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2749 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2750 #define CRS_ICR_ESYNCC_Pos        (3U)
2751 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2752 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2753 
2754 /******************************************************************************/
2755 /*                                                                            */
2756 /*                      Digital to Analog Converter                           */
2757 /*                                                                            */
2758 /******************************************************************************/
2759 /*
2760  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2761  */
2762 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
2763 
2764 /********************  Bit definition for DAC_CR register  ********************/
2765 #define DAC_CR_EN1_Pos              (0U)
2766 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2767 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2768 #define DAC_CR_TEN1_Pos             (1U)
2769 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2770 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2771 
2772 #define DAC_CR_TSEL1_Pos            (2U)
2773 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2774 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2775 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
2776 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
2777 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
2778 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
2779 
2780 #define DAC_CR_WAVE1_Pos            (6U)
2781 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2782 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2783 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
2784 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
2785 
2786 #define DAC_CR_MAMP1_Pos            (8U)
2787 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2788 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2789 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
2790 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
2791 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
2792 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
2793 
2794 #define DAC_CR_DMAEN1_Pos           (12U)
2795 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2796 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2797 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2798 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2799 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2800 #define DAC_CR_CEN1_Pos             (14U)
2801 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2802 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2803 
2804 #define DAC_CR_HFSEL_Pos            (15U)
2805 #define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
2806 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
2807 
2808 #define DAC_CR_EN2_Pos              (16U)
2809 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2810 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2811 #define DAC_CR_TEN2_Pos             (17U)
2812 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2813 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2814 
2815 #define DAC_CR_TSEL2_Pos            (18U)
2816 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2817 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2818 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
2819 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
2820 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
2821 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
2822 
2823 #define DAC_CR_WAVE2_Pos            (22U)
2824 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2825 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2826 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
2827 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
2828 
2829 #define DAC_CR_MAMP2_Pos            (24U)
2830 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2831 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2832 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
2833 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
2834 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
2835 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
2836 
2837 #define DAC_CR_DMAEN2_Pos           (28U)
2838 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2839 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2840 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2841 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2842 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2843 #define DAC_CR_CEN2_Pos             (30U)
2844 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2845 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2846 
2847 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2848 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2849 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2850 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2851 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2852 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2853 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2854 #define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
2855 #define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
2856 #define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
2857 #define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
2858 #define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
2859 #define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
2860 
2861 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2862 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2863 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2864 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2865 #define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
2866 #define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
2867 #define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
2868 
2869 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2870 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2871 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2872 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2873 #define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
2874 #define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
2875 #define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
2876 
2877 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2878 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2879 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2880 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2881 #define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
2882 #define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
2883 #define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
2884 
2885 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2886 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2887 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2888 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2889 #define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
2890 #define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
2891 #define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
2892 
2893 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2894 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2895 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2896 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2897 #define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
2898 #define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
2899 #define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
2900 
2901 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2902 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2903 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2904 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2905 #define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
2906 #define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
2907 #define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
2908 
2909 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2910 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2911 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2912 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2913 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2914 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2915 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2916 
2917 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2918 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2919 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2920 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2921 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2922 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2923 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2924 
2925 /******************  Bit definition for DAC_DHR8RD register  ******************/
2926 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2927 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2928 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2929 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2930 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2931 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2932 
2933 /*******************  Bit definition for DAC_DOR1 register  *******************/
2934 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2935 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2936 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2937 #define DAC_DOR1_DACC1DORB_Pos      (16U)
2938 #define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
2939 #define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
2940 
2941 /*******************  Bit definition for DAC_DOR2 register  *******************/
2942 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2943 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2944 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2945 #define DAC_DOR2_DACC2DORB_Pos      (16U)
2946 #define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
2947 #define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
2948 
2949 /********************  Bit definition for DAC_SR register  ********************/
2950 #define DAC_SR_DAC1RDY_Pos          (11U)
2951 #define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
2952 #define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
2953 #define DAC_SR_DORSTAT1_Pos         (12U)
2954 #define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
2955 #define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
2956 #define DAC_SR_DMAUDR1_Pos          (13U)
2957 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2958 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2959 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2960 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2961 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2962 #define DAC_SR_BWST1_Pos            (15U)
2963 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
2964 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2965 
2966 #define DAC_SR_DAC2RDY_Pos          (27U)
2967 #define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
2968 #define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
2969 #define DAC_SR_DORSTAT2_Pos         (28U)
2970 #define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
2971 #define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
2972 #define DAC_SR_DMAUDR2_Pos          (29U)
2973 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2974 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2975 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2976 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2977 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2978 #define DAC_SR_BWST2_Pos            (31U)
2979 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2980 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2981 
2982 /*******************  Bit definition for DAC_CCR register  ********************/
2983 #define DAC_CCR_OTRIM1_Pos          (0U)
2984 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2985 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2986 #define DAC_CCR_OTRIM2_Pos          (16U)
2987 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2988 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2989 
2990 /*******************  Bit definition for DAC_MCR register  *******************/
2991 #define DAC_MCR_MODE1_Pos           (0U)
2992 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2993 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2994 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
2995 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
2996 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
2997 
2998 #define DAC_MCR_DMADOUBLE1_Pos      (8U)
2999 #define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
3000 #define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
3001 
3002 #define DAC_MCR_SINFORMAT1_Pos      (9U)
3003 #define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
3004 #define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
3005 
3006 #define DAC_MCR_HFSEL_Pos           (14U)
3007 #define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
3008 #define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
3009 #define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
3010 #define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
3011 
3012 #define DAC_MCR_MODE2_Pos           (16U)
3013 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
3014 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
3015 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
3016 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
3017 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
3018 
3019 #define DAC_MCR_DMADOUBLE2_Pos      (24U)
3020 #define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
3021 #define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
3022 
3023 #define DAC_MCR_SINFORMAT2_Pos      (25U)
3024 #define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
3025 #define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
3026 
3027 /******************  Bit definition for DAC_SHSR1 register  ******************/
3028 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
3029 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
3030 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
3031 
3032 /******************  Bit definition for DAC_SHSR2 register  ******************/
3033 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
3034 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
3035 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
3036 
3037 /******************  Bit definition for DAC_SHHR register  ******************/
3038 #define DAC_SHHR_THOLD1_Pos         (0U)
3039 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
3040 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
3041 #define DAC_SHHR_THOLD2_Pos         (16U)
3042 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
3043 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
3044 
3045 /******************  Bit definition for DAC_SHRR register  ******************/
3046 #define DAC_SHRR_TREFRESH1_Pos      (0U)
3047 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
3048 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
3049 #define DAC_SHRR_TREFRESH2_Pos      (16U)
3050 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
3051 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
3052 
3053 /******************  Bit definition for DAC_STR1 register  ******************/
3054 #define DAC_STR1_STRSTDATA1_Pos     (0U)
3055 #define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
3056 #define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
3057 #define DAC_STR1_STDIR1_Pos         (12U)
3058 #define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
3059 #define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
3060 
3061 #define DAC_STR1_STINCDATA1_Pos     (16U)
3062 #define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
3063 #define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
3064 
3065 /******************  Bit definition for DAC_STR2 register  ******************/
3066 #define DAC_STR2_STRSTDATA2_Pos     (0U)
3067 #define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
3068 #define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
3069 #define DAC_STR2_STDIR2_Pos         (12U)
3070 #define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
3071 #define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
3072 
3073 #define DAC_STR2_STINCDATA2_Pos     (16U)
3074 #define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
3075 #define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
3076 
3077 /******************  Bit definition for DAC_STMODR register  ****************/
3078 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
3079 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
3080 #define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3081 #define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
3082 #define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
3083 #define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
3084 #define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
3085 
3086 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
3087 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
3088 #define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3089 #define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
3090 #define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
3091 #define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
3092 #define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
3093 
3094 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
3095 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
3096 #define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3097 #define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
3098 #define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
3099 #define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
3100 #define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
3101 
3102 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
3103 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
3104 #define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3105 #define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
3106 #define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
3107 #define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
3108 #define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
3109 
3110 /******************************************************************************/
3111 /*                                                                            */
3112 /*                                 Debug MCU                                  */
3113 /*                                                                            */
3114 /******************************************************************************/
3115 /********************  Bit definition for DBGMCU_IDCODE register  *************/
3116 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
3117 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
3118 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
3119 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
3120 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
3121 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
3122 
3123 /********************  Bit definition for DBGMCU_CR register  *****************/
3124 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
3125 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
3126 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
3127 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
3128 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
3129 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
3130 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
3131 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
3132 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
3133 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
3134 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
3135 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
3136 
3137 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
3138 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
3139 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
3140 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
3141 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
3142 
3143 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
3144 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
3145 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
3146 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3147 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
3148 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
3149 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3150 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
3151 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
3152 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
3153 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)
3154 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
3155 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
3156 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
3157 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
3158 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3159 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
3160 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
3161 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3162 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
3163 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
3164 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
3165 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
3166 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
3167 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3168 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
3169 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
3170 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3171 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
3172 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
3173 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3174 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
3175 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
3176 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3177 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (30U)
3178 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
3179 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
3180 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
3181 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
3182 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
3183 
3184 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
3185 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)
3186 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
3187 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
3188 
3189 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
3190 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
3191 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
3192 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
3193 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
3194 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
3195 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
3196 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
3197 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
3198 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
3199 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
3200 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
3201 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
3202 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
3203 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
3204 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
3205 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos       (20U)
3206 #define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
3207 #define DBGMCU_APB2FZ_DBG_TIM20_STOP           DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
3208 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos      (26U)
3209 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk      (0x1UL << DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos)/*!< 0x04000000 */
3210 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP          DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk
3211 
3212 /******************************************************************************/
3213 /*                                                                            */
3214 /*                           DMA Controller (DMA)                             */
3215 /*                                                                            */
3216 /******************************************************************************/
3217 
3218 /*******************  Bit definition for DMA_ISR register  ********************/
3219 #define DMA_ISR_GIF1_Pos       (0U)
3220 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
3221 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
3222 #define DMA_ISR_TCIF1_Pos      (1U)
3223 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
3224 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
3225 #define DMA_ISR_HTIF1_Pos      (2U)
3226 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
3227 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
3228 #define DMA_ISR_TEIF1_Pos      (3U)
3229 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
3230 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
3231 #define DMA_ISR_GIF2_Pos       (4U)
3232 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
3233 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
3234 #define DMA_ISR_TCIF2_Pos      (5U)
3235 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
3236 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
3237 #define DMA_ISR_HTIF2_Pos      (6U)
3238 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
3239 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
3240 #define DMA_ISR_TEIF2_Pos      (7U)
3241 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
3242 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
3243 #define DMA_ISR_GIF3_Pos       (8U)
3244 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
3245 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
3246 #define DMA_ISR_TCIF3_Pos      (9U)
3247 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
3248 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
3249 #define DMA_ISR_HTIF3_Pos      (10U)
3250 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
3251 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
3252 #define DMA_ISR_TEIF3_Pos      (11U)
3253 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
3254 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
3255 #define DMA_ISR_GIF4_Pos       (12U)
3256 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
3257 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
3258 #define DMA_ISR_TCIF4_Pos      (13U)
3259 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
3260 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
3261 #define DMA_ISR_HTIF4_Pos      (14U)
3262 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
3263 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
3264 #define DMA_ISR_TEIF4_Pos      (15U)
3265 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
3266 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
3267 #define DMA_ISR_GIF5_Pos       (16U)
3268 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
3269 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
3270 #define DMA_ISR_TCIF5_Pos      (17U)
3271 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
3272 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
3273 #define DMA_ISR_HTIF5_Pos      (18U)
3274 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
3275 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
3276 #define DMA_ISR_TEIF5_Pos      (19U)
3277 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
3278 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
3279 #define DMA_ISR_GIF6_Pos       (20U)
3280 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
3281 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
3282 #define DMA_ISR_TCIF6_Pos      (21U)
3283 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
3284 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
3285 #define DMA_ISR_HTIF6_Pos      (22U)
3286 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
3287 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
3288 #define DMA_ISR_TEIF6_Pos      (23U)
3289 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
3290 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
3291 #define DMA_ISR_GIF7_Pos       (24U)
3292 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
3293 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
3294 #define DMA_ISR_TCIF7_Pos      (25U)
3295 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
3296 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
3297 #define DMA_ISR_HTIF7_Pos      (26U)
3298 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
3299 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
3300 #define DMA_ISR_TEIF7_Pos      (27U)
3301 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
3302 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
3303 #define DMA_ISR_GIF8_Pos       (28U)
3304 #define DMA_ISR_GIF8_Msk       (0x1UL << DMA_ISR_GIF8_Pos)                     /*!< 0x10000000 */
3305 #define DMA_ISR_GIF8           DMA_ISR_GIF8_Msk                                /*!< Channel 8 Global interrupt flag */
3306 #define DMA_ISR_TCIF8_Pos      (29U)
3307 #define DMA_ISR_TCIF8_Msk      (0x1UL << DMA_ISR_TCIF8_Pos)                    /*!< 0x20000000 */
3308 #define DMA_ISR_TCIF8          DMA_ISR_TCIF8_Msk                               /*!< Channel 8 Transfer Complete flag */
3309 #define DMA_ISR_HTIF8_Pos      (30U)
3310 #define DMA_ISR_HTIF8_Msk      (0x1UL << DMA_ISR_HTIF8_Pos)                    /*!< 0x40000000 */
3311 #define DMA_ISR_HTIF8          DMA_ISR_HTIF8_Msk                               /*!< Channel 8 Half Transfer flag */
3312 #define DMA_ISR_TEIF8_Pos      (31U)
3313 #define DMA_ISR_TEIF8_Msk      (0x1UL << DMA_ISR_TEIF8_Pos)                    /*!< 0x80000000 */
3314 #define DMA_ISR_TEIF8          DMA_ISR_TEIF8_Msk                               /*!< Channel 8 Transfer Error flag */
3315 
3316 /*******************  Bit definition for DMA_IFCR register  *******************/
3317 #define DMA_IFCR_CGIF1_Pos     (0U)
3318 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
3319 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
3320 #define DMA_IFCR_CTCIF1_Pos    (1U)
3321 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
3322 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
3323 #define DMA_IFCR_CHTIF1_Pos    (2U)
3324 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
3325 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
3326 #define DMA_IFCR_CTEIF1_Pos    (3U)
3327 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
3328 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
3329 #define DMA_IFCR_CGIF2_Pos     (4U)
3330 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
3331 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
3332 #define DMA_IFCR_CTCIF2_Pos    (5U)
3333 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
3334 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
3335 #define DMA_IFCR_CHTIF2_Pos    (6U)
3336 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
3337 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
3338 #define DMA_IFCR_CTEIF2_Pos    (7U)
3339 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
3340 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
3341 #define DMA_IFCR_CGIF3_Pos     (8U)
3342 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
3343 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
3344 #define DMA_IFCR_CTCIF3_Pos    (9U)
3345 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
3346 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
3347 #define DMA_IFCR_CHTIF3_Pos    (10U)
3348 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
3349 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
3350 #define DMA_IFCR_CTEIF3_Pos    (11U)
3351 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
3352 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
3353 #define DMA_IFCR_CGIF4_Pos     (12U)
3354 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
3355 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
3356 #define DMA_IFCR_CTCIF4_Pos    (13U)
3357 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
3358 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
3359 #define DMA_IFCR_CHTIF4_Pos    (14U)
3360 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
3361 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
3362 #define DMA_IFCR_CTEIF4_Pos    (15U)
3363 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
3364 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
3365 #define DMA_IFCR_CGIF5_Pos     (16U)
3366 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
3367 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
3368 #define DMA_IFCR_CTCIF5_Pos    (17U)
3369 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
3370 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
3371 #define DMA_IFCR_CHTIF5_Pos    (18U)
3372 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
3373 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
3374 #define DMA_IFCR_CTEIF5_Pos    (19U)
3375 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
3376 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
3377 #define DMA_IFCR_CGIF6_Pos     (20U)
3378 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
3379 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
3380 #define DMA_IFCR_CTCIF6_Pos    (21U)
3381 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
3382 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
3383 #define DMA_IFCR_CHTIF6_Pos    (22U)
3384 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
3385 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
3386 #define DMA_IFCR_CTEIF6_Pos    (23U)
3387 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
3388 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
3389 #define DMA_IFCR_CGIF7_Pos     (24U)
3390 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
3391 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
3392 #define DMA_IFCR_CTCIF7_Pos    (25U)
3393 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
3394 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
3395 #define DMA_IFCR_CHTIF7_Pos    (26U)
3396 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
3397 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
3398 #define DMA_IFCR_CTEIF7_Pos    (27U)
3399 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
3400 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
3401 #define DMA_IFCR_CGIF8_Pos     (28U)
3402 #define DMA_IFCR_CGIF8_Msk     (0x1UL << DMA_IFCR_CGIF8_Pos)                   /*!< 0x10000000 */
3403 #define DMA_IFCR_CGIF8         DMA_IFCR_CGIF8_Msk                              /*!< Channel 8 Global interrupt clear */
3404 #define DMA_IFCR_CTCIF8_Pos    (29U)
3405 #define DMA_IFCR_CTCIF8_Msk    (0x1UL << DMA_IFCR_CTCIF8_Pos)                  /*!< 0x20000000 */
3406 #define DMA_IFCR_CTCIF8        DMA_IFCR_CTCIF8_Msk                             /*!< Channel 8 Transfer Complete clear */
3407 #define DMA_IFCR_CHTIF8_Pos    (30U)
3408 #define DMA_IFCR_CHTIF8_Msk    (0x1UL << DMA_IFCR_CHTIF8_Pos)                  /*!< 0x40000000 */
3409 #define DMA_IFCR_CHTIF8        DMA_IFCR_CHTIF8_Msk                             /*!< Channel 8 Half Transfer clear */
3410 #define DMA_IFCR_CTEIF8_Pos    (31U)
3411 #define DMA_IFCR_CTEIF8_Msk    (0x1UL << DMA_IFCR_CTEIF8_Pos)                  /*!< 0x80000000 */
3412 #define DMA_IFCR_CTEIF8        DMA_IFCR_CTEIF8_Msk                             /*!< Channel 8 Transfer Error clear */
3413 
3414 /*******************  Bit definition for DMA_CCR register  ********************/
3415 #define DMA_CCR_EN_Pos         (0U)
3416 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
3417 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
3418 #define DMA_CCR_TCIE_Pos       (1U)
3419 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
3420 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
3421 #define DMA_CCR_HTIE_Pos       (2U)
3422 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
3423 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
3424 #define DMA_CCR_TEIE_Pos       (3U)
3425 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
3426 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
3427 #define DMA_CCR_DIR_Pos        (4U)
3428 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
3429 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
3430 #define DMA_CCR_CIRC_Pos       (5U)
3431 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
3432 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
3433 #define DMA_CCR_PINC_Pos       (6U)
3434 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
3435 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
3436 #define DMA_CCR_MINC_Pos       (7U)
3437 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
3438 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
3439 
3440 #define DMA_CCR_PSIZE_Pos      (8U)
3441 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
3442 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
3443 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
3444 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
3445 
3446 #define DMA_CCR_MSIZE_Pos      (10U)
3447 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
3448 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
3449 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
3450 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
3451 
3452 #define DMA_CCR_PL_Pos         (12U)
3453 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
3454 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
3455 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
3456 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
3457 
3458 #define DMA_CCR_MEM2MEM_Pos    (14U)
3459 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
3460 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
3461 
3462 /******************  Bit definition for DMA_CNDTR register  *******************/
3463 #define DMA_CNDTR_NDT_Pos      (0U)
3464 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
3465 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
3466 
3467 /******************  Bit definition for DMA_CPAR register  ********************/
3468 #define DMA_CPAR_PA_Pos        (0U)
3469 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
3470 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
3471 
3472 /******************  Bit definition for DMA_CMAR register  ********************/
3473 #define DMA_CMAR_MA_Pos        (0U)
3474 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
3475 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
3476 
3477 /******************************************************************************/
3478 /*                                                                            */
3479 /*                             DMAMUX Controller                              */
3480 /*                                                                            */
3481 /******************************************************************************/
3482 
3483 /********************  Bits definition for DMAMUX_CxCR register  **************/
3484 #define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
3485 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3486 #define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
3487 #define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3488 #define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3489 #define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3490 #define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3491 #define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3492 #define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3493 #define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3494 #define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3495 
3496 #define DMAMUX_CxCR_SOIE_Pos                         (8U)
3497 #define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3498 #define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
3499 
3500 #define DMAMUX_CxCR_EGE_Pos                          (9U)
3501 #define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3502 #define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
3503 
3504 #define DMAMUX_CxCR_SE_Pos                           (16U)
3505 #define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3506 #define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
3507 
3508 #define DMAMUX_CxCR_SPOL_Pos                         (17U)
3509 #define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3510 #define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
3511 #define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3512 #define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3513 
3514 #define DMAMUX_CxCR_NBREQ_Pos                        (19U)
3515 #define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3516 #define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
3517 #define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3518 #define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3519 #define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3520 #define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3521 #define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3522 
3523 #define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
3524 #define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3525 #define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
3526 #define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3527 #define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3528 #define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3529 #define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3530 #define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3531 
3532 /********************  Bits definition for DMAMUX_CSR register  ****************/
3533 #define DMAMUX_CSR_SOF0_Pos                          (0U)
3534 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3535 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
3536 #define DMAMUX_CSR_SOF1_Pos                          (1U)
3537 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3538 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
3539 #define DMAMUX_CSR_SOF2_Pos                          (2U)
3540 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3541 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
3542 #define DMAMUX_CSR_SOF3_Pos                          (3U)
3543 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3544 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
3545 #define DMAMUX_CSR_SOF4_Pos                          (4U)
3546 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3547 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
3548 #define DMAMUX_CSR_SOF5_Pos                          (5U)
3549 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3550 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
3551 #define DMAMUX_CSR_SOF6_Pos                          (6U)
3552 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3553 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
3554 #define DMAMUX_CSR_SOF7_Pos                          (7U)
3555 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3556 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
3557 #define DMAMUX_CSR_SOF8_Pos                          (8U)
3558 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3559 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
3560 #define DMAMUX_CSR_SOF9_Pos                          (9U)
3561 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3562 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
3563 #define DMAMUX_CSR_SOF10_Pos                         (10U)
3564 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3565 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
3566 #define DMAMUX_CSR_SOF11_Pos                         (11U)
3567 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3568 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
3569 #define DMAMUX_CSR_SOF12_Pos                         (12U)
3570 #define DMAMUX_CSR_SOF12_Msk                         (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3571 #define DMAMUX_CSR_SOF12                             DMAMUX_CSR_SOF12_Msk
3572 #define DMAMUX_CSR_SOF13_Pos                         (13U)
3573 #define DMAMUX_CSR_SOF13_Msk                         (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3574 #define DMAMUX_CSR_SOF13                             DMAMUX_CSR_SOF13_Msk
3575 #define DMAMUX_CSR_SOF14_Pos                         (14U)
3576 #define DMAMUX_CSR_SOF14_Msk                         (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3577 #define DMAMUX_CSR_SOF14                             DMAMUX_CSR_SOF14_Msk
3578 #define DMAMUX_CSR_SOF15_Pos                         (15U)
3579 #define DMAMUX_CSR_SOF15_Msk                         (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3580 #define DMAMUX_CSR_SOF15                             DMAMUX_CSR_SOF15_Msk
3581 
3582 /********************  Bits definition for DMAMUX_CFR register  ****************/
3583 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
3584 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3585 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
3586 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
3587 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3588 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
3589 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
3590 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3591 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
3592 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
3593 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3594 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
3595 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
3596 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3597 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
3598 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
3599 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3600 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
3601 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
3602 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3603 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
3604 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
3605 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3606 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
3607 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
3608 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3609 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
3610 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
3611 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3612 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
3613 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
3614 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3615 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
3616 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
3617 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3618 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
3619 #define DMAMUX_CFR_CSOF12_Pos                        (12U)
3620 #define DMAMUX_CFR_CSOF12_Msk                        (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3621 #define DMAMUX_CFR_CSOF12                            DMAMUX_CFR_CSOF12_Msk
3622 #define DMAMUX_CFR_CSOF13_Pos                        (13U)
3623 #define DMAMUX_CFR_CSOF13_Msk                        (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3624 #define DMAMUX_CFR_CSOF13                            DMAMUX_CFR_CSOF13_Msk
3625 #define DMAMUX_CFR_CSOF14_Pos                        (14U)
3626 #define DMAMUX_CFR_CSOF14_Msk                        (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3627 #define DMAMUX_CFR_CSOF14                            DMAMUX_CFR_CSOF14_Msk
3628 #define DMAMUX_CFR_CSOF15_Pos                        (15U)
3629 #define DMAMUX_CFR_CSOF15_Msk                        (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3630 #define DMAMUX_CFR_CSOF15                            DMAMUX_CFR_CSOF15_Msk
3631 
3632 /********************  Bits definition for DMAMUX_RGxCR register  ************/
3633 #define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
3634 #define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3635 #define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
3636 #define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3637 #define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3638 #define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3639 #define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3640 #define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3641 
3642 #define DMAMUX_RGxCR_OIE_Pos                         (8U)
3643 #define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3644 #define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
3645 
3646 #define DMAMUX_RGxCR_GE_Pos                          (16U)
3647 #define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3648 #define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
3649 
3650 #define DMAMUX_RGxCR_GPOL_Pos                        (17U)
3651 #define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3652 #define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
3653 #define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3654 #define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3655 
3656 #define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
3657 #define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3658 #define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
3659 #define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3660 #define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3661 #define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3662 #define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3663 #define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3664 
3665 /********************  Bits definition for DMAMUX_RGSR register  **************/
3666 #define DMAMUX_RGSR_OF0_Pos                          (0U)
3667 #define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3668 #define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
3669 #define DMAMUX_RGSR_OF1_Pos                          (1U)
3670 #define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3671 #define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
3672 #define DMAMUX_RGSR_OF2_Pos                          (2U)
3673 #define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3674 #define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
3675 #define DMAMUX_RGSR_OF3_Pos                          (3U)
3676 #define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3677 #define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
3678 
3679 /********************  Bits definition for DMAMUX_RGCFR register  ************/
3680 #define DMAMUX_RGCFR_COF0_Pos                        (0U)
3681 #define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3682 #define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
3683 #define DMAMUX_RGCFR_COF1_Pos                        (1U)
3684 #define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3685 #define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
3686 #define DMAMUX_RGCFR_COF2_Pos                        (2U)
3687 #define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3688 #define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
3689 #define DMAMUX_RGCFR_COF3_Pos                        (3U)
3690 #define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3691 #define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
3692 
3693 /******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
3694 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
3695 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3696 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3697 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
3698 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3699 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3700 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
3701 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3702 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3703 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
3704 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3705 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3706 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
3707 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3708 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3709 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
3710 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3711 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3712 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
3713 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3714 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3715 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
3716 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3717 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3718 
3719 /******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
3720 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
3721 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3722 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3723 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
3724 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3725 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3726 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
3727 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3728 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3729 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
3730 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3731 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3732 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
3733 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3734 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3735 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
3736 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3737 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3738 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
3739 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3740 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3741 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
3742 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3743 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3744 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
3745 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3746 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3747 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
3748 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3749 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3750 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
3751 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3752 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3753 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
3754 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3755 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3756 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
3757 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3758 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3759 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
3760 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3761 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3762 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
3763 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3764 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3765 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
3766 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3767 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3768 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
3769 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3770 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3771 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
3772 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3773 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3774 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
3775 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3776 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3777 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
3778 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3779 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3780 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
3781 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3782 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3783 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
3784 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3785 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3786 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
3787 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3788 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3789 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
3790 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3791 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3792 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
3793 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3794 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3795 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
3796 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3797 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3798 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
3799 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3800 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3801 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
3802 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3803 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3804 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
3805 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3806 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3807 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
3808 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3809 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3810 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
3811 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3812 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3813 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
3814 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3815 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3816 
3817 
3818 /******************************************************************************/
3819 /*                                                                            */
3820 /*                    External Interrupt/Event Controller                     */
3821 /*                                                                            */
3822 /******************************************************************************/
3823 /*******************  Bit definition for EXTI_IMR1 register  ******************/
3824 #define EXTI_IMR1_IM0_Pos        (0U)
3825 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
3826 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
3827 #define EXTI_IMR1_IM1_Pos        (1U)
3828 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
3829 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
3830 #define EXTI_IMR1_IM2_Pos        (2U)
3831 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
3832 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
3833 #define EXTI_IMR1_IM3_Pos        (3U)
3834 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
3835 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
3836 #define EXTI_IMR1_IM4_Pos        (4U)
3837 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
3838 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
3839 #define EXTI_IMR1_IM5_Pos        (5U)
3840 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
3841 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
3842 #define EXTI_IMR1_IM6_Pos        (6U)
3843 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
3844 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
3845 #define EXTI_IMR1_IM7_Pos        (7U)
3846 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
3847 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
3848 #define EXTI_IMR1_IM8_Pos        (8U)
3849 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
3850 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
3851 #define EXTI_IMR1_IM9_Pos        (9U)
3852 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
3853 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
3854 #define EXTI_IMR1_IM10_Pos       (10U)
3855 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
3856 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
3857 #define EXTI_IMR1_IM11_Pos       (11U)
3858 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
3859 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
3860 #define EXTI_IMR1_IM12_Pos       (12U)
3861 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
3862 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
3863 #define EXTI_IMR1_IM13_Pos       (13U)
3864 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
3865 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
3866 #define EXTI_IMR1_IM14_Pos       (14U)
3867 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
3868 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
3869 #define EXTI_IMR1_IM15_Pos       (15U)
3870 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
3871 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
3872 #define EXTI_IMR1_IM16_Pos       (16U)
3873 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
3874 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
3875 #define EXTI_IMR1_IM17_Pos       (17U)
3876 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
3877 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
3878 #define EXTI_IMR1_IM18_Pos       (18U)
3879 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
3880 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
3881 #define EXTI_IMR1_IM19_Pos       (19U)
3882 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
3883 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
3884 #define EXTI_IMR1_IM20_Pos       (20U)
3885 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
3886 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
3887 #define EXTI_IMR1_IM21_Pos       (21U)
3888 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
3889 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
3890 #define EXTI_IMR1_IM22_Pos       (22U)
3891 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
3892 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
3893 #define EXTI_IMR1_IM23_Pos       (23U)
3894 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
3895 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
3896 #define EXTI_IMR1_IM24_Pos       (24U)
3897 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
3898 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
3899 #define EXTI_IMR1_IM25_Pos       (25U)
3900 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
3901 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
3902 #define EXTI_IMR1_IM26_Pos       (26U)
3903 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
3904 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
3905 #define EXTI_IMR1_IM27_Pos       (27U)
3906 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
3907 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
3908 #define EXTI_IMR1_IM28_Pos       (28U)
3909 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
3910 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
3911 #define EXTI_IMR1_IM29_Pos       (29U)
3912 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
3913 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
3914 #define EXTI_IMR1_IM30_Pos       (30U)
3915 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
3916 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
3917 #define EXTI_IMR1_IM31_Pos       (31U)
3918 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
3919 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
3920 #define EXTI_IMR1_IM_Pos         (0U)
3921 #define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */
3922 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
3923 
3924 /*******************  Bit definition for EXTI_EMR1 register  ******************/
3925 #define EXTI_EMR1_EM0_Pos        (0U)
3926 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
3927 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
3928 #define EXTI_EMR1_EM1_Pos        (1U)
3929 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
3930 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
3931 #define EXTI_EMR1_EM2_Pos        (2U)
3932 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
3933 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
3934 #define EXTI_EMR1_EM3_Pos        (3U)
3935 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
3936 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
3937 #define EXTI_EMR1_EM4_Pos        (4U)
3938 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
3939 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
3940 #define EXTI_EMR1_EM5_Pos        (5U)
3941 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
3942 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
3943 #define EXTI_EMR1_EM6_Pos        (6U)
3944 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
3945 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
3946 #define EXTI_EMR1_EM7_Pos        (7U)
3947 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
3948 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
3949 #define EXTI_EMR1_EM8_Pos        (8U)
3950 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
3951 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
3952 #define EXTI_EMR1_EM9_Pos        (9U)
3953 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
3954 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
3955 #define EXTI_EMR1_EM10_Pos       (10U)
3956 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
3957 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
3958 #define EXTI_EMR1_EM11_Pos       (11U)
3959 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
3960 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
3961 #define EXTI_EMR1_EM12_Pos       (12U)
3962 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
3963 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
3964 #define EXTI_EMR1_EM13_Pos       (13U)
3965 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
3966 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
3967 #define EXTI_EMR1_EM14_Pos       (14U)
3968 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
3969 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
3970 #define EXTI_EMR1_EM15_Pos       (15U)
3971 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
3972 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
3973 #define EXTI_EMR1_EM16_Pos       (16U)
3974 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
3975 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
3976 #define EXTI_EMR1_EM17_Pos       (17U)
3977 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
3978 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
3979 #define EXTI_EMR1_EM18_Pos       (18U)
3980 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
3981 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
3982 #define EXTI_EMR1_EM19_Pos       (19U)
3983 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
3984 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
3985 #define EXTI_EMR1_EM20_Pos       (20U)
3986 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
3987 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
3988 #define EXTI_EMR1_EM21_Pos       (21U)
3989 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
3990 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
3991 #define EXTI_EMR1_EM22_Pos       (22U)
3992 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
3993 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
3994 #define EXTI_EMR1_EM23_Pos       (23U)
3995 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
3996 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
3997 #define EXTI_EMR1_EM24_Pos       (24U)
3998 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
3999 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
4000 #define EXTI_EMR1_EM25_Pos       (25U)
4001 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
4002 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
4003 #define EXTI_EMR1_EM26_Pos       (26U)
4004 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
4005 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
4006 #define EXTI_EMR1_EM27_Pos       (27U)
4007 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
4008 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
4009 #define EXTI_EMR1_EM28_Pos       (28U)
4010 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
4011 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
4012 #define EXTI_EMR1_EM29_Pos       (29U)
4013 #define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
4014 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
4015 #define EXTI_EMR1_EM30_Pos       (30U)
4016 #define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
4017 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
4018 #define EXTI_EMR1_EM31_Pos       (31U)
4019 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
4020 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
4021 
4022 /******************  Bit definition for EXTI_RTSR1 register  ******************/
4023 #define EXTI_RTSR1_RT0_Pos       (0U)
4024 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
4025 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
4026 #define EXTI_RTSR1_RT1_Pos       (1U)
4027 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
4028 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
4029 #define EXTI_RTSR1_RT2_Pos       (2U)
4030 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
4031 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
4032 #define EXTI_RTSR1_RT3_Pos       (3U)
4033 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
4034 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
4035 #define EXTI_RTSR1_RT4_Pos       (4U)
4036 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
4037 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
4038 #define EXTI_RTSR1_RT5_Pos       (5U)
4039 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
4040 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
4041 #define EXTI_RTSR1_RT6_Pos       (6U)
4042 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
4043 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
4044 #define EXTI_RTSR1_RT7_Pos       (7U)
4045 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
4046 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
4047 #define EXTI_RTSR1_RT8_Pos       (8U)
4048 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
4049 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
4050 #define EXTI_RTSR1_RT9_Pos       (9U)
4051 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
4052 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
4053 #define EXTI_RTSR1_RT10_Pos      (10U)
4054 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
4055 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
4056 #define EXTI_RTSR1_RT11_Pos      (11U)
4057 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
4058 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
4059 #define EXTI_RTSR1_RT12_Pos      (12U)
4060 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
4061 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
4062 #define EXTI_RTSR1_RT13_Pos      (13U)
4063 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
4064 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
4065 #define EXTI_RTSR1_RT14_Pos      (14U)
4066 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
4067 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
4068 #define EXTI_RTSR1_RT15_Pos      (15U)
4069 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
4070 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
4071 #define EXTI_RTSR1_RT16_Pos      (16U)
4072 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
4073 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
4074 #define EXTI_RTSR1_RT17_Pos      (17U)
4075 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
4076 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
4077 #define EXTI_RTSR1_RT19_Pos      (19U)
4078 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
4079 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
4080 #define EXTI_RTSR1_RT20_Pos      (20U)
4081 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
4082 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
4083 #define EXTI_RTSR1_RT21_Pos      (21U)
4084 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
4085 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
4086 #define EXTI_RTSR1_RT22_Pos      (22U)
4087 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
4088 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
4089 #define EXTI_RTSR1_RT29_Pos      (29U)
4090 #define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
4091 #define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
4092 #define EXTI_RTSR1_RT30_Pos      (30U)
4093 #define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
4094 #define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
4095 #define EXTI_RTSR1_RT31_Pos      (31U)
4096 #define EXTI_RTSR1_RT31_Msk      (0x1UL << EXTI_RTSR1_RT31_Pos)                /*!< 0x80000000 */
4097 #define EXTI_RTSR1_RT31          EXTI_RTSR1_RT31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
4098 
4099 /******************  Bit definition for EXTI_FTSR1 register  ******************/
4100 #define EXTI_FTSR1_FT0_Pos       (0U)
4101 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
4102 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
4103 #define EXTI_FTSR1_FT1_Pos       (1U)
4104 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
4105 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
4106 #define EXTI_FTSR1_FT2_Pos       (2U)
4107 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
4108 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
4109 #define EXTI_FTSR1_FT3_Pos       (3U)
4110 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
4111 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
4112 #define EXTI_FTSR1_FT4_Pos       (4U)
4113 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
4114 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
4115 #define EXTI_FTSR1_FT5_Pos       (5U)
4116 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
4117 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
4118 #define EXTI_FTSR1_FT6_Pos       (6U)
4119 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
4120 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
4121 #define EXTI_FTSR1_FT7_Pos       (7U)
4122 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
4123 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
4124 #define EXTI_FTSR1_FT8_Pos       (8U)
4125 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
4126 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
4127 #define EXTI_FTSR1_FT9_Pos       (9U)
4128 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
4129 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
4130 #define EXTI_FTSR1_FT10_Pos      (10U)
4131 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
4132 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
4133 #define EXTI_FTSR1_FT11_Pos      (11U)
4134 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
4135 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
4136 #define EXTI_FTSR1_FT12_Pos      (12U)
4137 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
4138 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
4139 #define EXTI_FTSR1_FT13_Pos      (13U)
4140 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
4141 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
4142 #define EXTI_FTSR1_FT14_Pos      (14U)
4143 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
4144 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
4145 #define EXTI_FTSR1_FT15_Pos      (15U)
4146 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
4147 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
4148 #define EXTI_FTSR1_FT16_Pos      (16U)
4149 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
4150 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
4151 #define EXTI_FTSR1_FT17_Pos      (17U)
4152 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
4153 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
4154 #define EXTI_FTSR1_FT19_Pos      (19U)
4155 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
4156 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
4157 #define EXTI_FTSR1_FT20_Pos      (20U)
4158 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
4159 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
4160 #define EXTI_FTSR1_FT21_Pos      (21U)
4161 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
4162 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
4163 #define EXTI_FTSR1_FT22_Pos      (22U)
4164 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
4165 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
4166 #define EXTI_FTSR1_FT29_Pos      (29U)
4167 #define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
4168 #define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
4169 #define EXTI_FTSR1_FT30_Pos      (30U)
4170 #define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
4171 #define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
4172 #define EXTI_FTSR1_FT31_Pos      (31U)
4173 #define EXTI_FTSR1_FT31_Msk      (0x1UL << EXTI_FTSR1_FT31_Pos)                /*!< 0x80000000 */
4174 #define EXTI_FTSR1_FT31          EXTI_FTSR1_FT31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
4175 
4176 /******************  Bit definition for EXTI_SWIER1 register  *****************/
4177 #define EXTI_SWIER1_SWI0_Pos     (0U)
4178 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
4179 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
4180 #define EXTI_SWIER1_SWI1_Pos     (1U)
4181 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
4182 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
4183 #define EXTI_SWIER1_SWI2_Pos     (2U)
4184 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
4185 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
4186 #define EXTI_SWIER1_SWI3_Pos     (3U)
4187 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
4188 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
4189 #define EXTI_SWIER1_SWI4_Pos     (4U)
4190 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
4191 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
4192 #define EXTI_SWIER1_SWI5_Pos     (5U)
4193 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
4194 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
4195 #define EXTI_SWIER1_SWI6_Pos     (6U)
4196 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
4197 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
4198 #define EXTI_SWIER1_SWI7_Pos     (7U)
4199 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
4200 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
4201 #define EXTI_SWIER1_SWI8_Pos     (8U)
4202 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
4203 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
4204 #define EXTI_SWIER1_SWI9_Pos     (9U)
4205 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
4206 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
4207 #define EXTI_SWIER1_SWI10_Pos    (10U)
4208 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
4209 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
4210 #define EXTI_SWIER1_SWI11_Pos    (11U)
4211 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
4212 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
4213 #define EXTI_SWIER1_SWI12_Pos    (12U)
4214 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
4215 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
4216 #define EXTI_SWIER1_SWI13_Pos    (13U)
4217 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
4218 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
4219 #define EXTI_SWIER1_SWI14_Pos    (14U)
4220 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
4221 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
4222 #define EXTI_SWIER1_SWI15_Pos    (15U)
4223 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
4224 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
4225 #define EXTI_SWIER1_SWI16_Pos    (16U)
4226 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
4227 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
4228 #define EXTI_SWIER1_SWI17_Pos    (17U)
4229 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
4230 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
4231 #define EXTI_SWIER1_SWI19_Pos    (19U)
4232 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
4233 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
4234 #define EXTI_SWIER1_SWI20_Pos    (20U)
4235 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
4236 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
4237 #define EXTI_SWIER1_SWI21_Pos    (21U)
4238 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
4239 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
4240 #define EXTI_SWIER1_SWI22_Pos    (22U)
4241 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
4242 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
4243 #define EXTI_SWIER1_SWI29_Pos    (29U)
4244 #define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
4245 #define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
4246 #define EXTI_SWIER1_SWI30_Pos    (30U)
4247 #define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
4248 #define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
4249 #define EXTI_SWIER1_SWI31_Pos    (31U)
4250 #define EXTI_SWIER1_SWI31_Msk    (0x1UL << EXTI_SWIER1_SWI31_Pos)              /*!< 0x80000000 */
4251 #define EXTI_SWIER1_SWI31        EXTI_SWIER1_SWI31_Msk                         /*!< Software Interrupt on line 31 */
4252 
4253 /*******************  Bit definition for EXTI_PR1 register  *******************/
4254 #define EXTI_PR1_PIF0_Pos        (0U)
4255 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
4256 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
4257 #define EXTI_PR1_PIF1_Pos        (1U)
4258 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
4259 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
4260 #define EXTI_PR1_PIF2_Pos        (2U)
4261 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
4262 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
4263 #define EXTI_PR1_PIF3_Pos        (3U)
4264 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
4265 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
4266 #define EXTI_PR1_PIF4_Pos        (4U)
4267 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
4268 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
4269 #define EXTI_PR1_PIF5_Pos        (5U)
4270 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
4271 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
4272 #define EXTI_PR1_PIF6_Pos        (6U)
4273 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
4274 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
4275 #define EXTI_PR1_PIF7_Pos        (7U)
4276 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
4277 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
4278 #define EXTI_PR1_PIF8_Pos        (8U)
4279 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
4280 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
4281 #define EXTI_PR1_PIF9_Pos        (9U)
4282 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
4283 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
4284 #define EXTI_PR1_PIF10_Pos       (10U)
4285 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
4286 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
4287 #define EXTI_PR1_PIF11_Pos       (11U)
4288 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
4289 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
4290 #define EXTI_PR1_PIF12_Pos       (12U)
4291 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
4292 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
4293 #define EXTI_PR1_PIF13_Pos       (13U)
4294 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
4295 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
4296 #define EXTI_PR1_PIF14_Pos       (14U)
4297 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
4298 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
4299 #define EXTI_PR1_PIF15_Pos       (15U)
4300 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
4301 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
4302 #define EXTI_PR1_PIF16_Pos       (16U)
4303 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
4304 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
4305 #define EXTI_PR1_PIF17_Pos       (17U)
4306 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
4307 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
4308 #define EXTI_PR1_PIF19_Pos       (19U)
4309 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
4310 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
4311 #define EXTI_PR1_PIF20_Pos       (20U)
4312 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
4313 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
4314 #define EXTI_PR1_PIF21_Pos       (21U)
4315 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
4316 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
4317 #define EXTI_PR1_PIF22_Pos       (22U)
4318 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
4319 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
4320 #define EXTI_PR1_PIF29_Pos       (29U)
4321 #define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
4322 #define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
4323 #define EXTI_PR1_PIF30_Pos       (30U)
4324 #define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
4325 #define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
4326 #define EXTI_PR1_PIF31_Pos       (31U)
4327 #define EXTI_PR1_PIF31_Msk       (0x1UL << EXTI_PR1_PIF31_Pos)                 /*!< 0x80000000 */
4328 #define EXTI_PR1_PIF31           EXTI_PR1_PIF31_Msk                            /*!< Pending bit for line 31 */
4329 
4330 /*******************  Bit definition for EXTI_IMR2 register  ******************/
4331 #define EXTI_IMR2_IM32_Pos       (0U)
4332 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
4333 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
4334 #define EXTI_IMR2_IM33_Pos       (1U)
4335 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
4336 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
4337 #define EXTI_IMR2_IM34_Pos       (2U)
4338 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
4339 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
4340 #define EXTI_IMR2_IM35_Pos       (3U)
4341 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
4342 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
4343 #define EXTI_IMR2_IM36_Pos       (4U)
4344 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
4345 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
4346 #define EXTI_IMR2_IM37_Pos       (5U)
4347 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
4348 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
4349 #define EXTI_IMR2_IM38_Pos       (6U)
4350 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
4351 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
4352 #define EXTI_IMR2_IM39_Pos       (7U)
4353 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
4354 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
4355 #define EXTI_IMR2_IM40_Pos       (8U)
4356 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
4357 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
4358 #define EXTI_IMR2_IM41_Pos       (9U)
4359 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
4360 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
4361 #define EXTI_IMR2_IM42_Pos       (10U)
4362 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
4363 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< Interrupt Mask on line 42 */
4364 #define EXTI_IMR2_IM_Pos         (0U)
4365 #define EXTI_IMR2_IM_Msk         (0x7FFUL << EXTI_IMR2_IM_Pos)                 /*!< 0x000007FF */
4366 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
4367 
4368 /*******************  Bit definition for EXTI_EMR2 register  ******************/
4369 #define EXTI_EMR2_EM32_Pos       (0U)
4370 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
4371 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
4372 #define EXTI_EMR2_EM33_Pos       (1U)
4373 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
4374 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
4375 #define EXTI_EMR2_EM34_Pos       (2U)
4376 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
4377 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
4378 #define EXTI_EMR2_EM35_Pos       (3U)
4379 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
4380 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
4381 #define EXTI_EMR2_EM36_Pos       (4U)
4382 #define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
4383 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
4384 #define EXTI_EMR2_EM37_Pos       (5U)
4385 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
4386 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
4387 #define EXTI_EMR2_EM38_Pos       (6U)
4388 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
4389 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
4390 #define EXTI_EMR2_EM39_Pos       (7U)
4391 #define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
4392 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
4393 #define EXTI_EMR2_EM40_Pos       (8U)
4394 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
4395 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
4396 #define EXTI_EMR2_EM41_Pos       (9U)
4397 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
4398 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
4399 #define EXTI_EMR2_EM42_Pos       (10U)
4400 #define EXTI_EMR2_EM42_Msk       (0x1UL << EXTI_EMR2_EM42_Pos)                 /*!< 0x00000400 */
4401 #define EXTI_EMR2_EM42           EXTI_EMR2_EM42_Msk                            /*!< Event Mask on line 42 */
4402 #define EXTI_EMR2_EM_Pos         (0U)
4403 #define EXTI_EMR2_EM_Msk         (0x7FFUL << EXTI_EMR2_EM_Pos)                 /*!< 0x000007FF */
4404 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
4405 
4406 /******************  Bit definition for EXTI_RTSR2 register  ******************/
4407 #define EXTI_RTSR2_RT32_Pos      (0U)
4408 #define EXTI_RTSR2_RT32_Msk      (0x1UL << EXTI_RTSR2_RT32_Pos)                /*!< 0x00000001 */
4409 #define EXTI_RTSR2_RT32          EXTI_RTSR2_RT32_Msk                           /*!< Rising trigger event configuration bit of line 32 */
4410 #define EXTI_RTSR2_RT33_Pos      (1U)
4411 #define EXTI_RTSR2_RT33_Msk      (0x1UL << EXTI_RTSR2_RT33_Pos)                /*!< 0x00000002 */
4412 #define EXTI_RTSR2_RT33          EXTI_RTSR2_RT33_Msk                           /*!< Rising trigger event configuration bit of line 33 */
4413 #define EXTI_RTSR2_RT38_Pos      (6U)
4414 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
4415 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
4416 #define EXTI_RTSR2_RT39_Pos      (7U)
4417 #define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
4418 #define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
4419 #define EXTI_RTSR2_RT40_Pos      (8U)
4420 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
4421 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
4422 #define EXTI_RTSR2_RT41_Pos      (9U)
4423 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
4424 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
4425 
4426 /******************  Bit definition for EXTI_FTSR2 register  ******************/
4427 #define EXTI_FTSR2_FT32_Pos      (0U)
4428 #define EXTI_FTSR2_FT32_Msk      (0x1UL << EXTI_FTSR2_FT32_Pos)                /*!< 0x00000001 */
4429 #define EXTI_FTSR2_FT32          EXTI_FTSR2_FT32_Msk                           /*!< Falling trigger event configuration bit of line 32 */
4430 #define EXTI_FTSR2_FT33_Pos      (1U)
4431 #define EXTI_FTSR2_FT33_Msk      (0x1UL << EXTI_FTSR2_FT33_Pos)                /*!< 0x00000002 */
4432 #define EXTI_FTSR2_FT33          EXTI_FTSR2_FT33_Msk                           /*!< Falling trigger event configuration bit of line 33 */
4433 #define EXTI_FTSR2_FT38_Pos      (6U)
4434 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
4435 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
4436 #define EXTI_FTSR2_FT39_Pos      (7U)
4437 #define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
4438 #define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
4439 #define EXTI_FTSR2_FT40_Pos      (8U)
4440 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
4441 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
4442 #define EXTI_FTSR2_FT41_Pos      (9U)
4443 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
4444 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
4445 
4446 /******************  Bit definition for EXTI_SWIER2 register  *****************/
4447 #define EXTI_SWIER2_SWI32_Pos    (0U)
4448 #define EXTI_SWIER2_SWI32_Msk    (0x1UL << EXTI_SWIER2_SWI32_Pos)              /*!< 0x00000001 */
4449 #define EXTI_SWIER2_SWI32        EXTI_SWIER2_SWI32_Msk                         /*!< Software Interrupt on line 32 */
4450 #define EXTI_SWIER2_SWI33_Pos    (1U)
4451 #define EXTI_SWIER2_SWI33_Msk    (0x1UL << EXTI_SWIER2_SWI33_Pos)              /*!< 0x00000002 */
4452 #define EXTI_SWIER2_SWI33        EXTI_SWIER2_SWI33_Msk                         /*!< Software Interrupt on line 33 */
4453 #define EXTI_SWIER2_SWI38_Pos    (6U)
4454 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
4455 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
4456 #define EXTI_SWIER2_SWI39_Pos    (7U)
4457 #define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
4458 #define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
4459 #define EXTI_SWIER2_SWI40_Pos    (8U)
4460 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
4461 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
4462 #define EXTI_SWIER2_SWI41_Pos    (9U)
4463 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
4464 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
4465 
4466 /*******************  Bit definition for EXTI_PR2 register  *******************/
4467 #define EXTI_PR2_PIF32_Pos       (0U)
4468 #define EXTI_PR2_PIF32_Msk       (0x1UL << EXTI_PR2_PIF32_Pos)                 /*!< 0x00000001 */
4469 #define EXTI_PR2_PIF32           EXTI_PR2_PIF32_Msk                            /*!< Pending bit for line 32 */
4470 #define EXTI_PR2_PIF33_Pos       (1U)
4471 #define EXTI_PR2_PIF33_Msk       (0x1UL << EXTI_PR2_PIF33_Pos)                 /*!< 0x00000002 */
4472 #define EXTI_PR2_PIF33           EXTI_PR2_PIF33_Msk                            /*!< Pending bit for line 33 */
4473 #define EXTI_PR2_PIF38_Pos       (6U)
4474 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
4475 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
4476 #define EXTI_PR2_PIF39_Pos       (7U)
4477 #define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
4478 #define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
4479 #define EXTI_PR2_PIF40_Pos       (8U)
4480 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
4481 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
4482 #define EXTI_PR2_PIF41_Pos       (9U)
4483 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
4484 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
4485 
4486 /******************************************************************************/
4487 /*                                                                            */
4488 /*                 Flexible Datarate Controller Area Network                  */
4489 /*                                                                            */
4490 /******************************************************************************/
4491 /*!<FDCAN control and status registers */
4492 /*****************  Bit definition for FDCAN_CREL register  *******************/
4493 #define FDCAN_CREL_DAY_Pos        (0U)
4494 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
4495 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4496 #define FDCAN_CREL_MON_Pos        (8U)
4497 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
4498 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4499 #define FDCAN_CREL_YEAR_Pos       (16U)
4500 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
4501 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4502 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
4503 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
4504 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
4505 #define FDCAN_CREL_STEP_Pos       (24U)
4506 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
4507 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
4508 #define FDCAN_CREL_REL_Pos        (28U)
4509 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
4510 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
4511 
4512 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4513 #define FDCAN_ENDN_ETV_Pos        (0U)
4514 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
4515 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                    */
4516 
4517 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4518 #define FDCAN_DBTP_DSJW_Pos       (0U)
4519 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
4520 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
4521 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
4522 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
4523 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
4524 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
4525 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
4526 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
4527 #define FDCAN_DBTP_DBRP_Pos       (16U)
4528 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
4529 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
4530 #define FDCAN_DBTP_TDC_Pos        (23U)
4531 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
4532 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
4533 
4534 /*****************  Bit definition for FDCAN_TEST register  *******************/
4535 #define FDCAN_TEST_LBCK_Pos       (4U)
4536 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
4537 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
4538 #define FDCAN_TEST_TX_Pos         (5U)
4539 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
4540 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
4541 #define FDCAN_TEST_RX_Pos         (7U)
4542 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
4543 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
4544 
4545 /*****************  Bit definition for FDCAN_RWD register  ********************/
4546 #define FDCAN_RWD_WDC_Pos         (0U)
4547 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
4548 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
4549 #define FDCAN_RWD_WDV_Pos         (8U)
4550 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
4551 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
4552 
4553 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4554 #define FDCAN_CCCR_INIT_Pos       (0U)
4555 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
4556 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
4557 #define FDCAN_CCCR_CCE_Pos        (1U)
4558 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
4559 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
4560 #define FDCAN_CCCR_ASM_Pos        (2U)
4561 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
4562 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
4563 #define FDCAN_CCCR_CSA_Pos        (3U)
4564 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
4565 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
4566 #define FDCAN_CCCR_CSR_Pos        (4U)
4567 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
4568 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
4569 #define FDCAN_CCCR_MON_Pos        (5U)
4570 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
4571 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
4572 #define FDCAN_CCCR_DAR_Pos        (6U)
4573 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
4574 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
4575 #define FDCAN_CCCR_TEST_Pos       (7U)
4576 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4577 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4578 #define FDCAN_CCCR_FDOE_Pos       (8U)
4579 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4580 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4581 #define FDCAN_CCCR_BRSE_Pos       (9U)
4582 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4583 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4584 #define FDCAN_CCCR_PXHD_Pos       (12U)
4585 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4586 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4587 #define FDCAN_CCCR_EFBI_Pos       (13U)
4588 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4589 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4590 #define FDCAN_CCCR_TXP_Pos        (14U)
4591 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4592 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4593 #define FDCAN_CCCR_NISO_Pos       (15U)
4594 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4595 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4596 
4597 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4598 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4599 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4600 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4601 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4602 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4603 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4604 #define FDCAN_NBTP_NBRP_Pos       (16U)
4605 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4606 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4607 #define FDCAN_NBTP_NSJW_Pos       (25U)
4608 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4609 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4610 
4611 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4612 #define FDCAN_TSCC_TSS_Pos        (0U)
4613 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4614 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4615 #define FDCAN_TSCC_TCP_Pos        (16U)
4616 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4617 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4618 
4619 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4620 #define FDCAN_TSCV_TSC_Pos        (0U)
4621 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4622 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4623 
4624 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4625 #define FDCAN_TOCC_ETOC_Pos       (0U)
4626 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4627 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4628 #define FDCAN_TOCC_TOS_Pos        (1U)
4629 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4630 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4631 #define FDCAN_TOCC_TOP_Pos        (16U)
4632 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4633 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4634 
4635 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4636 #define FDCAN_TOCV_TOC_Pos        (0U)
4637 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4638 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4639 
4640 /*****************  Bit definition for FDCAN_ECR register  *********************/
4641 #define FDCAN_ECR_TEC_Pos         (0U)
4642 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
4643 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4644 #define FDCAN_ECR_REC_Pos         (8U)
4645 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4646 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4647 #define FDCAN_ECR_RP_Pos          (15U)
4648 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4649 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4650 #define FDCAN_ECR_CEL_Pos         (16U)
4651 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4652 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4653 
4654 /*****************  Bit definition for FDCAN_PSR register  *********************/
4655 #define FDCAN_PSR_LEC_Pos         (0U)
4656 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4657 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4658 #define FDCAN_PSR_ACT_Pos         (3U)
4659 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4660 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4661 #define FDCAN_PSR_EP_Pos          (5U)
4662 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4663 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4664 #define FDCAN_PSR_EW_Pos          (6U)
4665 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4666 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4667 #define FDCAN_PSR_BO_Pos          (7U)
4668 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4669 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4670 #define FDCAN_PSR_DLEC_Pos        (8U)
4671 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4672 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4673 #define FDCAN_PSR_RESI_Pos        (11U)
4674 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4675 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4676 #define FDCAN_PSR_RBRS_Pos        (12U)
4677 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4678 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4679 #define FDCAN_PSR_REDL_Pos        (13U)
4680 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4681 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4682 #define FDCAN_PSR_PXE_Pos         (14U)
4683 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4684 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4685 #define FDCAN_PSR_TDCV_Pos        (16U)
4686 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4687 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4688 
4689 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4690 #define FDCAN_TDCR_TDCF_Pos       (0U)
4691 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4692 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4693 #define FDCAN_TDCR_TDCO_Pos       (8U)
4694 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4695 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4696 
4697 /*****************  Bit definition for FDCAN_IR register  **********************/
4698 #define FDCAN_IR_RF0N_Pos         (0U)
4699 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4700 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4701 #define FDCAN_IR_RF0F_Pos         (1U)
4702 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
4703 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4704 #define FDCAN_IR_RF0L_Pos         (2U)
4705 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
4706 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4707 #define FDCAN_IR_RF1N_Pos         (3U)
4708 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
4709 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4710 #define FDCAN_IR_RF1F_Pos         (4U)
4711 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
4712 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4713 #define FDCAN_IR_RF1L_Pos         (5U)
4714 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
4715 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4716 #define FDCAN_IR_HPM_Pos          (6U)
4717 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
4718 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4719 #define FDCAN_IR_TC_Pos           (7U)
4720 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
4721 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4722 #define FDCAN_IR_TCF_Pos          (8U)
4723 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
4724 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4725 #define FDCAN_IR_TFE_Pos          (9U)
4726 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
4727 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4728 #define FDCAN_IR_TEFN_Pos         (10U)
4729 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
4730 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4731 #define FDCAN_IR_TEFF_Pos         (11U)
4732 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
4733 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4734 #define FDCAN_IR_TEFL_Pos         (12U)
4735 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
4736 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4737 #define FDCAN_IR_TSW_Pos          (13U)
4738 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
4739 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4740 #define FDCAN_IR_MRAF_Pos         (14U)
4741 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
4742 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4743 #define FDCAN_IR_TOO_Pos          (15U)
4744 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
4745 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4746 #define FDCAN_IR_ELO_Pos          (16U)
4747 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
4748 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4749 #define FDCAN_IR_EP_Pos           (17U)
4750 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
4751 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4752 #define FDCAN_IR_EW_Pos           (18U)
4753 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
4754 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4755 #define FDCAN_IR_BO_Pos           (19U)
4756 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
4757 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4758 #define FDCAN_IR_WDI_Pos          (20U)
4759 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
4760 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4761 #define FDCAN_IR_PEA_Pos          (21U)
4762 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
4763 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4764 #define FDCAN_IR_PED_Pos          (22U)
4765 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
4766 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4767 #define FDCAN_IR_ARA_Pos          (23U)
4768 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
4769 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4770 
4771 /*****************  Bit definition for FDCAN_IE register  **********************/
4772 #define FDCAN_IE_RF0NE_Pos        (0U)
4773 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4774 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
4775 #define FDCAN_IE_RF0FE_Pos        (1U)
4776 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
4777 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
4778 #define FDCAN_IE_RF0LE_Pos        (2U)
4779 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
4780 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
4781 #define FDCAN_IE_RF1NE_Pos        (3U)
4782 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
4783 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
4784 #define FDCAN_IE_RF1FE_Pos        (4U)
4785 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
4786 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
4787 #define FDCAN_IE_RF1LE_Pos        (5U)
4788 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
4789 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
4790 #define FDCAN_IE_HPME_Pos         (6U)
4791 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
4792 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
4793 #define FDCAN_IE_TCE_Pos          (7U)
4794 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
4795 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
4796 #define FDCAN_IE_TCFE_Pos         (8U)
4797 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
4798 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
4799 #define FDCAN_IE_TFEE_Pos         (9U)
4800 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
4801 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
4802 #define FDCAN_IE_TEFNE_Pos        (10U)
4803 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
4804 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
4805 #define FDCAN_IE_TEFFE_Pos        (11U)
4806 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
4807 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
4808 #define FDCAN_IE_TEFLE_Pos        (12U)
4809 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
4810 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
4811 #define FDCAN_IE_TSWE_Pos         (13U)
4812 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
4813 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
4814 #define FDCAN_IE_MRAFE_Pos        (14U)
4815 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
4816 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
4817 #define FDCAN_IE_TOOE_Pos         (15U)
4818 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
4819 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
4820 #define FDCAN_IE_ELOE_Pos         (16U)
4821 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
4822 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
4823 #define FDCAN_IE_EPE_Pos          (17U)
4824 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
4825 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
4826 #define FDCAN_IE_EWE_Pos          (18U)
4827 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
4828 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
4829 #define FDCAN_IE_BOE_Pos          (19U)
4830 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
4831 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
4832 #define FDCAN_IE_WDIE_Pos         (20U)
4833 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
4834 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
4835 #define FDCAN_IE_PEAE_Pos         (21U)
4836 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
4837 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
4838 #define FDCAN_IE_PEDE_Pos         (22U)
4839 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
4840 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
4841 #define FDCAN_IE_ARAE_Pos         (23U)
4842 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
4843 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
4844 
4845 /*****************  Bit definition for FDCAN_ILS register  **********************/
4846 #define FDCAN_ILS_RXFIFO0_Pos     (0U)
4847 #define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
4848 #define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
4849                                                                                    Rx FIFO 0 is Full
4850                                                                                    Rx FIFO 0 Has New Message                */
4851 #define FDCAN_ILS_RXFIFO1_Pos     (1U)
4852 #define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
4853 #define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
4854                                                                                    Rx FIFO 1 is Full
4855                                                                                    Rx FIFO 1 Has New Message                */
4856 #define FDCAN_ILS_SMSG_Pos        (2U)
4857 #define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
4858 #define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
4859                                                                                    Transmission Completed
4860                                                                                    High Priority Message                    */
4861 #define FDCAN_ILS_TFERR_Pos       (3U)
4862 #define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
4863 #define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
4864                                                                                    Tx Event FIFO Full
4865                                                                                    Tx Event FIFO New Entry
4866                                                                                    Tx FIFO Empty Interrupt Line             */
4867 #define FDCAN_ILS_MISC_Pos        (4U)
4868 #define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
4869 #define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
4870                                                                                     Message RAM Access Failure
4871                                                                                     Timestamp Wraparound                    */
4872 #define FDCAN_ILS_BERR_Pos        (5U)
4873 #define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
4874 #define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
4875                                                                                    Error Logging Overflow                   */
4876 #define FDCAN_ILS_PERR_Pos        (6U)
4877 #define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
4878 #define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
4879                                                                                    Protocol Error in Data Phase Line
4880                                                                                    Protocol Error in Arbitration Phase Line
4881                                                                                    Watchdog Interrupt Line
4882                                                                                    Bus_Off Status
4883                                                                                    Warning Status                           */
4884 
4885 /*****************  Bit definition for FDCAN_ILE register  **********************/
4886 #define FDCAN_ILE_EINT0_Pos       (0U)
4887 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4888 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
4889 #define FDCAN_ILE_EINT1_Pos       (1U)
4890 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4891 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
4892 
4893 /*****************  Bit definition for FDCAN_RXGFC register  ********************/
4894 #define FDCAN_RXGFC_RRFE_Pos      (0U)
4895 #define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
4896 #define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
4897 #define FDCAN_RXGFC_RRFS_Pos      (1U)
4898 #define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
4899 #define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
4900 #define FDCAN_RXGFC_ANFE_Pos      (2U)
4901 #define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
4902 #define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
4903 #define FDCAN_RXGFC_ANFS_Pos      (4U)
4904 #define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
4905 #define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
4906 #define FDCAN_RXGFC_F1OM_Pos      (8U)
4907 #define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
4908 #define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
4909 #define FDCAN_RXGFC_F0OM_Pos      (9U)
4910 #define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
4911 #define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
4912 #define FDCAN_RXGFC_LSS_Pos       (16U)
4913 #define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
4914 #define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
4915 #define FDCAN_RXGFC_LSE_Pos       (24U)
4916 #define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
4917 #define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
4918 
4919 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4920 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4921 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4922 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
4923 
4924 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4925 #define FDCAN_HPMS_BIDX_Pos       (0U)
4926 #define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
4927 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
4928 #define FDCAN_HPMS_MSI_Pos        (6U)
4929 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4930 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
4931 #define FDCAN_HPMS_FIDX_Pos       (8U)
4932 #define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
4933 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
4934 #define FDCAN_HPMS_FLST_Pos       (15U)
4935 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4936 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
4937 
4938 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4939 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4940 #define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
4941 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
4942 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4943 #define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
4944 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
4945 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4946 #define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
4947 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
4948 #define FDCAN_RXF0S_F0F_Pos       (24U)
4949 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4950 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
4951 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4952 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4953 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
4954 
4955 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4956 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4957 #define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
4958 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
4959 
4960 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4961 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4962 #define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
4963 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
4964 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4965 #define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
4966 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
4967 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4968 #define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
4969 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
4970 #define FDCAN_RXF1S_F1F_Pos       (24U)
4971 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4972 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
4973 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4974 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4975 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
4976 
4977 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4978 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4979 #define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
4980 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
4981 
4982 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4983 #define FDCAN_TXBC_TFQM_Pos       (24U)
4984 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
4985 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
4986 
4987 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4988 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4989 #define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
4990 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
4991 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4992 #define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
4993 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
4994 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4995 #define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
4996 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
4997 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4998 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4999 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
5000 
5001 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
5002 #define FDCAN_TXBRP_TRP_Pos       (0U)
5003 #define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
5004 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
5005 
5006 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
5007 #define FDCAN_TXBAR_AR_Pos        (0U)
5008 #define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
5009 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
5010 
5011 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
5012 #define FDCAN_TXBCR_CR_Pos        (0U)
5013 #define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
5014 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
5015 
5016 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
5017 #define FDCAN_TXBTO_TO_Pos        (0U)
5018 #define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
5019 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
5020 
5021 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
5022 #define FDCAN_TXBCF_CF_Pos        (0U)
5023 #define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
5024 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
5025 
5026 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
5027 #define FDCAN_TXBTIE_TIE_Pos      (0U)
5028 #define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
5029 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
5030 
5031 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
5032 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
5033 #define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
5034 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
5035 
5036 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
5037 #define FDCAN_TXEFS_EFFL_Pos      (0U)
5038 #define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
5039 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
5040 #define FDCAN_TXEFS_EFGI_Pos      (8U)
5041 #define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
5042 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
5043 #define FDCAN_TXEFS_EFPI_Pos      (16U)
5044 #define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
5045 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
5046 #define FDCAN_TXEFS_EFF_Pos       (24U)
5047 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
5048 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
5049 #define FDCAN_TXEFS_TEFL_Pos      (25U)
5050 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
5051 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
5052 
5053 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
5054 #define FDCAN_TXEFA_EFAI_Pos      (0U)
5055 #define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
5056 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
5057 
5058 
5059 /*!<FDCAN config registers */
5060 /*****************  Bit definition for FDCAN_CKDIV register  *********************/
5061 #define FDCAN_CKDIV_PDIV_Pos      (0U)
5062 #define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
5063 #define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
5064 
5065 /******************************************************************************/
5066 /*                                                                            */
5067 /*                                    FLASH                                   */
5068 /*                                                                            */
5069 /******************************************************************************/
5070 /*******************  Bits definition for FLASH_ACR register  *****************/
5071 #define FLASH_ACR_LATENCY_Pos             (0U)
5072 #define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
5073 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
5074 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
5075 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
5076 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
5077 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
5078 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
5079 #define FLASH_ACR_LATENCY_5WS             (0x00000005U)
5080 #define FLASH_ACR_LATENCY_6WS             (0x00000006U)
5081 #define FLASH_ACR_LATENCY_7WS             (0x00000007U)
5082 #define FLASH_ACR_LATENCY_8WS             (0x00000008U)
5083 #define FLASH_ACR_LATENCY_9WS             (0x00000009U)
5084 #define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
5085 #define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
5086 #define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
5087 #define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
5088 #define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
5089 #define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
5090 #define FLASH_ACR_PRFTEN_Pos              (8U)
5091 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
5092 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
5093 #define FLASH_ACR_ICEN_Pos                (9U)
5094 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
5095 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
5096 #define FLASH_ACR_DCEN_Pos                (10U)
5097 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
5098 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
5099 #define FLASH_ACR_ICRST_Pos               (11U)
5100 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
5101 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
5102 #define FLASH_ACR_DCRST_Pos               (12U)
5103 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
5104 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
5105 #define FLASH_ACR_RUN_PD_Pos              (13U)
5106 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
5107 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
5108 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
5109 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
5110 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
5111 #define FLASH_ACR_DBG_SWEN_Pos            (18U)
5112 #define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
5113 #define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
5114 
5115 /*******************  Bits definition for FLASH_SR register  ******************/
5116 #define FLASH_SR_EOP_Pos                  (0U)
5117 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
5118 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
5119 #define FLASH_SR_OPERR_Pos                (1U)
5120 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
5121 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
5122 #define FLASH_SR_PROGERR_Pos              (3U)
5123 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
5124 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
5125 #define FLASH_SR_WRPERR_Pos               (4U)
5126 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
5127 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
5128 #define FLASH_SR_PGAERR_Pos               (5U)
5129 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
5130 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
5131 #define FLASH_SR_SIZERR_Pos               (6U)
5132 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
5133 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
5134 #define FLASH_SR_PGSERR_Pos               (7U)
5135 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
5136 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
5137 #define FLASH_SR_MISERR_Pos               (8U)
5138 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
5139 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
5140 #define FLASH_SR_FASTERR_Pos              (9U)
5141 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
5142 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
5143 #define FLASH_SR_RDERR_Pos                (14U)
5144 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
5145 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
5146 #define FLASH_SR_OPTVERR_Pos              (15U)
5147 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
5148 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
5149 #define FLASH_SR_BSY_Pos                  (16U)
5150 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
5151 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
5152 
5153 /*******************  Bits definition for FLASH_CR register  ******************/
5154 #define FLASH_CR_PG_Pos                   (0U)
5155 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
5156 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
5157 #define FLASH_CR_PER_Pos                  (1U)
5158 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
5159 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
5160 #define FLASH_CR_MER1_Pos                 (2U)
5161 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
5162 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
5163 #define FLASH_CR_PNB_Pos                  (3U)
5164 #define FLASH_CR_PNB_Msk                  (0x7FUL << FLASH_CR_PNB_Pos)         /*!< 0x000003F8 */
5165 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
5166 #define FLASH_CR_BKER_Pos                 (11U)
5167 #define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */
5168 #define FLASH_CR_BKER                     FLASH_CR_BKER_Msk
5169 #define FLASH_CR_MER2_Pos                 (15U)
5170 #define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */
5171 #define FLASH_CR_MER2                     FLASH_CR_MER2_Msk
5172 #define FLASH_CR_STRT_Pos                 (16U)
5173 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
5174 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
5175 #define FLASH_CR_OPTSTRT_Pos              (17U)
5176 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
5177 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
5178 #define FLASH_CR_FSTPG_Pos                (18U)
5179 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
5180 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
5181 #define FLASH_CR_EOPIE_Pos                (24U)
5182 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
5183 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
5184 #define FLASH_CR_ERRIE_Pos                (25U)
5185 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
5186 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
5187 #define FLASH_CR_RDERRIE_Pos              (26U)
5188 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
5189 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
5190 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
5191 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
5192 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
5193 #define FLASH_CR_SEC_PROT1_Pos            (28U)
5194 #define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
5195 #define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
5196 #define FLASH_CR_SEC_PROT2_Pos            (29U)
5197 #define FLASH_CR_SEC_PROT2_Msk            (0x1UL << FLASH_CR_SEC_PROT2_Pos)    /*!< 0x20000000 */
5198 #define FLASH_CR_SEC_PROT2                FLASH_CR_SEC_PROT2_Msk
5199 #define FLASH_CR_OPTLOCK_Pos              (30U)
5200 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
5201 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
5202 #define FLASH_CR_LOCK_Pos                 (31U)
5203 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
5204 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
5205 
5206 /*******************  Bits definition for FLASH_ECCR register  ***************/
5207 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
5208 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
5209 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
5210 #define FLASH_ECCR_BK_ECC_Pos             (21U)
5211 #define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00200000 */
5212 #define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk
5213 #define FLASH_ECCR_SYSF_ECC_Pos           (22U)
5214 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
5215 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
5216 #define FLASH_ECCR_ECCIE_Pos              (24U)
5217 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
5218 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
5219 #define FLASH_ECCR_ECCC2_Pos              (28U)
5220 #define FLASH_ECCR_ECCC2_Msk              (0x1UL << FLASH_ECCR_ECCC2_Pos)      /*!< 0x10000000 */
5221 #define FLASH_ECCR_ECCC2                  FLASH_ECCR_ECCC2_Msk
5222 #define FLASH_ECCR_ECCD2_Pos              (29U)
5223 #define FLASH_ECCR_ECCD2_Msk              (0x1UL << FLASH_ECCR_ECCD2_Pos)      /*!< 0x20000000 */
5224 #define FLASH_ECCR_ECCD2                  FLASH_ECCR_ECCD2_Msk
5225 #define FLASH_ECCR_ECCC_Pos               (30U)
5226 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
5227 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
5228 #define FLASH_ECCR_ECCD_Pos               (31U)
5229 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
5230 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
5231 
5232 /*******************  Bits definition for FLASH_OPTR register  ***************/
5233 #define FLASH_OPTR_RDP_Pos                (0U)
5234 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
5235 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
5236 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
5237 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
5238 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
5239 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
5240 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
5241 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
5242 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
5243 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
5244 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
5245 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
5246 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
5247 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
5248 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
5249 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
5250 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
5251 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
5252 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
5253 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
5254 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
5255 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
5256 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
5257 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
5258 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
5259 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
5260 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
5261 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
5262 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
5263 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
5264 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
5265 #define FLASH_OPTR_BFB2_Pos               (20U)
5266 #define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */
5267 #define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk
5268 #define FLASH_OPTR_DBANK_Pos              (22U)
5269 #define FLASH_OPTR_DBANK_Msk              (0x1UL << FLASH_OPTR_DBANK_Pos)      /*!< 0x00400000 */
5270 #define FLASH_OPTR_DBANK                  FLASH_OPTR_DBANK_Msk
5271 #define FLASH_OPTR_nBOOT1_Pos             (23U)
5272 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
5273 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
5274 #define FLASH_OPTR_SRAM_PE_Pos            (24U)
5275 #define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
5276 #define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
5277 #define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
5278 #define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
5279 #define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
5280 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
5281 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
5282 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
5283 #define FLASH_OPTR_nBOOT0_Pos             (27U)
5284 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
5285 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
5286 #define FLASH_OPTR_NRST_MODE_Pos          (28U)
5287 #define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
5288 #define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
5289 #define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
5290 #define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
5291 #define FLASH_OPTR_IRHEN_Pos              (30U)
5292 #define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
5293 #define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
5294 
5295 /******************  Bits definition for FLASH_PCROP1SR register  **********/
5296 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
5297 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
5298 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
5299 
5300 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
5301 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
5302 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
5303 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
5304 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
5305 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
5306 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
5307 
5308 /******************  Bits definition for FLASH_WRP1AR register  ***************/
5309 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
5310 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
5311 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
5312 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
5313 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
5314 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
5315 
5316 /******************  Bits definition for FLASH_WRPB1R register  ***************/
5317 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
5318 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
5319 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
5320 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
5321 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5322 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
5323 
5324 /******************  Bits definition for FLASH_PCROP2SR register  **********/
5325 #define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)
5326 #define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
5327 #define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk
5328 
5329 /******************  Bits definition for FLASH_PCROP2ER register  ***********/
5330 #define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)
5331 #define FLASH_PCROP2ER_PCROP2_END_Msk     (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
5332 #define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk
5333 
5334 /******************  Bits definition for FLASH_WRP2AR register  ***************/
5335 #define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)
5336 #define FLASH_WRP2AR_WRP2A_STRT_Msk       (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
5337 #define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk
5338 #define FLASH_WRP2AR_WRP2A_END_Pos        (16U)
5339 #define FLASH_WRP2AR_WRP2A_END_Msk        (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
5340 #define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk
5341 
5342 /******************  Bits definition for FLASH_WRP2BR register  ***************/
5343 #define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)
5344 #define FLASH_WRP2BR_WRP2B_STRT_Msk       (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
5345 #define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk
5346 #define FLASH_WRP2BR_WRP2B_END_Pos        (16U)
5347 #define FLASH_WRP2BR_WRP2B_END_Msk        (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
5348 #define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk
5349 
5350 /******************  Bits definition for FLASH_SEC1R register  **************/
5351 #define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
5352 #define FLASH_SEC1R_SEC_SIZE1_Msk         (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5353 #define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
5354 #define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
5355 #define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5356 #define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
5357 
5358 /******************  Bits definition for FLASH_SEC2R register  **************/
5359 #define FLASH_SEC2R_SEC_SIZE2_Pos         (0U)
5360 #define FLASH_SEC2R_SEC_SIZE2_Msk         (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
5361 #define FLASH_SEC2R_SEC_SIZE2             FLASH_SEC2R_SEC_SIZE2_Msk
5362 
5363 /******************************************************************************/
5364 /*                                                                            */
5365 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
5366 /*                                                                            */
5367 /******************************************************************************/
5368 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
5369 #define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
5370 #define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
5371 #define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
5372 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5373 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5374 #define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
5375 #define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
5376 #define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
5377 #define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
5378 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
5379 #define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
5380 #define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
5381 #define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
5382 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5383 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5384 #define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
5385 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
5386 #define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
5387 #define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
5388 #define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
5389 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
5390 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
5391 #define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
5392 #define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
5393 #define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
5394 #define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
5395 /******************  Bit definition for FMAC_PARAM register  ******************/
5396 #define FMAC_PARAM_P_Pos              (0U)
5397 #define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
5398 #define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
5399 #define FMAC_PARAM_Q_Pos              (8U)
5400 #define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
5401 #define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
5402 #define FMAC_PARAM_R_Pos              (16U)
5403 #define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
5404 #define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
5405 #define FMAC_PARAM_FUNC_Pos           (24U)
5406 #define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
5407 #define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
5408 #define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
5409 #define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
5410 #define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
5411 #define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
5412 #define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
5413 #define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
5414 #define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
5415 #define FMAC_PARAM_START_Pos          (31U)
5416 #define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
5417 #define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
5418 /********************  Bit definition for FMAC_CR register  *******************/
5419 #define FMAC_CR_RIEN_Pos              (0U)
5420 #define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
5421 #define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
5422 #define FMAC_CR_WIEN_Pos              (1U)
5423 #define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
5424 #define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
5425 #define FMAC_CR_OVFLIEN_Pos           (2U)
5426 #define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
5427 #define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
5428 #define FMAC_CR_UNFLIEN_Pos           (3U)
5429 #define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
5430 #define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
5431 #define FMAC_CR_SATIEN_Pos            (4U)
5432 #define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
5433 #define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
5434 #define FMAC_CR_DMAREN_Pos            (8U)
5435 #define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
5436 #define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
5437 #define FMAC_CR_DMAWEN_Pos            (9U)
5438 #define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
5439 #define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
5440 #define FMAC_CR_CLIPEN_Pos            (15U)
5441 #define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
5442 #define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
5443 #define FMAC_CR_RESET_Pos             (16U)
5444 #define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
5445 #define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
5446 /*******************  Bit definition for FMAC_SR register  ********************/
5447 #define FMAC_SR_YEMPTY_Pos            (0U)
5448 #define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
5449 #define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
5450 #define FMAC_SR_X1FULL_Pos            (1U)
5451 #define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
5452 #define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
5453 #define FMAC_SR_OVFL_Pos              (8U)
5454 #define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
5455 #define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
5456 #define FMAC_SR_UNFL_Pos              (9U)
5457 #define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
5458 #define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
5459 #define FMAC_SR_SAT_Pos               (10U)
5460 #define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
5461 #define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
5462 /******************  Bit definition for FMAC_WDATA register  ******************/
5463 #define FMAC_WDATA_WDATA_Pos          (0U)
5464 #define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
5465 #define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
5466 /******************  Bit definition for FMACX_RDATA register  *****************/
5467 #define FMAC_RDATA_RDATA_Pos          (0U)
5468 #define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
5469 #define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
5470 
5471 /******************************************************************************/
5472 /*                                                                            */
5473 /*                          Flexible Memory Controller                        */
5474 /*                                                                            */
5475 /******************************************************************************/
5476 /******************  Bit definition for FMC_BCR1 register  *******************/
5477 #define FMC_BCR1_CCLKEN_Pos        (20U)
5478 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
5479 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */
5480 #define FMC_BCR1_WFDIS_Pos         (21U)
5481 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
5482 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
5483 
5484 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
5485 #define FMC_BCRx_MBKEN_Pos         (0U)
5486 #define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
5487 #define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
5488 #define FMC_BCRx_MUXEN_Pos         (1U)
5489 #define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
5490 #define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
5491 
5492 #define FMC_BCRx_MTYP_Pos          (2U)
5493 #define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
5494 #define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
5495 #define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
5496 #define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
5497 
5498 #define FMC_BCRx_MWID_Pos          (4U)
5499 #define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
5500 #define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
5501 #define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
5502 #define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
5503 
5504 #define FMC_BCRx_FACCEN_Pos        (6U)
5505 #define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
5506 #define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
5507 #define FMC_BCRx_BURSTEN_Pos       (8U)
5508 #define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
5509 #define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
5510 #define FMC_BCRx_WAITPOL_Pos       (9U)
5511 #define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
5512 #define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
5513 #define FMC_BCRx_WAITCFG_Pos       (11U)
5514 #define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
5515 #define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
5516 #define FMC_BCRx_WREN_Pos          (12U)
5517 #define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
5518 #define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
5519 #define FMC_BCRx_WAITEN_Pos        (13U)
5520 #define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
5521 #define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
5522 #define FMC_BCRx_EXTMOD_Pos        (14U)
5523 #define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
5524 #define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
5525 #define FMC_BCRx_ASYNCWAIT_Pos     (15U)
5526 #define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
5527 #define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
5528 
5529 #define FMC_BCRx_CPSIZE_Pos        (16U)
5530 #define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
5531 #define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
5532 #define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
5533 #define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
5534 #define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
5535 
5536 #define FMC_BCRx_CBURSTRW_Pos      (19U)
5537 #define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
5538 #define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
5539 
5540 #define FMC_BCRx_NBLSET_Pos        (22U)
5541 #define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
5542 #define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!<Byte lane (NBL) setup      */
5543 #define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00500000 */
5544 #define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
5545 
5546 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
5547 #define FMC_BTRx_ADDSET_Pos        (0U)
5548 #define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
5549 #define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
5550 #define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
5551 #define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
5552 #define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
5553 #define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
5554 
5555 #define FMC_BTRx_ADDHLD_Pos        (4U)
5556 #define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
5557 #define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
5558 #define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
5559 #define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
5560 #define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
5561 #define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
5562 
5563 #define FMC_BTRx_DATAST_Pos        (8U)
5564 #define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
5565 #define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
5566 #define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
5567 #define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
5568 #define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
5569 #define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
5570 #define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
5571 #define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
5572 #define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
5573 #define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
5574 
5575 #define FMC_BTRx_BUSTURN_Pos       (16U)
5576 #define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
5577 #define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5578 #define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
5579 #define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
5580 #define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
5581 #define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
5582 
5583 #define FMC_BTRx_CLKDIV_Pos        (20U)
5584 #define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
5585 #define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5586 #define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
5587 #define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
5588 #define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
5589 #define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
5590 
5591 #define FMC_BTRx_DATLAT_Pos        (24U)
5592 #define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
5593 #define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
5594 #define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
5595 #define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
5596 #define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
5597 #define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
5598 
5599 #define FMC_BTRx_ACCMOD_Pos        (28U)
5600 #define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
5601 #define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
5602 #define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
5603 #define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
5604 
5605 #define FMC_BTRx_DATAHLD_Pos       (30U)
5606 #define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
5607 #define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5608 #define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
5609 #define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
5610 
5611 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
5612 #define FMC_BWTRx_ADDSET_Pos       (0U)
5613 #define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
5614 #define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
5615 #define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
5616 #define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
5617 #define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
5618 #define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
5619 
5620 #define FMC_BWTRx_ADDHLD_Pos       (4U)
5621 #define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
5622 #define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5623 #define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
5624 #define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
5625 #define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
5626 #define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
5627 
5628 #define FMC_BWTRx_DATAST_Pos       (8U)
5629 #define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
5630 #define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
5631 #define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
5632 #define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
5633 #define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
5634 #define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
5635 #define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
5636 #define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
5637 #define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
5638 #define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
5639 
5640 #define FMC_BWTRx_BUSTURN_Pos      (16U)
5641 #define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
5642 #define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5643 #define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
5644 #define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
5645 #define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
5646 #define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
5647 
5648 #define FMC_BWTRx_ACCMOD_Pos       (28U)
5649 #define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
5650 #define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
5651 #define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
5652 #define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
5653 
5654 #define FMC_BWTRx_DATAHLD_Pos      (30U)
5655 #define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0xC0000000 */
5656 #define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!<DATAHLD[1:0] bits (Data hold phase duration) */
5657 #define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
5658 #define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
5659 
5660 /******************  Bit definition for FMC_PCSCNTR register ******************/
5661 #define FMC_PCSCNTR_CSCOUNT_Pos    (0U)
5662 #define FMC_PCSCNTR_CSCOUNT_Msk    (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos)       /*!< 0x0000FFFF */
5663 #define FMC_PCSCNTR_CSCOUNT        FMC_PCSCNTR_CSCOUNT_Msk                     /*!<CSCOUNT[15:0] bits (Chip select counter) */
5664 
5665 #define FMC_PCSCNTR_CNTB1EN_Pos    (16U)
5666 #define FMC_PCSCNTR_CNTB1EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos)          /*!< 0x00010000 */
5667 #define FMC_PCSCNTR_CNTB1EN        FMC_PCSCNTR_CNTB1EN_Msk                     /*!<Counter PSRAM/NOR Bank1_1 enable */
5668 
5669 #define FMC_PCSCNTR_CNTB2EN_Pos    (17U)
5670 #define FMC_PCSCNTR_CNTB2EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos)          /*!< 0x00020000 */
5671 #define FMC_PCSCNTR_CNTB2EN        FMC_PCSCNTR_CNTB2EN_Msk                     /*!<Counter PSRAM/NOR Bank1_2 enable */
5672 
5673 #define FMC_PCSCNTR_CNTB3EN_Pos    (18U)
5674 #define FMC_PCSCNTR_CNTB3EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos)          /*!< 0x00040000 */
5675 #define FMC_PCSCNTR_CNTB3EN        FMC_PCSCNTR_CNTB3EN_Msk                     /*!<Counter PSRAM/NOR Bank1_3 enable */
5676 
5677 #define FMC_PCSCNTR_CNTB4EN_Pos    (19U)
5678 #define FMC_PCSCNTR_CNTB4EN_Msk    (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos)          /*!< 0x00080000 */
5679 #define FMC_PCSCNTR_CNTB4EN        FMC_PCSCNTR_CNTB4EN_Msk                     /*!<Counter PSRAM/NOR Bank1_4 enable */
5680 
5681 /******************  Bit definition for FMC_PCR register  ********************/
5682 #define FMC_PCR_PWAITEN_Pos        (1U)
5683 #define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
5684 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
5685 #define FMC_PCR_PBKEN_Pos          (2U)
5686 #define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
5687 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
5688 #define FMC_PCR_PTYP_Pos           (3U)
5689 #define FMC_PCR_PTYP_Msk           (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */
5690 #define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
5691 
5692 #define FMC_PCR_PWID_Pos           (4U)
5693 #define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
5694 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
5695 #define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
5696 #define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
5697 
5698 #define FMC_PCR_ECCEN_Pos          (6U)
5699 #define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
5700 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
5701 
5702 #define FMC_PCR_TCLR_Pos           (9U)
5703 #define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
5704 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
5705 #define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
5706 #define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
5707 #define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
5708 #define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
5709 
5710 #define FMC_PCR_TAR_Pos            (13U)
5711 #define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
5712 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
5713 #define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
5714 #define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
5715 #define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
5716 #define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
5717 
5718 #define FMC_PCR_ECCPS_Pos          (17U)
5719 #define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
5720 #define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
5721 #define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
5722 #define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
5723 #define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */
5724 
5725 /*******************  Bit definition for FMC_SR register  ********************/
5726 #define FMC_SR_IRS_Pos             (0U)
5727 #define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
5728 #define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
5729 #define FMC_SR_ILS_Pos             (1U)
5730 #define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
5731 #define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
5732 #define FMC_SR_IFS_Pos             (2U)
5733 #define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
5734 #define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
5735 #define FMC_SR_IREN_Pos            (3U)
5736 #define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
5737 #define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
5738 #define FMC_SR_ILEN_Pos            (4U)
5739 #define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
5740 #define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
5741 #define FMC_SR_IFEN_Pos            (5U)
5742 #define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
5743 #define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
5744 #define FMC_SR_FEMPT_Pos           (6U)
5745 #define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
5746 #define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
5747 
5748 /******************  Bit definition for FMC_PMEM register  ******************/
5749 #define FMC_PMEM_MEMSET_Pos        (0U)
5750 #define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
5751 #define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
5752 #define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
5753 #define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
5754 #define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
5755 #define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
5756 #define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
5757 #define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
5758 #define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
5759 #define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
5760 
5761 #define FMC_PMEM_MEMWAIT_Pos       (8U)
5762 #define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
5763 #define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
5764 #define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
5765 #define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
5766 #define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
5767 #define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
5768 #define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
5769 #define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
5770 #define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
5771 #define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
5772 
5773 #define FMC_PMEM_MEMHOLD_Pos       (16U)
5774 #define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
5775 #define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
5776 #define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
5777 #define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
5778 #define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
5779 #define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
5780 #define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
5781 #define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
5782 #define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
5783 #define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
5784 
5785 #define FMC_PMEM_MEMHIZ_Pos        (24U)
5786 #define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
5787 #define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
5788 #define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
5789 #define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
5790 #define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
5791 #define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
5792 #define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
5793 #define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
5794 #define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
5795 #define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
5796 
5797 /******************  Bit definition for FMC_PATT register  *******************/
5798 #define FMC_PATT_ATTSET_Pos        (0U)
5799 #define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
5800 #define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
5801 #define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
5802 #define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
5803 #define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
5804 #define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
5805 #define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
5806 #define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
5807 #define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
5808 #define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
5809 
5810 #define FMC_PATT_ATTWAIT_Pos       (8U)
5811 #define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
5812 #define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
5813 #define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
5814 #define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
5815 #define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
5816 #define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
5817 #define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
5818 #define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
5819 #define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
5820 #define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
5821 
5822 #define FMC_PATT_ATTHOLD_Pos       (16U)
5823 #define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
5824 #define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
5825 #define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
5826 #define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
5827 #define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
5828 #define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
5829 #define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
5830 #define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
5831 #define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
5832 #define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
5833 
5834 #define FMC_PATT_ATTHIZ_Pos        (24U)
5835 #define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
5836 #define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
5837 #define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
5838 #define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
5839 #define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
5840 #define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
5841 #define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
5842 #define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
5843 #define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
5844 #define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
5845 
5846 /******************  Bit definition for FMC_ECCR register  *******************/
5847 #define FMC_ECCR_ECC_Pos           (0U)
5848 #define FMC_ECCR_ECC_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)          /*!< 0xFFFFFFFF */
5849 #define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
5850 
5851 /******************************************************************************/
5852 /*                                                                            */
5853 /*                       General Purpose IOs (GPIO)                           */
5854 /*                                                                            */
5855 /******************************************************************************/
5856 /******************  Bits definition for GPIO_MODER register  *****************/
5857 #define GPIO_MODER_MODE0_Pos           (0U)
5858 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
5859 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
5860 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
5861 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
5862 #define GPIO_MODER_MODE1_Pos           (2U)
5863 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
5864 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
5865 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
5866 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
5867 #define GPIO_MODER_MODE2_Pos           (4U)
5868 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
5869 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
5870 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
5871 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
5872 #define GPIO_MODER_MODE3_Pos           (6U)
5873 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
5874 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
5875 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
5876 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
5877 #define GPIO_MODER_MODE4_Pos           (8U)
5878 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
5879 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
5880 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
5881 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
5882 #define GPIO_MODER_MODE5_Pos           (10U)
5883 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
5884 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
5885 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
5886 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
5887 #define GPIO_MODER_MODE6_Pos           (12U)
5888 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
5889 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
5890 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
5891 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
5892 #define GPIO_MODER_MODE7_Pos           (14U)
5893 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
5894 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
5895 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
5896 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
5897 #define GPIO_MODER_MODE8_Pos           (16U)
5898 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
5899 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
5900 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
5901 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
5902 #define GPIO_MODER_MODE9_Pos           (18U)
5903 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
5904 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
5905 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
5906 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
5907 #define GPIO_MODER_MODE10_Pos          (20U)
5908 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
5909 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
5910 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
5911 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
5912 #define GPIO_MODER_MODE11_Pos          (22U)
5913 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
5914 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
5915 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
5916 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
5917 #define GPIO_MODER_MODE12_Pos          (24U)
5918 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
5919 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
5920 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
5921 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
5922 #define GPIO_MODER_MODE13_Pos          (26U)
5923 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
5924 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
5925 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
5926 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
5927 #define GPIO_MODER_MODE14_Pos          (28U)
5928 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
5929 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
5930 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
5931 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
5932 #define GPIO_MODER_MODE15_Pos          (30U)
5933 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
5934 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
5935 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
5936 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
5937 
5938 /* Legacy defines */
5939 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
5940 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
5941 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
5942 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
5943 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
5944 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
5945 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
5946 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
5947 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
5948 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
5949 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
5950 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
5951 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
5952 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
5953 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
5954 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
5955 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
5956 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
5957 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
5958 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
5959 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
5960 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
5961 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
5962 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
5963 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
5964 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
5965 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
5966 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
5967 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
5968 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
5969 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
5970 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
5971 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
5972 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
5973 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
5974 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
5975 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
5976 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
5977 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
5978 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
5979 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
5980 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
5981 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
5982 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
5983 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
5984 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
5985 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
5986 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
5987 
5988 /******************  Bits definition for GPIO_OTYPER register  ****************/
5989 #define GPIO_OTYPER_OT0_Pos            (0U)
5990 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
5991 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
5992 #define GPIO_OTYPER_OT1_Pos            (1U)
5993 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
5994 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
5995 #define GPIO_OTYPER_OT2_Pos            (2U)
5996 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
5997 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
5998 #define GPIO_OTYPER_OT3_Pos            (3U)
5999 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
6000 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
6001 #define GPIO_OTYPER_OT4_Pos            (4U)
6002 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
6003 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
6004 #define GPIO_OTYPER_OT5_Pos            (5U)
6005 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
6006 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
6007 #define GPIO_OTYPER_OT6_Pos            (6U)
6008 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
6009 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
6010 #define GPIO_OTYPER_OT7_Pos            (7U)
6011 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
6012 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
6013 #define GPIO_OTYPER_OT8_Pos            (8U)
6014 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
6015 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
6016 #define GPIO_OTYPER_OT9_Pos            (9U)
6017 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
6018 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
6019 #define GPIO_OTYPER_OT10_Pos           (10U)
6020 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
6021 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
6022 #define GPIO_OTYPER_OT11_Pos           (11U)
6023 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
6024 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
6025 #define GPIO_OTYPER_OT12_Pos           (12U)
6026 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
6027 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
6028 #define GPIO_OTYPER_OT13_Pos           (13U)
6029 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
6030 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
6031 #define GPIO_OTYPER_OT14_Pos           (14U)
6032 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
6033 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
6034 #define GPIO_OTYPER_OT15_Pos           (15U)
6035 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
6036 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
6037 
6038 /* Legacy defines */
6039 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
6040 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
6041 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
6042 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
6043 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
6044 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
6045 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
6046 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
6047 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
6048 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
6049 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
6050 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
6051 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
6052 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
6053 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
6054 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
6055 
6056 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
6057 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
6058 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
6059 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
6060 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
6061 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
6062 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
6063 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
6064 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
6065 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
6066 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
6067 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
6068 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
6069 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
6070 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
6071 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
6072 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
6073 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
6074 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
6075 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
6076 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
6077 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
6078 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
6079 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
6080 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
6081 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
6082 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
6083 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
6084 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
6085 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
6086 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
6087 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
6088 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
6089 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
6090 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
6091 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
6092 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
6093 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
6094 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
6095 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
6096 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
6097 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
6098 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
6099 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
6100 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
6101 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
6102 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
6103 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
6104 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
6105 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
6106 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
6107 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
6108 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
6109 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
6110 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
6111 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
6112 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
6113 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
6114 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
6115 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
6116 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
6117 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
6118 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
6119 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
6120 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
6121 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
6122 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
6123 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
6124 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
6125 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
6126 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
6127 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
6128 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
6129 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
6130 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
6131 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
6132 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
6133 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
6134 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
6135 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
6136 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
6137 
6138 /* Legacy defines */
6139 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
6140 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
6141 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
6142 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
6143 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
6144 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
6145 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
6146 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
6147 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
6148 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
6149 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
6150 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
6151 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
6152 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
6153 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
6154 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
6155 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
6156 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
6157 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
6158 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
6159 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
6160 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
6161 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
6162 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
6163 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
6164 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
6165 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
6166 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
6167 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
6168 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
6169 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
6170 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
6171 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
6172 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
6173 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
6174 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
6175 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
6176 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
6177 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
6178 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
6179 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
6180 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
6181 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
6182 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
6183 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
6184 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
6185 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
6186 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
6187 
6188 /******************  Bits definition for GPIO_PUPDR register  *****************/
6189 #define GPIO_PUPDR_PUPD0_Pos           (0U)
6190 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
6191 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
6192 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
6193 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
6194 #define GPIO_PUPDR_PUPD1_Pos           (2U)
6195 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
6196 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
6197 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
6198 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
6199 #define GPIO_PUPDR_PUPD2_Pos           (4U)
6200 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
6201 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
6202 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
6203 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
6204 #define GPIO_PUPDR_PUPD3_Pos           (6U)
6205 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
6206 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
6207 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
6208 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
6209 #define GPIO_PUPDR_PUPD4_Pos           (8U)
6210 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
6211 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
6212 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
6213 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
6214 #define GPIO_PUPDR_PUPD5_Pos           (10U)
6215 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
6216 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
6217 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
6218 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
6219 #define GPIO_PUPDR_PUPD6_Pos           (12U)
6220 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
6221 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
6222 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
6223 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
6224 #define GPIO_PUPDR_PUPD7_Pos           (14U)
6225 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
6226 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
6227 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
6228 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
6229 #define GPIO_PUPDR_PUPD8_Pos           (16U)
6230 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
6231 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
6232 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
6233 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
6234 #define GPIO_PUPDR_PUPD9_Pos           (18U)
6235 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
6236 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
6237 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
6238 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
6239 #define GPIO_PUPDR_PUPD10_Pos          (20U)
6240 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
6241 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
6242 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
6243 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
6244 #define GPIO_PUPDR_PUPD11_Pos          (22U)
6245 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
6246 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
6247 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
6248 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
6249 #define GPIO_PUPDR_PUPD12_Pos          (24U)
6250 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
6251 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
6252 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
6253 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
6254 #define GPIO_PUPDR_PUPD13_Pos          (26U)
6255 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
6256 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
6257 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
6258 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
6259 #define GPIO_PUPDR_PUPD14_Pos          (28U)
6260 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
6261 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
6262 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
6263 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
6264 #define GPIO_PUPDR_PUPD15_Pos          (30U)
6265 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
6266 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
6267 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
6268 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
6269 
6270 /* Legacy defines */
6271 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
6272 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
6273 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
6274 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
6275 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
6276 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
6277 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
6278 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
6279 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
6280 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
6281 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
6282 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
6283 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
6284 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
6285 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
6286 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
6287 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
6288 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
6289 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
6290 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
6291 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
6292 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
6293 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
6294 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
6295 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
6296 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
6297 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
6298 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
6299 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
6300 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
6301 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
6302 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
6303 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
6304 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
6305 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
6306 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
6307 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
6308 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
6309 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
6310 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
6311 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
6312 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
6313 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
6314 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
6315 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
6316 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
6317 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
6318 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
6319 
6320 /******************  Bits definition for GPIO_IDR register  *******************/
6321 #define GPIO_IDR_ID0_Pos               (0U)
6322 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
6323 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
6324 #define GPIO_IDR_ID1_Pos               (1U)
6325 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
6326 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
6327 #define GPIO_IDR_ID2_Pos               (2U)
6328 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
6329 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
6330 #define GPIO_IDR_ID3_Pos               (3U)
6331 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
6332 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
6333 #define GPIO_IDR_ID4_Pos               (4U)
6334 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
6335 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
6336 #define GPIO_IDR_ID5_Pos               (5U)
6337 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
6338 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
6339 #define GPIO_IDR_ID6_Pos               (6U)
6340 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
6341 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
6342 #define GPIO_IDR_ID7_Pos               (7U)
6343 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
6344 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
6345 #define GPIO_IDR_ID8_Pos               (8U)
6346 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
6347 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
6348 #define GPIO_IDR_ID9_Pos               (9U)
6349 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
6350 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
6351 #define GPIO_IDR_ID10_Pos              (10U)
6352 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
6353 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
6354 #define GPIO_IDR_ID11_Pos              (11U)
6355 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
6356 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
6357 #define GPIO_IDR_ID12_Pos              (12U)
6358 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
6359 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
6360 #define GPIO_IDR_ID13_Pos              (13U)
6361 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
6362 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
6363 #define GPIO_IDR_ID14_Pos              (14U)
6364 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
6365 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
6366 #define GPIO_IDR_ID15_Pos              (15U)
6367 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
6368 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
6369 
6370 /* Legacy defines */
6371 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
6372 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
6373 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
6374 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
6375 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
6376 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
6377 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
6378 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
6379 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
6380 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
6381 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
6382 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
6383 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
6384 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
6385 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
6386 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
6387 
6388 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6389 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
6390 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
6391 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
6392 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
6393 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
6394 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
6395 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
6396 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
6397 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
6398 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
6399 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
6400 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
6401 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
6402 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
6403 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
6404 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
6405 
6406 /******************  Bits definition for GPIO_ODR register  *******************/
6407 #define GPIO_ODR_OD0_Pos               (0U)
6408 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
6409 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
6410 #define GPIO_ODR_OD1_Pos               (1U)
6411 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
6412 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
6413 #define GPIO_ODR_OD2_Pos               (2U)
6414 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
6415 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
6416 #define GPIO_ODR_OD3_Pos               (3U)
6417 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
6418 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
6419 #define GPIO_ODR_OD4_Pos               (4U)
6420 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
6421 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
6422 #define GPIO_ODR_OD5_Pos               (5U)
6423 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
6424 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
6425 #define GPIO_ODR_OD6_Pos               (6U)
6426 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
6427 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
6428 #define GPIO_ODR_OD7_Pos               (7U)
6429 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
6430 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
6431 #define GPIO_ODR_OD8_Pos               (8U)
6432 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
6433 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
6434 #define GPIO_ODR_OD9_Pos               (9U)
6435 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
6436 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
6437 #define GPIO_ODR_OD10_Pos              (10U)
6438 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
6439 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
6440 #define GPIO_ODR_OD11_Pos              (11U)
6441 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
6442 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
6443 #define GPIO_ODR_OD12_Pos              (12U)
6444 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
6445 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
6446 #define GPIO_ODR_OD13_Pos              (13U)
6447 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
6448 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
6449 #define GPIO_ODR_OD14_Pos              (14U)
6450 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
6451 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
6452 #define GPIO_ODR_OD15_Pos              (15U)
6453 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
6454 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
6455 
6456 /* Legacy defines */
6457 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
6458 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
6459 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
6460 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
6461 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
6462 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
6463 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
6464 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
6465 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
6466 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
6467 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
6468 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
6469 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
6470 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
6471 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
6472 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
6473 
6474 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6475 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
6476 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
6477 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
6478 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
6479 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
6480 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
6481 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
6482 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
6483 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
6484 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
6485 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
6486 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
6487 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
6488 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
6489 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
6490 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
6491 
6492 /******************  Bits definition for GPIO_BSRR register  ******************/
6493 #define GPIO_BSRR_BS0_Pos              (0U)
6494 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
6495 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
6496 #define GPIO_BSRR_BS1_Pos              (1U)
6497 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
6498 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
6499 #define GPIO_BSRR_BS2_Pos              (2U)
6500 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
6501 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
6502 #define GPIO_BSRR_BS3_Pos              (3U)
6503 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
6504 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
6505 #define GPIO_BSRR_BS4_Pos              (4U)
6506 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
6507 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
6508 #define GPIO_BSRR_BS5_Pos              (5U)
6509 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
6510 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
6511 #define GPIO_BSRR_BS6_Pos              (6U)
6512 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
6513 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
6514 #define GPIO_BSRR_BS7_Pos              (7U)
6515 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
6516 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
6517 #define GPIO_BSRR_BS8_Pos              (8U)
6518 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
6519 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
6520 #define GPIO_BSRR_BS9_Pos              (9U)
6521 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
6522 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
6523 #define GPIO_BSRR_BS10_Pos             (10U)
6524 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
6525 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
6526 #define GPIO_BSRR_BS11_Pos             (11U)
6527 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
6528 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
6529 #define GPIO_BSRR_BS12_Pos             (12U)
6530 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
6531 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
6532 #define GPIO_BSRR_BS13_Pos             (13U)
6533 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
6534 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
6535 #define GPIO_BSRR_BS14_Pos             (14U)
6536 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
6537 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
6538 #define GPIO_BSRR_BS15_Pos             (15U)
6539 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
6540 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
6541 #define GPIO_BSRR_BR0_Pos              (16U)
6542 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
6543 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
6544 #define GPIO_BSRR_BR1_Pos              (17U)
6545 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
6546 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
6547 #define GPIO_BSRR_BR2_Pos              (18U)
6548 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
6549 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
6550 #define GPIO_BSRR_BR3_Pos              (19U)
6551 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
6552 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
6553 #define GPIO_BSRR_BR4_Pos              (20U)
6554 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
6555 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
6556 #define GPIO_BSRR_BR5_Pos              (21U)
6557 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
6558 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
6559 #define GPIO_BSRR_BR6_Pos              (22U)
6560 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
6561 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
6562 #define GPIO_BSRR_BR7_Pos              (23U)
6563 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
6564 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
6565 #define GPIO_BSRR_BR8_Pos              (24U)
6566 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
6567 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
6568 #define GPIO_BSRR_BR9_Pos              (25U)
6569 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
6570 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
6571 #define GPIO_BSRR_BR10_Pos             (26U)
6572 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
6573 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
6574 #define GPIO_BSRR_BR11_Pos             (27U)
6575 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
6576 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
6577 #define GPIO_BSRR_BR12_Pos             (28U)
6578 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
6579 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
6580 #define GPIO_BSRR_BR13_Pos             (29U)
6581 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
6582 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
6583 #define GPIO_BSRR_BR14_Pos             (30U)
6584 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
6585 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
6586 #define GPIO_BSRR_BR15_Pos             (31U)
6587 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
6588 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
6589 
6590 /* Legacy defines */
6591 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
6592 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
6593 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
6594 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
6595 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
6596 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
6597 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
6598 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
6599 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
6600 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
6601 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
6602 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
6603 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
6604 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
6605 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
6606 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
6607 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
6608 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
6609 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
6610 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
6611 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
6612 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
6613 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
6614 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
6615 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
6616 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
6617 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
6618 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
6619 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
6620 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
6621 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
6622 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
6623 
6624 /****************** Bit definition for GPIO_LCKR register *********************/
6625 #define GPIO_LCKR_LCK0_Pos             (0U)
6626 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6627 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
6628 #define GPIO_LCKR_LCK1_Pos             (1U)
6629 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6630 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
6631 #define GPIO_LCKR_LCK2_Pos             (2U)
6632 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6633 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
6634 #define GPIO_LCKR_LCK3_Pos             (3U)
6635 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6636 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
6637 #define GPIO_LCKR_LCK4_Pos             (4U)
6638 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6639 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
6640 #define GPIO_LCKR_LCK5_Pos             (5U)
6641 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6642 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
6643 #define GPIO_LCKR_LCK6_Pos             (6U)
6644 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6645 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
6646 #define GPIO_LCKR_LCK7_Pos             (7U)
6647 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6648 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
6649 #define GPIO_LCKR_LCK8_Pos             (8U)
6650 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6651 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
6652 #define GPIO_LCKR_LCK9_Pos             (9U)
6653 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6654 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
6655 #define GPIO_LCKR_LCK10_Pos            (10U)
6656 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6657 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
6658 #define GPIO_LCKR_LCK11_Pos            (11U)
6659 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6660 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
6661 #define GPIO_LCKR_LCK12_Pos            (12U)
6662 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6663 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
6664 #define GPIO_LCKR_LCK13_Pos            (13U)
6665 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6666 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
6667 #define GPIO_LCKR_LCK14_Pos            (14U)
6668 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6669 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
6670 #define GPIO_LCKR_LCK15_Pos            (15U)
6671 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6672 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
6673 #define GPIO_LCKR_LCKK_Pos             (16U)
6674 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6675 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
6676 
6677 /****************** Bit definition for GPIO_AFRL register *********************/
6678 #define GPIO_AFRL_AFSEL0_Pos           (0U)
6679 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6680 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
6681 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6682 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6683 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6684 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6685 #define GPIO_AFRL_AFSEL1_Pos           (4U)
6686 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6687 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
6688 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6689 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6690 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6691 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6692 #define GPIO_AFRL_AFSEL2_Pos           (8U)
6693 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6694 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
6695 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6696 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6697 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6698 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6699 #define GPIO_AFRL_AFSEL3_Pos           (12U)
6700 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6701 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
6702 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6703 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6704 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6705 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6706 #define GPIO_AFRL_AFSEL4_Pos           (16U)
6707 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6708 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
6709 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6710 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6711 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6712 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6713 #define GPIO_AFRL_AFSEL5_Pos           (20U)
6714 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6715 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
6716 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6717 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6718 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6719 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6720 #define GPIO_AFRL_AFSEL6_Pos           (24U)
6721 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6722 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
6723 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6724 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6725 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6726 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6727 #define GPIO_AFRL_AFSEL7_Pos           (28U)
6728 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6729 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
6730 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6731 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6732 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6733 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6734 
6735 /* Legacy defines */
6736 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
6737 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
6738 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
6739 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
6740 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
6741 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
6742 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
6743 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
6744 
6745 /****************** Bit definition for GPIO_AFRH register *********************/
6746 #define GPIO_AFRH_AFSEL8_Pos           (0U)
6747 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6748 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
6749 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6750 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6751 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6752 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6753 #define GPIO_AFRH_AFSEL9_Pos           (4U)
6754 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6755 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
6756 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6757 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6758 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6759 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6760 #define GPIO_AFRH_AFSEL10_Pos          (8U)
6761 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6762 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
6763 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6764 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6765 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6766 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6767 #define GPIO_AFRH_AFSEL11_Pos          (12U)
6768 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6769 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
6770 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6771 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6772 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6773 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6774 #define GPIO_AFRH_AFSEL12_Pos          (16U)
6775 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6776 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
6777 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6778 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6779 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6780 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6781 #define GPIO_AFRH_AFSEL13_Pos          (20U)
6782 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6783 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
6784 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6785 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6786 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6787 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6788 #define GPIO_AFRH_AFSEL14_Pos          (24U)
6789 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6790 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
6791 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6792 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6793 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6794 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6795 #define GPIO_AFRH_AFSEL15_Pos          (28U)
6796 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6797 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
6798 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6799 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6800 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6801 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6802 
6803 /* Legacy defines */
6804 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
6805 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
6806 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
6807 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
6808 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
6809 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
6810 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
6811 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
6812 
6813 /******************  Bits definition for GPIO_BRR register  ******************/
6814 #define GPIO_BRR_BR0_Pos               (0U)
6815 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6816 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
6817 #define GPIO_BRR_BR1_Pos               (1U)
6818 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6819 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
6820 #define GPIO_BRR_BR2_Pos               (2U)
6821 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6822 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
6823 #define GPIO_BRR_BR3_Pos               (3U)
6824 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6825 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
6826 #define GPIO_BRR_BR4_Pos               (4U)
6827 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6828 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
6829 #define GPIO_BRR_BR5_Pos               (5U)
6830 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6831 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
6832 #define GPIO_BRR_BR6_Pos               (6U)
6833 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6834 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
6835 #define GPIO_BRR_BR7_Pos               (7U)
6836 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6837 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
6838 #define GPIO_BRR_BR8_Pos               (8U)
6839 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6840 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
6841 #define GPIO_BRR_BR9_Pos               (9U)
6842 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6843 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
6844 #define GPIO_BRR_BR10_Pos              (10U)
6845 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6846 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
6847 #define GPIO_BRR_BR11_Pos              (11U)
6848 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6849 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
6850 #define GPIO_BRR_BR12_Pos              (12U)
6851 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6852 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
6853 #define GPIO_BRR_BR13_Pos              (13U)
6854 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6855 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
6856 #define GPIO_BRR_BR14_Pos              (14U)
6857 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6858 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
6859 #define GPIO_BRR_BR15_Pos              (15U)
6860 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6861 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
6862 
6863 /* Legacy defines */
6864 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
6865 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
6866 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
6867 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
6868 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
6869 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
6870 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
6871 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
6872 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
6873 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
6874 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
6875 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
6876 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
6877 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
6878 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
6879 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
6880 
6881 /******************************************************************************/
6882 /*                                                                            */
6883 /*                        High Resolution Timer (HRTIM)                       */
6884 /*                                                                            */
6885 /******************************************************************************/
6886 /******************** Master Timer control register ***************************/
6887 #define HRTIM_MCR_CK_PSC_Pos          (0U)
6888 #define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
6889 #define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
6890 #define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000001 */
6891 #define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000002 */
6892 #define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000004 */
6893 #define HRTIM_MCR_CONT_Pos            (3U)
6894 #define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
6895 #define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
6896 #define HRTIM_MCR_RETRIG_Pos          (4U)
6897 #define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
6898 #define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
6899 #define HRTIM_MCR_HALF_Pos            (5U)
6900 #define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
6901 #define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
6902 #define HRTIM_MCR_INTLVD_Pos          (6U)
6903 #define HRTIM_MCR_INTLVD_Msk          (0x3UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x000000C0 */
6904 #define HRTIM_MCR_INTLVD              HRTIM_MCR_INTLVD_Msk                     /*!< Interleaved mode */
6905 #define HRTIM_MCR_INTLVD_0            (0x1UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x00000040 */
6906 #define HRTIM_MCR_INTLVD_1            (0x2UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x00000080 */
6907 #define HRTIM_MCR_SYNC_IN_Pos         (8U)
6908 #define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
6909 #define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
6910 #define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000100 */
6911 #define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000200 */
6912 #define HRTIM_MCR_SYNCRSTM_Pos        (10U)
6913 #define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
6914 #define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
6915 #define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
6916 #define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
6917 #define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
6918 #define HRTIM_MCR_SYNC_OUT_Pos        (12U)
6919 #define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
6920 #define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
6921 #define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00001000 */
6922 #define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00002000 */
6923 #define HRTIM_MCR_SYNC_SRC_Pos        (14U)
6924 #define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
6925 #define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
6926 #define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x00004000 */
6927 #define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x00008000 */
6928 #define HRTIM_MCR_MCEN_Pos            (16U)
6929 #define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
6930 #define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
6931 #define HRTIM_MCR_TACEN_Pos           (17U)
6932 #define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
6933 #define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
6934 #define HRTIM_MCR_TBCEN_Pos           (18U)
6935 #define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
6936 #define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
6937 #define HRTIM_MCR_TCCEN_Pos           (19U)
6938 #define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
6939 #define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
6940 #define HRTIM_MCR_TDCEN_Pos           (20U)
6941 #define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
6942 #define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
6943 #define HRTIM_MCR_TECEN_Pos           (21U)
6944 #define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
6945 #define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
6946 #define HRTIM_MCR_TFCEN_Pos           (22U)
6947 #define HRTIM_MCR_TFCEN_Msk           (0x1UL << HRTIM_MCR_TFCEN_Pos)           /*!< 0x00400000 */
6948 #define HRTIM_MCR_TFCEN               HRTIM_MCR_TFCEN_Msk                      /*!< Timer F counter enable */
6949 #define HRTIM_MCR_DACSYNC_Pos         (25U)
6950 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
6951 #define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
6952 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x02000000 */
6953 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x04000000 */
6954 #define HRTIM_MCR_PREEN_Pos           (27U)
6955 #define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
6956 #define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
6957 #define HRTIM_MCR_MREPU_Pos           (29U)
6958 #define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
6959 #define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
6960 #define HRTIM_MCR_BRSTDMA_Pos         (30U)
6961 #define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
6962 #define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
6963 #define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0x40000000 */
6964 #define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0x80000000 */
6965 
6966 /******************** Master Timer Interrupt status register ******************/
6967 #define HRTIM_MISR_MCMP1_Pos          (0U)
6968 #define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
6969 #define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
6970 #define HRTIM_MISR_MCMP2_Pos          (1U)
6971 #define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
6972 #define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
6973 #define HRTIM_MISR_MCMP3_Pos          (2U)
6974 #define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
6975 #define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
6976 #define HRTIM_MISR_MCMP4_Pos          (3U)
6977 #define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
6978 #define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
6979 #define HRTIM_MISR_MREP_Pos           (4U)
6980 #define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
6981 #define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
6982 #define HRTIM_MISR_SYNC_Pos           (5U)
6983 #define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
6984 #define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
6985 #define HRTIM_MISR_MUPD_Pos           (6U)
6986 #define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
6987 #define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
6988 
6989 /******************** Master Timer Interrupt clear register *******************/
6990 #define HRTIM_MICR_MCMP1_Pos          (0U)
6991 #define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
6992 #define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
6993 #define HRTIM_MICR_MCMP2_Pos          (1U)
6994 #define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
6995 #define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
6996 #define HRTIM_MICR_MCMP3_Pos          (2U)
6997 #define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
6998 #define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
6999 #define HRTIM_MICR_MCMP4_Pos          (3U)
7000 #define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
7001 #define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
7002 #define HRTIM_MICR_MREP_Pos           (4U)
7003 #define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
7004 #define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
7005 #define HRTIM_MICR_SYNC_Pos           (5U)
7006 #define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
7007 #define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
7008 #define HRTIM_MICR_MUPD_Pos           (6U)
7009 #define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
7010 #define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
7011 
7012 /******************** Master Timer DMA/Interrupt enable register **************/
7013 #define HRTIM_MDIER_MCMP1IE_Pos       (0U)
7014 #define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
7015 #define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
7016 #define HRTIM_MDIER_MCMP2IE_Pos       (1U)
7017 #define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
7018 #define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
7019 #define HRTIM_MDIER_MCMP3IE_Pos       (2U)
7020 #define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
7021 #define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
7022 #define HRTIM_MDIER_MCMP4IE_Pos       (3U)
7023 #define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
7024 #define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
7025 #define HRTIM_MDIER_MREPIE_Pos        (4U)
7026 #define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
7027 #define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
7028 #define HRTIM_MDIER_SYNCIE_Pos        (5U)
7029 #define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
7030 #define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
7031 #define HRTIM_MDIER_MUPDIE_Pos        (6U)
7032 #define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
7033 #define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
7034 #define HRTIM_MDIER_MCMP1DE_Pos       (16U)
7035 #define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
7036 #define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
7037 #define HRTIM_MDIER_MCMP2DE_Pos       (17U)
7038 #define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
7039 #define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
7040 #define HRTIM_MDIER_MCMP3DE_Pos       (18U)
7041 #define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
7042 #define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
7043 #define HRTIM_MDIER_MCMP4DE_Pos       (19U)
7044 #define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
7045 #define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
7046 #define HRTIM_MDIER_MREPDE_Pos        (20U)
7047 #define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
7048 #define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
7049 #define HRTIM_MDIER_SYNCDE_Pos        (21U)
7050 #define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
7051 #define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
7052 #define HRTIM_MDIER_MUPDDE_Pos        (22U)
7053 #define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
7054 #define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
7055 
7056 /*******************  Bit definition for HRTIM_MCNTR register  ****************/
7057 #define HRTIM_MCNTR_MCNTR_Pos         (0U)
7058 #define HRTIM_MCNTR_MCNTR_Msk         (0x0000FFFFUL << HRTIM_MCNTR_MCNTR_Pos)  /*!< 0x0000FFFF */
7059 #define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
7060 
7061 /*******************  Bit definition for HRTIM_MPER register  *****************/
7062 #define HRTIM_MPER_MPER_Pos           (0U)
7063 #define HRTIM_MPER_MPER_Msk           (0x0000FFFFUL << HRTIM_MPER_MPER_Pos)    /*!< 0x0000FFFF */
7064 #define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
7065 
7066 /*******************  Bit definition for HRTIM_MREP register  *****************/
7067 #define HRTIM_MREP_MREP_Pos           (0U)
7068 #define HRTIM_MREP_MREP_Msk           (0x000000FFUL << HRTIM_MREP_MREP_Pos)    /*!< 0x000000FF */
7069 #define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
7070 
7071 /*******************  Bit definition for HRTIM_MCMP1R register  *****************/
7072 #define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
7073 #define HRTIM_MCMP1R_MCMP1R_Msk       (0x0000FFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)/*!< 0x0000FFFF */
7074 #define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
7075 
7076 /*******************  Bit definition for HRTIM_MCMP2R register  *****************/
7077 #define HRTIM_MCMP2R_MCMP2R_Pos       (0U)
7078 #define HRTIM_MCMP2R_MCMP2R_Msk       (0x0000FFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)/*!< 0x0000FFFF */
7079 #define HRTIM_MCMP2R_MCMP2R           HRTIM_MCMP2R_MCMP2R_Msk                  /*!<Compare Value */
7080 
7081 /*******************  Bit definition for HRTIM_MCMP3R register  *****************/
7082 #define HRTIM_MCMP3R_MCMP3R_Pos       (0U)
7083 #define HRTIM_MCMP3R_MCMP3R_Msk       (0x0000FFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)/*!< 0x0000FFFF */
7084 #define HRTIM_MCMP3R_MCMP3R           HRTIM_MCMP3R_MCMP3R_Msk                  /*!<Compare Value */
7085 
7086 /*******************  Bit definition for HRTIM_MCMP4R register  *****************/
7087 #define HRTIM_MCMP4R_MCMP4R_Pos       (0U)
7088 #define HRTIM_MCMP4R_MCMP4R_Msk       (0x0000FFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)/*!< 0x0000FFFF */
7089 #define HRTIM_MCMP4R_MCMP4R           HRTIM_MCMP4R_MCMP4R_Msk                  /*!<Compare Value */
7090 
7091 /* Legacy defines */
7092 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
7093 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
7094 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
7095 
7096 /******************** Slave control register **********************************/
7097 #define HRTIM_TIMCR_CK_PSC_Pos        (0U)
7098 #define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
7099 #define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
7100 #define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000001 */
7101 #define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000002 */
7102 #define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000004 */
7103 #define HRTIM_TIMCR_CONT_Pos          (3U)
7104 #define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
7105 #define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
7106 #define HRTIM_TIMCR_RETRIG_Pos        (4U)
7107 #define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
7108 #define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
7109 #define HRTIM_TIMCR_HALF_Pos          (5U)
7110 #define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
7111 #define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
7112 #define HRTIM_TIMCR_PSHPLL_Pos        (6U)
7113 #define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
7114 #define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
7115 #define HRTIM_TIMCR_INTLVD_Pos        (7U)
7116 #define HRTIM_TIMCR_INTLVD_Msk        (0x3UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000180 */
7117 #define HRTIM_TIMCR_INTLVD            HRTIM_TIMCR_INTLVD_Msk                   /*!< Interleaved mode */
7118 #define HRTIM_TIMCR_INTLVD_0          (0x1UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000080 */
7119 #define HRTIM_TIMCR_INTLVD_1          (0x2UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000100 */
7120 #define HRTIM_TIMCR_RSYNCU_Pos        (9U)
7121 #define HRTIM_TIMCR_RSYNCU_Msk        (0x1UL << HRTIM_TIMCR_RSYNCU_Pos)        /*!< 0x00000200 */
7122 #define HRTIM_TIMCR_RSYNCU            HRTIM_TIMCR_RSYNCU_Msk                   /*!< Resynchronization update */
7123 #define HRTIM_TIMCR_SYNCRST_Pos       (10U)
7124 #define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
7125 #define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
7126 #define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
7127 #define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
7128 #define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
7129 #define HRTIM_TIMCR_DELCMP2_Pos       (12U)
7130 #define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
7131 #define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
7132 #define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00001000 */
7133 #define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00002000 */
7134 #define HRTIM_TIMCR_DELCMP4_Pos       (14U)
7135 #define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
7136 #define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
7137 #define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x00004000 */
7138 #define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x00008000 */
7139 #define HRTIM_TIMCR_TFU_Pos           (16U)
7140 #define HRTIM_TIMCR_TFU_Msk           (0x1UL << HRTIM_TIMCR_TFU_Pos)           /*!< 0x00010000 */
7141 #define HRTIM_TIMCR_TFU               HRTIM_TIMCR_TFU_Msk                      /*!< Slave Timer F update reserved for TIM F */
7142 #define HRTIM_TIMCR_TREPU_Pos         (17U)
7143 #define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
7144 #define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
7145 #define HRTIM_TIMCR_TRSTU_Pos         (18U)
7146 #define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
7147 #define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
7148 #define HRTIM_TIMCR_TAU_Pos           (19U)
7149 #define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
7150 #define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
7151 #define HRTIM_TIMCR_TBU_Pos           (20U)
7152 #define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
7153 #define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
7154 #define HRTIM_TIMCR_TCU_Pos           (21U)
7155 #define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
7156 #define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
7157 #define HRTIM_TIMCR_TDU_Pos           (22U)
7158 #define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
7159 #define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
7160 #define HRTIM_TIMCR_TEU_Pos           (23U)
7161 #define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
7162 #define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
7163 #define HRTIM_TIMCR_MSTU_Pos          (24U)
7164 #define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x02000000 */
7165 #define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
7166 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
7167 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
7168 #define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
7169 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x02000000 */
7170 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x04000000 */
7171 #define HRTIM_TIMCR_PREEN_Pos         (27U)
7172 #define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
7173 #define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
7174 #define HRTIM_TIMCR_UPDGAT_Pos        (28U)
7175 #define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
7176 #define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
7177 #define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x10000000 */
7178 #define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x20000000 */
7179 #define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x40000000 */
7180 #define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x80000000 */
7181 
7182 /******************** Slave Interrupt status register **************************/
7183 #define HRTIM_TIMISR_CMP1_Pos         (0U)
7184 #define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
7185 #define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
7186 #define HRTIM_TIMISR_CMP2_Pos         (1U)
7187 #define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
7188 #define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
7189 #define HRTIM_TIMISR_CMP3_Pos         (2U)
7190 #define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
7191 #define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
7192 #define HRTIM_TIMISR_CMP4_Pos         (3U)
7193 #define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
7194 #define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
7195 #define HRTIM_TIMISR_REP_Pos          (4U)
7196 #define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
7197 #define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
7198 #define HRTIM_TIMISR_UPD_Pos          (6U)
7199 #define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
7200 #define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
7201 #define HRTIM_TIMISR_CPT1_Pos         (7U)
7202 #define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
7203 #define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
7204 #define HRTIM_TIMISR_CPT2_Pos         (8U)
7205 #define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
7206 #define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
7207 #define HRTIM_TIMISR_SET1_Pos         (9U)
7208 #define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
7209 #define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
7210 #define HRTIM_TIMISR_RST1_Pos         (10U)
7211 #define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
7212 #define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
7213 #define HRTIM_TIMISR_SET2_Pos         (11U)
7214 #define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
7215 #define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
7216 #define HRTIM_TIMISR_RST2_Pos         (12U)
7217 #define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
7218 #define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
7219 #define HRTIM_TIMISR_RST_Pos          (13U)
7220 #define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
7221 #define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
7222 #define HRTIM_TIMISR_DLYPRT_Pos       (14U)
7223 #define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
7224 #define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
7225 #define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
7226 #define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
7227 #define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
7228 #define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
7229 #define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
7230 #define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
7231 #define HRTIM_TIMISR_O1STAT_Pos       (18U)
7232 #define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
7233 #define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
7234 #define HRTIM_TIMISR_O2STAT_Pos       (19U)
7235 #define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
7236 #define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
7237 #define HRTIM_TIMISR_O1CPY_Pos        (20U)
7238 #define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
7239 #define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
7240 #define HRTIM_TIMISR_O2CPY_Pos        (21U)
7241 #define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
7242 #define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
7243 
7244 /******************** Slave Interrupt clear register **************************/
7245 #define HRTIM_TIMICR_CMP1C_Pos        (0U)
7246 #define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
7247 #define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
7248 #define HRTIM_TIMICR_CMP2C_Pos        (1U)
7249 #define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
7250 #define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
7251 #define HRTIM_TIMICR_CMP3C_Pos        (2U)
7252 #define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
7253 #define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
7254 #define HRTIM_TIMICR_CMP4C_Pos        (3U)
7255 #define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
7256 #define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
7257 #define HRTIM_TIMICR_REPC_Pos         (4U)
7258 #define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
7259 #define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
7260 #define HRTIM_TIMICR_UPDC_Pos         (6U)
7261 #define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
7262 #define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
7263 #define HRTIM_TIMICR_CPT1C_Pos        (7U)
7264 #define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
7265 #define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
7266 #define HRTIM_TIMICR_CPT2C_Pos        (8U)
7267 #define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
7268 #define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
7269 #define HRTIM_TIMICR_SET1C_Pos        (9U)
7270 #define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
7271 #define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
7272 #define HRTIM_TIMICR_RST1C_Pos        (10U)
7273 #define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
7274 #define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
7275 #define HRTIM_TIMICR_SET2C_Pos        (11U)
7276 #define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
7277 #define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
7278 #define HRTIM_TIMICR_RST2C_Pos        (12U)
7279 #define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
7280 #define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
7281 #define HRTIM_TIMICR_RSTC_Pos         (13U)
7282 #define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
7283 #define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
7284 #define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
7285 #define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
7286 #define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output delay protection clear flag */
7287 
7288 /******************** Slave DMA/Interrupt enable register *********************/
7289 #define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
7290 #define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
7291 #define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
7292 #define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
7293 #define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
7294 #define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
7295 #define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
7296 #define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
7297 #define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
7298 #define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
7299 #define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
7300 #define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
7301 #define HRTIM_TIMDIER_REPIE_Pos       (4U)
7302 #define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
7303 #define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
7304 #define HRTIM_TIMDIER_UPDIE_Pos       (6U)
7305 #define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
7306 #define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
7307 #define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
7308 #define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
7309 #define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
7310 #define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
7311 #define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
7312 #define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
7313 #define HRTIM_TIMDIER_SET1IE_Pos      (9U)
7314 #define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
7315 #define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
7316 #define HRTIM_TIMDIER_RST1IE_Pos      (10U)
7317 #define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
7318 #define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
7319 #define HRTIM_TIMDIER_SET2IE_Pos      (11U)
7320 #define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
7321 #define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
7322 #define HRTIM_TIMDIER_RST2IE_Pos      (12U)
7323 #define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
7324 #define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
7325 #define HRTIM_TIMDIER_RSTIE_Pos       (13U)
7326 #define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
7327 #define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
7328 #define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
7329 #define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
7330 #define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
7331 
7332 #define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
7333 #define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
7334 #define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
7335 #define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
7336 #define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
7337 #define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
7338 #define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
7339 #define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
7340 #define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
7341 #define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
7342 #define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
7343 #define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
7344 #define HRTIM_TIMDIER_REPDE_Pos       (20U)
7345 #define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
7346 #define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
7347 #define HRTIM_TIMDIER_UPDDE_Pos       (22U)
7348 #define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
7349 #define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
7350 #define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
7351 #define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
7352 #define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
7353 #define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
7354 #define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
7355 #define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
7356 #define HRTIM_TIMDIER_SET1DE_Pos      (25U)
7357 #define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
7358 #define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
7359 #define HRTIM_TIMDIER_RST1DE_Pos      (26U)
7360 #define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
7361 #define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
7362 #define HRTIM_TIMDIER_SET2DE_Pos      (27U)
7363 #define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
7364 #define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
7365 #define HRTIM_TIMDIER_RST2DE_Pos      (28U)
7366 #define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
7367 #define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
7368 #define HRTIM_TIMDIER_RSTDE_Pos       (29U)
7369 #define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
7370 #define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
7371 #define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
7372 #define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
7373 #define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
7374 
7375 /******************  Bit definition for HRTIM_CNTR register  ****************/
7376 #define HRTIM_CNTR_CNTR_Pos           (0U)
7377 #define HRTIM_CNTR_CNTR_Msk           (0x0000FFFFUL << HRTIM_CNTR_CNTR_Pos)    /*!< 0x0000FFFF */
7378 #define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
7379 
7380 /*******************  Bit definition for HRTIM_PER register  *****************/
7381 #define HRTIM_PER_PER_Pos             (0U)
7382 #define HRTIM_PER_PER_Msk             (0x0000FFFFUL << HRTIM_PER_PER_Pos)      /*!< 0x0000FFFF */
7383 #define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
7384 
7385 /*******************  Bit definition for HRTIM_REP register  *****************/
7386 #define HRTIM_REP_REP_Pos             (0U)
7387 #define HRTIM_REP_REP_Msk             (0x000000FFUL << HRTIM_REP_REP_Pos)      /*!< 0x000000FF */
7388 #define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
7389 
7390 /*******************  Bit definition for HRTIM_CMP1R register  *****************/
7391 #define HRTIM_CMP1R_CMP1R_Pos         (0U)
7392 #define HRTIM_CMP1R_CMP1R_Msk         (0x0000FFFFUL << HRTIM_CMP1R_CMP1R_Pos)  /*!< 0x0000FFFF */
7393 #define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
7394 
7395 /*******************  Bit definition for HRTIM_CMP1CR register  *****************/
7396 #define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
7397 #define HRTIM_CMP1CR_CMP1CR_Msk       (0x0000FFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)/*!< 0x0000FFFF */
7398 #define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
7399 
7400 /*******************  Bit definition for HRTIM_CMP2R register  *****************/
7401 #define HRTIM_CMP2R_CMP2R_Pos         (0U)
7402 #define HRTIM_CMP2R_CMP2R_Msk         (0x0000FFFFUL << HRTIM_CMP2R_CMP2R_Pos)  /*!< 0x0000FFFF */
7403 #define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
7404 
7405 /*******************  Bit definition for HRTIM_CMP3R register  *****************/
7406 #define HRTIM_CMP3R_CMP3R_Pos         (0U)
7407 #define HRTIM_CMP3R_CMP3R_Msk         (0x0000FFFFUL << HRTIM_CMP3R_CMP3R_Pos)  /*!< 0x0000FFFF */
7408 #define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
7409 
7410 /*******************  Bit definition for HRTIM_CMP4R register  *****************/
7411 #define HRTIM_CMP4R_CMP4R_Pos         (0U)
7412 #define HRTIM_CMP4R_CMP4R_Msk         (0x0000FFFFUL << HRTIM_CMP4R_CMP4R_Pos)  /*!< 0x0000FFFF */
7413 #define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
7414 
7415 /*******************  Bit definition for HRTIM_CPT1R register  ****************/
7416 #define HRTIM_CPT1R_CPT1R_Pos         (0U)
7417 #define HRTIM_CPT1R_CPT1R_Msk         (0x0000FFFFUL << HRTIM_CPT1R_CPT1R_Pos)  /*!< 0x0000FFFF */
7418 #define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture 1 Value */
7419 #define HRTIM_CPT1R_DIR_Pos           (16U)
7420 #define HRTIM_CPT1R_DIR_Msk           (0x1UL << HRTIM_CPT1R_DIR_Pos)           /*!< 0x00010000 */
7421 #define HRTIM_CPT1R_DIR               HRTIM_CPT1R_DIR_Msk                      /*!< Capture 1 direction> */
7422 
7423 /*******************  Bit definition for HRTIM_CPT2R register  ****************/
7424 #define HRTIM_CPT2R_CPT2R_Pos         (0U)
7425 #define HRTIM_CPT2R_CPT2R_Msk         (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos)  /*!< 0x0000FFFF */
7426 #define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture 2 Value */
7427 #define HRTIM_CPT2R_DIR_Pos           (16U)
7428 #define HRTIM_CPT2R_DIR_Msk           (0x1UL << HRTIM_CPT2R_DIR_Pos)           /*!< 0x00010000 */
7429 #define HRTIM_CPT2R_DIR               HRTIM_CPT2R_DIR_Msk                      /*!< Capture 2 direction */
7430 
7431 /******************** Bit definition for Slave Deadtime register **************/
7432 #define HRTIM_DTR_DTR_Pos             (0U)
7433 #define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
7434 #define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
7435 #define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000001 */
7436 #define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000002 */
7437 #define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000004 */
7438 #define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000008 */
7439 #define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000010 */
7440 #define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000020 */
7441 #define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000040 */
7442 #define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000080 */
7443 #define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000100 */
7444 #define HRTIM_DTR_SDTR_Pos            (9U)
7445 #define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
7446 #define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
7447 #define HRTIM_DTR_DTPRSC_Pos          (10U)
7448 #define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
7449 #define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
7450 #define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00000400 */
7451 #define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00000800 */
7452 #define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001000 */
7453 #define HRTIM_DTR_DTRSLK_Pos          (14U)
7454 #define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
7455 #define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
7456 #define HRTIM_DTR_DTRLK_Pos           (15U)
7457 #define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
7458 #define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
7459 #define HRTIM_DTR_DTF_Pos             (16U)
7460 #define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
7461 #define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
7462 #define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00010000 */
7463 #define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00020000 */
7464 #define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00040000 */
7465 #define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00080000 */
7466 #define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00100000 */
7467 #define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00200000 */
7468 #define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00400000 */
7469 #define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00800000 */
7470 #define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)           /*!< 0x01000000 */
7471 #define HRTIM_DTR_SDTF_Pos            (25U)
7472 #define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
7473 #define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
7474 #define HRTIM_DTR_DTFSLK_Pos          (30U)
7475 #define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
7476 #define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
7477 #define HRTIM_DTR_DTFLK_Pos           (31U)
7478 #define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
7479 #define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
7480 
7481 /**** Bit definition for Slave Output 1 set register **************************/
7482 #define HRTIM_SET1R_SST_Pos           (0U)
7483 #define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
7484 #define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
7485 #define HRTIM_SET1R_RESYNC_Pos        (1U)
7486 #define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
7487 #define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
7488 #define HRTIM_SET1R_PER_Pos           (2U)
7489 #define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
7490 #define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
7491 #define HRTIM_SET1R_CMP1_Pos          (3U)
7492 #define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
7493 #define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
7494 #define HRTIM_SET1R_CMP2_Pos          (4U)
7495 #define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
7496 #define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
7497 #define HRTIM_SET1R_CMP3_Pos          (5U)
7498 #define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
7499 #define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
7500 #define HRTIM_SET1R_CMP4_Pos          (6U)
7501 #define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
7502 #define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
7503 
7504 #define HRTIM_SET1R_MSTPER_Pos        (7U)
7505 #define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
7506 #define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
7507 #define HRTIM_SET1R_MSTCMP1_Pos       (8U)
7508 #define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
7509 #define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
7510 #define HRTIM_SET1R_MSTCMP2_Pos       (9U)
7511 #define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
7512 #define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
7513 #define HRTIM_SET1R_MSTCMP3_Pos       (10U)
7514 #define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
7515 #define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
7516 #define HRTIM_SET1R_MSTCMP4_Pos       (11U)
7517 #define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
7518 #define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
7519 
7520 #define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
7521 #define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7522 #define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7523 #define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
7524 #define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7525 #define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7526 #define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
7527 #define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7528 #define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7529 #define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
7530 #define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7531 #define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7532 #define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
7533 #define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7534 #define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7535 #define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
7536 #define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7537 #define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7538 #define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
7539 #define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7540 #define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7541 #define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
7542 #define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7543 #define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7544 #define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
7545 #define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7546 #define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7547 
7548 #define HRTIM_SET1R_EXTVNT1_Pos       (21U)
7549 #define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
7550 #define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
7551 #define HRTIM_SET1R_EXTVNT2_Pos       (22U)
7552 #define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
7553 #define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
7554 #define HRTIM_SET1R_EXTVNT3_Pos       (23U)
7555 #define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
7556 #define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
7557 #define HRTIM_SET1R_EXTVNT4_Pos       (24U)
7558 #define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
7559 #define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
7560 #define HRTIM_SET1R_EXTVNT5_Pos       (25U)
7561 #define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
7562 #define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
7563 #define HRTIM_SET1R_EXTVNT6_Pos       (26U)
7564 #define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
7565 #define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
7566 #define HRTIM_SET1R_EXTVNT7_Pos       (27U)
7567 #define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
7568 #define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
7569 #define HRTIM_SET1R_EXTVNT8_Pos       (28U)
7570 #define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
7571 #define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
7572 #define HRTIM_SET1R_EXTVNT9_Pos       (29U)
7573 #define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
7574 #define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
7575 #define HRTIM_SET1R_EXTVNT10_Pos      (30U)
7576 #define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
7577 #define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
7578 
7579 #define HRTIM_SET1R_UPDATE_Pos        (31U)
7580 #define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
7581 #define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7582 
7583 /**** Bit definition for Slave Output 1 reset register ************************/
7584 #define HRTIM_RST1R_SRT_Pos           (0U)
7585 #define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
7586 #define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
7587 #define HRTIM_RST1R_RESYNC_Pos        (1U)
7588 #define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
7589 #define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
7590 #define HRTIM_RST1R_PER_Pos           (2U)
7591 #define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
7592 #define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
7593 #define HRTIM_RST1R_CMP1_Pos          (3U)
7594 #define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
7595 #define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
7596 #define HRTIM_RST1R_CMP2_Pos          (4U)
7597 #define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
7598 #define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
7599 #define HRTIM_RST1R_CMP3_Pos          (5U)
7600 #define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
7601 #define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
7602 #define HRTIM_RST1R_CMP4_Pos          (6U)
7603 #define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
7604 #define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
7605 
7606 #define HRTIM_RST1R_MSTPER_Pos        (7U)
7607 #define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
7608 #define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
7609 #define HRTIM_RST1R_MSTCMP1_Pos       (8U)
7610 #define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
7611 #define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
7612 #define HRTIM_RST1R_MSTCMP2_Pos       (9U)
7613 #define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
7614 #define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
7615 #define HRTIM_RST1R_MSTCMP3_Pos       (10U)
7616 #define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
7617 #define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
7618 #define HRTIM_RST1R_MSTCMP4_Pos       (11U)
7619 #define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
7620 #define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
7621 
7622 #define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
7623 #define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7624 #define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7625 #define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
7626 #define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7627 #define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7628 #define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
7629 #define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7630 #define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7631 #define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
7632 #define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7633 #define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7634 #define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
7635 #define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7636 #define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7637 #define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
7638 #define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7639 #define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7640 #define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
7641 #define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7642 #define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7643 #define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
7644 #define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7645 #define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7646 #define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
7647 #define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7648 #define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7649 
7650 #define HRTIM_RST1R_EXTVNT1_Pos       (21U)
7651 #define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
7652 #define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
7653 #define HRTIM_RST1R_EXTVNT2_Pos       (22U)
7654 #define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
7655 #define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
7656 #define HRTIM_RST1R_EXTVNT3_Pos       (23U)
7657 #define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
7658 #define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
7659 #define HRTIM_RST1R_EXTVNT4_Pos       (24U)
7660 #define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
7661 #define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
7662 #define HRTIM_RST1R_EXTVNT5_Pos       (25U)
7663 #define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
7664 #define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
7665 #define HRTIM_RST1R_EXTVNT6_Pos       (26U)
7666 #define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
7667 #define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
7668 #define HRTIM_RST1R_EXTVNT7_Pos       (27U)
7669 #define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
7670 #define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
7671 #define HRTIM_RST1R_EXTVNT8_Pos       (28U)
7672 #define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
7673 #define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
7674 #define HRTIM_RST1R_EXTVNT9_Pos       (29U)
7675 #define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
7676 #define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
7677 #define HRTIM_RST1R_EXTVNT10_Pos      (30U)
7678 #define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
7679 #define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
7680 #define HRTIM_RST1R_UPDATE_Pos        (31U)
7681 #define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
7682 #define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7683 
7684 /**** Bit definition for Slave Output 2 set register **************************/
7685 #define HRTIM_SET2R_SST_Pos           (0U)
7686 #define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
7687 #define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
7688 #define HRTIM_SET2R_RESYNC_Pos        (1U)
7689 #define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
7690 #define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
7691 #define HRTIM_SET2R_PER_Pos           (2U)
7692 #define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
7693 #define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
7694 #define HRTIM_SET2R_CMP1_Pos          (3U)
7695 #define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
7696 #define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
7697 #define HRTIM_SET2R_CMP2_Pos          (4U)
7698 #define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
7699 #define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
7700 #define HRTIM_SET2R_CMP3_Pos          (5U)
7701 #define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
7702 #define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
7703 #define HRTIM_SET2R_CMP4_Pos          (6U)
7704 #define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
7705 #define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
7706 
7707 #define HRTIM_SET2R_MSTPER_Pos        (7U)
7708 #define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
7709 #define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
7710 #define HRTIM_SET2R_MSTCMP1_Pos       (8U)
7711 #define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
7712 #define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
7713 #define HRTIM_SET2R_MSTCMP2_Pos       (9U)
7714 #define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
7715 #define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
7716 #define HRTIM_SET2R_MSTCMP3_Pos       (10U)
7717 #define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
7718 #define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
7719 #define HRTIM_SET2R_MSTCMP4_Pos       (11U)
7720 #define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
7721 #define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
7722 
7723 #define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
7724 #define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7725 #define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7726 #define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
7727 #define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7728 #define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7729 #define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
7730 #define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7731 #define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7732 #define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
7733 #define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7734 #define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7735 #define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
7736 #define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7737 #define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7738 #define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
7739 #define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7740 #define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7741 #define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
7742 #define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7743 #define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7744 #define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
7745 #define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7746 #define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7747 #define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
7748 #define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7749 #define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7750 
7751 #define HRTIM_SET2R_EXTVNT1_Pos       (21U)
7752 #define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
7753 #define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
7754 #define HRTIM_SET2R_EXTVNT2_Pos       (22U)
7755 #define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
7756 #define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
7757 #define HRTIM_SET2R_EXTVNT3_Pos       (23U)
7758 #define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
7759 #define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
7760 #define HRTIM_SET2R_EXTVNT4_Pos       (24U)
7761 #define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
7762 #define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
7763 #define HRTIM_SET2R_EXTVNT5_Pos       (25U)
7764 #define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
7765 #define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
7766 #define HRTIM_SET2R_EXTVNT6_Pos       (26U)
7767 #define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
7768 #define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
7769 #define HRTIM_SET2R_EXTVNT7_Pos       (27U)
7770 #define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
7771 #define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
7772 #define HRTIM_SET2R_EXTVNT8_Pos       (28U)
7773 #define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
7774 #define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
7775 #define HRTIM_SET2R_EXTVNT9_Pos       (29U)
7776 #define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
7777 #define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
7778 #define HRTIM_SET2R_EXTVNT10_Pos      (30U)
7779 #define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
7780 #define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
7781 
7782 #define HRTIM_SET2R_UPDATE_Pos        (31U)
7783 #define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
7784 #define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7785 
7786 /**** Bit definition for Slave Output 2 reset register ************************/
7787 #define HRTIM_RST2R_SRT_Pos           (0U)
7788 #define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
7789 #define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
7790 #define HRTIM_RST2R_RESYNC_Pos        (1U)
7791 #define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
7792 #define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
7793 #define HRTIM_RST2R_PER_Pos           (2U)
7794 #define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
7795 #define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
7796 #define HRTIM_RST2R_CMP1_Pos          (3U)
7797 #define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
7798 #define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
7799 #define HRTIM_RST2R_CMP2_Pos          (4U)
7800 #define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
7801 #define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
7802 #define HRTIM_RST2R_CMP3_Pos          (5U)
7803 #define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
7804 #define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
7805 #define HRTIM_RST2R_CMP4_Pos          (6U)
7806 #define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
7807 #define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
7808 #define HRTIM_RST2R_MSTPER_Pos        (7U)
7809 #define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
7810 #define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
7811 #define HRTIM_RST2R_MSTCMP1_Pos       (8U)
7812 #define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
7813 #define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
7814 #define HRTIM_RST2R_MSTCMP2_Pos       (9U)
7815 #define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
7816 #define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
7817 #define HRTIM_RST2R_MSTCMP3_Pos       (10U)
7818 #define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
7819 #define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
7820 #define HRTIM_RST2R_MSTCMP4_Pos       (11U)
7821 #define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
7822 #define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
7823 
7824 #define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
7825 #define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7826 #define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7827 #define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
7828 #define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7829 #define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7830 #define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
7831 #define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7832 #define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7833 #define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
7834 #define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7835 #define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7836 #define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
7837 #define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7838 #define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7839 #define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
7840 #define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7841 #define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7842 #define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
7843 #define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7844 #define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7845 #define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
7846 #define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7847 #define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7848 #define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
7849 #define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7850 #define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7851 
7852 #define HRTIM_RST2R_EXTVNT1_Pos       (21U)
7853 #define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
7854 #define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
7855 #define HRTIM_RST2R_EXTVNT2_Pos       (22U)
7856 #define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
7857 #define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
7858 #define HRTIM_RST2R_EXTVNT3_Pos       (23U)
7859 #define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
7860 #define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
7861 #define HRTIM_RST2R_EXTVNT4_Pos       (24U)
7862 #define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
7863 #define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
7864 #define HRTIM_RST2R_EXTVNT5_Pos       (25U)
7865 #define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
7866 #define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
7867 #define HRTIM_RST2R_EXTVNT6_Pos       (26U)
7868 #define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
7869 #define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
7870 #define HRTIM_RST2R_EXTVNT7_Pos       (27U)
7871 #define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
7872 #define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
7873 #define HRTIM_RST2R_EXTVNT8_Pos       (28U)
7874 #define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
7875 #define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
7876 #define HRTIM_RST2R_EXTVNT9_Pos       (29U)
7877 #define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
7878 #define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
7879 #define HRTIM_RST2R_EXTVNT10_Pos      (30U)
7880 #define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
7881 #define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
7882 #define HRTIM_RST2R_UPDATE_Pos        (31U)
7883 #define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
7884 #define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7885 
7886 /**** Bit definition for Slave external event filtering  register 1 ***********/
7887 #define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
7888 #define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
7889 #define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
7890 #define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
7891 #define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
7892 #define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
7893 #define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000002 */
7894 #define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000004 */
7895 #define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000008 */
7896 #define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000010 */
7897 
7898 #define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
7899 #define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
7900 #define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
7901 #define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
7902 #define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
7903 #define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
7904 #define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000080 */
7905 #define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000100 */
7906 #define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000200 */
7907 #define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000400 */
7908 
7909 #define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
7910 #define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
7911 #define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
7912 #define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
7913 #define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
7914 #define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
7915 #define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00002000 */
7916 #define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00004000 */
7917 #define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00008000 */
7918 #define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00010000 */
7919 
7920 #define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
7921 #define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
7922 #define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
7923 #define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
7924 #define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
7925 #define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
7926 #define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00080000 */
7927 #define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00100000 */
7928 #define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00200000 */
7929 #define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00400000 */
7930 
7931 #define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
7932 #define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
7933 #define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
7934 #define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
7935 #define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
7936 #define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
7937 #define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x02000000 */
7938 #define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x04000000 */
7939 #define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x08000000 */
7940 #define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x10000000 */
7941 
7942 /**** Bit definition for Slave external event filtering  register 2 ***********/
7943 #define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
7944 #define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
7945 #define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
7946 #define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
7947 #define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
7948 #define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
7949 #define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000002 */
7950 #define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000004 */
7951 #define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000008 */
7952 #define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000010 */
7953 
7954 #define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
7955 #define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
7956 #define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
7957 #define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
7958 #define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
7959 #define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
7960 #define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000080 */
7961 #define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000100 */
7962 #define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000200 */
7963 #define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000400 */
7964 
7965 #define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
7966 #define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
7967 #define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
7968 #define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
7969 #define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
7970 #define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
7971 #define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00002000 */
7972 #define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00004000 */
7973 #define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00008000 */
7974 #define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00010000 */
7975 
7976 #define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
7977 #define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
7978 #define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
7979 #define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
7980 #define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
7981 #define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
7982 #define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00080000 */
7983 #define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00100000 */
7984 #define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00200000 */
7985 #define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00400000 */
7986 
7987 #define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
7988 #define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
7989 #define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
7990 #define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
7991 #define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
7992 #define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
7993 #define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x02000000 */
7994 #define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x04000000 */
7995 #define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x08000000 */
7996 #define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x10000000 */
7997 
7998 /**** Bit definition for Slave Timer reset register ***************************/
7999 
8000 #define HRTIM_RSTR_TIMFCMP1_Pos       (0U)
8001 #define HRTIM_RSTR_TIMFCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos)       /*!< 0x00000001 */
8002 #define HRTIM_RSTR_TIMFCMP1           HRTIM_RSTR_TIMFCMP1_Msk                  /*!< Timer F compare 1 */
8003 #define HRTIM_RSTR_UPDATE_Pos         (1U)
8004 #define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
8005 #define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
8006 #define HRTIM_RSTR_CMP2_Pos           (2U)
8007 #define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
8008 #define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
8009 #define HRTIM_RSTR_CMP4_Pos           (3U)
8010 #define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
8011 #define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
8012 #define HRTIM_RSTR_MSTPER_Pos         (4U)
8013 #define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
8014 #define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
8015 #define HRTIM_RSTR_MSTCMP1_Pos        (5U)
8016 #define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
8017 #define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
8018 #define HRTIM_RSTR_MSTCMP2_Pos        (6U)
8019 #define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
8020 #define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
8021 #define HRTIM_RSTR_MSTCMP3_Pos        (7U)
8022 #define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
8023 #define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
8024 #define HRTIM_RSTR_MSTCMP4_Pos        (8U)
8025 #define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
8026 #define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
8027 #define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
8028 #define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
8029 #define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
8030 #define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
8031 #define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
8032 #define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
8033 #define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
8034 #define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
8035 #define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
8036 #define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
8037 #define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
8038 #define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
8039 #define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
8040 #define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
8041 #define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
8042 #define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
8043 #define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
8044 #define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
8045 #define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
8046 #define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
8047 #define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
8048 #define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
8049 #define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
8050 #define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
8051 #define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
8052 #define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
8053 #define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
8054 #define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
8055 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
8056 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
8057 
8058 /* Slave Timer A reset enable bits upon other slave timers events */
8059 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
8060 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
8061 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
8062 #define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
8063 #define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
8064 #define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
8065 #define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
8066 #define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
8067 #define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
8068 
8069 #define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
8070 #define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
8071 #define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
8072 #define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
8073 #define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
8074 #define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
8075 #define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
8076 #define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
8077 #define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
8078 
8079 #define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
8080 #define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
8081 #define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
8082 #define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
8083 #define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
8084 #define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
8085 #define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
8086 #define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
8087 #define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
8088 
8089 #define HRTIM_RSTR_TIMECMP1_Pos       (28U)
8090 #define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
8091 #define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
8092 #define HRTIM_RSTR_TIMECMP2_Pos       (29U)
8093 #define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
8094 #define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
8095 #define HRTIM_RSTR_TIMECMP4_Pos       (30U)
8096 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
8097 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
8098 
8099 #define HRTIM_RSTR_TIMFCMP2_Pos       (31U)
8100 #define HRTIM_RSTR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos)       /*!< 0x80000000 */
8101 #define HRTIM_RSTR_TIMFCMP2           HRTIM_RSTR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
8102 
8103 /* Slave Timer B reset enable bits upon other slave timers events */
8104 #define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
8105 #define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)        /*!< 0x00080000 */
8106 #define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
8107 #define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
8108 #define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)        /*!< 0x00100000 */
8109 #define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
8110 #define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
8111 #define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)        /*!< 0x00200000 */
8112 #define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
8113 
8114 #define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
8115 #define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)        /*!< 0x00400000 */
8116 #define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
8117 #define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
8118 #define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)        /*!< 0x00800000 */
8119 #define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
8120 #define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
8121 #define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)        /*!< 0x01000000 */
8122 #define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
8123 
8124 #define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
8125 #define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)        /*!< 0x02000000 */
8126 #define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
8127 #define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
8128 #define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)        /*!< 0x04000000 */
8129 #define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
8130 #define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
8131 #define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)        /*!< 0x08000000 */
8132 #define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
8133 
8134 #define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
8135 #define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)        /*!< 0x10000000 */
8136 #define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
8137 #define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
8138 #define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)        /*!< 0x20000000 */
8139 #define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
8140 #define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
8141 #define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)        /*!< 0x40000000 */
8142 #define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
8143 
8144 #define HRTIM_RSTBR_TIMFCMP2_Pos       (31U)
8145 #define HRTIM_RSTBR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos)       /*!< 0x80000000 */
8146 #define HRTIM_RSTBR_TIMFCMP2           HRTIM_RSTBR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
8147 
8148 /* Slave Timer C reset enable bits upon other slave timers events */
8149 #define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
8150 #define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)        /*!< 0x00080000 */
8151 #define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
8152 #define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
8153 #define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)        /*!< 0x00100000 */
8154 #define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
8155 #define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
8156 #define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)        /*!< 0x00200000 */
8157 #define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
8158 
8159 #define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
8160 #define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)        /*!< 0x00400000 */
8161 #define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
8162 #define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
8163 #define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)        /*!< 0x00800000 */
8164 #define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
8165 #define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
8166 #define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)        /*!< 0x01000000 */
8167 #define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
8168 
8169 #define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
8170 #define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)        /*!< 0x02000000 */
8171 #define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
8172 #define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
8173 #define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)        /*!< 0x04000000 */
8174 #define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
8175 #define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
8176 #define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)        /*!< 0x08000000 */
8177 #define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
8178 
8179 #define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
8180 #define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)        /*!< 0x10000000 */
8181 #define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
8182 #define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
8183 #define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)        /*!< 0x20000000 */
8184 #define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
8185 #define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
8186 #define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)        /*!< 0x40000000 */
8187 #define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
8188 
8189 #define HRTIM_RSTCR_TIMFCMP2_Pos       (31U)
8190 #define HRTIM_RSTCR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos)       /*!< 0x80000000 */
8191 #define HRTIM_RSTCR_TIMFCMP2           HRTIM_RSTCR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
8192 
8193 /* Slave Timer D reset enable bits upon other slave timers events */
8194 #define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
8195 #define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)        /*!< 0x00080000 */
8196 #define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
8197 #define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
8198 #define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)        /*!< 0x00100000 */
8199 #define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
8200 #define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
8201 #define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)        /*!< 0x00200000 */
8202 #define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
8203 
8204 #define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
8205 #define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)        /*!< 0x00400000 */
8206 #define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
8207 #define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
8208 #define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)        /*!< 0x00800000 */
8209 #define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
8210 #define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
8211 #define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)        /*!< 0x01000000 */
8212 #define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
8213 
8214 #define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
8215 #define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)        /*!< 0x02000000 */
8216 #define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
8217 #define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
8218 #define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)        /*!< 0x04000000 */
8219 #define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
8220 #define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
8221 #define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)        /*!< 0x08000000 */
8222 #define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
8223 
8224 #define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
8225 #define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)        /*!< 0x10000000 */
8226 #define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
8227 #define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
8228 #define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)        /*!< 0x20000000 */
8229 #define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
8230 #define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
8231 #define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)        /*!< 0x40000000 */
8232 #define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
8233 
8234 #define HRTIM_RSTDR_TIMFCMP2_Pos       (31U)
8235 #define HRTIM_RSTDR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos)       /*!< 0x80000000 */
8236 #define HRTIM_RSTDR_TIMFCMP2           HRTIM_RSTDR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
8237 
8238 /* Slave Timer E reset enable bits upon other slave timers events */
8239 #define HRTIM_RSTER_TIMACMP1_Pos       (19U)
8240 #define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)        /*!< 0x00080000 */
8241 #define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                  /*!< Timer A compare 1 */
8242 #define HRTIM_RSTER_TIMACMP2_Pos       (20U)
8243 #define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)        /*!< 0x00100000 */
8244 #define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                  /*!< Timer A compare 2 */
8245 #define HRTIM_RSTER_TIMACMP4_Pos       (21U)
8246 #define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)        /*!< 0x00200000 */
8247 #define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                  /*!< Timer A compare 4 */
8248 
8249 #define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
8250 #define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)        /*!< 0x00400000 */
8251 #define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
8252 #define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
8253 #define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)        /*!< 0x00800000 */
8254 #define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
8255 #define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
8256 #define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)        /*!< 0x01000000 */
8257 #define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
8258 
8259 #define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
8260 #define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)        /*!< 0x02000000 */
8261 #define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
8262 #define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
8263 #define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)        /*!< 0x04000000 */
8264 #define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
8265 #define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
8266 #define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)        /*!< 0x08000000 */
8267 #define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
8268 
8269 #define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
8270 #define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)        /*!< 0x10000000 */
8271 #define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
8272 #define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
8273 #define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)        /*!< 0x20000000 */
8274 #define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
8275 #define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
8276 #define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)        /*!< 0x40000000 */
8277 #define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
8278 
8279 #define HRTIM_RSTER_TIMFCMP2_Pos       (31U)
8280 #define HRTIM_RSTER_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos)       /*!< 0x80000000 */
8281 #define HRTIM_RSTER_TIMFCMP2           HRTIM_RSTER_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
8282 
8283 /* Slave Timer F reset enable bits upon other slave timers events */
8284 #define HRTIM_RSTFR_TIMACMP1_Pos       (19U)
8285 #define HRTIM_RSTFR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos)        /*!< 0x00080000 */
8286 #define HRTIM_RSTFR_TIMACMP1           HRTIM_RSTFR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
8287 #define HRTIM_RSTFR_TIMACMP2_Pos       (20U)
8288 #define HRTIM_RSTFR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos)        /*!< 0x00100000 */
8289 #define HRTIM_RSTFR_TIMACMP2           HRTIM_RSTFR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
8290 #define HRTIM_RSTFR_TIMACMP4_Pos       (21U)
8291 #define HRTIM_RSTFR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos)        /*!< 0x00200000 */
8292 #define HRTIM_RSTFR_TIMACMP4           HRTIM_RSTFR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
8293 
8294 #define HRTIM_RSTFR_TIMBCMP1_Pos       (22U)
8295 #define HRTIM_RSTFR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos)        /*!< 0x00400000 */
8296 #define HRTIM_RSTFR_TIMBCMP1           HRTIM_RSTFR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
8297 #define HRTIM_RSTFR_TIMBCMP2_Pos       (23U)
8298 #define HRTIM_RSTFR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos)        /*!< 0x00800000 */
8299 #define HRTIM_RSTFR_TIMBCMP2           HRTIM_RSTFR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
8300 #define HRTIM_RSTFR_TIMBCMP4_Pos       (24U)
8301 #define HRTIM_RSTFR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos)        /*!< 0x01000000 */
8302 #define HRTIM_RSTFR_TIMBCMP4           HRTIM_RSTFR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
8303 
8304 #define HRTIM_RSTFR_TIMCCMP1_Pos       (25U)
8305 #define HRTIM_RSTFR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos)        /*!< 0x02000000 */
8306 #define HRTIM_RSTFR_TIMCCMP1           HRTIM_RSTFR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
8307 #define HRTIM_RSTFR_TIMCCMP2_Pos       (26U)
8308 #define HRTIM_RSTFR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos)        /*!< 0x04000000 */
8309 #define HRTIM_RSTFR_TIMCCMP2           HRTIM_RSTFR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
8310 #define HRTIM_RSTFR_TIMCCMP4_Pos       (27U)
8311 #define HRTIM_RSTFR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos)        /*!< 0x08000000 */
8312 #define HRTIM_RSTFR_TIMCCMP4           HRTIM_RSTFR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
8313 
8314 #define HRTIM_RSTFR_TIMDCMP1_Pos       (28U)
8315 #define HRTIM_RSTFR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos)        /*!< 0x10000000 */
8316 #define HRTIM_RSTFR_TIMDCMP1           HRTIM_RSTFR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
8317 #define HRTIM_RSTFR_TIMDCMP2_Pos       (29U)
8318 #define HRTIM_RSTFR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos)        /*!< 0x20000000 */
8319 #define HRTIM_RSTFR_TIMDCMP2           HRTIM_RSTFR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
8320 #define HRTIM_RSTFR_TIMDCMP4_Pos       (30U)
8321 #define HRTIM_RSTFR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos)        /*!< 0x40000000 */
8322 #define HRTIM_RSTFR_TIMDCMP4           HRTIM_RSTFR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
8323 
8324 #define HRTIM_RSTFR_TIMECMP2_Pos       (31U)
8325 #define HRTIM_RSTFR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos)       /*!< 0x80000000 */
8326 #define HRTIM_RSTFR_TIMECMP2           HRTIM_RSTFR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
8327 
8328 /**** Bit definition for Slave Timer Chopper register *************************/
8329 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
8330 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
8331 #define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
8332 #define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000001 */
8333 #define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000002 */
8334 #define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000004 */
8335 #define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000008 */
8336 
8337 #define HRTIM_CHPR_CARDTY_Pos         (4U)
8338 #define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
8339 #define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
8340 #define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000010 */
8341 #define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000020 */
8342 #define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000040 */
8343 
8344 #define HRTIM_CHPR_STRPW_Pos          (7U)
8345 #define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
8346 #define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
8347 #define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000080 */
8348 #define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000100 */
8349 #define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000200 */
8350 #define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000400 */
8351 
8352 /**** Bit definition for Slave Timer Capture 1 control register ***************/
8353 #define HRTIM_CPT1CR_SWCPT_Pos        (0U)
8354 #define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
8355 #define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
8356 #define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
8357 #define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
8358 #define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
8359 #define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
8360 #define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
8361 #define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
8362 #define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
8363 #define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
8364 #define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
8365 #define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
8366 #define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
8367 #define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
8368 #define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
8369 #define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
8370 #define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
8371 #define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
8372 #define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
8373 #define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
8374 #define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
8375 #define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
8376 #define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
8377 #define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
8378 #define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
8379 #define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
8380 #define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
8381 #define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
8382 #define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
8383 #define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
8384 #define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
8385 #define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
8386 #define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
8387 #define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
8388 #define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
8389 
8390 #define HRTIM_CPT1CR_TF1SET_Pos       (0U)
8391 #define HRTIM_CPT1CR_TF1SET_Msk       (0x1UL << HRTIM_CPT1CR_TF1SET_Pos)       /*!< 0x00000001 */
8392 #define HRTIM_CPT1CR_TF1SET           HRTIM_CPT1CR_TF1SET_Msk                  /*!< Timer F output 1 set */
8393 #define HRTIM_CPT1CR_TF1RST_Pos       (1U)
8394 #define HRTIM_CPT1CR_TF1RST_Msk       (0x1UL << HRTIM_CPT1CR_TF1RST_Pos)       /*!< 0x00000002 */
8395 #define HRTIM_CPT1CR_TF1RST           HRTIM_CPT1CR_TF1RST_Msk                  /*!< Timer F output 1 reset */
8396 #define HRTIM_CPT1CR_TIMFCMP1_Pos     (2U)
8397 #define HRTIM_CPT1CR_TIMFCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos)     /*!< 0x00000004 */
8398 #define HRTIM_CPT1CR_TIMFCMP1         HRTIM_CPT1CR_TIMFCMP1_Msk                /*!< Timer F compare 1 */
8399 #define HRTIM_CPT1CR_TIMFCMP2_Pos     (3U)
8400 #define HRTIM_CPT1CR_TIMFCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos)     /*!< 0x00000008 */
8401 #define HRTIM_CPT1CR_TIMFCMP2         HRTIM_CPT1CR_TIMFCMP2_Msk                /*!< Timer F compare 2 */
8402 
8403 #define HRTIM_CPT1CR_TA1SET_Pos       (12U)
8404 #define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
8405 #define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
8406 #define HRTIM_CPT1CR_TA1RST_Pos       (13U)
8407 #define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
8408 #define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
8409 #define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
8410 #define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
8411 #define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
8412 #define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
8413 #define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
8414 #define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
8415 
8416 #define HRTIM_CPT1CR_TB1SET_Pos       (16U)
8417 #define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
8418 #define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
8419 #define HRTIM_CPT1CR_TB1RST_Pos       (17U)
8420 #define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
8421 #define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
8422 #define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
8423 #define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
8424 #define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
8425 #define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
8426 #define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
8427 #define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
8428 
8429 #define HRTIM_CPT1CR_TC1SET_Pos       (20U)
8430 #define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
8431 #define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
8432 #define HRTIM_CPT1CR_TC1RST_Pos       (21U)
8433 #define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
8434 #define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
8435 #define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
8436 #define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
8437 #define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
8438 #define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
8439 #define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
8440 #define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
8441 
8442 #define HRTIM_CPT1CR_TD1SET_Pos       (24U)
8443 #define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
8444 #define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
8445 #define HRTIM_CPT1CR_TD1RST_Pos       (25U)
8446 #define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
8447 #define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
8448 #define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
8449 #define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
8450 #define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
8451 #define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
8452 #define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
8453 #define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
8454 
8455 #define HRTIM_CPT1CR_TE1SET_Pos       (28U)
8456 #define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
8457 #define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
8458 #define HRTIM_CPT1CR_TE1RST_Pos       (29U)
8459 #define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
8460 #define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
8461 #define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
8462 #define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
8463 #define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
8464 #define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
8465 #define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
8466 #define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
8467 
8468 /**** Bit definition for Slave Timer Capture 2 control register ***************/
8469 #define HRTIM_CPT2CR_SWCPT_Pos        (0U)
8470 #define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
8471 #define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
8472 #define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
8473 #define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
8474 #define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
8475 #define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
8476 #define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
8477 #define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
8478 #define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
8479 #define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
8480 #define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
8481 #define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
8482 #define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
8483 #define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
8484 #define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
8485 #define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
8486 #define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
8487 #define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
8488 #define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
8489 #define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
8490 #define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
8491 #define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
8492 #define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
8493 #define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
8494 #define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
8495 #define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
8496 #define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
8497 #define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
8498 #define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
8499 #define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
8500 #define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
8501 #define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
8502 #define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
8503 #define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
8504 #define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
8505 
8506 #define HRTIM_CPT2CR_TF1SET_Pos       (0U)
8507 #define HRTIM_CPT2CR_TF1SET_Msk       (0x1UL << HRTIM_CPT2CR_TF1SET_Pos)       /*!< 0x00000001 */
8508 #define HRTIM_CPT2CR_TF1SET           HRTIM_CPT2CR_TF1SET_Msk                  /*!< Timer F output 1 set */
8509 #define HRTIM_CPT2CR_TF1RST_Pos       (1U)
8510 #define HRTIM_CPT2CR_TF1RST_Msk       (0x1UL << HRTIM_CPT2CR_TF1RST_Pos)       /*!< 0x00000002 */
8511 #define HRTIM_CPT2CR_TF1RST           HRTIM_CPT2CR_TF1RST_Msk                  /*!< Timer F output 1 reset */
8512 #define HRTIM_CPT2CR_TIMFCMP1_Pos     (2U)
8513 #define HRTIM_CPT2CR_TIMFCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos)     /*!< 0x00000004 */
8514 #define HRTIM_CPT2CR_TIMFCMP1         HRTIM_CPT2CR_TIMFCMP1_Msk                /*!< Timer F compare 1 */
8515 #define HRTIM_CPT2CR_TIMFCMP2_Pos     (3U)
8516 #define HRTIM_CPT2CR_TIMFCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos)     /*!< 0x00000008 */
8517 #define HRTIM_CPT2CR_TIMFCMP2         HRTIM_CPT2CR_TIMFCMP2_Msk                /*!< Timer F compare 2 */
8518 
8519 #define HRTIM_CPT2CR_TA1SET_Pos       (12U)
8520 #define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
8521 #define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
8522 #define HRTIM_CPT2CR_TA1RST_Pos       (13U)
8523 #define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
8524 #define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
8525 #define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
8526 #define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
8527 #define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
8528 #define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
8529 #define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
8530 #define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
8531 
8532 #define HRTIM_CPT2CR_TB1SET_Pos       (16U)
8533 #define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
8534 #define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
8535 #define HRTIM_CPT2CR_TB1RST_Pos       (17U)
8536 #define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
8537 #define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
8538 #define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
8539 #define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
8540 #define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
8541 #define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
8542 #define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
8543 #define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
8544 
8545 #define HRTIM_CPT2CR_TC1SET_Pos       (20U)
8546 #define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
8547 #define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
8548 #define HRTIM_CPT2CR_TC1RST_Pos       (21U)
8549 #define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
8550 #define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
8551 #define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
8552 #define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
8553 #define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
8554 #define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
8555 #define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
8556 #define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
8557 
8558 #define HRTIM_CPT2CR_TD1SET_Pos       (24U)
8559 #define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
8560 #define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
8561 #define HRTIM_CPT2CR_TD1RST_Pos       (25U)
8562 #define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
8563 #define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
8564 #define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
8565 #define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
8566 #define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
8567 #define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
8568 #define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
8569 #define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
8570 
8571 #define HRTIM_CPT2CR_TE1SET_Pos       (28U)
8572 #define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
8573 #define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
8574 #define HRTIM_CPT2CR_TE1RST_Pos       (29U)
8575 #define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
8576 #define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
8577 #define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
8578 #define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
8579 #define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
8580 #define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
8581 #define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
8582 #define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
8583 
8584 /**** Bit definition for Slave Timer Output register **************************/
8585 #define HRTIM_OUTR_POL1_Pos           (1U)
8586 #define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
8587 #define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
8588 #define HRTIM_OUTR_IDLM1_Pos          (2U)
8589 #define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
8590 #define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
8591 #define HRTIM_OUTR_IDLES1_Pos         (3U)
8592 #define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
8593 #define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
8594 #define HRTIM_OUTR_FAULT1_Pos         (4U)
8595 #define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
8596 #define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
8597 #define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000010 */
8598 #define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000020 */
8599 #define HRTIM_OUTR_CHP1_Pos           (6U)
8600 #define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
8601 #define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
8602 #define HRTIM_OUTR_DIDL1_Pos          (7U)
8603 #define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
8604 #define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
8605 
8606 #define HRTIM_OUTR_DTEN_Pos           (8U)
8607 #define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
8608 #define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
8609 #define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
8610 #define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
8611 #define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
8612 #define HRTIM_OUTR_DLYPRT_Pos         (10U)
8613 #define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
8614 #define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
8615 #define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00000400 */
8616 #define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00000800 */
8617 #define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001000 */
8618 #define HRTIM_OUTR_BIAR_Pos           (14U)
8619 #define HRTIM_OUTR_BIAR_Msk           (0x1UL << HRTIM_OUTR_BIAR_Pos)           /*!< 0x00004000 */
8620 #define HRTIM_OUTR_BIAR               HRTIM_OUTR_BIAR_Msk                      /*!< Slave output Balanced Idle Automatic resume */
8621 #define HRTIM_OUTR_POL2_Pos           (17U)
8622 #define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
8623 #define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
8624 #define HRTIM_OUTR_IDLM2_Pos          (18U)
8625 #define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
8626 #define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
8627 #define HRTIM_OUTR_IDLES2_Pos         (19U)
8628 #define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
8629 #define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
8630 #define HRTIM_OUTR_FAULT2_Pos         (20U)
8631 #define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
8632 #define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
8633 #define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00100000 */
8634 #define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00200000 */
8635 #define HRTIM_OUTR_CHP2_Pos           (22U)
8636 #define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
8637 #define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
8638 #define HRTIM_OUTR_DIDL2_Pos          (23U)
8639 #define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
8640 #define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
8641 
8642 /**** Bit definition for Timerx Fault register ***************************/
8643 #define HRTIM_FLTR_FLT1EN_Pos         (0U)
8644 #define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
8645 #define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
8646 #define HRTIM_FLTR_FLT2EN_Pos         (1U)
8647 #define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
8648 #define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
8649 #define HRTIM_FLTR_FLT3EN_Pos         (2U)
8650 #define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
8651 #define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
8652 #define HRTIM_FLTR_FLT4EN_Pos         (3U)
8653 #define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
8654 #define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
8655 #define HRTIM_FLTR_FLT5EN_Pos         (4U)
8656 #define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
8657 #define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
8658 #define HRTIM_FLTR_FLT6EN_Pos         (5U)
8659 #define HRTIM_FLTR_FLT6EN_Msk         (0x1UL << HRTIM_FLTR_FLT6EN_Pos)         /*!< 0x00000020 */
8660 #define HRTIM_FLTR_FLT6EN             HRTIM_FLTR_FLT6EN_Msk                    /*!< Fault 6 enable */
8661 #define HRTIM_FLTR_FLTLCK_Pos         (31U)
8662 #define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
8663 #define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
8664 
8665 /**** Bit definition for HRTIM Timerx control register 2 ****************/
8666 #define HRTIM_TIMCR2_DCDE_Pos           (0U)
8667 #define HRTIM_TIMCR2_DCDE_Msk           (0x1UL << HRTIM_TIMCR2_DCDE_Pos)           /*!< 0x00000001 */
8668 #define HRTIM_TIMCR2_DCDE               HRTIM_TIMCR2_DCDE_Msk                      /*!< Dual Channel DAC trigger enable */
8669 #define HRTIM_TIMCR2_DCDS_Pos           (1U)
8670 #define HRTIM_TIMCR2_DCDS_Msk           (0x1UL << HRTIM_TIMCR2_DCDS_Pos)           /*!< 0x00000002 */
8671 #define HRTIM_TIMCR2_DCDS               HRTIM_TIMCR2_DCDS_Msk                      /*!< Dual Channel DAC step trigger */
8672 #define HRTIM_TIMCR2_DCDR_Pos           (2U)
8673 #define HRTIM_TIMCR2_DCDR_Msk           (0x1UL << HRTIM_TIMCR2_DCDR_Pos)           /*!< 0x00000004 */
8674 #define HRTIM_TIMCR2_DCDR               HRTIM_TIMCR2_DCDR_Msk                      /*!< Dual Channel DAC reset trigger */
8675 #define HRTIM_TIMCR2_UDM_Pos           (4U)
8676 #define HRTIM_TIMCR2_UDM_Msk           (0x1UL << HRTIM_TIMCR2_UDM_Pos)             /*!< 0x00000010 */
8677 #define HRTIM_TIMCR2_UDM               HRTIM_TIMCR2_UDM_Msk                        /*!< Up-Down Mode*/
8678 #define HRTIM_TIMCR2_ROM_Pos           (6U)
8679 #define HRTIM_TIMCR2_ROM_Msk           (0x3UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x000000C0 */
8680 #define HRTIM_TIMCR2_ROM               HRTIM_TIMCR2_ROM_Msk                        /*!< Roll-over Mode */
8681 #define HRTIM_TIMCR2_ROM_0             (0x1UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x00000040 */
8682 #define HRTIM_TIMCR2_ROM_1             (0x2UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x00000080 */
8683 #define HRTIM_TIMCR2_OUTROM_Pos        (8U)
8684 #define HRTIM_TIMCR2_OUTROM_Msk        (0x3UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000300 */
8685 #define HRTIM_TIMCR2_OUTROM            HRTIM_TIMCR2_OUTROM_Msk                     /*!< Output Roll-Over Mode */
8686 #define HRTIM_TIMCR2_OUTROM_0          (0x1UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000100 */
8687 #define HRTIM_TIMCR2_OUTROM_1          (0x2UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000200 */
8688 #define HRTIM_TIMCR2_ADROM_Pos         (10U)
8689 #define HRTIM_TIMCR2_ADROM_Msk         (0x3UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000C00 */
8690 #define HRTIM_TIMCR2_ADROM             HRTIM_TIMCR2_ADROM_Msk                      /*!< ADC Roll-Over Mode */
8691 #define HRTIM_TIMCR2_ADROM_0           (0x1UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000400 */
8692 #define HRTIM_TIMCR2_ADROM_1           (0x2UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000800 */
8693 #define HRTIM_TIMCR2_BMROM_Pos         (12U)
8694 #define HRTIM_TIMCR2_BMROM_Msk         (0x3UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00003000 */
8695 #define HRTIM_TIMCR2_BMROM             HRTIM_TIMCR2_BMROM_Msk                      /*!< Burst Mode Rollover Mode */
8696 #define HRTIM_TIMCR2_BMROM_0           (0x1UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00001000 */
8697 #define HRTIM_TIMCR2_BMROM_1           (0x2UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00002000 */
8698 #define HRTIM_TIMCR2_FEROM_Pos         (14U)
8699 #define HRTIM_TIMCR2_FEROM_Msk         (0x3UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x0000C000 */
8700 #define HRTIM_TIMCR2_FEROM             HRTIM_TIMCR2_FEROM_Msk                      /*!< Fault and Event Rollover Mode */
8701 #define HRTIM_TIMCR2_FEROM_0           (0x1UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x00004000 */
8702 #define HRTIM_TIMCR2_FEROM_1           (0x2UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x00008000 */
8703 #define HRTIM_TIMCR2_GTCMP1_Pos        (16U)
8704 #define HRTIM_TIMCR2_GTCMP1_Msk        (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos)          /*!< 0x00010000 */
8705 #define HRTIM_TIMCR2_GTCMP1            HRTIM_TIMCR2_GTCMP1_Msk                     /*!< Greater than Compare 1 PWM mode */
8706 #define HRTIM_TIMCR2_GTCMP3_Pos        (17U)
8707 #define HRTIM_TIMCR2_GTCMP3_Msk        (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos)          /*!< 0x00020000 */
8708 #define HRTIM_TIMCR2_GTCMP3            HRTIM_TIMCR2_GTCMP3_Msk                     /*!< Greater than Compare 3 PWM mode */
8709 #define HRTIM_TIMCR2_TRGHLF_Pos        (20U)
8710 #define HRTIM_TIMCR2_TRGHLF_Msk        (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos)          /*!< 0x00100000 */
8711 #define HRTIM_TIMCR2_TRGHLF            HRTIM_TIMCR2_TRGHLF_Msk                     /*!< Triggered-Half mode */
8712 
8713 /**** Bit definition for Slave external event filtering  register 3 ***********/
8714 #define HRTIM_EEFR3_EEVACE_Pos        (0U)
8715 #define HRTIM_EEFR3_EEVACE_Msk        (0x1UL << HRTIM_EEFR3_EEVACE_Pos)       /*!< 0x00000001 */
8716 #define HRTIM_EEFR3_EEVACE            HRTIM_EEFR3_EEVACE_Msk                  /*!< External Event A Counter Enable */
8717 #define HRTIM_EEFR3_EEVACRES_Pos      (1U)
8718 #define HRTIM_EEFR3_EEVACRES_Msk      (0x1UL << HRTIM_EEFR3_EEVACRES_Pos)     /*!< 0x00000002 */
8719 #define HRTIM_EEFR3_EEVACRES          HRTIM_EEFR3_EEVACRES_Msk                /*!< External Event A Counter Reset */
8720 #define HRTIM_EEFR3_EEVARSTM_Pos      (2U)
8721 #define HRTIM_EEFR3_EEVARSTM_Msk      (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos)     /*!< 0x00000004 */
8722 #define HRTIM_EEFR3_EEVARSTM          HRTIM_EEFR3_EEVARSTM_Msk                /*!< External Event A Counter Reset Mode */
8723 #define HRTIM_EEFR3_EEVASEL_Pos       (4U)
8724 #define HRTIM_EEFR3_EEVASEL_Msk       (0xFUL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x000000F0 */
8725 #define HRTIM_EEFR3_EEVASEL           HRTIM_EEFR3_EEVASEL_Msk                 /*!< External Event A Selection */
8726 #define HRTIM_EEFR3_EEVASEL_0         (0x1UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000010 */
8727 #define HRTIM_EEFR3_EEVASEL_1         (0x2UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000020 */
8728 #define HRTIM_EEFR3_EEVASEL_2         (0x4UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000040 */
8729 #define HRTIM_EEFR3_EEVASEL_3         (0x8UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000080 */
8730 #define HRTIM_EEFR3_EEVACNT_Pos       (8U)
8731 #define HRTIM_EEFR3_EEVACNT_Msk       (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00003F00 */
8732 #define HRTIM_EEFR3_EEVACNT           HRTIM_EEFR3_EEVACNT_Msk                 /*!< External Event A Selection */
8733 #define HRTIM_EEFR3_EEVACNT_0         (0x1UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000100 */
8734 #define HRTIM_EEFR3_EEVACNT_1         (0x2UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000200 */
8735 #define HRTIM_EEFR3_EEVACNT_2         (0x4UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000400 */
8736 #define HRTIM_EEFR3_EEVACNT_3         (0x8UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000800 */
8737 #define HRTIM_EEFR3_EEVACNT_4         (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00001000 */
8738 #define HRTIM_EEFR3_EEVACNT_5         (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00002000 */
8739 #define HRTIM_EEFR3_EEVBCE_Pos        (16U)
8740 #define HRTIM_EEFR3_EEVBCE_Msk        (0x1UL << HRTIM_EEFR3_EEVBCE_Pos)       /*!< 0x00010000 */
8741 #define HRTIM_EEFR3_EEVBCE            HRTIM_EEFR3_EEVBCE_Msk                  /*!< External Event B Counter Enable */
8742 #define HRTIM_EEFR3_EEVBCRES_Pos      (17U)
8743 #define HRTIM_EEFR3_EEVBCRES_Msk      (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos)     /*!< 0x00020000 */
8744 #define HRTIM_EEFR3_EEVBCRES          HRTIM_EEFR3_EEVBCRES_Msk                /*!< External Event B Counter Reset */
8745 #define HRTIM_EEFR3_EEVBRSTM_Pos      (18U)
8746 #define HRTIM_EEFR3_EEVBRSTM_Msk      (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos)     /*!< 0x00040000 */
8747 #define HRTIM_EEFR3_EEVBRSTM          HRTIM_EEFR3_EEVBRSTM_Msk                /*!< External Event B Counter Reset Mode */
8748 #define HRTIM_EEFR3_EEVBSEL_Pos       (20U)
8749 #define HRTIM_EEFR3_EEVBSEL_Msk       (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00F00000 */
8750 #define HRTIM_EEFR3_EEVBSEL           HRTIM_EEFR3_EEVBSEL_Msk                 /*!< External Event B Selection */
8751 #define HRTIM_EEFR3_EEVBSEL_0         (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00100000 */
8752 #define HRTIM_EEFR3_EEVBSEL_1         (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00200000 */
8753 #define HRTIM_EEFR3_EEVBSEL_2         (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00400000 */
8754 #define HRTIM_EEFR3_EEVBSEL_3         (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00800000 */
8755 #define HRTIM_EEFR3_EEVBCNT_Pos       (24U)
8756 #define HRTIM_EEFR3_EEVBCNT_Msk       (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos)     /*!< 0x3F000000 */
8757 #define HRTIM_EEFR3_EEVBCNT           HRTIM_EEFR3_EEVBCNT_Msk                 /*!< External Event B Counter */
8758 #define HRTIM_EEFR3_EEVBCNT_0         (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x01000000 */
8759 #define HRTIM_EEFR3_EEVBCNT_1         (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x02000000 */
8760 #define HRTIM_EEFR3_EEVBCNT_2         (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x04000000 */
8761 #define HRTIM_EEFR3_EEVBCNT_3         (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x08000000 */
8762 #define HRTIM_EEFR3_EEVBCNT_4         (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x10000000 */
8763 #define HRTIM_EEFR3_EEVBCNT_5         (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x20000000 */
8764 
8765 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
8766 #define HRTIM_CR1_MUDIS_Pos           (0U)
8767 #define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)          /*!< 0x00000001 */
8768 #define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                     /*!< Master update disable*/
8769 #define HRTIM_CR1_TAUDIS_Pos          (1U)
8770 #define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)         /*!< 0x00000002 */
8771 #define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                    /*!< Timer A update disable*/
8772 #define HRTIM_CR1_TBUDIS_Pos          (2U)
8773 #define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)         /*!< 0x00000004 */
8774 #define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                    /*!< Timer B update disable*/
8775 #define HRTIM_CR1_TCUDIS_Pos          (3U)
8776 #define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)         /*!< 0x00000008 */
8777 #define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                    /*!< Timer C update disable*/
8778 #define HRTIM_CR1_TDUDIS_Pos          (4U)
8779 #define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)         /*!< 0x00000010 */
8780 #define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                    /*!< Timer D update disable*/
8781 #define HRTIM_CR1_TEUDIS_Pos          (5U)
8782 #define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)         /*!< 0x00000020 */
8783 #define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                    /*!< Timer E update disable*/
8784 #define HRTIM_CR1_TFUDIS_Pos          (6U)
8785 #define HRTIM_CR1_TFUDIS_Msk          (0x1UL << HRTIM_CR1_TFUDIS_Pos)         /*!< 0x00000040 */
8786 #define HRTIM_CR1_TFUDIS              HRTIM_CR1_TFUDIS_Msk                    /*!< Timer F update disable*/
8787 #define HRTIM_CR1_ADC1USRC_Pos        (16U)
8788 #define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00070000 */
8789 #define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                  /*!< ADC Trigger 1 update source */
8790 #define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00010000 */
8791 #define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00020000 */
8792 #define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00040000 */
8793 #define HRTIM_CR1_ADC2USRC_Pos        (19U)
8794 #define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00380000 */
8795 #define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                  /*!< ADC Trigger 2 update source */
8796 #define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00080000 */
8797 #define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00100000 */
8798 #define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00200000 */
8799 #define HRTIM_CR1_ADC3USRC_Pos        (22U)
8800 #define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x01C00000 */
8801 #define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                  /*!< ADC Trigger 3 update source */
8802 #define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x00400000 */
8803 #define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x00800000 */
8804 #define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x01000000 */
8805 #define HRTIM_CR1_ADC4USRC_Pos        (25U)
8806 #define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x0E000000 */
8807 #define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                  /*!< ADC Trigger 4 update source */
8808 #define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x02000000 */
8809 #define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x04000000 */
8810 #define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x0800000 */
8811 
8812 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
8813 #define HRTIM_CR2_MSWU_Pos            (0U)
8814 #define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)           /*!< 0x00000001 */
8815 #define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                      /*!< Master software update */
8816 #define HRTIM_CR2_TASWU_Pos           (1U)
8817 #define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)          /*!< 0x00000002 */
8818 #define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                     /*!< Timer A software update */
8819 #define HRTIM_CR2_TBSWU_Pos           (2U)
8820 #define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)          /*!< 0x00000004 */
8821 #define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                     /*!< Timer B software update */
8822 #define HRTIM_CR2_TCSWU_Pos           (3U)
8823 #define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)          /*!< 0x00000008 */
8824 #define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                     /*!< Timer C software update */
8825 #define HRTIM_CR2_TDSWU_Pos           (4U)
8826 #define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)          /*!< 0x00000010 */
8827 #define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                     /*!< Timer D software update */
8828 #define HRTIM_CR2_TESWU_Pos           (5U)
8829 #define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)          /*!< 0x00000020 */
8830 #define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                     /*!< Timer E software update */
8831 #define HRTIM_CR2_TFSWU_Pos           (6U)
8832 #define HRTIM_CR2_TFSWU_Msk           (0x1UL << HRTIM_CR2_TFSWU_Pos)          /*!< 0x00000040 */
8833 #define HRTIM_CR2_TFSWU               HRTIM_CR2_TFSWU_Msk                     /*!< Timer F software update */
8834 #define HRTIM_CR2_MRST_Pos            (8U)
8835 #define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)           /*!< 0x00000100 */
8836 #define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                      /*!< Master count software reset */
8837 #define HRTIM_CR2_TARST_Pos           (9U)
8838 #define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)          /*!< 0x00000200 */
8839 #define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                     /*!< Timer A count software reset */
8840 #define HRTIM_CR2_TBRST_Pos           (10U)
8841 #define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)          /*!< 0x00000400 */
8842 #define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                     /*!< Timer B count software reset */
8843 #define HRTIM_CR2_TCRST_Pos           (11U)
8844 #define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)          /*!< 0x00000800 */
8845 #define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                     /*!< Timer C count software reset */
8846 #define HRTIM_CR2_TDRST_Pos           (12U)
8847 #define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)          /*!< 0x00001000 */
8848 #define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                     /*!< Timer D count software reset */
8849 #define HRTIM_CR2_TERST_Pos           (13U)
8850 #define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)          /*!< 0x00002000 */
8851 #define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                     /*!< Timer E count software reset */
8852 #define HRTIM_CR2_TFRST_Pos           (14U)
8853 #define HRTIM_CR2_TFRST_Msk           (0x1UL << HRTIM_CR2_TFRST_Pos)          /*!< 0x00004000 */
8854 #define HRTIM_CR2_TFRST               HRTIM_CR2_TFRST_Msk                     /*!< Timer F count software reset */
8855 #define HRTIM_CR2_SWPA_Pos            (16U)
8856 #define HRTIM_CR2_SWPA_Msk            (0x1UL << HRTIM_CR2_SWPA_Pos)           /*!< 0x00010000 */
8857 #define HRTIM_CR2_SWPA                HRTIM_CR2_SWPA_Msk                      /*!< Timer A swap outputs */
8858 #define HRTIM_CR2_SWPB_Pos            (17U)
8859 #define HRTIM_CR2_SWPB_Msk            (0x1UL << HRTIM_CR2_SWPB_Pos)           /*!< 0x00020000 */
8860 #define HRTIM_CR2_SWPB                HRTIM_CR2_SWPB_Msk                      /*!< Timer B swap outputs */
8861 #define HRTIM_CR2_SWPC_Pos            (18U)
8862 #define HRTIM_CR2_SWPC_Msk            (0x1UL << HRTIM_CR2_SWPC_Pos)           /*!< 0x00040000 */
8863 #define HRTIM_CR2_SWPC                HRTIM_CR2_SWPC_Msk                      /*!< Timer C swap outputs */
8864 #define HRTIM_CR2_SWPD_Pos            (19U)
8865 #define HRTIM_CR2_SWPD_Msk            (0x1UL << HRTIM_CR2_SWPD_Pos)           /*!< 0x00080000 */
8866 #define HRTIM_CR2_SWPD                HRTIM_CR2_SWPD_Msk                      /*!< Timer D swap outputs */
8867 #define HRTIM_CR2_SWPE_Pos            (20U)
8868 #define HRTIM_CR2_SWPE_Msk            (0x1UL << HRTIM_CR2_SWPE_Pos)           /*!< 0x00100000 */
8869 #define HRTIM_CR2_SWPE                HRTIM_CR2_SWPE_Msk                      /*!< Timer E swap outputs */
8870 #define HRTIM_CR2_SWPF_Pos            (21U)
8871 #define HRTIM_CR2_SWPF_Msk            (0x1UL << HRTIM_CR2_SWPF_Pos)           /*!< 0x00200000 */
8872 #define HRTIM_CR2_SWPF                HRTIM_CR2_SWPF_Msk                      /*!< Timer F swap outputs */
8873 
8874 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
8875 #define HRTIM_ISR_FLT1_Pos            (0U)
8876 #define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
8877 #define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
8878 #define HRTIM_ISR_FLT2_Pos            (1U)
8879 #define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
8880 #define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
8881 #define HRTIM_ISR_FLT3_Pos            (2U)
8882 #define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
8883 #define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
8884 #define HRTIM_ISR_FLT4_Pos            (3U)
8885 #define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
8886 #define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
8887 #define HRTIM_ISR_FLT5_Pos            (4U)
8888 #define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
8889 #define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
8890 #define HRTIM_ISR_SYSFLT_Pos          (5U)
8891 #define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
8892 #define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
8893 #define HRTIM_ISR_FLT6_Pos            (6U)
8894 #define HRTIM_ISR_FLT6_Msk            (0x1UL << HRTIM_ISR_FLT6_Pos)            /*!< 0x00000040 */
8895 #define HRTIM_ISR_FLT6                HRTIM_ISR_FLT6_Msk                       /*!< Fault 6 interrupt flag */
8896 #define HRTIM_ISR_DLLRDY_Pos          (16U)
8897 #define HRTIM_ISR_DLLRDY_Msk          (0x1UL << HRTIM_ISR_DLLRDY_Pos)          /*!< 0x00010000 */
8898 #define HRTIM_ISR_DLLRDY              HRTIM_ISR_DLLRDY_Msk                     /*!< DLL ready interrupt flag */
8899 #define HRTIM_ISR_BMPER_Pos           (17U)
8900 #define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
8901 #define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
8902 
8903 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
8904 #define HRTIM_ICR_FLT1C_Pos           (0U)
8905 #define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
8906 #define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
8907 #define HRTIM_ICR_FLT2C_Pos           (1U)
8908 #define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
8909 #define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
8910 #define HRTIM_ICR_FLT3C_Pos           (2U)
8911 #define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
8912 #define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
8913 #define HRTIM_ICR_FLT4C_Pos           (3U)
8914 #define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
8915 #define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
8916 #define HRTIM_ICR_FLT5C_Pos           (4U)
8917 #define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
8918 #define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
8919 #define HRTIM_ICR_SYSFLTC_Pos         (5U)
8920 #define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
8921 #define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
8922 
8923 #define HRTIM_ICR_FLT6C_Pos           (6U)
8924 #define HRTIM_ICR_FLT6C_Msk           (0x1UL << HRTIM_ICR_FLT6C_Pos)           /*!< 0x00000040 */
8925 #define HRTIM_ICR_FLT6C               HRTIM_ICR_FLT6C_Msk                      /*!< Fault 6 interrupt flag clear */
8926 
8927 #define HRTIM_ICR_DLLRDYC_Pos         (16U)
8928 #define HRTIM_ICR_DLLRDYC_Msk         (0x1UL << HRTIM_ICR_DLLRDYC_Pos)         /*!< 0x00010000 */
8929 #define HRTIM_ICR_DLLRDYC             HRTIM_ICR_DLLRDYC_Msk                    /*!< DLL ready interrupt flag clear */
8930 #define HRTIM_ICR_BMPERC_Pos          (17U)
8931 #define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
8932 #define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
8933 
8934 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
8935 #define HRTIM_IER_FLT1_Pos            (0U)
8936 #define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
8937 #define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
8938 #define HRTIM_IER_FLT2_Pos            (1U)
8939 #define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
8940 #define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
8941 #define HRTIM_IER_FLT3_Pos            (2U)
8942 #define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
8943 #define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
8944 #define HRTIM_IER_FLT4_Pos            (3U)
8945 #define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
8946 #define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
8947 #define HRTIM_IER_FLT5_Pos            (4U)
8948 #define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
8949 #define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
8950 #define HRTIM_IER_SYSFLT_Pos          (5U)
8951 #define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
8952 #define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
8953 #define HRTIM_IER_FLT6_Pos            (6U)
8954 #define HRTIM_IER_FLT6_Msk            (0x1UL << HRTIM_IER_FLT6_Pos)            /*!< 0x00000040 */
8955 #define HRTIM_IER_FLT6                HRTIM_IER_FLT6_Msk                       /*!< Fault 6 interrupt enable */
8956 
8957 #define HRTIM_IER_DLLRDY_Pos          (16U)
8958 #define HRTIM_IER_DLLRDY_Msk          (0x1UL << HRTIM_IER_DLLRDY_Pos)          /*!< 0x00010000 */
8959 #define HRTIM_IER_DLLRDY              HRTIM_IER_DLLRDY_Msk                     /*!< DLL ready interrupt enable */
8960 #define HRTIM_IER_BMPER_Pos           (17U)
8961 #define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
8962 #define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
8963 
8964 /**** Bit definition for Common HRTIM Timer output enable register ************/
8965 #define HRTIM_OENR_TA1OEN_Pos         (0U)
8966 #define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
8967 #define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
8968 #define HRTIM_OENR_TA2OEN_Pos         (1U)
8969 #define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
8970 #define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
8971 #define HRTIM_OENR_TB1OEN_Pos         (2U)
8972 #define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
8973 #define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
8974 #define HRTIM_OENR_TB2OEN_Pos         (3U)
8975 #define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
8976 #define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
8977 #define HRTIM_OENR_TC1OEN_Pos         (4U)
8978 #define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
8979 #define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
8980 #define HRTIM_OENR_TC2OEN_Pos         (5U)
8981 #define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
8982 #define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
8983 #define HRTIM_OENR_TD1OEN_Pos         (6U)
8984 #define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
8985 #define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
8986 #define HRTIM_OENR_TD2OEN_Pos         (7U)
8987 #define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
8988 #define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
8989 #define HRTIM_OENR_TE1OEN_Pos         (8U)
8990 #define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
8991 #define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
8992 #define HRTIM_OENR_TE2OEN_Pos         (9U)
8993 #define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
8994 #define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
8995 #define HRTIM_OENR_TF1OEN_Pos         (10U)
8996 #define HRTIM_OENR_TF1OEN_Msk         (0x1UL << HRTIM_OENR_TF1OEN_Pos)         /*!< 0x00000400 */
8997 #define HRTIM_OENR_TF1OEN             HRTIM_OENR_TF1OEN_Msk                    /*!< Timer F Output 1 enable */
8998 #define HRTIM_OENR_TF2OEN_Pos         (11U)
8999 #define HRTIM_OENR_TF2OEN_Msk         (0x1UL << HRTIM_OENR_TF2OEN_Pos)         /*!< 0x00000800 */
9000 #define HRTIM_OENR_TF2OEN             HRTIM_OENR_TF2OEN_Msk                    /*!< Timer F Output 2 enable */
9001 
9002 /**** Bit definition for Common HRTIM Timer output disable register ***********/
9003 #define HRTIM_ODISR_TA1ODIS_Pos       (0U)
9004 #define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
9005 #define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
9006 #define HRTIM_ODISR_TA2ODIS_Pos       (1U)
9007 #define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
9008 #define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
9009 #define HRTIM_ODISR_TB1ODIS_Pos       (2U)
9010 #define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
9011 #define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
9012 #define HRTIM_ODISR_TB2ODIS_Pos       (3U)
9013 #define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
9014 #define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
9015 #define HRTIM_ODISR_TC1ODIS_Pos       (4U)
9016 #define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
9017 #define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
9018 #define HRTIM_ODISR_TC2ODIS_Pos       (5U)
9019 #define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
9020 #define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
9021 #define HRTIM_ODISR_TD1ODIS_Pos       (6U)
9022 #define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
9023 #define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
9024 #define HRTIM_ODISR_TD2ODIS_Pos       (7U)
9025 #define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
9026 #define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
9027 #define HRTIM_ODISR_TE1ODIS_Pos       (8U)
9028 #define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
9029 #define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
9030 #define HRTIM_ODISR_TE2ODIS_Pos       (9U)
9031 #define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
9032 #define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
9033 #define HRTIM_ODISR_TF1ODIS_Pos       (10U)
9034 #define HRTIM_ODISR_TF1ODIS_Msk       (0x1UL << HRTIM_ODISR_TF1ODIS_Pos)       /*!< 0x00000100 */
9035 #define HRTIM_ODISR_TF1ODIS           HRTIM_ODISR_TF1ODIS_Msk                  /*!< Timer F Output 1 disable */
9036 #define HRTIM_ODISR_TF2ODIS_Pos       (11U)
9037 #define HRTIM_ODISR_TF2ODIS_Msk       (0x1UL << HRTIM_ODISR_TF2ODIS_Pos)       /*!< 0x00000200 */
9038 #define HRTIM_ODISR_TF2ODIS           HRTIM_ODISR_TF2ODIS_Msk                  /*!< Timer F Output 2 disable */
9039 
9040 /**** Bit definition for Common HRTIM Timer output disable status register *****/
9041 #define HRTIM_ODSR_TA1ODS_Pos         (0U)
9042 #define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
9043 #define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
9044 #define HRTIM_ODSR_TA2ODS_Pos         (1U)
9045 #define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
9046 #define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
9047 #define HRTIM_ODSR_TB1ODS_Pos         (2U)
9048 #define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
9049 #define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
9050 #define HRTIM_ODSR_TB2ODS_Pos         (3U)
9051 #define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
9052 #define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
9053 #define HRTIM_ODSR_TC1ODS_Pos         (4U)
9054 #define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
9055 #define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
9056 #define HRTIM_ODSR_TC2ODS_Pos         (5U)
9057 #define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
9058 #define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
9059 #define HRTIM_ODSR_TD1ODS_Pos         (6U)
9060 #define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
9061 #define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
9062 #define HRTIM_ODSR_TD2ODS_Pos         (7U)
9063 #define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
9064 #define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
9065 #define HRTIM_ODSR_TE1ODS_Pos         (8U)
9066 #define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
9067 #define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
9068 #define HRTIM_ODSR_TE2ODS_Pos         (9U)
9069 #define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
9070 #define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
9071 #define HRTIM_ODSR_TF1ODS_Pos         (10U)
9072 #define HRTIM_ODSR_TF1ODS_Msk         (0x1UL << HRTIM_ODSR_TF1ODS_Pos)         /*!< 0x00000100 */
9073 #define HRTIM_ODSR_TF1ODS             HRTIM_ODSR_TF1ODS_Msk                    /*!< Timer F Output 1 disable status */
9074 #define HRTIM_ODSR_TF2ODS_Pos         (11U)
9075 #define HRTIM_ODSR_TF2ODS_Msk         (0x1UL << HRTIM_ODSR_TF2ODS_Pos)         /*!< 0x00000200 */
9076 #define HRTIM_ODSR_TF2ODS             HRTIM_ODSR_TF2ODS_Msk                    /*!< Timer F Output 2 disable status */
9077 
9078 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
9079 #define HRTIM_BMCR_BME_Pos            (0U)
9080 #define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
9081 #define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enable */
9082 #define HRTIM_BMCR_BMOM_Pos           (1U)
9083 #define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
9084 #define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
9085 #define HRTIM_BMCR_BMCLK_Pos          (2U)
9086 #define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
9087 #define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
9088 #define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000004 */
9089 #define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000008 */
9090 #define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000010 */
9091 #define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000020 */
9092 #define HRTIM_BMCR_BMPRSC_Pos         (6U)
9093 #define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
9094 #define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
9095 #define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000040 */
9096 #define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000080 */
9097 #define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000100 */
9098 #define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000200 */
9099 #define HRTIM_BMCR_BMPREN_Pos         (10U)
9100 #define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
9101 #define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
9102 #define HRTIM_BMCR_MTBM_Pos           (16U)
9103 #define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
9104 #define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
9105 #define HRTIM_BMCR_TABM_Pos           (17U)
9106 #define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
9107 #define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
9108 #define HRTIM_BMCR_TBBM_Pos           (18U)
9109 #define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
9110 #define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
9111 #define HRTIM_BMCR_TCBM_Pos           (19U)
9112 #define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
9113 #define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
9114 #define HRTIM_BMCR_TDBM_Pos           (20U)
9115 #define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
9116 #define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
9117 #define HRTIM_BMCR_TEBM_Pos           (21U)
9118 #define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
9119 #define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
9120 
9121 #define HRTIM_BMCR_TFBM_Pos           (22U)
9122 #define HRTIM_BMCR_TFBM_Msk           (0x1UL << HRTIM_BMCR_TFBM_Pos)           /*!< 0x00400000 */
9123 #define HRTIM_BMCR_TFBM               HRTIM_BMCR_TFBM_Msk                      /*!< Timer F Burst mode */
9124 
9125 #define HRTIM_BMCR_BMSTAT_Pos         (31U)
9126 #define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
9127 #define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
9128 
9129 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
9130 #define HRTIM_BMTRGR_SW_Pos           (0U)
9131 #define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
9132 #define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
9133 #define HRTIM_BMTRGR_MSTRST_Pos       (1U)
9134 #define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
9135 #define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
9136 #define HRTIM_BMTRGR_MSTREP_Pos       (2U)
9137 #define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
9138 #define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
9139 #define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
9140 #define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
9141 #define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
9142 #define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
9143 #define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
9144 #define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
9145 #define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
9146 #define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
9147 #define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
9148 #define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
9149 #define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
9150 #define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
9151 #define HRTIM_BMTRGR_TARST_Pos        (7U)
9152 #define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
9153 #define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
9154 #define HRTIM_BMTRGR_TAREP_Pos        (8U)
9155 #define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
9156 #define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
9157 #define HRTIM_BMTRGR_TACMP1_Pos       (9U)
9158 #define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
9159 #define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
9160 #define HRTIM_BMTRGR_TACMP2_Pos       (10U)
9161 #define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
9162 #define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
9163 #define HRTIM_BMTRGR_TBRST_Pos        (11U)
9164 #define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
9165 #define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
9166 #define HRTIM_BMTRGR_TBREP_Pos        (12U)
9167 #define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
9168 #define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
9169 #define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
9170 #define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
9171 #define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
9172 #define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
9173 #define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
9174 #define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
9175 #define HRTIM_BMTRGR_TCRST_Pos        (15U)
9176 #define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
9177 #define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
9178 #define HRTIM_BMTRGR_TCREP_Pos        (16U)
9179 #define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
9180 #define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
9181 #define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
9182 #define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
9183 #define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
9184 #define HRTIM_BMTRGR_TFRST_Pos        (18U)
9185 #define HRTIM_BMTRGR_TFRST_Msk        (0x1UL << HRTIM_BMTRGR_TFRST_Pos)        /*!< 0x00040000 */
9186 #define HRTIM_BMTRGR_TFRST            HRTIM_BMTRGR_TFRST_Msk                   /*!< Timer F reset */
9187 #define HRTIM_BMTRGR_TDRST_Pos        (19U)
9188 #define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
9189 #define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
9190 #define HRTIM_BMTRGR_TDREP_Pos        (20U)
9191 #define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
9192 #define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
9193 #define HRTIM_BMTRGR_TFREP_Pos        (21U)
9194 #define HRTIM_BMTRGR_TFREP_Msk        (0x1UL << HRTIM_BMTRGR_TFREP_Pos)        /*!< 0x00200000 */
9195 #define HRTIM_BMTRGR_TFREP            HRTIM_BMTRGR_TFREP_Msk                   /*!< Timer F repetition*/
9196 #define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
9197 #define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
9198 #define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
9199 #define HRTIM_BMTRGR_TFCMP1_Pos       (23U)
9200 #define HRTIM_BMTRGR_TFCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos)       /*!< 0x00800000 */
9201 #define HRTIM_BMTRGR_TFCMP1            HRTIM_BMTRGR_TFCMP1_Msk                 /*!< Timer F compare 1 */
9202 #define HRTIM_BMTRGR_TEREP_Pos        (24U)
9203 #define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
9204 #define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
9205 #define HRTIM_BMTRGR_TECMP1_Pos       (25U)
9206 #define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
9207 #define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
9208 #define HRTIM_BMTRGR_TECMP2_Pos       (26U)
9209 #define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
9210 #define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
9211 #define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
9212 #define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
9213 #define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
9214 #define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
9215 #define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
9216 #define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
9217 #define HRTIM_BMTRGR_EEV7_Pos         (29U)
9218 #define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
9219 #define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
9220 #define HRTIM_BMTRGR_EEV8_Pos         (30U)
9221 #define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
9222 #define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
9223 #define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
9224 #define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
9225 #define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
9226 
9227 /*******************  Bit definition for HRTIM_BMCMPR register  ***************/
9228 #define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
9229 #define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
9230 #define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
9231 
9232 /*******************  Bit definition for HRTIM_BMPER register  ****************/
9233 #define HRTIM_BMPER_BMPER_Pos         (0U)
9234 #define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
9235 #define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
9236 
9237 /*******************  Bit definition for HRTIM_EECR1 register  ****************/
9238 #define HRTIM_EECR1_EE1SRC_Pos        (0U)
9239 #define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
9240 #define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
9241 #define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000001 */
9242 #define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000002 */
9243 #define HRTIM_EECR1_EE1POL_Pos        (2U)
9244 #define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
9245 #define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
9246 #define HRTIM_EECR1_EE1SNS_Pos        (3U)
9247 #define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
9248 #define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
9249 #define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000008 */
9250 #define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000010 */
9251 #define HRTIM_EECR1_EE1FAST_Pos       (5U)
9252 #define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
9253 #define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
9254 
9255 #define HRTIM_EECR1_EE2SRC_Pos        (6U)
9256 #define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
9257 #define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
9258 #define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x00000040 */
9259 #define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x00000080 */
9260 #define HRTIM_EECR1_EE2POL_Pos        (8U)
9261 #define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
9262 #define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
9263 #define HRTIM_EECR1_EE2SNS_Pos        (9U)
9264 #define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
9265 #define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
9266 #define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000200 */
9267 #define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000400 */
9268 #define HRTIM_EECR1_EE2FAST_Pos       (11U)
9269 #define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
9270 #define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
9271 
9272 #define HRTIM_EECR1_EE3SRC_Pos        (12U)
9273 #define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
9274 #define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
9275 #define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00001000 */
9276 #define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00002000 */
9277 #define HRTIM_EECR1_EE3POL_Pos        (14U)
9278 #define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
9279 #define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
9280 #define HRTIM_EECR1_EE3SNS_Pos        (15U)
9281 #define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
9282 #define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
9283 #define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00008000 */
9284 #define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00010000 */
9285 #define HRTIM_EECR1_EE3FAST_Pos       (17U)
9286 #define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
9287 #define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
9288 
9289 #define HRTIM_EECR1_EE4SRC_Pos        (18U)
9290 #define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
9291 #define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
9292 #define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x00040000 */
9293 #define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x00080000 */
9294 #define HRTIM_EECR1_EE4POL_Pos        (20U)
9295 #define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
9296 #define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
9297 #define HRTIM_EECR1_EE4SNS_Pos        (21U)
9298 #define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
9299 #define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
9300 #define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00200000 */
9301 #define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00400000 */
9302 #define HRTIM_EECR1_EE4FAST_Pos       (23U)
9303 #define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
9304 #define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
9305 
9306 #define HRTIM_EECR1_EE5SRC_Pos        (24U)
9307 #define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
9308 #define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
9309 #define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x01000000 */
9310 #define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x02000000 */
9311 #define HRTIM_EECR1_EE5POL_Pos        (26U)
9312 #define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
9313 #define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
9314 #define HRTIM_EECR1_EE5SNS_Pos        (27U)
9315 #define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
9316 #define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
9317 #define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x08000000 */
9318 #define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x10000000 */
9319 #define HRTIM_EECR1_EE5FAST_Pos       (29U)
9320 #define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
9321 #define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
9322 
9323 /*******************  Bit definition for HRTIM_EECR2 register  ****************/
9324 #define HRTIM_EECR2_EE6SRC_Pos        (0U)
9325 #define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
9326 #define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
9327 #define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000001 */
9328 #define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000002 */
9329 #define HRTIM_EECR2_EE6POL_Pos        (2U)
9330 #define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
9331 #define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
9332 #define HRTIM_EECR2_EE6SNS_Pos        (3U)
9333 #define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
9334 #define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
9335 #define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000008 */
9336 #define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000010 */
9337 
9338 #define HRTIM_EECR2_EE7SRC_Pos        (6U)
9339 #define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
9340 #define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
9341 #define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x00000040 */
9342 #define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x00000080 */
9343 #define HRTIM_EECR2_EE7POL_Pos        (8U)
9344 #define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
9345 #define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
9346 #define HRTIM_EECR2_EE7SNS_Pos        (9U)
9347 #define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
9348 #define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
9349 #define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000200 */
9350 #define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000400 */
9351 
9352 #define HRTIM_EECR2_EE8SRC_Pos        (12U)
9353 #define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
9354 #define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
9355 #define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00001000 */
9356 #define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00002000 */
9357 #define HRTIM_EECR2_EE8POL_Pos        (14U)
9358 #define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
9359 #define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
9360 #define HRTIM_EECR2_EE8SNS_Pos        (15U)
9361 #define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
9362 #define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
9363 #define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00008000 */
9364 #define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00010000 */
9365 
9366 #define HRTIM_EECR2_EE9SRC_Pos        (18U)
9367 #define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
9368 #define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
9369 #define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x00040000 */
9370 #define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x00080000 */
9371 #define HRTIM_EECR2_EE9POL_Pos        (20U)
9372 #define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
9373 #define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
9374 #define HRTIM_EECR2_EE9SNS_Pos        (21U)
9375 #define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
9376 #define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
9377 #define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00200000 */
9378 #define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00400000 */
9379 
9380 #define HRTIM_EECR2_EE10SRC_Pos       (24U)
9381 #define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
9382 #define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
9383 #define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x01000000 */
9384 #define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x02000000 */
9385 #define HRTIM_EECR2_EE10POL_Pos       (26U)
9386 #define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
9387 #define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
9388 #define HRTIM_EECR2_EE10SNS_Pos       (27U)
9389 #define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
9390 #define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
9391 #define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x08000000 */
9392 #define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x10000000 */
9393 
9394 /*******************  Bit definition for HRTIM_EECR3 register  ****************/
9395 #define HRTIM_EECR3_EE6F_Pos          (0U)
9396 #define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
9397 #define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
9398 #define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000001 */
9399 #define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000002 */
9400 #define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000004 */
9401 #define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000008 */
9402 #define HRTIM_EECR3_EE7F_Pos          (6U)
9403 #define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
9404 #define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
9405 #define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000040 */
9406 #define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000080 */
9407 #define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000100 */
9408 #define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000200 */
9409 #define HRTIM_EECR3_EE8F_Pos          (12U)
9410 #define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
9411 #define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
9412 #define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00001000 */
9413 #define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00002000 */
9414 #define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00004000 */
9415 #define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00008000 */
9416 #define HRTIM_EECR3_EE9F_Pos          (18U)
9417 #define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
9418 #define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
9419 #define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00040000 */
9420 #define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00080000 */
9421 #define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00100000 */
9422 #define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00200000 */
9423 #define HRTIM_EECR3_EE10F_Pos         (24U)
9424 #define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
9425 #define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
9426 #define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x01000000 */
9427 #define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x02000000 */
9428 #define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x04000000 */
9429 #define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x08000000 */
9430 #define HRTIM_EECR3_EEVSD_Pos         (30U)
9431 #define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
9432 #define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
9433 #define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0x40000000 */
9434 #define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0x80000000 */
9435 
9436 /*******************  Bit definition for HRTIM_ADC1R register  ****************/
9437 #define HRTIM_ADC1R_AD1MC1_Pos        (0U)
9438 #define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
9439 #define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
9440 #define HRTIM_ADC1R_AD1MC2_Pos        (1U)
9441 #define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
9442 #define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
9443 #define HRTIM_ADC1R_AD1MC3_Pos        (2U)
9444 #define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
9445 #define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
9446 #define HRTIM_ADC1R_AD1MC4_Pos        (3U)
9447 #define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
9448 #define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
9449 #define HRTIM_ADC1R_AD1MPER_Pos       (4U)
9450 #define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
9451 #define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
9452 #define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
9453 #define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
9454 #define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
9455 #define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
9456 #define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
9457 #define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
9458 #define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
9459 #define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
9460 #define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
9461 #define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
9462 #define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
9463 #define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
9464 #define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
9465 #define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
9466 #define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
9467 
9468 #define HRTIM_ADC1R_AD1TFC2_Pos       (10U)
9469 #define HRTIM_ADC1R_AD1TFC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC2_Pos)       /*!< 0x00000400 */
9470 #define HRTIM_ADC1R_AD1TFC2           HRTIM_ADC1R_AD1TFC2_Msk                  /*!< ADC Trigger 1 on Timer F compare 2 */
9471 
9472 #define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
9473 #define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
9474 #define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
9475 #define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
9476 #define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
9477 #define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
9478 #define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
9479 #define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
9480 #define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
9481 #define HRTIM_ADC1R_AD1TARST_Pos      (14U)
9482 #define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
9483 #define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
9484 
9485 #define HRTIM_ADC1R_AD1TFC3_Pos       (15U)
9486 #define HRTIM_ADC1R_AD1TFC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC3_Pos)       /*!< 0x00008000 */
9487 #define HRTIM_ADC1R_AD1TFC3           HRTIM_ADC1R_AD1TFC3_Msk                  /*!< ADC Trigger 1 on Timer F compare 3 */
9488 
9489 #define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
9490 #define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
9491 #define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
9492 #define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
9493 #define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
9494 #define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
9495 #define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
9496 #define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
9497 #define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
9498 #define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
9499 #define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
9500 #define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
9501 
9502 #define HRTIM_ADC1R_AD1TFC4_Pos       (20U)
9503 #define HRTIM_ADC1R_AD1TFC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC4_Pos)       /*!< 0x00100000 */
9504 #define HRTIM_ADC1R_AD1TFC4           HRTIM_ADC1R_AD1TFC4_Msk                  /*!< ADC Trigger 1 on Timer F compare 4 */
9505 
9506 #define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
9507 #define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
9508 #define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
9509 #define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
9510 #define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
9511 #define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
9512 #define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
9513 #define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
9514 #define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
9515 
9516 #define HRTIM_ADC1R_AD1TFPER_Pos      (24U)
9517 #define HRTIM_ADC1R_AD1TFPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TFPER_Pos)      /*!< 0x01000000 */
9518 #define HRTIM_ADC1R_AD1TFPER          HRTIM_ADC1R_AD1TFPER_Msk                 /*!< ADC Trigger 1 on Timer F period */
9519 
9520 #define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
9521 #define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
9522 #define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
9523 #define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
9524 #define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
9525 #define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
9526 #define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
9527 #define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
9528 #define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
9529 
9530 #define HRTIM_ADC1R_AD1TFRST_Pos      (28U)
9531 #define HRTIM_ADC1R_AD1TFRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TFRST_Pos)      /*!< 0x10000000 */
9532 #define HRTIM_ADC1R_AD1TFRST          HRTIM_ADC1R_AD1TFRST_Msk                 /*!< ADC Trigger 1 on Timer F reset */
9533 
9534 #define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
9535 #define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
9536 #define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
9537 #define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
9538 #define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
9539 #define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
9540 #define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
9541 #define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
9542 #define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E compare period */
9543 
9544 /*******************  Bit definition for HRTIM_ADC2R register  ****************/
9545 #define HRTIM_ADC2R_AD2MC1_Pos        (0U)
9546 #define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
9547 #define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
9548 #define HRTIM_ADC2R_AD2MC2_Pos        (1U)
9549 #define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
9550 #define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
9551 #define HRTIM_ADC2R_AD2MC3_Pos        (2U)
9552 #define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
9553 #define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
9554 #define HRTIM_ADC2R_AD2MC4_Pos        (3U)
9555 #define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
9556 #define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
9557 #define HRTIM_ADC2R_AD2MPER_Pos       (4U)
9558 #define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
9559 #define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
9560 #define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
9561 #define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
9562 #define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
9563 #define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
9564 #define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
9565 #define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
9566 #define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
9567 #define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
9568 #define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
9569 #define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
9570 #define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
9571 #define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
9572 #define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
9573 #define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
9574 #define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
9575 #define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
9576 #define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
9577 #define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
9578 
9579 #define HRTIM_ADC2R_AD2TFC2_Pos       (11U)
9580 #define HRTIM_ADC2R_AD2TFC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC2_Pos)       /*!< 0x00000800 */
9581 #define HRTIM_ADC2R_AD2TFC2           HRTIM_ADC2R_AD2TFC2_Msk                  /*!< ADC Trigger 2 on Timer F compare 2 */
9582 
9583 #define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
9584 #define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
9585 #define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
9586 #define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
9587 #define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
9588 #define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
9589 #define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
9590 #define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
9591 #define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
9592 
9593 #define HRTIM_ADC2R_AD2TFC3_Pos       (15U)
9594 #define HRTIM_ADC2R_AD2TFC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC3_Pos)       /*!< 0x00008000 */
9595 #define HRTIM_ADC2R_AD2TFC3           HRTIM_ADC2R_AD2TFC3_Msk                  /*!< ADC Trigger 2 on Timer F compare 3 */
9596 
9597 #define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
9598 #define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
9599 #define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
9600 #define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
9601 #define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
9602 #define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
9603 #define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
9604 #define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
9605 #define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
9606 
9607 #define HRTIM_ADC2R_AD2TFC4_Pos       (19U)
9608 #define HRTIM_ADC2R_AD2TFC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC4_Pos)       /*!< 0x00080000 */
9609 #define HRTIM_ADC2R_AD2TFC4           HRTIM_ADC2R_AD2TFC4_Msk                  /*!< ADC Trigger 2 on Timer F compare 4 */
9610 
9611 #define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
9612 #define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
9613 #define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
9614 #define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
9615 #define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
9616 #define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
9617 #define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
9618 #define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
9619 #define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
9620 #define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
9621 #define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
9622 #define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
9623 
9624 #define HRTIM_ADC2R_AD2TFPER_Pos      (24U)
9625 #define HRTIM_ADC2R_AD2TFPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TFPER_Pos)      /*!< 0x01000000 */
9626 #define HRTIM_ADC2R_AD2TFPER          HRTIM_ADC2R_AD2TFPER_Msk                 /*!< ADC Trigger 2 on Timer F period */
9627 
9628 #define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
9629 #define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
9630 #define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
9631 #define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
9632 #define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
9633 #define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
9634 #define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
9635 #define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
9636 #define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
9637 #define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
9638 #define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
9639 #define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
9640 #define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
9641 #define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
9642 #define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
9643 #define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
9644 #define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
9645 #define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
9646 #define HRTIM_ADC2R_AD2TERST_Pos      (31U)
9647 #define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
9648 #define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
9649 
9650 /*******************  Bit definition for HRTIM_ADC3R register  ****************/
9651 #define HRTIM_ADC3R_AD3MC1_Pos        (0U)
9652 #define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
9653 #define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
9654 #define HRTIM_ADC3R_AD3MC2_Pos        (1U)
9655 #define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
9656 #define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
9657 #define HRTIM_ADC3R_AD3MC3_Pos        (2U)
9658 #define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
9659 #define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
9660 #define HRTIM_ADC3R_AD3MC4_Pos        (3U)
9661 #define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
9662 #define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
9663 #define HRTIM_ADC3R_AD3MPER_Pos       (4U)
9664 #define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
9665 #define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
9666 #define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
9667 #define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
9668 #define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
9669 #define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
9670 #define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
9671 #define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
9672 #define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
9673 #define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
9674 #define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
9675 #define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
9676 #define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
9677 #define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
9678 #define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
9679 #define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
9680 #define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
9681 
9682 #define HRTIM_ADC3R_AD3TFC2_Pos       (10U)
9683 #define HRTIM_ADC3R_AD3TFC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC2_Pos)       /*!< 0x00000400 */
9684 #define HRTIM_ADC3R_AD3TFC2           HRTIM_ADC3R_AD3TFC2_Msk                  /*!< ADC Trigger 3 on Timer F compare 2 */
9685 
9686 #define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
9687 #define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
9688 #define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
9689 #define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
9690 #define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
9691 #define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
9692 #define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
9693 #define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
9694 #define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
9695 #define HRTIM_ADC3R_AD3TARST_Pos      (14U)
9696 #define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
9697 #define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
9698 
9699 #define HRTIM_ADC3R_AD3TFC3_Pos       (15U)
9700 #define HRTIM_ADC3R_AD3TFC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC3_Pos)       /*!< 0x00008000 */
9701 #define HRTIM_ADC3R_AD3TFC3           HRTIM_ADC3R_AD3TFC3_Msk                  /*!< ADC Trigger 3 on Timer F compare 3 */
9702 
9703 #define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
9704 #define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
9705 #define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
9706 #define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
9707 #define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
9708 #define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
9709 #define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
9710 #define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
9711 #define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
9712 #define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
9713 #define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
9714 #define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
9715 
9716 #define HRTIM_ADC3R_AD3TFC4_Pos       (20U)
9717 #define HRTIM_ADC3R_AD3TFC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC4_Pos)       /*!< 0x00100000 */
9718 #define HRTIM_ADC3R_AD3TFC4           HRTIM_ADC3R_AD3TFC4_Msk                  /*!< ADC Trigger 3 on Timer F compare 4 */
9719 
9720 #define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
9721 #define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
9722 #define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
9723 #define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
9724 #define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
9725 #define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
9726 #define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
9727 #define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
9728 #define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
9729 
9730 #define HRTIM_ADC3R_AD3TFPER_Pos      (24U)
9731 #define HRTIM_ADC3R_AD3TFPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TFPER_Pos)      /*!< 0x01000000 */
9732 #define HRTIM_ADC3R_AD3TFPER          HRTIM_ADC3R_AD3TFPER_Msk                 /*!< ADC Trigger 3 on Timer F period */
9733 
9734 #define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
9735 #define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
9736 #define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
9737 #define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
9738 #define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
9739 #define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
9740 #define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
9741 #define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
9742 #define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
9743 
9744 #define HRTIM_ADC3R_AD3TFRST_Pos      (28U)
9745 #define HRTIM_ADC3R_AD3TFRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TFRST_Pos)      /*!< 0x10000000 */
9746 #define HRTIM_ADC3R_AD3TFRST          HRTIM_ADC3R_AD3TFRST_Msk                 /*!< ADC Trigger 3 on Timer F reset */
9747 
9748 #define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
9749 #define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
9750 #define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
9751 #define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
9752 #define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
9753 #define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
9754 #define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
9755 #define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
9756 #define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
9757 
9758 /*******************  Bit definition for HRTIM_ADC4R register  ****************/
9759 #define HRTIM_ADC4R_AD4MC1_Pos        (0U)
9760 #define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
9761 #define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
9762 #define HRTIM_ADC4R_AD4MC2_Pos        (1U)
9763 #define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
9764 #define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
9765 #define HRTIM_ADC4R_AD4MC3_Pos        (2U)
9766 #define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
9767 #define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
9768 #define HRTIM_ADC4R_AD4MC4_Pos        (3U)
9769 #define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
9770 #define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
9771 #define HRTIM_ADC4R_AD4MPER_Pos       (4U)
9772 #define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
9773 #define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
9774 #define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
9775 #define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
9776 #define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
9777 #define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
9778 #define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
9779 #define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
9780 #define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
9781 #define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
9782 #define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
9783 #define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
9784 #define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
9785 #define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
9786 #define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
9787 #define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
9788 #define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
9789 #define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
9790 #define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
9791 #define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
9792 
9793 #define HRTIM_ADC4R_AD4TFC2_Pos       (11U)
9794 #define HRTIM_ADC4R_AD4TFC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC2_Pos)       /*!< 0x00000800 */
9795 #define HRTIM_ADC4R_AD4TFC2           HRTIM_ADC4R_AD4TFC2_Msk                  /*!< ADC Trigger 4 on Timer F compare 2 */
9796 
9797 #define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
9798 #define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
9799 #define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
9800 #define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
9801 #define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
9802 #define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
9803 #define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
9804 #define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
9805 #define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
9806 
9807 #define HRTIM_ADC4R_AD4TFC3_Pos       (15U)
9808 #define HRTIM_ADC4R_AD4TFC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC3_Pos)       /*!< 0x00008000 */
9809 #define HRTIM_ADC4R_AD4TFC3           HRTIM_ADC4R_AD4TFC3_Msk                  /*!< ADC Trigger 4 on Timer F compare 3 */
9810 
9811 #define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
9812 #define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
9813 #define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
9814 #define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
9815 #define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
9816 #define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
9817 #define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
9818 #define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
9819 #define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
9820 
9821 #define HRTIM_ADC4R_AD4TFC4_Pos       (19U)
9822 #define HRTIM_ADC4R_AD4TFC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC4_Pos)       /*!< 0x00080000 */
9823 #define HRTIM_ADC4R_AD4TFC4           HRTIM_ADC4R_AD4TFC4_Msk                  /*!< ADC Trigger 4 on Timer F compare 4 */
9824 
9825 #define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
9826 #define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
9827 #define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
9828 #define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
9829 #define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
9830 #define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
9831 #define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
9832 #define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
9833 #define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
9834 #define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
9835 #define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
9836 #define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
9837 
9838 #define HRTIM_ADC4R_AD4TFPER_Pos      (24U)
9839 #define HRTIM_ADC4R_AD4TFPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TFPER_Pos)      /*!< 0x01000000 */
9840 #define HRTIM_ADC4R_AD4TFPER          HRTIM_ADC4R_AD4TFPER_Msk                 /*!< ADC Trigger 4 on Timer F period */
9841 
9842 #define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
9843 #define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
9844 #define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
9845 #define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
9846 #define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
9847 #define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
9848 #define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
9849 #define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
9850 #define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
9851 #define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
9852 #define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
9853 #define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
9854 #define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
9855 #define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
9856 #define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
9857 #define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
9858 #define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
9859 #define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
9860 #define HRTIM_ADC4R_AD4TERST_Pos      (31U)
9861 #define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
9862 #define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
9863 
9864 /*******************  Bit definition for HRTIM_DLLCR register  ****************/
9865 #define HRTIM_DLLCR_CAL_Pos           (0U)
9866 #define HRTIM_DLLCR_CAL_Msk           (0x1UL << HRTIM_DLLCR_CAL_Pos)           /*!< 0x00000001 */
9867 #define HRTIM_DLLCR_CAL               HRTIM_DLLCR_CAL_Msk                      /*!< DLL calibration start */
9868 #define HRTIM_DLLCR_CALEN_Pos         (1U)
9869 #define HRTIM_DLLCR_CALEN_Msk         (0x1UL << HRTIM_DLLCR_CALEN_Pos)         /*!< 0x00000002 */
9870 #define HRTIM_DLLCR_CALEN             HRTIM_DLLCR_CALEN_Msk                    /*!< DLL calibration enable */
9871 #define HRTIM_DLLCR_CALRTE_Pos        (2U)
9872 #define HRTIM_DLLCR_CALRTE_Msk        (0x3UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x0000000C */
9873 #define HRTIM_DLLCR_CALRTE            HRTIM_DLLCR_CALRTE_Msk                   /*!< DLL calibration rate */
9874 #define HRTIM_DLLCR_CALRTE_0          (0x1UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x00000004 */
9875 #define HRTIM_DLLCR_CALRTE_1          (0x2UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x00000008 */
9876 
9877 /*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
9878 #define HRTIM_FLTINR1_FLT1E_Pos       (0U)
9879 #define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
9880 #define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
9881 #define HRTIM_FLTINR1_FLT1P_Pos       (1U)
9882 #define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
9883 #define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
9884 #define HRTIM_FLTINR1_FLT1SRC_0_Pos   (2U)
9885 #define HRTIM_FLTINR1_FLT1SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT1SRC_0_Pos)   /*!< 0x00000004 */
9886 #define HRTIM_FLTINR1_FLT1SRC_0       HRTIM_FLTINR1_FLT1SRC_0_Msk              /*!< Fault 1 source bit 0 */
9887 #define HRTIM_FLTINR1_FLT1F_Pos       (3U)
9888 #define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
9889 #define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
9890 #define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000008 */
9891 #define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000010 */
9892 #define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000020 */
9893 #define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000040 */
9894 #define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
9895 #define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
9896 #define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
9897 #define HRTIM_FLTINR1_FLT2E_Pos       (8U)
9898 #define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
9899 #define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
9900 #define HRTIM_FLTINR1_FLT2P_Pos       (9U)
9901 #define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
9902 #define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
9903 #define HRTIM_FLTINR1_FLT2SRC_0_Pos   (10U)
9904 #define HRTIM_FLTINR1_FLT2SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT2SRC_0_Pos)    /*!< 0x00000400 */
9905 #define HRTIM_FLTINR1_FLT2SRC_0       HRTIM_FLTINR1_FLT2SRC_0_Msk               /*!< Fault 2 source bit 0 */
9906 #define HRTIM_FLTINR1_FLT2F_Pos       (11U)
9907 #define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
9908 #define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
9909 #define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00000800 */
9910 #define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00001000 */
9911 #define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00002000 */
9912 #define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00004000 */
9913 #define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
9914 #define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
9915 #define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
9916 #define HRTIM_FLTINR1_FLT3E_Pos       (16U)
9917 #define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
9918 #define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
9919 #define HRTIM_FLTINR1_FLT3P_Pos       (17U)
9920 #define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
9921 #define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
9922 #define HRTIM_FLTINR1_FLT3SRC_0_Pos   (18U)
9923 #define HRTIM_FLTINR1_FLT3SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT3SRC_0_Pos)   /*!< 0x00040000 */
9924 #define HRTIM_FLTINR1_FLT3SRC_0       HRTIM_FLTINR1_FLT3SRC_0_Msk              /*!< Fault 3 source bit 0 */
9925 #define HRTIM_FLTINR1_FLT3F_Pos       (19U)
9926 #define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
9927 #define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
9928 #define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00080000 */
9929 #define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00100000 */
9930 #define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00200000 */
9931 #define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00400000 */
9932 #define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
9933 #define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
9934 #define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
9935 #define HRTIM_FLTINR1_FLT4E_Pos       (24U)
9936 #define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
9937 #define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
9938 #define HRTIM_FLTINR1_FLT4P_Pos       (25U)
9939 #define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
9940 #define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
9941 #define HRTIM_FLTINR1_FLT4SRC_0_Pos   (26U)
9942 #define HRTIM_FLTINR1_FLT4SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT4SRC_0_Pos)    /*!< 0x04000000 */
9943 #define HRTIM_FLTINR1_FLT4SRC_0       HRTIM_FLTINR1_FLT4SRC_0_Msk               /*!< Fault 4 source bit 0 */
9944 #define HRTIM_FLTINR1_FLT4F_Pos       (27U)
9945 #define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
9946 #define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
9947 #define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x08000000 */
9948 #define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x10000000 */
9949 #define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x20000000 */
9950 #define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x40000000 */
9951 #define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
9952 #define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
9953 #define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
9954 
9955 /*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
9956 #define HRTIM_FLTINR2_FLT5E_Pos       (0U)
9957 #define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
9958 #define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
9959 #define HRTIM_FLTINR2_FLT5P_Pos       (1U)
9960 #define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
9961 #define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
9962 #define HRTIM_FLTINR2_FLT5SRC_0_Pos   (2U)
9963 #define HRTIM_FLTINR2_FLT5SRC_0_Msk   (0x1UL << HRTIM_FLTINR2_FLT5SRC_0_Pos)   /*!< 0x00000004 */
9964 #define HRTIM_FLTINR2_FLT5SRC_0       HRTIM_FLTINR2_FLT5SRC_0_Msk              /*!< Fault 5 source bit 0 */
9965 #define HRTIM_FLTINR2_FLT5F_Pos       (3U)
9966 #define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
9967 #define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
9968 #define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000008 */
9969 #define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000010 */
9970 #define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000020 */
9971 #define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000040 */
9972 #define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
9973 #define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
9974 #define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
9975 #define HRTIM_FLTINR2_FLT6E_Pos       (8U)
9976 #define HRTIM_FLTINR2_FLT6E_Msk       (0x1UL << HRTIM_FLTINR2_FLT6E_Pos)       /*!< 0x00000100 */
9977 #define HRTIM_FLTINR2_FLT6E           HRTIM_FLTINR2_FLT6E_Msk                  /*!< Fault 6 enable */
9978 #define HRTIM_FLTINR2_FLT6P_Pos       (9U)
9979 #define HRTIM_FLTINR2_FLT6P_Msk       (0x1UL << HRTIM_FLTINR2_FLT6P_Pos)       /*!< 0x00000200 */
9980 #define HRTIM_FLTINR2_FLT6P           HRTIM_FLTINR2_FLT6P_Msk                  /*!< Fault 6 polarity */
9981 #define HRTIM_FLTINR2_FLT6SRC_0_Pos   (10U)
9982 #define HRTIM_FLTINR2_FLT6SRC_0_Msk   (0x1UL << HRTIM_FLTINR2_FLT6SRC_0_Pos)   /*!< 0x00000400 */
9983 #define HRTIM_FLTINR2_FLT6SRC_0       HRTIM_FLTINR2_FLT6SRC_0_Msk              /*!< Fault 6 source bit 0 */
9984 #define HRTIM_FLTINR2_FLT6F_Pos       (11U)
9985 #define HRTIM_FLTINR2_FLT6F_Msk       (0xFUL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00007800 */
9986 #define HRTIM_FLTINR2_FLT6F           HRTIM_FLTINR2_FLT6F_Msk                  /*!< Fault 6 filter */
9987 #define HRTIM_FLTINR2_FLT6F_0         (0x1UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000008 */
9988 #define HRTIM_FLTINR2_FLT6F_1         (0x2UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000010 */
9989 #define HRTIM_FLTINR2_FLT6F_2         (0x4UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000020 */
9990 #define HRTIM_FLTINR2_FLT6F_3         (0x8UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000040 */
9991 #define HRTIM_FLTINR2_FLT6LCK_Pos     (15U)
9992 #define HRTIM_FLTINR2_FLT6LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT6LCK_Pos)     /*!< 0x00008000 */
9993 #define HRTIM_FLTINR2_FLT6LCK         HRTIM_FLTINR2_FLT6LCK_Msk                /*!< Fault 6 lock */
9994 #define HRTIM_FLTINR2_FLT1SRC_1_Pos   (16U)
9995 #define HRTIM_FLTINR2_FLT1SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT1SRC_1_Pos)   /*!< 0x00010000 */
9996 #define HRTIM_FLTINR2_FLT1SRC_1       HRTIM_FLTINR2_FLT1SRC_1_Msk              /*!< Fault 1 source bit 1 */
9997 #define HRTIM_FLTINR2_FLT2SRC_1_Pos   (17U)
9998 #define HRTIM_FLTINR2_FLT2SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT2SRC_1_Pos)   /*!< 0x00020000 */
9999 #define HRTIM_FLTINR2_FLT2SRC_1       HRTIM_FLTINR2_FLT2SRC_1_Msk              /*!< Fault 2 source bit1 */
10000 #define HRTIM_FLTINR2_FLT3SRC_1_Pos   (18U)
10001 #define HRTIM_FLTINR2_FLT3SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT3SRC_1_Pos)   /*!< 0x00040000 */
10002 #define HRTIM_FLTINR2_FLT3SRC_1       HRTIM_FLTINR2_FLT3SRC_1_Msk              /*!< Fault 3 source bit 1 */
10003 #define HRTIM_FLTINR2_FLT4SRC_1_Pos   (19U)
10004 #define HRTIM_FLTINR2_FLT4SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT4SRC_1_Pos)   /*!< 0x00080000 */
10005 #define HRTIM_FLTINR2_FLT4SRC_1       HRTIM_FLTINR2_FLT4SRC_1_Msk              /*!< Fault 4 source bit 1 */
10006 #define HRTIM_FLTINR2_FLT5SRC_1_Pos   (20U)
10007 #define HRTIM_FLTINR2_FLT5SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT5SRC_1_Pos)   /*!< 0x00100000 */
10008 #define HRTIM_FLTINR2_FLT5SRC_1       HRTIM_FLTINR2_FLT5SRC_1_Msk              /*!< Fault 5 source bit 1 */
10009 #define HRTIM_FLTINR2_FLT6SRC_1_Pos   (21U)
10010 #define HRTIM_FLTINR2_FLT6SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT6SRC_1_Pos)   /*!< 0x00200000 */
10011 #define HRTIM_FLTINR2_FLT6SRC_1       HRTIM_FLTINR2_FLT6SRC_1_Msk              /*!< Fault 6 source bit 1 */
10012 #define HRTIM_FLTINR2_FLTSD_Pos       (24U)
10013 #define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
10014 #define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
10015 #define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x01000000 */
10016 #define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x02000000 */
10017 
10018 /*******************  Bit definition for HRTIM_FLTINR3 register  ***************/
10019 #define HRTIM_FLTINR3_FLT1BLKE_Pos     (0U)
10020 #define HRTIM_FLTINR3_FLT1BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT1BLKE_Pos)   /*!< 0x00000001 */
10021 #define HRTIM_FLTINR3_FLT1BLKE         HRTIM_FLTINR3_FLT1BLKE_Msk              /*!< Fault 1 Blanking Enable */
10022 #define HRTIM_FLTINR3_FLT1BLKS_Pos     (1U)
10023 #define HRTIM_FLTINR3_FLT1BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT1BLKS_Pos)   /*!< 0x00000002 */
10024 #define HRTIM_FLTINR3_FLT1BLKS         HRTIM_FLTINR3_FLT1BLKS_Msk              /*!< Fault 1 Blanking Source */
10025 #define HRTIM_FLTINR3_FLT1CNT_Pos      (2U)
10026 #define HRTIM_FLTINR3_FLT1CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x0000003C */
10027 #define HRTIM_FLTINR3_FLT1CNT          HRTIM_FLTINR3_FLT1CNT_Msk               /*!< Fault 1 Counter */
10028 #define HRTIM_FLTINR3_FLT1CNT_0        (0x1UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000004 */
10029 #define HRTIM_FLTINR3_FLT1CNT_1        (0x2UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000008 */
10030 #define HRTIM_FLTINR3_FLT1CNT_2        (0x4UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000010 */
10031 #define HRTIM_FLTINR3_FLT1CNT_3        (0x8UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000020 */
10032 #define HRTIM_FLTINR3_FLT1CRES_Pos     (6U)
10033 #define HRTIM_FLTINR3_FLT1CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT1CRES_Pos)   /*!< 0x00000040 */
10034 #define HRTIM_FLTINR3_FLT1CRES         HRTIM_FLTINR3_FLT1CRES_Msk              /*!< Fault 1 Counter Reset  */
10035 #define HRTIM_FLTINR3_FLT1RSTM_Pos     (7U)
10036 #define HRTIM_FLTINR3_FLT1RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT1RSTM_Pos)   /*!< 0x00000080 */
10037 #define HRTIM_FLTINR3_FLT1RSTM         HRTIM_FLTINR3_FLT1RSTM_Msk              /*!< Fault 1 Counter Reset Mode */
10038 #define HRTIM_FLTINR3_FLT2BLKE_Pos     (8U)
10039 #define HRTIM_FLTINR3_FLT2BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT2BLKE_Pos)   /*!< 0x00000100 */
10040 #define HRTIM_FLTINR3_FLT2BLKE         HRTIM_FLTINR3_FLT2BLKE_Msk              /*!< Fault 2 Blanking Enable */
10041 #define HRTIM_FLTINR3_FLT2BLKS_Pos     (9U)
10042 #define HRTIM_FLTINR3_FLT2BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT2BLKS_Pos)   /*!< 0x00000200 */
10043 #define HRTIM_FLTINR3_FLT2BLKS         HRTIM_FLTINR3_FLT2BLKS_Msk              /*!< Fault 2 Blanking Source */
10044 #define HRTIM_FLTINR3_FLT2CNT_Pos      (10U)
10045 #define HRTIM_FLTINR3_FLT2CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00003C00 */
10046 #define HRTIM_FLTINR3_FLT2CNT          HRTIM_FLTINR3_FLT2CNT_Msk               /*!< Fault 2 Counter */
10047 #define HRTIM_FLTINR3_FLT2CNT_0        (0x1UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00000400 */
10048 #define HRTIM_FLTINR3_FLT2CNT_1        (0x2UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00000800 */
10049 #define HRTIM_FLTINR3_FLT2CNT_2        (0x4UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00001000 */
10050 #define HRTIM_FLTINR3_FLT2CNT_3        (0x8UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00002000 */
10051 #define HRTIM_FLTINR3_FLT2CRES_Pos     (14U)
10052 #define HRTIM_FLTINR3_FLT2CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT2CRES_Pos)   /*!< 0x00004000 */
10053 #define HRTIM_FLTINR3_FLT2CRES         HRTIM_FLTINR3_FLT2CRES_Msk              /*!< Fault 2 Counter Reset  */
10054 #define HRTIM_FLTINR3_FLT2RSTM_Pos     (15U)
10055 #define HRTIM_FLTINR3_FLT2RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT2RSTM_Pos)   /*!< 0x00008000 */
10056 #define HRTIM_FLTINR3_FLT2RSTM         HRTIM_FLTINR3_FLT2RSTM_Msk              /*!< Fault 2 Counter Reset Mode */
10057 #define HRTIM_FLTINR3_FLT3BLKE_Pos     (16U)
10058 #define HRTIM_FLTINR3_FLT3BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT3BLKE_Pos)   /*!< 0x00010000 */
10059 #define HRTIM_FLTINR3_FLT3BLKE         HRTIM_FLTINR3_FLT3BLKE_Msk              /*!< Fault 3 Blanking Enable */
10060 #define HRTIM_FLTINR3_FLT3BLKS_Pos     (17U)
10061 #define HRTIM_FLTINR3_FLT3BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT3BLKS_Pos)   /*!< 0x00020000 */
10062 #define HRTIM_FLTINR3_FLT3BLKS         HRTIM_FLTINR3_FLT3BLKS_Msk              /*!< Fault 3 Blanking Source */
10063 #define HRTIM_FLTINR3_FLT3CNT_Pos      (18U)
10064 #define HRTIM_FLTINR3_FLT3CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x003C0000 */
10065 #define HRTIM_FLTINR3_FLT3CNT          HRTIM_FLTINR3_FLT3CNT_Msk               /*!< Fault 3 Counter */
10066 #define HRTIM_FLTINR3_FLT3CNT_0        (0x1UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00040000 */
10067 #define HRTIM_FLTINR3_FLT3CNT_1        (0x2UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00080000 */
10068 #define HRTIM_FLTINR3_FLT3CNT_2        (0x4UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00100000 */
10069 #define HRTIM_FLTINR3_FLT3CNT_3        (0x8UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00200000 */
10070 #define HRTIM_FLTINR3_FLT3CRES_Pos     (22U)
10071 #define HRTIM_FLTINR3_FLT3CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT3CRES_Pos)   /*!< 0x00400000 */
10072 #define HRTIM_FLTINR3_FLT3CRES         HRTIM_FLTINR3_FLT3CRES_Msk              /*!< Fault 3 Counter Reset  */
10073 #define HRTIM_FLTINR3_FLT3RSTM_Pos     (23U)
10074 #define HRTIM_FLTINR3_FLT3RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT3RSTM_Pos)   /*!< 0x00800000 */
10075 #define HRTIM_FLTINR3_FLT3RSTM         HRTIM_FLTINR3_FLT3RSTM_Msk              /*!< Fault 3 Counter Reset Mode */
10076 #define HRTIM_FLTINR3_FLT4BLKE_Pos     (24U)
10077 #define HRTIM_FLTINR3_FLT4BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT4BLKE_Pos)   /*!< 0x01000000 */
10078 #define HRTIM_FLTINR3_FLT4BLKE         HRTIM_FLTINR3_FLT4BLKE_Msk              /*!< Fault 4 Blanking Enable */
10079 #define HRTIM_FLTINR3_FLT4BLKS_Pos     (25U)
10080 #define HRTIM_FLTINR3_FLT4BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT4BLKS_Pos)   /*!< 0x02000000 */
10081 #define HRTIM_FLTINR3_FLT4BLKS         HRTIM_FLTINR3_FLT4BLKS_Msk              /*!< Fault 4 Blanking Source */
10082 #define HRTIM_FLTINR3_FLT4CNT_Pos      (26U)
10083 #define HRTIM_FLTINR3_FLT4CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x003C0000 */
10084 #define HRTIM_FLTINR3_FLT4CNT          HRTIM_FLTINR3_FLT4CNT_Msk               /*!< Fault 4 Counter */
10085 #define HRTIM_FLTINR3_FLT4CNT_0        (0x1UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00040000 */
10086 #define HRTIM_FLTINR3_FLT4CNT_1        (0x2UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00080000 */
10087 #define HRTIM_FLTINR3_FLT4CNT_2        (0x4UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00100000 */
10088 #define HRTIM_FLTINR3_FLT4CNT_3        (0x8UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00200000 */
10089 #define HRTIM_FLTINR3_FLT4CRES_Pos     (30U)
10090 #define HRTIM_FLTINR3_FLT4CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT4CRES_Pos)   /*!< 0x40000000 */
10091 #define HRTIM_FLTINR3_FLT4CRES         HRTIM_FLTINR3_FLT4CRES_Msk              /*!< Fault 4 Counter Reset  */
10092 #define HRTIM_FLTINR3_FLT4RSTM_Pos     (31U)
10093 #define HRTIM_FLTINR3_FLT4RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT4RSTM_Pos)   /*!< 0x80000000 */
10094 #define HRTIM_FLTINR3_FLT4RSTM         HRTIM_FLTINR3_FLT4RSTM_Msk              /*!< Fault 4 Counter Reset Mode */
10095 
10096 /*******************  Bit definition for HRTIM_FLTINR4 register  ***************/
10097 #define HRTIM_FLTINR4_FLT5BLKE_Pos     (0U)
10098 #define HRTIM_FLTINR4_FLT5BLKE_Msk     (0x1UL << HRTIM_FLTINR4_FLT5BLKE_Pos)   /*!< 0x00000001 */
10099 #define HRTIM_FLTINR4_FLT5BLKE         HRTIM_FLTINR4_FLT5BLKE_Msk              /*!< Fault 5 Blanking Enable */
10100 #define HRTIM_FLTINR4_FLT5BLKS_Pos     (1U)
10101 #define HRTIM_FLTINR4_FLT5BLKS_Msk     (0x1UL << HRTIM_FLTINR4_FLT5BLKS_Pos)   /*!< 0x00000002 */
10102 #define HRTIM_FLTINR4_FLT5BLKS         HRTIM_FLTINR4_FLT5BLKS_Msk              /*!< Fault 5 Blanking Source */
10103 #define HRTIM_FLTINR4_FLT5CNT_Pos      (2U)
10104 #define HRTIM_FLTINR4_FLT5CNT_Msk      (0xFUL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x0000003C */
10105 #define HRTIM_FLTINR4_FLT5CNT          HRTIM_FLTINR4_FLT5CNT_Msk               /*!< Fault 5 Counter */
10106 #define HRTIM_FLTINR4_FLT5CNT_0        (0x1UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000004 */
10107 #define HRTIM_FLTINR4_FLT5CNT_1        (0x2UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000008 */
10108 #define HRTIM_FLTINR4_FLT5CNT_2        (0x4UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000010 */
10109 #define HRTIM_FLTINR4_FLT5CNT_3        (0x8UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000020 */
10110 #define HRTIM_FLTINR4_FLT5CRES_Pos     (6U)
10111 #define HRTIM_FLTINR4_FLT5CRES_Msk     (0x1UL << HRTIM_FLTINR4_FLT5CRES_Pos)   /*!< 0x00000040 */
10112 #define HRTIM_FLTINR4_FLT5CRES         HRTIM_FLTINR4_FLT5CRES_Msk              /*!< Fault 5 Counter Reset  */
10113 #define HRTIM_FLTINR4_FLT5RSTM_Pos     (7U)
10114 #define HRTIM_FLTINR4_FLT5RSTM_Msk     (0x1UL << HRTIM_FLTINR4_FLT5RSTM_Pos)   /*!< 0x00000080 */
10115 #define HRTIM_FLTINR4_FLT5RSTM         HRTIM_FLTINR4_FLT5RSTM_Msk              /*!< Fault 5 Counter Reset Mode */
10116 #define HRTIM_FLTINR4_FLT6BLKE_Pos     (8U)
10117 #define HRTIM_FLTINR4_FLT6BLKE_Msk     (0x1UL << HRTIM_FLTINR4_FLT6BLKE_Pos)   /*!< 0x00000100 */
10118 #define HRTIM_FLTINR4_FLT6BLKE         HRTIM_FLTINR4_FLT6BLKE_Msk              /*!< Fault 6 Blanking Enable */
10119 #define HRTIM_FLTINR4_FLT6BLKS_Pos     (9U)
10120 #define HRTIM_FLTINR4_FLT6BLKS_Msk     (0x1UL << HRTIM_FLTINR4_FLT6BLKS_Pos)   /*!< 0x00000200 */
10121 #define HRTIM_FLTINR4_FLT6BLKS         HRTIM_FLTINR4_FLT6BLKS_Msk              /*!< Fault 6 Blanking Source */
10122 #define HRTIM_FLTINR4_FLT6CNT_Pos      (10U)
10123 #define HRTIM_FLTINR4_FLT6CNT_Msk      (0xFUL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00003C00 */
10124 #define HRTIM_FLTINR4_FLT6CNT          HRTIM_FLTINR4_FLT6CNT_Msk               /*!< Fault 6 Counter */
10125 #define HRTIM_FLTINR4_FLT6CNT_0        (0x1UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00000400 */
10126 #define HRTIM_FLTINR4_FLT6CNT_1        (0x2UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00000800 */
10127 #define HRTIM_FLTINR4_FLT6CNT_2        (0x4UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00001000 */
10128 #define HRTIM_FLTINR4_FLT6CNT_3        (0x8UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00002000 */
10129 #define HRTIM_FLTINR4_FLT6CRES_Pos     (14U)
10130 #define HRTIM_FLTINR4_FLT6CRES_Msk     (0x1UL << HRTIM_FLTINR4_FLT6CRES_Pos)   /*!< 0x00004000 */
10131 #define HRTIM_FLTINR4_FLT6CRES         HRTIM_FLTINR4_FLT6CRES_Msk              /*!< Fault 6 Counter Reset  */
10132 #define HRTIM_FLTINR4_FLT6RSTM_Pos     (15U)
10133 #define HRTIM_FLTINR4_FLT6RSTM_Msk     (0x1UL << HRTIM_FLTINR4_FLT6RSTM_Pos)   /*!< 0x00008000 */
10134 #define HRTIM_FLTINR4_FLT6RSTM         HRTIM_FLTINR4_FLT6RSTM_Msk              /*!< Fault 6 Counter Reset Mode */
10135 
10136 /*******************  Bit definition for HRTIM_BDMUPR register  ***************/
10137 #define HRTIM_BDMUPR_MCR_Pos          (0U)
10138 #define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
10139 #define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
10140 #define HRTIM_BDMUPR_MICR_Pos         (1U)
10141 #define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
10142 #define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
10143 #define HRTIM_BDMUPR_MDIER_Pos        (2U)
10144 #define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
10145 #define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
10146 #define HRTIM_BDMUPR_MCNT_Pos         (3U)
10147 #define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
10148 #define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
10149 #define HRTIM_BDMUPR_MPER_Pos         (4U)
10150 #define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
10151 #define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
10152 #define HRTIM_BDMUPR_MREP_Pos         (5U)
10153 #define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
10154 #define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
10155 #define HRTIM_BDMUPR_MCMP1_Pos        (6U)
10156 #define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
10157 #define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
10158 #define HRTIM_BDMUPR_MCMP2_Pos        (7U)
10159 #define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
10160 #define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
10161 #define HRTIM_BDMUPR_MCMP3_Pos        (8U)
10162 #define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
10163 #define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
10164 #define HRTIM_BDMUPR_MCMP4_Pos        (9U)
10165 #define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
10166 #define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
10167 
10168 /*******************  Bit definition for HRTIM_BDTUPR register  ***************/
10169 #define HRTIM_BDTUPR_TIMCR_Pos        (0U)
10170 #define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
10171 #define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
10172 #define HRTIM_BDTUPR_TIMICR_Pos       (1U)
10173 #define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
10174 #define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
10175 #define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
10176 #define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
10177 #define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
10178 #define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
10179 #define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
10180 #define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
10181 #define HRTIM_BDTUPR_TIMPER_Pos       (4U)
10182 #define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
10183 #define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
10184 #define HRTIM_BDTUPR_TIMREP_Pos       (5U)
10185 #define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
10186 #define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
10187 #define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
10188 #define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
10189 #define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
10190 #define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
10191 #define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
10192 #define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
10193 #define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
10194 #define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
10195 #define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
10196 #define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
10197 #define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
10198 #define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
10199 #define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
10200 #define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
10201 #define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
10202 #define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
10203 #define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
10204 #define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
10205 #define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
10206 #define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
10207 #define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
10208 #define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
10209 #define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
10210 #define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
10211 #define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
10212 #define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
10213 #define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
10214 #define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
10215 #define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
10216 #define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
10217 #define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
10218 #define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
10219 #define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
10220 #define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
10221 #define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
10222 #define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
10223 #define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
10224 #define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
10225 #define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
10226 #define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
10227 #define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
10228 #define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
10229 #define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
10230 #define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
10231 #define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
10232 #define HRTIM_BDTUPR_TIMCR2_Pos       (21U)
10233 #define HRTIM_BDTUPR_TIMCR2_Msk       (0x1UL << HRTIM_BDTUPR_TIMCR2_Pos)       /*!< 0x00200000 */
10234 #define HRTIM_BDTUPR_TIMCR2           HRTIM_BDTUPR_TIMCR2_Msk                  /*!<  TIMCR2 register update enable */
10235 #define HRTIM_BDTUPR_TIMEEFR3_Pos     (22U)
10236 #define HRTIM_BDTUPR_TIMEEFR3_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR3_Pos)     /*!< 0x00400000 */
10237 #define HRTIM_BDTUPR_TIMEEFR3         HRTIM_BDTUPR_TIMEEFR3_Msk                /*!<  TIMEEFR3 register update enable */
10238 
10239 /*******************  Bit definition for HRTIM_BDMADR register  ***************/
10240 #define HRTIM_BDMADR_BDMADR_Pos       (0U)
10241 #define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)/*!< 0xFFFFFFFF */
10242 #define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
10243 
10244 /*******************  Bit definition for HRTIM_ADC Extended Trigger register  ***************/
10245 #define HRTIM_ADCER_AD5TRG_Pos       (0U)
10246 #define HRTIM_ADCER_AD5TRG_Msk       (0x1FUL << HRTIM_ADCER_AD5TRG_Pos)    /*!< 0x0000001F */
10247 #define HRTIM_ADCER_AD5TRG           HRTIM_ADCER_AD5TRG_Msk                /*!< ADC5 trigger */
10248 #define HRTIM_ADCER_AD6TRG_Pos       (5U)
10249 #define HRTIM_ADCER_AD6TRG_Msk       (0x1FUL << HRTIM_ADCER_AD6TRG_Pos)    /*!< 0x000003E0 */
10250 #define HRTIM_ADCER_AD6TRG           HRTIM_ADCER_AD6TRG_Msk                /*!< ADC6 trigger */
10251 #define HRTIM_ADCER_AD7TRG_Pos       (10U)
10252 #define HRTIM_ADCER_AD7TRG_Msk       (0x1FUL << HRTIM_ADCER_AD7TRG_Pos)    /*!< 0x00007C00 */
10253 #define HRTIM_ADCER_AD7TRG           HRTIM_ADCER_AD7TRG_Msk                /*!< ADC7 trigger */
10254 #define HRTIM_ADCER_AD8TRG_Pos       (16U)
10255 #define HRTIM_ADCER_AD8TRG_Msk       (0x1FUL << HRTIM_ADCER_AD8TRG_Pos)    /*!< 0x001F0000 */
10256 #define HRTIM_ADCER_AD8TRG           HRTIM_ADCER_AD8TRG_Msk                /*!< ADC8 trigger */
10257 #define HRTIM_ADCER_AD9TRG_Pos       (21U)
10258 #define HRTIM_ADCER_AD9TRG_Msk       (0x1FUL << HRTIM_ADCER_AD9TRG_Pos)    /*!< 0x003E00000 */
10259 #define HRTIM_ADCER_AD9TRG           HRTIM_ADCER_AD9TRG_Msk                /*!< ADC9 trigger */
10260 #define HRTIM_ADCER_AD10TRG_Pos      (26U)
10261 #define HRTIM_ADCER_AD10TRG_Msk      (0x1FUL << HRTIM_ADCER_AD10TRG_Pos)    /*!< 0x7C000000 */
10262 #define HRTIM_ADCER_AD10TRG           HRTIM_ADCER_AD10TRG_Msk                /*!< ADC10 trigger */
10263 
10264 /*******************  Bit definition for HRTIM_ADC Trigger Update register  ***************/
10265 #define HRTIM_ADCUR_AD5USRC_Pos       (0U)
10266 #define HRTIM_ADCUR_AD5USRC_Msk       (0x7UL << HRTIM_ADCUR_AD5USRC_Pos)     /*!< 0x00000007 */
10267 #define HRTIM_ADCUR_AD5USRC           HRTIM_ADCUR_AD5USRC_Msk                /*!< ADC5 trigger Update Source */
10268 #define HRTIM_ADCUR_AD6USRC_Pos       (4U)
10269 #define HRTIM_ADCUR_AD6USRC_Msk       (0x7UL << HRTIM_ADCUR_AD6USRC_Pos)     /*!< 0x00000070 */
10270 #define HRTIM_ADCUR_AD6USRC           HRTIM_ADCUR_AD6USRC_Msk                /*!< ADC6 trigger Update Source */
10271 #define HRTIM_ADCUR_AD7USRC_Pos       (8U)
10272 #define HRTIM_ADCUR_AD7USRC_Msk       (0x7UL << HRTIM_ADCUR_AD7USRC_Pos)     /*!< 0x00000700 */
10273 #define HRTIM_ADCUR_AD7USRC           HRTIM_ADCUR_AD7USRC_Msk                /*!< ADC7 trigger Update Source */
10274 #define HRTIM_ADCUR_AD8USRC_Pos       (12U)
10275 #define HRTIM_ADCUR_AD8USRC_Msk       (0x7UL << HRTIM_ADCUR_AD8USRC_Pos)     /*!< 0x00007000 */
10276 #define HRTIM_ADCUR_AD8USRC           HRTIM_ADCUR_AD8USRC_Msk                /*!< ADC8 trigger Update Source */
10277 #define HRTIM_ADCUR_AD9USRC_Pos       (16U)
10278 #define HRTIM_ADCUR_AD9USRC_Msk       (0x7UL << HRTIM_ADCUR_AD9USRC_Pos)     /*!< 0x000070000 */
10279 #define HRTIM_ADCUR_AD9USRC           HRTIM_ADCUR_AD9USRC_Msk                /*!< ADC9 trigger Update Source */
10280 #define HRTIM_ADCUR_AD10USRC_Pos      (20U)
10281 #define HRTIM_ADCUR_AD10USRC_Msk      (0x7UL << HRTIM_ADCUR_AD10USRC_Pos)    /*!< 0x00700000 */
10282 #define HRTIM_ADCUR_AD10USRC          HRTIM_ADCUR_AD10USRC_Msk               /*!< ADC10 trigger Update Source */
10283 
10284 /*******************  Bit definition for HRTIM_ADCPS1 ADC Post Scaler register 1 ***************/
10285 #define HRTIM_ADCPS1_AD1PSC_Pos       (0U)
10286 #define HRTIM_ADCPS1_AD1PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD1PSC_Pos)    /*!< 0x0000001F */
10287 #define HRTIM_ADCPS1_AD1PSC           HRTIM_ADCPS1_AD1PSC_Msk                /*!< ADC1 post scaler */
10288 #define HRTIM_ADCPS1_AD2PSC_Pos       (6U)
10289 #define HRTIM_ADCPS1_AD2PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD2PSC_Pos)    /*!< 0x000007C0 */
10290 #define HRTIM_ADCPS1_AD2PSC           HRTIM_ADCPS1_AD2PSC_Msk                /*!< ADC2 post scaler */
10291 #define HRTIM_ADCPS1_AD3PSC_Pos       (12U)
10292 #define HRTIM_ADCPS1_AD3PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD3PSC_Pos)    /*!< 0x0001F000 */
10293 #define HRTIM_ADCPS1_AD3PSC           HRTIM_ADCPS1_AD3PSC_Msk                /*!< ADC3 post scaler */
10294 #define HRTIM_ADCPS1_AD4PSC_Pos       (18U)
10295 #define HRTIM_ADCPS1_AD4PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD4PSC_Pos)    /*!< 0x007C0000 */
10296 #define HRTIM_ADCPS1_AD4PSC           HRTIM_ADCPS1_AD4PSC_Msk                /*!< ADC4 post scaler */
10297 #define HRTIM_ADCPS1_AD5PSC_Pos       (24U)
10298 #define HRTIM_ADCPS1_AD5PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD5PSC_Pos)    /*!< 0x1F000000 */
10299 #define HRTIM_ADCPS1_AD5PSC           HRTIM_ADCPS1_AD5PSC_Msk                /*!< ADC5 post scaler */
10300 
10301 /*******************  Bit definition for HRTIM_ADCPS2 ADC Post Scaler register 2 ***************/
10302 #define HRTIM_ADCPS2_AD6PSC_Pos       (0U)
10303 #define HRTIM_ADCPS2_AD6PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD6PSC_Pos)    /*!< 0x0000001F */
10304 #define HRTIM_ADCPS2_AD6PSC           HRTIM_ADCPS2_AD6PSC_Msk                /*!< ADC6 post scaler */
10305 #define HRTIM_ADCPS2_AD7PSC_Pos       (6U)
10306 #define HRTIM_ADCPS2_AD7PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD7PSC_Pos)    /*!< 0x000007C0 */
10307 #define HRTIM_ADCPS2_AD7PSC           HRTIM_ADCPS2_AD7PSC_Msk                /*!< ADC7 post scaler */
10308 #define HRTIM_ADCPS2_AD8PSC_Pos       (12U)
10309 #define HRTIM_ADCPS2_AD8PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD8PSC_Pos)    /*!< 0x0001F000 */
10310 #define HRTIM_ADCPS2_AD8PSC           HRTIM_ADCPS2_AD8PSC_Msk                /*!< ADC8 post scaler */
10311 #define HRTIM_ADCPS2_AD9PSC_Pos       (18U)
10312 #define HRTIM_ADCPS2_AD9PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD9PSC_Pos)    /*!< 0x007C0000 */
10313 #define HRTIM_ADCPS2_AD9PSC           HRTIM_ADCPS2_AD9PSC_Msk                /*!< ADC9 post scaler */
10314 #define HRTIM_ADCPS2_AD10PSC_Pos      (24U)
10315 #define HRTIM_ADCPS2_AD10PSC_Msk      (0x1FUL << HRTIM_ADCPS2_AD10PSC_Pos)   /*!< 0x1F000000 */
10316 #define HRTIM_ADCPS2_AD10PSC          HRTIM_ADCPS2_AD10PSC_Msk               /*!< ADC10 post scaler */
10317 
10318 
10319 /******************************************************************************/
10320 /*                                                                            */
10321 /*                      Inter-integrated Circuit Interface (I2C)              */
10322 /*                                                                            */
10323 /******************************************************************************/
10324 /*******************  Bit definition for I2C_CR1 register  *******************/
10325 #define I2C_CR1_PE_Pos               (0U)
10326 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
10327 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
10328 #define I2C_CR1_TXIE_Pos             (1U)
10329 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
10330 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
10331 #define I2C_CR1_RXIE_Pos             (2U)
10332 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
10333 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
10334 #define I2C_CR1_ADDRIE_Pos           (3U)
10335 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
10336 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
10337 #define I2C_CR1_NACKIE_Pos           (4U)
10338 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
10339 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
10340 #define I2C_CR1_STOPIE_Pos           (5U)
10341 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
10342 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
10343 #define I2C_CR1_TCIE_Pos             (6U)
10344 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
10345 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
10346 #define I2C_CR1_ERRIE_Pos            (7U)
10347 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
10348 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
10349 #define I2C_CR1_DNF_Pos              (8U)
10350 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
10351 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
10352 #define I2C_CR1_ANFOFF_Pos           (12U)
10353 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
10354 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
10355 #define I2C_CR1_SWRST_Pos            (13U)
10356 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
10357 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
10358 #define I2C_CR1_TXDMAEN_Pos          (14U)
10359 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
10360 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
10361 #define I2C_CR1_RXDMAEN_Pos          (15U)
10362 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
10363 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
10364 #define I2C_CR1_SBC_Pos              (16U)
10365 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
10366 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
10367 #define I2C_CR1_NOSTRETCH_Pos        (17U)
10368 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
10369 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
10370 #define I2C_CR1_WUPEN_Pos            (18U)
10371 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
10372 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
10373 #define I2C_CR1_GCEN_Pos             (19U)
10374 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
10375 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
10376 #define I2C_CR1_SMBHEN_Pos           (20U)
10377 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
10378 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
10379 #define I2C_CR1_SMBDEN_Pos           (21U)
10380 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
10381 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
10382 #define I2C_CR1_ALERTEN_Pos          (22U)
10383 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
10384 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
10385 #define I2C_CR1_PECEN_Pos            (23U)
10386 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
10387 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
10388 
10389 /******************  Bit definition for I2C_CR2 register  ********************/
10390 #define I2C_CR2_SADD_Pos             (0U)
10391 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
10392 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
10393 #define I2C_CR2_RD_WRN_Pos           (10U)
10394 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
10395 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
10396 #define I2C_CR2_ADD10_Pos            (11U)
10397 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
10398 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
10399 #define I2C_CR2_HEAD10R_Pos          (12U)
10400 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
10401 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
10402 #define I2C_CR2_START_Pos            (13U)
10403 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
10404 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
10405 #define I2C_CR2_STOP_Pos             (14U)
10406 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
10407 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
10408 #define I2C_CR2_NACK_Pos             (15U)
10409 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
10410 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
10411 #define I2C_CR2_NBYTES_Pos           (16U)
10412 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
10413 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
10414 #define I2C_CR2_RELOAD_Pos           (24U)
10415 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
10416 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
10417 #define I2C_CR2_AUTOEND_Pos          (25U)
10418 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
10419 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
10420 #define I2C_CR2_PECBYTE_Pos          (26U)
10421 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
10422 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
10423 
10424 /*******************  Bit definition for I2C_OAR1 register  ******************/
10425 #define I2C_OAR1_OA1_Pos             (0U)
10426 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
10427 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
10428 #define I2C_OAR1_OA1MODE_Pos         (10U)
10429 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
10430 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
10431 #define I2C_OAR1_OA1EN_Pos           (15U)
10432 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
10433 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
10434 
10435 /*******************  Bit definition for I2C_OAR2 register  ******************/
10436 #define I2C_OAR2_OA2_Pos             (1U)
10437 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
10438 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
10439 #define I2C_OAR2_OA2MSK_Pos          (8U)
10440 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
10441 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
10442 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
10443 #define I2C_OAR2_OA2MASK01_Pos       (8U)
10444 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
10445 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
10446 #define I2C_OAR2_OA2MASK02_Pos       (9U)
10447 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
10448 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10449 #define I2C_OAR2_OA2MASK03_Pos       (8U)
10450 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
10451 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10452 #define I2C_OAR2_OA2MASK04_Pos       (10U)
10453 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
10454 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10455 #define I2C_OAR2_OA2MASK05_Pos       (8U)
10456 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
10457 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10458 #define I2C_OAR2_OA2MASK06_Pos       (9U)
10459 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
10460 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
10461 #define I2C_OAR2_OA2MASK07_Pos       (8U)
10462 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
10463 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
10464 #define I2C_OAR2_OA2EN_Pos           (15U)
10465 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
10466 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
10467 
10468 /*******************  Bit definition for I2C_TIMINGR register *******************/
10469 #define I2C_TIMINGR_SCLL_Pos         (0U)
10470 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
10471 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
10472 #define I2C_TIMINGR_SCLH_Pos         (8U)
10473 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
10474 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
10475 #define I2C_TIMINGR_SDADEL_Pos       (16U)
10476 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
10477 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
10478 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
10479 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
10480 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
10481 #define I2C_TIMINGR_PRESC_Pos        (28U)
10482 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
10483 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
10484 
10485 /******************* Bit definition for I2C_TIMEOUTR register *******************/
10486 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
10487 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
10488 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
10489 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
10490 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
10491 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
10492 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
10493 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
10494 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
10495 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
10496 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
10497 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
10498 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
10499 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
10500 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
10501 
10502 /******************  Bit definition for I2C_ISR register  *********************/
10503 #define I2C_ISR_TXE_Pos              (0U)
10504 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
10505 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
10506 #define I2C_ISR_TXIS_Pos             (1U)
10507 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
10508 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
10509 #define I2C_ISR_RXNE_Pos             (2U)
10510 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
10511 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
10512 #define I2C_ISR_ADDR_Pos             (3U)
10513 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
10514 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
10515 #define I2C_ISR_NACKF_Pos            (4U)
10516 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
10517 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
10518 #define I2C_ISR_STOPF_Pos            (5U)
10519 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
10520 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
10521 #define I2C_ISR_TC_Pos               (6U)
10522 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
10523 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
10524 #define I2C_ISR_TCR_Pos              (7U)
10525 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
10526 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
10527 #define I2C_ISR_BERR_Pos             (8U)
10528 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
10529 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
10530 #define I2C_ISR_ARLO_Pos             (9U)
10531 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
10532 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
10533 #define I2C_ISR_OVR_Pos              (10U)
10534 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
10535 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
10536 #define I2C_ISR_PECERR_Pos           (11U)
10537 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
10538 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
10539 #define I2C_ISR_TIMEOUT_Pos          (12U)
10540 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
10541 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
10542 #define I2C_ISR_ALERT_Pos            (13U)
10543 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
10544 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
10545 #define I2C_ISR_BUSY_Pos             (15U)
10546 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
10547 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
10548 #define I2C_ISR_DIR_Pos              (16U)
10549 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
10550 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
10551 #define I2C_ISR_ADDCODE_Pos          (17U)
10552 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
10553 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
10554 
10555 /******************  Bit definition for I2C_ICR register  *********************/
10556 #define I2C_ICR_ADDRCF_Pos           (3U)
10557 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
10558 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
10559 #define I2C_ICR_NACKCF_Pos           (4U)
10560 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
10561 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
10562 #define I2C_ICR_STOPCF_Pos           (5U)
10563 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
10564 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
10565 #define I2C_ICR_BERRCF_Pos           (8U)
10566 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
10567 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
10568 #define I2C_ICR_ARLOCF_Pos           (9U)
10569 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
10570 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
10571 #define I2C_ICR_OVRCF_Pos            (10U)
10572 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
10573 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
10574 #define I2C_ICR_PECCF_Pos            (11U)
10575 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
10576 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
10577 #define I2C_ICR_TIMOUTCF_Pos         (12U)
10578 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
10579 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
10580 #define I2C_ICR_ALERTCF_Pos          (13U)
10581 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
10582 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
10583 
10584 /******************  Bit definition for I2C_PECR register  *********************/
10585 #define I2C_PECR_PEC_Pos             (0U)
10586 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
10587 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
10588 
10589 /******************  Bit definition for I2C_RXDR register  *********************/
10590 #define I2C_RXDR_RXDATA_Pos          (0U)
10591 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
10592 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
10593 
10594 /******************  Bit definition for I2C_TXDR register  *********************/
10595 #define I2C_TXDR_TXDATA_Pos          (0U)
10596 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
10597 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
10598 
10599 /******************************************************************************/
10600 /*                                                                            */
10601 /*                           Independent WATCHDOG                             */
10602 /*                                                                            */
10603 /******************************************************************************/
10604 /*******************  Bit definition for IWDG_KR register  ********************/
10605 #define IWDG_KR_KEY_Pos      (0U)
10606 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
10607 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
10608 
10609 /*******************  Bit definition for IWDG_PR register  ********************/
10610 #define IWDG_PR_PR_Pos       (0U)
10611 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
10612 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
10613 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
10614 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
10615 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
10616 
10617 /*******************  Bit definition for IWDG_RLR register  *******************/
10618 #define IWDG_RLR_RL_Pos      (0U)
10619 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
10620 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
10621 
10622 /*******************  Bit definition for IWDG_SR register  ********************/
10623 #define IWDG_SR_PVU_Pos      (0U)
10624 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
10625 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
10626 #define IWDG_SR_RVU_Pos      (1U)
10627 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
10628 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
10629 #define IWDG_SR_WVU_Pos      (2U)
10630 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
10631 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
10632 
10633 /*******************  Bit definition for IWDG_KR register  ********************/
10634 #define IWDG_WINR_WIN_Pos    (0U)
10635 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
10636 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
10637 
10638 /******************************************************************************/
10639 /*                                                                            */
10640 /*                         Operational Amplifier (OPAMP)                      */
10641 /*                                                                            */
10642 /******************************************************************************/
10643 /*********************  Bit definition for OPAMPx_CSR register  ***************/
10644 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
10645 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)         /*!< 0x00000001 */
10646 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
10647 #define OPAMP_CSR_FORCEVP_Pos        (1U)
10648 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)          /*!< 0x00000002 */
10649 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
10650 #define OPAMP_CSR_VPSEL_Pos          (2U)
10651 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x0000000C */
10652 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
10653 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000004 */
10654 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)            /*!< 0x00000008 */
10655 #define OPAMP_CSR_USERTRIM_Pos       (4U)
10656 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00000010 */
10657 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
10658 #define OPAMP_CSR_VMSEL_Pos          (5U)
10659 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000060 */
10660 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
10661 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000020 */
10662 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)            /*!< 0x00000040 */
10663 #define OPAMP_CSR_HIGHSPEEDEN_Pos    (7U)
10664 #define OPAMP_CSR_HIGHSPEEDEN_Msk    (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)      /*!< 0x00000080 */
10665 #define OPAMP_CSR_HIGHSPEEDEN        OPAMP_CSR_HIGHSPEEDEN_Msk                 /*!< High speed mode enable */
10666 #define OPAMP_CSR_OPAMPINTEN_Pos     (8U)
10667 #define OPAMP_CSR_OPAMPINTEN_Msk     (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)       /*!< 0x00000100 */
10668 #define OPAMP_CSR_OPAMPINTEN         OPAMP_CSR_OPAMPINTEN_Msk                  /*!< Internal output enable */
10669 #define OPAMP_CSR_CALON_Pos          (11U)
10670 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00000800 */
10671 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
10672 #define OPAMP_CSR_CALSEL_Pos         (12U)
10673 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00003000 */
10674 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
10675 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00001000 */
10676 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
10677 #define OPAMP_CSR_PGGAIN_Pos         (14U)
10678 #define OPAMP_CSR_PGGAIN_Msk         (0x1FUL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x0007C000 */
10679 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
10680 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00004000 */
10681 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00008000 */
10682 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00010000 */
10683 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)           /*!< 0x00020000 */
10684 #define OPAMP_CSR_PGGAIN_4           (0x10UL << OPAMP_CSR_PGGAIN_Pos)          /*!< 0x00040000 */
10685 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
10686 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)     /*!< 0x00F80000 */
10687 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
10688 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
10689 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)     /*!< 0x1F000000 */
10690 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
10691 #define OPAMP_CSR_OUTCAL_Pos         (30U)
10692 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)           /*!< 0x40000000 */
10693 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP output status flag */
10694 #define OPAMP_CSR_LOCK_Pos           (31U)
10695 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)             /*!< 0x80000000 */
10696 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP control/status register lock */
10697 
10698 /*********************  Bit definition for OPAMPx_TCMR register  ***************/
10699 
10700 #define OPAMP_TCMR_VMSSEL_Pos        (0U)
10701 #define OPAMP_TCMR_VMSSEL_Msk        (0x1UL << OPAMP_TCMR_VMSSEL_Pos)          /*!< 0x00000001 */
10702 #define OPAMP_TCMR_VMSSEL            OPAMP_TCMR_VMSSEL_Msk                     /*!< Secondary inverting input selection */
10703 #define OPAMP_TCMR_VPSSEL_Pos        (1U)
10704 #define OPAMP_TCMR_VPSSEL_Msk        (0x3UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000006 */
10705 #define OPAMP_TCMR_VPSSEL            OPAMP_TCMR_VPSSEL_Msk                     /*!< Secondary non inverting input selection */
10706 #define OPAMP_TCMR_VPSSEL_0          (0x1UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000002 */
10707 #define OPAMP_TCMR_VPSSEL_1          (0x2UL << OPAMP_TCMR_VPSSEL_Pos)          /*!< 0x00000004 */
10708 #define OPAMP_TCMR_T1CMEN_Pos        (3U)
10709 #define OPAMP_TCMR_T1CMEN_Msk        (0x1UL << OPAMP_TCMR_T1CMEN_Pos)          /*!< 0x00000008 */
10710 #define OPAMP_TCMR_T1CMEN            OPAMP_TCMR_T1CMEN_Msk                     /*!< Timer 1 controlled mux mode enable */
10711 #define OPAMP_TCMR_T8CMEN_Pos        (4U)
10712 #define OPAMP_TCMR_T8CMEN_Msk        (0x1UL << OPAMP_TCMR_T8CMEN_Pos)          /*!< 0x00000010 */
10713 #define OPAMP_TCMR_T8CMEN            OPAMP_TCMR_T8CMEN_Msk                     /*!< Timer 8 controlled mux mode enable */
10714 #define OPAMP_TCMR_T20CMEN_Pos       (5U)
10715 #define OPAMP_TCMR_T20CMEN_Msk       (0x1UL << OPAMP_TCMR_T20CMEN_Pos)         /*!< 0x00000020 */
10716 #define OPAMP_TCMR_T20CMEN           OPAMP_TCMR_T20CMEN_Msk                    /*!< Timer 20 controlled mux mode enable */
10717 #define OPAMP_TCMR_LOCK_Pos          (31U)
10718 #define OPAMP_TCMR_LOCK_Msk          (0x1UL << OPAMP_TCMR_LOCK_Pos)            /*!< 0x80000000 */
10719 #define OPAMP_TCMR_LOCK              OPAMP_TCMR_LOCK_Msk                       /*!< OPAMP SW control register lock */
10720 
10721 
10722 /******************************************************************************/
10723 /*                                                                            */
10724 /*                             Power Control                                  */
10725 /*                                                                            */
10726 /******************************************************************************/
10727 
10728 /********************  Bit definition for PWR_CR1 register  ********************/
10729 
10730 #define PWR_CR1_LPR_Pos              (14U)
10731 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
10732 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
10733 #define PWR_CR1_VOS_Pos              (9U)
10734 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
10735 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10736 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
10737 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
10738 #define PWR_CR1_DBP_Pos              (8U)
10739 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
10740 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
10741 #define PWR_CR1_LPMS_Pos             (0U)
10742 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
10743 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
10744 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
10745 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
10746 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
10747 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
10748 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
10749 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
10750 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
10751 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
10752 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
10753 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
10754 
10755 
10756 /********************  Bit definition for PWR_CR2 register  ********************/
10757 
10758 /*!< PVME  Peripheral Voltage Monitor Enable */
10759 #define PWR_CR2_PVME_Pos             (4U)
10760 #define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
10761 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
10762 #define PWR_CR2_PVME4_Pos            (7U)
10763 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
10764 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
10765 #define PWR_CR2_PVME3_Pos            (6U)
10766 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
10767 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
10768 #define PWR_CR2_PVME2_Pos            (5U)
10769 #define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
10770 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
10771 #define PWR_CR2_PVME1_Pos            (4U)
10772 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
10773 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
10774 
10775 /*!< PVD level configuration */
10776 #define PWR_CR2_PLS_Pos              (1U)
10777 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
10778 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
10779 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
10780 #define PWR_CR2_PLS_LEV1_Pos         (1U)
10781 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
10782 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
10783 #define PWR_CR2_PLS_LEV2_Pos         (2U)
10784 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
10785 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
10786 #define PWR_CR2_PLS_LEV3_Pos         (1U)
10787 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
10788 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
10789 #define PWR_CR2_PLS_LEV4_Pos         (3U)
10790 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
10791 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
10792 #define PWR_CR2_PLS_LEV5_Pos         (1U)
10793 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
10794 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
10795 #define PWR_CR2_PLS_LEV6_Pos         (2U)
10796 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
10797 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
10798 #define PWR_CR2_PLS_LEV7_Pos         (1U)
10799 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
10800 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
10801 #define PWR_CR2_PVDE_Pos             (0U)
10802 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
10803 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
10804 
10805 /********************  Bit definition for PWR_CR3 register  ********************/
10806 #define PWR_CR3_EIWF_Pos             (15U)
10807 #define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
10808 #define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
10809 #define PWR_CR3_UCPD_DBDIS_Pos       (14U)
10810 #define PWR_CR3_UCPD_DBDIS_Msk       (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)         /*!< 0x00004000 */
10811 #define PWR_CR3_UCPD_DBDIS           PWR_CR3_UCPD_DBDIS_Msk                    /*!< USB Type-C and Power Delivery Dead Battery disable. */
10812 #define PWR_CR3_UCPD_STDBY_Pos       (13U)
10813 #define PWR_CR3_UCPD_STDBY_Msk       (0x1UL << PWR_CR3_UCPD_STDBY_Pos)         /*!< 0x00002000 */
10814 #define PWR_CR3_UCPD_STDBY           PWR_CR3_UCPD_STDBY_Msk                    /*!< USB Type-C and Power Delivery standby mode. */
10815 #define PWR_CR3_APC_Pos              (10U)
10816 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
10817 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
10818 #define PWR_CR3_RRS_Pos              (8U)
10819 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
10820 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
10821 #define PWR_CR3_EWUP5_Pos            (4U)
10822 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
10823 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
10824 #define PWR_CR3_EWUP4_Pos            (3U)
10825 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
10826 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
10827 #define PWR_CR3_EWUP3_Pos            (2U)
10828 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
10829 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
10830 #define PWR_CR3_EWUP2_Pos            (1U)
10831 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
10832 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
10833 #define PWR_CR3_EWUP1_Pos            (0U)
10834 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
10835 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
10836 #define PWR_CR3_EWUP_Pos             (0U)
10837 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
10838 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
10839 
10840 /********************  Bit definition for PWR_CR4 register  ********************/
10841 #define PWR_CR4_VBRS_Pos             (9U)
10842 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
10843 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
10844 #define PWR_CR4_VBE_Pos              (8U)
10845 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
10846 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
10847 #define PWR_CR4_WP5_Pos              (4U)
10848 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
10849 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
10850 #define PWR_CR4_WP4_Pos              (3U)
10851 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
10852 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
10853 #define PWR_CR4_WP3_Pos              (2U)
10854 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
10855 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
10856 #define PWR_CR4_WP2_Pos              (1U)
10857 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
10858 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
10859 #define PWR_CR4_WP1_Pos              (0U)
10860 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
10861 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
10862 
10863 /********************  Bit definition for PWR_SR1 register  ********************/
10864 #define PWR_SR1_WUFI_Pos             (15U)
10865 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
10866 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
10867 #define PWR_SR1_SBF_Pos              (8U)
10868 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
10869 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
10870 #define PWR_SR1_WUF_Pos              (0U)
10871 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
10872 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
10873 #define PWR_SR1_WUF5_Pos             (4U)
10874 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
10875 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
10876 #define PWR_SR1_WUF4_Pos             (3U)
10877 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
10878 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
10879 #define PWR_SR1_WUF3_Pos             (2U)
10880 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
10881 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
10882 #define PWR_SR1_WUF2_Pos             (1U)
10883 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
10884 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
10885 #define PWR_SR1_WUF1_Pos             (0U)
10886 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
10887 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
10888 
10889 /********************  Bit definition for PWR_SR2 register  ********************/
10890 #define PWR_SR2_PVMO4_Pos            (15U)
10891 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
10892 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
10893 #define PWR_SR2_PVMO3_Pos            (14U)
10894 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
10895 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
10896 #define PWR_SR2_PVMO2_Pos            (13U)
10897 #define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
10898 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
10899 #define PWR_SR2_PVMO1_Pos            (12U)
10900 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
10901 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
10902 #define PWR_SR2_PVDO_Pos             (11U)
10903 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
10904 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
10905 #define PWR_SR2_VOSF_Pos             (10U)
10906 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
10907 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
10908 #define PWR_SR2_REGLPF_Pos           (9U)
10909 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
10910 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
10911 #define PWR_SR2_REGLPS_Pos           (8U)
10912 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
10913 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
10914 
10915 /********************  Bit definition for PWR_SCR register  ********************/
10916 #define PWR_SCR_CSBF_Pos             (8U)
10917 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
10918 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
10919 #define PWR_SCR_CWUF_Pos             (0U)
10920 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
10921 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
10922 #define PWR_SCR_CWUF5_Pos            (4U)
10923 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
10924 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
10925 #define PWR_SCR_CWUF4_Pos            (3U)
10926 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
10927 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
10928 #define PWR_SCR_CWUF3_Pos            (2U)
10929 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
10930 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
10931 #define PWR_SCR_CWUF2_Pos            (1U)
10932 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
10933 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
10934 #define PWR_SCR_CWUF1_Pos            (0U)
10935 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
10936 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
10937 
10938 /********************  Bit definition for PWR_PUCRA register  ********************/
10939 #define PWR_PUCRA_PA15_Pos           (15U)
10940 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
10941 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
10942 #define PWR_PUCRA_PA13_Pos           (13U)
10943 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
10944 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
10945 #define PWR_PUCRA_PA12_Pos           (12U)
10946 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
10947 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
10948 #define PWR_PUCRA_PA11_Pos           (11U)
10949 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
10950 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
10951 #define PWR_PUCRA_PA10_Pos           (10U)
10952 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
10953 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
10954 #define PWR_PUCRA_PA9_Pos            (9U)
10955 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
10956 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
10957 #define PWR_PUCRA_PA8_Pos            (8U)
10958 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
10959 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
10960 #define PWR_PUCRA_PA7_Pos            (7U)
10961 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
10962 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
10963 #define PWR_PUCRA_PA6_Pos            (6U)
10964 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
10965 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
10966 #define PWR_PUCRA_PA5_Pos            (5U)
10967 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
10968 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
10969 #define PWR_PUCRA_PA4_Pos            (4U)
10970 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
10971 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
10972 #define PWR_PUCRA_PA3_Pos            (3U)
10973 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
10974 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
10975 #define PWR_PUCRA_PA2_Pos            (2U)
10976 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
10977 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
10978 #define PWR_PUCRA_PA1_Pos            (1U)
10979 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
10980 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
10981 #define PWR_PUCRA_PA0_Pos            (0U)
10982 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
10983 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
10984 
10985 /********************  Bit definition for PWR_PDCRA register  ********************/
10986 #define PWR_PDCRA_PA14_Pos           (14U)
10987 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
10988 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
10989 #define PWR_PDCRA_PA12_Pos           (12U)
10990 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
10991 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
10992 #define PWR_PDCRA_PA11_Pos           (11U)
10993 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
10994 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
10995 #define PWR_PDCRA_PA10_Pos           (10U)
10996 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
10997 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
10998 #define PWR_PDCRA_PA9_Pos            (9U)
10999 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
11000 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
11001 #define PWR_PDCRA_PA8_Pos            (8U)
11002 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
11003 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
11004 #define PWR_PDCRA_PA7_Pos            (7U)
11005 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
11006 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
11007 #define PWR_PDCRA_PA6_Pos            (6U)
11008 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
11009 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
11010 #define PWR_PDCRA_PA5_Pos            (5U)
11011 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
11012 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
11013 #define PWR_PDCRA_PA4_Pos            (4U)
11014 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
11015 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
11016 #define PWR_PDCRA_PA3_Pos            (3U)
11017 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
11018 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
11019 #define PWR_PDCRA_PA2_Pos            (2U)
11020 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
11021 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
11022 #define PWR_PDCRA_PA1_Pos            (1U)
11023 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
11024 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
11025 #define PWR_PDCRA_PA0_Pos            (0U)
11026 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
11027 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
11028 
11029 /********************  Bit definition for PWR_PUCRB register  ********************/
11030 
11031 #define PWR_PUCRB_PB15_Pos           (15U)
11032 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
11033 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
11034 #define PWR_PUCRB_PB14_Pos           (14U)
11035 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
11036 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
11037 #define PWR_PUCRB_PB13_Pos           (13U)
11038 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
11039 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
11040 #define PWR_PUCRB_PB12_Pos           (12U)
11041 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
11042 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
11043 #define PWR_PUCRB_PB11_Pos           (11U)
11044 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
11045 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
11046 #define PWR_PUCRB_PB10_Pos           (10U)
11047 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
11048 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
11049 #define PWR_PUCRB_PB9_Pos            (9U)
11050 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
11051 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
11052 #define PWR_PUCRB_PB8_Pos            (8U)
11053 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
11054 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
11055 #define PWR_PUCRB_PB7_Pos            (7U)
11056 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
11057 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
11058 #define PWR_PUCRB_PB6_Pos            (6U)
11059 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
11060 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
11061 #define PWR_PUCRB_PB5_Pos            (5U)
11062 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
11063 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
11064 #define PWR_PUCRB_PB4_Pos            (4U)
11065 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
11066 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
11067 #define PWR_PUCRB_PB3_Pos            (3U)
11068 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
11069 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
11070 #define PWR_PUCRB_PB2_Pos            (2U)
11071 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
11072 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
11073 #define PWR_PUCRB_PB1_Pos            (1U)
11074 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
11075 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
11076 #define PWR_PUCRB_PB0_Pos            (0U)
11077 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
11078 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
11079 
11080 /********************  Bit definition for PWR_PDCRB register  ********************/
11081 #define PWR_PDCRB_PB15_Pos           (15U)
11082 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
11083 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
11084 #define PWR_PDCRB_PB14_Pos           (14U)
11085 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
11086 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
11087 #define PWR_PDCRB_PB13_Pos           (13U)
11088 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
11089 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
11090 #define PWR_PDCRB_PB12_Pos           (12U)
11091 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
11092 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
11093 #define PWR_PDCRB_PB11_Pos           (11U)
11094 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
11095 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
11096 #define PWR_PDCRB_PB10_Pos           (10U)
11097 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
11098 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
11099 #define PWR_PDCRB_PB9_Pos            (9U)
11100 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
11101 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
11102 #define PWR_PDCRB_PB8_Pos            (8U)
11103 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
11104 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
11105 #define PWR_PDCRB_PB7_Pos            (7U)
11106 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
11107 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
11108 #define PWR_PDCRB_PB6_Pos            (6U)
11109 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
11110 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
11111 #define PWR_PDCRB_PB5_Pos            (5U)
11112 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
11113 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
11114 #define PWR_PDCRB_PB3_Pos            (3U)
11115 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
11116 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
11117 #define PWR_PDCRB_PB2_Pos            (2U)
11118 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
11119 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
11120 #define PWR_PDCRB_PB1_Pos            (1U)
11121 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
11122 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
11123 #define PWR_PDCRB_PB0_Pos            (0U)
11124 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
11125 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
11126 
11127 /********************  Bit definition for PWR_PUCRC register  ********************/
11128 #define PWR_PUCRC_PC15_Pos           (15U)
11129 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
11130 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
11131 #define PWR_PUCRC_PC14_Pos           (14U)
11132 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
11133 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
11134 #define PWR_PUCRC_PC13_Pos           (13U)
11135 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
11136 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
11137 #define PWR_PUCRC_PC12_Pos           (12U)
11138 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
11139 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
11140 #define PWR_PUCRC_PC11_Pos           (11U)
11141 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
11142 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
11143 #define PWR_PUCRC_PC10_Pos           (10U)
11144 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
11145 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
11146 #define PWR_PUCRC_PC9_Pos            (9U)
11147 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
11148 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
11149 #define PWR_PUCRC_PC8_Pos            (8U)
11150 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
11151 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
11152 #define PWR_PUCRC_PC7_Pos            (7U)
11153 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
11154 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
11155 #define PWR_PUCRC_PC6_Pos            (6U)
11156 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
11157 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
11158 #define PWR_PUCRC_PC5_Pos            (5U)
11159 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
11160 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
11161 #define PWR_PUCRC_PC4_Pos            (4U)
11162 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
11163 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
11164 #define PWR_PUCRC_PC3_Pos            (3U)
11165 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
11166 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
11167 #define PWR_PUCRC_PC2_Pos            (2U)
11168 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
11169 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
11170 #define PWR_PUCRC_PC1_Pos            (1U)
11171 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
11172 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
11173 #define PWR_PUCRC_PC0_Pos            (0U)
11174 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
11175 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
11176 
11177 /********************  Bit definition for PWR_PDCRC register  ********************/
11178 #define PWR_PDCRC_PC15_Pos           (15U)
11179 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
11180 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
11181 #define PWR_PDCRC_PC14_Pos           (14U)
11182 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
11183 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
11184 #define PWR_PDCRC_PC13_Pos           (13U)
11185 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
11186 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
11187 #define PWR_PDCRC_PC12_Pos           (12U)
11188 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
11189 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
11190 #define PWR_PDCRC_PC11_Pos           (11U)
11191 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
11192 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
11193 #define PWR_PDCRC_PC10_Pos           (10U)
11194 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
11195 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
11196 #define PWR_PDCRC_PC9_Pos            (9U)
11197 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
11198 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
11199 #define PWR_PDCRC_PC8_Pos            (8U)
11200 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
11201 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
11202 #define PWR_PDCRC_PC7_Pos            (7U)
11203 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
11204 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
11205 #define PWR_PDCRC_PC6_Pos            (6U)
11206 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
11207 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
11208 #define PWR_PDCRC_PC5_Pos            (5U)
11209 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
11210 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
11211 #define PWR_PDCRC_PC4_Pos            (4U)
11212 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
11213 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
11214 #define PWR_PDCRC_PC3_Pos            (3U)
11215 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
11216 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
11217 #define PWR_PDCRC_PC2_Pos            (2U)
11218 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
11219 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
11220 #define PWR_PDCRC_PC1_Pos            (1U)
11221 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
11222 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
11223 #define PWR_PDCRC_PC0_Pos            (0U)
11224 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
11225 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
11226 
11227 /********************  Bit definition for PWR_PUCRD register  ********************/
11228 #define PWR_PUCRD_PD15_Pos           (15U)
11229 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
11230 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
11231 #define PWR_PUCRD_PD14_Pos           (14U)
11232 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
11233 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
11234 #define PWR_PUCRD_PD13_Pos           (13U)
11235 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
11236 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
11237 #define PWR_PUCRD_PD12_Pos           (12U)
11238 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
11239 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
11240 #define PWR_PUCRD_PD11_Pos           (11U)
11241 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
11242 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
11243 #define PWR_PUCRD_PD10_Pos           (10U)
11244 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
11245 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
11246 #define PWR_PUCRD_PD9_Pos            (9U)
11247 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
11248 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
11249 #define PWR_PUCRD_PD8_Pos            (8U)
11250 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
11251 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
11252 #define PWR_PUCRD_PD7_Pos            (7U)
11253 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
11254 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
11255 #define PWR_PUCRD_PD6_Pos            (6U)
11256 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
11257 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
11258 #define PWR_PUCRD_PD5_Pos            (5U)
11259 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
11260 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
11261 #define PWR_PUCRD_PD4_Pos            (4U)
11262 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
11263 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
11264 #define PWR_PUCRD_PD3_Pos            (3U)
11265 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
11266 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
11267 #define PWR_PUCRD_PD2_Pos            (2U)
11268 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
11269 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
11270 #define PWR_PUCRD_PD1_Pos            (1U)
11271 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
11272 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
11273 #define PWR_PUCRD_PD0_Pos            (0U)
11274 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
11275 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
11276 
11277 /********************  Bit definition for PWR_PDCRD register  ********************/
11278 #define PWR_PDCRD_PD15_Pos           (15U)
11279 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
11280 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
11281 #define PWR_PDCRD_PD14_Pos           (14U)
11282 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
11283 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
11284 #define PWR_PDCRD_PD13_Pos           (13U)
11285 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
11286 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
11287 #define PWR_PDCRD_PD12_Pos           (12U)
11288 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
11289 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
11290 #define PWR_PDCRD_PD11_Pos           (11U)
11291 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
11292 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
11293 #define PWR_PDCRD_PD10_Pos           (10U)
11294 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
11295 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
11296 #define PWR_PDCRD_PD9_Pos            (9U)
11297 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
11298 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
11299 #define PWR_PDCRD_PD8_Pos            (8U)
11300 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
11301 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
11302 #define PWR_PDCRD_PD7_Pos            (7U)
11303 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
11304 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
11305 #define PWR_PDCRD_PD6_Pos            (6U)
11306 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
11307 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
11308 #define PWR_PDCRD_PD5_Pos            (5U)
11309 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
11310 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
11311 #define PWR_PDCRD_PD4_Pos            (4U)
11312 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
11313 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
11314 #define PWR_PDCRD_PD3_Pos            (3U)
11315 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
11316 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
11317 #define PWR_PDCRD_PD2_Pos            (2U)
11318 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
11319 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
11320 #define PWR_PDCRD_PD1_Pos            (1U)
11321 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
11322 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
11323 #define PWR_PDCRD_PD0_Pos            (0U)
11324 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
11325 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
11326 
11327 /********************  Bit definition for PWR_PUCRE register  ********************/
11328 #define PWR_PUCRE_PE15_Pos           (15U)
11329 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
11330 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
11331 #define PWR_PUCRE_PE14_Pos           (14U)
11332 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
11333 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
11334 #define PWR_PUCRE_PE13_Pos           (13U)
11335 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
11336 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
11337 #define PWR_PUCRE_PE12_Pos           (12U)
11338 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
11339 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
11340 #define PWR_PUCRE_PE11_Pos           (11U)
11341 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
11342 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
11343 #define PWR_PUCRE_PE10_Pos           (10U)
11344 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
11345 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
11346 #define PWR_PUCRE_PE9_Pos            (9U)
11347 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
11348 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
11349 #define PWR_PUCRE_PE8_Pos            (8U)
11350 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
11351 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
11352 #define PWR_PUCRE_PE7_Pos            (7U)
11353 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
11354 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
11355 #define PWR_PUCRE_PE6_Pos            (6U)
11356 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
11357 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
11358 #define PWR_PUCRE_PE5_Pos            (5U)
11359 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
11360 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
11361 #define PWR_PUCRE_PE4_Pos            (4U)
11362 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
11363 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
11364 #define PWR_PUCRE_PE3_Pos            (3U)
11365 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
11366 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
11367 #define PWR_PUCRE_PE2_Pos            (2U)
11368 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
11369 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
11370 #define PWR_PUCRE_PE1_Pos            (1U)
11371 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
11372 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
11373 #define PWR_PUCRE_PE0_Pos            (0U)
11374 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
11375 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
11376 
11377 /********************  Bit definition for PWR_PDCRE register  ********************/
11378 #define PWR_PDCRE_PE15_Pos           (15U)
11379 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
11380 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
11381 #define PWR_PDCRE_PE14_Pos           (14U)
11382 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
11383 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
11384 #define PWR_PDCRE_PE13_Pos           (13U)
11385 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
11386 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
11387 #define PWR_PDCRE_PE12_Pos           (12U)
11388 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
11389 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
11390 #define PWR_PDCRE_PE11_Pos           (11U)
11391 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
11392 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
11393 #define PWR_PDCRE_PE10_Pos           (10U)
11394 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
11395 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
11396 #define PWR_PDCRE_PE9_Pos            (9U)
11397 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
11398 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
11399 #define PWR_PDCRE_PE8_Pos            (8U)
11400 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
11401 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
11402 #define PWR_PDCRE_PE7_Pos            (7U)
11403 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
11404 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
11405 #define PWR_PDCRE_PE6_Pos            (6U)
11406 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
11407 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
11408 #define PWR_PDCRE_PE5_Pos            (5U)
11409 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
11410 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
11411 #define PWR_PDCRE_PE4_Pos            (4U)
11412 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
11413 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
11414 #define PWR_PDCRE_PE3_Pos            (3U)
11415 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
11416 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
11417 #define PWR_PDCRE_PE2_Pos            (2U)
11418 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
11419 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
11420 #define PWR_PDCRE_PE1_Pos            (1U)
11421 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
11422 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
11423 #define PWR_PDCRE_PE0_Pos            (0U)
11424 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
11425 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
11426 
11427 /********************  Bit definition for PWR_PUCRF register  ********************/
11428 #define PWR_PUCRF_PF15_Pos           (15U)
11429 #define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
11430 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
11431 #define PWR_PUCRF_PF14_Pos           (14U)
11432 #define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
11433 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
11434 #define PWR_PUCRF_PF13_Pos           (13U)
11435 #define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
11436 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
11437 #define PWR_PUCRF_PF12_Pos           (12U)
11438 #define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
11439 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
11440 #define PWR_PUCRF_PF11_Pos           (11U)
11441 #define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
11442 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
11443 #define PWR_PUCRF_PF10_Pos           (10U)
11444 #define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
11445 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
11446 #define PWR_PUCRF_PF9_Pos            (9U)
11447 #define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
11448 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
11449 #define PWR_PUCRF_PF8_Pos            (8U)
11450 #define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
11451 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
11452 #define PWR_PUCRF_PF7_Pos            (7U)
11453 #define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
11454 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
11455 #define PWR_PUCRF_PF6_Pos            (6U)
11456 #define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
11457 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
11458 #define PWR_PUCRF_PF5_Pos            (5U)
11459 #define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
11460 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
11461 #define PWR_PUCRF_PF4_Pos            (4U)
11462 #define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
11463 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
11464 #define PWR_PUCRF_PF3_Pos            (3U)
11465 #define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
11466 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
11467 #define PWR_PUCRF_PF2_Pos            (2U)
11468 #define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
11469 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
11470 #define PWR_PUCRF_PF1_Pos            (1U)
11471 #define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
11472 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
11473 #define PWR_PUCRF_PF0_Pos            (0U)
11474 #define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
11475 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
11476 
11477 /********************  Bit definition for PWR_PDCRF register  ********************/
11478 #define PWR_PDCRF_PF15_Pos           (15U)
11479 #define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */
11480 #define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
11481 #define PWR_PDCRF_PF14_Pos           (14U)
11482 #define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */
11483 #define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
11484 #define PWR_PDCRF_PF13_Pos           (13U)
11485 #define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */
11486 #define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
11487 #define PWR_PDCRF_PF12_Pos           (12U)
11488 #define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */
11489 #define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
11490 #define PWR_PDCRF_PF11_Pos           (11U)
11491 #define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */
11492 #define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
11493 #define PWR_PDCRF_PF10_Pos           (10U)
11494 #define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
11495 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
11496 #define PWR_PDCRF_PF9_Pos            (9U)
11497 #define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
11498 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
11499 #define PWR_PDCRF_PF8_Pos            (8U)
11500 #define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */
11501 #define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
11502 #define PWR_PDCRF_PF7_Pos            (7U)
11503 #define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */
11504 #define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
11505 #define PWR_PDCRF_PF6_Pos            (6U)
11506 #define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */
11507 #define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
11508 #define PWR_PDCRF_PF5_Pos            (5U)
11509 #define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */
11510 #define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
11511 #define PWR_PDCRF_PF4_Pos            (4U)
11512 #define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */
11513 #define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
11514 #define PWR_PDCRF_PF3_Pos            (3U)
11515 #define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */
11516 #define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
11517 #define PWR_PDCRF_PF2_Pos            (2U)
11518 #define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
11519 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
11520 #define PWR_PDCRF_PF1_Pos            (1U)
11521 #define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
11522 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
11523 #define PWR_PDCRF_PF0_Pos            (0U)
11524 #define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
11525 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
11526 
11527 /********************  Bit definition for PWR_PUCRG register  ********************/
11528 #define PWR_PUCRG_PG15_Pos           (15U)
11529 #define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */
11530 #define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
11531 #define PWR_PUCRG_PG14_Pos           (14U)
11532 #define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */
11533 #define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
11534 #define PWR_PUCRG_PG13_Pos           (13U)
11535 #define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */
11536 #define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
11537 #define PWR_PUCRG_PG12_Pos           (12U)
11538 #define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */
11539 #define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
11540 #define PWR_PUCRG_PG11_Pos           (11U)
11541 #define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */
11542 #define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
11543 #define PWR_PUCRG_PG10_Pos           (10U)
11544 #define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
11545 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
11546 #define PWR_PUCRG_PG9_Pos            (9U)
11547 #define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */
11548 #define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
11549 #define PWR_PUCRG_PG8_Pos            (8U)
11550 #define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */
11551 #define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
11552 #define PWR_PUCRG_PG7_Pos            (7U)
11553 #define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */
11554 #define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
11555 #define PWR_PUCRG_PG6_Pos            (6U)
11556 #define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */
11557 #define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
11558 #define PWR_PUCRG_PG5_Pos            (5U)
11559 #define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */
11560 #define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
11561 #define PWR_PUCRG_PG4_Pos            (4U)
11562 #define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */
11563 #define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
11564 #define PWR_PUCRG_PG3_Pos            (3U)
11565 #define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */
11566 #define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
11567 #define PWR_PUCRG_PG2_Pos            (2U)
11568 #define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */
11569 #define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
11570 #define PWR_PUCRG_PG1_Pos            (1U)
11571 #define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */
11572 #define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
11573 #define PWR_PUCRG_PG0_Pos            (0U)
11574 #define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */
11575 #define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
11576 
11577 /********************  Bit definition for PWR_PDCRG register  ********************/
11578 #define PWR_PDCRG_PG10_Pos           (10U)
11579 #define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
11580 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
11581 #define PWR_PDCRG_PG9_Pos            (9U)
11582 #define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
11583 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
11584 #define PWR_PDCRG_PG8_Pos            (8U)
11585 #define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
11586 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
11587 #define PWR_PDCRG_PG7_Pos            (7U)
11588 #define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
11589 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
11590 #define PWR_PDCRG_PG6_Pos            (6U)
11591 #define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
11592 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
11593 #define PWR_PDCRG_PG5_Pos            (5U)
11594 #define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
11595 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
11596 #define PWR_PDCRG_PG4_Pos            (4U)
11597 #define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
11598 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
11599 #define PWR_PDCRG_PG3_Pos            (3U)
11600 #define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
11601 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
11602 #define PWR_PDCRG_PG2_Pos            (2U)
11603 #define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
11604 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
11605 #define PWR_PDCRG_PG1_Pos            (1U)
11606 #define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
11607 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
11608 #define PWR_PDCRG_PG0_Pos            (0U)
11609 #define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
11610 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
11611 
11612 /********************  Bit definition for PWR_CR5 register  ********************/
11613 #define PWR_CR5_R1MODE_Pos           (8U)
11614 #define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
11615 #define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
11616 
11617 /******************************************************************************/
11618 /*                                                                            */
11619 /*                                    QUADSPI                                 */
11620 /*                                                                            */
11621 /******************************************************************************/
11622 /*****************  Bit definition for QUADSPI_CR register  *******************/
11623 #define QUADSPI_CR_EN_Pos              (0U)
11624 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
11625 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
11626 #define QUADSPI_CR_ABORT_Pos           (1U)
11627 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
11628 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
11629 #define QUADSPI_CR_DMAEN_Pos           (2U)
11630 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
11631 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
11632 #define QUADSPI_CR_TCEN_Pos            (3U)
11633 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
11634 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
11635 #define QUADSPI_CR_SSHIFT_Pos          (4U)
11636 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
11637 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
11638 #define QUADSPI_CR_DFM_Pos             (6U)
11639 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
11640 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
11641 #define QUADSPI_CR_FSEL_Pos            (7U)
11642 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
11643 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
11644 #define QUADSPI_CR_FTHRES_Pos          (8U)
11645 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
11646 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
11647 #define QUADSPI_CR_TEIE_Pos            (16U)
11648 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
11649 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
11650 #define QUADSPI_CR_TCIE_Pos            (17U)
11651 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
11652 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
11653 #define QUADSPI_CR_FTIE_Pos            (18U)
11654 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
11655 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
11656 #define QUADSPI_CR_SMIE_Pos            (19U)
11657 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
11658 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
11659 #define QUADSPI_CR_TOIE_Pos            (20U)
11660 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
11661 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
11662 #define QUADSPI_CR_APMS_Pos            (22U)
11663 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
11664 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
11665 #define QUADSPI_CR_PMM_Pos             (23U)
11666 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
11667 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
11668 #define QUADSPI_CR_PRESCALER_Pos       (24U)
11669 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
11670 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
11671 
11672 /*****************  Bit definition for QUADSPI_DCR register  ******************/
11673 #define QUADSPI_DCR_CKMODE_Pos         (0U)
11674 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
11675 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
11676 #define QUADSPI_DCR_CSHT_Pos           (8U)
11677 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
11678 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
11679 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
11680 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
11681 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
11682 #define QUADSPI_DCR_FSIZE_Pos          (16U)
11683 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
11684 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
11685 
11686 /******************  Bit definition for QUADSPI_SR register  *******************/
11687 #define QUADSPI_SR_TEF_Pos             (0U)
11688 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
11689 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
11690 #define QUADSPI_SR_TCF_Pos             (1U)
11691 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
11692 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
11693 #define QUADSPI_SR_FTF_Pos             (2U)
11694 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
11695 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
11696 #define QUADSPI_SR_SMF_Pos             (3U)
11697 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
11698 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
11699 #define QUADSPI_SR_TOF_Pos             (4U)
11700 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
11701 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
11702 #define QUADSPI_SR_BUSY_Pos            (5U)
11703 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
11704 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
11705 #define QUADSPI_SR_FLEVEL_Pos          (8U)
11706 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
11707 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
11708 
11709 /******************  Bit definition for QUADSPI_FCR register  ******************/
11710 #define QUADSPI_FCR_CTEF_Pos           (0U)
11711 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
11712 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
11713 #define QUADSPI_FCR_CTCF_Pos           (1U)
11714 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
11715 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
11716 #define QUADSPI_FCR_CSMF_Pos           (3U)
11717 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
11718 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
11719 #define QUADSPI_FCR_CTOF_Pos           (4U)
11720 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
11721 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
11722 
11723 /******************  Bit definition for QUADSPI_DLR register  ******************/
11724 #define QUADSPI_DLR_DL_Pos             (0U)
11725 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
11726 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
11727 
11728 /******************  Bit definition for QUADSPI_CCR register  ******************/
11729 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
11730 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
11731 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
11732 #define QUADSPI_CCR_IMODE_Pos          (8U)
11733 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
11734 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
11735 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
11736 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
11737 #define QUADSPI_CCR_ADMODE_Pos         (10U)
11738 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
11739 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
11740 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
11741 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
11742 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
11743 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
11744 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
11745 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
11746 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
11747 #define QUADSPI_CCR_ABMODE_Pos         (14U)
11748 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
11749 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
11750 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
11751 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
11752 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
11753 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
11754 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
11755 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
11756 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
11757 #define QUADSPI_CCR_DCYC_Pos           (18U)
11758 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
11759 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
11760 #define QUADSPI_CCR_DMODE_Pos          (24U)
11761 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
11762 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
11763 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
11764 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
11765 #define QUADSPI_CCR_FMODE_Pos          (26U)
11766 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
11767 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
11768 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
11769 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
11770 #define QUADSPI_CCR_SIOO_Pos           (28U)
11771 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
11772 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
11773 #define QUADSPI_CCR_DHHC_Pos           (30U)
11774 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
11775 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
11776 #define QUADSPI_CCR_DDRM_Pos           (31U)
11777 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
11778 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
11779 
11780 /******************  Bit definition for QUADSPI_AR register  *******************/
11781 #define QUADSPI_AR_ADDRESS_Pos         (0U)
11782 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
11783 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
11784 
11785 /******************  Bit definition for QUADSPI_ABR register  ******************/
11786 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
11787 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
11788 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
11789 
11790 /******************  Bit definition for QUADSPI_DR register  *******************/
11791 #define QUADSPI_DR_DATA_Pos            (0U)
11792 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
11793 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
11794 
11795 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
11796 #define QUADSPI_PSMKR_MASK_Pos         (0U)
11797 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
11798 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
11799 
11800 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
11801 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
11802 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
11803 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
11804 
11805 /******************  Bit definition for QUADSPI_PIR register  *****************/
11806 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
11807 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
11808 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
11809 
11810 /******************  Bit definition for QUADSPI_LPTR register  *****************/
11811 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
11812 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
11813 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
11814 
11815 /******************************************************************************/
11816 /*                                                                            */
11817 /*                         Reset and Clock Control                            */
11818 /*                                                                            */
11819 /******************************************************************************/
11820 /*
11821 * @brief Specific device feature definitions  (not present on all devices in the STM32G4 series)
11822 */
11823 
11824 #define RCC_HSI48_SUPPORT
11825 #define RCC_PLLP_DIV_2_31_SUPPORT
11826 
11827 /********************  Bit definition for RCC_CR register  ********************/
11828 #define RCC_CR_HSION_Pos                     (8U)
11829 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
11830 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
11831 #define RCC_CR_HSIKERON_Pos                  (9U)
11832 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
11833 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
11834 #define RCC_CR_HSIRDY_Pos                    (10U)
11835 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
11836 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
11837 
11838 #define RCC_CR_HSEON_Pos                     (16U)
11839 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
11840 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
11841 #define RCC_CR_HSERDY_Pos                    (17U)
11842 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
11843 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
11844 #define RCC_CR_HSEBYP_Pos                    (18U)
11845 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
11846 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
11847 #define RCC_CR_CSSON_Pos                     (19U)
11848 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
11849 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
11850 
11851 #define RCC_CR_PLLON_Pos                     (24U)
11852 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
11853 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
11854 #define RCC_CR_PLLRDY_Pos                    (25U)
11855 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
11856 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
11857 
11858 /********************  Bit definition for RCC_ICSCR register  ***************/
11859 /*!< HSICAL configuration */
11860 #define RCC_ICSCR_HSICAL_Pos                 (16U)
11861 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
11862 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
11863 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
11864 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
11865 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
11866 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
11867 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
11868 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
11869 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
11870 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
11871 
11872 /*!< HSITRIM configuration */
11873 #define RCC_ICSCR_HSITRIM_Pos                (24U)
11874 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
11875 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
11876 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
11877 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
11878 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
11879 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
11880 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
11881 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
11882 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
11883 
11884 /********************  Bit definition for RCC_CFGR register  ******************/
11885 /*!< SW configuration */
11886 #define RCC_CFGR_SW_Pos                      (0U)
11887 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
11888 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
11889 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
11890 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
11891 
11892 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
11893 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
11894 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
11895 
11896 /*!< SWS configuration */
11897 #define RCC_CFGR_SWS_Pos                     (2U)
11898 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
11899 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
11900 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
11901 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
11902 
11903 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
11904 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
11905 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
11906 
11907 /*!< HPRE configuration */
11908 #define RCC_CFGR_HPRE_Pos                    (4U)
11909 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
11910 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
11911 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
11912 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
11913 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
11914 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
11915 
11916 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
11917 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
11918 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
11919 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
11920 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
11921 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
11922 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
11923 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
11924 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
11925 
11926 /*!< PPRE1 configuration */
11927 #define RCC_CFGR_PPRE1_Pos                   (8U)
11928 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
11929 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
11930 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
11931 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
11932 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
11933 
11934 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11935 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
11936 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
11937 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
11938 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
11939 
11940 /*!< PPRE2 configuration */
11941 #define RCC_CFGR_PPRE2_Pos                   (11U)
11942 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
11943 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
11944 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
11945 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
11946 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
11947 
11948 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11949 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
11950 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
11951 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
11952 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
11953 
11954 /*!< MCOSEL configuration */
11955 #define RCC_CFGR_MCOSEL_Pos                  (24U)
11956 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
11957 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
11958 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
11959 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
11960 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
11961 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
11962 
11963 #define RCC_CFGR_MCOPRE_Pos                  (28U)
11964 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
11965 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
11966 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
11967 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
11968 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
11969 
11970 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
11971 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
11972 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
11973 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
11974 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
11975 
11976 /* Legacy aliases */
11977 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
11978 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
11979 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
11980 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
11981 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
11982 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
11983 
11984 /********************  Bit definition for RCC_PLLCFGR register  ***************/
11985 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
11986 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
11987 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
11988 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
11989 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
11990 
11991 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
11992 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
11993 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
11994 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
11995 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
11996 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
11997 
11998 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
11999 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
12000 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
12001 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
12002 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
12003 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
12004 #define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
12005 
12006 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
12007 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
12008 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
12009 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
12010 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
12011 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
12012 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
12013 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
12014 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
12015 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
12016 
12017 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
12018 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
12019 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
12020 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
12021 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
12022 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
12023 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
12024 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
12025 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
12026 
12027 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
12028 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
12029 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
12030 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
12031 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
12032 
12033 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
12034 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
12035 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
12036 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
12037 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
12038 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
12039 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
12040 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
12041 
12042 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
12043 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
12044 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
12045 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
12046 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
12047 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
12048 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
12049 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
12050 
12051 /********************  Bit definition for RCC_CIER register  ******************/
12052 #define RCC_CIER_LSIRDYIE_Pos                (0U)
12053 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
12054 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
12055 #define RCC_CIER_LSERDYIE_Pos                (1U)
12056 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
12057 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
12058 #define RCC_CIER_HSIRDYIE_Pos                (3U)
12059 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
12060 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
12061 #define RCC_CIER_HSERDYIE_Pos                (4U)
12062 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
12063 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
12064 #define RCC_CIER_PLLRDYIE_Pos                (5U)
12065 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
12066 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
12067 #define RCC_CIER_LSECSSIE_Pos                (9U)
12068 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
12069 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
12070 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
12071 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
12072 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
12073 
12074 /********************  Bit definition for RCC_CIFR register  ******************/
12075 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
12076 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
12077 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
12078 #define RCC_CIFR_LSERDYF_Pos                 (1U)
12079 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
12080 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
12081 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
12082 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
12083 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
12084 #define RCC_CIFR_HSERDYF_Pos                 (4U)
12085 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
12086 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
12087 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
12088 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
12089 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
12090 #define RCC_CIFR_CSSF_Pos                    (8U)
12091 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
12092 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
12093 #define RCC_CIFR_LSECSSF_Pos                 (9U)
12094 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
12095 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
12096 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
12097 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
12098 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
12099 
12100 /********************  Bit definition for RCC_CICR register  ******************/
12101 #define RCC_CICR_LSIRDYC_Pos                 (0U)
12102 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
12103 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
12104 #define RCC_CICR_LSERDYC_Pos                 (1U)
12105 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
12106 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
12107 #define RCC_CICR_HSIRDYC_Pos                 (3U)
12108 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
12109 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
12110 #define RCC_CICR_HSERDYC_Pos                 (4U)
12111 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
12112 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
12113 #define RCC_CICR_PLLRDYC_Pos                 (5U)
12114 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
12115 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
12116 #define RCC_CICR_CSSC_Pos                    (8U)
12117 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
12118 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
12119 #define RCC_CICR_LSECSSC_Pos                 (9U)
12120 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
12121 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
12122 #define RCC_CICR_HSI48RDYC_Pos               (10U)
12123 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
12124 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
12125 
12126 /********************  Bit definition for RCC_AHB1RSTR register  **************/
12127 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
12128 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
12129 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
12130 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
12131 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
12132 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
12133 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
12134 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
12135 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
12136 #define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
12137 #define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
12138 #define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
12139 #define RCC_AHB1RSTR_FMACRST_Pos             (4U)
12140 #define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
12141 #define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
12142 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
12143 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
12144 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
12145 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
12146 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
12147 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
12148 
12149 /********************  Bit definition for RCC_AHB2RSTR register  **************/
12150 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
12151 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
12152 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
12153 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
12154 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
12155 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
12156 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
12157 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
12158 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
12159 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
12160 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
12161 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
12162 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
12163 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
12164 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
12165 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
12166 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
12167 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
12168 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
12169 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
12170 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
12171 #define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
12172 #define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
12173 #define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
12174 #define RCC_AHB2RSTR_ADC345RST_Pos           (14U)
12175 #define RCC_AHB2RSTR_ADC345RST_Msk           (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
12176 #define RCC_AHB2RSTR_ADC345RST               RCC_AHB2RSTR_ADC345RST_Msk
12177 #define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
12178 #define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
12179 #define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
12180 #define RCC_AHB2RSTR_DAC2RST_Pos             (17U)
12181 #define RCC_AHB2RSTR_DAC2RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
12182 #define RCC_AHB2RSTR_DAC2RST                 RCC_AHB2RSTR_DAC2RST_Msk
12183 #define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
12184 #define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
12185 #define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
12186 #define RCC_AHB2RSTR_DAC4RST_Pos             (19U)
12187 #define RCC_AHB2RSTR_DAC4RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
12188 #define RCC_AHB2RSTR_DAC4RST                 RCC_AHB2RSTR_DAC4RST_Msk
12189 #define RCC_AHB2RSTR_RNGRST_Pos              (26U)
12190 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
12191 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
12192 
12193 /********************  Bit definition for RCC_AHB3RSTR register  **************/
12194 #define RCC_AHB3RSTR_FMCRST_Pos              (0U)
12195 #define RCC_AHB3RSTR_FMCRST_Msk              (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
12196 #define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk
12197 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
12198 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
12199 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
12200 
12201 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
12202 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
12203 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
12204 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
12205 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
12206 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
12207 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
12208 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
12209 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
12210 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
12211 #define RCC_APB1RSTR1_TIM5RST_Pos            (3U)
12212 #define RCC_APB1RSTR1_TIM5RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
12213 #define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk
12214 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
12215 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
12216 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
12217 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
12218 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
12219 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
12220 #define RCC_APB1RSTR1_CRSRST_Pos             (8U)
12221 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
12222 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
12223 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
12224 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
12225 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
12226 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
12227 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
12228 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
12229 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
12230 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
12231 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
12232 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
12233 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
12234 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
12235 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
12236 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
12237 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
12238 #define RCC_APB1RSTR1_UART5RST_Pos           (20U)
12239 #define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
12240 #define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk
12241 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
12242 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
12243 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
12244 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
12245 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
12246 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
12247 #define RCC_APB1RSTR1_USBRST_Pos             (23U)
12248 #define RCC_APB1RSTR1_USBRST_Msk             (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
12249 #define RCC_APB1RSTR1_USBRST                 RCC_APB1RSTR1_USBRST_Msk
12250 #define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
12251 #define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
12252 #define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
12253 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
12254 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
12255 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
12256 #define RCC_APB1RSTR1_I2C3RST_Pos            (30U)
12257 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
12258 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
12259 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
12260 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
12261 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
12262 
12263 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
12264 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
12265 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
12266 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
12267 #define RCC_APB1RSTR2_I2C4RST_Pos            (1U)
12268 #define RCC_APB1RSTR2_I2C4RST_Msk            (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
12269 #define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk
12270 #define RCC_APB1RSTR2_UCPD1RST_Pos           (8U)
12271 #define RCC_APB1RSTR2_UCPD1RST_Msk           (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
12272 #define RCC_APB1RSTR2_UCPD1RST               RCC_APB1RSTR2_UCPD1RST_Msk
12273 
12274 /********************  Bit definition for RCC_APB2RSTR register  **************/
12275 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
12276 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
12277 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
12278 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
12279 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
12280 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
12281 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
12282 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
12283 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
12284 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
12285 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
12286 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
12287 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
12288 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
12289 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
12290 #define RCC_APB2RSTR_SPI4RST_Pos             (15U)
12291 #define RCC_APB2RSTR_SPI4RST_Msk             (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
12292 #define RCC_APB2RSTR_SPI4RST                 RCC_APB2RSTR_SPI4RST_Msk
12293 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
12294 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
12295 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
12296 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
12297 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
12298 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
12299 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
12300 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
12301 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
12302 #define RCC_APB2RSTR_TIM20RST_Pos            (20U)
12303 #define RCC_APB2RSTR_TIM20RST_Msk            (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
12304 #define RCC_APB2RSTR_TIM20RST                RCC_APB2RSTR_TIM20RST_Msk
12305 #define RCC_APB2RSTR_SAI1RST_Pos             (21U)
12306 #define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
12307 #define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
12308 #define RCC_APB2RSTR_HRTIM1RST_Pos           (26U)
12309 #define RCC_APB2RSTR_HRTIM1RST_Msk           (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)/*!< 0x04000000 */
12310 #define RCC_APB2RSTR_HRTIM1RST               RCC_APB2RSTR_HRTIM1RST_Msk
12311 
12312 /********************  Bit definition for RCC_AHB1ENR register  ***************/
12313 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
12314 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
12315 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
12316 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
12317 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
12318 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
12319 #define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
12320 #define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
12321 #define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
12322 #define RCC_AHB1ENR_CORDICEN_Pos             (3U)
12323 #define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
12324 #define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
12325 #define RCC_AHB1ENR_FMACEN_Pos               (4U)
12326 #define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
12327 #define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
12328 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
12329 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
12330 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
12331 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
12332 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
12333 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
12334 
12335 /********************  Bit definition for RCC_AHB2ENR register  ***************/
12336 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
12337 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
12338 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
12339 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
12340 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
12341 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
12342 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
12343 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
12344 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
12345 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
12346 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
12347 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
12348 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
12349 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
12350 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
12351 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
12352 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
12353 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
12354 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
12355 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
12356 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
12357 #define RCC_AHB2ENR_ADC12EN_Pos              (13U)
12358 #define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
12359 #define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
12360 #define RCC_AHB2ENR_ADC345EN_Pos             (14U)
12361 #define RCC_AHB2ENR_ADC345EN_Msk             (0x1UL << RCC_AHB2ENR_ADC345EN_Pos)  /*!< 0x00004000 */
12362 #define RCC_AHB2ENR_ADC345EN                 RCC_AHB2ENR_ADC345EN_Msk
12363 #define RCC_AHB2ENR_DAC1EN_Pos               (16U)
12364 #define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
12365 #define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
12366 #define RCC_AHB2ENR_DAC2EN_Pos               (17U)
12367 #define RCC_AHB2ENR_DAC2EN_Msk               (0x1UL << RCC_AHB2ENR_DAC2EN_Pos)  /*!< 0x00020000 */
12368 #define RCC_AHB2ENR_DAC2EN                   RCC_AHB2ENR_DAC2EN_Msk
12369 #define RCC_AHB2ENR_DAC3EN_Pos               (18U)
12370 #define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
12371 #define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
12372 #define RCC_AHB2ENR_DAC4EN_Pos               (19U)
12373 #define RCC_AHB2ENR_DAC4EN_Msk               (0x1UL << RCC_AHB2ENR_DAC4EN_Pos)  /*!< 0x00080000 */
12374 #define RCC_AHB2ENR_DAC4EN                   RCC_AHB2ENR_DAC4EN_Msk
12375 #define RCC_AHB2ENR_RNGEN_Pos                (26U)
12376 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
12377 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
12378 
12379 /********************  Bit definition for RCC_AHB3ENR register  ***************/
12380 #define RCC_AHB3ENR_FMCEN_Pos                (0U)
12381 #define RCC_AHB3ENR_FMCEN_Msk                (0x1UL << RCC_AHB3ENR_FMCEN_Pos)  /*!< 0x00000001 */
12382 #define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk
12383 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
12384 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
12385 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
12386 
12387 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
12388 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
12389 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
12390 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
12391 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
12392 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
12393 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
12394 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
12395 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
12396 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
12397 #define RCC_APB1ENR1_TIM5EN_Pos              (3U)
12398 #define RCC_APB1ENR1_TIM5EN_Msk              (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
12399 #define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk
12400 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
12401 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
12402 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
12403 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
12404 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
12405 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
12406 #define RCC_APB1ENR1_CRSEN_Pos               (8U)
12407 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
12408 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
12409 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
12410 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
12411 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
12412 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
12413 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
12414 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
12415 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
12416 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
12417 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
12418 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
12419 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
12420 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
12421 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
12422 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
12423 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
12424 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
12425 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
12426 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
12427 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
12428 #define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
12429 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
12430 #define RCC_APB1ENR1_UART5EN_Pos             (20U)
12431 #define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
12432 #define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk
12433 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
12434 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
12435 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
12436 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
12437 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
12438 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
12439 #define RCC_APB1ENR1_USBEN_Pos               (23U)
12440 #define RCC_APB1ENR1_USBEN_Msk               (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
12441 #define RCC_APB1ENR1_USBEN                   RCC_APB1ENR1_USBEN_Msk
12442 #define RCC_APB1ENR1_FDCANEN_Pos             (25U)
12443 #define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
12444 #define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
12445 #define RCC_APB1ENR1_PWREN_Pos               (28U)
12446 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
12447 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
12448 #define RCC_APB1ENR1_I2C3EN_Pos              (30U)
12449 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
12450 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
12451 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
12452 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
12453 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
12454 
12455 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
12456 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
12457 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
12458 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
12459 #define RCC_APB1ENR2_I2C4EN_Pos              (1U)
12460 #define RCC_APB1ENR2_I2C4EN_Msk              (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
12461 #define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk
12462 #define RCC_APB1ENR2_UCPD1EN_Pos             (8U)
12463 #define RCC_APB1ENR2_UCPD1EN_Msk             (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
12464 #define RCC_APB1ENR2_UCPD1EN                 RCC_APB1ENR2_UCPD1EN_Msk
12465 
12466 /********************  Bit definition for RCC_APB2ENR register  ***************/
12467 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
12468 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
12469 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
12470 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
12471 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
12472 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
12473 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
12474 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
12475 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
12476 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
12477 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
12478 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
12479 #define RCC_APB2ENR_USART1EN_Pos             (14U)
12480 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
12481 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
12482 #define RCC_APB2ENR_SPI4EN_Pos               (15U)
12483 #define RCC_APB2ENR_SPI4EN_Msk               (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
12484 #define RCC_APB2ENR_SPI4EN                   RCC_APB2ENR_SPI4EN_Msk
12485 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
12486 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
12487 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
12488 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
12489 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
12490 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
12491 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
12492 #define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
12493 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
12494 #define RCC_APB2ENR_TIM20EN_Pos              (20U)
12495 #define RCC_APB2ENR_TIM20EN_Msk              (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
12496 #define RCC_APB2ENR_TIM20EN                  RCC_APB2ENR_TIM20EN_Msk
12497 #define RCC_APB2ENR_SAI1EN_Pos               (21U)
12498 #define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
12499 #define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
12500 #define RCC_APB2ENR_HRTIM1EN_Pos              (26U)
12501 #define RCC_APB2ENR_HRTIM1EN_Msk              (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)/*!< 0x04000000 */
12502 #define RCC_APB2ENR_HRTIM1EN                  RCC_APB2ENR_HRTIM1EN_Msk
12503 
12504 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
12505 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
12506 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
12507 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
12508 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
12509 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
12510 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
12511 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
12512 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
12513 #define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
12514 #define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
12515 #define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
12516 #define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
12517 #define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
12518 #define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
12519 #define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
12520 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
12521 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
12522 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
12523 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
12524 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
12525 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
12526 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
12527 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
12528 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
12529 
12530 /********************  Bit definition for RCC_AHB2SMENR register  *************/
12531 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
12532 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
12533 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
12534 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
12535 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
12536 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
12537 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
12538 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
12539 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
12540 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
12541 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
12542 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
12543 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
12544 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
12545 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
12546 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
12547 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
12548 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
12549 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
12550 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
12551 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
12552 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
12553 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
12554 #define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
12555 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (10U)
12556 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
12557 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
12558 #define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
12559 #define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
12560 #define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
12561 #define RCC_AHB2SMENR_ADC345SMEN_Pos         (14U)
12562 #define RCC_AHB2SMENR_ADC345SMEN_Msk         (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
12563 #define RCC_AHB2SMENR_ADC345SMEN             RCC_AHB2SMENR_ADC345SMEN_Msk
12564 #define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
12565 #define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
12566 #define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
12567 #define RCC_AHB2SMENR_DAC2SMEN_Pos           (17U)
12568 #define RCC_AHB2SMENR_DAC2SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
12569 #define RCC_AHB2SMENR_DAC2SMEN               RCC_AHB2SMENR_DAC2SMEN_Msk
12570 #define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
12571 #define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
12572 #define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
12573 #define RCC_AHB2SMENR_DAC4SMEN_Pos           (19U)
12574 #define RCC_AHB2SMENR_DAC4SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
12575 #define RCC_AHB2SMENR_DAC4SMEN               RCC_AHB2SMENR_DAC4SMEN_Msk
12576 #define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
12577 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
12578 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
12579 
12580 /********************  Bit definition for RCC_AHB3SMENR register  *************/
12581 #define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)
12582 #define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
12583 #define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk
12584 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
12585 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
12586 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
12587 
12588 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
12589 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
12590 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
12591 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
12592 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
12593 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
12594 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
12595 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
12596 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
12597 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
12598 #define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)
12599 #define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
12600 #define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk
12601 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
12602 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
12603 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
12604 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
12605 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
12606 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
12607 #define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
12608 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
12609 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
12610 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
12611 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
12612 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
12613 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
12614 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
12615 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
12616 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
12617 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
12618 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
12619 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
12620 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
12621 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
12622 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
12623 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
12624 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
12625 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
12626 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
12627 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
12628 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
12629 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
12630 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
12631 #define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)
12632 #define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
12633 #define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk
12634 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
12635 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
12636 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
12637 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
12638 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
12639 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
12640 #define RCC_APB1SMENR1_USBSMEN_Pos           (23U)
12641 #define RCC_APB1SMENR1_USBSMEN_Msk           (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
12642 #define RCC_APB1SMENR1_USBSMEN               RCC_APB1SMENR1_USBSMEN_Msk
12643 #define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
12644 #define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
12645 #define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
12646 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
12647 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
12648 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
12649 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (30U)
12650 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
12651 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
12652 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
12653 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
12654 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
12655 
12656 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
12657 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
12658 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
12659 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
12660 #define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)
12661 #define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
12662 #define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk
12663 #define RCC_APB1SMENR2_UCPD1SMEN_Pos         (8U)
12664 #define RCC_APB1SMENR2_UCPD1SMEN_Msk         (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
12665 #define RCC_APB1SMENR2_UCPD1SMEN             RCC_APB1SMENR2_UCPD1SMEN_Msk
12666 
12667 /********************  Bit definition for RCC_APB2SMENR register  *************/
12668 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
12669 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
12670 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
12671 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
12672 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
12673 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
12674 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
12675 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
12676 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
12677 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
12678 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
12679 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
12680 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
12681 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
12682 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
12683 #define RCC_APB2SMENR_SPI4SMEN_Pos           (15U)
12684 #define RCC_APB2SMENR_SPI4SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
12685 #define RCC_APB2SMENR_SPI4SMEN               RCC_APB2SMENR_SPI4SMEN_Msk
12686 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
12687 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
12688 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
12689 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
12690 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
12691 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
12692 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
12693 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
12694 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
12695 #define RCC_APB2SMENR_TIM20SMEN_Pos          (20U)
12696 #define RCC_APB2SMENR_TIM20SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
12697 #define RCC_APB2SMENR_TIM20SMEN              RCC_APB2SMENR_TIM20SMEN_Msk
12698 #define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
12699 #define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
12700 #define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
12701 #define RCC_APB2SMENR_HRTIM1SMEN_Pos          (26U)
12702 #define RCC_APB2SMENR_HRTIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_HRTIM1SMEN_Pos)/*!< 0x04000000 */
12703 #define RCC_APB2SMENR_HRTIM1SMEN              RCC_APB2SMENR_HRTIM1SMEN_Msk
12704 
12705 /********************  Bit definition for RCC_CCIPR register  ******************/
12706 #define RCC_CCIPR_USART1SEL_Pos              (0U)
12707 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
12708 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
12709 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
12710 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
12711 
12712 #define RCC_CCIPR_USART2SEL_Pos              (2U)
12713 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
12714 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
12715 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
12716 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
12717 
12718 #define RCC_CCIPR_USART3SEL_Pos              (4U)
12719 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
12720 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
12721 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
12722 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
12723 
12724 #define RCC_CCIPR_UART4SEL_Pos               (6U)
12725 #define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
12726 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
12727 #define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
12728 #define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
12729 
12730 #define RCC_CCIPR_UART5SEL_Pos               (8U)
12731 #define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
12732 #define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk
12733 #define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
12734 #define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
12735 
12736 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
12737 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
12738 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
12739 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
12740 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
12741 
12742 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
12743 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
12744 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
12745 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
12746 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
12747 
12748 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
12749 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
12750 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
12751 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
12752 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
12753 
12754 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
12755 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
12756 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
12757 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
12758 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
12759 
12760 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
12761 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
12762 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
12763 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
12764 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
12765 
12766 #define RCC_CCIPR_SAI1SEL_Pos                (20U)
12767 #define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
12768 #define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
12769 #define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
12770 #define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
12771 
12772 #define RCC_CCIPR_I2S23SEL_Pos               (22U)
12773 #define RCC_CCIPR_I2S23SEL_Msk               (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
12774 #define RCC_CCIPR_I2S23SEL                   RCC_CCIPR_I2S23SEL_Msk
12775 #define RCC_CCIPR_I2S23SEL_0                 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
12776 #define RCC_CCIPR_I2S23SEL_1                 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
12777 
12778 #define RCC_CCIPR_FDCANSEL_Pos               (24U)
12779 #define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
12780 #define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
12781 #define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
12782 #define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
12783 
12784 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
12785 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
12786 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
12787 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
12788 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
12789 
12790 #define RCC_CCIPR_ADC12SEL_Pos               (28U)
12791 #define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
12792 #define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
12793 #define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
12794 #define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
12795 
12796 #define RCC_CCIPR_ADC345SEL_Pos              (30U)
12797 #define RCC_CCIPR_ADC345SEL_Msk              (0x3UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
12798 #define RCC_CCIPR_ADC345SEL                  RCC_CCIPR_ADC345SEL_Msk
12799 #define RCC_CCIPR_ADC345SEL_0                (0x1UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x40000000 */
12800 #define RCC_CCIPR_ADC345SEL_1                (0x2UL << RCC_CCIPR_ADC345SEL_Pos)   /*!< 0x80000000 */
12801 
12802 /********************  Bit definition for RCC_BDCR register  ******************/
12803 #define RCC_BDCR_LSEON_Pos                   (0U)
12804 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
12805 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
12806 #define RCC_BDCR_LSERDY_Pos                  (1U)
12807 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
12808 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
12809 #define RCC_BDCR_LSEBYP_Pos                  (2U)
12810 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
12811 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
12812 
12813 #define RCC_BDCR_LSEDRV_Pos                  (3U)
12814 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
12815 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
12816 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
12817 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
12818 
12819 #define RCC_BDCR_LSECSSON_Pos                (5U)
12820 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
12821 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
12822 #define RCC_BDCR_LSECSSD_Pos                 (6U)
12823 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
12824 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
12825 
12826 #define RCC_BDCR_RTCSEL_Pos                  (8U)
12827 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
12828 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
12829 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
12830 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
12831 
12832 #define RCC_BDCR_RTCEN_Pos                   (15U)
12833 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
12834 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
12835 #define RCC_BDCR_BDRST_Pos                   (16U)
12836 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
12837 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
12838 #define RCC_BDCR_LSCOEN_Pos                  (24U)
12839 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
12840 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
12841 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
12842 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
12843 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
12844 
12845 /********************  Bit definition for RCC_CSR register  *******************/
12846 #define RCC_CSR_LSION_Pos                    (0U)
12847 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
12848 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
12849 #define RCC_CSR_LSIRDY_Pos                   (1U)
12850 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
12851 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
12852 
12853 #define RCC_CSR_RMVF_Pos                     (23U)
12854 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
12855 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
12856 #define RCC_CSR_OBLRSTF_Pos                  (25U)
12857 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
12858 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
12859 #define RCC_CSR_PINRSTF_Pos                  (26U)
12860 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
12861 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
12862 #define RCC_CSR_BORRSTF_Pos                  (27U)
12863 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
12864 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
12865 #define RCC_CSR_SFTRSTF_Pos                  (28U)
12866 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
12867 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
12868 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
12869 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
12870 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
12871 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
12872 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
12873 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
12874 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
12875 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
12876 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
12877 
12878 /********************  Bit definition for RCC_CRRCR register  *****************/
12879 #define RCC_CRRCR_HSI48ON_Pos                (0U)
12880 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
12881 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
12882 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
12883 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
12884 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
12885 
12886 /*!< HSI48CAL configuration */
12887 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
12888 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
12889 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
12890 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
12891 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
12892 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
12893 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
12894 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
12895 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
12896 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
12897 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
12898 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
12899 
12900 /********************  Bit definition for RCC_CCIPR2 register  ******************/
12901 #define RCC_CCIPR2_I2C4SEL_Pos               (0U)
12902 #define RCC_CCIPR2_I2C4SEL_Msk               (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
12903 #define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk
12904 #define RCC_CCIPR2_I2C4SEL_0                 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
12905 #define RCC_CCIPR2_I2C4SEL_1                 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
12906 
12907 #define RCC_CCIPR2_QSPISEL_Pos               (20U)
12908 #define RCC_CCIPR2_QSPISEL_Msk               (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
12909 #define RCC_CCIPR2_QSPISEL                   RCC_CCIPR2_QSPISEL_Msk
12910 #define RCC_CCIPR2_QSPISEL_0                 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
12911 #define RCC_CCIPR2_QSPISEL_1                 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
12912 
12913 /******************************************************************************/
12914 /*                                                                            */
12915 /*                                    RNG                                     */
12916 /*                                                                            */
12917 /******************************************************************************/
12918 /********************  Bits definition for RNG_CR register  *******************/
12919 #define RNG_CR_RNGEN_Pos    (2U)
12920 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
12921 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
12922 #define RNG_CR_IE_Pos       (3U)
12923 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
12924 #define RNG_CR_IE           RNG_CR_IE_Msk
12925 #define RNG_CR_CED_Pos      (5U)
12926 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
12927 #define RNG_CR_CED          RNG_CR_IE_Msk
12928 
12929 /********************  Bits definition for RNG_SR register  *******************/
12930 #define RNG_SR_DRDY_Pos     (0U)
12931 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
12932 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
12933 #define RNG_SR_CECS_Pos     (1U)
12934 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
12935 #define RNG_SR_CECS         RNG_SR_CECS_Msk
12936 #define RNG_SR_SECS_Pos     (2U)
12937 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
12938 #define RNG_SR_SECS         RNG_SR_SECS_Msk
12939 #define RNG_SR_CEIS_Pos     (5U)
12940 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
12941 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
12942 #define RNG_SR_SEIS_Pos     (6U)
12943 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
12944 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
12945 
12946 /******************************************************************************/
12947 /*                                                                            */
12948 /*                           Real-Time Clock (RTC)                            */
12949 /*                                                                            */
12950 /******************************************************************************/
12951 
12952 /********************  Bits definition for RTC_TR register  *******************/
12953 #define RTC_TR_PM_Pos                (22U)
12954 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
12955 #define RTC_TR_PM                    RTC_TR_PM_Msk
12956 #define RTC_TR_HT_Pos                (20U)
12957 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
12958 #define RTC_TR_HT                    RTC_TR_HT_Msk
12959 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
12960 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
12961 #define RTC_TR_HU_Pos                (16U)
12962 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
12963 #define RTC_TR_HU                    RTC_TR_HU_Msk
12964 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
12965 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
12966 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
12967 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
12968 #define RTC_TR_MNT_Pos               (12U)
12969 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
12970 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
12971 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
12972 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
12973 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
12974 #define RTC_TR_MNU_Pos               (8U)
12975 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
12976 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
12977 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
12978 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
12979 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
12980 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
12981 #define RTC_TR_ST_Pos                (4U)
12982 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
12983 #define RTC_TR_ST                    RTC_TR_ST_Msk
12984 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
12985 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
12986 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
12987 #define RTC_TR_SU_Pos                (0U)
12988 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
12989 #define RTC_TR_SU                    RTC_TR_SU_Msk
12990 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
12991 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
12992 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
12993 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
12994 
12995 /********************  Bits definition for RTC_DR register  *******************/
12996 #define RTC_DR_YT_Pos                (20U)
12997 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
12998 #define RTC_DR_YT                    RTC_DR_YT_Msk
12999 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
13000 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
13001 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
13002 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
13003 #define RTC_DR_YU_Pos                (16U)
13004 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
13005 #define RTC_DR_YU                    RTC_DR_YU_Msk
13006 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
13007 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
13008 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
13009 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
13010 #define RTC_DR_WDU_Pos               (13U)
13011 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
13012 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
13013 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
13014 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
13015 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
13016 #define RTC_DR_MT_Pos                (12U)
13017 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
13018 #define RTC_DR_MT                    RTC_DR_MT_Msk
13019 #define RTC_DR_MU_Pos                (8U)
13020 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
13021 #define RTC_DR_MU                    RTC_DR_MU_Msk
13022 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
13023 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
13024 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
13025 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
13026 #define RTC_DR_DT_Pos                (4U)
13027 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
13028 #define RTC_DR_DT                    RTC_DR_DT_Msk
13029 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
13030 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
13031 #define RTC_DR_DU_Pos                (0U)
13032 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
13033 #define RTC_DR_DU                    RTC_DR_DU_Msk
13034 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
13035 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
13036 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
13037 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
13038 
13039 /********************  Bits definition for RTC_SSR register  ******************/
13040 #define RTC_SSR_SS_Pos               (0U)
13041 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
13042 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
13043 
13044 /********************  Bits definition for RTC_ICSR register  ******************/
13045 #define RTC_ICSR_RECALPF_Pos         (16U)
13046 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
13047 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
13048 #define RTC_ICSR_INIT_Pos            (7U)
13049 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
13050 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
13051 #define RTC_ICSR_INITF_Pos           (6U)
13052 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
13053 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
13054 #define RTC_ICSR_RSF_Pos             (5U)
13055 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
13056 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
13057 #define RTC_ICSR_INITS_Pos           (4U)
13058 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
13059 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
13060 #define RTC_ICSR_SHPF_Pos            (3U)
13061 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
13062 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
13063 #define RTC_ICSR_WUTWF_Pos           (2U)
13064 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
13065 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
13066 #define RTC_ICSR_ALRBWF_Pos          (1U)
13067 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
13068 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
13069 #define RTC_ICSR_ALRAWF_Pos          (0U)
13070 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
13071 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
13072 
13073 /********************  Bits definition for RTC_PRER register  *****************/
13074 #define RTC_PRER_PREDIV_A_Pos        (16U)
13075 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
13076 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
13077 #define RTC_PRER_PREDIV_S_Pos        (0U)
13078 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
13079 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
13080 
13081 /********************  Bits definition for RTC_WUTR register  *****************/
13082 #define RTC_WUTR_WUT_Pos             (0U)
13083 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
13084 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
13085 
13086 /********************  Bits definition for RTC_CR register  *******************/
13087 #define RTC_CR_OUT2EN_Pos            (31U)
13088 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
13089 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
13090 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
13091 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
13092 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
13093 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
13094 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
13095 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
13096 #define RTC_CR_TAMPOE_Pos            (26U)
13097 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
13098 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
13099 #define RTC_CR_TAMPTS_Pos            (25U)
13100 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
13101 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
13102 #define RTC_CR_ITSE_Pos              (24U)
13103 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
13104 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
13105 #define RTC_CR_COE_Pos               (23U)
13106 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
13107 #define RTC_CR_COE                   RTC_CR_COE_Msk
13108 #define RTC_CR_OSEL_Pos              (21U)
13109 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
13110 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
13111 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
13112 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
13113 #define RTC_CR_POL_Pos               (20U)
13114 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
13115 #define RTC_CR_POL                   RTC_CR_POL_Msk
13116 #define RTC_CR_COSEL_Pos             (19U)
13117 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
13118 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
13119 #define RTC_CR_BKP_Pos               (18U)
13120 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
13121 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
13122 #define RTC_CR_SUB1H_Pos             (17U)
13123 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
13124 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
13125 #define RTC_CR_ADD1H_Pos             (16U)
13126 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
13127 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
13128 #define RTC_CR_TSIE_Pos              (15U)
13129 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
13130 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
13131 #define RTC_CR_WUTIE_Pos             (14U)
13132 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
13133 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
13134 #define RTC_CR_ALRBIE_Pos            (13U)
13135 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
13136 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
13137 #define RTC_CR_ALRAIE_Pos            (12U)
13138 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
13139 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
13140 #define RTC_CR_TSE_Pos               (11U)
13141 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
13142 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
13143 #define RTC_CR_WUTE_Pos              (10U)
13144 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
13145 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
13146 #define RTC_CR_ALRBE_Pos             (9U)
13147 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
13148 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
13149 #define RTC_CR_ALRAE_Pos             (8U)
13150 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
13151 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
13152 #define RTC_CR_FMT_Pos               (6U)
13153 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
13154 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
13155 #define RTC_CR_BYPSHAD_Pos           (5U)
13156 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
13157 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
13158 #define RTC_CR_REFCKON_Pos           (4U)
13159 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
13160 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
13161 #define RTC_CR_TSEDGE_Pos            (3U)
13162 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
13163 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
13164 #define RTC_CR_WUCKSEL_Pos           (0U)
13165 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
13166 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
13167 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
13168 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
13169 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
13170 
13171 /********************  Bits definition for RTC_WPR register  ******************/
13172 #define RTC_WPR_KEY_Pos              (0U)
13173 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
13174 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
13175 
13176 /********************  Bits definition for RTC_CALR register  *****************/
13177 #define RTC_CALR_CALP_Pos            (15U)
13178 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
13179 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
13180 #define RTC_CALR_CALW8_Pos           (14U)
13181 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
13182 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
13183 #define RTC_CALR_CALW16_Pos          (13U)
13184 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
13185 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
13186 #define RTC_CALR_CALM_Pos            (0U)
13187 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
13188 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
13189 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
13190 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
13191 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
13192 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
13193 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
13194 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
13195 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
13196 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
13197 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
13198 
13199 /********************  Bits definition for RTC_SHIFTR register  ***************/
13200 #define RTC_SHIFTR_SUBFS_Pos         (0U)
13201 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
13202 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
13203 #define RTC_SHIFTR_ADD1S_Pos         (31U)
13204 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
13205 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
13206 
13207 /********************  Bits definition for RTC_TSTR register  *****************/
13208 #define RTC_TSTR_PM_Pos              (22U)
13209 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
13210 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
13211 #define RTC_TSTR_HT_Pos              (20U)
13212 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
13213 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
13214 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
13215 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
13216 #define RTC_TSTR_HU_Pos              (16U)
13217 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
13218 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
13219 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
13220 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
13221 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
13222 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
13223 #define RTC_TSTR_MNT_Pos             (12U)
13224 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
13225 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
13226 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
13227 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
13228 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
13229 #define RTC_TSTR_MNU_Pos             (8U)
13230 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
13231 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
13232 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
13233 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
13234 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
13235 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
13236 #define RTC_TSTR_ST_Pos              (4U)
13237 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
13238 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
13239 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
13240 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
13241 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
13242 #define RTC_TSTR_SU_Pos              (0U)
13243 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
13244 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
13245 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
13246 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
13247 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
13248 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
13249 
13250 /********************  Bits definition for RTC_TSDR register  *****************/
13251 #define RTC_TSDR_WDU_Pos             (13U)
13252 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
13253 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
13254 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
13255 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
13256 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
13257 #define RTC_TSDR_MT_Pos              (12U)
13258 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
13259 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
13260 #define RTC_TSDR_MU_Pos              (8U)
13261 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
13262 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
13263 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
13264 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
13265 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
13266 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
13267 #define RTC_TSDR_DT_Pos              (4U)
13268 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
13269 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
13270 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
13271 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
13272 #define RTC_TSDR_DU_Pos              (0U)
13273 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
13274 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
13275 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
13276 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
13277 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
13278 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
13279 
13280 /********************  Bits definition for RTC_TSSSR register  ****************/
13281 #define RTC_TSSSR_SS_Pos             (0U)
13282 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
13283 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
13284 
13285 /********************  Bits definition for RTC_ALRMAR register  ***************/
13286 #define RTC_ALRMAR_MSK4_Pos          (31U)
13287 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
13288 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
13289 #define RTC_ALRMAR_WDSEL_Pos         (30U)
13290 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
13291 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
13292 #define RTC_ALRMAR_DT_Pos            (28U)
13293 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
13294 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
13295 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
13296 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
13297 #define RTC_ALRMAR_DU_Pos            (24U)
13298 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
13299 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
13300 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
13301 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
13302 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
13303 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
13304 #define RTC_ALRMAR_MSK3_Pos          (23U)
13305 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
13306 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
13307 #define RTC_ALRMAR_PM_Pos            (22U)
13308 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
13309 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
13310 #define RTC_ALRMAR_HT_Pos            (20U)
13311 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
13312 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
13313 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
13314 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
13315 #define RTC_ALRMAR_HU_Pos            (16U)
13316 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
13317 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
13318 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
13319 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
13320 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
13321 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
13322 #define RTC_ALRMAR_MSK2_Pos          (15U)
13323 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
13324 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
13325 #define RTC_ALRMAR_MNT_Pos           (12U)
13326 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
13327 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
13328 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
13329 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
13330 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
13331 #define RTC_ALRMAR_MNU_Pos           (8U)
13332 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
13333 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
13334 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
13335 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
13336 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
13337 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
13338 #define RTC_ALRMAR_MSK1_Pos          (7U)
13339 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
13340 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
13341 #define RTC_ALRMAR_ST_Pos            (4U)
13342 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
13343 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
13344 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
13345 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
13346 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
13347 #define RTC_ALRMAR_SU_Pos            (0U)
13348 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
13349 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
13350 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
13351 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
13352 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
13353 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
13354 
13355 /********************  Bits definition for RTC_ALRMASSR register  *************/
13356 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
13357 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
13358 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
13359 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
13360 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
13361 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
13362 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
13363 #define RTC_ALRMASSR_SS_Pos          (0U)
13364 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
13365 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
13366 
13367 /********************  Bits definition for RTC_ALRMBR register  ***************/
13368 #define RTC_ALRMBR_MSK4_Pos          (31U)
13369 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
13370 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
13371 #define RTC_ALRMBR_WDSEL_Pos         (30U)
13372 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
13373 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
13374 #define RTC_ALRMBR_DT_Pos            (28U)
13375 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
13376 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
13377 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
13378 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
13379 #define RTC_ALRMBR_DU_Pos            (24U)
13380 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
13381 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
13382 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
13383 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
13384 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
13385 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
13386 #define RTC_ALRMBR_MSK3_Pos          (23U)
13387 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
13388 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
13389 #define RTC_ALRMBR_PM_Pos            (22U)
13390 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
13391 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
13392 #define RTC_ALRMBR_HT_Pos            (20U)
13393 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
13394 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
13395 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
13396 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
13397 #define RTC_ALRMBR_HU_Pos            (16U)
13398 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
13399 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
13400 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
13401 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
13402 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
13403 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
13404 #define RTC_ALRMBR_MSK2_Pos          (15U)
13405 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
13406 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
13407 #define RTC_ALRMBR_MNT_Pos           (12U)
13408 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
13409 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
13410 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
13411 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
13412 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
13413 #define RTC_ALRMBR_MNU_Pos           (8U)
13414 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
13415 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
13416 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
13417 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
13418 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
13419 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
13420 #define RTC_ALRMBR_MSK1_Pos          (7U)
13421 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
13422 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
13423 #define RTC_ALRMBR_ST_Pos            (4U)
13424 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
13425 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
13426 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
13427 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
13428 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
13429 #define RTC_ALRMBR_SU_Pos            (0U)
13430 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
13431 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
13432 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
13433 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
13434 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
13435 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
13436 
13437 /********************  Bits definition for RTC_ALRMASSR register  *************/
13438 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
13439 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
13440 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
13441 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
13442 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
13443 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
13444 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
13445 #define RTC_ALRMBSSR_SS_Pos          (0U)
13446 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
13447 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
13448 
13449 /********************  Bits definition for RTC_SR register  *******************/
13450 #define RTC_SR_ITSF_Pos              (5U)
13451 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
13452 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
13453 #define RTC_SR_TSOVF_Pos             (4U)
13454 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
13455 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
13456 #define RTC_SR_TSF_Pos               (3U)
13457 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
13458 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
13459 #define RTC_SR_WUTF_Pos              (2U)
13460 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
13461 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
13462 #define RTC_SR_ALRBF_Pos             (1U)
13463 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
13464 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
13465 #define RTC_SR_ALRAF_Pos             (0U)
13466 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
13467 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
13468 
13469 /********************  Bits definition for RTC_MISR register  *****************/
13470 #define RTC_MISR_ITSMF_Pos           (5U)
13471 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
13472 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
13473 #define RTC_MISR_TSOVMF_Pos          (4U)
13474 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
13475 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
13476 #define RTC_MISR_TSMF_Pos            (3U)
13477 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
13478 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
13479 #define RTC_MISR_WUTMF_Pos           (2U)
13480 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
13481 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
13482 #define RTC_MISR_ALRBMF_Pos          (1U)
13483 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
13484 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
13485 #define RTC_MISR_ALRAMF_Pos          (0U)
13486 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
13487 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
13488 
13489 /********************  Bits definition for RTC_SCR register  ******************/
13490 #define RTC_SCR_CITSF_Pos            (5U)
13491 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
13492 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
13493 #define RTC_SCR_CTSOVF_Pos           (4U)
13494 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
13495 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
13496 #define RTC_SCR_CTSF_Pos             (3U)
13497 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
13498 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
13499 #define RTC_SCR_CWUTF_Pos            (2U)
13500 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
13501 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
13502 #define RTC_SCR_CALRBF_Pos           (1U)
13503 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
13504 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
13505 #define RTC_SCR_CALRAF_Pos           (0U)
13506 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
13507 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
13508 
13509 /******************************************************************************/
13510 /*                                                                            */
13511 /*                     Tamper and backup register (TAMP)                      */
13512 /*                                                                            */
13513 /******************************************************************************/
13514 /********************  Bits definition for TAMP_CR1 register  *****************/
13515 #define TAMP_CR1_TAMP1E_Pos          (0U)
13516 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
13517 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
13518 #define TAMP_CR1_TAMP2E_Pos          (1U)
13519 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
13520 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
13521 #define TAMP_CR1_TAMP3E_Pos          (2U)
13522 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
13523 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
13524 #define TAMP_CR1_ITAMP3E_Pos         (18U)
13525 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
13526 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
13527 #define TAMP_CR1_ITAMP4E_Pos         (19U)
13528 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
13529 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
13530 #define TAMP_CR1_ITAMP5E_Pos         (20U)
13531 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
13532 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
13533 #define TAMP_CR1_ITAMP6E_Pos         (21U)
13534 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
13535 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
13536 
13537 /********************  Bits definition for TAMP_CR2 register  *****************/
13538 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
13539 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
13540 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
13541 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
13542 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
13543 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
13544 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
13545 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
13546 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
13547 #define TAMP_CR2_TAMP1MSK_Pos         (16U)
13548 #define TAMP_CR2_TAMP1MSK_Msk         (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
13549 #define TAMP_CR2_TAMP1MSK             TAMP_CR2_TAMP1MSK_Msk
13550 #define TAMP_CR2_TAMP2MSK_Pos         (17U)
13551 #define TAMP_CR2_TAMP2MSK_Msk         (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
13552 #define TAMP_CR2_TAMP2MSK             TAMP_CR2_TAMP2MSK_Msk
13553 #define TAMP_CR2_TAMP3MSK_Pos         (18U)
13554 #define TAMP_CR2_TAMP3MSK_Msk         (0x1UL << TAMP_CR2_TAMP3MSK_Pos)           /*!< 0x00040000 */
13555 #define TAMP_CR2_TAMP3MSK             TAMP_CR2_TAMP3MSK_Msk
13556 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
13557 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
13558 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
13559 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
13560 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
13561 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
13562 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
13563 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
13564 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
13565 
13566 /* Legacy aliases */
13567 #define TAMP_CR2_TAMP1MF_Pos            TAMP_CR2_TAMP1MSK_Pos
13568 #define TAMP_CR2_TAMP1MF_Msk            TAMP_CR2_TAMP1MSK_Msk
13569 #define TAMP_CR2_TAMP1MF                TAMP_CR2_TAMP1MSK
13570 #define TAMP_CR2_TAMP2MF_Pos            TAMP_CR2_TAMP2MSK_Pos
13571 #define TAMP_CR2_TAMP2MF_Msk            TAMP_CR2_TAMP2MSK_Msk
13572 #define TAMP_CR2_TAMP2MF                TAMP_CR2_TAMP2MSK
13573 #define TAMP_CR2_TAMP3MF_Pos            TAMP_CR2_TAMP3MSK_Pos
13574 #define TAMP_CR2_TAMP3MF_Msk            TAMP_CR2_TAMP3MSK_Msk
13575 #define TAMP_CR2_TAMP3MF                TAMP_CR2_TAMP3MSK
13576 
13577 /********************  Bits definition for TAMP_FLTCR register  ***************/
13578 #define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
13579 #define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
13580 #define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
13581 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
13582 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
13583 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
13584 #define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
13585 #define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
13586 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
13587 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
13588 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
13589 #define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
13590 #define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
13591 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
13592 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
13593 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
13594 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
13595 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
13596 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
13597 
13598 /********************  Bits definition for TAMP_IER register  *****************/
13599 #define TAMP_IER_TAMP1IE_Pos         (0U)
13600 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
13601 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
13602 #define TAMP_IER_TAMP2IE_Pos         (1U)
13603 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
13604 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
13605 #define TAMP_IER_TAMP3IE_Pos         (2U)
13606 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
13607 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
13608 #define TAMP_IER_ITAMP3IE_Pos        (18U)
13609 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
13610 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
13611 #define TAMP_IER_ITAMP4IE_Pos        (19U)
13612 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
13613 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
13614 #define TAMP_IER_ITAMP5IE_Pos        (20U)
13615 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
13616 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
13617 #define TAMP_IER_ITAMP6IE_Pos        (21U)
13618 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
13619 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
13620 
13621 /********************  Bits definition for TAMP_SR register  ******************/
13622 #define TAMP_SR_TAMP1F_Pos           (0U)
13623 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
13624 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
13625 #define TAMP_SR_TAMP2F_Pos           (1U)
13626 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
13627 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
13628 #define TAMP_SR_TAMP3F_Pos           (2U)
13629 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
13630 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
13631 #define TAMP_SR_ITAMP3F_Pos          (18U)
13632 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
13633 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
13634 #define TAMP_SR_ITAMP4F_Pos          (19U)
13635 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
13636 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
13637 #define TAMP_SR_ITAMP5F_Pos          (20U)
13638 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
13639 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
13640 #define TAMP_SR_ITAMP6F_Pos          (21U)
13641 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
13642 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
13643 
13644 /********************  Bits definition for TAMP_MISR register  ****************/
13645 #define TAMP_MISR_TAMP1MF_Pos        (0U)
13646 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
13647 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
13648 #define TAMP_MISR_TAMP2MF_Pos        (1U)
13649 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
13650 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
13651 #define TAMP_MISR_TAMP3MF_Pos        (2U)
13652 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
13653 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
13654 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
13655 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
13656 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
13657 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
13658 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
13659 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
13660 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
13661 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
13662 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
13663 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
13664 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
13665 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
13666 
13667 /********************  Bits definition for TAMP_SCR register  *****************/
13668 #define TAMP_SCR_CTAMP1F_Pos         (0U)
13669 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
13670 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
13671 #define TAMP_SCR_CTAMP2F_Pos         (1U)
13672 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
13673 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
13674 #define TAMP_SCR_CTAMP3F_Pos         (2U)
13675 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
13676 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
13677 #define TAMP_SCR_CITAMP3F_Pos        (18U)
13678 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
13679 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
13680 #define TAMP_SCR_CITAMP4F_Pos        (19U)
13681 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
13682 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
13683 #define TAMP_SCR_CITAMP5F_Pos        (20U)
13684 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
13685 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
13686 #define TAMP_SCR_CITAMP6F_Pos        (21U)
13687 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
13688 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
13689 
13690 /********************  Bits definition for TAMP_BKP0R register  ***************/
13691 #define TAMP_BKP0R_Pos               (0U)
13692 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
13693 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
13694 
13695 /********************  Bits definition for TAMP_BKP1R register  ***************/
13696 #define TAMP_BKP1R_Pos               (0U)
13697 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
13698 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
13699 
13700 /********************  Bits definition for TAMP_BKP2R register  ***************/
13701 #define TAMP_BKP2R_Pos               (0U)
13702 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
13703 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
13704 
13705 /********************  Bits definition for TAMP_BKP3R register  ***************/
13706 #define TAMP_BKP3R_Pos               (0U)
13707 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
13708 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
13709 
13710 /********************  Bits definition for TAMP_BKP4R register  ***************/
13711 #define TAMP_BKP4R_Pos               (0U)
13712 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
13713 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
13714 
13715 /********************  Bits definition for TAMP_BKP5R register  ***************/
13716 #define TAMP_BKP5R_Pos               (0U)
13717 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
13718 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
13719 
13720 /********************  Bits definition for TAMP_BKP6R register  ***************/
13721 #define TAMP_BKP6R_Pos               (0U)
13722 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
13723 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
13724 
13725 /********************  Bits definition for TAMP_BKP7R register  ***************/
13726 #define TAMP_BKP7R_Pos               (0U)
13727 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
13728 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
13729 
13730 /********************  Bits definition for TAMP_BKP8R register  ***************/
13731 #define TAMP_BKP8R_Pos               (0U)
13732 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
13733 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
13734 
13735 /********************  Bits definition for TAMP_BKP9R register  ***************/
13736 #define TAMP_BKP9R_Pos               (0U)
13737 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
13738 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
13739 
13740 /********************  Bits definition for TAMP_BKP10R register  ***************/
13741 #define TAMP_BKP10R_Pos               (0U)
13742 #define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
13743 #define TAMP_BKP10R                   TAMP_BKP10R_Msk
13744 
13745 /********************  Bits definition for TAMP_BKP11R register  ***************/
13746 #define TAMP_BKP11R_Pos               (0U)
13747 #define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
13748 #define TAMP_BKP11R                   TAMP_BKP11R_Msk
13749 
13750 /********************  Bits definition for TAMP_BKP12R register  ***************/
13751 #define TAMP_BKP12R_Pos               (0U)
13752 #define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
13753 #define TAMP_BKP12R                   TAMP_BKP12R_Msk
13754 
13755 /********************  Bits definition for TAMP_BKP13R register  ***************/
13756 #define TAMP_BKP13R_Pos               (0U)
13757 #define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
13758 #define TAMP_BKP13R                   TAMP_BKP13R_Msk
13759 
13760 /********************  Bits definition for TAMP_BKP14R register  ***************/
13761 #define TAMP_BKP14R_Pos               (0U)
13762 #define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
13763 #define TAMP_BKP14R                   TAMP_BKP14R_Msk
13764 
13765 /********************  Bits definition for TAMP_BKP15R register  ***************/
13766 #define TAMP_BKP15R_Pos               (0U)
13767 #define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
13768 #define TAMP_BKP15R                   TAMP_BKP15R_Msk
13769 
13770 /********************  Bits definition for TAMP_BKP16R register  ***************/
13771 #define TAMP_BKP16R_Pos               (0U)
13772 #define TAMP_BKP16R_Msk               (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
13773 #define TAMP_BKP16R                   TAMP_BKP16R_Msk
13774 
13775 /********************  Bits definition for TAMP_BKP17R register  ***************/
13776 #define TAMP_BKP17R_Pos               (0U)
13777 #define TAMP_BKP17R_Msk               (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
13778 #define TAMP_BKP17R                   TAMP_BKP17R_Msk
13779 
13780 /********************  Bits definition for TAMP_BKP18R register  ***************/
13781 #define TAMP_BKP18R_Pos               (0U)
13782 #define TAMP_BKP18R_Msk               (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
13783 #define TAMP_BKP18R                   TAMP_BKP18R_Msk
13784 
13785 /********************  Bits definition for TAMP_BKP19R register  ***************/
13786 #define TAMP_BKP19R_Pos               (0U)
13787 #define TAMP_BKP19R_Msk               (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
13788 #define TAMP_BKP19R                   TAMP_BKP19R_Msk
13789 
13790 /********************  Bits definition for TAMP_BKP20R register  ***************/
13791 #define TAMP_BKP20R_Pos               (0U)
13792 #define TAMP_BKP20R_Msk               (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
13793 #define TAMP_BKP20R                   TAMP_BKP20R_Msk
13794 
13795 /********************  Bits definition for TAMP_BKP21R register  ***************/
13796 #define TAMP_BKP21R_Pos               (0U)
13797 #define TAMP_BKP21R_Msk               (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
13798 #define TAMP_BKP21R                   TAMP_BKP21R_Msk
13799 
13800 /********************  Bits definition for TAMP_BKP22R register  ***************/
13801 #define TAMP_BKP22R_Pos               (0U)
13802 #define TAMP_BKP22R_Msk               (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
13803 #define TAMP_BKP22R                   TAMP_BKP22R_Msk
13804 
13805 /********************  Bits definition for TAMP_BKP23R register  ***************/
13806 #define TAMP_BKP23R_Pos               (0U)
13807 #define TAMP_BKP23R_Msk               (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
13808 #define TAMP_BKP23R                   TAMP_BKP23R_Msk
13809 
13810 /********************  Bits definition for TAMP_BKP24R register  ***************/
13811 #define TAMP_BKP24R_Pos               (0U)
13812 #define TAMP_BKP24R_Msk               (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
13813 #define TAMP_BKP24R                   TAMP_BKP24R_Msk
13814 
13815 /********************  Bits definition for TAMP_BKP25R register  ***************/
13816 #define TAMP_BKP25R_Pos               (0U)
13817 #define TAMP_BKP25R_Msk               (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
13818 #define TAMP_BKP25R                   TAMP_BKP25R_Msk
13819 
13820 /********************  Bits definition for TAMP_BKP26R register  ***************/
13821 #define TAMP_BKP26R_Pos               (0U)
13822 #define TAMP_BKP26R_Msk               (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
13823 #define TAMP_BKP26R                   TAMP_BKP26R_Msk
13824 
13825 /********************  Bits definition for TAMP_BKP27R register  ***************/
13826 #define TAMP_BKP27R_Pos               (0U)
13827 #define TAMP_BKP27R_Msk               (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
13828 #define TAMP_BKP27R                   TAMP_BKP27R_Msk
13829 
13830 /********************  Bits definition for TAMP_BKP28R register  ***************/
13831 #define TAMP_BKP28R_Pos               (0U)
13832 #define TAMP_BKP28R_Msk               (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
13833 #define TAMP_BKP28R                   TAMP_BKP28R_Msk
13834 
13835 /********************  Bits definition for TAMP_BKP29R register  ***************/
13836 #define TAMP_BKP29R_Pos               (0U)
13837 #define TAMP_BKP29R_Msk               (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
13838 #define TAMP_BKP29R                   TAMP_BKP29R_Msk
13839 
13840 /********************  Bits definition for TAMP_BKP30R register  ***************/
13841 #define TAMP_BKP30R_Pos               (0U)
13842 #define TAMP_BKP30R_Msk               (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
13843 #define TAMP_BKP30R                   TAMP_BKP30R_Msk
13844 
13845 /********************  Bits definition for TAMP_BKP31R register  ***************/
13846 #define TAMP_BKP31R_Pos               (0U)
13847 #define TAMP_BKP31R_Msk               (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
13848 #define TAMP_BKP31R                   TAMP_BKP31R_Msk
13849 
13850 
13851 /******************************************************************************/
13852 /*                                                                            */
13853 /*                          Serial Audio Interface                            */
13854 /*                                                                            */
13855 /******************************************************************************/
13856 /*******************  Bit definition for SAI_xCR1 register  *******************/
13857 #define SAI_xCR1_MODE_Pos          (0U)
13858 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
13859 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
13860 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */
13861 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */
13862 
13863 #define SAI_xCR1_PRTCFG_Pos        (2U)
13864 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
13865 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
13866 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */
13867 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */
13868 
13869 #define SAI_xCR1_DS_Pos            (5U)
13870 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
13871 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
13872 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */
13873 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */
13874 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */
13875 
13876 #define SAI_xCR1_LSBFIRST_Pos      (8U)
13877 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
13878 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
13879 #define SAI_xCR1_CKSTR_Pos         (9U)
13880 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
13881 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
13882 
13883 #define SAI_xCR1_SYNCEN_Pos        (10U)
13884 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
13885 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
13886 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */
13887 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */
13888 
13889 #define SAI_xCR1_MONO_Pos          (12U)
13890 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
13891 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
13892 #define SAI_xCR1_OUTDRIV_Pos       (13U)
13893 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
13894 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
13895 #define SAI_xCR1_SAIEN_Pos         (16U)
13896 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
13897 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
13898 #define SAI_xCR1_DMAEN_Pos         (17U)
13899 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
13900 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
13901 #define SAI_xCR1_NODIV_Pos         (19U)
13902 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
13903 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
13904 
13905 #define SAI_xCR1_MCKDIV_Pos        (20U)
13906 #define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
13907 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
13908 #define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
13909 #define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
13910 #define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
13911 #define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
13912 #define SAI_xCR1_MCKDIV_4          (0x01000000U)                               /*!<Bit 4  */
13913 #define SAI_xCR1_MCKDIV_5          (0x02000000U)                               /*!<Bit 5  */
13914 
13915 #define SAI_xCR1_OSR_Pos           (26U)
13916 #define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
13917 #define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<Oversampling ratio for master clock */
13918 
13919 #define SAI_xCR1_MCKEN_Pos         (27U)
13920 #define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
13921 #define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master clock generation enable */
13922 
13923 /*******************  Bit definition for SAI_xCR2 register  *******************/
13924 #define SAI_xCR2_FTH_Pos           (0U)
13925 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
13926 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
13927 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */
13928 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */
13929 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */
13930 
13931 #define SAI_xCR2_FFLUSH_Pos        (3U)
13932 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
13933 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
13934 #define SAI_xCR2_TRIS_Pos          (4U)
13935 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
13936 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
13937 #define SAI_xCR2_MUTE_Pos          (5U)
13938 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
13939 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
13940 #define SAI_xCR2_MUTEVAL_Pos       (6U)
13941 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
13942 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
13943 
13944 
13945 #define SAI_xCR2_MUTECNT_Pos       (7U)
13946 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
13947 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
13948 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */
13949 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */
13950 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */
13951 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */
13952 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */
13953 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */
13954 
13955 #define SAI_xCR2_CPL_Pos           (13U)
13956 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
13957 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
13958 #define SAI_xCR2_COMP_Pos          (14U)
13959 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
13960 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
13961 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */
13962 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */
13963 
13964 
13965 /******************  Bit definition for SAI_xFRCR register  *******************/
13966 #define SAI_xFRCR_FRL_Pos          (0U)
13967 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
13968 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
13969 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */
13970 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */
13971 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */
13972 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */
13973 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */
13974 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */
13975 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */
13976 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */
13977 
13978 #define SAI_xFRCR_FSALL_Pos        (8U)
13979 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
13980 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
13981 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */
13982 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */
13983 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */
13984 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */
13985 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */
13986 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */
13987 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */
13988 
13989 #define SAI_xFRCR_FSDEF_Pos        (16U)
13990 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
13991 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
13992 #define SAI_xFRCR_FSPOL_Pos        (17U)
13993 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
13994 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
13995 #define SAI_xFRCR_FSOFF_Pos        (18U)
13996 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
13997 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
13998 
13999 /******************  Bit definition for SAI_xSLOTR register  *******************/
14000 #define SAI_xSLOTR_FBOFF_Pos       (0U)
14001 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
14002 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
14003 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */
14004 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */
14005 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */
14006 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */
14007 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */
14008 
14009 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
14010 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
14011 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
14012 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */
14013 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */
14014 
14015 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
14016 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
14017 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
14018 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */
14019 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */
14020 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */
14021 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */
14022 
14023 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
14024 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
14025 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
14026 
14027 /*******************  Bit definition for SAI_xIMR register  *******************/
14028 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
14029 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
14030 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
14031 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
14032 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
14033 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
14034 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
14035 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
14036 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
14037 #define SAI_xIMR_FREQIE_Pos        (3U)
14038 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
14039 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
14040 #define SAI_xIMR_CNRDYIE_Pos       (4U)
14041 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
14042 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
14043 #define SAI_xIMR_AFSDETIE_Pos      (5U)
14044 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
14045 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
14046 #define SAI_xIMR_LFSDETIE_Pos      (6U)
14047 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
14048 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
14049 
14050 /********************  Bit definition for SAI_xSR register  *******************/
14051 #define SAI_xSR_OVRUDR_Pos         (0U)
14052 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
14053 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
14054 #define SAI_xSR_MUTEDET_Pos        (1U)
14055 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
14056 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
14057 #define SAI_xSR_WCKCFG_Pos         (2U)
14058 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
14059 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
14060 #define SAI_xSR_FREQ_Pos           (3U)
14061 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
14062 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
14063 #define SAI_xSR_CNRDY_Pos          (4U)
14064 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
14065 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
14066 #define SAI_xSR_AFSDET_Pos         (5U)
14067 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
14068 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
14069 #define SAI_xSR_LFSDET_Pos         (6U)
14070 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
14071 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
14072 
14073 #define SAI_xSR_FLVL_Pos           (16U)
14074 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
14075 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
14076 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */
14077 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */
14078 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */
14079 
14080 /******************  Bit definition for SAI_xCLRFR register  ******************/
14081 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
14082 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
14083 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
14084 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
14085 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
14086 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
14087 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
14088 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
14089 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
14090 #define SAI_xCLRFR_CFREQ_Pos       (3U)
14091 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
14092 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
14093 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
14094 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
14095 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
14096 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
14097 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
14098 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
14099 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
14100 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
14101 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
14102 
14103 /******************  Bit definition for SAI_xDR register  ******************/
14104 #define SAI_xDR_DATA_Pos           (0U)
14105 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
14106 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
14107 
14108 /******************  Bit definition for SAI_PDMCR register  *******************/
14109 #define SAI_PDMCR_PDMEN_Pos        (0U)
14110 #define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
14111 #define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM enable */
14112 
14113 #define SAI_PDMCR_MICNBR_Pos       (4U)
14114 #define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
14115 #define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<MICNBR[1:0] (Number of microphones) */
14116 #define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000010 */
14117 #define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000020 */
14118 
14119 #define SAI_PDMCR_CKEN1_Pos        (8U)
14120 #define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
14121 #define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock 1 enable */
14122 #define SAI_PDMCR_CKEN2_Pos        (9U)
14123 #define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
14124 #define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock 2 enable */
14125 #define SAI_PDMCR_CKEN3_Pos        (10U)
14126 #define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
14127 #define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock 3 enable */
14128 #define SAI_PDMCR_CKEN4_Pos        (11U)
14129 #define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
14130 #define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock 4 enable */
14131 
14132 /******************  Bit definition for SAI_PDMDLY register  ******************/
14133 #define SAI_PDMDLY_DLYM1L_Pos      (0U)
14134 #define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
14135 #define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
14136 #define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000001 */
14137 #define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000002 */
14138 #define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000004 */
14139 
14140 #define SAI_PDMDLY_DLYM1R_Pos      (4U)
14141 #define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
14142 #define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
14143 #define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000010 */
14144 #define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000020 */
14145 #define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000040 */
14146 
14147 #define SAI_PDMDLY_DLYM2L_Pos      (8U)
14148 #define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
14149 #define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
14150 #define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000100 */
14151 #define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000200 */
14152 #define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000400 */
14153 
14154 #define SAI_PDMDLY_DLYM2R_Pos      (12U)
14155 #define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
14156 #define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
14157 #define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00001000 */
14158 #define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00002000 */
14159 #define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00004000 */
14160 
14161 #define SAI_PDMDLY_DLYM3L_Pos      (16U)
14162 #define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
14163 #define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
14164 #define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00010000 */
14165 #define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00020000 */
14166 #define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00040000 */
14167 
14168 #define SAI_PDMDLY_DLYM3R_Pos      (20U)
14169 #define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
14170 #define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
14171 #define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00100000 */
14172 #define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00200000 */
14173 #define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00400000 */
14174 
14175 #define SAI_PDMDLY_DLYM4L_Pos      (24U)
14176 #define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
14177 #define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
14178 #define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x01000000 */
14179 #define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x02000000 */
14180 #define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x04000000 */
14181 
14182 #define SAI_PDMDLY_DLYM4R_Pos      (28U)
14183 #define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
14184 #define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
14185 #define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x10000000 */
14186 #define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x20000000 */
14187 #define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x40000000 */
14188 
14189 
14190 /******************************************************************************/
14191 /*                                                                            */
14192 /*                        Serial Peripheral Interface (SPI)                   */
14193 /*                                                                            */
14194 /******************************************************************************/
14195 /*
14196  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
14197  */
14198 #define SPI_I2S_SUPPORT                       /*!< I2S support */
14199 
14200 /*******************  Bit definition for SPI_CR1 register  ********************/
14201 #define SPI_CR1_CPHA_Pos            (0U)
14202 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
14203 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
14204 #define SPI_CR1_CPOL_Pos            (1U)
14205 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
14206 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
14207 #define SPI_CR1_MSTR_Pos            (2U)
14208 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
14209 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
14210 
14211 #define SPI_CR1_BR_Pos              (3U)
14212 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
14213 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
14214 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
14215 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
14216 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
14217 
14218 #define SPI_CR1_SPE_Pos             (6U)
14219 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
14220 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
14221 #define SPI_CR1_LSBFIRST_Pos        (7U)
14222 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
14223 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
14224 #define SPI_CR1_SSI_Pos             (8U)
14225 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
14226 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
14227 #define SPI_CR1_SSM_Pos             (9U)
14228 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
14229 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
14230 #define SPI_CR1_RXONLY_Pos          (10U)
14231 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
14232 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
14233 #define SPI_CR1_CRCL_Pos            (11U)
14234 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
14235 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
14236 #define SPI_CR1_CRCNEXT_Pos         (12U)
14237 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
14238 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
14239 #define SPI_CR1_CRCEN_Pos           (13U)
14240 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
14241 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
14242 #define SPI_CR1_BIDIOE_Pos          (14U)
14243 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
14244 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
14245 #define SPI_CR1_BIDIMODE_Pos        (15U)
14246 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
14247 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
14248 
14249 /*******************  Bit definition for SPI_CR2 register  ********************/
14250 #define SPI_CR2_RXDMAEN_Pos         (0U)
14251 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
14252 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
14253 #define SPI_CR2_TXDMAEN_Pos         (1U)
14254 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
14255 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
14256 #define SPI_CR2_SSOE_Pos            (2U)
14257 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
14258 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
14259 #define SPI_CR2_NSSP_Pos            (3U)
14260 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
14261 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
14262 #define SPI_CR2_FRF_Pos             (4U)
14263 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
14264 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
14265 #define SPI_CR2_ERRIE_Pos           (5U)
14266 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
14267 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
14268 #define SPI_CR2_RXNEIE_Pos          (6U)
14269 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
14270 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
14271 #define SPI_CR2_TXEIE_Pos           (7U)
14272 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
14273 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
14274 #define SPI_CR2_DS_Pos              (8U)
14275 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
14276 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
14277 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
14278 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
14279 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
14280 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
14281 #define SPI_CR2_FRXTH_Pos           (12U)
14282 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
14283 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
14284 #define SPI_CR2_LDMARX_Pos          (13U)
14285 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
14286 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
14287 #define SPI_CR2_LDMATX_Pos          (14U)
14288 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
14289 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
14290 
14291 /********************  Bit definition for SPI_SR register  ********************/
14292 #define SPI_SR_RXNE_Pos             (0U)
14293 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
14294 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
14295 #define SPI_SR_TXE_Pos              (1U)
14296 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
14297 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
14298 #define SPI_SR_CHSIDE_Pos           (2U)
14299 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
14300 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
14301 #define SPI_SR_UDR_Pos              (3U)
14302 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
14303 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
14304 #define SPI_SR_CRCERR_Pos           (4U)
14305 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
14306 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
14307 #define SPI_SR_MODF_Pos             (5U)
14308 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
14309 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
14310 #define SPI_SR_OVR_Pos              (6U)
14311 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
14312 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
14313 #define SPI_SR_BSY_Pos              (7U)
14314 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
14315 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
14316 #define SPI_SR_FRE_Pos              (8U)
14317 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
14318 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
14319 #define SPI_SR_FRLVL_Pos            (9U)
14320 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
14321 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
14322 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
14323 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
14324 #define SPI_SR_FTLVL_Pos            (11U)
14325 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
14326 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
14327 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
14328 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
14329 
14330 /********************  Bit definition for SPI_DR register  ********************/
14331 #define SPI_DR_DR_Pos               (0U)
14332 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
14333 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
14334 
14335 /*******************  Bit definition for SPI_CRCPR register  ******************/
14336 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
14337 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
14338 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
14339 
14340 /******************  Bit definition for SPI_RXCRCR register  ******************/
14341 #define SPI_RXCRCR_RXCRC_Pos        (0U)
14342 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
14343 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
14344 
14345 /******************  Bit definition for SPI_TXCRCR register  ******************/
14346 #define SPI_TXCRCR_TXCRC_Pos        (0U)
14347 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
14348 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
14349 
14350 /******************  Bit definition for SPI_I2SCFGR register  *****************/
14351 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
14352 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
14353 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
14354 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
14355 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
14356 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
14357 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
14358 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
14359 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
14360 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
14361 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
14362 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
14363 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
14364 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
14365 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
14366 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
14367 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
14368 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
14369 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
14370 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
14371 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
14372 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
14373 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
14374 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
14375 #define SPI_I2SCFGR_I2SE_Pos        (10U)
14376 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
14377 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
14378 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
14379 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
14380 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
14381 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
14382 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
14383 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
14384 
14385 /******************  Bit definition for SPI_I2SPR register  *******************/
14386 #define SPI_I2SPR_I2SDIV_Pos        (0U)
14387 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
14388 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
14389 #define SPI_I2SPR_ODD_Pos           (8U)
14390 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
14391 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
14392 #define SPI_I2SPR_MCKOE_Pos         (9U)
14393 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
14394 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
14395 
14396 /******************************************************************************/
14397 /*                                                                            */
14398 /*                                 SYSCFG                                     */
14399 /*                                                                            */
14400 /******************************************************************************/
14401 /******************  Bit definition for SYSCFG_MEMRMP register ***************/
14402 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
14403 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
14404 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
14405 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
14406 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
14407 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
14408 
14409 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
14410 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
14411 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
14412 
14413 /******************  Bit definition for SYSCFG_CFGR1 register ******************/
14414 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
14415 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
14416 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
14417 #define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
14418 #define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
14419 #define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
14420 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
14421 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
14422 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
14423 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
14424 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
14425 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
14426 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
14427 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
14428 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
14429 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
14430 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
14431 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
14432 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
14433 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
14434 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
14435 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
14436 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
14437 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
14438 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
14439 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
14440 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
14441 #define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)
14442 #define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos)   /*!< 0x00800000 */
14443 #define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */
14444 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
14445 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
14446 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
14447 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
14448 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
14449 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
14450 
14451 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
14452 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
14453 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
14454 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
14455 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
14456 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
14457 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
14458 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
14459 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
14460 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
14461 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
14462 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
14463 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
14464 
14465 /**
14466   * @brief   EXTI0 configuration
14467   */
14468 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
14469 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
14470 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
14471 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
14472 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
14473 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
14474 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
14475 
14476 /**
14477   * @brief   EXTI1 configuration
14478   */
14479 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
14480 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
14481 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
14482 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
14483 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
14484 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
14485 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
14486 
14487 /**
14488   * @brief   EXTI2 configuration
14489   */
14490 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
14491 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
14492 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
14493 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
14494 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
14495 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
14496 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
14497 
14498 /**
14499   * @brief   EXTI3 configuration
14500   */
14501 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
14502 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
14503 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
14504 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
14505 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
14506 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
14507 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
14508 
14509 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
14510 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
14511 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
14512 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
14513 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
14514 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
14515 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
14516 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
14517 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
14518 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
14519 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
14520 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
14521 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
14522 
14523 /**
14524   * @brief   EXTI4 configuration
14525   */
14526 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
14527 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
14528 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
14529 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
14530 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
14531 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
14532 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
14533 
14534 /**
14535   * @brief   EXTI5 configuration
14536   */
14537 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
14538 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
14539 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
14540 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
14541 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
14542 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
14543 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
14544 
14545 /**
14546   * @brief   EXTI6 configuration
14547   */
14548 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
14549 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
14550 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
14551 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
14552 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
14553 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
14554 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
14555 
14556 /**
14557   * @brief   EXTI7 configuration
14558   */
14559 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
14560 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
14561 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
14562 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
14563 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
14564 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
14565 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
14566 
14567 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
14568 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
14569 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
14570 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
14571 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
14572 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
14573 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
14574 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
14575 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
14576 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
14577 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
14578 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
14579 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
14580 
14581 /**
14582   * @brief   EXTI8 configuration
14583   */
14584 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
14585 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
14586 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
14587 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
14588 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
14589 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
14590 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
14591 
14592 /**
14593   * @brief   EXTI9 configuration
14594   */
14595 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
14596 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
14597 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
14598 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
14599 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
14600 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
14601 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
14602 
14603 /**
14604   * @brief   EXTI10 configuration
14605   */
14606 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
14607 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
14608 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
14609 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
14610 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
14611 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
14612 
14613 /**
14614   * @brief   EXTI11 configuration
14615   */
14616 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
14617 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
14618 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
14619 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
14620 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
14621 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
14622 
14623 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
14624 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
14625 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
14626 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
14627 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
14628 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
14629 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
14630 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
14631 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
14632 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
14633 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
14634 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
14635 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
14636 
14637 /**
14638   * @brief   EXTI12 configuration
14639   */
14640 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
14641 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
14642 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
14643 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
14644 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
14645 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
14646 
14647 /**
14648   * @brief   EXTI13 configuration
14649   */
14650 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
14651 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
14652 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
14653 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
14654 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
14655 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
14656 
14657 /**
14658   * @brief   EXTI14 configuration
14659   */
14660 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
14661 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
14662 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
14663 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
14664 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
14665 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
14666 
14667 /**
14668   * @brief   EXTI15 configuration
14669   */
14670 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
14671 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
14672 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
14673 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
14674 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
14675 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
14676 
14677 /******************  Bit definition for SYSCFG_SCSR register  ****************/
14678 #define SYSCFG_SCSR_CCMER_Pos         (0U)
14679 #define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
14680 #define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
14681 #define SYSCFG_SCSR_CCMBSY_Pos        (1U)
14682 #define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
14683 #define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
14684 
14685 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
14686 #define SYSCFG_CFGR2_CLL_Pos            (0U)
14687 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
14688 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
14689 #define SYSCFG_CFGR2_SPL_Pos            (1U)
14690 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
14691 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
14692 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
14693 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
14694 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
14695 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
14696 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
14697 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
14698 #define SYSCFG_CFGR2_SPF_Pos            (8U)
14699 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
14700 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
14701 
14702 /******************  Bit definition for SYSCFG_SWPR register  ****************/
14703 #define SYSCFG_SWPR_PAGE0_Pos          (0U)
14704 #define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
14705 #define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
14706 #define SYSCFG_SWPR_PAGE1_Pos          (1U)
14707 #define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
14708 #define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
14709 #define SYSCFG_SWPR_PAGE2_Pos          (2U)
14710 #define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
14711 #define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
14712 #define SYSCFG_SWPR_PAGE3_Pos          (3U)
14713 #define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
14714 #define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
14715 #define SYSCFG_SWPR_PAGE4_Pos          (4U)
14716 #define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
14717 #define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
14718 #define SYSCFG_SWPR_PAGE5_Pos          (5U)
14719 #define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
14720 #define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
14721 #define SYSCFG_SWPR_PAGE6_Pos          (6U)
14722 #define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
14723 #define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
14724 #define SYSCFG_SWPR_PAGE7_Pos          (7U)
14725 #define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
14726 #define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
14727 #define SYSCFG_SWPR_PAGE8_Pos          (8U)
14728 #define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
14729 #define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
14730 #define SYSCFG_SWPR_PAGE9_Pos          (9U)
14731 #define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
14732 #define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
14733 #define SYSCFG_SWPR_PAGE10_Pos         (10U)
14734 #define SYSCFG_SWPR_PAGE10_Msk         (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
14735 #define SYSCFG_SWPR_PAGE10             (SYSCFG_SWPR_PAGE10_Msk)               /*!< CCMSRAM  Write protection page 10*/
14736 #define SYSCFG_SWPR_PAGE11_Pos         (11U)
14737 #define SYSCFG_SWPR_PAGE11_Msk         (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
14738 #define SYSCFG_SWPR_PAGE11             (SYSCFG_SWPR_PAGE11_Msk)               /*!< CCMSRAM  Write protection page 11*/
14739 #define SYSCFG_SWPR_PAGE12_Pos         (12U)
14740 #define SYSCFG_SWPR_PAGE12_Msk         (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
14741 #define SYSCFG_SWPR_PAGE12             (SYSCFG_SWPR_PAGE12_Msk)               /*!< CCMSRAM  Write protection page 12*/
14742 #define SYSCFG_SWPR_PAGE13_Pos         (13U)
14743 #define SYSCFG_SWPR_PAGE13_Msk         (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
14744 #define SYSCFG_SWPR_PAGE13             (SYSCFG_SWPR_PAGE13_Msk)               /*!< CCMSRAM  Write protection page 13*/
14745 #define SYSCFG_SWPR_PAGE14_Pos         (14U)
14746 #define SYSCFG_SWPR_PAGE14_Msk         (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
14747 #define SYSCFG_SWPR_PAGE14             (SYSCFG_SWPR_PAGE14_Msk)               /*!< CCMSRAM  Write protection page 14*/
14748 #define SYSCFG_SWPR_PAGE15_Pos         (15U)
14749 #define SYSCFG_SWPR_PAGE15_Msk         (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
14750 #define SYSCFG_SWPR_PAGE15             (SYSCFG_SWPR_PAGE15_Msk)               /*!< CCMSRAM  Write protection page 15*/
14751 #define SYSCFG_SWPR_PAGE16_Pos         (16U)
14752 #define SYSCFG_SWPR_PAGE16_Msk         (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */
14753 #define SYSCFG_SWPR_PAGE16             (SYSCFG_SWPR_PAGE16_Msk)               /*!< CCMSRAM  Write protection page 16*/
14754 #define SYSCFG_SWPR_PAGE17_Pos         (17U)
14755 #define SYSCFG_SWPR_PAGE17_Msk         (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */
14756 #define SYSCFG_SWPR_PAGE17             (SYSCFG_SWPR_PAGE17_Msk)               /*!< CCMSRAM  Write protection page 17*/
14757 #define SYSCFG_SWPR_PAGE18_Pos         (18U)
14758 #define SYSCFG_SWPR_PAGE18_Msk         (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */
14759 #define SYSCFG_SWPR_PAGE18             (SYSCFG_SWPR_PAGE18_Msk)               /*!< CCMSRAM  Write protection page 18*/
14760 #define SYSCFG_SWPR_PAGE19_Pos         (19U)
14761 #define SYSCFG_SWPR_PAGE19_Msk         (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */
14762 #define SYSCFG_SWPR_PAGE19             (SYSCFG_SWPR_PAGE19_Msk)               /*!< CCMSRAM  Write protection page 19*/
14763 #define SYSCFG_SWPR_PAGE20_Pos         (20U)
14764 #define SYSCFG_SWPR_PAGE20_Msk         (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */
14765 #define SYSCFG_SWPR_PAGE20             (SYSCFG_SWPR_PAGE20_Msk)               /*!< CCMSRAM  Write protection page 20*/
14766 #define SYSCFG_SWPR_PAGE21_Pos         (21U)
14767 #define SYSCFG_SWPR_PAGE21_Msk         (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */
14768 #define SYSCFG_SWPR_PAGE21             (SYSCFG_SWPR_PAGE21_Msk)               /*!< CCMSRAM  Write protection page 21*/
14769 #define SYSCFG_SWPR_PAGE22_Pos         (22U)
14770 #define SYSCFG_SWPR_PAGE22_Msk         (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */
14771 #define SYSCFG_SWPR_PAGE22             (SYSCFG_SWPR_PAGE22_Msk)               /*!< CCMSRAM  Write protection page 22*/
14772 #define SYSCFG_SWPR_PAGE23_Pos         (23U)
14773 #define SYSCFG_SWPR_PAGE23_Msk         (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */
14774 #define SYSCFG_SWPR_PAGE23             (SYSCFG_SWPR_PAGE23_Msk)               /*!< CCMSRAM  Write protection page 23*/
14775 #define SYSCFG_SWPR_PAGE24_Pos         (24U)
14776 #define SYSCFG_SWPR_PAGE24_Msk         (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */
14777 #define SYSCFG_SWPR_PAGE24             (SYSCFG_SWPR_PAGE24_Msk)               /*!< CCMSRAM  Write protection page 24*/
14778 #define SYSCFG_SWPR_PAGE25_Pos         (25U)
14779 #define SYSCFG_SWPR_PAGE25_Msk         (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */
14780 #define SYSCFG_SWPR_PAGE25             (SYSCFG_SWPR_PAGE25_Msk)               /*!< CCMSRAM  Write protection page 25*/
14781 #define SYSCFG_SWPR_PAGE26_Pos         (26U)
14782 #define SYSCFG_SWPR_PAGE26_Msk         (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */
14783 #define SYSCFG_SWPR_PAGE26             (SYSCFG_SWPR_PAGE26_Msk)               /*!< CCMSRAM  Write protection page 26*/
14784 #define SYSCFG_SWPR_PAGE27_Pos         (27U)
14785 #define SYSCFG_SWPR_PAGE27_Msk         (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */
14786 #define SYSCFG_SWPR_PAGE27             (SYSCFG_SWPR_PAGE27_Msk)               /*!< CCMSRAM  Write protection page 27*/
14787 #define SYSCFG_SWPR_PAGE28_Pos         (28U)
14788 #define SYSCFG_SWPR_PAGE28_Msk         (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */
14789 #define SYSCFG_SWPR_PAGE28             (SYSCFG_SWPR_PAGE28_Msk)               /*!< CCMSRAM  Write protection page 28*/
14790 #define SYSCFG_SWPR_PAGE29_Pos         (29U)
14791 #define SYSCFG_SWPR_PAGE29_Msk         (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */
14792 #define SYSCFG_SWPR_PAGE29             (SYSCFG_SWPR_PAGE29_Msk)               /*!< CCMSRAM  Write protection page 29*/
14793 #define SYSCFG_SWPR_PAGE30_Pos         (30U)
14794 #define SYSCFG_SWPR_PAGE30_Msk         (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */
14795 #define SYSCFG_SWPR_PAGE30             (SYSCFG_SWPR_PAGE30_Msk)               /*!< CCMSRAM  Write protection page 30*/
14796 #define SYSCFG_SWPR_PAGE31_Pos         (31U)
14797 #define SYSCFG_SWPR_PAGE31_Msk         (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */
14798 #define SYSCFG_SWPR_PAGE31             (SYSCFG_SWPR_PAGE31_Msk)               /*!< CCMSRAM  Write protection page 31*/
14799 
14800 /******************  Bit definition for SYSCFG_SKR register  ****************/
14801 #define SYSCFG_SKR_KEY_Pos              (0U)
14802 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
14803 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
14804 
14805 /******************************************************************************/
14806 /*                                                                            */
14807 /*                                    TIM                                     */
14808 /*                                                                            */
14809 /******************************************************************************/
14810 /*******************  Bit definition for TIM_CR1 register  ********************/
14811 #define TIM_CR1_CEN_Pos           (0U)
14812 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
14813 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
14814 #define TIM_CR1_UDIS_Pos          (1U)
14815 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
14816 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
14817 #define TIM_CR1_URS_Pos           (2U)
14818 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
14819 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
14820 #define TIM_CR1_OPM_Pos           (3U)
14821 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
14822 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
14823 #define TIM_CR1_DIR_Pos           (4U)
14824 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
14825 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
14826 
14827 #define TIM_CR1_CMS_Pos           (5U)
14828 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
14829 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
14830 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
14831 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
14832 
14833 #define TIM_CR1_ARPE_Pos          (7U)
14834 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
14835 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
14836 
14837 #define TIM_CR1_CKD_Pos           (8U)
14838 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
14839 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
14840 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
14841 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
14842 
14843 #define TIM_CR1_UIFREMAP_Pos      (11U)
14844 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
14845 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
14846 
14847 #define TIM_CR1_DITHEN_Pos      (12U)
14848 #define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
14849 #define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
14850 
14851 /*******************  Bit definition for TIM_CR2 register  ********************/
14852 #define TIM_CR2_CCPC_Pos          (0U)
14853 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
14854 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
14855 #define TIM_CR2_CCUS_Pos          (2U)
14856 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
14857 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
14858 #define TIM_CR2_CCDS_Pos          (3U)
14859 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
14860 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
14861 
14862 #define TIM_CR2_MMS_Pos           (4U)
14863 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
14864 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
14865 #define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
14866 #define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
14867 #define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
14868 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
14869 
14870 #define TIM_CR2_TI1S_Pos          (7U)
14871 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
14872 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
14873 #define TIM_CR2_OIS1_Pos          (8U)
14874 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
14875 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
14876 #define TIM_CR2_OIS1N_Pos         (9U)
14877 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
14878 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
14879 #define TIM_CR2_OIS2_Pos          (10U)
14880 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
14881 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
14882 #define TIM_CR2_OIS2N_Pos         (11U)
14883 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
14884 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
14885 #define TIM_CR2_OIS3_Pos          (12U)
14886 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
14887 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
14888 #define TIM_CR2_OIS3N_Pos         (13U)
14889 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
14890 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
14891 #define TIM_CR2_OIS4_Pos          (14U)
14892 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
14893 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
14894 #define TIM_CR2_OIS4N_Pos         (15U)
14895 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
14896 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
14897 #define TIM_CR2_OIS5_Pos          (16U)
14898 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
14899 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
14900 #define TIM_CR2_OIS6_Pos          (18U)
14901 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
14902 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
14903 
14904 #define TIM_CR2_MMS2_Pos          (20U)
14905 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
14906 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
14907 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
14908 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
14909 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
14910 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
14911 
14912 /*******************  Bit definition for TIM_SMCR register  *******************/
14913 #define TIM_SMCR_SMS_Pos          (0U)
14914 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
14915 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
14916 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
14917 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
14918 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
14919 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
14920 
14921 #define TIM_SMCR_OCCS_Pos         (3U)
14922 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
14923 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
14924 
14925 #define TIM_SMCR_TS_Pos           (4U)
14926 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
14927 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
14928 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
14929 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
14930 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
14931 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
14932 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
14933 
14934 #define TIM_SMCR_MSM_Pos          (7U)
14935 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
14936 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
14937 
14938 #define TIM_SMCR_ETF_Pos          (8U)
14939 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
14940 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
14941 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
14942 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
14943 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
14944 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
14945 
14946 #define TIM_SMCR_ETPS_Pos         (12U)
14947 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
14948 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
14949 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
14950 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
14951 
14952 #define TIM_SMCR_ECE_Pos          (14U)
14953 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
14954 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
14955 #define TIM_SMCR_ETP_Pos          (15U)
14956 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
14957 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
14958 
14959 #define TIM_SMCR_SMSPE_Pos        (24U)
14960 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
14961 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
14962 
14963 #define TIM_SMCR_SMSPS_Pos        (25U)
14964 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
14965 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
14966 
14967 /*******************  Bit definition for TIM_DIER register  *******************/
14968 #define TIM_DIER_UIE_Pos          (0U)
14969 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
14970 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
14971 #define TIM_DIER_CC1IE_Pos        (1U)
14972 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
14973 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
14974 #define TIM_DIER_CC2IE_Pos        (2U)
14975 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
14976 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
14977 #define TIM_DIER_CC3IE_Pos        (3U)
14978 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
14979 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
14980 #define TIM_DIER_CC4IE_Pos        (4U)
14981 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
14982 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
14983 #define TIM_DIER_COMIE_Pos        (5U)
14984 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
14985 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
14986 #define TIM_DIER_TIE_Pos          (6U)
14987 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
14988 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
14989 #define TIM_DIER_BIE_Pos          (7U)
14990 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
14991 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
14992 #define TIM_DIER_UDE_Pos          (8U)
14993 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
14994 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
14995 #define TIM_DIER_CC1DE_Pos        (9U)
14996 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
14997 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
14998 #define TIM_DIER_CC2DE_Pos        (10U)
14999 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
15000 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
15001 #define TIM_DIER_CC3DE_Pos        (11U)
15002 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
15003 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
15004 #define TIM_DIER_CC4DE_Pos        (12U)
15005 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
15006 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
15007 #define TIM_DIER_COMDE_Pos        (13U)
15008 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
15009 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
15010 #define TIM_DIER_TDE_Pos          (14U)
15011 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
15012 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
15013 #define TIM_DIER_IDXIE_Pos        (20U)
15014 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
15015 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
15016 #define TIM_DIER_DIRIE_Pos        (21U)
15017 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
15018 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
15019 #define TIM_DIER_IERRIE_Pos       (22U)
15020 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
15021 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
15022 #define TIM_DIER_TERRIE_Pos       (23U)
15023 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
15024 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
15025 
15026 /********************  Bit definition for TIM_SR register  ********************/
15027 #define TIM_SR_UIF_Pos            (0U)
15028 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
15029 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
15030 #define TIM_SR_CC1IF_Pos          (1U)
15031 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
15032 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
15033 #define TIM_SR_CC2IF_Pos          (2U)
15034 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
15035 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
15036 #define TIM_SR_CC3IF_Pos          (3U)
15037 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
15038 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
15039 #define TIM_SR_CC4IF_Pos          (4U)
15040 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
15041 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
15042 #define TIM_SR_COMIF_Pos          (5U)
15043 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
15044 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
15045 #define TIM_SR_TIF_Pos            (6U)
15046 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
15047 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
15048 #define TIM_SR_BIF_Pos            (7U)
15049 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
15050 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
15051 #define TIM_SR_B2IF_Pos           (8U)
15052 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
15053 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
15054 #define TIM_SR_CC1OF_Pos          (9U)
15055 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
15056 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
15057 #define TIM_SR_CC2OF_Pos          (10U)
15058 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
15059 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
15060 #define TIM_SR_CC3OF_Pos          (11U)
15061 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
15062 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
15063 #define TIM_SR_CC4OF_Pos          (12U)
15064 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
15065 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
15066 #define TIM_SR_SBIF_Pos           (13U)
15067 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
15068 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
15069 #define TIM_SR_CC5IF_Pos          (16U)
15070 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
15071 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
15072 #define TIM_SR_CC6IF_Pos          (17U)
15073 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
15074 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
15075 #define TIM_SR_IDXF_Pos           (20U)
15076 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
15077 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
15078 #define TIM_SR_DIRF_Pos           (21U)
15079 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
15080 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
15081 #define TIM_SR_IERRF_Pos          (22U)
15082 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
15083 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
15084 #define TIM_SR_TERRF_Pos          (23U)
15085 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
15086 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
15087 
15088 /*******************  Bit definition for TIM_EGR register  ********************/
15089 #define TIM_EGR_UG_Pos            (0U)
15090 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
15091 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
15092 #define TIM_EGR_CC1G_Pos          (1U)
15093 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
15094 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
15095 #define TIM_EGR_CC2G_Pos          (2U)
15096 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
15097 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
15098 #define TIM_EGR_CC3G_Pos          (3U)
15099 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
15100 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
15101 #define TIM_EGR_CC4G_Pos          (4U)
15102 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
15103 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
15104 #define TIM_EGR_COMG_Pos          (5U)
15105 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
15106 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
15107 #define TIM_EGR_TG_Pos            (6U)
15108 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
15109 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
15110 #define TIM_EGR_BG_Pos            (7U)
15111 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
15112 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
15113 #define TIM_EGR_B2G_Pos           (8U)
15114 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
15115 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
15116 
15117 
15118 /******************  Bit definition for TIM_CCMR1 register  *******************/
15119 #define TIM_CCMR1_CC1S_Pos        (0U)
15120 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
15121 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
15122 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
15123 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
15124 
15125 #define TIM_CCMR1_OC1FE_Pos       (2U)
15126 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
15127 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
15128 #define TIM_CCMR1_OC1PE_Pos       (3U)
15129 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
15130 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
15131 
15132 #define TIM_CCMR1_OC1M_Pos        (4U)
15133 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
15134 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
15135 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
15136 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
15137 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
15138 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
15139 
15140 #define TIM_CCMR1_OC1CE_Pos       (7U)
15141 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
15142 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
15143 
15144 #define TIM_CCMR1_CC2S_Pos        (8U)
15145 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
15146 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
15147 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
15148 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
15149 
15150 #define TIM_CCMR1_OC2FE_Pos       (10U)
15151 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
15152 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
15153 #define TIM_CCMR1_OC2PE_Pos       (11U)
15154 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
15155 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
15156 
15157 #define TIM_CCMR1_OC2M_Pos        (12U)
15158 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
15159 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
15160 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
15161 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
15162 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
15163 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
15164 
15165 #define TIM_CCMR1_OC2CE_Pos       (15U)
15166 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
15167 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
15168 
15169 /*----------------------------------------------------------------------------*/
15170 #define TIM_CCMR1_IC1PSC_Pos      (2U)
15171 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
15172 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
15173 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
15174 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
15175 
15176 #define TIM_CCMR1_IC1F_Pos        (4U)
15177 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
15178 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
15179 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
15180 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
15181 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
15182 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
15183 
15184 #define TIM_CCMR1_IC2PSC_Pos      (10U)
15185 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
15186 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
15187 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
15188 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
15189 
15190 #define TIM_CCMR1_IC2F_Pos        (12U)
15191 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
15192 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
15193 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
15194 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
15195 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
15196 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
15197 
15198 /******************  Bit definition for TIM_CCMR2 register  *******************/
15199 #define TIM_CCMR2_CC3S_Pos        (0U)
15200 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
15201 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
15202 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
15203 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
15204 
15205 #define TIM_CCMR2_OC3FE_Pos       (2U)
15206 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
15207 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
15208 #define TIM_CCMR2_OC3PE_Pos       (3U)
15209 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
15210 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
15211 
15212 #define TIM_CCMR2_OC3M_Pos        (4U)
15213 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
15214 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
15215 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
15216 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
15217 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
15218 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
15219 
15220 #define TIM_CCMR2_OC3CE_Pos       (7U)
15221 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
15222 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
15223 
15224 #define TIM_CCMR2_CC4S_Pos        (8U)
15225 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
15226 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
15227 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
15228 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
15229 
15230 #define TIM_CCMR2_OC4FE_Pos       (10U)
15231 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
15232 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
15233 #define TIM_CCMR2_OC4PE_Pos       (11U)
15234 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
15235 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
15236 
15237 #define TIM_CCMR2_OC4M_Pos        (12U)
15238 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
15239 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
15240 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
15241 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
15242 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
15243 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
15244 
15245 #define TIM_CCMR2_OC4CE_Pos       (15U)
15246 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
15247 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
15248 
15249 /*----------------------------------------------------------------------------*/
15250 #define TIM_CCMR2_IC3PSC_Pos      (2U)
15251 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
15252 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
15253 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
15254 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
15255 
15256 #define TIM_CCMR2_IC3F_Pos        (4U)
15257 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
15258 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
15259 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
15260 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
15261 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
15262 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
15263 
15264 #define TIM_CCMR2_IC4PSC_Pos      (10U)
15265 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
15266 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
15267 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
15268 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
15269 
15270 #define TIM_CCMR2_IC4F_Pos        (12U)
15271 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
15272 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
15273 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
15274 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
15275 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
15276 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
15277 
15278 /******************  Bit definition for TIM_CCMR3 register  *******************/
15279 #define TIM_CCMR3_OC5FE_Pos       (2U)
15280 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
15281 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
15282 #define TIM_CCMR3_OC5PE_Pos       (3U)
15283 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
15284 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
15285 
15286 #define TIM_CCMR3_OC5M_Pos        (4U)
15287 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
15288 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
15289 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
15290 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
15291 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
15292 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
15293 
15294 #define TIM_CCMR3_OC5CE_Pos       (7U)
15295 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
15296 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
15297 
15298 #define TIM_CCMR3_OC6FE_Pos       (10U)
15299 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
15300 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
15301 #define TIM_CCMR3_OC6PE_Pos       (11U)
15302 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
15303 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
15304 
15305 #define TIM_CCMR3_OC6M_Pos        (12U)
15306 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
15307 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
15308 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
15309 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
15310 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
15311 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
15312 
15313 #define TIM_CCMR3_OC6CE_Pos       (15U)
15314 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
15315 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
15316 
15317 /*******************  Bit definition for TIM_CCER register  *******************/
15318 #define TIM_CCER_CC1E_Pos         (0U)
15319 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
15320 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
15321 #define TIM_CCER_CC1P_Pos         (1U)
15322 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
15323 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
15324 #define TIM_CCER_CC1NE_Pos        (2U)
15325 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
15326 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
15327 #define TIM_CCER_CC1NP_Pos        (3U)
15328 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
15329 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
15330 #define TIM_CCER_CC2E_Pos         (4U)
15331 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
15332 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
15333 #define TIM_CCER_CC2P_Pos         (5U)
15334 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
15335 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
15336 #define TIM_CCER_CC2NE_Pos        (6U)
15337 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
15338 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
15339 #define TIM_CCER_CC2NP_Pos        (7U)
15340 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
15341 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
15342 #define TIM_CCER_CC3E_Pos         (8U)
15343 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
15344 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
15345 #define TIM_CCER_CC3P_Pos         (9U)
15346 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
15347 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
15348 #define TIM_CCER_CC3NE_Pos        (10U)
15349 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
15350 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
15351 #define TIM_CCER_CC3NP_Pos        (11U)
15352 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
15353 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
15354 #define TIM_CCER_CC4E_Pos         (12U)
15355 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
15356 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
15357 #define TIM_CCER_CC4P_Pos         (13U)
15358 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
15359 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
15360 #define TIM_CCER_CC4NE_Pos        (14U)
15361 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
15362 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
15363 #define TIM_CCER_CC4NP_Pos        (15U)
15364 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
15365 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
15366 #define TIM_CCER_CC5E_Pos         (16U)
15367 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
15368 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
15369 #define TIM_CCER_CC5P_Pos         (17U)
15370 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
15371 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
15372 #define TIM_CCER_CC6E_Pos         (20U)
15373 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
15374 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
15375 #define TIM_CCER_CC6P_Pos         (21U)
15376 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
15377 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
15378 
15379 /*******************  Bit definition for TIM_CNT register  ********************/
15380 #define TIM_CNT_CNT_Pos           (0U)
15381 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
15382 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
15383 #define TIM_CNT_UIFCPY_Pos        (31U)
15384 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
15385 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
15386 
15387 /*******************  Bit definition for TIM_PSC register  ********************/
15388 #define TIM_PSC_PSC_Pos           (0U)
15389 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
15390 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
15391 
15392 /*******************  Bit definition for TIM_ARR register  ********************/
15393 #define TIM_ARR_ARR_Pos           (0U)
15394 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
15395 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
15396 
15397 /*******************  Bit definition for TIM_RCR register  ********************/
15398 #define TIM_RCR_REP_Pos           (0U)
15399 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
15400 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
15401 
15402 /*******************  Bit definition for TIM_CCR1 register  *******************/
15403 #define TIM_CCR1_CCR1_Pos         (0U)
15404 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
15405 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
15406 
15407 /*******************  Bit definition for TIM_CCR2 register  *******************/
15408 #define TIM_CCR2_CCR2_Pos         (0U)
15409 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
15410 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
15411 
15412 /*******************  Bit definition for TIM_CCR3 register  *******************/
15413 #define TIM_CCR3_CCR3_Pos         (0U)
15414 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
15415 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
15416 
15417 /*******************  Bit definition for TIM_CCR4 register  *******************/
15418 #define TIM_CCR4_CCR4_Pos         (0U)
15419 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
15420 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
15421 
15422 /*******************  Bit definition for TIM_CCR5 register  *******************/
15423 #define TIM_CCR5_CCR5_Pos         (0U)
15424 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
15425 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
15426 #define TIM_CCR5_GC5C1_Pos        (29U)
15427 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
15428 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
15429 #define TIM_CCR5_GC5C2_Pos        (30U)
15430 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
15431 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
15432 #define TIM_CCR5_GC5C3_Pos        (31U)
15433 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
15434 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
15435 
15436 /*******************  Bit definition for TIM_CCR6 register  *******************/
15437 #define TIM_CCR6_CCR6_Pos         (0U)
15438 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
15439 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
15440 
15441 /*******************  Bit definition for TIM_BDTR register  *******************/
15442 #define TIM_BDTR_DTG_Pos          (0U)
15443 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
15444 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
15445 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
15446 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
15447 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
15448 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
15449 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
15450 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
15451 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
15452 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
15453 
15454 #define TIM_BDTR_LOCK_Pos         (8U)
15455 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
15456 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
15457 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
15458 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
15459 
15460 #define TIM_BDTR_OSSI_Pos         (10U)
15461 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
15462 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
15463 #define TIM_BDTR_OSSR_Pos         (11U)
15464 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
15465 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
15466 #define TIM_BDTR_BKE_Pos          (12U)
15467 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
15468 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
15469 #define TIM_BDTR_BKP_Pos          (13U)
15470 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
15471 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
15472 #define TIM_BDTR_AOE_Pos          (14U)
15473 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
15474 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
15475 #define TIM_BDTR_MOE_Pos          (15U)
15476 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
15477 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
15478 
15479 #define TIM_BDTR_BKF_Pos          (16U)
15480 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
15481 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
15482 #define TIM_BDTR_BK2F_Pos         (20U)
15483 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
15484 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
15485 
15486 #define TIM_BDTR_BK2E_Pos         (24U)
15487 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
15488 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
15489 #define TIM_BDTR_BK2P_Pos         (25U)
15490 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
15491 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
15492 
15493 #define TIM_BDTR_BKDSRM_Pos       (26U)
15494 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
15495 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
15496 #define TIM_BDTR_BK2DSRM_Pos      (27U)
15497 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
15498 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
15499 
15500 #define TIM_BDTR_BKBID_Pos        (28U)
15501 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
15502 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
15503 #define TIM_BDTR_BK2BID_Pos       (29U)
15504 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
15505 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
15506 
15507 /*******************  Bit definition for TIM_DCR register  ********************/
15508 #define TIM_DCR_DBA_Pos           (0U)
15509 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
15510 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
15511 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
15512 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
15513 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
15514 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
15515 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
15516 
15517 #define TIM_DCR_DBL_Pos           (8U)
15518 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
15519 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
15520 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
15521 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
15522 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
15523 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
15524 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
15525 
15526 /*******************  Bit definition for TIM1_AF1 register  *******************/
15527 #define TIM1_AF1_BKINE_Pos        (0U)
15528 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
15529 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
15530 #define TIM1_AF1_BKCMP1E_Pos      (1U)
15531 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
15532 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
15533 #define TIM1_AF1_BKCMP2E_Pos      (2U)
15534 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
15535 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
15536 #define TIM1_AF1_BKCMP3E_Pos      (3U)
15537 #define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
15538 #define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
15539 #define TIM1_AF1_BKCMP4E_Pos      (4U)
15540 #define TIM1_AF1_BKCMP4E_Msk      (0x1UL << TIM1_AF1_BKCMP4E_Pos)              /*!< 0x00000010 */
15541 #define TIM1_AF1_BKCMP4E          TIM1_AF1_BKCMP4E_Msk                         /*!<BRK COMP4 enable */
15542 #define TIM1_AF1_BKCMP5E_Pos      (5U)
15543 #define TIM1_AF1_BKCMP5E_Msk      (0x1UL << TIM1_AF1_BKCMP5E_Pos)              /*!< 0x00000020 */
15544 #define TIM1_AF1_BKCMP5E          TIM1_AF1_BKCMP5E_Msk                         /*!<BRK COMP5 enable */
15545 #define TIM1_AF1_BKCMP6E_Pos      (6U)
15546 #define TIM1_AF1_BKCMP6E_Msk      (0x1UL << TIM1_AF1_BKCMP6E_Pos)              /*!< 0x00000040 */
15547 #define TIM1_AF1_BKCMP6E          TIM1_AF1_BKCMP6E_Msk                         /*!<BRK COMP6 enable */
15548 #define TIM1_AF1_BKCMP7E_Pos      (7U)
15549 #define TIM1_AF1_BKCMP7E_Msk      (0x1UL << TIM1_AF1_BKCMP7E_Pos)              /*!< 0x00000080 */
15550 #define TIM1_AF1_BKCMP7E          TIM1_AF1_BKCMP7E_Msk                         /*!<BRK COMP7 enable */
15551 #define TIM1_AF1_BKINP_Pos        (9U)
15552 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
15553 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
15554 #define TIM1_AF1_BKCMP1P_Pos      (10U)
15555 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
15556 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
15557 #define TIM1_AF1_BKCMP2P_Pos      (11U)
15558 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
15559 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
15560 #define TIM1_AF1_BKCMP3P_Pos      (12U)
15561 #define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
15562 #define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
15563 #define TIM1_AF1_BKCMP4P_Pos      (13U)
15564 #define TIM1_AF1_BKCMP4P_Msk      (0x1UL << TIM1_AF1_BKCMP4P_Pos)              /*!< 0x00002000 */
15565 #define TIM1_AF1_BKCMP4P          TIM1_AF1_BKCMP4P_Msk                         /*!<BRK COMP4 input polarity */
15566 #define TIM1_AF1_ETRSEL_Pos       (14U)
15567 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
15568 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
15569 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
15570 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
15571 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
15572 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
15573 
15574 /*******************  Bit definition for TIM1_AF2 register  *********************/
15575 #define TIM1_AF2_BK2INE_Pos        (0U)
15576 #define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
15577 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
15578 #define TIM1_AF2_BK2CMP1E_Pos      (1U)
15579 #define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
15580 #define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
15581 #define TIM1_AF2_BK2CMP2E_Pos      (2U)
15582 #define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
15583 #define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
15584 #define TIM1_AF2_BK2CMP3E_Pos      (3U)
15585 #define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
15586 #define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
15587 #define TIM1_AF2_BK2CMP4E_Pos      (4U)
15588 #define TIM1_AF2_BK2CMP4E_Msk      (0x1UL << TIM1_AF2_BK2CMP4E_Pos)              /*!< 0x00000010 */
15589 #define TIM1_AF2_BK2CMP4E          TIM1_AF2_BK2CMP4E_Msk                         /*!<BRK2 COMP4 enable */
15590 #define TIM1_AF2_BK2CMP5E_Pos      (5U)
15591 #define TIM1_AF2_BK2CMP5E_Msk      (0x1UL << TIM1_AF2_BK2CMP5E_Pos)              /*!< 0x00000020 */
15592 #define TIM1_AF2_BK2CMP5E          TIM1_AF2_BK2CMP5E_Msk                         /*!<BRK2 COMP5 enable */
15593 #define TIM1_AF2_BK2CMP6E_Pos      (6U)
15594 #define TIM1_AF2_BK2CMP6E_Msk      (0x1UL << TIM1_AF2_BK2CMP6E_Pos)              /*!< 0x00000040 */
15595 #define TIM1_AF2_BK2CMP6E          TIM1_AF2_BK2CMP6E_Msk                         /*!<BRK2 COMP6 enable */
15596 #define TIM1_AF2_BK2CMP7E_Pos      (7U)
15597 #define TIM1_AF2_BK2CMP7E_Msk      (0x1UL << TIM1_AF2_BK2CMP7E_Pos)              /*!< 0x00000080 */
15598 #define TIM1_AF2_BK2CMP7E          TIM1_AF2_BK2CMP7E_Msk                         /*!<BRK2 COMP7 enable */
15599 #define TIM1_AF2_BK2INP_Pos        (9U)
15600 #define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
15601 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
15602 #define TIM1_AF2_BK2CMP1P_Pos      (10U)
15603 #define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
15604 #define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
15605 #define TIM1_AF2_BK2CMP2P_Pos      (11U)
15606 #define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
15607 #define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
15608 #define TIM1_AF2_BK2CMP3P_Pos      (12U)
15609 #define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
15610 #define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
15611 #define TIM1_AF2_BK2CMP4P_Pos      (13U)
15612 #define TIM1_AF2_BK2CMP4P_Msk      (0x1UL << TIM1_AF2_BK2CMP4P_Pos)              /*!< 0x00000800 */
15613 #define TIM1_AF2_BK2CMP4P          TIM1_AF2_BK2CMP4P_Msk                         /*!<BRK2 COMP4 input polarity */
15614 #define TIM1_AF2_OCRSEL_Pos        (16U)
15615 #define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
15616 #define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
15617 #define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
15618 #define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
15619 #define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
15620 
15621 /*******************  Bit definition for TIM_OR register  *********************/
15622 #define TIM_OR_HSE32EN_Pos       (0U)
15623 #define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
15624 #define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
15625 
15626 /*******************  Bit definition for TIM_TISEL register  *********************/
15627 #define TIM_TISEL_TI1SEL_Pos      (0U)
15628 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
15629 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
15630 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
15631 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
15632 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
15633 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
15634 
15635 #define TIM_TISEL_TI2SEL_Pos      (8U)
15636 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
15637 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
15638 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
15639 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
15640 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
15641 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
15642 
15643 #define TIM_TISEL_TI3SEL_Pos      (16U)
15644 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
15645 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
15646 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
15647 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
15648 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
15649 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
15650 
15651 #define TIM_TISEL_TI4SEL_Pos      (24U)
15652 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
15653 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
15654 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
15655 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
15656 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
15657 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
15658 
15659 /*******************  Bit definition for TIM_DTR2 register  *********************/
15660 #define TIM_DTR2_DTGF_Pos      (0U)
15661 #define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
15662 #define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
15663 #define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
15664 #define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
15665 #define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
15666 #define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
15667 #define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
15668 #define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
15669 #define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
15670 #define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
15671 
15672 #define TIM_DTR2_DTAE_Pos      (16U)
15673 #define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
15674 #define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
15675 #define TIM_DTR2_DTPE_Pos      (17U)
15676 #define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
15677 #define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
15678 
15679 /*******************  Bit definition for TIM_ECR register  *********************/
15680 #define TIM_ECR_IE_Pos       (0U)
15681 #define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
15682 #define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
15683 
15684 #define TIM_ECR_IDIR_Pos      (1U)
15685 #define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
15686 #define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
15687 #define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
15688 #define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
15689 
15690 #define TIM_ECR_FIDX_Pos      (5U)
15691 #define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
15692 #define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
15693 
15694 #define TIM_ECR_IPOS_Pos      (6U)
15695 #define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
15696 #define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
15697 #define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
15698 #define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
15699 
15700 #define TIM_ECR_PW_Pos        (16U)
15701 #define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
15702 #define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
15703 #define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
15704 #define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
15705 #define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
15706 #define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
15707 #define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
15708 #define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
15709 #define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
15710 #define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
15711 
15712 #define TIM_ECR_PWPRSC_Pos    (24U)
15713 #define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
15714 #define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
15715 #define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
15716 #define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
15717 #define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
15718 
15719 /*******************  Bit definition for TIM_DMAR register  *******************/
15720 #define TIM_DMAR_DMAB_Pos         (0U)
15721 #define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
15722 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
15723 
15724 /******************************************************************************/
15725 /*                                                                            */
15726 /*                         Low Power Timer (LPTIM)                           */
15727 /*                                                                            */
15728 /******************************************************************************/
15729 /******************  Bit definition for LPTIM_ISR register  *******************/
15730 #define LPTIM_ISR_CMPM_Pos          (0U)
15731 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
15732 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
15733 #define LPTIM_ISR_ARRM_Pos          (1U)
15734 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
15735 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
15736 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
15737 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
15738 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
15739 #define LPTIM_ISR_CMPOK_Pos         (3U)
15740 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
15741 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
15742 #define LPTIM_ISR_ARROK_Pos         (4U)
15743 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
15744 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
15745 #define LPTIM_ISR_UP_Pos            (5U)
15746 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
15747 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
15748 #define LPTIM_ISR_DOWN_Pos          (6U)
15749 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
15750 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
15751 
15752 /******************  Bit definition for LPTIM_ICR register  *******************/
15753 #define LPTIM_ICR_CMPMCF_Pos        (0U)
15754 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
15755 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
15756 #define LPTIM_ICR_ARRMCF_Pos        (1U)
15757 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
15758 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
15759 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
15760 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
15761 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
15762 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
15763 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
15764 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
15765 #define LPTIM_ICR_ARROKCF_Pos       (4U)
15766 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
15767 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
15768 #define LPTIM_ICR_UPCF_Pos          (5U)
15769 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
15770 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
15771 #define LPTIM_ICR_DOWNCF_Pos        (6U)
15772 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
15773 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
15774 
15775 /******************  Bit definition for LPTIM_IER register ********************/
15776 #define LPTIM_IER_CMPMIE_Pos        (0U)
15777 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
15778 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
15779 #define LPTIM_IER_ARRMIE_Pos        (1U)
15780 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
15781 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
15782 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
15783 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
15784 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
15785 #define LPTIM_IER_CMPOKIE_Pos       (3U)
15786 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
15787 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
15788 #define LPTIM_IER_ARROKIE_Pos       (4U)
15789 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
15790 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
15791 #define LPTIM_IER_UPIE_Pos          (5U)
15792 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
15793 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
15794 #define LPTIM_IER_DOWNIE_Pos        (6U)
15795 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
15796 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
15797 
15798 /******************  Bit definition for LPTIM_CFGR register *******************/
15799 #define LPTIM_CFGR_CKSEL_Pos        (0U)
15800 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
15801 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
15802 
15803 #define LPTIM_CFGR_CKPOL_Pos        (1U)
15804 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
15805 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
15806 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
15807 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
15808 
15809 #define LPTIM_CFGR_CKFLT_Pos        (3U)
15810 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
15811 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
15812 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
15813 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
15814 
15815 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
15816 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
15817 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
15818 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
15819 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
15820 
15821 #define LPTIM_CFGR_PRESC_Pos        (9U)
15822 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
15823 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
15824 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
15825 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
15826 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
15827 
15828 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
15829 #define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
15830 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
15831 #define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
15832 #define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
15833 #define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
15834 #define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
15835 
15836 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
15837 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
15838 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
15839 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
15840 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
15841 
15842 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
15843 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
15844 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
15845 #define LPTIM_CFGR_WAVE_Pos         (20U)
15846 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
15847 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
15848 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
15849 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
15850 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
15851 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
15852 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
15853 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
15854 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
15855 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
15856 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
15857 #define LPTIM_CFGR_ENC_Pos          (24U)
15858 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
15859 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
15860 
15861 /******************  Bit definition for LPTIM_CR register  ********************/
15862 #define LPTIM_CR_ENABLE_Pos         (0U)
15863 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
15864 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
15865 #define LPTIM_CR_SNGSTRT_Pos        (1U)
15866 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
15867 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
15868 #define LPTIM_CR_CNTSTRT_Pos        (2U)
15869 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
15870 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
15871 #define LPTIM_CR_COUNTRST_Pos       (3U)
15872 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
15873 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
15874 #define LPTIM_CR_RSTARE_Pos         (4U)
15875 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
15876 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
15877 
15878 /******************  Bit definition for LPTIM_CMP register  *******************/
15879 #define LPTIM_CMP_CMP_Pos           (0U)
15880 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
15881 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
15882 
15883 /******************  Bit definition for LPTIM_ARR register  *******************/
15884 #define LPTIM_ARR_ARR_Pos           (0U)
15885 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
15886 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
15887 
15888 /******************  Bit definition for LPTIM_CNT register  *******************/
15889 #define LPTIM_CNT_CNT_Pos           (0U)
15890 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
15891 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
15892 
15893 /******************  Bit definition for LPTIM_OR register  *******************/
15894 #define LPTIM_OR_IN1_Pos             (0U)
15895 #define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
15896 #define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
15897 #define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
15898 #define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
15899 #define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
15900 
15901 #define LPTIM_OR_IN2_Pos             (1U)
15902 #define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
15903 #define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
15904 #define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
15905 #define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
15906 #define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
15907 /******************************************************************************/
15908 /*                                                                            */
15909 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
15910 /*                                                                            */
15911 /******************************************************************************/
15912 /******************  Bit definition for USART_CR1 register  *******************/
15913 #define USART_CR1_UE_Pos             (0U)
15914 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
15915 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
15916 #define USART_CR1_UESM_Pos           (1U)
15917 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
15918 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
15919 #define USART_CR1_RE_Pos             (2U)
15920 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
15921 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
15922 #define USART_CR1_TE_Pos             (3U)
15923 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
15924 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
15925 #define USART_CR1_IDLEIE_Pos         (4U)
15926 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
15927 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
15928 #define USART_CR1_RXNEIE_Pos         (5U)
15929 #define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
15930 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
15931 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
15932 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
15933 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
15934 #define USART_CR1_TCIE_Pos           (6U)
15935 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
15936 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
15937 #define USART_CR1_TXEIE_Pos          (7U)
15938 #define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
15939 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
15940 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
15941 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
15942 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
15943 #define USART_CR1_PEIE_Pos           (8U)
15944 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
15945 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
15946 #define USART_CR1_PS_Pos             (9U)
15947 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
15948 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
15949 #define USART_CR1_PCE_Pos            (10U)
15950 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
15951 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
15952 #define USART_CR1_WAKE_Pos           (11U)
15953 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
15954 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
15955 #define USART_CR1_M_Pos              (12U)
15956 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
15957 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
15958 #define USART_CR1_M0_Pos             (12U)
15959 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
15960 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
15961 #define USART_CR1_MME_Pos            (13U)
15962 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
15963 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
15964 #define USART_CR1_CMIE_Pos           (14U)
15965 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
15966 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
15967 #define USART_CR1_OVER8_Pos          (15U)
15968 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
15969 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
15970 #define USART_CR1_DEDT_Pos           (16U)
15971 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
15972 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
15973 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
15974 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
15975 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
15976 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
15977 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
15978 #define USART_CR1_DEAT_Pos           (21U)
15979 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
15980 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
15981 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
15982 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
15983 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
15984 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
15985 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
15986 #define USART_CR1_RTOIE_Pos          (26U)
15987 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
15988 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
15989 #define USART_CR1_EOBIE_Pos          (27U)
15990 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
15991 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
15992 #define USART_CR1_M1_Pos             (28U)
15993 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
15994 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
15995 #define USART_CR1_FIFOEN_Pos         (29U)
15996 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
15997 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
15998 #define USART_CR1_TXFEIE_Pos         (30U)
15999 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
16000 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
16001 #define USART_CR1_RXFFIE_Pos         (31U)
16002 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
16003 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
16004 
16005 /******************  Bit definition for USART_CR2 register  *******************/
16006 #define USART_CR2_SLVEN_Pos          (0U)
16007 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
16008 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
16009 #define USART_CR2_DIS_NSS_Pos        (3U)
16010 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
16011 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
16012 #define USART_CR2_ADDM7_Pos          (4U)
16013 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
16014 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
16015 #define USART_CR2_LBDL_Pos           (5U)
16016 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
16017 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
16018 #define USART_CR2_LBDIE_Pos          (6U)
16019 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
16020 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
16021 #define USART_CR2_LBCL_Pos           (8U)
16022 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
16023 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
16024 #define USART_CR2_CPHA_Pos           (9U)
16025 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
16026 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
16027 #define USART_CR2_CPOL_Pos           (10U)
16028 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
16029 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
16030 #define USART_CR2_CLKEN_Pos          (11U)
16031 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
16032 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
16033 #define USART_CR2_STOP_Pos           (12U)
16034 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
16035 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
16036 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
16037 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
16038 #define USART_CR2_LINEN_Pos          (14U)
16039 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
16040 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
16041 #define USART_CR2_SWAP_Pos           (15U)
16042 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
16043 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
16044 #define USART_CR2_RXINV_Pos          (16U)
16045 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
16046 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
16047 #define USART_CR2_TXINV_Pos          (17U)
16048 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
16049 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
16050 #define USART_CR2_DATAINV_Pos        (18U)
16051 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
16052 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
16053 #define USART_CR2_MSBFIRST_Pos       (19U)
16054 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
16055 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
16056 #define USART_CR2_ABREN_Pos          (20U)
16057 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
16058 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
16059 #define USART_CR2_ABRMODE_Pos        (21U)
16060 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
16061 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
16062 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
16063 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
16064 #define USART_CR2_RTOEN_Pos          (23U)
16065 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
16066 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
16067 #define USART_CR2_ADD_Pos            (24U)
16068 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
16069 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
16070 
16071 /******************  Bit definition for USART_CR3 register  *******************/
16072 #define USART_CR3_EIE_Pos            (0U)
16073 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
16074 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
16075 #define USART_CR3_IREN_Pos           (1U)
16076 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
16077 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
16078 #define USART_CR3_IRLP_Pos           (2U)
16079 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
16080 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
16081 #define USART_CR3_HDSEL_Pos          (3U)
16082 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
16083 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
16084 #define USART_CR3_NACK_Pos           (4U)
16085 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
16086 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
16087 #define USART_CR3_SCEN_Pos           (5U)
16088 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
16089 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
16090 #define USART_CR3_DMAR_Pos           (6U)
16091 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
16092 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
16093 #define USART_CR3_DMAT_Pos           (7U)
16094 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
16095 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
16096 #define USART_CR3_RTSE_Pos           (8U)
16097 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
16098 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
16099 #define USART_CR3_CTSE_Pos           (9U)
16100 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
16101 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
16102 #define USART_CR3_CTSIE_Pos          (10U)
16103 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
16104 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
16105 #define USART_CR3_ONEBIT_Pos         (11U)
16106 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
16107 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
16108 #define USART_CR3_OVRDIS_Pos         (12U)
16109 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
16110 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
16111 #define USART_CR3_DDRE_Pos           (13U)
16112 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
16113 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
16114 #define USART_CR3_DEM_Pos            (14U)
16115 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
16116 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
16117 #define USART_CR3_DEP_Pos            (15U)
16118 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
16119 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
16120 #define USART_CR3_SCARCNT_Pos        (17U)
16121 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
16122 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
16123 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
16124 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
16125 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
16126 #define USART_CR3_WUS_Pos            (20U)
16127 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
16128 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
16129 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
16130 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
16131 #define USART_CR3_WUFIE_Pos          (22U)
16132 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
16133 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
16134 #define USART_CR3_TXFTIE_Pos         (23U)
16135 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
16136 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
16137 #define USART_CR3_TCBGTIE_Pos        (24U)
16138 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
16139 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
16140 #define USART_CR3_RXFTCFG_Pos        (25U)
16141 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
16142 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
16143 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
16144 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
16145 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
16146 #define USART_CR3_RXFTIE_Pos         (28U)
16147 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
16148 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
16149 #define USART_CR3_TXFTCFG_Pos        (29U)
16150 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
16151 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
16152 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
16153 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
16154 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
16155 
16156 /******************  Bit definition for USART_BRR register  *******************/
16157 #define USART_BRR_LPUART_Pos         (0U)
16158 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
16159 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
16160 #define USART_BRR_BRR_Pos            (0U)
16161 #define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
16162 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
16163 
16164 /******************  Bit definition for USART_GTPR register  ******************/
16165 #define USART_GTPR_PSC_Pos           (0U)
16166 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
16167 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
16168 #define USART_GTPR_GT_Pos            (8U)
16169 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
16170 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
16171 
16172 /*******************  Bit definition for USART_RTOR register  *****************/
16173 #define USART_RTOR_RTO_Pos           (0U)
16174 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
16175 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
16176 #define USART_RTOR_BLEN_Pos          (24U)
16177 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
16178 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
16179 
16180 /*******************  Bit definition for USART_RQR register  ******************/
16181 #define USART_RQR_ABRRQ_Pos          (0U)
16182 #define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
16183 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
16184 #define USART_RQR_SBKRQ_Pos          (1U)
16185 #define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
16186 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
16187 #define USART_RQR_MMRQ_Pos           (2U)
16188 #define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
16189 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
16190 #define USART_RQR_RXFRQ_Pos          (3U)
16191 #define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
16192 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
16193 #define USART_RQR_TXFRQ_Pos          (4U)
16194 #define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
16195 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
16196 
16197 /*******************  Bit definition for USART_ISR register  ******************/
16198 #define USART_ISR_PE_Pos             (0U)
16199 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
16200 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
16201 #define USART_ISR_FE_Pos             (1U)
16202 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
16203 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
16204 #define USART_ISR_NE_Pos             (2U)
16205 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
16206 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
16207 #define USART_ISR_ORE_Pos            (3U)
16208 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
16209 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
16210 #define USART_ISR_IDLE_Pos           (4U)
16211 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
16212 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
16213 #define USART_ISR_RXNE_Pos           (5U)
16214 #define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
16215 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
16216 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
16217 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
16218 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
16219 #define USART_ISR_TC_Pos             (6U)
16220 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
16221 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
16222 #define USART_ISR_TXE_Pos            (7U)
16223 #define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
16224 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
16225 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
16226 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
16227 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
16228 #define USART_ISR_LBDF_Pos           (8U)
16229 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
16230 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
16231 #define USART_ISR_CTSIF_Pos          (9U)
16232 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
16233 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
16234 #define USART_ISR_CTS_Pos            (10U)
16235 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
16236 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
16237 #define USART_ISR_RTOF_Pos           (11U)
16238 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
16239 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
16240 #define USART_ISR_EOBF_Pos           (12U)
16241 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
16242 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
16243 #define USART_ISR_UDR_Pos            (13U)
16244 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
16245 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
16246 #define USART_ISR_ABRE_Pos           (14U)
16247 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
16248 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
16249 #define USART_ISR_ABRF_Pos           (15U)
16250 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
16251 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
16252 #define USART_ISR_BUSY_Pos           (16U)
16253 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
16254 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
16255 #define USART_ISR_CMF_Pos            (17U)
16256 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
16257 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
16258 #define USART_ISR_SBKF_Pos           (18U)
16259 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
16260 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
16261 #define USART_ISR_RWU_Pos            (19U)
16262 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
16263 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
16264 #define USART_ISR_WUF_Pos            (20U)
16265 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
16266 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
16267 #define USART_ISR_TEACK_Pos          (21U)
16268 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
16269 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
16270 #define USART_ISR_REACK_Pos          (22U)
16271 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
16272 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
16273 #define USART_ISR_TXFE_Pos           (23U)
16274 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
16275 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
16276 #define USART_ISR_RXFF_Pos           (24U)
16277 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
16278 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
16279 #define USART_ISR_TCBGT_Pos          (25U)
16280 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
16281 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
16282 #define USART_ISR_RXFT_Pos           (26U)
16283 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
16284 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
16285 #define USART_ISR_TXFT_Pos           (27U)
16286 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
16287 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
16288 
16289 /*******************  Bit definition for USART_ICR register  ******************/
16290 #define USART_ICR_PECF_Pos           (0U)
16291 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
16292 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
16293 #define USART_ICR_FECF_Pos           (1U)
16294 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
16295 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
16296 #define USART_ICR_NECF_Pos           (2U)
16297 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
16298 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
16299 #define USART_ICR_ORECF_Pos          (3U)
16300 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
16301 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
16302 #define USART_ICR_IDLECF_Pos         (4U)
16303 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
16304 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
16305 #define USART_ICR_TXFECF_Pos         (5U)
16306 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
16307 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
16308 #define USART_ICR_TCCF_Pos           (6U)
16309 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
16310 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
16311 #define USART_ICR_TCBGTCF_Pos        (7U)
16312 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
16313 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
16314 #define USART_ICR_LBDCF_Pos          (8U)
16315 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
16316 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
16317 #define USART_ICR_CTSCF_Pos          (9U)
16318 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
16319 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
16320 #define USART_ICR_RTOCF_Pos          (11U)
16321 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
16322 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
16323 #define USART_ICR_EOBCF_Pos          (12U)
16324 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
16325 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
16326 #define USART_ICR_UDRCF_Pos          (13U)
16327 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
16328 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
16329 #define USART_ICR_CMCF_Pos           (17U)
16330 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
16331 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
16332 #define USART_ICR_WUCF_Pos           (20U)
16333 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
16334 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
16335 
16336 /*******************  Bit definition for USART_RDR register  ******************/
16337 #define USART_RDR_RDR_Pos            (0U)
16338 #define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
16339 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
16340 
16341 /*******************  Bit definition for USART_TDR register  ******************/
16342 #define USART_TDR_TDR_Pos            (0U)
16343 #define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
16344 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
16345 
16346 /*******************  Bit definition for USART_PRESC register  ****************/
16347 #define USART_PRESC_PRESCALER_Pos    (0U)
16348 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
16349 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
16350 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
16351 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
16352 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
16353 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
16354 
16355 /******************************************************************************/
16356 /*                                                                            */
16357 /*                                 VREFBUF                                    */
16358 /*                                                                            */
16359 /******************************************************************************/
16360 /*******************  Bit definition for VREFBUF_CSR register  ****************/
16361 #define VREFBUF_CSR_ENVR_Pos    (0U)
16362 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
16363 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
16364 #define VREFBUF_CSR_HIZ_Pos     (1U)
16365 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
16366 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
16367 #define VREFBUF_CSR_VRR_Pos     (3U)
16368 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
16369 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
16370 #define VREFBUF_CSR_VRS_Pos     (4U)
16371 #define VREFBUF_CSR_VRS_Msk     (0x3UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000030 */
16372 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<VRS[5:0] bits (Voltage reference scale) */
16373 #define VREFBUF_CSR_VRS_0       (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000010 */
16374 #define VREFBUF_CSR_VRS_1       (0x2UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000020 */
16375 
16376 /*******************  Bit definition for VREFBUF_CCR register  ******************/
16377 #define VREFBUF_CCR_TRIM_Pos    (0U)
16378 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
16379 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
16380 
16381 /******************************************************************************/
16382 /*                                                                            */
16383 /*                         USB Device FS Endpoint registers                   */
16384 /*                                                                            */
16385 /******************************************************************************/
16386 #define USB_EP0R                             USB_BASE                    /*!< endpoint 0 register address */
16387 #define USB_EP1R                             (USB_BASE + 0x0x00000004)   /*!< endpoint 1 register address */
16388 #define USB_EP2R                             (USB_BASE + 0x0x00000008)   /*!< endpoint 2 register address */
16389 #define USB_EP3R                             (USB_BASE + 0x0x0000000C)   /*!< endpoint 3 register address */
16390 #define USB_EP4R                             (USB_BASE + 0x0x00000010)   /*!< endpoint 4 register address */
16391 #define USB_EP5R                             (USB_BASE + 0x0x00000014)   /*!< endpoint 5 register address */
16392 #define USB_EP6R                             (USB_BASE + 0x0x00000018)   /*!< endpoint 6 register address */
16393 #define USB_EP7R                             (USB_BASE + 0x0x0000001C)   /*!< endpoint 7 register address */
16394 
16395 /* bit positions */
16396 #define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
16397 #define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
16398 #define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
16399 #define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
16400 #define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
16401 #define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
16402 #define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
16403 #define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
16404 #define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
16405 #define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
16406 
16407 /* EndPoint REGister MASK (no toggle fields) */
16408 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
16409                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
16410 #define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
16411 #define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
16412 #define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
16413 #define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
16414 #define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
16415 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
16416 
16417 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
16418                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
16419 #define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
16420 #define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
16421 #define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
16422 #define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
16423 #define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
16424 #define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
16425 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
16426                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
16427 #define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
16428 #define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
16429 #define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
16430 #define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
16431 #define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
16432 #define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
16433 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
16434 
16435 /******************************************************************************/
16436 /*                                                                            */
16437 /*                         USB Device FS General registers                    */
16438 /*                                                                            */
16439 /******************************************************************************/
16440 #define USB_CNTR                             (USB_BASE + 0x00000040U)     /*!< Control register */
16441 #define USB_ISTR                             (USB_BASE + 0x00000044U)     /*!< Interrupt status register */
16442 #define USB_FNR                              (USB_BASE + 0x00000048U)     /*!< Frame number register */
16443 #define USB_DADDR                            (USB_BASE + 0x0000004CU)     /*!< Device address register */
16444 #define USB_BTABLE                           (USB_BASE + 0x00000050U)     /*!< Buffer Table address register */
16445 #define USB_LPMCSR                           (USB_BASE + 0x00000054U)     /*!< LPM Control and Status register */
16446 #define USB_BCDR                             (USB_BASE + 0x00000058U)     /*!< Battery Charging detector register*/
16447 
16448 /******************  Bits definition for USB_CNTR register  *******************/
16449 #define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
16450 #define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
16451 #define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
16452 #define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
16453 #define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
16454 #define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
16455 #define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
16456 #define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
16457 #define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
16458 #define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
16459 #define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
16460 #define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
16461 #define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
16462 #define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
16463 #define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
16464 
16465 /******************  Bits definition for USB_ISTR register  *******************/
16466 #define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
16467 #define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
16468 #define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
16469 #define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
16470 #define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
16471 #define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
16472 #define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
16473 #define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
16474 #define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
16475 #define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
16476 #define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
16477 
16478 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
16479 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
16480 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
16481 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
16482 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
16483 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
16484 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
16485 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
16486 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
16487 
16488 /******************  Bits definition for USB_FNR register  ********************/
16489 #define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
16490 #define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
16491 #define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
16492 #define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
16493 #define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
16494 
16495 /******************  Bits definition for USB_DADDR register    ****************/
16496 #define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
16497 #define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
16498 #define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
16499 #define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
16500 #define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
16501 #define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
16502 #define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
16503 #define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
16504 
16505 #define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
16506 
16507 /******************  Bit definition for USB_BTABLE register  ******************/
16508 #define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
16509 
16510 /******************  Bits definition for USB_BCDR register  *******************/
16511 #define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
16512 #define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
16513 #define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
16514 #define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
16515 #define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
16516 #define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
16517 #define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
16518 #define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
16519 #define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
16520 
16521 /*******************  Bit definition for LPMCSR register  *********************/
16522 #define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
16523 #define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
16524 #define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
16525 #define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
16526 
16527 /*!< Buffer descriptor table */
16528 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
16529 #define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
16530 #define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
16531 #define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
16532 
16533 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
16534 #define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
16535 #define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
16536 #define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
16537 
16538 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
16539 #define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
16540 #define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
16541 #define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
16542 
16543 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
16544 #define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
16545 #define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
16546 #define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
16547 
16548 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
16549 #define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
16550 #define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
16551 #define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
16552 
16553 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
16554 #define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
16555 #define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
16556 #define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
16557 
16558 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
16559 #define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
16560 #define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
16561 #define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
16562 
16563 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
16564 #define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
16565 #define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
16566 #define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
16567 
16568 /*----------------------------------------------------------------------------*/
16569 
16570 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
16571 #define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
16572 #define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
16573 #define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
16574 
16575 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
16576 #define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
16577 #define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
16578 #define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
16579 
16580 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
16581 #define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
16582 #define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
16583 #define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
16584 
16585 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
16586 #define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
16587 #define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
16588 #define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
16589 
16590 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
16591 #define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
16592 #define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
16593 #define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
16594 
16595 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
16596 #define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
16597 #define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
16598 #define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
16599 
16600 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
16601 #define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
16602 #define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
16603 #define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
16604 
16605 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
16606 #define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
16607 #define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
16608 #define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
16609 
16610 /*----------------------------------------------------------------------------*/
16611 
16612 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
16613 #define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 0 (low) */
16614 
16615 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
16616 #define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 0 (high) */
16617 
16618 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
16619 #define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 1 (low) */
16620 
16621 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
16622 #define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 1 (high) */
16623 
16624 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
16625 #define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 2 (low) */
16626 
16627 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
16628 #define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 2 (high) */
16629 
16630 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
16631 #define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 3 (low) */
16632 
16633 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
16634 #define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 3 (high) */
16635 
16636 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
16637 #define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 4 (low) */
16638 
16639 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
16640 #define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 4 (high) */
16641 
16642 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
16643 #define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 5 (low) */
16644 
16645 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
16646 #define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 5 (high) */
16647 
16648 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
16649 #define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 6 (low) */
16650 
16651 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
16652 #define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 6 (high) */
16653 
16654 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
16655 #define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFU)        /*!< Transmission Byte Count 7 (low) */
16656 
16657 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
16658 #define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000U)        /*!< Transmission Byte Count 7 (high) */
16659 
16660 /*----------------------------------------------------------------------------*/
16661 
16662 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
16663 #define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
16664 #define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
16665 #define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
16666 
16667 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
16668 #define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
16669 #define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
16670 #define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
16671 
16672 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
16673 #define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
16674 #define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
16675 #define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
16676 
16677 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
16678 #define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
16679 #define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
16680 #define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
16681 
16682 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
16683 #define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
16684 #define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
16685 #define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
16686 
16687 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
16688 #define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
16689 #define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
16690 #define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
16691 
16692 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
16693 #define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
16694 #define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
16695 #define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
16696 
16697 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
16698 #define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
16699 #define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
16700 #define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
16701 
16702 /*----------------------------------------------------------------------------*/
16703 
16704 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
16705 #define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
16706 #define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
16707 #define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
16708 
16709 #define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
16710 #define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16711 #define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16712 #define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16713 #define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16714 #define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16715 #define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16716 #define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16717 
16718 #define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
16719 #define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
16720 #define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
16721 
16722 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
16723 #define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
16724 #define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
16725 #define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
16726 
16727 #define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
16728 #define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16729 #define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16730 #define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16731 #define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16732 #define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16733 #define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16734 #define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16735 
16736 #define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
16737 #define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
16738 #define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
16739 
16740 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
16741 #define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
16742 #define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
16743 #define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
16744 
16745 #define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
16746 #define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16747 #define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16748 #define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16749 #define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16750 #define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16751 #define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16752 #define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16753 
16754 #define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
16755 #define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
16756 #define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
16757 
16758 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
16759 #define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
16760 #define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
16761 #define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
16762 
16763 #define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
16764 #define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16765 #define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16766 #define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16767 #define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16768 #define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16769 #define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16770 #define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16771 
16772 #define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
16773 #define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
16774 #define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
16775 
16776 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
16777 #define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
16778 #define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
16779 #define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
16780 
16781 #define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
16782 #define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16783 #define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16784 #define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16785 #define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16786 #define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16787 #define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16788 #define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16789 
16790 #define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
16791 #define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
16792 #define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
16793 
16794 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
16795 #define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
16796 #define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
16797 #define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
16798 
16799 #define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
16800 #define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16801 #define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16802 #define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16803 #define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16804 #define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16805 #define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16806 #define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16807 
16808 #define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
16809 #define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
16810 #define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
16811 
16812 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
16813 #define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
16814 #define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
16815 #define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
16816 
16817 #define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
16818 #define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16819 #define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16820 #define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16821 #define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16822 #define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16823 #define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16824 #define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16825 
16826 #define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
16827 #define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
16828 #define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
16829 
16830 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
16831 #define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
16832 #define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
16833 #define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
16834 
16835 #define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
16836 #define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
16837 #define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
16838 #define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
16839 #define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
16840 #define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
16841 #define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
16842 #define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
16843 
16844 #define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
16845 #define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
16846 #define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
16847 
16848 /*----------------------------------------------------------------------------*/
16849 
16850 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
16851 #define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16852 
16853 #define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16854 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16855 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16856 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16857 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16858 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16859 
16860 #define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16861 
16862 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
16863 #define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16864 
16865 #define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16866 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 1 */
16867 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16868 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16869 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16870 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16871 
16872 #define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16873 
16874 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
16875 #define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16876 
16877 #define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16878 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16879 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16880 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16881 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16882 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16883 
16884 #define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16885 
16886 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
16887 #define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16888 
16889 #define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16890 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
16891 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16892 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16893 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16894 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16895 
16896 #define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16897 
16898 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
16899 #define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16900 
16901 #define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16902 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16903 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16904 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16905 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16906 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16907 
16908 #define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16909 
16910 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
16911 #define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16912 
16913 #define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16914 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
16915 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16916 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16917 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16918 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16919 
16920 #define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16921 
16922 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
16923 #define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16924 
16925 #define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16926 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16927 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16928 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16929 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16930 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16931 
16932 #define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16933 
16934 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
16935 #define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16936 
16937 #define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16938 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
16939 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16940 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16941 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16942 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16943 
16944 #define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16945 
16946 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
16947 #define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16948 
16949 #define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16950 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16951 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16952 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16953 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16954 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16955 
16956 #define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16957 
16958 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
16959 #define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16960 
16961 #define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16962 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
16963 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16964 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16965 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16966 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16967 
16968 #define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16969 
16970 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
16971 #define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16972 
16973 #define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16974 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16975 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
16976 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
16977 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
16978 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
16979 
16980 #define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
16981 
16982 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
16983 #define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
16984 
16985 #define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
16986 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
16987 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
16988 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
16989 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
16990 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
16991 
16992 #define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
16993 
16994 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
16995 #define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
16996 
16997 #define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
16998 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
16999 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
17000 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
17001 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
17002 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
17003 
17004 #define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
17005 
17006 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
17007 #define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
17008 
17009 #define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
17010 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
17011 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
17012 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
17013 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
17014 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
17015 
17016 #define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
17017 
17018 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
17019 #define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFU)           /*!< Reception Byte Count (low) */
17020 
17021 #define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00U)           /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
17022 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400U)           /*!< Bit 0 */
17023 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800U)           /*!< Bit 1 */
17024 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000U)           /*!< Bit 2 */
17025 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000U)           /*!< Bit 3 */
17026 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000U)           /*!< Bit 4 */
17027 
17028 #define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000U)           /*!< BLock SIZE (low) */
17029 
17030 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
17031 #define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000U)           /*!< Reception Byte Count (high) */
17032 
17033 #define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000U)           /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
17034 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000U)           /*!< Bit 0 */
17035 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000U)           /*!< Bit 1 */
17036 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000U)           /*!< Bit 2 */
17037 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000U)           /*!< Bit 3 */
17038 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000U)           /*!< Bit 4 */
17039 
17040 #define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000U)           /*!< BLock SIZE (high) */
17041 
17042 /******************************************************************************/
17043 /*                                                                            */
17044 /*                                    UCPD                                    */
17045 /*                                                                            */
17046 /******************************************************************************/
17047 /********************  Bits definition for UCPD_CFG1 register  *******************/
17048 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
17049 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
17050 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
17051 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
17052 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
17053 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
17054 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
17055 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
17056 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
17057 #define UCPD_CFG1_IFRGAP_Pos                (6U)
17058 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
17059 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
17060 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
17061 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
17062 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
17063 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
17064 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
17065 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
17066 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
17067 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
17068 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
17069 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
17070 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
17071 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
17072 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
17073 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
17074 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
17075 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
17076 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
17077 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
17078 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
17079 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
17080 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
17081 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
17082 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
17083 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
17084 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
17085 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
17086 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
17087 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
17088 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
17089 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
17090 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
17091 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
17092 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
17093 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
17094 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
17095 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
17096 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
17097 #define UCPD_CFG1_UCPDEN_Pos                (31U)
17098 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
17099 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
17100 
17101 /********************  Bits definition for UCPD_CFG2 register  *******************/
17102 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
17103 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
17104 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
17105 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
17106 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
17107 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
17108 #define UCPD_CFG2_FORCECLK_Pos              (2U)
17109 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
17110 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
17111 #define UCPD_CFG2_WUPEN_Pos                 (3U)
17112 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
17113 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
17114 
17115 /********************  Bits definition for UCPD_CR register  ********************/
17116 #define UCPD_CR_TXMODE_Pos                  (0U)
17117 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
17118 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
17119 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
17120 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
17121 #define UCPD_CR_TXSEND_Pos                  (2U)
17122 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
17123 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
17124 #define UCPD_CR_TXHRST_Pos                  (3U)
17125 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
17126 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
17127 #define UCPD_CR_RXMODE_Pos                  (4U)
17128 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
17129 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
17130 #define UCPD_CR_PHYRXEN_Pos                 (5U)
17131 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
17132 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
17133 #define UCPD_CR_PHYCCSEL_Pos                (6U)
17134 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
17135 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
17136 #define UCPD_CR_ANASUBMODE_Pos              (7U)
17137 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
17138 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
17139 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
17140 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
17141 #define UCPD_CR_ANAMODE_Pos                 (9U)
17142 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
17143 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
17144 #define UCPD_CR_CCENABLE_Pos                (10U)
17145 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
17146 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
17147 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
17148 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
17149 #define UCPD_CR_FRSRXEN_Pos                 (16U)
17150 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)       /*!< 0x00010000 */
17151 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                  /*!< Enable FRS request detection function */
17152 #define UCPD_CR_FRSTX_Pos                   (17U)
17153 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
17154 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
17155 #define UCPD_CR_RDCH_Pos                    (18U)
17156 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
17157 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
17158 #define UCPD_CR_CC1TCDIS_Pos                (20U)
17159 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
17160 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
17161 #define UCPD_CR_CC2TCDIS_Pos                (21U)
17162 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
17163 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
17164 
17165 /********************  Bits definition for UCPD_IMR register  *******************/
17166 #define UCPD_IMR_TXISIE_Pos                 (0U)
17167 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
17168 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
17169 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
17170 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
17171 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
17172 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
17173 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
17174 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
17175 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
17176 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
17177 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
17178 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
17179 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
17180 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
17181 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
17182 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
17183 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
17184 #define UCPD_IMR_TXUNDIE_Pos                (6U)
17185 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
17186 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
17187 #define UCPD_IMR_RXNEIE_Pos                 (8U)
17188 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
17189 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
17190 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
17191 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
17192 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
17193 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
17194 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
17195 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
17196 #define UCPD_IMR_RXOVRIE_Pos                (11U)
17197 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
17198 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
17199 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
17200 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
17201 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
17202 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
17203 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
17204 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
17205 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
17206 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
17207 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
17208 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
17209 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)     /*!< 0x00100000 */
17210 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                /*!< Fast Role Swap interrupt  */
17211 
17212 /********************  Bits definition for UCPD_SR register  ********************/
17213 #define UCPD_SR_TXIS_Pos                    (0U)
17214 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
17215 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
17216 #define UCPD_SR_TXMSGDISC_Pos               (1U)
17217 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
17218 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
17219 #define UCPD_SR_TXMSGSENT_Pos               (2U)
17220 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
17221 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
17222 #define UCPD_SR_TXMSGABT_Pos                (3U)
17223 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
17224 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
17225 #define UCPD_SR_HRSTDISC_Pos                (4U)
17226 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
17227 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
17228 #define UCPD_SR_HRSTSENT_Pos                (5U)
17229 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
17230 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
17231 #define UCPD_SR_TXUND_Pos                   (6U)
17232 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
17233 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
17234 #define UCPD_SR_RXNE_Pos                    (8U)
17235 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
17236 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
17237 #define UCPD_SR_RXORDDET_Pos                (9U)
17238 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
17239 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
17240 #define UCPD_SR_RXHRSTDET_Pos               (10U)
17241 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
17242 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
17243 #define UCPD_SR_RXOVR_Pos                   (11U)
17244 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
17245 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
17246 #define UCPD_SR_RXMSGEND_Pos                (12U)
17247 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
17248 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
17249 #define UCPD_SR_RXERR_Pos                   (13U)
17250 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
17251 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
17252 #define UCPD_SR_TYPECEVT1_Pos               (14U)
17253 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
17254 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
17255 #define UCPD_SR_TYPECEVT2_Pos               (15U)
17256 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
17257 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
17258 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
17259 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
17260 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
17261 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
17262 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
17263 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
17264 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
17265 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
17266 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
17267 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
17268 #define UCPD_SR_FRSEVT_Pos                  (20U)
17269 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)        /*!< 0x00100000 */
17270 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                   /*!< Fast Role Swap detection event  */
17271 
17272 /********************  Bits definition for UCPD_ICR register  *******************/
17273 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
17274 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
17275 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
17276 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
17277 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
17278 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
17279 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
17280 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
17281 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
17282 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
17283 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
17284 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
17285 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
17286 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
17287 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
17288 #define UCPD_ICR_TXUNDCF_Pos                (6U)
17289 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
17290 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
17291 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
17292 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
17293 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
17294 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
17295 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
17296 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
17297 #define UCPD_ICR_RXOVRCF_Pos                (11U)
17298 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
17299 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
17300 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
17301 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
17302 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
17303 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
17304 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
17305 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
17306 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
17307 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
17308 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
17309 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
17310 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)     /*!< 0x00100000 */
17311 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                /*!< Fast Role Swap event flag clear  */
17312 
17313 /********************  Bits definition for UCPD_TXORDSET register  **************/
17314 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
17315 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
17316 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
17317 
17318 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
17319 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
17320 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
17321 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
17322 
17323 /********************  Bits definition for UCPD_TXDR register  *******************/
17324 #define UCPD_TXDR_TXDATA_Pos                (0U)
17325 #define UCPD_TXDR_TXDATA_Msk                 (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
17326 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                  /*!< Tx Data Register */
17327 
17328 /********************  Bits definition for UCPD_RXORDSET register  **************/
17329 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
17330 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
17331 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
17332 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
17333 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
17334 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
17335 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
17336 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
17337 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
17338 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
17339 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
17340 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
17341 
17342 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
17343 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
17344 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
17345 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
17346 
17347 /********************  Bits definition for UCPD_RXDR register  *******************/
17348 #define UCPD_RXDR_RXDATA_Pos                (0U)
17349 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
17350 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
17351 
17352 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
17353 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
17354 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
17355 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
17356 
17357 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
17358 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
17359 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
17360 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
17361 
17362 /******************************************************************************/
17363 /*                                                                            */
17364 /*                            Window WATCHDOG                                 */
17365 /*                                                                            */
17366 /******************************************************************************/
17367 /*******************  Bit definition for WWDG_CR register  ********************/
17368 #define WWDG_CR_T_Pos           (0U)
17369 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
17370 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17371 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
17372 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
17373 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
17374 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
17375 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
17376 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
17377 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
17378 
17379 #define WWDG_CR_WDGA_Pos        (7U)
17380 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
17381 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
17382 
17383 /*******************  Bit definition for WWDG_CFR register  *******************/
17384 #define WWDG_CFR_W_Pos          (0U)
17385 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
17386 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
17387 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
17388 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
17389 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
17390 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
17391 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
17392 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
17393 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
17394 
17395 #define WWDG_CFR_WDGTB_Pos      (11U)
17396 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
17397 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
17398 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
17399 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
17400 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
17401 
17402 #define WWDG_CFR_EWI_Pos        (9U)
17403 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
17404 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
17405 
17406 /*******************  Bit definition for WWDG_SR register  ********************/
17407 #define WWDG_SR_EWIF_Pos        (0U)
17408 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
17409 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
17410 
17411 /**
17412   * @}
17413   */
17414 
17415 /**
17416   * @}
17417   */
17418 
17419 /** @addtogroup Exported_macros
17420   * @{
17421   */
17422 
17423 /******************************* ADC Instances ********************************/
17424 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17425                                        ((INSTANCE) == ADC2) || \
17426                                        ((INSTANCE) == ADC3) || \
17427                                        ((INSTANCE) == ADC4) || \
17428                                        ((INSTANCE) == ADC5))
17429 
17430 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17431                                                     ((INSTANCE) == ADC3))
17432 
17433 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
17434                                           ((INSTANCE) == ADC345_COMMON) )
17435 
17436 
17437 /******************************** FDCAN Instances ******************************/
17438 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
17439                                          ((INSTANCE) == FDCAN2) || \
17440                                          ((INSTANCE) == FDCAN3))
17441 
17442 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
17443 /******************************** COMP Instances ******************************/
17444 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
17445                                         ((INSTANCE) == COMP2) || \
17446                                         ((INSTANCE) == COMP3) || \
17447                                         ((INSTANCE) == COMP4) || \
17448                                         ((INSTANCE) == COMP5) || \
17449                                         ((INSTANCE) == COMP6) || \
17450                                         ((INSTANCE) == COMP7))
17451 
17452 /******************************* CORDIC Instances *****************************/
17453 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
17454 
17455 /******************************* CRC Instances ********************************/
17456 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
17457 
17458 /******************************* DAC Instances ********************************/
17459 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
17460                                        ((INSTANCE) == DAC2) || \
17461                                        ((INSTANCE) == DAC3) || \
17462                                        ((INSTANCE) == DAC4))
17463 
17464 
17465 /******************************** DMA Instances *******************************/
17466 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
17467                                        ((INSTANCE) == DMA1_Channel2) || \
17468                                        ((INSTANCE) == DMA1_Channel3) || \
17469                                        ((INSTANCE) == DMA1_Channel4) || \
17470                                        ((INSTANCE) == DMA1_Channel5) || \
17471                                        ((INSTANCE) == DMA1_Channel6) || \
17472                                        ((INSTANCE) == DMA1_Channel7) || \
17473                                        ((INSTANCE) == DMA1_Channel8) || \
17474                                        ((INSTANCE) == DMA2_Channel1) || \
17475                                        ((INSTANCE) == DMA2_Channel2) || \
17476                                        ((INSTANCE) == DMA2_Channel3) || \
17477                                        ((INSTANCE) == DMA2_Channel4) || \
17478                                        ((INSTANCE) == DMA2_Channel5) || \
17479                                        ((INSTANCE) == DMA2_Channel6) || \
17480                                        ((INSTANCE) == DMA2_Channel7) || \
17481                                        ((INSTANCE) == DMA2_Channel8))
17482 
17483 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
17484                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
17485                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
17486                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
17487 
17488 /******************************* FMAC Instances *******************************/
17489 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
17490 
17491 /******************************* GPIO Instances *******************************/
17492 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
17493                                         ((INSTANCE) == GPIOB) || \
17494                                         ((INSTANCE) == GPIOC) || \
17495                                         ((INSTANCE) == GPIOD) || \
17496                                         ((INSTANCE) == GPIOE) || \
17497                                         ((INSTANCE) == GPIOF) || \
17498                                         ((INSTANCE) == GPIOG))
17499 
17500 /******************************* GPIO AF Instances ****************************/
17501 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
17502 
17503 /**************************** GPIO Lock Instances *****************************/
17504 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17505 
17506 /******************************** I2C Instances *******************************/
17507 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17508                                        ((INSTANCE) == I2C2) || \
17509                                        ((INSTANCE) == I2C3) || \
17510                                        ((INSTANCE) == I2C4))
17511 
17512 /****************** I2C Instances : wakeup capability from stop modes *********/
17513 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
17514 
17515 /****************************** OPAMP Instances *******************************/
17516 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
17517                                          ((INSTANCE) == OPAMP2) || \
17518                                          ((INSTANCE) == OPAMP3) || \
17519                                          ((INSTANCE) == OPAMP4) || \
17520                                          ((INSTANCE) == OPAMP5) || \
17521                                          ((INSTANCE) == OPAMP6))
17522 
17523 /******************************** PCD Instances *******************************/
17524 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
17525 
17526 /******************************* QSPI Instances *******************************/
17527 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
17528 
17529 /******************************* RNG Instances ********************************/
17530 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
17531 
17532 /****************************** RTC Instances *********************************/
17533 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
17534 
17535 #define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
17536 
17537 /****************************** SMBUS Instances *******************************/
17538 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17539                                          ((INSTANCE) == I2C2) || \
17540                                          ((INSTANCE) == I2C3) || \
17541                                          ((INSTANCE) == I2C4))
17542 
17543 /******************************** SAI Instances *******************************/
17544 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
17545 
17546 /******************************** SPI Instances *******************************/
17547 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
17548                                        ((INSTANCE) == SPI2) || \
17549                                        ((INSTANCE) == SPI3) || \
17550                                        ((INSTANCE) == SPI4))
17551 
17552 /******************************** I2S Instances *******************************/
17553 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI2) || \
17554                                             ((__INSTANCE__) == SPI3))
17555 
17556 /****************** LPTIM Instances : All supported instances *****************/
17557 #define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
17558 
17559 /****************** LPTIM Instances : supporting encoder interface **************/
17560 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
17561 
17562 /****************** LPTIM Instances : All supported instances *****************/
17563 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
17564 
17565 /****************** TIM Instances : All supported instances *******************/
17566 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
17567                                          ((INSTANCE) == TIM2)   || \
17568                                          ((INSTANCE) == TIM3)   || \
17569                                          ((INSTANCE) == TIM4)   || \
17570                                          ((INSTANCE) == TIM5)   || \
17571                                          ((INSTANCE) == TIM6)   || \
17572                                          ((INSTANCE) == TIM7)   || \
17573                                          ((INSTANCE) == TIM8)   || \
17574                                          ((INSTANCE) == TIM15)  || \
17575                                          ((INSTANCE) == TIM16)  || \
17576                                          ((INSTANCE) == TIM17)  || \
17577                                          ((INSTANCE) == TIM20))
17578 
17579 /****************** TIM Instances : supporting 32 bits counter ****************/
17580 
17581 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
17582                                                ((INSTANCE) == TIM5))
17583 
17584 /****************** TIM Instances : supporting the break function *************/
17585 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
17586                                             ((INSTANCE) == TIM8)    || \
17587                                             ((INSTANCE) == TIM15)   || \
17588                                             ((INSTANCE) == TIM16)   || \
17589                                             ((INSTANCE) == TIM17)   || \
17590                                             ((INSTANCE) == TIM20))
17591 
17592 /************** TIM Instances : supporting Break source selection *************/
17593 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17594                                                ((INSTANCE) == TIM8)   || \
17595                                                ((INSTANCE) == TIM15)  || \
17596                                                ((INSTANCE) == TIM16)  || \
17597                                                ((INSTANCE) == TIM17)  || \
17598                                                ((INSTANCE) == TIM20))
17599 
17600 /****************** TIM Instances : supporting 2 break inputs *****************/
17601 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
17602                                             ((INSTANCE) == TIM8)    || \
17603                                             ((INSTANCE) == TIM20))
17604 
17605 /************* TIM Instances : at least 1 capture/compare channel *************/
17606 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17607                                          ((INSTANCE) == TIM2)   || \
17608                                          ((INSTANCE) == TIM3)   || \
17609                                          ((INSTANCE) == TIM4)   || \
17610                                          ((INSTANCE) == TIM5)   || \
17611                                          ((INSTANCE) == TIM8)   || \
17612                                          ((INSTANCE) == TIM15)  || \
17613                                          ((INSTANCE) == TIM16)  || \
17614                                          ((INSTANCE) == TIM17)  || \
17615                                          ((INSTANCE) == TIM20))
17616 
17617 /************ TIM Instances : at least 2 capture/compare channels *************/
17618 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17619                                          ((INSTANCE) == TIM2)   || \
17620                                          ((INSTANCE) == TIM3)   || \
17621                                          ((INSTANCE) == TIM4)   || \
17622                                          ((INSTANCE) == TIM5)   || \
17623                                          ((INSTANCE) == TIM8)   || \
17624                                          ((INSTANCE) == TIM15)  || \
17625                                          ((INSTANCE) == TIM20))
17626 
17627 /************ TIM Instances : at least 3 capture/compare channels *************/
17628 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17629                                          ((INSTANCE) == TIM2)   || \
17630                                          ((INSTANCE) == TIM3)   || \
17631                                          ((INSTANCE) == TIM4)   || \
17632                                          ((INSTANCE) == TIM5)   || \
17633                                          ((INSTANCE) == TIM8)   || \
17634                                          ((INSTANCE) == TIM20))
17635 
17636 /************ TIM Instances : at least 4 capture/compare channels *************/
17637 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17638                                          ((INSTANCE) == TIM2)   || \
17639                                          ((INSTANCE) == TIM3)   || \
17640                                          ((INSTANCE) == TIM4)   || \
17641                                          ((INSTANCE) == TIM5)   || \
17642                                          ((INSTANCE) == TIM8)   || \
17643                                          ((INSTANCE) == TIM20))
17644 
17645 /****************** TIM Instances : at least 5 capture/compare channels *******/
17646 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17647                                          ((INSTANCE) == TIM8)   || \
17648                                          ((INSTANCE) == TIM20))
17649 
17650 /****************** TIM Instances : at least 6 capture/compare channels *******/
17651 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17652                                          ((INSTANCE) == TIM8)   || \
17653                                          ((INSTANCE) == TIM20))
17654 
17655 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17656 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
17657                                             ((INSTANCE) == TIM8)   || \
17658                                             ((INSTANCE) == TIM15)  || \
17659                                             ((INSTANCE) == TIM16)  || \
17660                                             ((INSTANCE) == TIM17)  || \
17661                                             ((INSTANCE) == TIM20))
17662 
17663 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17664 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
17665                                             ((INSTANCE) == TIM2)   || \
17666                                             ((INSTANCE) == TIM3)   || \
17667                                             ((INSTANCE) == TIM4)   || \
17668                                             ((INSTANCE) == TIM5)   || \
17669                                             ((INSTANCE) == TIM6)   || \
17670                                             ((INSTANCE) == TIM7)   || \
17671                                             ((INSTANCE) == TIM8)   || \
17672                                             ((INSTANCE) == TIM15)  || \
17673                                             ((INSTANCE) == TIM16)  || \
17674                                             ((INSTANCE) == TIM17)  || \
17675                                             ((INSTANCE) == TIM20))
17676 
17677 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
17678 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
17679                                             ((INSTANCE) == TIM2)   || \
17680                                             ((INSTANCE) == TIM3)   || \
17681                                             ((INSTANCE) == TIM4)   || \
17682                                             ((INSTANCE) == TIM5)   || \
17683                                             ((INSTANCE) == TIM8)   || \
17684                                             ((INSTANCE) == TIM15)  || \
17685                                             ((INSTANCE) == TIM16)  || \
17686                                             ((INSTANCE) == TIM17)  || \
17687                                             ((INSTANCE) == TIM20))
17688 
17689 /******************** TIM Instances : DMA burst feature ***********************/
17690 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17691                                             ((INSTANCE) == TIM2)   || \
17692                                             ((INSTANCE) == TIM3)   || \
17693                                             ((INSTANCE) == TIM4)   || \
17694                                             ((INSTANCE) == TIM5)   || \
17695                                             ((INSTANCE) == TIM8)   || \
17696                                             ((INSTANCE) == TIM15)  || \
17697                                             ((INSTANCE) == TIM16)  || \
17698                                             ((INSTANCE) == TIM17)  || \
17699                                             ((INSTANCE) == TIM20))
17700 
17701 /******************* TIM Instances : output(s) available **********************/
17702 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
17703     ((((INSTANCE) == TIM1) &&                  \
17704      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17705       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17706       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17707       ((CHANNEL) == TIM_CHANNEL_4) ||          \
17708       ((CHANNEL) == TIM_CHANNEL_5) ||          \
17709       ((CHANNEL) == TIM_CHANNEL_6)))           \
17710      ||                                        \
17711      (((INSTANCE) == TIM2) &&                  \
17712      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17713       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17714       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17715       ((CHANNEL) == TIM_CHANNEL_4)))           \
17716      ||                                        \
17717      (((INSTANCE) == TIM3) &&                  \
17718      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17719       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17720       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17721       ((CHANNEL) == TIM_CHANNEL_4)))           \
17722      ||                                        \
17723      (((INSTANCE) == TIM4) &&                  \
17724      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17725       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17726       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17727       ((CHANNEL) == TIM_CHANNEL_4)))           \
17728      ||                                        \
17729      (((INSTANCE) == TIM5) &&                  \
17730      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17731       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17732       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17733       ((CHANNEL) == TIM_CHANNEL_4)))           \
17734      ||                                        \
17735      (((INSTANCE) == TIM8) &&                  \
17736      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17737       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17738       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17739       ((CHANNEL) == TIM_CHANNEL_4) ||          \
17740       ((CHANNEL) == TIM_CHANNEL_5) ||          \
17741       ((CHANNEL) == TIM_CHANNEL_6)))           \
17742      ||                                        \
17743      (((INSTANCE) == TIM15) &&                 \
17744      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17745       ((CHANNEL) == TIM_CHANNEL_2)))           \
17746      ||                                        \
17747      (((INSTANCE) == TIM16) &&                 \
17748      (((CHANNEL) == TIM_CHANNEL_1)))           \
17749      ||                                        \
17750      (((INSTANCE) == TIM17) &&                 \
17751       (((CHANNEL) == TIM_CHANNEL_1)))          \
17752      ||                                        \
17753      (((INSTANCE) == TIM20) &&                 \
17754      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17755       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17756       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17757       ((CHANNEL) == TIM_CHANNEL_4) ||          \
17758       ((CHANNEL) == TIM_CHANNEL_5) ||          \
17759       ((CHANNEL) == TIM_CHANNEL_6))))
17760 
17761 /****************** TIM Instances : supporting complementary output(s) ********/
17762 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
17763    ((((INSTANCE) == TIM1) &&                    \
17764      (((CHANNEL) == TIM_CHANNEL_1) ||           \
17765       ((CHANNEL) == TIM_CHANNEL_2) ||           \
17766       ((CHANNEL) == TIM_CHANNEL_3) ||           \
17767       ((CHANNEL) == TIM_CHANNEL_4)))            \
17768     ||                                          \
17769     (((INSTANCE) == TIM8) &&                    \
17770      (((CHANNEL) == TIM_CHANNEL_1) ||           \
17771       ((CHANNEL) == TIM_CHANNEL_2) ||           \
17772       ((CHANNEL) == TIM_CHANNEL_3) ||           \
17773       ((CHANNEL) == TIM_CHANNEL_4)))            \
17774     ||                                          \
17775     (((INSTANCE) == TIM15) &&                   \
17776      ((CHANNEL) == TIM_CHANNEL_1))              \
17777     ||                                          \
17778     (((INSTANCE) == TIM16) &&                   \
17779      ((CHANNEL) == TIM_CHANNEL_1))              \
17780     ||                                          \
17781     (((INSTANCE) == TIM17) &&                   \
17782      ((CHANNEL) == TIM_CHANNEL_1))              \
17783     ||                                          \
17784     (((INSTANCE) == TIM20) &&                   \
17785      (((CHANNEL) == TIM_CHANNEL_1) ||           \
17786       ((CHANNEL) == TIM_CHANNEL_2) ||           \
17787       ((CHANNEL) == TIM_CHANNEL_3) ||           \
17788       ((CHANNEL) == TIM_CHANNEL_4))))
17789 
17790 /****************** TIM Instances : supporting clock division *****************/
17791 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
17792                                                     ((INSTANCE) == TIM2)    || \
17793                                                     ((INSTANCE) == TIM3)    || \
17794                                                     ((INSTANCE) == TIM4)    || \
17795                                                     ((INSTANCE) == TIM5)    || \
17796                                                     ((INSTANCE) == TIM8)    || \
17797                                                     ((INSTANCE) == TIM15)   || \
17798                                                     ((INSTANCE) == TIM16)   || \
17799                                                     ((INSTANCE) == TIM17)   || \
17800                                                     ((INSTANCE) == TIM20))
17801 
17802 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17803 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17804                                                         ((INSTANCE) == TIM2) || \
17805                                                         ((INSTANCE) == TIM3) || \
17806                                                         ((INSTANCE) == TIM4) || \
17807                                                         ((INSTANCE) == TIM5) || \
17808                                                         ((INSTANCE) == TIM8) || \
17809                                                         ((INSTANCE) == TIM20))
17810 
17811 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17812 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17813                                                         ((INSTANCE) == TIM2) || \
17814                                                         ((INSTANCE) == TIM3) || \
17815                                                         ((INSTANCE) == TIM4) || \
17816                                                         ((INSTANCE) == TIM5) || \
17817                                                         ((INSTANCE) == TIM8) || \
17818                                                         ((INSTANCE) == TIM20))
17819 
17820 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17821 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
17822                                                         ((INSTANCE) == TIM2) || \
17823                                                         ((INSTANCE) == TIM3) || \
17824                                                         ((INSTANCE) == TIM4) || \
17825                                                         ((INSTANCE) == TIM5) || \
17826                                                         ((INSTANCE) == TIM8) || \
17827                                                         ((INSTANCE) == TIM15)|| \
17828                                                         ((INSTANCE) == TIM20))
17829 
17830 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17831 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
17832                                                         ((INSTANCE) == TIM2) || \
17833                                                         ((INSTANCE) == TIM3) || \
17834                                                         ((INSTANCE) == TIM4) || \
17835                                                         ((INSTANCE) == TIM5) || \
17836                                                         ((INSTANCE) == TIM8) || \
17837                                                         ((INSTANCE) == TIM15)|| \
17838                                                         ((INSTANCE) == TIM20))
17839 
17840 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17841 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17842                                                      ((INSTANCE) == TIM8)   || \
17843                                                      ((INSTANCE) == TIM20))
17844 
17845 /****************** TIM Instances : supporting commutation event generation ***/
17846 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17847                                                      ((INSTANCE) == TIM8)   || \
17848                                                      ((INSTANCE) == TIM15)  || \
17849                                                      ((INSTANCE) == TIM16)  || \
17850                                                      ((INSTANCE) == TIM17)  || \
17851                                                      ((INSTANCE) == TIM20))
17852 
17853 /****************** TIM Instances : supporting counting mode selection ********/
17854 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17855                                                         ((INSTANCE) == TIM2) || \
17856                                                         ((INSTANCE) == TIM3) || \
17857                                                         ((INSTANCE) == TIM4) || \
17858                                                         ((INSTANCE) == TIM5) || \
17859                                                         ((INSTANCE) == TIM8) || \
17860                                                         ((INSTANCE) == TIM20))
17861 
17862 /****************** TIM Instances : supporting encoder interface **************/
17863 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
17864                                                       ((INSTANCE) == TIM2)  || \
17865                                                       ((INSTANCE) == TIM3)  || \
17866                                                       ((INSTANCE) == TIM4)  || \
17867                                                       ((INSTANCE) == TIM5)  || \
17868                                                       ((INSTANCE) == TIM8)  || \
17869                                                       ((INSTANCE) == TIM20))
17870 
17871 /****************** TIM Instances : supporting Hall sensor interface **********/
17872 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17873                                                          ((INSTANCE) == TIM2)   || \
17874                                                          ((INSTANCE) == TIM3)   || \
17875                                                          ((INSTANCE) == TIM4)   || \
17876                                                          ((INSTANCE) == TIM5)   || \
17877                                                          ((INSTANCE) == TIM8)   || \
17878                                                          ((INSTANCE) == TIM15)  || \
17879                                                          ((INSTANCE) == TIM20))
17880 
17881 /**************** TIM Instances : external trigger input available ************/
17882 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
17883                                             ((INSTANCE) == TIM2)  || \
17884                                             ((INSTANCE) == TIM3)  || \
17885                                             ((INSTANCE) == TIM4)  || \
17886                                             ((INSTANCE) == TIM5)  || \
17887                                             ((INSTANCE) == TIM8)  || \
17888                                             ((INSTANCE) == TIM20))
17889 
17890 /************* TIM Instances : supporting ETR source selection ***************/
17891 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
17892                                              ((INSTANCE) == TIM2)  || \
17893                                              ((INSTANCE) == TIM3)  || \
17894                                              ((INSTANCE) == TIM4)  || \
17895                                              ((INSTANCE) == TIM5)  || \
17896                                              ((INSTANCE) == TIM8)  || \
17897                                              ((INSTANCE) == TIM20))
17898 
17899 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
17900 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
17901                                             ((INSTANCE) == TIM2)  || \
17902                                             ((INSTANCE) == TIM3)  || \
17903                                             ((INSTANCE) == TIM4)  || \
17904                                             ((INSTANCE) == TIM5)  || \
17905                                             ((INSTANCE) == TIM6)  || \
17906                                             ((INSTANCE) == TIM7)  || \
17907                                             ((INSTANCE) == TIM8)  || \
17908                                             ((INSTANCE) == TIM15) || \
17909                                             ((INSTANCE) == TIM20))
17910 
17911 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17912 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
17913                                             ((INSTANCE) == TIM2)  || \
17914                                             ((INSTANCE) == TIM3)  || \
17915                                             ((INSTANCE) == TIM4)  || \
17916                                             ((INSTANCE) == TIM5)  || \
17917                                             ((INSTANCE) == TIM8)  || \
17918                                             ((INSTANCE) == TIM15) || \
17919                                             ((INSTANCE) == TIM20))
17920 
17921 /****************** TIM Instances : supporting OCxREF clear *******************/
17922 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1)  || \
17923                                                        ((INSTANCE) == TIM2)  || \
17924                                                        ((INSTANCE) == TIM3)  || \
17925                                                        ((INSTANCE) == TIM4)  || \
17926                                                        ((INSTANCE) == TIM5)  || \
17927                                                        ((INSTANCE) == TIM8)  || \
17928                                                        ((INSTANCE) == TIM15) || \
17929                                                        ((INSTANCE) == TIM16) || \
17930                                                        ((INSTANCE) == TIM17) || \
17931                                                        ((INSTANCE) == TIM20))
17932 
17933 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
17934 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
17935                                                        ((INSTANCE) == TIM2)  || \
17936                                                        ((INSTANCE) == TIM3)  || \
17937                                                        ((INSTANCE) == TIM8)  || \
17938                                                        ((INSTANCE) == TIM15) || \
17939                                                        ((INSTANCE) == TIM16) || \
17940                                                        ((INSTANCE) == TIM17) || \
17941                                                        ((INSTANCE) == TIM20))
17942 
17943 /****************** TIM Instances : remapping capability **********************/
17944 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
17945                                             ((INSTANCE) == TIM2)  || \
17946                                             ((INSTANCE) == TIM3)  || \
17947                                             ((INSTANCE) == TIM4)  || \
17948                                             ((INSTANCE) == TIM5)  || \
17949                                             ((INSTANCE) == TIM8)  || \
17950                                             ((INSTANCE) == TIM20))
17951 
17952 /****************** TIM Instances : supporting repetition counter *************/
17953 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
17954                                                        ((INSTANCE) == TIM8)  || \
17955                                                        ((INSTANCE) == TIM15) || \
17956                                                        ((INSTANCE) == TIM16) || \
17957                                                        ((INSTANCE) == TIM17) || \
17958                                                        ((INSTANCE) == TIM20))
17959 
17960 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
17961 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
17962                                             ((INSTANCE) == TIM8)    || \
17963                                             ((INSTANCE) == TIM20))
17964 
17965 /******************* TIM Instances : Timer input XOR function *****************/
17966 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
17967                                             ((INSTANCE) == TIM2)   || \
17968                                             ((INSTANCE) == TIM3)   || \
17969                                             ((INSTANCE) == TIM4)   || \
17970                                             ((INSTANCE) == TIM5)   || \
17971                                             ((INSTANCE) == TIM8)   || \
17972                                             ((INSTANCE) == TIM15)  || \
17973                                             ((INSTANCE) == TIM20))
17974 
17975 /******************* TIM Instances : Timer input selection ********************/
17976 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
17977                                          ((INSTANCE) == TIM2)   || \
17978                                          ((INSTANCE) == TIM3)   || \
17979                                          ((INSTANCE) == TIM4)   || \
17980                                          ((INSTANCE) == TIM5)   || \
17981                                          ((INSTANCE) == TIM8)   || \
17982                                          ((INSTANCE) == TIM15)  || \
17983                                          ((INSTANCE) == TIM16)  || \
17984                                          ((INSTANCE) == TIM17)  || \
17985                                          ((INSTANCE) == TIM20))
17986 
17987 /****************** TIM Instances : Advanced timer instances *******************/
17988 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
17989                                                   ((INSTANCE) == TIM8)   || \
17990                                                   ((INSTANCE) == TIM20))
17991 
17992 /****************** TIM Instances : supporting HSE/32 request instances *******************/
17993 #define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
17994                                                  ((INSTANCE) == TIM17))
17995 
17996 /****************************** HRTIM Instances *******************************/
17997 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
17998 
17999 /******************** USART Instances : Synchronous mode **********************/
18000 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18001                                      ((INSTANCE) == USART2) || \
18002                                      ((INSTANCE) == USART3))
18003 
18004 /******************** UART Instances : Asynchronous mode **********************/
18005 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18006                                     ((INSTANCE) == USART2) || \
18007                                     ((INSTANCE) == USART3) || \
18008                                     ((INSTANCE) == UART4) || \
18009                                     ((INSTANCE) == UART5))
18010 
18011 /*********************** UART Instances : FIFO mode ***************************/
18012 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18013                                          ((INSTANCE) == USART2) || \
18014                                          ((INSTANCE) == USART3) || \
18015                                          ((INSTANCE) == UART4) || \
18016                                          ((INSTANCE) == UART5) || \
18017                                          ((INSTANCE) == LPUART1))
18018 
18019 /*********************** UART Instances : SPI Slave mode **********************/
18020 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18021                                               ((INSTANCE) == USART2) || \
18022                                               ((INSTANCE) == USART3))
18023 
18024 /****************** UART Instances : Auto Baud Rate detection ****************/
18025 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18026                                                             ((INSTANCE) == USART2) || \
18027                                                             ((INSTANCE) == USART3) || \
18028                                                             ((INSTANCE) == UART4)  || \
18029                                                             ((INSTANCE) == UART5))
18030 
18031 /****************** UART Instances : Driver Enable *****************/
18032 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
18033                                                       ((INSTANCE) == USART2) || \
18034                                                       ((INSTANCE) == USART3) || \
18035                                                       ((INSTANCE) == UART4)  || \
18036                                                       ((INSTANCE) == UART5)  || \
18037                                                       ((INSTANCE) == LPUART1))
18038 
18039 /******************** UART Instances : Half-Duplex mode **********************/
18040 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
18041                                                  ((INSTANCE) == USART2) || \
18042                                                  ((INSTANCE) == USART3) || \
18043                                                  ((INSTANCE) == UART4)  || \
18044                                                  ((INSTANCE) == UART5)  || \
18045                                                  ((INSTANCE) == LPUART1))
18046 
18047 /****************** UART Instances : Hardware Flow control ********************/
18048 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18049                                            ((INSTANCE) == USART2) || \
18050                                            ((INSTANCE) == USART3) || \
18051                                            ((INSTANCE) == UART4)  || \
18052                                            ((INSTANCE) == UART5)  || \
18053                                            ((INSTANCE) == LPUART1))
18054 
18055 /******************** UART Instances : LIN mode **********************/
18056 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
18057                                           ((INSTANCE) == USART2) || \
18058                                           ((INSTANCE) == USART3) || \
18059                                           ((INSTANCE) == UART4)  || \
18060                                           ((INSTANCE) == UART5))
18061 
18062 /******************** UART Instances : Wake-up from Stop mode **********************/
18063 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
18064                                                       ((INSTANCE) == USART2) || \
18065                                                       ((INSTANCE) == USART3) || \
18066                                                       ((INSTANCE) == UART4)  || \
18067                                                       ((INSTANCE) == UART5)  || \
18068                                                       ((INSTANCE) == LPUART1))
18069 
18070 /*********************** UART Instances : IRDA mode ***************************/
18071 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18072                                     ((INSTANCE) == USART2) || \
18073                                     ((INSTANCE) == USART3) || \
18074                                     ((INSTANCE) == UART4)  || \
18075                                     ((INSTANCE) == UART5))
18076 
18077 /********************* USART Instances : Smard card mode ***********************/
18078 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18079                                          ((INSTANCE) == USART2) || \
18080                                          ((INSTANCE) == USART3))
18081 
18082 /******************** LPUART Instance *****************************************/
18083 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
18084 
18085 /****************************** IWDG Instances ********************************/
18086 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
18087 
18088 /****************************** WWDG Instances ********************************/
18089 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
18090 
18091 /****************************** UCPD Instances ********************************/
18092 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == UCPD1)
18093 
18094 /******************************* USB Instances *******************************/
18095 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
18096 
18097 /**
18098   * @}
18099   */
18100 
18101 
18102 /******************************************************************************/
18103 /*  For a painless codes migration between the STM32G4xx device product       */
18104 /*  lines, the aliases defined below are put in place to overcome the         */
18105 /*  differences in the interrupt handlers and IRQn definitions.               */
18106 /*  No need to update developed interrupt code when moving across             */
18107 /*  product lines within the same STM32G4 Family                              */
18108 /******************************************************************************/
18109 
18110 /* Aliases for __IRQn */
18111 
18112 /* Aliases for __IRQHandler */
18113 
18114 #ifdef __cplusplus
18115 }
18116 #endif /* __cplusplus */
18117 
18118 #endif /* __STM32G474xx_H */
18119 
18120 /**
18121   * @}
18122   */
18123 
18124   /**
18125   * @}
18126   */
18127 
18128