1 /** 2 ****************************************************************************** 3 * @file stm32f328xx.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File. 6 * 7 * This file contains: 8 * - Data structures and the address mapping for all peripherals 9 * - Peripheral's registers declarations and bits definition 10 * - Macros to access peripheral's registers hardware 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2016 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 */ 24 25 /** @addtogroup CMSIS_Device 26 * @{ 27 */ 28 29 /** @addtogroup stm32f328xx 30 * @{ 31 */ 32 33 #ifndef __STM32F328xx_H 34 #define __STM32F328xx_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif /* __cplusplus */ 39 40 /** @addtogroup Configuration_section_for_CMSIS 41 * @{ 42 */ 43 44 /** 45 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 46 */ 47 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ 48 #define __MPU_PRESENT 0U /*!< STM32F328xx devices do not provide an MPU */ 49 #define __NVIC_PRIO_BITS 4U /*!< STM32F328xx devices use 4 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 51 #define __FPU_PRESENT 1U /*!< STM32F328xx devices provide an FPU */ 52 53 /** 54 * @} 55 */ 56 57 /** @addtogroup Peripheral_interrupt_number_definition 58 * @{ 59 */ 60 61 /** 62 * @brief STM32F328xx devices Interrupt Number Definition, according to the selected device 63 * in @ref Library_configuration_section 64 */ 65 typedef enum 66 { 67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 68 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 69 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 70 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 71 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 72 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 73 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 74 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 77 /****** STM32 specific Interrupt Numbers **********************************************************************/ 78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 79 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ 80 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ 81 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 82 RCC_IRQn = 5, /*!< RCC global Interrupt */ 83 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 84 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 85 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ 86 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 87 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 88 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 89 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 90 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 91 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 92 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 93 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 94 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 95 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ 96 CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ 97 CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ 98 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ 99 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ 100 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 101 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 102 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 103 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 104 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 105 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 106 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 107 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 108 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 109 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 110 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 111 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ 112 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ 113 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 114 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ 115 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ 116 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ 117 COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ 118 COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ 119 FPU_IRQn = 81, /*!< Floating point Interrupt */ 120 } IRQn_Type; 121 122 /** 123 * @} 124 */ 125 126 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 127 #include "system_stm32f3xx.h" /* STM32F3xx System Header */ 128 #include <stdint.h> 129 130 /** @addtogroup Peripheral_registers_structures 131 * @{ 132 */ 133 134 /** 135 * @brief Analog to Digital Converter 136 */ 137 138 typedef struct 139 { 140 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ 141 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ 142 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 143 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ 144 uint32_t RESERVED0; /*!< Reserved, 0x010 */ 145 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ 146 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ 147 uint32_t RESERVED1; /*!< Reserved, 0x01C */ 148 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ 149 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ 150 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ 151 uint32_t RESERVED2; /*!< Reserved, 0x02C */ 152 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 153 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 154 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 155 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 156 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ 157 uint32_t RESERVED3; /*!< Reserved, 0x044 */ 158 uint32_t RESERVED4; /*!< Reserved, 0x048 */ 159 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ 160 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ 161 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 162 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 163 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 164 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 165 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ 166 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ 167 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ 168 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ 169 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ 170 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 171 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ 172 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ 173 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 174 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 175 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ 176 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ 177 178 } ADC_TypeDef; 179 180 typedef struct 181 { 182 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ 183 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ 184 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ 185 __IO uint32_t CDR; /*!< ADC common regular data register for dual 186 AND triple modes, Address offset: ADC1/3 base address + 0x30C */ 187 } ADC_Common_TypeDef; 188 189 /** 190 * @brief Controller Area Network TxMailBox 191 */ 192 typedef struct 193 { 194 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 195 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 196 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 197 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 198 } CAN_TxMailBox_TypeDef; 199 200 /** 201 * @brief Controller Area Network FIFOMailBox 202 */ 203 typedef struct 204 { 205 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 206 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 207 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 208 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 209 } CAN_FIFOMailBox_TypeDef; 210 211 /** 212 * @brief Controller Area Network FilterRegister 213 */ 214 typedef struct 215 { 216 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 217 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 218 } CAN_FilterRegister_TypeDef; 219 220 /** 221 * @brief Controller Area Network 222 */ 223 typedef struct 224 { 225 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 226 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 227 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 228 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 229 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 230 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 231 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 232 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 233 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 234 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 235 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 236 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 237 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 238 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 239 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 240 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 241 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 242 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 243 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 244 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 245 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 246 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 247 } CAN_TypeDef; 248 249 /** 250 * @brief Analog Comparators 251 */ 252 typedef struct 253 { 254 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 255 } COMP_TypeDef; 256 257 typedef struct 258 { 259 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 260 } COMP_Common_TypeDef; 261 262 /** 263 * @brief CRC calculation unit 264 */ 265 266 typedef struct 267 { 268 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 269 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 270 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 271 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 272 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 273 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 274 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 275 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 276 } CRC_TypeDef; 277 278 /** 279 * @brief Digital to Analog Converter 280 */ 281 282 typedef struct 283 { 284 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 285 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 286 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 287 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 288 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 289 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 290 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 291 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 292 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 293 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 294 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 295 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 296 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 297 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 298 } DAC_TypeDef; 299 300 /** 301 * @brief Debug MCU 302 */ 303 304 typedef struct 305 { 306 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 307 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 308 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 309 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 310 }DBGMCU_TypeDef; 311 312 /** 313 * @brief DMA Controller 314 */ 315 316 typedef struct 317 { 318 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 319 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 320 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 321 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 322 } DMA_Channel_TypeDef; 323 324 typedef struct 325 { 326 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 327 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 328 } DMA_TypeDef; 329 330 /** 331 * @brief External Interrupt/Event Controller 332 */ 333 334 typedef struct 335 { 336 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 337 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 338 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 339 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 340 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 341 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 342 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 343 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 344 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ 345 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ 346 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ 347 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ 348 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ 349 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ 350 }EXTI_TypeDef; 351 352 /** 353 * @brief FLASH Registers 354 */ 355 356 typedef struct 357 { 358 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 359 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ 360 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ 361 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ 362 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ 363 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ 364 uint32_t RESERVED; /*!< Reserved, 0x18 */ 365 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ 366 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ 367 368 } FLASH_TypeDef; 369 370 /** 371 * @brief Option Bytes Registers 372 */ 373 typedef struct 374 { 375 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ 376 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ 377 __IO uint16_t Data0; /*!<FLASH option byte Data0 options, Address offset: 0x04 */ 378 __IO uint16_t Data1; /*!<FLASH option byte Data1 options, Address offset: 0x06 */ 379 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ 380 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ 381 } OB_TypeDef; 382 383 /** 384 * @brief General Purpose I/O 385 */ 386 387 typedef struct 388 { 389 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 390 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 391 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 392 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 393 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 394 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 395 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 396 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 397 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 398 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 399 }GPIO_TypeDef; 400 401 /** 402 * @brief Operational Amplifier (OPAMP) 403 */ 404 405 typedef struct 406 { 407 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 408 } OPAMP_TypeDef; 409 410 /** 411 * @brief System configuration controller 412 */ 413 414 typedef struct 415 { 416 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 417 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ 418 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ 419 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 420 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */ 421 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */ 422 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */ 423 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */ 424 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */ 425 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */ 426 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */ 427 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */ 428 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */ 429 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */ 430 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */ 431 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */ 432 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */ 433 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */ 434 } SYSCFG_TypeDef; 435 436 /** 437 * @brief Inter-integrated Circuit Interface 438 */ 439 440 typedef struct 441 { 442 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 443 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 444 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 445 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 446 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 447 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 448 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 449 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 450 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 451 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 452 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 453 }I2C_TypeDef; 454 455 /** 456 * @brief Independent WATCHDOG 457 */ 458 459 typedef struct 460 { 461 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 462 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 463 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 464 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 465 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 466 } IWDG_TypeDef; 467 468 /** 469 * @brief Power Control 470 */ 471 472 typedef struct 473 { 474 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 475 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 476 } PWR_TypeDef; 477 478 /** 479 * @brief Reset and Clock Control 480 */ 481 typedef struct 482 { 483 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 484 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 485 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 486 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 487 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 488 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 489 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 490 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 491 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 492 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 493 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 494 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 495 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 496 } RCC_TypeDef; 497 498 /** 499 * @brief Real-Time Clock 500 */ 501 502 typedef struct 503 { 504 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 505 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 506 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 507 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 508 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 509 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 510 uint32_t RESERVED0; /*!< Reserved, 0x18 */ 511 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 512 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 513 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 514 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 515 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 516 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 517 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 518 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 519 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 520 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 521 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 522 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 523 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 524 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 525 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 526 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 527 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 528 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 529 } RTC_TypeDef; 530 531 532 /** 533 * @brief Serial Peripheral Interface 534 */ 535 536 typedef struct 537 { 538 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 539 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 540 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 541 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 542 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 543 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 544 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 545 } SPI_TypeDef; 546 547 /** 548 * @brief TIM 549 */ 550 typedef struct 551 { 552 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 553 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 554 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 555 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 556 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 557 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 558 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 559 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 560 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 561 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 562 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 563 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 564 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 565 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 566 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 567 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 568 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 569 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 570 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 571 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 572 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 573 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 574 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 575 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ 576 } TIM_TypeDef; 577 578 /** 579 * @brief Touch Sensing Controller (TSC) 580 */ 581 typedef struct 582 { 583 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 584 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 585 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 586 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 587 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 588 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 589 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 590 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 591 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 592 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 593 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 594 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 595 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 596 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 597 } TSC_TypeDef; 598 599 /** 600 * @brief Universal Synchronous Asynchronous Receiver Transmitter 601 */ 602 603 typedef struct 604 { 605 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 606 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 607 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 608 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 609 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 610 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 611 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 612 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 613 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 614 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 615 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 616 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 617 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 618 } USART_TypeDef; 619 620 /** 621 * @brief Window WATCHDOG 622 */ 623 typedef struct 624 { 625 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 626 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 627 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 628 } WWDG_TypeDef; 629 630 /** 631 * @} 632 */ 633 634 /** @addtogroup Peripheral_memory_map 635 * @{ 636 */ 637 638 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 639 #define CCMDATARAM_BASE 0x10000000UL /*!< CCM(core coupled memory) data RAM base address in the alias region */ 640 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 641 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 642 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ 643 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 644 645 646 /*!< Peripheral memory map */ 647 #define APB1PERIPH_BASE PERIPH_BASE 648 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 649 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 650 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 651 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) 652 653 /*!< APB1 peripherals */ 654 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 655 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 656 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 657 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 658 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 659 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 660 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 661 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 662 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 663 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 664 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400UL) 665 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 666 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL) 667 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800UL) 668 #define DAC_BASE DAC1_BASE 669 670 /*!< APB2 peripherals */ 671 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 672 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL) 673 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL) 674 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL) 675 #define COMP_BASE COMP2_BASE 676 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL) 677 #define OPAMP_BASE OPAMP2_BASE 678 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 679 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 680 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 681 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 682 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) 683 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 684 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 685 686 /*!< AHB1 peripherals */ 687 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) 688 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL) 689 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL) 690 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL) 691 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL) 692 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL) 693 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL) 694 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL) 695 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL) 696 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ 697 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ 698 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 699 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 700 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) 701 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) 702 703 /*!< AHB2 peripherals */ 704 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 705 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 706 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 707 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) 708 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 709 710 /*!< AHB3 peripherals */ 711 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL) 712 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL) 713 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL) 714 715 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ 716 /** 717 * @} 718 */ 719 720 /** @addtogroup Peripheral_declaration 721 * @{ 722 */ 723 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 724 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 725 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 726 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 727 #define RTC ((RTC_TypeDef *) RTC_BASE) 728 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 729 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 730 #define USART2 ((USART_TypeDef *) USART2_BASE) 731 #define USART3 ((USART_TypeDef *) USART3_BASE) 732 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 733 #define CAN ((CAN_TypeDef *) CAN_BASE) 734 #define PWR ((PWR_TypeDef *) PWR_BASE) 735 #define DAC ((DAC_TypeDef *) DAC_BASE) 736 #define DAC1 ((DAC_TypeDef *) DAC1_BASE) 737 #define DAC2 ((DAC_TypeDef *) DAC2_BASE) 738 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 739 #define COMP4 ((COMP_TypeDef *) COMP4_BASE) 740 #define COMP6 ((COMP_TypeDef *) COMP6_BASE) 741 /* Legacy define */ 742 #define COMP ((COMP_TypeDef *) COMP_BASE) 743 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 744 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) 745 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 746 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 747 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 748 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 749 #define USART1 ((USART_TypeDef *) USART1_BASE) 750 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 751 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 752 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 753 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 754 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 755 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 756 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 757 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 758 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 759 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 760 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 761 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 762 #define RCC ((RCC_TypeDef *) RCC_BASE) 763 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 764 #define OB ((OB_TypeDef *) OB_BASE) 765 #define CRC ((CRC_TypeDef *) CRC_BASE) 766 #define TSC ((TSC_TypeDef *) TSC_BASE) 767 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 768 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 769 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 770 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 771 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 772 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 773 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 774 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE) 775 /* Legacy defines */ 776 #define ADC1_2_COMMON ADC12_COMMON 777 778 /** 779 * @} 780 */ 781 782 /** @addtogroup Exported_constants 783 * @{ 784 */ 785 786 /** @addtogroup Hardware_Constant_Definition 787 * @{ 788 */ 789 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 790 791 /** 792 * @} 793 */ 794 795 /** @addtogroup Peripheral_Registers_Bits_Definition 796 * @{ 797 */ 798 799 /******************************************************************************/ 800 /* Peripheral Registers_Bits_Definition */ 801 /******************************************************************************/ 802 803 /******************************************************************************/ 804 /* */ 805 /* Analog to Digital Converter SAR (ADC) */ 806 /* */ 807 /******************************************************************************/ 808 809 #define ADC5_V1_1 /*!< ADC IP version */ 810 811 /* 812 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 813 */ 814 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ 815 816 /******************** Bit definition for ADC_ISR register ********************/ 817 #define ADC_ISR_ADRDY_Pos (0U) 818 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 819 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 820 #define ADC_ISR_EOSMP_Pos (1U) 821 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 822 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 823 #define ADC_ISR_EOC_Pos (2U) 824 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 825 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 826 #define ADC_ISR_EOS_Pos (3U) 827 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 828 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 829 #define ADC_ISR_OVR_Pos (4U) 830 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 831 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 832 #define ADC_ISR_JEOC_Pos (5U) 833 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ 834 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ 835 #define ADC_ISR_JEOS_Pos (6U) 836 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ 837 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 838 #define ADC_ISR_AWD1_Pos (7U) 839 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 840 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 841 #define ADC_ISR_AWD2_Pos (8U) 842 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 843 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 844 #define ADC_ISR_AWD3_Pos (9U) 845 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 846 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 847 #define ADC_ISR_JQOVF_Pos (10U) 848 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ 849 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ 850 851 /* Legacy defines */ 852 #define ADC_ISR_ADRD (ADC_ISR_ADRDY) 853 854 /******************** Bit definition for ADC_IER register ********************/ 855 #define ADC_IER_ADRDYIE_Pos (0U) 856 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 857 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 858 #define ADC_IER_EOSMPIE_Pos (1U) 859 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 860 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 861 #define ADC_IER_EOCIE_Pos (2U) 862 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 863 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 864 #define ADC_IER_EOSIE_Pos (3U) 865 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 866 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 867 #define ADC_IER_OVRIE_Pos (4U) 868 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 869 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 870 #define ADC_IER_JEOCIE_Pos (5U) 871 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ 872 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ 873 #define ADC_IER_JEOSIE_Pos (6U) 874 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ 875 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 876 #define ADC_IER_AWD1IE_Pos (7U) 877 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 878 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 879 #define ADC_IER_AWD2IE_Pos (8U) 880 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 881 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 882 #define ADC_IER_AWD3IE_Pos (9U) 883 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 884 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 885 #define ADC_IER_JQOVFIE_Pos (10U) 886 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ 887 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ 888 889 /* Legacy defines */ 890 #define ADC_IER_RDY (ADC_IER_ADRDYIE) 891 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) 892 #define ADC_IER_EOC (ADC_IER_EOCIE) 893 #define ADC_IER_EOS (ADC_IER_EOSIE) 894 #define ADC_IER_OVR (ADC_IER_OVRIE) 895 #define ADC_IER_JEOC (ADC_IER_JEOCIE) 896 #define ADC_IER_JEOS (ADC_IER_JEOSIE) 897 #define ADC_IER_AWD1 (ADC_IER_AWD1IE) 898 #define ADC_IER_AWD2 (ADC_IER_AWD2IE) 899 #define ADC_IER_AWD3 (ADC_IER_AWD3IE) 900 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) 901 902 /******************** Bit definition for ADC_CR register ********************/ 903 #define ADC_CR_ADEN_Pos (0U) 904 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 905 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 906 #define ADC_CR_ADDIS_Pos (1U) 907 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 908 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 909 #define ADC_CR_ADSTART_Pos (2U) 910 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 911 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 912 #define ADC_CR_JADSTART_Pos (3U) 913 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ 914 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ 915 #define ADC_CR_ADSTP_Pos (4U) 916 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 917 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 918 #define ADC_CR_JADSTP_Pos (5U) 919 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ 920 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ 921 #define ADC_CR_ADVREGEN_Pos (28U) 922 #define ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos) /*!< 0x30000000 */ 923 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 924 #define ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 925 #define ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos) /*!< 0x20000000 */ 926 #define ADC_CR_ADCALDIF_Pos (30U) 927 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ 928 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ 929 #define ADC_CR_ADCAL_Pos (31U) 930 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 931 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 932 933 /******************** Bit definition for ADC_CFGR register ******************/ 934 #define ADC_CFGR_DMAEN_Pos (0U) 935 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ 936 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ 937 #define ADC_CFGR_DMACFG_Pos (1U) 938 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ 939 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ 940 941 #define ADC_CFGR_RES_Pos (3U) 942 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ 943 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ 944 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ 945 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ 946 947 #define ADC_CFGR_ALIGN_Pos (5U) 948 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ 949 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ 950 951 #define ADC_CFGR_EXTSEL_Pos (6U) 952 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ 953 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ 954 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ 955 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ 956 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ 957 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ 958 959 #define ADC_CFGR_EXTEN_Pos (10U) 960 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ 961 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 962 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ 963 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ 964 965 #define ADC_CFGR_OVRMOD_Pos (12U) 966 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ 967 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 968 #define ADC_CFGR_CONT_Pos (13U) 969 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ 970 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ 971 #define ADC_CFGR_AUTDLY_Pos (14U) 972 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ 973 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ 974 975 #define ADC_CFGR_DISCEN_Pos (16U) 976 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ 977 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 978 979 #define ADC_CFGR_DISCNUM_Pos (17U) 980 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ 981 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ 982 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ 983 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ 984 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ 985 986 #define ADC_CFGR_JDISCEN_Pos (20U) 987 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ 988 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ 989 #define ADC_CFGR_JQM_Pos (21U) 990 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ 991 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ 992 #define ADC_CFGR_AWD1SGL_Pos (22U) 993 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ 994 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 995 #define ADC_CFGR_AWD1EN_Pos (23U) 996 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ 997 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 998 #define ADC_CFGR_JAWD1EN_Pos (24U) 999 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ 1000 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 1001 #define ADC_CFGR_JAUTO_Pos (25U) 1002 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ 1003 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 1004 1005 #define ADC_CFGR_AWD1CH_Pos (26U) 1006 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ 1007 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 1008 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ 1009 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ 1010 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ 1011 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ 1012 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ 1013 1014 /* Legacy defines */ 1015 #define ADC_CFGR_AUTOFF_Pos (15U) 1016 #define ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos) /*!< 0x00008000 */ 1017 #define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk /*!< ADC low power auto power off */ 1018 1019 /******************** Bit definition for ADC_SMPR1 register *****************/ 1020 #define ADC_SMPR1_SMP0_Pos (0U) 1021 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ 1022 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1023 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ 1024 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ 1025 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ 1026 1027 #define ADC_SMPR1_SMP1_Pos (3U) 1028 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ 1029 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1030 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ 1031 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ 1032 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ 1033 1034 #define ADC_SMPR1_SMP2_Pos (6U) 1035 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ 1036 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1037 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ 1038 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ 1039 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ 1040 1041 #define ADC_SMPR1_SMP3_Pos (9U) 1042 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ 1043 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1044 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ 1045 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ 1046 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ 1047 1048 #define ADC_SMPR1_SMP4_Pos (12U) 1049 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ 1050 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1051 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ 1052 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ 1053 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ 1054 1055 #define ADC_SMPR1_SMP5_Pos (15U) 1056 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ 1057 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1058 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ 1059 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ 1060 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ 1061 1062 #define ADC_SMPR1_SMP6_Pos (18U) 1063 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ 1064 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1065 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ 1066 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ 1067 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ 1068 1069 #define ADC_SMPR1_SMP7_Pos (21U) 1070 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ 1071 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1072 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ 1073 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ 1074 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ 1075 1076 #define ADC_SMPR1_SMP8_Pos (24U) 1077 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ 1078 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1079 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ 1080 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ 1081 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ 1082 1083 #define ADC_SMPR1_SMP9_Pos (27U) 1084 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ 1085 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1086 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ 1087 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ 1088 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ 1089 1090 /******************** Bit definition for ADC_SMPR2 register *****************/ 1091 #define ADC_SMPR2_SMP10_Pos (0U) 1092 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1093 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1094 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1095 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1096 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1097 1098 #define ADC_SMPR2_SMP11_Pos (3U) 1099 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1100 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1101 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1102 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1103 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1104 1105 #define ADC_SMPR2_SMP12_Pos (6U) 1106 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1107 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1108 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1109 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1110 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1111 1112 #define ADC_SMPR2_SMP13_Pos (9U) 1113 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1114 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1115 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1116 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1117 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1118 1119 #define ADC_SMPR2_SMP14_Pos (12U) 1120 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1121 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1122 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1123 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1124 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1125 1126 #define ADC_SMPR2_SMP15_Pos (15U) 1127 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1128 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 1129 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1130 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1131 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1132 1133 #define ADC_SMPR2_SMP16_Pos (18U) 1134 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1135 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1136 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1137 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1138 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1139 1140 #define ADC_SMPR2_SMP17_Pos (21U) 1141 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1142 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1143 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1144 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1145 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1146 1147 #define ADC_SMPR2_SMP18_Pos (24U) 1148 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1149 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1150 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1151 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1152 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1153 1154 /******************** Bit definition for ADC_TR1 register *******************/ 1155 #define ADC_TR1_LT1_Pos (0U) 1156 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 1157 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1158 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 1159 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 1160 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 1161 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 1162 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 1163 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 1164 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 1165 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 1166 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 1167 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 1168 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 1169 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 1170 1171 #define ADC_TR1_HT1_Pos (16U) 1172 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 1173 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1174 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 1175 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 1176 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 1177 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 1178 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 1179 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 1180 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 1181 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 1182 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 1183 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 1184 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 1185 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 1186 1187 /******************** Bit definition for ADC_TR2 register *******************/ 1188 #define ADC_TR2_LT2_Pos (0U) 1189 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ 1190 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1191 #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ 1192 #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ 1193 #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ 1194 #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ 1195 #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ 1196 #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ 1197 #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ 1198 #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ 1199 1200 #define ADC_TR2_HT2_Pos (16U) 1201 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ 1202 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1203 #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ 1204 #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ 1205 #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ 1206 #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ 1207 #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ 1208 #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ 1209 #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ 1210 #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ 1211 1212 /******************** Bit definition for ADC_TR3 register *******************/ 1213 #define ADC_TR3_LT3_Pos (0U) 1214 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ 1215 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1216 #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ 1217 #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ 1218 #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ 1219 #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ 1220 #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ 1221 #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ 1222 #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ 1223 #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ 1224 1225 #define ADC_TR3_HT3_Pos (16U) 1226 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ 1227 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1228 #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ 1229 #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ 1230 #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ 1231 #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ 1232 #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ 1233 #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ 1234 #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ 1235 #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ 1236 1237 /******************** Bit definition for ADC_SQR1 register ******************/ 1238 #define ADC_SQR1_L_Pos (0U) 1239 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ 1240 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1241 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ 1242 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ 1243 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ 1244 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ 1245 1246 #define ADC_SQR1_SQ1_Pos (6U) 1247 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ 1248 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1249 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ 1250 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ 1251 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ 1252 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ 1253 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ 1254 1255 #define ADC_SQR1_SQ2_Pos (12U) 1256 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ 1257 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1258 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ 1259 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ 1260 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ 1261 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ 1262 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ 1263 1264 #define ADC_SQR1_SQ3_Pos (18U) 1265 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ 1266 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1267 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ 1268 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ 1269 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ 1270 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ 1271 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ 1272 1273 #define ADC_SQR1_SQ4_Pos (24U) 1274 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ 1275 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1276 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ 1277 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ 1278 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ 1279 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ 1280 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ 1281 1282 /******************** Bit definition for ADC_SQR2 register ******************/ 1283 #define ADC_SQR2_SQ5_Pos (0U) 1284 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ 1285 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1286 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ 1287 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ 1288 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ 1289 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ 1290 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ 1291 1292 #define ADC_SQR2_SQ6_Pos (6U) 1293 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ 1294 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1295 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ 1296 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ 1297 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ 1298 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ 1299 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ 1300 1301 #define ADC_SQR2_SQ7_Pos (12U) 1302 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ 1303 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1304 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ 1305 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ 1306 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ 1307 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ 1308 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ 1309 1310 #define ADC_SQR2_SQ8_Pos (18U) 1311 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ 1312 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1313 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ 1314 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ 1315 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ 1316 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ 1317 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ 1318 1319 #define ADC_SQR2_SQ9_Pos (24U) 1320 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ 1321 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1322 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ 1323 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ 1324 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ 1325 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ 1326 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ 1327 1328 /******************** Bit definition for ADC_SQR3 register ******************/ 1329 #define ADC_SQR3_SQ10_Pos (0U) 1330 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ 1331 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1332 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ 1333 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ 1334 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ 1335 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ 1336 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ 1337 1338 #define ADC_SQR3_SQ11_Pos (6U) 1339 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ 1340 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1341 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ 1342 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ 1343 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ 1344 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ 1345 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ 1346 1347 #define ADC_SQR3_SQ12_Pos (12U) 1348 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ 1349 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1350 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ 1351 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ 1352 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ 1353 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ 1354 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ 1355 1356 #define ADC_SQR3_SQ13_Pos (18U) 1357 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ 1358 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1359 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ 1360 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ 1361 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ 1362 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ 1363 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ 1364 1365 #define ADC_SQR3_SQ14_Pos (24U) 1366 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ 1367 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1368 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ 1369 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ 1370 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ 1371 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ 1372 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ 1373 1374 /******************** Bit definition for ADC_SQR4 register ******************/ 1375 #define ADC_SQR4_SQ15_Pos (0U) 1376 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ 1377 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1378 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ 1379 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ 1380 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ 1381 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ 1382 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ 1383 1384 #define ADC_SQR4_SQ16_Pos (6U) 1385 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ 1386 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1387 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ 1388 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ 1389 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ 1390 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ 1391 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ 1392 1393 /******************** Bit definition for ADC_DR register ********************/ 1394 #define ADC_DR_RDATA_Pos (0U) 1395 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ 1396 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ 1397 #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ 1398 #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ 1399 #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ 1400 #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ 1401 #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ 1402 #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ 1403 #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ 1404 #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ 1405 #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ 1406 #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ 1407 #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ 1408 #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ 1409 #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ 1410 #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ 1411 #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ 1412 #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ 1413 1414 /******************** Bit definition for ADC_JSQR register ******************/ 1415 #define ADC_JSQR_JL_Pos (0U) 1416 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ 1417 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1418 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ 1419 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ 1420 1421 #define ADC_JSQR_JEXTSEL_Pos (2U) 1422 #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ 1423 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1424 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ 1425 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ 1426 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ 1427 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ 1428 1429 #define ADC_JSQR_JEXTEN_Pos (6U) 1430 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ 1431 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1432 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ 1433 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ 1434 1435 #define ADC_JSQR_JSQ1_Pos (8U) 1436 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ 1437 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1438 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ 1439 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ 1440 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ 1441 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ 1442 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ 1443 1444 #define ADC_JSQR_JSQ2_Pos (14U) 1445 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ 1446 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1447 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ 1448 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ 1449 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ 1450 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ 1451 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ 1452 1453 #define ADC_JSQR_JSQ3_Pos (20U) 1454 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ 1455 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1456 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ 1457 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ 1458 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ 1459 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ 1460 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ 1461 1462 #define ADC_JSQR_JSQ4_Pos (26U) 1463 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ 1464 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1465 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ 1466 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ 1467 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ 1468 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ 1469 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ 1470 1471 1472 /******************** Bit definition for ADC_OFR1 register ******************/ 1473 #define ADC_OFR1_OFFSET1_Pos (0U) 1474 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ 1475 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ 1476 #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ 1477 #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ 1478 #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ 1479 #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ 1480 #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ 1481 #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ 1482 #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ 1483 #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ 1484 #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ 1485 #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ 1486 #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ 1487 #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ 1488 1489 #define ADC_OFR1_OFFSET1_CH_Pos (26U) 1490 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ 1491 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ 1492 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ 1493 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ 1494 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ 1495 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ 1496 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ 1497 1498 #define ADC_OFR1_OFFSET1_EN_Pos (31U) 1499 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ 1500 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ 1501 1502 /******************** Bit definition for ADC_OFR2 register ******************/ 1503 #define ADC_OFR2_OFFSET2_Pos (0U) 1504 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ 1505 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ 1506 #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ 1507 #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ 1508 #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ 1509 #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ 1510 #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ 1511 #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ 1512 #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ 1513 #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ 1514 #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ 1515 #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ 1516 #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ 1517 #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ 1518 1519 #define ADC_OFR2_OFFSET2_CH_Pos (26U) 1520 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ 1521 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ 1522 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ 1523 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ 1524 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ 1525 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ 1526 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ 1527 1528 #define ADC_OFR2_OFFSET2_EN_Pos (31U) 1529 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ 1530 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ 1531 1532 /******************** Bit definition for ADC_OFR3 register ******************/ 1533 #define ADC_OFR3_OFFSET3_Pos (0U) 1534 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ 1535 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ 1536 #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ 1537 #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ 1538 #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ 1539 #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ 1540 #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ 1541 #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ 1542 #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ 1543 #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ 1544 #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ 1545 #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ 1546 #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ 1547 #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ 1548 1549 #define ADC_OFR3_OFFSET3_CH_Pos (26U) 1550 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ 1551 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ 1552 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ 1553 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ 1554 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ 1555 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ 1556 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ 1557 1558 #define ADC_OFR3_OFFSET3_EN_Pos (31U) 1559 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ 1560 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ 1561 1562 /******************** Bit definition for ADC_OFR4 register ******************/ 1563 #define ADC_OFR4_OFFSET4_Pos (0U) 1564 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ 1565 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ 1566 #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ 1567 #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ 1568 #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ 1569 #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ 1570 #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ 1571 #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ 1572 #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ 1573 #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ 1574 #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ 1575 #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ 1576 #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ 1577 #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ 1578 1579 #define ADC_OFR4_OFFSET4_CH_Pos (26U) 1580 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ 1581 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ 1582 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ 1583 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ 1584 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ 1585 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ 1586 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ 1587 1588 #define ADC_OFR4_OFFSET4_EN_Pos (31U) 1589 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ 1590 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ 1591 1592 /******************** Bit definition for ADC_JDR1 register ******************/ 1593 #define ADC_JDR1_JDATA_Pos (0U) 1594 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1595 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1596 #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ 1597 #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ 1598 #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ 1599 #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ 1600 #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ 1601 #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ 1602 #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ 1603 #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ 1604 #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ 1605 #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ 1606 #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ 1607 #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ 1608 #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ 1609 #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ 1610 #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ 1611 #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ 1612 1613 /******************** Bit definition for ADC_JDR2 register ******************/ 1614 #define ADC_JDR2_JDATA_Pos (0U) 1615 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1616 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1617 #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ 1618 #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ 1619 #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ 1620 #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ 1621 #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ 1622 #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ 1623 #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ 1624 #define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ 1625 #define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ 1626 #define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ 1627 #define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ 1628 #define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ 1629 #define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ 1630 #define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ 1631 #define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ 1632 #define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ 1633 1634 /******************** Bit definition for ADC_JDR3 register ******************/ 1635 #define ADC_JDR3_JDATA_Pos (0U) 1636 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1637 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1638 #define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ 1639 #define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ 1640 #define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ 1641 #define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ 1642 #define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ 1643 #define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ 1644 #define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ 1645 #define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ 1646 #define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ 1647 #define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ 1648 #define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ 1649 #define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ 1650 #define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ 1651 #define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ 1652 #define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ 1653 #define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ 1654 1655 /******************** Bit definition for ADC_JDR4 register ******************/ 1656 #define ADC_JDR4_JDATA_Pos (0U) 1657 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1658 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1659 #define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ 1660 #define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ 1661 #define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ 1662 #define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ 1663 #define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ 1664 #define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ 1665 #define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ 1666 #define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ 1667 #define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ 1668 #define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ 1669 #define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ 1670 #define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ 1671 #define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ 1672 #define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ 1673 #define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ 1674 #define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ 1675 1676 /******************** Bit definition for ADC_AWD2CR register ****************/ 1677 #define ADC_AWD2CR_AWD2CH_Pos (1U) 1678 #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ 1679 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1680 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1681 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1682 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1683 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1684 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1685 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1686 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1687 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1688 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1689 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1690 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1691 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1692 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1693 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1694 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1695 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1696 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1697 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1698 1699 /******************** Bit definition for ADC_AWD3CR register ****************/ 1700 #define ADC_AWD3CR_AWD3CH_Pos (1U) 1701 #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ 1702 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1703 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1704 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1705 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1706 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1707 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1708 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1709 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1710 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1711 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1712 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1713 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1714 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1715 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1716 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1717 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1718 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1719 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1720 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1721 1722 /******************** Bit definition for ADC_DIFSEL register ****************/ 1723 #define ADC_DIFSEL_DIFSEL_Pos (1U) 1724 #define ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0003FFFF */ 1725 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ 1726 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ 1727 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ 1728 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ 1729 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ 1730 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ 1731 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ 1732 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ 1733 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ 1734 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ 1735 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ 1736 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ 1737 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ 1738 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ 1739 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ 1740 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ 1741 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ 1742 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ 1743 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ 1744 1745 /******************** Bit definition for ADC_CALFACT register ***************/ 1746 #define ADC_CALFACT_CALFACT_S_Pos (0U) 1747 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ 1748 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ 1749 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ 1750 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ 1751 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ 1752 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ 1753 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ 1754 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ 1755 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ 1756 1757 #define ADC_CALFACT_CALFACT_D_Pos (16U) 1758 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ 1759 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ 1760 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ 1761 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ 1762 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ 1763 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ 1764 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ 1765 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ 1766 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ 1767 1768 /************************* ADC Common registers *****************************/ 1769 /*************** Bit definition for ADC12_COMMON_CSR register ***************/ 1770 #define ADC12_CSR_ADRDY_MST_Pos (0U) 1771 #define ADC12_CSR_ADRDY_MST_Msk (0x1UL << ADC12_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ 1772 #define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ 1773 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U) 1774 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */ 1775 #define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ 1776 #define ADC12_CSR_ADRDY_EOC_MST_Pos (2U) 1777 #define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */ 1778 #define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ 1779 #define ADC12_CSR_ADRDY_EOS_MST_Pos (3U) 1780 #define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */ 1781 #define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ 1782 #define ADC12_CSR_ADRDY_OVR_MST_Pos (4U) 1783 #define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */ 1784 #define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk /*!< Overrun flag of the master ADC */ 1785 #define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U) 1786 #define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */ 1787 #define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ 1788 #define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U) 1789 #define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */ 1790 #define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ 1791 #define ADC12_CSR_AWD1_MST_Pos (7U) 1792 #define ADC12_CSR_AWD1_MST_Msk (0x1UL << ADC12_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ 1793 #define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ 1794 #define ADC12_CSR_AWD2_MST_Pos (8U) 1795 #define ADC12_CSR_AWD2_MST_Msk (0x1UL << ADC12_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ 1796 #define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ 1797 #define ADC12_CSR_AWD3_MST_Pos (9U) 1798 #define ADC12_CSR_AWD3_MST_Msk (0x1UL << ADC12_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ 1799 #define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ 1800 #define ADC12_CSR_JQOVF_MST_Pos (10U) 1801 #define ADC12_CSR_JQOVF_MST_Msk (0x1UL << ADC12_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ 1802 #define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ 1803 #define ADC12_CSR_ADRDY_SLV_Pos (16U) 1804 #define ADC12_CSR_ADRDY_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ 1805 #define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ 1806 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U) 1807 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */ 1808 #define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ 1809 #define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U) 1810 #define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */ 1811 #define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ 1812 #define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U) 1813 #define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */ 1814 #define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ 1815 #define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U) 1816 #define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */ 1817 #define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ 1818 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U) 1819 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */ 1820 #define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ 1821 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U) 1822 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */ 1823 #define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ 1824 #define ADC12_CSR_AWD1_SLV_Pos (23U) 1825 #define ADC12_CSR_AWD1_SLV_Msk (0x1UL << ADC12_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ 1826 #define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ 1827 #define ADC12_CSR_AWD2_SLV_Pos (24U) 1828 #define ADC12_CSR_AWD2_SLV_Msk (0x1UL << ADC12_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ 1829 #define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ 1830 #define ADC12_CSR_AWD3_SLV_Pos (25U) 1831 #define ADC12_CSR_AWD3_SLV_Msk (0x1UL << ADC12_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ 1832 #define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ 1833 #define ADC12_CSR_JQOVF_SLV_Pos (26U) 1834 #define ADC12_CSR_JQOVF_SLV_Msk (0x1UL << ADC12_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ 1835 #define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ 1836 1837 /*************** Bit definition for ADC12_COMMON_CCR register ***************/ 1838 #define ADC12_CCR_MULTI_Pos (0U) 1839 #define ADC12_CCR_MULTI_Msk (0x1FUL << ADC12_CCR_MULTI_Pos) /*!< 0x0000001F */ 1840 #define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk /*!< Multi ADC mode selection */ 1841 #define ADC12_CCR_MULTI_0 (0x01UL << ADC12_CCR_MULTI_Pos) /*!< 0x00000001 */ 1842 #define ADC12_CCR_MULTI_1 (0x02UL << ADC12_CCR_MULTI_Pos) /*!< 0x00000002 */ 1843 #define ADC12_CCR_MULTI_2 (0x04UL << ADC12_CCR_MULTI_Pos) /*!< 0x00000004 */ 1844 #define ADC12_CCR_MULTI_3 (0x08UL << ADC12_CCR_MULTI_Pos) /*!< 0x00000008 */ 1845 #define ADC12_CCR_MULTI_4 (0x10UL << ADC12_CCR_MULTI_Pos) /*!< 0x00000010 */ 1846 #define ADC12_CCR_DELAY_Pos (8U) 1847 #define ADC12_CCR_DELAY_Msk (0xFUL << ADC12_CCR_DELAY_Pos) /*!< 0x00000F00 */ 1848 #define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ 1849 #define ADC12_CCR_DELAY_0 (0x1UL << ADC12_CCR_DELAY_Pos) /*!< 0x00000100 */ 1850 #define ADC12_CCR_DELAY_1 (0x2UL << ADC12_CCR_DELAY_Pos) /*!< 0x00000200 */ 1851 #define ADC12_CCR_DELAY_2 (0x4UL << ADC12_CCR_DELAY_Pos) /*!< 0x00000400 */ 1852 #define ADC12_CCR_DELAY_3 (0x8UL << ADC12_CCR_DELAY_Pos) /*!< 0x00000800 */ 1853 #define ADC12_CCR_DMACFG_Pos (13U) 1854 #define ADC12_CCR_DMACFG_Msk (0x1UL << ADC12_CCR_DMACFG_Pos) /*!< 0x00002000 */ 1855 #define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk /*!< DMA configuration for multi-ADC mode */ 1856 #define ADC12_CCR_MDMA_Pos (14U) 1857 #define ADC12_CCR_MDMA_Msk (0x3UL << ADC12_CCR_MDMA_Pos) /*!< 0x0000C000 */ 1858 #define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk /*!< DMA mode for multi-ADC mode */ 1859 #define ADC12_CCR_MDMA_0 (0x1UL << ADC12_CCR_MDMA_Pos) /*!< 0x00004000 */ 1860 #define ADC12_CCR_MDMA_1 (0x2UL << ADC12_CCR_MDMA_Pos) /*!< 0x00008000 */ 1861 #define ADC12_CCR_CKMODE_Pos (16U) 1862 #define ADC12_CCR_CKMODE_Msk (0x3UL << ADC12_CCR_CKMODE_Pos) /*!< 0x00030000 */ 1863 #define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk /*!< ADC clock mode */ 1864 #define ADC12_CCR_CKMODE_0 (0x1UL << ADC12_CCR_CKMODE_Pos) /*!< 0x00010000 */ 1865 #define ADC12_CCR_CKMODE_1 (0x2UL << ADC12_CCR_CKMODE_Pos) /*!< 0x00020000 */ 1866 #define ADC12_CCR_VREFEN_Pos (22U) 1867 #define ADC12_CCR_VREFEN_Msk (0x1UL << ADC12_CCR_VREFEN_Pos) /*!< 0x00400000 */ 1868 #define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk /*!< VREFINT enable */ 1869 #define ADC12_CCR_TSEN_Pos (23U) 1870 #define ADC12_CCR_TSEN_Msk (0x1UL << ADC12_CCR_TSEN_Pos) /*!< 0x00800000 */ 1871 #define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk /*!< Temperature sensor enable */ 1872 #define ADC12_CCR_VBATEN_Pos (24U) 1873 #define ADC12_CCR_VBATEN_Msk (0x1UL << ADC12_CCR_VBATEN_Pos) /*!< 0x01000000 */ 1874 #define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk /*!< VBAT enable */ 1875 1876 /*************** Bit definition for ADC12_COMMON_CDR register ***************/ 1877 #define ADC12_CDR_RDATA_MST_Pos (0U) 1878 #define ADC12_CDR_RDATA_MST_Msk (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ 1879 #define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */ 1880 #define ADC12_CDR_RDATA_MST_0 (0x0001UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ 1881 #define ADC12_CDR_RDATA_MST_1 (0x0002UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ 1882 #define ADC12_CDR_RDATA_MST_2 (0x0004UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ 1883 #define ADC12_CDR_RDATA_MST_3 (0x0008UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ 1884 #define ADC12_CDR_RDATA_MST_4 (0x0010UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ 1885 #define ADC12_CDR_RDATA_MST_5 (0x0020UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ 1886 #define ADC12_CDR_RDATA_MST_6 (0x0040UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ 1887 #define ADC12_CDR_RDATA_MST_7 (0x0080UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ 1888 #define ADC12_CDR_RDATA_MST_8 (0x0100UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ 1889 #define ADC12_CDR_RDATA_MST_9 (0x0200UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ 1890 #define ADC12_CDR_RDATA_MST_10 (0x0400UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ 1891 #define ADC12_CDR_RDATA_MST_11 (0x0800UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ 1892 #define ADC12_CDR_RDATA_MST_12 (0x1000UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ 1893 #define ADC12_CDR_RDATA_MST_13 (0x2000UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ 1894 #define ADC12_CDR_RDATA_MST_14 (0x4000UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ 1895 #define ADC12_CDR_RDATA_MST_15 (0x8000UL << ADC12_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ 1896 1897 #define ADC12_CDR_RDATA_SLV_Pos (16U) 1898 #define ADC12_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ 1899 #define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */ 1900 #define ADC12_CDR_RDATA_SLV_0 (0x0001UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ 1901 #define ADC12_CDR_RDATA_SLV_1 (0x0002UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ 1902 #define ADC12_CDR_RDATA_SLV_2 (0x0004UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ 1903 #define ADC12_CDR_RDATA_SLV_3 (0x0008UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ 1904 #define ADC12_CDR_RDATA_SLV_4 (0x0010UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ 1905 #define ADC12_CDR_RDATA_SLV_5 (0x0020UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ 1906 #define ADC12_CDR_RDATA_SLV_6 (0x0040UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ 1907 #define ADC12_CDR_RDATA_SLV_7 (0x0080UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ 1908 #define ADC12_CDR_RDATA_SLV_8 (0x0100UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ 1909 #define ADC12_CDR_RDATA_SLV_9 (0x0200UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ 1910 #define ADC12_CDR_RDATA_SLV_10 (0x0400UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ 1911 #define ADC12_CDR_RDATA_SLV_11 (0x0800UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ 1912 #define ADC12_CDR_RDATA_SLV_12 (0x1000UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ 1913 #define ADC12_CDR_RDATA_SLV_13 (0x2000UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ 1914 #define ADC12_CDR_RDATA_SLV_14 (0x4000UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ 1915 #define ADC12_CDR_RDATA_SLV_15 (0x8000UL << ADC12_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ 1916 1917 /******************** Bit definition for ADC_CSR register *******************/ 1918 #define ADC_CSR_ADRDY_MST_Pos (0U) 1919 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ 1920 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ 1921 #define ADC_CSR_EOSMP_MST_Pos (1U) 1922 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ 1923 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ 1924 #define ADC_CSR_EOC_MST_Pos (2U) 1925 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ 1926 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ 1927 #define ADC_CSR_EOS_MST_Pos (3U) 1928 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ 1929 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ 1930 #define ADC_CSR_OVR_MST_Pos (4U) 1931 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ 1932 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ 1933 #define ADC_CSR_JEOC_MST_Pos (5U) 1934 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ 1935 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ 1936 #define ADC_CSR_JEOS_MST_Pos (6U) 1937 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ 1938 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1939 #define ADC_CSR_AWD1_MST_Pos (7U) 1940 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ 1941 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1942 #define ADC_CSR_AWD2_MST_Pos (8U) 1943 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ 1944 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ 1945 #define ADC_CSR_AWD3_MST_Pos (9U) 1946 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ 1947 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ 1948 #define ADC_CSR_JQOVF_MST_Pos (10U) 1949 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ 1950 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ 1951 1952 #define ADC_CSR_ADRDY_SLV_Pos (16U) 1953 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ 1954 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ 1955 #define ADC_CSR_EOSMP_SLV_Pos (17U) 1956 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ 1957 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ 1958 #define ADC_CSR_EOC_SLV_Pos (18U) 1959 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ 1960 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ 1961 #define ADC_CSR_EOS_SLV_Pos (19U) 1962 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ 1963 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ 1964 #define ADC_CSR_OVR_SLV_Pos (20U) 1965 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ 1966 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ 1967 #define ADC_CSR_JEOC_SLV_Pos (21U) 1968 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ 1969 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ 1970 #define ADC_CSR_JEOS_SLV_Pos (22U) 1971 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ 1972 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ 1973 #define ADC_CSR_AWD1_SLV_Pos (23U) 1974 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ 1975 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ 1976 #define ADC_CSR_AWD2_SLV_Pos (24U) 1977 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ 1978 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ 1979 #define ADC_CSR_AWD3_SLV_Pos (25U) 1980 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ 1981 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ 1982 #define ADC_CSR_JQOVF_SLV_Pos (26U) 1983 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ 1984 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ 1985 1986 /* Legacy defines */ 1987 #define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST 1988 #define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST 1989 #define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST 1990 #define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST 1991 #define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST 1992 #define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST 1993 1994 #define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV 1995 #define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV 1996 #define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV 1997 #define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV 1998 #define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV 1999 #define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV 2000 2001 /******************** Bit definition for ADC_CCR register *******************/ 2002 #define ADC_CCR_DUAL_Pos (0U) 2003 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ 2004 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ 2005 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ 2006 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ 2007 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ 2008 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ 2009 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ 2010 2011 #define ADC_CCR_DELAY_Pos (8U) 2012 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ 2013 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ 2014 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ 2015 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ 2016 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ 2017 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ 2018 2019 #define ADC_CCR_DMACFG_Pos (13U) 2020 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ 2021 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ 2022 2023 #define ADC_CCR_MDMA_Pos (14U) 2024 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ 2025 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ 2026 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ 2027 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ 2028 2029 #define ADC_CCR_CKMODE_Pos (16U) 2030 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ 2031 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ 2032 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ 2033 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ 2034 2035 #define ADC_CCR_VREFEN_Pos (22U) 2036 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 2037 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 2038 #define ADC_CCR_TSEN_Pos (23U) 2039 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 2040 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 2041 #define ADC_CCR_VBATEN_Pos (24U) 2042 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 2043 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 2044 2045 /* Legacy defines */ 2046 #define ADC_CCR_MULTI (ADC_CCR_DUAL) 2047 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) 2048 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) 2049 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) 2050 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) 2051 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) 2052 2053 /******************** Bit definition for ADC_CDR register *******************/ 2054 #define ADC_CDR_RDATA_MST_Pos (0U) 2055 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ 2056 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ 2057 #define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ 2058 #define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ 2059 #define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ 2060 #define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ 2061 #define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ 2062 #define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ 2063 #define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ 2064 #define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ 2065 #define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ 2066 #define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ 2067 #define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ 2068 #define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ 2069 #define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ 2070 #define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ 2071 #define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ 2072 #define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ 2073 2074 #define ADC_CDR_RDATA_SLV_Pos (16U) 2075 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ 2076 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ 2077 #define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ 2078 #define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ 2079 #define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ 2080 #define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ 2081 #define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ 2082 #define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ 2083 #define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ 2084 #define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ 2085 #define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ 2086 #define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ 2087 #define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ 2088 #define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ 2089 #define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ 2090 #define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ 2091 #define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ 2092 #define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ 2093 2094 /******************************************************************************/ 2095 /* */ 2096 /* Analog Comparators (COMP) */ 2097 /* */ 2098 /******************************************************************************/ 2099 2100 #define COMP_V1_3_0_0 /*!< Comparator IP version */ 2101 2102 /********************** Bit definition for COMP2_CSR register ***************/ 2103 #define COMP2_CSR_COMP2EN_Pos (0U) 2104 #define COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */ 2105 #define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */ 2106 #define COMP2_CSR_COMP2INSEL_Pos (4U) 2107 #define COMP2_CSR_COMP2INSEL_Msk (0x40007UL << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */ 2108 #define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */ 2109 #define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */ 2110 #define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */ 2111 #define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */ 2112 #define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */ 2113 #define COMP2_CSR_COMP2OUTSEL_Pos (10U) 2114 #define COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */ 2115 #define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */ 2116 #define COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000400 */ 2117 #define COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00000800 */ 2118 #define COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00001000 */ 2119 #define COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00002000 */ 2120 #define COMP2_CSR_COMP2POL_Pos (15U) 2121 #define COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos) /*!< 0x00008000 */ 2122 #define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk /*!< COMP2 output polarity */ 2123 #define COMP2_CSR_COMP2BLANKING_Pos (18U) 2124 #define COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */ 2125 #define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk /*!< COMP2 blanking */ 2126 #define COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */ 2127 #define COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */ 2128 #define COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */ 2129 #define COMP2_CSR_COMP2OUT_Pos (30U) 2130 #define COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos) /*!< 0x40000000 */ 2131 #define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk /*!< COMP2 output level */ 2132 #define COMP2_CSR_COMP2LOCK_Pos (31U) 2133 #define COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 2134 #define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 2135 2136 /********************** Bit definition for COMP4_CSR register ***************/ 2137 #define COMP4_CSR_COMP4EN_Pos (0U) 2138 #define COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */ 2139 #define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */ 2140 #define COMP4_CSR_COMP4INSEL_Pos (4U) 2141 #define COMP4_CSR_COMP4INSEL_Msk (0x40007UL << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */ 2142 #define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */ 2143 #define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */ 2144 #define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */ 2145 #define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */ 2146 #define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */ 2147 #define COMP4_CSR_COMP4OUTSEL_Pos (10U) 2148 #define COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */ 2149 #define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */ 2150 #define COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000400 */ 2151 #define COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00000800 */ 2152 #define COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00001000 */ 2153 #define COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00002000 */ 2154 #define COMP4_CSR_COMP4POL_Pos (15U) 2155 #define COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos) /*!< 0x00008000 */ 2156 #define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk /*!< COMP4 output polarity */ 2157 #define COMP4_CSR_COMP4BLANKING_Pos (18U) 2158 #define COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */ 2159 #define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk /*!< COMP4 blanking */ 2160 #define COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */ 2161 #define COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */ 2162 #define COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */ 2163 #define COMP4_CSR_COMP4OUT_Pos (30U) 2164 #define COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos) /*!< 0x40000000 */ 2165 #define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk /*!< COMP4 output level */ 2166 #define COMP4_CSR_COMP4LOCK_Pos (31U) 2167 #define COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos) /*!< 0x80000000 */ 2168 #define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk /*!< COMP4 lock */ 2169 2170 /********************** Bit definition for COMP6_CSR register ***************/ 2171 #define COMP6_CSR_COMP6EN_Pos (0U) 2172 #define COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */ 2173 #define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */ 2174 #define COMP6_CSR_COMP6INSEL_Pos (4U) 2175 #define COMP6_CSR_COMP6INSEL_Msk (0x40007UL << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */ 2176 #define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */ 2177 #define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */ 2178 #define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */ 2179 #define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */ 2180 #define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */ 2181 #define COMP6_CSR_COMP6OUTSEL_Pos (10U) 2182 #define COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */ 2183 #define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */ 2184 #define COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000400 */ 2185 #define COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00000800 */ 2186 #define COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00001000 */ 2187 #define COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00002000 */ 2188 #define COMP6_CSR_COMP6POL_Pos (15U) 2189 #define COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos) /*!< 0x00008000 */ 2190 #define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk /*!< COMP6 output polarity */ 2191 #define COMP6_CSR_COMP6BLANKING_Pos (18U) 2192 #define COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */ 2193 #define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk /*!< COMP6 blanking */ 2194 #define COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */ 2195 #define COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */ 2196 #define COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */ 2197 #define COMP6_CSR_COMP6OUT_Pos (30U) 2198 #define COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos) /*!< 0x40000000 */ 2199 #define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk /*!< COMP6 output level */ 2200 #define COMP6_CSR_COMP6LOCK_Pos (31U) 2201 #define COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos) /*!< 0x80000000 */ 2202 #define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk /*!< COMP6 lock */ 2203 2204 /********************** Bit definition for COMP_CSR register ****************/ 2205 #define COMP_CSR_COMPxEN_Pos (0U) 2206 #define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 2207 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 2208 #define COMP_CSR_COMPxINSEL_Pos (4U) 2209 #define COMP_CSR_COMPxINSEL_Msk (0x40007UL << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */ 2210 #define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */ 2211 #define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */ 2212 #define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */ 2213 #define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */ 2214 #define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */ 2215 #define COMP_CSR_COMPxOUTSEL_Pos (10U) 2216 #define COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */ 2217 #define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */ 2218 #define COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000400 */ 2219 #define COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00000800 */ 2220 #define COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00001000 */ 2221 #define COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00002000 */ 2222 #define COMP_CSR_COMPxPOL_Pos (15U) 2223 #define COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos) /*!< 0x00008000 */ 2224 #define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk /*!< COMPx output polarity */ 2225 #define COMP_CSR_COMPxBLANKING_Pos (18U) 2226 #define COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x000C0000 */ 2227 #define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk /*!< COMPx blanking */ 2228 #define COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00040000 */ 2229 #define COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00080000 */ 2230 #define COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos) /*!< 0x00100000 */ 2231 #define COMP_CSR_COMPxOUT_Pos (30U) 2232 #define COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos) /*!< 0x40000000 */ 2233 #define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk /*!< COMPx output level */ 2234 #define COMP_CSR_COMPxLOCK_Pos (31U) 2235 #define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ 2236 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 2237 2238 /******************************************************************************/ 2239 /* */ 2240 /* Operational Amplifier (OPAMP) */ 2241 /* */ 2242 /******************************************************************************/ 2243 /********************* Bit definition for OPAMP2_CSR register ***************/ 2244 #define OPAMP2_CSR_OPAMP2EN_Pos (0U) 2245 #define OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos) /*!< 0x00000001 */ 2246 #define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk /*!< OPAMP2 enable */ 2247 #define OPAMP2_CSR_FORCEVP_Pos (1U) 2248 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */ 2249 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ 2250 #define OPAMP2_CSR_VPSEL_Pos (2U) 2251 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */ 2252 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverting input selection */ 2253 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */ 2254 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */ 2255 #define OPAMP2_CSR_VMSEL_Pos (5U) 2256 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */ 2257 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */ 2258 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */ 2259 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */ 2260 #define OPAMP2_CSR_TCMEN_Pos (7U) 2261 #define OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos) /*!< 0x00000080 */ 2262 #define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ 2263 #define OPAMP2_CSR_VMSSEL_Pos (8U) 2264 #define OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos) /*!< 0x00000100 */ 2265 #define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ 2266 #define OPAMP2_CSR_VPSSEL_Pos (9U) 2267 #define OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000600 */ 2268 #define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ 2269 #define OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000200 */ 2270 #define OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos) /*!< 0x00000400 */ 2271 #define OPAMP2_CSR_CALON_Pos (11U) 2272 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */ 2273 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */ 2274 #define OPAMP2_CSR_CALSEL_Pos (12U) 2275 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */ 2276 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */ 2277 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */ 2278 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */ 2279 #define OPAMP2_CSR_PGGAIN_Pos (14U) 2280 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ 2281 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ 2282 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */ 2283 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */ 2284 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */ 2285 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */ 2286 #define OPAMP2_CSR_USERTRIM_Pos (18U) 2287 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */ 2288 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */ 2289 #define OPAMP2_CSR_TRIMOFFSETP_Pos (19U) 2290 #define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ 2291 #define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ 2292 #define OPAMP2_CSR_TRIMOFFSETN_Pos (24U) 2293 #define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ 2294 #define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ 2295 #define OPAMP2_CSR_TSTREF_Pos (29U) 2296 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */ 2297 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ 2298 #define OPAMP2_CSR_OUTCAL_Pos (30U) 2299 #define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */ 2300 #define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ 2301 #define OPAMP2_CSR_LOCK_Pos (31U) 2302 #define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */ 2303 #define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */ 2304 2305 /********************* Bit definition for OPAMPx_CSR register ***************/ 2306 #define OPAMP_CSR_OPAMPxEN_Pos (0U) 2307 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ 2308 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ 2309 #define OPAMP_CSR_FORCEVP_Pos (1U) 2310 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ 2311 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ 2312 #define OPAMP_CSR_VPSEL_Pos (2U) 2313 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ 2314 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */ 2315 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ 2316 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ 2317 #define OPAMP_CSR_VMSEL_Pos (5U) 2318 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ 2319 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ 2320 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ 2321 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ 2322 #define OPAMP_CSR_TCMEN_Pos (7U) 2323 #define OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos) /*!< 0x00000080 */ 2324 #define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk /*!< Timer-Controlled Mux mode enable */ 2325 #define OPAMP_CSR_VMSSEL_Pos (8U) 2326 #define OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos) /*!< 0x00000100 */ 2327 #define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk /*!< Inverting input secondary selection */ 2328 #define OPAMP_CSR_VPSSEL_Pos (9U) 2329 #define OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000600 */ 2330 #define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk /*!< Non inverting input secondary selection */ 2331 #define OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000200 */ 2332 #define OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos) /*!< 0x00000400 */ 2333 #define OPAMP_CSR_CALON_Pos (11U) 2334 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ 2335 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ 2336 #define OPAMP_CSR_CALSEL_Pos (12U) 2337 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ 2338 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ 2339 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ 2340 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ 2341 #define OPAMP_CSR_PGGAIN_Pos (14U) 2342 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ 2343 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ 2344 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ 2345 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ 2346 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ 2347 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ 2348 #define OPAMP_CSR_USERTRIM_Pos (18U) 2349 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */ 2350 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ 2351 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U) 2352 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ 2353 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ 2354 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U) 2355 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ 2356 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ 2357 #define OPAMP_CSR_TSTREF_Pos (29U) 2358 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */ 2359 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */ 2360 #define OPAMP_CSR_OUTCAL_Pos (30U) 2361 #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ 2362 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ 2363 #define OPAMP_CSR_LOCK_Pos (31U) 2364 #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 2365 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */ 2366 2367 /******************************************************************************/ 2368 /* */ 2369 /* Controller Area Network (CAN ) */ 2370 /* */ 2371 /******************************************************************************/ 2372 /******************* Bit definition for CAN_MCR register ********************/ 2373 #define CAN_MCR_INRQ_Pos (0U) 2374 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ 2375 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ 2376 #define CAN_MCR_SLEEP_Pos (1U) 2377 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ 2378 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ 2379 #define CAN_MCR_TXFP_Pos (2U) 2380 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ 2381 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ 2382 #define CAN_MCR_RFLM_Pos (3U) 2383 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ 2384 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ 2385 #define CAN_MCR_NART_Pos (4U) 2386 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ 2387 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ 2388 #define CAN_MCR_AWUM_Pos (5U) 2389 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ 2390 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ 2391 #define CAN_MCR_ABOM_Pos (6U) 2392 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ 2393 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ 2394 #define CAN_MCR_TTCM_Pos (7U) 2395 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ 2396 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ 2397 #define CAN_MCR_RESET_Pos (15U) 2398 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ 2399 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ 2400 2401 /******************* Bit definition for CAN_MSR register ********************/ 2402 #define CAN_MSR_INAK_Pos (0U) 2403 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ 2404 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ 2405 #define CAN_MSR_SLAK_Pos (1U) 2406 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ 2407 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ 2408 #define CAN_MSR_ERRI_Pos (2U) 2409 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ 2410 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ 2411 #define CAN_MSR_WKUI_Pos (3U) 2412 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ 2413 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ 2414 #define CAN_MSR_SLAKI_Pos (4U) 2415 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ 2416 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ 2417 #define CAN_MSR_TXM_Pos (8U) 2418 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ 2419 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ 2420 #define CAN_MSR_RXM_Pos (9U) 2421 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ 2422 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ 2423 #define CAN_MSR_SAMP_Pos (10U) 2424 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ 2425 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ 2426 #define CAN_MSR_RX_Pos (11U) 2427 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ 2428 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ 2429 2430 /******************* Bit definition for CAN_TSR register ********************/ 2431 #define CAN_TSR_RQCP0_Pos (0U) 2432 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ 2433 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ 2434 #define CAN_TSR_TXOK0_Pos (1U) 2435 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ 2436 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ 2437 #define CAN_TSR_ALST0_Pos (2U) 2438 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ 2439 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ 2440 #define CAN_TSR_TERR0_Pos (3U) 2441 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ 2442 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ 2443 #define CAN_TSR_ABRQ0_Pos (7U) 2444 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ 2445 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ 2446 #define CAN_TSR_RQCP1_Pos (8U) 2447 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ 2448 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ 2449 #define CAN_TSR_TXOK1_Pos (9U) 2450 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ 2451 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ 2452 #define CAN_TSR_ALST1_Pos (10U) 2453 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ 2454 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ 2455 #define CAN_TSR_TERR1_Pos (11U) 2456 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ 2457 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ 2458 #define CAN_TSR_ABRQ1_Pos (15U) 2459 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ 2460 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ 2461 #define CAN_TSR_RQCP2_Pos (16U) 2462 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ 2463 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ 2464 #define CAN_TSR_TXOK2_Pos (17U) 2465 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ 2466 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ 2467 #define CAN_TSR_ALST2_Pos (18U) 2468 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ 2469 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ 2470 #define CAN_TSR_TERR2_Pos (19U) 2471 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ 2472 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ 2473 #define CAN_TSR_ABRQ2_Pos (23U) 2474 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ 2475 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ 2476 #define CAN_TSR_CODE_Pos (24U) 2477 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ 2478 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ 2479 2480 #define CAN_TSR_TME_Pos (26U) 2481 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ 2482 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ 2483 #define CAN_TSR_TME0_Pos (26U) 2484 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ 2485 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ 2486 #define CAN_TSR_TME1_Pos (27U) 2487 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ 2488 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ 2489 #define CAN_TSR_TME2_Pos (28U) 2490 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ 2491 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ 2492 2493 #define CAN_TSR_LOW_Pos (29U) 2494 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ 2495 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ 2496 #define CAN_TSR_LOW0_Pos (29U) 2497 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ 2498 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ 2499 #define CAN_TSR_LOW1_Pos (30U) 2500 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ 2501 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ 2502 #define CAN_TSR_LOW2_Pos (31U) 2503 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ 2504 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ 2505 2506 /******************* Bit definition for CAN_RF0R register *******************/ 2507 #define CAN_RF0R_FMP0_Pos (0U) 2508 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ 2509 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ 2510 #define CAN_RF0R_FULL0_Pos (3U) 2511 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ 2512 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ 2513 #define CAN_RF0R_FOVR0_Pos (4U) 2514 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ 2515 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ 2516 #define CAN_RF0R_RFOM0_Pos (5U) 2517 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ 2518 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ 2519 2520 /******************* Bit definition for CAN_RF1R register *******************/ 2521 #define CAN_RF1R_FMP1_Pos (0U) 2522 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ 2523 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ 2524 #define CAN_RF1R_FULL1_Pos (3U) 2525 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ 2526 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ 2527 #define CAN_RF1R_FOVR1_Pos (4U) 2528 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ 2529 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ 2530 #define CAN_RF1R_RFOM1_Pos (5U) 2531 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ 2532 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ 2533 2534 /******************** Bit definition for CAN_IER register *******************/ 2535 #define CAN_IER_TMEIE_Pos (0U) 2536 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ 2537 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ 2538 #define CAN_IER_FMPIE0_Pos (1U) 2539 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ 2540 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ 2541 #define CAN_IER_FFIE0_Pos (2U) 2542 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ 2543 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ 2544 #define CAN_IER_FOVIE0_Pos (3U) 2545 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ 2546 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ 2547 #define CAN_IER_FMPIE1_Pos (4U) 2548 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ 2549 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ 2550 #define CAN_IER_FFIE1_Pos (5U) 2551 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ 2552 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ 2553 #define CAN_IER_FOVIE1_Pos (6U) 2554 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ 2555 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ 2556 #define CAN_IER_EWGIE_Pos (8U) 2557 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ 2558 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ 2559 #define CAN_IER_EPVIE_Pos (9U) 2560 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ 2561 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ 2562 #define CAN_IER_BOFIE_Pos (10U) 2563 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ 2564 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ 2565 #define CAN_IER_LECIE_Pos (11U) 2566 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ 2567 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ 2568 #define CAN_IER_ERRIE_Pos (15U) 2569 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ 2570 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ 2571 #define CAN_IER_WKUIE_Pos (16U) 2572 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ 2573 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ 2574 #define CAN_IER_SLKIE_Pos (17U) 2575 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ 2576 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ 2577 2578 /******************** Bit definition for CAN_ESR register *******************/ 2579 #define CAN_ESR_EWGF_Pos (0U) 2580 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ 2581 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ 2582 #define CAN_ESR_EPVF_Pos (1U) 2583 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ 2584 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ 2585 #define CAN_ESR_BOFF_Pos (2U) 2586 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ 2587 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ 2588 2589 #define CAN_ESR_LEC_Pos (4U) 2590 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ 2591 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ 2592 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ 2593 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ 2594 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ 2595 2596 #define CAN_ESR_TEC_Pos (16U) 2597 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ 2598 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ 2599 #define CAN_ESR_REC_Pos (24U) 2600 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ 2601 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ 2602 2603 /******************* Bit definition for CAN_BTR register ********************/ 2604 #define CAN_BTR_BRP_Pos (0U) 2605 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ 2606 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ 2607 #define CAN_BTR_TS1_Pos (16U) 2608 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ 2609 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ 2610 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ 2611 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ 2612 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ 2613 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ 2614 #define CAN_BTR_TS2_Pos (20U) 2615 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ 2616 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ 2617 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ 2618 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ 2619 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ 2620 #define CAN_BTR_SJW_Pos (24U) 2621 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ 2622 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ 2623 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ 2624 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ 2625 #define CAN_BTR_LBKM_Pos (30U) 2626 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ 2627 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ 2628 #define CAN_BTR_SILM_Pos (31U) 2629 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ 2630 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ 2631 2632 /*!<Mailbox registers */ 2633 /****************** Bit definition for CAN_TI0R register ********************/ 2634 #define CAN_TI0R_TXRQ_Pos (0U) 2635 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ 2636 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2637 #define CAN_TI0R_RTR_Pos (1U) 2638 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ 2639 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ 2640 #define CAN_TI0R_IDE_Pos (2U) 2641 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ 2642 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ 2643 #define CAN_TI0R_EXID_Pos (3U) 2644 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2645 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ 2646 #define CAN_TI0R_STID_Pos (21U) 2647 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ 2648 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2649 2650 /****************** Bit definition for CAN_TDT0R register *******************/ 2651 #define CAN_TDT0R_DLC_Pos (0U) 2652 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ 2653 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ 2654 #define CAN_TDT0R_TGT_Pos (8U) 2655 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ 2656 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ 2657 #define CAN_TDT0R_TIME_Pos (16U) 2658 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2659 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ 2660 2661 /****************** Bit definition for CAN_TDL0R register *******************/ 2662 #define CAN_TDL0R_DATA0_Pos (0U) 2663 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ 2664 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ 2665 #define CAN_TDL0R_DATA1_Pos (8U) 2666 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2667 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ 2668 #define CAN_TDL0R_DATA2_Pos (16U) 2669 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2670 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ 2671 #define CAN_TDL0R_DATA3_Pos (24U) 2672 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2673 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ 2674 2675 /****************** Bit definition for CAN_TDH0R register *******************/ 2676 #define CAN_TDH0R_DATA4_Pos (0U) 2677 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ 2678 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ 2679 #define CAN_TDH0R_DATA5_Pos (8U) 2680 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2681 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ 2682 #define CAN_TDH0R_DATA6_Pos (16U) 2683 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2684 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ 2685 #define CAN_TDH0R_DATA7_Pos (24U) 2686 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2687 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ 2688 2689 /******************* Bit definition for CAN_TI1R register *******************/ 2690 #define CAN_TI1R_TXRQ_Pos (0U) 2691 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ 2692 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2693 #define CAN_TI1R_RTR_Pos (1U) 2694 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ 2695 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ 2696 #define CAN_TI1R_IDE_Pos (2U) 2697 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ 2698 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ 2699 #define CAN_TI1R_EXID_Pos (3U) 2700 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2701 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ 2702 #define CAN_TI1R_STID_Pos (21U) 2703 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ 2704 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2705 2706 /******************* Bit definition for CAN_TDT1R register ******************/ 2707 #define CAN_TDT1R_DLC_Pos (0U) 2708 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ 2709 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ 2710 #define CAN_TDT1R_TGT_Pos (8U) 2711 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ 2712 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ 2713 #define CAN_TDT1R_TIME_Pos (16U) 2714 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2715 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ 2716 2717 /******************* Bit definition for CAN_TDL1R register ******************/ 2718 #define CAN_TDL1R_DATA0_Pos (0U) 2719 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ 2720 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ 2721 #define CAN_TDL1R_DATA1_Pos (8U) 2722 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2723 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ 2724 #define CAN_TDL1R_DATA2_Pos (16U) 2725 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2726 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ 2727 #define CAN_TDL1R_DATA3_Pos (24U) 2728 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2729 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ 2730 2731 /******************* Bit definition for CAN_TDH1R register ******************/ 2732 #define CAN_TDH1R_DATA4_Pos (0U) 2733 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ 2734 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ 2735 #define CAN_TDH1R_DATA5_Pos (8U) 2736 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2737 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ 2738 #define CAN_TDH1R_DATA6_Pos (16U) 2739 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2740 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ 2741 #define CAN_TDH1R_DATA7_Pos (24U) 2742 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2743 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ 2744 2745 /******************* Bit definition for CAN_TI2R register *******************/ 2746 #define CAN_TI2R_TXRQ_Pos (0U) 2747 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ 2748 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ 2749 #define CAN_TI2R_RTR_Pos (1U) 2750 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ 2751 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ 2752 #define CAN_TI2R_IDE_Pos (2U) 2753 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ 2754 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ 2755 #define CAN_TI2R_EXID_Pos (3U) 2756 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ 2757 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ 2758 #define CAN_TI2R_STID_Pos (21U) 2759 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ 2760 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2761 2762 /******************* Bit definition for CAN_TDT2R register ******************/ 2763 #define CAN_TDT2R_DLC_Pos (0U) 2764 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ 2765 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ 2766 #define CAN_TDT2R_TGT_Pos (8U) 2767 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ 2768 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ 2769 #define CAN_TDT2R_TIME_Pos (16U) 2770 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ 2771 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ 2772 2773 /******************* Bit definition for CAN_TDL2R register ******************/ 2774 #define CAN_TDL2R_DATA0_Pos (0U) 2775 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ 2776 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ 2777 #define CAN_TDL2R_DATA1_Pos (8U) 2778 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ 2779 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ 2780 #define CAN_TDL2R_DATA2_Pos (16U) 2781 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ 2782 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ 2783 #define CAN_TDL2R_DATA3_Pos (24U) 2784 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ 2785 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ 2786 2787 /******************* Bit definition for CAN_TDH2R register ******************/ 2788 #define CAN_TDH2R_DATA4_Pos (0U) 2789 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ 2790 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ 2791 #define CAN_TDH2R_DATA5_Pos (8U) 2792 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ 2793 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ 2794 #define CAN_TDH2R_DATA6_Pos (16U) 2795 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ 2796 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ 2797 #define CAN_TDH2R_DATA7_Pos (24U) 2798 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ 2799 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ 2800 2801 /******************* Bit definition for CAN_RI0R register *******************/ 2802 #define CAN_RI0R_RTR_Pos (1U) 2803 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ 2804 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ 2805 #define CAN_RI0R_IDE_Pos (2U) 2806 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ 2807 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ 2808 #define CAN_RI0R_EXID_Pos (3U) 2809 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ 2810 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ 2811 #define CAN_RI0R_STID_Pos (21U) 2812 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ 2813 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2814 2815 /******************* Bit definition for CAN_RDT0R register ******************/ 2816 #define CAN_RDT0R_DLC_Pos (0U) 2817 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ 2818 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ 2819 #define CAN_RDT0R_FMI_Pos (8U) 2820 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ 2821 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ 2822 #define CAN_RDT0R_TIME_Pos (16U) 2823 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 2824 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ 2825 2826 /******************* Bit definition for CAN_RDL0R register ******************/ 2827 #define CAN_RDL0R_DATA0_Pos (0U) 2828 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ 2829 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ 2830 #define CAN_RDL0R_DATA1_Pos (8U) 2831 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 2832 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ 2833 #define CAN_RDL0R_DATA2_Pos (16U) 2834 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 2835 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ 2836 #define CAN_RDL0R_DATA3_Pos (24U) 2837 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ 2838 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ 2839 2840 /******************* Bit definition for CAN_RDH0R register ******************/ 2841 #define CAN_RDH0R_DATA4_Pos (0U) 2842 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ 2843 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ 2844 #define CAN_RDH0R_DATA5_Pos (8U) 2845 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 2846 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ 2847 #define CAN_RDH0R_DATA6_Pos (16U) 2848 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 2849 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ 2850 #define CAN_RDH0R_DATA7_Pos (24U) 2851 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ 2852 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ 2853 2854 /******************* Bit definition for CAN_RI1R register *******************/ 2855 #define CAN_RI1R_RTR_Pos (1U) 2856 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ 2857 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ 2858 #define CAN_RI1R_IDE_Pos (2U) 2859 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ 2860 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ 2861 #define CAN_RI1R_EXID_Pos (3U) 2862 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ 2863 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ 2864 #define CAN_RI1R_STID_Pos (21U) 2865 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ 2866 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ 2867 2868 /******************* Bit definition for CAN_RDT1R register ******************/ 2869 #define CAN_RDT1R_DLC_Pos (0U) 2870 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ 2871 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ 2872 #define CAN_RDT1R_FMI_Pos (8U) 2873 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ 2874 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ 2875 #define CAN_RDT1R_TIME_Pos (16U) 2876 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 2877 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ 2878 2879 /******************* Bit definition for CAN_RDL1R register ******************/ 2880 #define CAN_RDL1R_DATA0_Pos (0U) 2881 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ 2882 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ 2883 #define CAN_RDL1R_DATA1_Pos (8U) 2884 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 2885 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ 2886 #define CAN_RDL1R_DATA2_Pos (16U) 2887 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 2888 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ 2889 #define CAN_RDL1R_DATA3_Pos (24U) 2890 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ 2891 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ 2892 2893 /******************* Bit definition for CAN_RDH1R register ******************/ 2894 #define CAN_RDH1R_DATA4_Pos (0U) 2895 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ 2896 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ 2897 #define CAN_RDH1R_DATA5_Pos (8U) 2898 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 2899 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ 2900 #define CAN_RDH1R_DATA6_Pos (16U) 2901 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 2902 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ 2903 #define CAN_RDH1R_DATA7_Pos (24U) 2904 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ 2905 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ 2906 2907 /*!<CAN filter registers */ 2908 /******************* Bit definition for CAN_FMR register ********************/ 2909 #define CAN_FMR_FINIT_Pos (0U) 2910 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ 2911 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ 2912 2913 /******************* Bit definition for CAN_FM1R register *******************/ 2914 #define CAN_FM1R_FBM_Pos (0U) 2915 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ 2916 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ 2917 #define CAN_FM1R_FBM0_Pos (0U) 2918 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ 2919 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ 2920 #define CAN_FM1R_FBM1_Pos (1U) 2921 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ 2922 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ 2923 #define CAN_FM1R_FBM2_Pos (2U) 2924 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ 2925 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ 2926 #define CAN_FM1R_FBM3_Pos (3U) 2927 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ 2928 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ 2929 #define CAN_FM1R_FBM4_Pos (4U) 2930 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ 2931 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ 2932 #define CAN_FM1R_FBM5_Pos (5U) 2933 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ 2934 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ 2935 #define CAN_FM1R_FBM6_Pos (6U) 2936 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ 2937 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ 2938 #define CAN_FM1R_FBM7_Pos (7U) 2939 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ 2940 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ 2941 #define CAN_FM1R_FBM8_Pos (8U) 2942 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ 2943 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ 2944 #define CAN_FM1R_FBM9_Pos (9U) 2945 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ 2946 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ 2947 #define CAN_FM1R_FBM10_Pos (10U) 2948 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ 2949 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ 2950 #define CAN_FM1R_FBM11_Pos (11U) 2951 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ 2952 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ 2953 #define CAN_FM1R_FBM12_Pos (12U) 2954 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ 2955 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ 2956 #define CAN_FM1R_FBM13_Pos (13U) 2957 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ 2958 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ 2959 2960 /******************* Bit definition for CAN_FS1R register *******************/ 2961 #define CAN_FS1R_FSC_Pos (0U) 2962 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ 2963 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ 2964 #define CAN_FS1R_FSC0_Pos (0U) 2965 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ 2966 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ 2967 #define CAN_FS1R_FSC1_Pos (1U) 2968 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ 2969 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ 2970 #define CAN_FS1R_FSC2_Pos (2U) 2971 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ 2972 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ 2973 #define CAN_FS1R_FSC3_Pos (3U) 2974 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ 2975 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ 2976 #define CAN_FS1R_FSC4_Pos (4U) 2977 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ 2978 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ 2979 #define CAN_FS1R_FSC5_Pos (5U) 2980 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ 2981 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ 2982 #define CAN_FS1R_FSC6_Pos (6U) 2983 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ 2984 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ 2985 #define CAN_FS1R_FSC7_Pos (7U) 2986 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ 2987 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ 2988 #define CAN_FS1R_FSC8_Pos (8U) 2989 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ 2990 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ 2991 #define CAN_FS1R_FSC9_Pos (9U) 2992 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ 2993 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ 2994 #define CAN_FS1R_FSC10_Pos (10U) 2995 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ 2996 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ 2997 #define CAN_FS1R_FSC11_Pos (11U) 2998 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ 2999 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ 3000 #define CAN_FS1R_FSC12_Pos (12U) 3001 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ 3002 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ 3003 #define CAN_FS1R_FSC13_Pos (13U) 3004 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ 3005 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ 3006 3007 /****************** Bit definition for CAN_FFA1R register *******************/ 3008 #define CAN_FFA1R_FFA_Pos (0U) 3009 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ 3010 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ 3011 #define CAN_FFA1R_FFA0_Pos (0U) 3012 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ 3013 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */ 3014 #define CAN_FFA1R_FFA1_Pos (1U) 3015 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ 3016 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */ 3017 #define CAN_FFA1R_FFA2_Pos (2U) 3018 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ 3019 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */ 3020 #define CAN_FFA1R_FFA3_Pos (3U) 3021 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ 3022 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */ 3023 #define CAN_FFA1R_FFA4_Pos (4U) 3024 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ 3025 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */ 3026 #define CAN_FFA1R_FFA5_Pos (5U) 3027 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ 3028 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */ 3029 #define CAN_FFA1R_FFA6_Pos (6U) 3030 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ 3031 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */ 3032 #define CAN_FFA1R_FFA7_Pos (7U) 3033 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ 3034 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */ 3035 #define CAN_FFA1R_FFA8_Pos (8U) 3036 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ 3037 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */ 3038 #define CAN_FFA1R_FFA9_Pos (9U) 3039 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ 3040 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */ 3041 #define CAN_FFA1R_FFA10_Pos (10U) 3042 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ 3043 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */ 3044 #define CAN_FFA1R_FFA11_Pos (11U) 3045 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ 3046 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */ 3047 #define CAN_FFA1R_FFA12_Pos (12U) 3048 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ 3049 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */ 3050 #define CAN_FFA1R_FFA13_Pos (13U) 3051 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ 3052 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */ 3053 3054 /******************* Bit definition for CAN_FA1R register *******************/ 3055 #define CAN_FA1R_FACT_Pos (0U) 3056 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ 3057 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ 3058 #define CAN_FA1R_FACT0_Pos (0U) 3059 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ 3060 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */ 3061 #define CAN_FA1R_FACT1_Pos (1U) 3062 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ 3063 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */ 3064 #define CAN_FA1R_FACT2_Pos (2U) 3065 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ 3066 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */ 3067 #define CAN_FA1R_FACT3_Pos (3U) 3068 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ 3069 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */ 3070 #define CAN_FA1R_FACT4_Pos (4U) 3071 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ 3072 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */ 3073 #define CAN_FA1R_FACT5_Pos (5U) 3074 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ 3075 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */ 3076 #define CAN_FA1R_FACT6_Pos (6U) 3077 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ 3078 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */ 3079 #define CAN_FA1R_FACT7_Pos (7U) 3080 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ 3081 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */ 3082 #define CAN_FA1R_FACT8_Pos (8U) 3083 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ 3084 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */ 3085 #define CAN_FA1R_FACT9_Pos (9U) 3086 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ 3087 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */ 3088 #define CAN_FA1R_FACT10_Pos (10U) 3089 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ 3090 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */ 3091 #define CAN_FA1R_FACT11_Pos (11U) 3092 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ 3093 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */ 3094 #define CAN_FA1R_FACT12_Pos (12U) 3095 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ 3096 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */ 3097 #define CAN_FA1R_FACT13_Pos (13U) 3098 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ 3099 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */ 3100 3101 /******************* Bit definition for CAN_F0R1 register *******************/ 3102 #define CAN_F0R1_FB0_Pos (0U) 3103 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ 3104 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ 3105 #define CAN_F0R1_FB1_Pos (1U) 3106 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ 3107 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ 3108 #define CAN_F0R1_FB2_Pos (2U) 3109 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ 3110 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ 3111 #define CAN_F0R1_FB3_Pos (3U) 3112 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ 3113 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ 3114 #define CAN_F0R1_FB4_Pos (4U) 3115 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ 3116 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ 3117 #define CAN_F0R1_FB5_Pos (5U) 3118 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ 3119 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ 3120 #define CAN_F0R1_FB6_Pos (6U) 3121 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ 3122 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ 3123 #define CAN_F0R1_FB7_Pos (7U) 3124 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ 3125 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ 3126 #define CAN_F0R1_FB8_Pos (8U) 3127 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ 3128 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ 3129 #define CAN_F0R1_FB9_Pos (9U) 3130 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ 3131 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ 3132 #define CAN_F0R1_FB10_Pos (10U) 3133 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ 3134 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ 3135 #define CAN_F0R1_FB11_Pos (11U) 3136 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ 3137 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ 3138 #define CAN_F0R1_FB12_Pos (12U) 3139 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ 3140 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ 3141 #define CAN_F0R1_FB13_Pos (13U) 3142 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ 3143 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ 3144 #define CAN_F0R1_FB14_Pos (14U) 3145 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ 3146 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ 3147 #define CAN_F0R1_FB15_Pos (15U) 3148 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ 3149 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ 3150 #define CAN_F0R1_FB16_Pos (16U) 3151 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ 3152 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ 3153 #define CAN_F0R1_FB17_Pos (17U) 3154 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ 3155 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ 3156 #define CAN_F0R1_FB18_Pos (18U) 3157 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ 3158 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ 3159 #define CAN_F0R1_FB19_Pos (19U) 3160 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ 3161 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ 3162 #define CAN_F0R1_FB20_Pos (20U) 3163 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ 3164 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ 3165 #define CAN_F0R1_FB21_Pos (21U) 3166 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ 3167 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ 3168 #define CAN_F0R1_FB22_Pos (22U) 3169 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ 3170 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ 3171 #define CAN_F0R1_FB23_Pos (23U) 3172 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ 3173 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ 3174 #define CAN_F0R1_FB24_Pos (24U) 3175 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ 3176 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ 3177 #define CAN_F0R1_FB25_Pos (25U) 3178 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ 3179 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ 3180 #define CAN_F0R1_FB26_Pos (26U) 3181 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ 3182 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ 3183 #define CAN_F0R1_FB27_Pos (27U) 3184 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ 3185 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ 3186 #define CAN_F0R1_FB28_Pos (28U) 3187 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ 3188 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ 3189 #define CAN_F0R1_FB29_Pos (29U) 3190 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ 3191 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ 3192 #define CAN_F0R1_FB30_Pos (30U) 3193 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ 3194 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ 3195 #define CAN_F0R1_FB31_Pos (31U) 3196 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ 3197 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ 3198 3199 /******************* Bit definition for CAN_F1R1 register *******************/ 3200 #define CAN_F1R1_FB0_Pos (0U) 3201 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ 3202 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ 3203 #define CAN_F1R1_FB1_Pos (1U) 3204 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ 3205 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ 3206 #define CAN_F1R1_FB2_Pos (2U) 3207 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ 3208 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ 3209 #define CAN_F1R1_FB3_Pos (3U) 3210 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ 3211 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ 3212 #define CAN_F1R1_FB4_Pos (4U) 3213 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ 3214 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ 3215 #define CAN_F1R1_FB5_Pos (5U) 3216 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ 3217 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ 3218 #define CAN_F1R1_FB6_Pos (6U) 3219 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ 3220 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ 3221 #define CAN_F1R1_FB7_Pos (7U) 3222 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ 3223 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ 3224 #define CAN_F1R1_FB8_Pos (8U) 3225 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ 3226 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ 3227 #define CAN_F1R1_FB9_Pos (9U) 3228 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ 3229 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ 3230 #define CAN_F1R1_FB10_Pos (10U) 3231 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ 3232 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ 3233 #define CAN_F1R1_FB11_Pos (11U) 3234 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ 3235 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ 3236 #define CAN_F1R1_FB12_Pos (12U) 3237 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ 3238 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ 3239 #define CAN_F1R1_FB13_Pos (13U) 3240 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ 3241 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ 3242 #define CAN_F1R1_FB14_Pos (14U) 3243 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ 3244 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ 3245 #define CAN_F1R1_FB15_Pos (15U) 3246 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ 3247 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ 3248 #define CAN_F1R1_FB16_Pos (16U) 3249 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ 3250 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ 3251 #define CAN_F1R1_FB17_Pos (17U) 3252 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ 3253 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ 3254 #define CAN_F1R1_FB18_Pos (18U) 3255 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ 3256 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ 3257 #define CAN_F1R1_FB19_Pos (19U) 3258 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ 3259 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ 3260 #define CAN_F1R1_FB20_Pos (20U) 3261 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ 3262 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ 3263 #define CAN_F1R1_FB21_Pos (21U) 3264 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ 3265 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ 3266 #define CAN_F1R1_FB22_Pos (22U) 3267 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ 3268 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ 3269 #define CAN_F1R1_FB23_Pos (23U) 3270 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ 3271 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ 3272 #define CAN_F1R1_FB24_Pos (24U) 3273 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ 3274 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ 3275 #define CAN_F1R1_FB25_Pos (25U) 3276 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ 3277 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ 3278 #define CAN_F1R1_FB26_Pos (26U) 3279 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ 3280 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ 3281 #define CAN_F1R1_FB27_Pos (27U) 3282 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ 3283 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ 3284 #define CAN_F1R1_FB28_Pos (28U) 3285 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ 3286 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ 3287 #define CAN_F1R1_FB29_Pos (29U) 3288 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ 3289 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ 3290 #define CAN_F1R1_FB30_Pos (30U) 3291 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ 3292 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ 3293 #define CAN_F1R1_FB31_Pos (31U) 3294 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ 3295 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ 3296 3297 /******************* Bit definition for CAN_F2R1 register *******************/ 3298 #define CAN_F2R1_FB0_Pos (0U) 3299 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ 3300 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ 3301 #define CAN_F2R1_FB1_Pos (1U) 3302 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ 3303 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ 3304 #define CAN_F2R1_FB2_Pos (2U) 3305 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ 3306 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ 3307 #define CAN_F2R1_FB3_Pos (3U) 3308 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ 3309 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ 3310 #define CAN_F2R1_FB4_Pos (4U) 3311 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ 3312 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ 3313 #define CAN_F2R1_FB5_Pos (5U) 3314 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ 3315 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ 3316 #define CAN_F2R1_FB6_Pos (6U) 3317 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ 3318 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ 3319 #define CAN_F2R1_FB7_Pos (7U) 3320 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ 3321 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ 3322 #define CAN_F2R1_FB8_Pos (8U) 3323 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ 3324 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ 3325 #define CAN_F2R1_FB9_Pos (9U) 3326 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ 3327 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ 3328 #define CAN_F2R1_FB10_Pos (10U) 3329 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ 3330 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ 3331 #define CAN_F2R1_FB11_Pos (11U) 3332 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ 3333 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ 3334 #define CAN_F2R1_FB12_Pos (12U) 3335 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ 3336 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ 3337 #define CAN_F2R1_FB13_Pos (13U) 3338 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ 3339 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ 3340 #define CAN_F2R1_FB14_Pos (14U) 3341 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ 3342 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ 3343 #define CAN_F2R1_FB15_Pos (15U) 3344 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ 3345 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ 3346 #define CAN_F2R1_FB16_Pos (16U) 3347 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ 3348 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ 3349 #define CAN_F2R1_FB17_Pos (17U) 3350 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ 3351 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ 3352 #define CAN_F2R1_FB18_Pos (18U) 3353 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ 3354 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ 3355 #define CAN_F2R1_FB19_Pos (19U) 3356 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ 3357 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ 3358 #define CAN_F2R1_FB20_Pos (20U) 3359 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ 3360 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ 3361 #define CAN_F2R1_FB21_Pos (21U) 3362 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ 3363 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ 3364 #define CAN_F2R1_FB22_Pos (22U) 3365 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ 3366 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ 3367 #define CAN_F2R1_FB23_Pos (23U) 3368 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ 3369 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ 3370 #define CAN_F2R1_FB24_Pos (24U) 3371 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ 3372 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ 3373 #define CAN_F2R1_FB25_Pos (25U) 3374 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ 3375 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ 3376 #define CAN_F2R1_FB26_Pos (26U) 3377 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ 3378 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ 3379 #define CAN_F2R1_FB27_Pos (27U) 3380 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ 3381 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ 3382 #define CAN_F2R1_FB28_Pos (28U) 3383 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ 3384 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ 3385 #define CAN_F2R1_FB29_Pos (29U) 3386 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ 3387 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ 3388 #define CAN_F2R1_FB30_Pos (30U) 3389 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ 3390 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ 3391 #define CAN_F2R1_FB31_Pos (31U) 3392 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ 3393 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ 3394 3395 /******************* Bit definition for CAN_F3R1 register *******************/ 3396 #define CAN_F3R1_FB0_Pos (0U) 3397 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ 3398 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ 3399 #define CAN_F3R1_FB1_Pos (1U) 3400 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ 3401 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ 3402 #define CAN_F3R1_FB2_Pos (2U) 3403 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ 3404 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ 3405 #define CAN_F3R1_FB3_Pos (3U) 3406 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ 3407 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ 3408 #define CAN_F3R1_FB4_Pos (4U) 3409 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ 3410 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ 3411 #define CAN_F3R1_FB5_Pos (5U) 3412 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ 3413 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ 3414 #define CAN_F3R1_FB6_Pos (6U) 3415 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ 3416 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ 3417 #define CAN_F3R1_FB7_Pos (7U) 3418 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ 3419 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ 3420 #define CAN_F3R1_FB8_Pos (8U) 3421 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ 3422 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ 3423 #define CAN_F3R1_FB9_Pos (9U) 3424 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ 3425 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ 3426 #define CAN_F3R1_FB10_Pos (10U) 3427 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ 3428 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ 3429 #define CAN_F3R1_FB11_Pos (11U) 3430 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ 3431 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ 3432 #define CAN_F3R1_FB12_Pos (12U) 3433 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ 3434 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ 3435 #define CAN_F3R1_FB13_Pos (13U) 3436 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ 3437 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ 3438 #define CAN_F3R1_FB14_Pos (14U) 3439 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ 3440 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ 3441 #define CAN_F3R1_FB15_Pos (15U) 3442 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ 3443 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ 3444 #define CAN_F3R1_FB16_Pos (16U) 3445 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ 3446 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ 3447 #define CAN_F3R1_FB17_Pos (17U) 3448 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ 3449 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ 3450 #define CAN_F3R1_FB18_Pos (18U) 3451 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ 3452 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ 3453 #define CAN_F3R1_FB19_Pos (19U) 3454 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ 3455 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ 3456 #define CAN_F3R1_FB20_Pos (20U) 3457 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ 3458 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ 3459 #define CAN_F3R1_FB21_Pos (21U) 3460 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ 3461 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ 3462 #define CAN_F3R1_FB22_Pos (22U) 3463 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ 3464 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ 3465 #define CAN_F3R1_FB23_Pos (23U) 3466 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ 3467 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ 3468 #define CAN_F3R1_FB24_Pos (24U) 3469 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ 3470 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ 3471 #define CAN_F3R1_FB25_Pos (25U) 3472 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ 3473 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ 3474 #define CAN_F3R1_FB26_Pos (26U) 3475 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ 3476 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ 3477 #define CAN_F3R1_FB27_Pos (27U) 3478 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ 3479 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ 3480 #define CAN_F3R1_FB28_Pos (28U) 3481 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ 3482 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ 3483 #define CAN_F3R1_FB29_Pos (29U) 3484 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ 3485 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ 3486 #define CAN_F3R1_FB30_Pos (30U) 3487 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ 3488 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ 3489 #define CAN_F3R1_FB31_Pos (31U) 3490 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ 3491 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ 3492 3493 /******************* Bit definition for CAN_F4R1 register *******************/ 3494 #define CAN_F4R1_FB0_Pos (0U) 3495 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ 3496 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ 3497 #define CAN_F4R1_FB1_Pos (1U) 3498 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ 3499 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ 3500 #define CAN_F4R1_FB2_Pos (2U) 3501 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ 3502 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ 3503 #define CAN_F4R1_FB3_Pos (3U) 3504 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ 3505 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ 3506 #define CAN_F4R1_FB4_Pos (4U) 3507 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ 3508 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ 3509 #define CAN_F4R1_FB5_Pos (5U) 3510 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ 3511 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ 3512 #define CAN_F4R1_FB6_Pos (6U) 3513 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ 3514 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ 3515 #define CAN_F4R1_FB7_Pos (7U) 3516 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ 3517 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ 3518 #define CAN_F4R1_FB8_Pos (8U) 3519 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ 3520 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ 3521 #define CAN_F4R1_FB9_Pos (9U) 3522 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ 3523 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ 3524 #define CAN_F4R1_FB10_Pos (10U) 3525 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ 3526 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ 3527 #define CAN_F4R1_FB11_Pos (11U) 3528 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ 3529 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ 3530 #define CAN_F4R1_FB12_Pos (12U) 3531 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ 3532 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ 3533 #define CAN_F4R1_FB13_Pos (13U) 3534 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ 3535 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ 3536 #define CAN_F4R1_FB14_Pos (14U) 3537 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ 3538 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ 3539 #define CAN_F4R1_FB15_Pos (15U) 3540 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ 3541 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ 3542 #define CAN_F4R1_FB16_Pos (16U) 3543 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ 3544 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ 3545 #define CAN_F4R1_FB17_Pos (17U) 3546 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ 3547 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ 3548 #define CAN_F4R1_FB18_Pos (18U) 3549 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ 3550 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ 3551 #define CAN_F4R1_FB19_Pos (19U) 3552 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ 3553 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ 3554 #define CAN_F4R1_FB20_Pos (20U) 3555 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ 3556 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ 3557 #define CAN_F4R1_FB21_Pos (21U) 3558 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ 3559 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ 3560 #define CAN_F4R1_FB22_Pos (22U) 3561 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ 3562 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ 3563 #define CAN_F4R1_FB23_Pos (23U) 3564 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ 3565 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ 3566 #define CAN_F4R1_FB24_Pos (24U) 3567 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ 3568 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ 3569 #define CAN_F4R1_FB25_Pos (25U) 3570 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ 3571 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ 3572 #define CAN_F4R1_FB26_Pos (26U) 3573 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ 3574 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ 3575 #define CAN_F4R1_FB27_Pos (27U) 3576 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ 3577 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ 3578 #define CAN_F4R1_FB28_Pos (28U) 3579 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ 3580 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ 3581 #define CAN_F4R1_FB29_Pos (29U) 3582 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ 3583 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ 3584 #define CAN_F4R1_FB30_Pos (30U) 3585 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ 3586 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ 3587 #define CAN_F4R1_FB31_Pos (31U) 3588 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ 3589 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ 3590 3591 /******************* Bit definition for CAN_F5R1 register *******************/ 3592 #define CAN_F5R1_FB0_Pos (0U) 3593 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ 3594 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ 3595 #define CAN_F5R1_FB1_Pos (1U) 3596 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ 3597 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ 3598 #define CAN_F5R1_FB2_Pos (2U) 3599 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ 3600 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ 3601 #define CAN_F5R1_FB3_Pos (3U) 3602 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ 3603 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ 3604 #define CAN_F5R1_FB4_Pos (4U) 3605 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ 3606 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ 3607 #define CAN_F5R1_FB5_Pos (5U) 3608 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ 3609 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ 3610 #define CAN_F5R1_FB6_Pos (6U) 3611 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ 3612 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ 3613 #define CAN_F5R1_FB7_Pos (7U) 3614 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ 3615 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ 3616 #define CAN_F5R1_FB8_Pos (8U) 3617 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ 3618 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ 3619 #define CAN_F5R1_FB9_Pos (9U) 3620 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ 3621 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ 3622 #define CAN_F5R1_FB10_Pos (10U) 3623 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ 3624 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ 3625 #define CAN_F5R1_FB11_Pos (11U) 3626 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ 3627 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ 3628 #define CAN_F5R1_FB12_Pos (12U) 3629 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ 3630 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ 3631 #define CAN_F5R1_FB13_Pos (13U) 3632 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ 3633 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ 3634 #define CAN_F5R1_FB14_Pos (14U) 3635 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ 3636 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ 3637 #define CAN_F5R1_FB15_Pos (15U) 3638 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ 3639 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ 3640 #define CAN_F5R1_FB16_Pos (16U) 3641 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ 3642 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ 3643 #define CAN_F5R1_FB17_Pos (17U) 3644 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ 3645 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ 3646 #define CAN_F5R1_FB18_Pos (18U) 3647 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ 3648 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ 3649 #define CAN_F5R1_FB19_Pos (19U) 3650 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ 3651 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ 3652 #define CAN_F5R1_FB20_Pos (20U) 3653 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ 3654 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ 3655 #define CAN_F5R1_FB21_Pos (21U) 3656 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ 3657 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ 3658 #define CAN_F5R1_FB22_Pos (22U) 3659 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ 3660 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ 3661 #define CAN_F5R1_FB23_Pos (23U) 3662 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ 3663 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ 3664 #define CAN_F5R1_FB24_Pos (24U) 3665 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ 3666 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ 3667 #define CAN_F5R1_FB25_Pos (25U) 3668 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ 3669 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ 3670 #define CAN_F5R1_FB26_Pos (26U) 3671 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ 3672 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ 3673 #define CAN_F5R1_FB27_Pos (27U) 3674 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ 3675 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ 3676 #define CAN_F5R1_FB28_Pos (28U) 3677 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ 3678 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ 3679 #define CAN_F5R1_FB29_Pos (29U) 3680 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ 3681 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ 3682 #define CAN_F5R1_FB30_Pos (30U) 3683 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ 3684 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ 3685 #define CAN_F5R1_FB31_Pos (31U) 3686 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ 3687 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ 3688 3689 /******************* Bit definition for CAN_F6R1 register *******************/ 3690 #define CAN_F6R1_FB0_Pos (0U) 3691 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ 3692 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ 3693 #define CAN_F6R1_FB1_Pos (1U) 3694 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ 3695 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ 3696 #define CAN_F6R1_FB2_Pos (2U) 3697 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ 3698 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ 3699 #define CAN_F6R1_FB3_Pos (3U) 3700 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ 3701 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ 3702 #define CAN_F6R1_FB4_Pos (4U) 3703 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ 3704 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ 3705 #define CAN_F6R1_FB5_Pos (5U) 3706 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ 3707 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ 3708 #define CAN_F6R1_FB6_Pos (6U) 3709 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ 3710 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ 3711 #define CAN_F6R1_FB7_Pos (7U) 3712 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ 3713 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ 3714 #define CAN_F6R1_FB8_Pos (8U) 3715 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ 3716 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ 3717 #define CAN_F6R1_FB9_Pos (9U) 3718 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ 3719 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ 3720 #define CAN_F6R1_FB10_Pos (10U) 3721 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ 3722 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ 3723 #define CAN_F6R1_FB11_Pos (11U) 3724 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ 3725 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ 3726 #define CAN_F6R1_FB12_Pos (12U) 3727 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ 3728 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ 3729 #define CAN_F6R1_FB13_Pos (13U) 3730 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ 3731 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ 3732 #define CAN_F6R1_FB14_Pos (14U) 3733 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ 3734 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ 3735 #define CAN_F6R1_FB15_Pos (15U) 3736 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ 3737 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ 3738 #define CAN_F6R1_FB16_Pos (16U) 3739 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ 3740 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ 3741 #define CAN_F6R1_FB17_Pos (17U) 3742 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ 3743 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ 3744 #define CAN_F6R1_FB18_Pos (18U) 3745 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ 3746 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ 3747 #define CAN_F6R1_FB19_Pos (19U) 3748 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ 3749 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ 3750 #define CAN_F6R1_FB20_Pos (20U) 3751 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ 3752 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ 3753 #define CAN_F6R1_FB21_Pos (21U) 3754 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ 3755 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ 3756 #define CAN_F6R1_FB22_Pos (22U) 3757 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ 3758 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ 3759 #define CAN_F6R1_FB23_Pos (23U) 3760 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ 3761 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ 3762 #define CAN_F6R1_FB24_Pos (24U) 3763 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ 3764 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ 3765 #define CAN_F6R1_FB25_Pos (25U) 3766 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ 3767 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ 3768 #define CAN_F6R1_FB26_Pos (26U) 3769 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ 3770 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ 3771 #define CAN_F6R1_FB27_Pos (27U) 3772 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ 3773 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ 3774 #define CAN_F6R1_FB28_Pos (28U) 3775 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ 3776 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ 3777 #define CAN_F6R1_FB29_Pos (29U) 3778 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ 3779 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ 3780 #define CAN_F6R1_FB30_Pos (30U) 3781 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ 3782 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ 3783 #define CAN_F6R1_FB31_Pos (31U) 3784 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ 3785 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ 3786 3787 /******************* Bit definition for CAN_F7R1 register *******************/ 3788 #define CAN_F7R1_FB0_Pos (0U) 3789 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ 3790 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ 3791 #define CAN_F7R1_FB1_Pos (1U) 3792 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ 3793 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ 3794 #define CAN_F7R1_FB2_Pos (2U) 3795 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ 3796 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ 3797 #define CAN_F7R1_FB3_Pos (3U) 3798 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ 3799 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ 3800 #define CAN_F7R1_FB4_Pos (4U) 3801 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ 3802 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ 3803 #define CAN_F7R1_FB5_Pos (5U) 3804 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ 3805 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ 3806 #define CAN_F7R1_FB6_Pos (6U) 3807 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ 3808 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ 3809 #define CAN_F7R1_FB7_Pos (7U) 3810 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ 3811 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ 3812 #define CAN_F7R1_FB8_Pos (8U) 3813 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ 3814 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ 3815 #define CAN_F7R1_FB9_Pos (9U) 3816 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ 3817 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ 3818 #define CAN_F7R1_FB10_Pos (10U) 3819 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ 3820 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ 3821 #define CAN_F7R1_FB11_Pos (11U) 3822 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ 3823 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ 3824 #define CAN_F7R1_FB12_Pos (12U) 3825 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ 3826 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ 3827 #define CAN_F7R1_FB13_Pos (13U) 3828 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ 3829 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ 3830 #define CAN_F7R1_FB14_Pos (14U) 3831 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ 3832 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ 3833 #define CAN_F7R1_FB15_Pos (15U) 3834 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ 3835 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ 3836 #define CAN_F7R1_FB16_Pos (16U) 3837 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ 3838 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ 3839 #define CAN_F7R1_FB17_Pos (17U) 3840 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ 3841 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ 3842 #define CAN_F7R1_FB18_Pos (18U) 3843 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ 3844 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ 3845 #define CAN_F7R1_FB19_Pos (19U) 3846 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ 3847 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ 3848 #define CAN_F7R1_FB20_Pos (20U) 3849 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ 3850 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ 3851 #define CAN_F7R1_FB21_Pos (21U) 3852 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ 3853 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ 3854 #define CAN_F7R1_FB22_Pos (22U) 3855 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ 3856 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ 3857 #define CAN_F7R1_FB23_Pos (23U) 3858 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ 3859 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ 3860 #define CAN_F7R1_FB24_Pos (24U) 3861 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ 3862 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ 3863 #define CAN_F7R1_FB25_Pos (25U) 3864 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ 3865 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ 3866 #define CAN_F7R1_FB26_Pos (26U) 3867 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ 3868 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ 3869 #define CAN_F7R1_FB27_Pos (27U) 3870 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ 3871 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ 3872 #define CAN_F7R1_FB28_Pos (28U) 3873 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ 3874 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ 3875 #define CAN_F7R1_FB29_Pos (29U) 3876 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ 3877 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ 3878 #define CAN_F7R1_FB30_Pos (30U) 3879 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ 3880 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ 3881 #define CAN_F7R1_FB31_Pos (31U) 3882 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ 3883 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ 3884 3885 /******************* Bit definition for CAN_F8R1 register *******************/ 3886 #define CAN_F8R1_FB0_Pos (0U) 3887 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ 3888 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ 3889 #define CAN_F8R1_FB1_Pos (1U) 3890 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ 3891 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ 3892 #define CAN_F8R1_FB2_Pos (2U) 3893 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ 3894 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ 3895 #define CAN_F8R1_FB3_Pos (3U) 3896 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ 3897 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ 3898 #define CAN_F8R1_FB4_Pos (4U) 3899 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ 3900 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ 3901 #define CAN_F8R1_FB5_Pos (5U) 3902 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ 3903 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ 3904 #define CAN_F8R1_FB6_Pos (6U) 3905 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ 3906 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ 3907 #define CAN_F8R1_FB7_Pos (7U) 3908 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ 3909 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ 3910 #define CAN_F8R1_FB8_Pos (8U) 3911 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ 3912 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ 3913 #define CAN_F8R1_FB9_Pos (9U) 3914 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ 3915 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ 3916 #define CAN_F8R1_FB10_Pos (10U) 3917 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ 3918 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ 3919 #define CAN_F8R1_FB11_Pos (11U) 3920 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ 3921 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ 3922 #define CAN_F8R1_FB12_Pos (12U) 3923 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ 3924 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ 3925 #define CAN_F8R1_FB13_Pos (13U) 3926 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ 3927 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ 3928 #define CAN_F8R1_FB14_Pos (14U) 3929 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ 3930 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ 3931 #define CAN_F8R1_FB15_Pos (15U) 3932 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ 3933 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ 3934 #define CAN_F8R1_FB16_Pos (16U) 3935 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ 3936 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ 3937 #define CAN_F8R1_FB17_Pos (17U) 3938 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ 3939 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ 3940 #define CAN_F8R1_FB18_Pos (18U) 3941 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ 3942 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ 3943 #define CAN_F8R1_FB19_Pos (19U) 3944 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ 3945 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ 3946 #define CAN_F8R1_FB20_Pos (20U) 3947 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ 3948 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ 3949 #define CAN_F8R1_FB21_Pos (21U) 3950 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ 3951 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ 3952 #define CAN_F8R1_FB22_Pos (22U) 3953 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ 3954 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ 3955 #define CAN_F8R1_FB23_Pos (23U) 3956 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ 3957 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ 3958 #define CAN_F8R1_FB24_Pos (24U) 3959 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ 3960 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ 3961 #define CAN_F8R1_FB25_Pos (25U) 3962 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ 3963 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ 3964 #define CAN_F8R1_FB26_Pos (26U) 3965 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ 3966 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ 3967 #define CAN_F8R1_FB27_Pos (27U) 3968 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ 3969 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ 3970 #define CAN_F8R1_FB28_Pos (28U) 3971 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ 3972 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ 3973 #define CAN_F8R1_FB29_Pos (29U) 3974 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ 3975 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ 3976 #define CAN_F8R1_FB30_Pos (30U) 3977 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ 3978 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ 3979 #define CAN_F8R1_FB31_Pos (31U) 3980 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ 3981 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ 3982 3983 /******************* Bit definition for CAN_F9R1 register *******************/ 3984 #define CAN_F9R1_FB0_Pos (0U) 3985 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ 3986 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ 3987 #define CAN_F9R1_FB1_Pos (1U) 3988 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ 3989 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ 3990 #define CAN_F9R1_FB2_Pos (2U) 3991 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ 3992 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ 3993 #define CAN_F9R1_FB3_Pos (3U) 3994 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ 3995 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ 3996 #define CAN_F9R1_FB4_Pos (4U) 3997 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ 3998 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ 3999 #define CAN_F9R1_FB5_Pos (5U) 4000 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ 4001 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ 4002 #define CAN_F9R1_FB6_Pos (6U) 4003 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ 4004 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ 4005 #define CAN_F9R1_FB7_Pos (7U) 4006 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ 4007 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ 4008 #define CAN_F9R1_FB8_Pos (8U) 4009 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ 4010 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ 4011 #define CAN_F9R1_FB9_Pos (9U) 4012 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ 4013 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ 4014 #define CAN_F9R1_FB10_Pos (10U) 4015 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ 4016 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ 4017 #define CAN_F9R1_FB11_Pos (11U) 4018 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ 4019 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ 4020 #define CAN_F9R1_FB12_Pos (12U) 4021 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ 4022 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ 4023 #define CAN_F9R1_FB13_Pos (13U) 4024 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ 4025 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ 4026 #define CAN_F9R1_FB14_Pos (14U) 4027 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ 4028 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ 4029 #define CAN_F9R1_FB15_Pos (15U) 4030 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ 4031 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ 4032 #define CAN_F9R1_FB16_Pos (16U) 4033 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ 4034 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ 4035 #define CAN_F9R1_FB17_Pos (17U) 4036 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ 4037 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ 4038 #define CAN_F9R1_FB18_Pos (18U) 4039 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ 4040 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ 4041 #define CAN_F9R1_FB19_Pos (19U) 4042 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ 4043 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ 4044 #define CAN_F9R1_FB20_Pos (20U) 4045 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ 4046 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ 4047 #define CAN_F9R1_FB21_Pos (21U) 4048 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ 4049 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ 4050 #define CAN_F9R1_FB22_Pos (22U) 4051 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ 4052 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ 4053 #define CAN_F9R1_FB23_Pos (23U) 4054 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ 4055 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ 4056 #define CAN_F9R1_FB24_Pos (24U) 4057 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ 4058 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ 4059 #define CAN_F9R1_FB25_Pos (25U) 4060 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ 4061 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ 4062 #define CAN_F9R1_FB26_Pos (26U) 4063 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ 4064 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ 4065 #define CAN_F9R1_FB27_Pos (27U) 4066 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ 4067 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ 4068 #define CAN_F9R1_FB28_Pos (28U) 4069 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ 4070 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ 4071 #define CAN_F9R1_FB29_Pos (29U) 4072 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ 4073 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ 4074 #define CAN_F9R1_FB30_Pos (30U) 4075 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ 4076 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ 4077 #define CAN_F9R1_FB31_Pos (31U) 4078 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ 4079 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ 4080 4081 /******************* Bit definition for CAN_F10R1 register ******************/ 4082 #define CAN_F10R1_FB0_Pos (0U) 4083 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ 4084 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ 4085 #define CAN_F10R1_FB1_Pos (1U) 4086 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ 4087 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ 4088 #define CAN_F10R1_FB2_Pos (2U) 4089 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ 4090 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ 4091 #define CAN_F10R1_FB3_Pos (3U) 4092 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ 4093 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ 4094 #define CAN_F10R1_FB4_Pos (4U) 4095 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ 4096 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ 4097 #define CAN_F10R1_FB5_Pos (5U) 4098 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ 4099 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ 4100 #define CAN_F10R1_FB6_Pos (6U) 4101 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ 4102 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ 4103 #define CAN_F10R1_FB7_Pos (7U) 4104 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ 4105 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ 4106 #define CAN_F10R1_FB8_Pos (8U) 4107 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ 4108 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ 4109 #define CAN_F10R1_FB9_Pos (9U) 4110 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ 4111 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ 4112 #define CAN_F10R1_FB10_Pos (10U) 4113 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ 4114 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ 4115 #define CAN_F10R1_FB11_Pos (11U) 4116 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ 4117 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ 4118 #define CAN_F10R1_FB12_Pos (12U) 4119 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ 4120 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ 4121 #define CAN_F10R1_FB13_Pos (13U) 4122 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ 4123 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ 4124 #define CAN_F10R1_FB14_Pos (14U) 4125 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ 4126 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ 4127 #define CAN_F10R1_FB15_Pos (15U) 4128 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ 4129 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ 4130 #define CAN_F10R1_FB16_Pos (16U) 4131 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ 4132 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ 4133 #define CAN_F10R1_FB17_Pos (17U) 4134 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ 4135 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ 4136 #define CAN_F10R1_FB18_Pos (18U) 4137 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ 4138 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ 4139 #define CAN_F10R1_FB19_Pos (19U) 4140 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ 4141 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ 4142 #define CAN_F10R1_FB20_Pos (20U) 4143 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ 4144 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ 4145 #define CAN_F10R1_FB21_Pos (21U) 4146 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ 4147 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ 4148 #define CAN_F10R1_FB22_Pos (22U) 4149 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ 4150 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ 4151 #define CAN_F10R1_FB23_Pos (23U) 4152 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ 4153 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ 4154 #define CAN_F10R1_FB24_Pos (24U) 4155 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ 4156 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ 4157 #define CAN_F10R1_FB25_Pos (25U) 4158 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ 4159 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ 4160 #define CAN_F10R1_FB26_Pos (26U) 4161 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ 4162 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ 4163 #define CAN_F10R1_FB27_Pos (27U) 4164 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ 4165 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ 4166 #define CAN_F10R1_FB28_Pos (28U) 4167 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ 4168 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ 4169 #define CAN_F10R1_FB29_Pos (29U) 4170 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ 4171 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ 4172 #define CAN_F10R1_FB30_Pos (30U) 4173 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ 4174 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ 4175 #define CAN_F10R1_FB31_Pos (31U) 4176 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ 4177 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ 4178 4179 /******************* Bit definition for CAN_F11R1 register ******************/ 4180 #define CAN_F11R1_FB0_Pos (0U) 4181 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ 4182 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ 4183 #define CAN_F11R1_FB1_Pos (1U) 4184 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ 4185 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ 4186 #define CAN_F11R1_FB2_Pos (2U) 4187 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ 4188 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ 4189 #define CAN_F11R1_FB3_Pos (3U) 4190 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ 4191 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ 4192 #define CAN_F11R1_FB4_Pos (4U) 4193 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ 4194 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ 4195 #define CAN_F11R1_FB5_Pos (5U) 4196 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ 4197 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ 4198 #define CAN_F11R1_FB6_Pos (6U) 4199 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ 4200 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ 4201 #define CAN_F11R1_FB7_Pos (7U) 4202 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ 4203 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ 4204 #define CAN_F11R1_FB8_Pos (8U) 4205 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ 4206 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ 4207 #define CAN_F11R1_FB9_Pos (9U) 4208 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ 4209 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ 4210 #define CAN_F11R1_FB10_Pos (10U) 4211 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ 4212 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ 4213 #define CAN_F11R1_FB11_Pos (11U) 4214 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ 4215 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ 4216 #define CAN_F11R1_FB12_Pos (12U) 4217 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ 4218 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ 4219 #define CAN_F11R1_FB13_Pos (13U) 4220 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ 4221 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ 4222 #define CAN_F11R1_FB14_Pos (14U) 4223 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ 4224 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ 4225 #define CAN_F11R1_FB15_Pos (15U) 4226 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ 4227 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ 4228 #define CAN_F11R1_FB16_Pos (16U) 4229 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ 4230 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ 4231 #define CAN_F11R1_FB17_Pos (17U) 4232 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ 4233 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ 4234 #define CAN_F11R1_FB18_Pos (18U) 4235 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ 4236 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ 4237 #define CAN_F11R1_FB19_Pos (19U) 4238 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ 4239 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ 4240 #define CAN_F11R1_FB20_Pos (20U) 4241 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ 4242 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ 4243 #define CAN_F11R1_FB21_Pos (21U) 4244 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ 4245 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ 4246 #define CAN_F11R1_FB22_Pos (22U) 4247 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ 4248 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ 4249 #define CAN_F11R1_FB23_Pos (23U) 4250 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ 4251 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ 4252 #define CAN_F11R1_FB24_Pos (24U) 4253 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ 4254 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ 4255 #define CAN_F11R1_FB25_Pos (25U) 4256 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ 4257 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ 4258 #define CAN_F11R1_FB26_Pos (26U) 4259 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ 4260 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ 4261 #define CAN_F11R1_FB27_Pos (27U) 4262 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ 4263 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ 4264 #define CAN_F11R1_FB28_Pos (28U) 4265 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ 4266 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ 4267 #define CAN_F11R1_FB29_Pos (29U) 4268 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ 4269 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ 4270 #define CAN_F11R1_FB30_Pos (30U) 4271 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ 4272 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ 4273 #define CAN_F11R1_FB31_Pos (31U) 4274 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ 4275 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ 4276 4277 /******************* Bit definition for CAN_F12R1 register ******************/ 4278 #define CAN_F12R1_FB0_Pos (0U) 4279 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ 4280 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ 4281 #define CAN_F12R1_FB1_Pos (1U) 4282 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ 4283 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ 4284 #define CAN_F12R1_FB2_Pos (2U) 4285 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ 4286 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ 4287 #define CAN_F12R1_FB3_Pos (3U) 4288 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ 4289 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ 4290 #define CAN_F12R1_FB4_Pos (4U) 4291 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ 4292 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ 4293 #define CAN_F12R1_FB5_Pos (5U) 4294 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ 4295 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ 4296 #define CAN_F12R1_FB6_Pos (6U) 4297 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ 4298 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ 4299 #define CAN_F12R1_FB7_Pos (7U) 4300 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ 4301 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ 4302 #define CAN_F12R1_FB8_Pos (8U) 4303 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ 4304 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ 4305 #define CAN_F12R1_FB9_Pos (9U) 4306 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ 4307 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ 4308 #define CAN_F12R1_FB10_Pos (10U) 4309 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ 4310 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ 4311 #define CAN_F12R1_FB11_Pos (11U) 4312 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ 4313 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ 4314 #define CAN_F12R1_FB12_Pos (12U) 4315 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ 4316 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ 4317 #define CAN_F12R1_FB13_Pos (13U) 4318 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ 4319 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ 4320 #define CAN_F12R1_FB14_Pos (14U) 4321 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ 4322 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ 4323 #define CAN_F12R1_FB15_Pos (15U) 4324 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ 4325 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ 4326 #define CAN_F12R1_FB16_Pos (16U) 4327 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ 4328 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ 4329 #define CAN_F12R1_FB17_Pos (17U) 4330 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ 4331 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ 4332 #define CAN_F12R1_FB18_Pos (18U) 4333 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ 4334 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ 4335 #define CAN_F12R1_FB19_Pos (19U) 4336 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ 4337 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ 4338 #define CAN_F12R1_FB20_Pos (20U) 4339 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ 4340 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ 4341 #define CAN_F12R1_FB21_Pos (21U) 4342 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ 4343 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ 4344 #define CAN_F12R1_FB22_Pos (22U) 4345 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ 4346 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ 4347 #define CAN_F12R1_FB23_Pos (23U) 4348 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ 4349 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ 4350 #define CAN_F12R1_FB24_Pos (24U) 4351 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ 4352 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ 4353 #define CAN_F12R1_FB25_Pos (25U) 4354 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ 4355 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ 4356 #define CAN_F12R1_FB26_Pos (26U) 4357 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ 4358 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ 4359 #define CAN_F12R1_FB27_Pos (27U) 4360 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ 4361 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ 4362 #define CAN_F12R1_FB28_Pos (28U) 4363 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ 4364 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ 4365 #define CAN_F12R1_FB29_Pos (29U) 4366 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ 4367 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ 4368 #define CAN_F12R1_FB30_Pos (30U) 4369 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ 4370 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ 4371 #define CAN_F12R1_FB31_Pos (31U) 4372 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ 4373 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ 4374 4375 /******************* Bit definition for CAN_F13R1 register ******************/ 4376 #define CAN_F13R1_FB0_Pos (0U) 4377 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ 4378 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ 4379 #define CAN_F13R1_FB1_Pos (1U) 4380 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ 4381 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ 4382 #define CAN_F13R1_FB2_Pos (2U) 4383 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ 4384 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ 4385 #define CAN_F13R1_FB3_Pos (3U) 4386 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ 4387 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ 4388 #define CAN_F13R1_FB4_Pos (4U) 4389 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ 4390 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ 4391 #define CAN_F13R1_FB5_Pos (5U) 4392 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ 4393 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ 4394 #define CAN_F13R1_FB6_Pos (6U) 4395 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ 4396 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ 4397 #define CAN_F13R1_FB7_Pos (7U) 4398 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ 4399 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ 4400 #define CAN_F13R1_FB8_Pos (8U) 4401 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ 4402 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ 4403 #define CAN_F13R1_FB9_Pos (9U) 4404 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ 4405 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ 4406 #define CAN_F13R1_FB10_Pos (10U) 4407 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ 4408 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ 4409 #define CAN_F13R1_FB11_Pos (11U) 4410 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ 4411 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ 4412 #define CAN_F13R1_FB12_Pos (12U) 4413 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ 4414 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ 4415 #define CAN_F13R1_FB13_Pos (13U) 4416 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ 4417 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ 4418 #define CAN_F13R1_FB14_Pos (14U) 4419 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ 4420 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ 4421 #define CAN_F13R1_FB15_Pos (15U) 4422 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ 4423 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ 4424 #define CAN_F13R1_FB16_Pos (16U) 4425 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ 4426 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ 4427 #define CAN_F13R1_FB17_Pos (17U) 4428 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ 4429 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ 4430 #define CAN_F13R1_FB18_Pos (18U) 4431 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ 4432 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ 4433 #define CAN_F13R1_FB19_Pos (19U) 4434 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ 4435 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ 4436 #define CAN_F13R1_FB20_Pos (20U) 4437 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ 4438 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ 4439 #define CAN_F13R1_FB21_Pos (21U) 4440 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ 4441 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ 4442 #define CAN_F13R1_FB22_Pos (22U) 4443 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ 4444 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ 4445 #define CAN_F13R1_FB23_Pos (23U) 4446 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ 4447 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ 4448 #define CAN_F13R1_FB24_Pos (24U) 4449 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ 4450 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ 4451 #define CAN_F13R1_FB25_Pos (25U) 4452 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ 4453 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ 4454 #define CAN_F13R1_FB26_Pos (26U) 4455 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ 4456 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ 4457 #define CAN_F13R1_FB27_Pos (27U) 4458 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ 4459 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ 4460 #define CAN_F13R1_FB28_Pos (28U) 4461 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ 4462 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ 4463 #define CAN_F13R1_FB29_Pos (29U) 4464 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ 4465 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ 4466 #define CAN_F13R1_FB30_Pos (30U) 4467 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ 4468 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ 4469 #define CAN_F13R1_FB31_Pos (31U) 4470 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ 4471 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ 4472 4473 /******************* Bit definition for CAN_F0R2 register *******************/ 4474 #define CAN_F0R2_FB0_Pos (0U) 4475 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ 4476 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ 4477 #define CAN_F0R2_FB1_Pos (1U) 4478 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ 4479 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ 4480 #define CAN_F0R2_FB2_Pos (2U) 4481 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ 4482 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ 4483 #define CAN_F0R2_FB3_Pos (3U) 4484 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ 4485 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ 4486 #define CAN_F0R2_FB4_Pos (4U) 4487 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ 4488 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ 4489 #define CAN_F0R2_FB5_Pos (5U) 4490 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ 4491 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ 4492 #define CAN_F0R2_FB6_Pos (6U) 4493 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ 4494 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ 4495 #define CAN_F0R2_FB7_Pos (7U) 4496 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ 4497 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ 4498 #define CAN_F0R2_FB8_Pos (8U) 4499 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ 4500 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ 4501 #define CAN_F0R2_FB9_Pos (9U) 4502 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ 4503 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ 4504 #define CAN_F0R2_FB10_Pos (10U) 4505 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ 4506 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ 4507 #define CAN_F0R2_FB11_Pos (11U) 4508 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ 4509 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ 4510 #define CAN_F0R2_FB12_Pos (12U) 4511 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ 4512 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ 4513 #define CAN_F0R2_FB13_Pos (13U) 4514 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ 4515 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ 4516 #define CAN_F0R2_FB14_Pos (14U) 4517 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ 4518 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ 4519 #define CAN_F0R2_FB15_Pos (15U) 4520 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ 4521 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ 4522 #define CAN_F0R2_FB16_Pos (16U) 4523 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ 4524 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ 4525 #define CAN_F0R2_FB17_Pos (17U) 4526 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ 4527 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ 4528 #define CAN_F0R2_FB18_Pos (18U) 4529 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ 4530 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ 4531 #define CAN_F0R2_FB19_Pos (19U) 4532 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ 4533 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ 4534 #define CAN_F0R2_FB20_Pos (20U) 4535 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ 4536 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ 4537 #define CAN_F0R2_FB21_Pos (21U) 4538 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ 4539 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ 4540 #define CAN_F0R2_FB22_Pos (22U) 4541 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ 4542 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ 4543 #define CAN_F0R2_FB23_Pos (23U) 4544 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ 4545 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ 4546 #define CAN_F0R2_FB24_Pos (24U) 4547 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ 4548 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ 4549 #define CAN_F0R2_FB25_Pos (25U) 4550 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ 4551 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ 4552 #define CAN_F0R2_FB26_Pos (26U) 4553 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ 4554 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ 4555 #define CAN_F0R2_FB27_Pos (27U) 4556 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ 4557 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ 4558 #define CAN_F0R2_FB28_Pos (28U) 4559 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ 4560 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ 4561 #define CAN_F0R2_FB29_Pos (29U) 4562 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ 4563 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ 4564 #define CAN_F0R2_FB30_Pos (30U) 4565 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ 4566 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ 4567 #define CAN_F0R2_FB31_Pos (31U) 4568 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ 4569 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ 4570 4571 /******************* Bit definition for CAN_F1R2 register *******************/ 4572 #define CAN_F1R2_FB0_Pos (0U) 4573 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ 4574 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ 4575 #define CAN_F1R2_FB1_Pos (1U) 4576 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ 4577 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ 4578 #define CAN_F1R2_FB2_Pos (2U) 4579 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ 4580 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ 4581 #define CAN_F1R2_FB3_Pos (3U) 4582 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ 4583 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ 4584 #define CAN_F1R2_FB4_Pos (4U) 4585 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ 4586 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ 4587 #define CAN_F1R2_FB5_Pos (5U) 4588 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ 4589 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ 4590 #define CAN_F1R2_FB6_Pos (6U) 4591 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ 4592 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ 4593 #define CAN_F1R2_FB7_Pos (7U) 4594 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ 4595 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ 4596 #define CAN_F1R2_FB8_Pos (8U) 4597 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ 4598 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ 4599 #define CAN_F1R2_FB9_Pos (9U) 4600 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ 4601 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ 4602 #define CAN_F1R2_FB10_Pos (10U) 4603 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ 4604 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ 4605 #define CAN_F1R2_FB11_Pos (11U) 4606 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ 4607 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ 4608 #define CAN_F1R2_FB12_Pos (12U) 4609 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ 4610 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ 4611 #define CAN_F1R2_FB13_Pos (13U) 4612 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ 4613 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ 4614 #define CAN_F1R2_FB14_Pos (14U) 4615 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ 4616 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ 4617 #define CAN_F1R2_FB15_Pos (15U) 4618 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ 4619 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ 4620 #define CAN_F1R2_FB16_Pos (16U) 4621 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ 4622 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ 4623 #define CAN_F1R2_FB17_Pos (17U) 4624 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ 4625 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ 4626 #define CAN_F1R2_FB18_Pos (18U) 4627 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ 4628 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ 4629 #define CAN_F1R2_FB19_Pos (19U) 4630 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ 4631 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ 4632 #define CAN_F1R2_FB20_Pos (20U) 4633 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ 4634 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ 4635 #define CAN_F1R2_FB21_Pos (21U) 4636 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ 4637 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ 4638 #define CAN_F1R2_FB22_Pos (22U) 4639 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ 4640 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ 4641 #define CAN_F1R2_FB23_Pos (23U) 4642 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ 4643 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ 4644 #define CAN_F1R2_FB24_Pos (24U) 4645 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ 4646 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ 4647 #define CAN_F1R2_FB25_Pos (25U) 4648 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ 4649 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ 4650 #define CAN_F1R2_FB26_Pos (26U) 4651 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ 4652 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ 4653 #define CAN_F1R2_FB27_Pos (27U) 4654 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ 4655 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ 4656 #define CAN_F1R2_FB28_Pos (28U) 4657 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ 4658 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ 4659 #define CAN_F1R2_FB29_Pos (29U) 4660 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ 4661 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ 4662 #define CAN_F1R2_FB30_Pos (30U) 4663 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ 4664 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ 4665 #define CAN_F1R2_FB31_Pos (31U) 4666 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ 4667 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ 4668 4669 /******************* Bit definition for CAN_F2R2 register *******************/ 4670 #define CAN_F2R2_FB0_Pos (0U) 4671 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ 4672 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ 4673 #define CAN_F2R2_FB1_Pos (1U) 4674 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ 4675 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ 4676 #define CAN_F2R2_FB2_Pos (2U) 4677 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ 4678 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ 4679 #define CAN_F2R2_FB3_Pos (3U) 4680 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ 4681 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ 4682 #define CAN_F2R2_FB4_Pos (4U) 4683 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ 4684 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ 4685 #define CAN_F2R2_FB5_Pos (5U) 4686 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ 4687 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ 4688 #define CAN_F2R2_FB6_Pos (6U) 4689 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ 4690 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ 4691 #define CAN_F2R2_FB7_Pos (7U) 4692 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ 4693 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ 4694 #define CAN_F2R2_FB8_Pos (8U) 4695 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ 4696 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ 4697 #define CAN_F2R2_FB9_Pos (9U) 4698 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ 4699 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ 4700 #define CAN_F2R2_FB10_Pos (10U) 4701 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ 4702 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ 4703 #define CAN_F2R2_FB11_Pos (11U) 4704 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ 4705 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ 4706 #define CAN_F2R2_FB12_Pos (12U) 4707 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ 4708 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ 4709 #define CAN_F2R2_FB13_Pos (13U) 4710 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ 4711 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ 4712 #define CAN_F2R2_FB14_Pos (14U) 4713 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ 4714 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ 4715 #define CAN_F2R2_FB15_Pos (15U) 4716 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ 4717 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ 4718 #define CAN_F2R2_FB16_Pos (16U) 4719 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ 4720 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ 4721 #define CAN_F2R2_FB17_Pos (17U) 4722 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ 4723 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ 4724 #define CAN_F2R2_FB18_Pos (18U) 4725 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ 4726 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ 4727 #define CAN_F2R2_FB19_Pos (19U) 4728 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ 4729 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ 4730 #define CAN_F2R2_FB20_Pos (20U) 4731 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ 4732 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ 4733 #define CAN_F2R2_FB21_Pos (21U) 4734 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ 4735 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ 4736 #define CAN_F2R2_FB22_Pos (22U) 4737 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ 4738 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ 4739 #define CAN_F2R2_FB23_Pos (23U) 4740 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ 4741 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ 4742 #define CAN_F2R2_FB24_Pos (24U) 4743 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ 4744 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ 4745 #define CAN_F2R2_FB25_Pos (25U) 4746 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ 4747 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ 4748 #define CAN_F2R2_FB26_Pos (26U) 4749 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ 4750 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ 4751 #define CAN_F2R2_FB27_Pos (27U) 4752 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ 4753 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ 4754 #define CAN_F2R2_FB28_Pos (28U) 4755 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ 4756 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ 4757 #define CAN_F2R2_FB29_Pos (29U) 4758 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ 4759 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ 4760 #define CAN_F2R2_FB30_Pos (30U) 4761 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ 4762 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ 4763 #define CAN_F2R2_FB31_Pos (31U) 4764 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ 4765 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ 4766 4767 /******************* Bit definition for CAN_F3R2 register *******************/ 4768 #define CAN_F3R2_FB0_Pos (0U) 4769 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ 4770 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ 4771 #define CAN_F3R2_FB1_Pos (1U) 4772 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ 4773 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ 4774 #define CAN_F3R2_FB2_Pos (2U) 4775 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ 4776 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ 4777 #define CAN_F3R2_FB3_Pos (3U) 4778 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ 4779 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ 4780 #define CAN_F3R2_FB4_Pos (4U) 4781 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ 4782 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ 4783 #define CAN_F3R2_FB5_Pos (5U) 4784 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ 4785 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ 4786 #define CAN_F3R2_FB6_Pos (6U) 4787 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ 4788 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ 4789 #define CAN_F3R2_FB7_Pos (7U) 4790 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ 4791 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ 4792 #define CAN_F3R2_FB8_Pos (8U) 4793 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ 4794 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ 4795 #define CAN_F3R2_FB9_Pos (9U) 4796 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ 4797 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ 4798 #define CAN_F3R2_FB10_Pos (10U) 4799 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ 4800 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ 4801 #define CAN_F3R2_FB11_Pos (11U) 4802 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ 4803 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ 4804 #define CAN_F3R2_FB12_Pos (12U) 4805 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ 4806 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ 4807 #define CAN_F3R2_FB13_Pos (13U) 4808 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ 4809 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ 4810 #define CAN_F3R2_FB14_Pos (14U) 4811 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ 4812 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ 4813 #define CAN_F3R2_FB15_Pos (15U) 4814 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ 4815 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ 4816 #define CAN_F3R2_FB16_Pos (16U) 4817 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ 4818 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ 4819 #define CAN_F3R2_FB17_Pos (17U) 4820 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ 4821 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ 4822 #define CAN_F3R2_FB18_Pos (18U) 4823 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ 4824 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ 4825 #define CAN_F3R2_FB19_Pos (19U) 4826 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ 4827 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ 4828 #define CAN_F3R2_FB20_Pos (20U) 4829 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ 4830 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ 4831 #define CAN_F3R2_FB21_Pos (21U) 4832 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ 4833 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ 4834 #define CAN_F3R2_FB22_Pos (22U) 4835 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ 4836 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ 4837 #define CAN_F3R2_FB23_Pos (23U) 4838 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ 4839 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ 4840 #define CAN_F3R2_FB24_Pos (24U) 4841 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ 4842 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ 4843 #define CAN_F3R2_FB25_Pos (25U) 4844 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ 4845 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ 4846 #define CAN_F3R2_FB26_Pos (26U) 4847 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ 4848 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ 4849 #define CAN_F3R2_FB27_Pos (27U) 4850 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ 4851 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ 4852 #define CAN_F3R2_FB28_Pos (28U) 4853 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ 4854 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ 4855 #define CAN_F3R2_FB29_Pos (29U) 4856 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ 4857 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ 4858 #define CAN_F3R2_FB30_Pos (30U) 4859 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ 4860 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ 4861 #define CAN_F3R2_FB31_Pos (31U) 4862 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ 4863 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ 4864 4865 /******************* Bit definition for CAN_F4R2 register *******************/ 4866 #define CAN_F4R2_FB0_Pos (0U) 4867 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ 4868 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ 4869 #define CAN_F4R2_FB1_Pos (1U) 4870 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ 4871 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ 4872 #define CAN_F4R2_FB2_Pos (2U) 4873 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ 4874 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ 4875 #define CAN_F4R2_FB3_Pos (3U) 4876 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ 4877 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ 4878 #define CAN_F4R2_FB4_Pos (4U) 4879 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ 4880 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ 4881 #define CAN_F4R2_FB5_Pos (5U) 4882 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ 4883 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ 4884 #define CAN_F4R2_FB6_Pos (6U) 4885 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ 4886 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ 4887 #define CAN_F4R2_FB7_Pos (7U) 4888 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ 4889 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ 4890 #define CAN_F4R2_FB8_Pos (8U) 4891 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ 4892 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ 4893 #define CAN_F4R2_FB9_Pos (9U) 4894 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ 4895 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ 4896 #define CAN_F4R2_FB10_Pos (10U) 4897 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ 4898 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ 4899 #define CAN_F4R2_FB11_Pos (11U) 4900 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ 4901 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ 4902 #define CAN_F4R2_FB12_Pos (12U) 4903 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ 4904 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ 4905 #define CAN_F4R2_FB13_Pos (13U) 4906 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ 4907 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ 4908 #define CAN_F4R2_FB14_Pos (14U) 4909 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ 4910 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ 4911 #define CAN_F4R2_FB15_Pos (15U) 4912 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ 4913 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ 4914 #define CAN_F4R2_FB16_Pos (16U) 4915 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ 4916 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ 4917 #define CAN_F4R2_FB17_Pos (17U) 4918 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ 4919 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ 4920 #define CAN_F4R2_FB18_Pos (18U) 4921 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ 4922 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ 4923 #define CAN_F4R2_FB19_Pos (19U) 4924 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ 4925 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ 4926 #define CAN_F4R2_FB20_Pos (20U) 4927 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ 4928 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ 4929 #define CAN_F4R2_FB21_Pos (21U) 4930 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ 4931 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ 4932 #define CAN_F4R2_FB22_Pos (22U) 4933 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ 4934 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ 4935 #define CAN_F4R2_FB23_Pos (23U) 4936 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ 4937 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ 4938 #define CAN_F4R2_FB24_Pos (24U) 4939 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ 4940 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ 4941 #define CAN_F4R2_FB25_Pos (25U) 4942 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ 4943 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ 4944 #define CAN_F4R2_FB26_Pos (26U) 4945 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ 4946 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ 4947 #define CAN_F4R2_FB27_Pos (27U) 4948 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ 4949 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ 4950 #define CAN_F4R2_FB28_Pos (28U) 4951 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ 4952 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ 4953 #define CAN_F4R2_FB29_Pos (29U) 4954 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ 4955 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ 4956 #define CAN_F4R2_FB30_Pos (30U) 4957 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ 4958 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ 4959 #define CAN_F4R2_FB31_Pos (31U) 4960 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ 4961 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ 4962 4963 /******************* Bit definition for CAN_F5R2 register *******************/ 4964 #define CAN_F5R2_FB0_Pos (0U) 4965 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ 4966 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ 4967 #define CAN_F5R2_FB1_Pos (1U) 4968 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ 4969 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ 4970 #define CAN_F5R2_FB2_Pos (2U) 4971 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ 4972 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ 4973 #define CAN_F5R2_FB3_Pos (3U) 4974 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ 4975 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ 4976 #define CAN_F5R2_FB4_Pos (4U) 4977 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ 4978 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ 4979 #define CAN_F5R2_FB5_Pos (5U) 4980 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ 4981 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ 4982 #define CAN_F5R2_FB6_Pos (6U) 4983 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ 4984 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ 4985 #define CAN_F5R2_FB7_Pos (7U) 4986 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ 4987 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ 4988 #define CAN_F5R2_FB8_Pos (8U) 4989 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ 4990 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ 4991 #define CAN_F5R2_FB9_Pos (9U) 4992 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ 4993 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ 4994 #define CAN_F5R2_FB10_Pos (10U) 4995 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ 4996 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ 4997 #define CAN_F5R2_FB11_Pos (11U) 4998 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ 4999 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ 5000 #define CAN_F5R2_FB12_Pos (12U) 5001 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ 5002 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ 5003 #define CAN_F5R2_FB13_Pos (13U) 5004 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ 5005 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ 5006 #define CAN_F5R2_FB14_Pos (14U) 5007 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ 5008 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ 5009 #define CAN_F5R2_FB15_Pos (15U) 5010 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ 5011 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ 5012 #define CAN_F5R2_FB16_Pos (16U) 5013 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ 5014 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ 5015 #define CAN_F5R2_FB17_Pos (17U) 5016 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ 5017 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ 5018 #define CAN_F5R2_FB18_Pos (18U) 5019 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ 5020 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ 5021 #define CAN_F5R2_FB19_Pos (19U) 5022 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ 5023 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ 5024 #define CAN_F5R2_FB20_Pos (20U) 5025 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ 5026 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ 5027 #define CAN_F5R2_FB21_Pos (21U) 5028 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ 5029 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ 5030 #define CAN_F5R2_FB22_Pos (22U) 5031 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ 5032 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ 5033 #define CAN_F5R2_FB23_Pos (23U) 5034 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ 5035 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ 5036 #define CAN_F5R2_FB24_Pos (24U) 5037 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ 5038 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ 5039 #define CAN_F5R2_FB25_Pos (25U) 5040 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ 5041 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ 5042 #define CAN_F5R2_FB26_Pos (26U) 5043 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ 5044 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ 5045 #define CAN_F5R2_FB27_Pos (27U) 5046 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ 5047 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ 5048 #define CAN_F5R2_FB28_Pos (28U) 5049 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ 5050 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ 5051 #define CAN_F5R2_FB29_Pos (29U) 5052 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ 5053 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ 5054 #define CAN_F5R2_FB30_Pos (30U) 5055 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ 5056 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ 5057 #define CAN_F5R2_FB31_Pos (31U) 5058 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ 5059 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ 5060 5061 /******************* Bit definition for CAN_F6R2 register *******************/ 5062 #define CAN_F6R2_FB0_Pos (0U) 5063 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ 5064 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ 5065 #define CAN_F6R2_FB1_Pos (1U) 5066 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ 5067 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ 5068 #define CAN_F6R2_FB2_Pos (2U) 5069 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ 5070 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ 5071 #define CAN_F6R2_FB3_Pos (3U) 5072 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ 5073 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ 5074 #define CAN_F6R2_FB4_Pos (4U) 5075 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ 5076 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ 5077 #define CAN_F6R2_FB5_Pos (5U) 5078 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ 5079 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ 5080 #define CAN_F6R2_FB6_Pos (6U) 5081 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ 5082 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ 5083 #define CAN_F6R2_FB7_Pos (7U) 5084 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ 5085 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ 5086 #define CAN_F6R2_FB8_Pos (8U) 5087 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ 5088 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ 5089 #define CAN_F6R2_FB9_Pos (9U) 5090 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ 5091 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ 5092 #define CAN_F6R2_FB10_Pos (10U) 5093 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ 5094 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ 5095 #define CAN_F6R2_FB11_Pos (11U) 5096 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ 5097 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ 5098 #define CAN_F6R2_FB12_Pos (12U) 5099 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ 5100 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ 5101 #define CAN_F6R2_FB13_Pos (13U) 5102 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ 5103 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ 5104 #define CAN_F6R2_FB14_Pos (14U) 5105 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ 5106 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ 5107 #define CAN_F6R2_FB15_Pos (15U) 5108 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ 5109 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ 5110 #define CAN_F6R2_FB16_Pos (16U) 5111 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ 5112 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ 5113 #define CAN_F6R2_FB17_Pos (17U) 5114 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ 5115 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ 5116 #define CAN_F6R2_FB18_Pos (18U) 5117 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ 5118 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ 5119 #define CAN_F6R2_FB19_Pos (19U) 5120 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ 5121 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ 5122 #define CAN_F6R2_FB20_Pos (20U) 5123 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ 5124 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ 5125 #define CAN_F6R2_FB21_Pos (21U) 5126 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ 5127 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ 5128 #define CAN_F6R2_FB22_Pos (22U) 5129 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ 5130 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ 5131 #define CAN_F6R2_FB23_Pos (23U) 5132 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ 5133 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ 5134 #define CAN_F6R2_FB24_Pos (24U) 5135 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ 5136 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ 5137 #define CAN_F6R2_FB25_Pos (25U) 5138 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ 5139 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ 5140 #define CAN_F6R2_FB26_Pos (26U) 5141 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ 5142 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ 5143 #define CAN_F6R2_FB27_Pos (27U) 5144 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ 5145 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ 5146 #define CAN_F6R2_FB28_Pos (28U) 5147 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ 5148 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ 5149 #define CAN_F6R2_FB29_Pos (29U) 5150 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ 5151 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ 5152 #define CAN_F6R2_FB30_Pos (30U) 5153 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ 5154 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ 5155 #define CAN_F6R2_FB31_Pos (31U) 5156 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ 5157 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ 5158 5159 /******************* Bit definition for CAN_F7R2 register *******************/ 5160 #define CAN_F7R2_FB0_Pos (0U) 5161 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ 5162 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ 5163 #define CAN_F7R2_FB1_Pos (1U) 5164 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ 5165 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ 5166 #define CAN_F7R2_FB2_Pos (2U) 5167 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ 5168 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ 5169 #define CAN_F7R2_FB3_Pos (3U) 5170 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ 5171 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ 5172 #define CAN_F7R2_FB4_Pos (4U) 5173 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ 5174 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ 5175 #define CAN_F7R2_FB5_Pos (5U) 5176 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ 5177 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ 5178 #define CAN_F7R2_FB6_Pos (6U) 5179 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ 5180 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ 5181 #define CAN_F7R2_FB7_Pos (7U) 5182 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ 5183 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ 5184 #define CAN_F7R2_FB8_Pos (8U) 5185 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ 5186 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ 5187 #define CAN_F7R2_FB9_Pos (9U) 5188 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ 5189 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ 5190 #define CAN_F7R2_FB10_Pos (10U) 5191 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ 5192 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ 5193 #define CAN_F7R2_FB11_Pos (11U) 5194 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ 5195 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ 5196 #define CAN_F7R2_FB12_Pos (12U) 5197 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ 5198 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ 5199 #define CAN_F7R2_FB13_Pos (13U) 5200 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ 5201 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ 5202 #define CAN_F7R2_FB14_Pos (14U) 5203 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ 5204 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ 5205 #define CAN_F7R2_FB15_Pos (15U) 5206 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ 5207 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ 5208 #define CAN_F7R2_FB16_Pos (16U) 5209 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ 5210 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ 5211 #define CAN_F7R2_FB17_Pos (17U) 5212 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ 5213 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ 5214 #define CAN_F7R2_FB18_Pos (18U) 5215 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ 5216 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ 5217 #define CAN_F7R2_FB19_Pos (19U) 5218 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ 5219 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ 5220 #define CAN_F7R2_FB20_Pos (20U) 5221 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ 5222 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ 5223 #define CAN_F7R2_FB21_Pos (21U) 5224 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ 5225 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ 5226 #define CAN_F7R2_FB22_Pos (22U) 5227 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ 5228 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ 5229 #define CAN_F7R2_FB23_Pos (23U) 5230 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ 5231 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ 5232 #define CAN_F7R2_FB24_Pos (24U) 5233 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ 5234 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ 5235 #define CAN_F7R2_FB25_Pos (25U) 5236 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ 5237 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ 5238 #define CAN_F7R2_FB26_Pos (26U) 5239 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ 5240 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ 5241 #define CAN_F7R2_FB27_Pos (27U) 5242 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ 5243 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ 5244 #define CAN_F7R2_FB28_Pos (28U) 5245 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ 5246 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ 5247 #define CAN_F7R2_FB29_Pos (29U) 5248 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ 5249 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ 5250 #define CAN_F7R2_FB30_Pos (30U) 5251 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ 5252 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ 5253 #define CAN_F7R2_FB31_Pos (31U) 5254 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ 5255 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ 5256 5257 /******************* Bit definition for CAN_F8R2 register *******************/ 5258 #define CAN_F8R2_FB0_Pos (0U) 5259 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ 5260 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ 5261 #define CAN_F8R2_FB1_Pos (1U) 5262 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ 5263 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ 5264 #define CAN_F8R2_FB2_Pos (2U) 5265 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ 5266 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ 5267 #define CAN_F8R2_FB3_Pos (3U) 5268 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ 5269 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ 5270 #define CAN_F8R2_FB4_Pos (4U) 5271 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ 5272 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ 5273 #define CAN_F8R2_FB5_Pos (5U) 5274 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ 5275 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ 5276 #define CAN_F8R2_FB6_Pos (6U) 5277 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ 5278 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ 5279 #define CAN_F8R2_FB7_Pos (7U) 5280 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ 5281 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ 5282 #define CAN_F8R2_FB8_Pos (8U) 5283 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ 5284 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ 5285 #define CAN_F8R2_FB9_Pos (9U) 5286 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ 5287 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ 5288 #define CAN_F8R2_FB10_Pos (10U) 5289 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ 5290 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ 5291 #define CAN_F8R2_FB11_Pos (11U) 5292 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ 5293 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ 5294 #define CAN_F8R2_FB12_Pos (12U) 5295 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ 5296 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ 5297 #define CAN_F8R2_FB13_Pos (13U) 5298 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ 5299 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ 5300 #define CAN_F8R2_FB14_Pos (14U) 5301 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ 5302 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ 5303 #define CAN_F8R2_FB15_Pos (15U) 5304 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ 5305 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ 5306 #define CAN_F8R2_FB16_Pos (16U) 5307 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ 5308 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ 5309 #define CAN_F8R2_FB17_Pos (17U) 5310 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ 5311 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ 5312 #define CAN_F8R2_FB18_Pos (18U) 5313 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ 5314 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ 5315 #define CAN_F8R2_FB19_Pos (19U) 5316 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ 5317 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ 5318 #define CAN_F8R2_FB20_Pos (20U) 5319 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ 5320 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ 5321 #define CAN_F8R2_FB21_Pos (21U) 5322 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ 5323 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ 5324 #define CAN_F8R2_FB22_Pos (22U) 5325 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ 5326 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ 5327 #define CAN_F8R2_FB23_Pos (23U) 5328 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ 5329 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ 5330 #define CAN_F8R2_FB24_Pos (24U) 5331 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ 5332 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ 5333 #define CAN_F8R2_FB25_Pos (25U) 5334 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ 5335 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ 5336 #define CAN_F8R2_FB26_Pos (26U) 5337 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ 5338 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ 5339 #define CAN_F8R2_FB27_Pos (27U) 5340 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ 5341 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ 5342 #define CAN_F8R2_FB28_Pos (28U) 5343 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ 5344 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ 5345 #define CAN_F8R2_FB29_Pos (29U) 5346 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ 5347 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ 5348 #define CAN_F8R2_FB30_Pos (30U) 5349 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ 5350 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ 5351 #define CAN_F8R2_FB31_Pos (31U) 5352 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ 5353 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ 5354 5355 /******************* Bit definition for CAN_F9R2 register *******************/ 5356 #define CAN_F9R2_FB0_Pos (0U) 5357 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ 5358 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ 5359 #define CAN_F9R2_FB1_Pos (1U) 5360 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ 5361 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ 5362 #define CAN_F9R2_FB2_Pos (2U) 5363 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ 5364 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ 5365 #define CAN_F9R2_FB3_Pos (3U) 5366 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ 5367 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ 5368 #define CAN_F9R2_FB4_Pos (4U) 5369 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ 5370 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ 5371 #define CAN_F9R2_FB5_Pos (5U) 5372 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ 5373 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ 5374 #define CAN_F9R2_FB6_Pos (6U) 5375 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ 5376 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ 5377 #define CAN_F9R2_FB7_Pos (7U) 5378 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ 5379 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ 5380 #define CAN_F9R2_FB8_Pos (8U) 5381 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ 5382 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ 5383 #define CAN_F9R2_FB9_Pos (9U) 5384 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ 5385 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ 5386 #define CAN_F9R2_FB10_Pos (10U) 5387 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ 5388 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ 5389 #define CAN_F9R2_FB11_Pos (11U) 5390 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ 5391 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ 5392 #define CAN_F9R2_FB12_Pos (12U) 5393 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ 5394 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ 5395 #define CAN_F9R2_FB13_Pos (13U) 5396 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ 5397 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ 5398 #define CAN_F9R2_FB14_Pos (14U) 5399 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ 5400 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ 5401 #define CAN_F9R2_FB15_Pos (15U) 5402 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ 5403 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ 5404 #define CAN_F9R2_FB16_Pos (16U) 5405 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ 5406 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ 5407 #define CAN_F9R2_FB17_Pos (17U) 5408 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ 5409 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ 5410 #define CAN_F9R2_FB18_Pos (18U) 5411 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ 5412 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ 5413 #define CAN_F9R2_FB19_Pos (19U) 5414 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ 5415 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ 5416 #define CAN_F9R2_FB20_Pos (20U) 5417 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ 5418 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ 5419 #define CAN_F9R2_FB21_Pos (21U) 5420 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ 5421 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ 5422 #define CAN_F9R2_FB22_Pos (22U) 5423 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ 5424 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ 5425 #define CAN_F9R2_FB23_Pos (23U) 5426 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ 5427 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ 5428 #define CAN_F9R2_FB24_Pos (24U) 5429 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ 5430 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ 5431 #define CAN_F9R2_FB25_Pos (25U) 5432 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ 5433 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ 5434 #define CAN_F9R2_FB26_Pos (26U) 5435 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ 5436 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ 5437 #define CAN_F9R2_FB27_Pos (27U) 5438 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ 5439 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ 5440 #define CAN_F9R2_FB28_Pos (28U) 5441 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ 5442 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ 5443 #define CAN_F9R2_FB29_Pos (29U) 5444 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ 5445 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ 5446 #define CAN_F9R2_FB30_Pos (30U) 5447 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ 5448 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ 5449 #define CAN_F9R2_FB31_Pos (31U) 5450 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ 5451 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ 5452 5453 /******************* Bit definition for CAN_F10R2 register ******************/ 5454 #define CAN_F10R2_FB0_Pos (0U) 5455 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ 5456 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ 5457 #define CAN_F10R2_FB1_Pos (1U) 5458 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ 5459 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ 5460 #define CAN_F10R2_FB2_Pos (2U) 5461 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ 5462 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ 5463 #define CAN_F10R2_FB3_Pos (3U) 5464 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ 5465 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ 5466 #define CAN_F10R2_FB4_Pos (4U) 5467 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ 5468 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ 5469 #define CAN_F10R2_FB5_Pos (5U) 5470 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ 5471 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ 5472 #define CAN_F10R2_FB6_Pos (6U) 5473 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ 5474 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ 5475 #define CAN_F10R2_FB7_Pos (7U) 5476 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ 5477 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ 5478 #define CAN_F10R2_FB8_Pos (8U) 5479 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ 5480 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ 5481 #define CAN_F10R2_FB9_Pos (9U) 5482 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ 5483 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ 5484 #define CAN_F10R2_FB10_Pos (10U) 5485 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ 5486 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ 5487 #define CAN_F10R2_FB11_Pos (11U) 5488 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ 5489 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ 5490 #define CAN_F10R2_FB12_Pos (12U) 5491 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ 5492 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ 5493 #define CAN_F10R2_FB13_Pos (13U) 5494 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ 5495 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ 5496 #define CAN_F10R2_FB14_Pos (14U) 5497 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ 5498 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ 5499 #define CAN_F10R2_FB15_Pos (15U) 5500 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ 5501 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ 5502 #define CAN_F10R2_FB16_Pos (16U) 5503 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ 5504 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ 5505 #define CAN_F10R2_FB17_Pos (17U) 5506 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ 5507 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ 5508 #define CAN_F10R2_FB18_Pos (18U) 5509 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ 5510 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ 5511 #define CAN_F10R2_FB19_Pos (19U) 5512 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ 5513 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ 5514 #define CAN_F10R2_FB20_Pos (20U) 5515 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ 5516 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ 5517 #define CAN_F10R2_FB21_Pos (21U) 5518 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ 5519 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ 5520 #define CAN_F10R2_FB22_Pos (22U) 5521 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ 5522 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ 5523 #define CAN_F10R2_FB23_Pos (23U) 5524 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ 5525 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ 5526 #define CAN_F10R2_FB24_Pos (24U) 5527 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ 5528 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ 5529 #define CAN_F10R2_FB25_Pos (25U) 5530 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ 5531 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ 5532 #define CAN_F10R2_FB26_Pos (26U) 5533 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ 5534 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ 5535 #define CAN_F10R2_FB27_Pos (27U) 5536 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ 5537 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ 5538 #define CAN_F10R2_FB28_Pos (28U) 5539 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ 5540 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ 5541 #define CAN_F10R2_FB29_Pos (29U) 5542 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ 5543 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ 5544 #define CAN_F10R2_FB30_Pos (30U) 5545 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ 5546 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ 5547 #define CAN_F10R2_FB31_Pos (31U) 5548 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ 5549 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ 5550 5551 /******************* Bit definition for CAN_F11R2 register ******************/ 5552 #define CAN_F11R2_FB0_Pos (0U) 5553 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ 5554 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ 5555 #define CAN_F11R2_FB1_Pos (1U) 5556 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ 5557 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ 5558 #define CAN_F11R2_FB2_Pos (2U) 5559 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ 5560 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ 5561 #define CAN_F11R2_FB3_Pos (3U) 5562 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ 5563 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ 5564 #define CAN_F11R2_FB4_Pos (4U) 5565 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ 5566 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ 5567 #define CAN_F11R2_FB5_Pos (5U) 5568 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ 5569 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ 5570 #define CAN_F11R2_FB6_Pos (6U) 5571 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ 5572 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ 5573 #define CAN_F11R2_FB7_Pos (7U) 5574 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ 5575 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ 5576 #define CAN_F11R2_FB8_Pos (8U) 5577 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ 5578 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ 5579 #define CAN_F11R2_FB9_Pos (9U) 5580 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ 5581 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ 5582 #define CAN_F11R2_FB10_Pos (10U) 5583 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ 5584 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ 5585 #define CAN_F11R2_FB11_Pos (11U) 5586 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ 5587 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ 5588 #define CAN_F11R2_FB12_Pos (12U) 5589 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ 5590 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ 5591 #define CAN_F11R2_FB13_Pos (13U) 5592 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ 5593 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ 5594 #define CAN_F11R2_FB14_Pos (14U) 5595 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ 5596 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ 5597 #define CAN_F11R2_FB15_Pos (15U) 5598 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ 5599 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ 5600 #define CAN_F11R2_FB16_Pos (16U) 5601 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ 5602 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ 5603 #define CAN_F11R2_FB17_Pos (17U) 5604 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ 5605 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ 5606 #define CAN_F11R2_FB18_Pos (18U) 5607 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ 5608 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ 5609 #define CAN_F11R2_FB19_Pos (19U) 5610 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ 5611 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ 5612 #define CAN_F11R2_FB20_Pos (20U) 5613 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ 5614 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ 5615 #define CAN_F11R2_FB21_Pos (21U) 5616 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ 5617 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ 5618 #define CAN_F11R2_FB22_Pos (22U) 5619 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ 5620 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ 5621 #define CAN_F11R2_FB23_Pos (23U) 5622 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ 5623 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ 5624 #define CAN_F11R2_FB24_Pos (24U) 5625 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ 5626 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ 5627 #define CAN_F11R2_FB25_Pos (25U) 5628 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ 5629 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ 5630 #define CAN_F11R2_FB26_Pos (26U) 5631 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ 5632 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ 5633 #define CAN_F11R2_FB27_Pos (27U) 5634 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ 5635 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ 5636 #define CAN_F11R2_FB28_Pos (28U) 5637 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ 5638 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ 5639 #define CAN_F11R2_FB29_Pos (29U) 5640 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ 5641 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ 5642 #define CAN_F11R2_FB30_Pos (30U) 5643 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ 5644 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ 5645 #define CAN_F11R2_FB31_Pos (31U) 5646 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ 5647 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ 5648 5649 /******************* Bit definition for CAN_F12R2 register ******************/ 5650 #define CAN_F12R2_FB0_Pos (0U) 5651 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ 5652 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ 5653 #define CAN_F12R2_FB1_Pos (1U) 5654 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ 5655 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ 5656 #define CAN_F12R2_FB2_Pos (2U) 5657 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ 5658 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ 5659 #define CAN_F12R2_FB3_Pos (3U) 5660 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ 5661 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ 5662 #define CAN_F12R2_FB4_Pos (4U) 5663 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ 5664 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ 5665 #define CAN_F12R2_FB5_Pos (5U) 5666 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ 5667 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ 5668 #define CAN_F12R2_FB6_Pos (6U) 5669 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ 5670 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ 5671 #define CAN_F12R2_FB7_Pos (7U) 5672 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ 5673 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ 5674 #define CAN_F12R2_FB8_Pos (8U) 5675 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ 5676 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ 5677 #define CAN_F12R2_FB9_Pos (9U) 5678 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ 5679 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ 5680 #define CAN_F12R2_FB10_Pos (10U) 5681 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ 5682 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ 5683 #define CAN_F12R2_FB11_Pos (11U) 5684 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ 5685 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ 5686 #define CAN_F12R2_FB12_Pos (12U) 5687 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ 5688 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ 5689 #define CAN_F12R2_FB13_Pos (13U) 5690 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ 5691 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ 5692 #define CAN_F12R2_FB14_Pos (14U) 5693 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ 5694 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ 5695 #define CAN_F12R2_FB15_Pos (15U) 5696 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ 5697 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ 5698 #define CAN_F12R2_FB16_Pos (16U) 5699 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ 5700 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ 5701 #define CAN_F12R2_FB17_Pos (17U) 5702 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ 5703 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ 5704 #define CAN_F12R2_FB18_Pos (18U) 5705 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ 5706 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ 5707 #define CAN_F12R2_FB19_Pos (19U) 5708 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ 5709 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ 5710 #define CAN_F12R2_FB20_Pos (20U) 5711 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ 5712 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ 5713 #define CAN_F12R2_FB21_Pos (21U) 5714 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ 5715 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ 5716 #define CAN_F12R2_FB22_Pos (22U) 5717 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ 5718 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ 5719 #define CAN_F12R2_FB23_Pos (23U) 5720 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ 5721 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ 5722 #define CAN_F12R2_FB24_Pos (24U) 5723 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ 5724 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ 5725 #define CAN_F12R2_FB25_Pos (25U) 5726 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ 5727 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ 5728 #define CAN_F12R2_FB26_Pos (26U) 5729 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ 5730 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ 5731 #define CAN_F12R2_FB27_Pos (27U) 5732 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ 5733 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ 5734 #define CAN_F12R2_FB28_Pos (28U) 5735 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ 5736 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ 5737 #define CAN_F12R2_FB29_Pos (29U) 5738 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ 5739 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ 5740 #define CAN_F12R2_FB30_Pos (30U) 5741 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ 5742 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ 5743 #define CAN_F12R2_FB31_Pos (31U) 5744 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ 5745 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ 5746 5747 /******************* Bit definition for CAN_F13R2 register ******************/ 5748 #define CAN_F13R2_FB0_Pos (0U) 5749 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ 5750 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ 5751 #define CAN_F13R2_FB1_Pos (1U) 5752 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ 5753 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ 5754 #define CAN_F13R2_FB2_Pos (2U) 5755 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ 5756 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ 5757 #define CAN_F13R2_FB3_Pos (3U) 5758 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ 5759 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ 5760 #define CAN_F13R2_FB4_Pos (4U) 5761 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ 5762 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ 5763 #define CAN_F13R2_FB5_Pos (5U) 5764 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ 5765 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ 5766 #define CAN_F13R2_FB6_Pos (6U) 5767 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ 5768 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ 5769 #define CAN_F13R2_FB7_Pos (7U) 5770 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ 5771 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ 5772 #define CAN_F13R2_FB8_Pos (8U) 5773 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ 5774 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ 5775 #define CAN_F13R2_FB9_Pos (9U) 5776 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ 5777 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ 5778 #define CAN_F13R2_FB10_Pos (10U) 5779 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ 5780 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ 5781 #define CAN_F13R2_FB11_Pos (11U) 5782 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ 5783 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ 5784 #define CAN_F13R2_FB12_Pos (12U) 5785 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ 5786 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ 5787 #define CAN_F13R2_FB13_Pos (13U) 5788 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ 5789 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ 5790 #define CAN_F13R2_FB14_Pos (14U) 5791 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ 5792 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ 5793 #define CAN_F13R2_FB15_Pos (15U) 5794 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ 5795 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ 5796 #define CAN_F13R2_FB16_Pos (16U) 5797 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ 5798 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ 5799 #define CAN_F13R2_FB17_Pos (17U) 5800 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ 5801 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ 5802 #define CAN_F13R2_FB18_Pos (18U) 5803 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ 5804 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ 5805 #define CAN_F13R2_FB19_Pos (19U) 5806 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ 5807 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ 5808 #define CAN_F13R2_FB20_Pos (20U) 5809 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ 5810 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ 5811 #define CAN_F13R2_FB21_Pos (21U) 5812 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ 5813 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ 5814 #define CAN_F13R2_FB22_Pos (22U) 5815 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ 5816 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ 5817 #define CAN_F13R2_FB23_Pos (23U) 5818 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ 5819 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ 5820 #define CAN_F13R2_FB24_Pos (24U) 5821 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ 5822 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ 5823 #define CAN_F13R2_FB25_Pos (25U) 5824 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ 5825 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ 5826 #define CAN_F13R2_FB26_Pos (26U) 5827 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ 5828 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ 5829 #define CAN_F13R2_FB27_Pos (27U) 5830 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ 5831 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ 5832 #define CAN_F13R2_FB28_Pos (28U) 5833 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ 5834 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ 5835 #define CAN_F13R2_FB29_Pos (29U) 5836 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ 5837 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ 5838 #define CAN_F13R2_FB30_Pos (30U) 5839 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ 5840 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ 5841 #define CAN_F13R2_FB31_Pos (31U) 5842 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ 5843 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ 5844 5845 /******************************************************************************/ 5846 /* */ 5847 /* CRC calculation unit (CRC) */ 5848 /* */ 5849 /******************************************************************************/ 5850 /******************* Bit definition for CRC_DR register *********************/ 5851 #define CRC_DR_DR_Pos (0U) 5852 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 5853 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 5854 5855 /******************* Bit definition for CRC_IDR register ********************/ 5856 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 5857 5858 /******************** Bit definition for CRC_CR register ********************/ 5859 #define CRC_CR_RESET_Pos (0U) 5860 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 5861 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 5862 #define CRC_CR_POLYSIZE_Pos (3U) 5863 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 5864 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 5865 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 5866 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 5867 #define CRC_CR_REV_IN_Pos (5U) 5868 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 5869 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 5870 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 5871 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 5872 #define CRC_CR_REV_OUT_Pos (7U) 5873 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 5874 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 5875 5876 /******************* Bit definition for CRC_INIT register *******************/ 5877 #define CRC_INIT_INIT_Pos (0U) 5878 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 5879 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 5880 5881 /******************* Bit definition for CRC_POL register ********************/ 5882 #define CRC_POL_POL_Pos (0U) 5883 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 5884 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 5885 5886 /******************************************************************************/ 5887 /* */ 5888 /* Digital to Analog Converter (DAC) */ 5889 /* */ 5890 /******************************************************************************/ 5891 5892 /* 5893 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 5894 */ 5895 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */ 5896 5897 5898 /******************** Bit definition for DAC_CR register ********************/ 5899 #define DAC_CR_EN1_Pos (0U) 5900 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 5901 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ 5902 #define DAC_CR_BOFF1_Pos (1U) 5903 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 5904 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ 5905 #define DAC_CR_OUTEN1_Pos (1U) 5906 #define DAC_CR_OUTEN1_Msk (0x1UL << DAC_CR_OUTEN1_Pos) /*!< 0x00000002 */ 5907 #define DAC_CR_OUTEN1 DAC_CR_OUTEN1_Msk /*!< DAC channel1 output switch enable (only for DAC instance: DAC2) */ 5908 #define DAC_CR_TEN1_Pos (2U) 5909 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 5910 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ 5911 5912 #define DAC_CR_TSEL1_Pos (3U) 5913 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 5914 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 5915 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 5916 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 5917 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 5918 5919 #define DAC_CR_WAVE1_Pos (6U) 5920 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 5921 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 5922 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 5923 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 5924 5925 #define DAC_CR_MAMP1_Pos (8U) 5926 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 5927 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 5928 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 5929 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 5930 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 5931 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 5932 5933 #define DAC_CR_DMAEN1_Pos (12U) 5934 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 5935 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ 5936 #define DAC_CR_DMAUDRIE1_Pos (13U) 5937 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 5938 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun IT enable */ 5939 #define DAC_CR_EN2_Pos (16U) 5940 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 5941 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ 5942 #define DAC_CR_BOFF2_Pos (17U) 5943 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 5944 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ 5945 #define DAC_CR_OUTEN2_Pos (17U) 5946 #define DAC_CR_OUTEN2_Msk (0x1UL << DAC_CR_OUTEN2_Pos) /*!< 0x00020000 */ 5947 #define DAC_CR_OUTEN2 DAC_CR_OUTEN2_Msk /*!< DAC channel2 output switch enable (only for DAC instance: DAC2) */ 5948 #define DAC_CR_TEN2_Pos (18U) 5949 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 5950 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ 5951 5952 #define DAC_CR_TSEL2_Pos (19U) 5953 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 5954 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ 5955 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 5956 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 5957 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 5958 5959 #define DAC_CR_WAVE2_Pos (22U) 5960 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 5961 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 5962 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 5963 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 5964 5965 #define DAC_CR_MAMP2_Pos (24U) 5966 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 5967 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 5968 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 5969 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 5970 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 5971 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 5972 5973 #define DAC_CR_DMAEN2_Pos (28U) 5974 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 5975 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ 5976 #define DAC_CR_DMAUDRIE2_Pos (29U) 5977 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 5978 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun IT enable */ 5979 5980 /***************** Bit definition for DAC_SWTRIGR register ******************/ 5981 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 5982 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 5983 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ 5984 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 5985 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 5986 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ 5987 5988 /***************** Bit definition for DAC_DHR12R1 register ******************/ 5989 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 5990 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 5991 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 5992 5993 /***************** Bit definition for DAC_DHR12L1 register ******************/ 5994 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 5995 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 5996 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 5997 5998 /****************** Bit definition for DAC_DHR8R1 register ******************/ 5999 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 6000 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 6001 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 6002 6003 /***************** Bit definition for DAC_DHR12R2 register ******************/ 6004 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 6005 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 6006 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 6007 6008 /***************** Bit definition for DAC_DHR12L2 register ******************/ 6009 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 6010 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 6011 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 6012 6013 /****************** Bit definition for DAC_DHR8R2 register ******************/ 6014 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 6015 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 6016 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 6017 6018 /***************** Bit definition for DAC_DHR12RD register ******************/ 6019 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 6020 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 6021 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 6022 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 6023 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 6024 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 6025 6026 /***************** Bit definition for DAC_DHR12LD register ******************/ 6027 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 6028 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 6029 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 6030 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 6031 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 6032 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 6033 6034 /****************** Bit definition for DAC_DHR8RD register ******************/ 6035 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 6036 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 6037 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 6038 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 6039 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 6040 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 6041 6042 /******************* Bit definition for DAC_DOR1 register *******************/ 6043 #define DAC_DOR1_DACC1DOR_Pos (0U) 6044 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 6045 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ 6046 6047 /******************* Bit definition for DAC_DOR2 register *******************/ 6048 #define DAC_DOR2_DACC2DOR_Pos (0U) 6049 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 6050 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ 6051 6052 /******************** Bit definition for DAC_SR register ********************/ 6053 #define DAC_SR_DMAUDR1_Pos (13U) 6054 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 6055 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ 6056 #define DAC_SR_DMAUDR2_Pos (29U) 6057 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 6058 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ 6059 6060 /******************************************************************************/ 6061 /* */ 6062 /* Debug MCU (DBGMCU) */ 6063 /* */ 6064 /******************************************************************************/ 6065 /******************** Bit definition for DBGMCU_IDCODE register *************/ 6066 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 6067 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 6068 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 6069 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 6070 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 6071 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 6072 6073 /******************** Bit definition for DBGMCU_CR register *****************/ 6074 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 6075 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 6076 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 6077 #define DBGMCU_CR_DBG_STOP_Pos (1U) 6078 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 6079 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 6080 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 6081 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 6082 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 6083 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 6084 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 6085 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 6086 6087 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 6088 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 6089 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 6090 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 6091 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 6092 6093 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 6094 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 6095 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 6096 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 6097 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 6098 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 6099 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 6100 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 6101 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 6102 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 6103 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 6104 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 6105 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 6106 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 6107 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 6108 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 6109 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 6110 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 6111 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 6112 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 6113 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 6114 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 6115 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 6116 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 6117 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 6118 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U) 6119 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */ 6120 #define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk 6121 6122 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 6123 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) 6124 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ 6125 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 6126 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U) 6127 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */ 6128 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk 6129 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U) 6130 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */ 6131 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk 6132 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U) 6133 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */ 6134 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk 6135 6136 /******************************************************************************/ 6137 /* */ 6138 /* DMA Controller (DMA) */ 6139 /* */ 6140 /******************************************************************************/ 6141 /******************* Bit definition for DMA_ISR register ********************/ 6142 #define DMA_ISR_GIF1_Pos (0U) 6143 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 6144 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 6145 #define DMA_ISR_TCIF1_Pos (1U) 6146 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 6147 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 6148 #define DMA_ISR_HTIF1_Pos (2U) 6149 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 6150 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 6151 #define DMA_ISR_TEIF1_Pos (3U) 6152 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 6153 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 6154 #define DMA_ISR_GIF2_Pos (4U) 6155 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 6156 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 6157 #define DMA_ISR_TCIF2_Pos (5U) 6158 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 6159 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 6160 #define DMA_ISR_HTIF2_Pos (6U) 6161 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 6162 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 6163 #define DMA_ISR_TEIF2_Pos (7U) 6164 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 6165 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 6166 #define DMA_ISR_GIF3_Pos (8U) 6167 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 6168 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 6169 #define DMA_ISR_TCIF3_Pos (9U) 6170 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 6171 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 6172 #define DMA_ISR_HTIF3_Pos (10U) 6173 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 6174 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 6175 #define DMA_ISR_TEIF3_Pos (11U) 6176 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 6177 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 6178 #define DMA_ISR_GIF4_Pos (12U) 6179 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 6180 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 6181 #define DMA_ISR_TCIF4_Pos (13U) 6182 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 6183 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 6184 #define DMA_ISR_HTIF4_Pos (14U) 6185 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 6186 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 6187 #define DMA_ISR_TEIF4_Pos (15U) 6188 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 6189 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 6190 #define DMA_ISR_GIF5_Pos (16U) 6191 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 6192 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 6193 #define DMA_ISR_TCIF5_Pos (17U) 6194 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 6195 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 6196 #define DMA_ISR_HTIF5_Pos (18U) 6197 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 6198 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 6199 #define DMA_ISR_TEIF5_Pos (19U) 6200 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 6201 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 6202 #define DMA_ISR_GIF6_Pos (20U) 6203 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 6204 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 6205 #define DMA_ISR_TCIF6_Pos (21U) 6206 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 6207 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 6208 #define DMA_ISR_HTIF6_Pos (22U) 6209 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 6210 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 6211 #define DMA_ISR_TEIF6_Pos (23U) 6212 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 6213 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 6214 #define DMA_ISR_GIF7_Pos (24U) 6215 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 6216 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 6217 #define DMA_ISR_TCIF7_Pos (25U) 6218 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 6219 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 6220 #define DMA_ISR_HTIF7_Pos (26U) 6221 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 6222 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 6223 #define DMA_ISR_TEIF7_Pos (27U) 6224 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 6225 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 6226 6227 /******************* Bit definition for DMA_IFCR register *******************/ 6228 #define DMA_IFCR_CGIF1_Pos (0U) 6229 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 6230 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 6231 #define DMA_IFCR_CTCIF1_Pos (1U) 6232 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 6233 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 6234 #define DMA_IFCR_CHTIF1_Pos (2U) 6235 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 6236 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 6237 #define DMA_IFCR_CTEIF1_Pos (3U) 6238 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 6239 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 6240 #define DMA_IFCR_CGIF2_Pos (4U) 6241 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 6242 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 6243 #define DMA_IFCR_CTCIF2_Pos (5U) 6244 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 6245 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 6246 #define DMA_IFCR_CHTIF2_Pos (6U) 6247 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 6248 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 6249 #define DMA_IFCR_CTEIF2_Pos (7U) 6250 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 6251 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 6252 #define DMA_IFCR_CGIF3_Pos (8U) 6253 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 6254 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 6255 #define DMA_IFCR_CTCIF3_Pos (9U) 6256 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 6257 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 6258 #define DMA_IFCR_CHTIF3_Pos (10U) 6259 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 6260 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 6261 #define DMA_IFCR_CTEIF3_Pos (11U) 6262 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 6263 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 6264 #define DMA_IFCR_CGIF4_Pos (12U) 6265 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 6266 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 6267 #define DMA_IFCR_CTCIF4_Pos (13U) 6268 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 6269 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 6270 #define DMA_IFCR_CHTIF4_Pos (14U) 6271 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 6272 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 6273 #define DMA_IFCR_CTEIF4_Pos (15U) 6274 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 6275 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 6276 #define DMA_IFCR_CGIF5_Pos (16U) 6277 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 6278 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 6279 #define DMA_IFCR_CTCIF5_Pos (17U) 6280 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 6281 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 6282 #define DMA_IFCR_CHTIF5_Pos (18U) 6283 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 6284 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 6285 #define DMA_IFCR_CTEIF5_Pos (19U) 6286 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 6287 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 6288 #define DMA_IFCR_CGIF6_Pos (20U) 6289 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 6290 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 6291 #define DMA_IFCR_CTCIF6_Pos (21U) 6292 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 6293 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 6294 #define DMA_IFCR_CHTIF6_Pos (22U) 6295 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 6296 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 6297 #define DMA_IFCR_CTEIF6_Pos (23U) 6298 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 6299 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 6300 #define DMA_IFCR_CGIF7_Pos (24U) 6301 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 6302 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 6303 #define DMA_IFCR_CTCIF7_Pos (25U) 6304 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 6305 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 6306 #define DMA_IFCR_CHTIF7_Pos (26U) 6307 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 6308 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 6309 #define DMA_IFCR_CTEIF7_Pos (27U) 6310 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 6311 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 6312 6313 /******************* Bit definition for DMA_CCR register ********************/ 6314 #define DMA_CCR_EN_Pos (0U) 6315 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 6316 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 6317 #define DMA_CCR_TCIE_Pos (1U) 6318 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 6319 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 6320 #define DMA_CCR_HTIE_Pos (2U) 6321 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 6322 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 6323 #define DMA_CCR_TEIE_Pos (3U) 6324 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 6325 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 6326 #define DMA_CCR_DIR_Pos (4U) 6327 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 6328 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 6329 #define DMA_CCR_CIRC_Pos (5U) 6330 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 6331 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 6332 #define DMA_CCR_PINC_Pos (6U) 6333 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 6334 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 6335 #define DMA_CCR_MINC_Pos (7U) 6336 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 6337 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 6338 6339 #define DMA_CCR_PSIZE_Pos (8U) 6340 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 6341 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 6342 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 6343 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 6344 6345 #define DMA_CCR_MSIZE_Pos (10U) 6346 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 6347 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 6348 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 6349 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 6350 6351 #define DMA_CCR_PL_Pos (12U) 6352 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 6353 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 6354 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 6355 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 6356 6357 #define DMA_CCR_MEM2MEM_Pos (14U) 6358 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 6359 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 6360 6361 /****************** Bit definition for DMA_CNDTR register *******************/ 6362 #define DMA_CNDTR_NDT_Pos (0U) 6363 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 6364 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 6365 6366 /****************** Bit definition for DMA_CPAR register ********************/ 6367 #define DMA_CPAR_PA_Pos (0U) 6368 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 6369 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 6370 6371 /****************** Bit definition for DMA_CMAR register ********************/ 6372 #define DMA_CMAR_MA_Pos (0U) 6373 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 6374 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 6375 6376 /******************************************************************************/ 6377 /* */ 6378 /* External Interrupt/Event Controller (EXTI) */ 6379 /* */ 6380 /******************************************************************************/ 6381 /******************* Bit definition for EXTI_IMR register *******************/ 6382 #define EXTI_IMR_MR0_Pos (0U) 6383 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 6384 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 6385 #define EXTI_IMR_MR1_Pos (1U) 6386 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 6387 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 6388 #define EXTI_IMR_MR2_Pos (2U) 6389 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 6390 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 6391 #define EXTI_IMR_MR3_Pos (3U) 6392 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 6393 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 6394 #define EXTI_IMR_MR4_Pos (4U) 6395 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 6396 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 6397 #define EXTI_IMR_MR5_Pos (5U) 6398 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 6399 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 6400 #define EXTI_IMR_MR6_Pos (6U) 6401 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 6402 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 6403 #define EXTI_IMR_MR7_Pos (7U) 6404 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 6405 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 6406 #define EXTI_IMR_MR8_Pos (8U) 6407 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 6408 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 6409 #define EXTI_IMR_MR9_Pos (9U) 6410 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 6411 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 6412 #define EXTI_IMR_MR10_Pos (10U) 6413 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 6414 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 6415 #define EXTI_IMR_MR11_Pos (11U) 6416 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 6417 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 6418 #define EXTI_IMR_MR12_Pos (12U) 6419 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 6420 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 6421 #define EXTI_IMR_MR13_Pos (13U) 6422 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 6423 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 6424 #define EXTI_IMR_MR14_Pos (14U) 6425 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 6426 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 6427 #define EXTI_IMR_MR15_Pos (15U) 6428 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 6429 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 6430 #define EXTI_IMR_MR16_Pos (16U) 6431 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 6432 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 6433 #define EXTI_IMR_MR17_Pos (17U) 6434 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 6435 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 6436 #define EXTI_IMR_MR19_Pos (19U) 6437 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 6438 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 6439 #define EXTI_IMR_MR20_Pos (20U) 6440 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 6441 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 6442 #define EXTI_IMR_MR22_Pos (22U) 6443 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 6444 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 6445 #define EXTI_IMR_MR23_Pos (23U) 6446 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 6447 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 6448 #define EXTI_IMR_MR25_Pos (25U) 6449 #define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ 6450 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ 6451 #define EXTI_IMR_MR30_Pos (30U) 6452 #define EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */ 6453 #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */ 6454 6455 /* References Defines */ 6456 #define EXTI_IMR_IM0 EXTI_IMR_MR0 6457 #define EXTI_IMR_IM1 EXTI_IMR_MR1 6458 #define EXTI_IMR_IM2 EXTI_IMR_MR2 6459 #define EXTI_IMR_IM3 EXTI_IMR_MR3 6460 #define EXTI_IMR_IM4 EXTI_IMR_MR4 6461 #define EXTI_IMR_IM5 EXTI_IMR_MR5 6462 #define EXTI_IMR_IM6 EXTI_IMR_MR6 6463 #define EXTI_IMR_IM7 EXTI_IMR_MR7 6464 #define EXTI_IMR_IM8 EXTI_IMR_MR8 6465 #define EXTI_IMR_IM9 EXTI_IMR_MR9 6466 #define EXTI_IMR_IM10 EXTI_IMR_MR10 6467 #define EXTI_IMR_IM11 EXTI_IMR_MR11 6468 #define EXTI_IMR_IM12 EXTI_IMR_MR12 6469 #define EXTI_IMR_IM13 EXTI_IMR_MR13 6470 #define EXTI_IMR_IM14 EXTI_IMR_MR14 6471 #define EXTI_IMR_IM15 EXTI_IMR_MR15 6472 #define EXTI_IMR_IM16 EXTI_IMR_MR16 6473 #define EXTI_IMR_IM17 EXTI_IMR_MR17 6474 #if defined(EXTI_IMR_MR18) 6475 #define EXTI_IMR_IM18 EXTI_IMR_MR18 6476 #endif 6477 #define EXTI_IMR_IM19 EXTI_IMR_MR19 6478 #define EXTI_IMR_IM20 EXTI_IMR_MR20 6479 #if defined(EXTI_IMR_MR21) 6480 #define EXTI_IMR_IM21 EXTI_IMR_MR21 6481 #endif 6482 #define EXTI_IMR_IM22 EXTI_IMR_MR22 6483 #define EXTI_IMR_IM23 EXTI_IMR_MR23 6484 #if defined(EXTI_IMR_MR24) 6485 #define EXTI_IMR_IM24 EXTI_IMR_MR24 6486 #endif 6487 #define EXTI_IMR_IM25 EXTI_IMR_MR25 6488 #if defined(EXTI_IMR_MR26) 6489 #define EXTI_IMR_IM26 EXTI_IMR_MR26 6490 #endif 6491 #if defined(EXTI_IMR_MR27) 6492 #define EXTI_IMR_IM27 EXTI_IMR_MR27 6493 #endif 6494 #if defined(EXTI_IMR_MR28) 6495 #define EXTI_IMR_IM28 EXTI_IMR_MR28 6496 #endif 6497 #if defined(EXTI_IMR_MR29) 6498 #define EXTI_IMR_IM29 EXTI_IMR_MR29 6499 #endif 6500 #if defined(EXTI_IMR_MR30) 6501 #define EXTI_IMR_IM30 EXTI_IMR_MR30 6502 #endif 6503 #if defined(EXTI_IMR_MR31) 6504 #define EXTI_IMR_IM31 EXTI_IMR_MR31 6505 #endif 6506 6507 #define EXTI_IMR_IM_Pos (0U) 6508 #define EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */ 6509 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 6510 6511 /******************* Bit definition for EXTI_EMR register *******************/ 6512 #define EXTI_EMR_MR0_Pos (0U) 6513 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 6514 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 6515 #define EXTI_EMR_MR1_Pos (1U) 6516 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 6517 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 6518 #define EXTI_EMR_MR2_Pos (2U) 6519 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 6520 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 6521 #define EXTI_EMR_MR3_Pos (3U) 6522 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 6523 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 6524 #define EXTI_EMR_MR4_Pos (4U) 6525 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 6526 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 6527 #define EXTI_EMR_MR5_Pos (5U) 6528 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 6529 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 6530 #define EXTI_EMR_MR6_Pos (6U) 6531 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 6532 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 6533 #define EXTI_EMR_MR7_Pos (7U) 6534 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 6535 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 6536 #define EXTI_EMR_MR8_Pos (8U) 6537 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 6538 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 6539 #define EXTI_EMR_MR9_Pos (9U) 6540 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 6541 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 6542 #define EXTI_EMR_MR10_Pos (10U) 6543 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 6544 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 6545 #define EXTI_EMR_MR11_Pos (11U) 6546 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 6547 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 6548 #define EXTI_EMR_MR12_Pos (12U) 6549 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 6550 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 6551 #define EXTI_EMR_MR13_Pos (13U) 6552 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 6553 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 6554 #define EXTI_EMR_MR14_Pos (14U) 6555 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 6556 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 6557 #define EXTI_EMR_MR15_Pos (15U) 6558 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 6559 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 6560 #define EXTI_EMR_MR16_Pos (16U) 6561 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 6562 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 6563 #define EXTI_EMR_MR17_Pos (17U) 6564 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 6565 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 6566 #define EXTI_EMR_MR19_Pos (19U) 6567 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 6568 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 6569 #define EXTI_EMR_MR20_Pos (20U) 6570 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 6571 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 6572 #define EXTI_EMR_MR22_Pos (22U) 6573 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 6574 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 6575 #define EXTI_EMR_MR23_Pos (23U) 6576 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 6577 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 6578 #define EXTI_EMR_MR25_Pos (25U) 6579 #define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ 6580 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ 6581 #define EXTI_EMR_MR30_Pos (30U) 6582 #define EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */ 6583 #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */ 6584 6585 /* References Defines */ 6586 #define EXTI_EMR_EM0 EXTI_EMR_MR0 6587 #define EXTI_EMR_EM1 EXTI_EMR_MR1 6588 #define EXTI_EMR_EM2 EXTI_EMR_MR2 6589 #define EXTI_EMR_EM3 EXTI_EMR_MR3 6590 #define EXTI_EMR_EM4 EXTI_EMR_MR4 6591 #define EXTI_EMR_EM5 EXTI_EMR_MR5 6592 #define EXTI_EMR_EM6 EXTI_EMR_MR6 6593 #define EXTI_EMR_EM7 EXTI_EMR_MR7 6594 #define EXTI_EMR_EM8 EXTI_EMR_MR8 6595 #define EXTI_EMR_EM9 EXTI_EMR_MR9 6596 #define EXTI_EMR_EM10 EXTI_EMR_MR10 6597 #define EXTI_EMR_EM11 EXTI_EMR_MR11 6598 #define EXTI_EMR_EM12 EXTI_EMR_MR12 6599 #define EXTI_EMR_EM13 EXTI_EMR_MR13 6600 #define EXTI_EMR_EM14 EXTI_EMR_MR14 6601 #define EXTI_EMR_EM15 EXTI_EMR_MR15 6602 #define EXTI_EMR_EM16 EXTI_EMR_MR16 6603 #define EXTI_EMR_EM17 EXTI_EMR_MR17 6604 #if defined(EXTI_EMR_MR18) 6605 #define EXTI_EMR_EM18 EXTI_EMR_MR18 6606 #endif 6607 #define EXTI_EMR_EM19 EXTI_EMR_MR19 6608 #define EXTI_EMR_EM20 EXTI_EMR_MR20 6609 #if defined(EXTI_EMR_MR21) 6610 #define EXTI_EMR_EM21 EXTI_EMR_MR21 6611 #endif 6612 #define EXTI_EMR_EM22 EXTI_EMR_MR22 6613 #define EXTI_EMR_EM23 EXTI_EMR_MR23 6614 #if defined(EXTI_EMR_MR24) 6615 #define EXTI_EMR_EM24 EXTI_EMR_MR24 6616 #endif 6617 #define EXTI_EMR_EM25 EXTI_EMR_MR25 6618 #if defined(EXTI_EMR_MR26) 6619 #define EXTI_EMR_EM26 EXTI_EMR_MR26 6620 #endif 6621 #if defined(EXTI_EMR_MR27) 6622 #define EXTI_EMR_EM27 EXTI_EMR_MR27 6623 #endif 6624 #if defined(EXTI_EMR_MR28) 6625 #define EXTI_EMR_EM28 EXTI_EMR_MR28 6626 #endif 6627 #if defined(EXTI_EMR_MR29) 6628 #define EXTI_EMR_EM29 EXTI_EMR_MR29 6629 #endif 6630 #if defined(EXTI_EMR_MR30) 6631 #define EXTI_EMR_EM30 EXTI_EMR_MR30 6632 #endif 6633 #if defined(EXTI_EMR_MR31) 6634 #define EXTI_EMR_EM31 EXTI_EMR_MR31 6635 #endif 6636 6637 /****************** Bit definition for EXTI_RTSR register *******************/ 6638 #define EXTI_RTSR_TR0_Pos (0U) 6639 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 6640 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 6641 #define EXTI_RTSR_TR1_Pos (1U) 6642 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 6643 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 6644 #define EXTI_RTSR_TR2_Pos (2U) 6645 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 6646 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 6647 #define EXTI_RTSR_TR3_Pos (3U) 6648 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 6649 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 6650 #define EXTI_RTSR_TR4_Pos (4U) 6651 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 6652 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 6653 #define EXTI_RTSR_TR5_Pos (5U) 6654 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 6655 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 6656 #define EXTI_RTSR_TR6_Pos (6U) 6657 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 6658 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 6659 #define EXTI_RTSR_TR7_Pos (7U) 6660 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 6661 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 6662 #define EXTI_RTSR_TR8_Pos (8U) 6663 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 6664 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 6665 #define EXTI_RTSR_TR9_Pos (9U) 6666 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 6667 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 6668 #define EXTI_RTSR_TR10_Pos (10U) 6669 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 6670 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 6671 #define EXTI_RTSR_TR11_Pos (11U) 6672 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 6673 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 6674 #define EXTI_RTSR_TR12_Pos (12U) 6675 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 6676 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 6677 #define EXTI_RTSR_TR13_Pos (13U) 6678 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 6679 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 6680 #define EXTI_RTSR_TR14_Pos (14U) 6681 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 6682 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 6683 #define EXTI_RTSR_TR15_Pos (15U) 6684 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 6685 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 6686 #define EXTI_RTSR_TR16_Pos (16U) 6687 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 6688 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 6689 #define EXTI_RTSR_TR17_Pos (17U) 6690 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 6691 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 6692 #define EXTI_RTSR_TR19_Pos (19U) 6693 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 6694 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 6695 #define EXTI_RTSR_TR20_Pos (20U) 6696 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 6697 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 6698 #define EXTI_RTSR_TR22_Pos (22U) 6699 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 6700 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 6701 #define EXTI_RTSR_TR30_Pos (30U) 6702 #define EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */ 6703 #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */ 6704 6705 /* References Defines */ 6706 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 6707 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 6708 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 6709 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 6710 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 6711 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 6712 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 6713 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 6714 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 6715 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 6716 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 6717 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 6718 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 6719 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 6720 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 6721 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 6722 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 6723 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 6724 #if defined(EXTI_RTSR_TR18) 6725 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 6726 #endif 6727 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 6728 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 6729 #if defined(EXTI_RTSR_TR21) 6730 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 6731 #endif 6732 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 6733 #if defined(EXTI_RTSR_TR23) 6734 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 6735 #endif 6736 #if defined(EXTI_RTSR_TR24) 6737 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24 6738 #endif 6739 #if defined(EXTI_RTSR_TR25) 6740 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25 6741 #endif 6742 #if defined(EXTI_RTSR_TR26) 6743 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26 6744 #endif 6745 #if defined(EXTI_RTSR_TR27) 6746 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27 6747 #endif 6748 #if defined(EXTI_RTSR_TR28) 6749 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28 6750 #endif 6751 #if defined(EXTI_RTSR_TR29) 6752 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29 6753 #endif 6754 #if defined(EXTI_RTSR_TR30) 6755 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30 6756 #endif 6757 #if defined(EXTI_RTSR_TR31) 6758 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31 6759 #endif 6760 6761 /****************** Bit definition for EXTI_FTSR register *******************/ 6762 #define EXTI_FTSR_TR0_Pos (0U) 6763 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 6764 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 6765 #define EXTI_FTSR_TR1_Pos (1U) 6766 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 6767 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 6768 #define EXTI_FTSR_TR2_Pos (2U) 6769 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 6770 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 6771 #define EXTI_FTSR_TR3_Pos (3U) 6772 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 6773 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 6774 #define EXTI_FTSR_TR4_Pos (4U) 6775 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 6776 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 6777 #define EXTI_FTSR_TR5_Pos (5U) 6778 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 6779 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 6780 #define EXTI_FTSR_TR6_Pos (6U) 6781 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 6782 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 6783 #define EXTI_FTSR_TR7_Pos (7U) 6784 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 6785 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 6786 #define EXTI_FTSR_TR8_Pos (8U) 6787 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 6788 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 6789 #define EXTI_FTSR_TR9_Pos (9U) 6790 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 6791 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 6792 #define EXTI_FTSR_TR10_Pos (10U) 6793 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 6794 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 6795 #define EXTI_FTSR_TR11_Pos (11U) 6796 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 6797 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 6798 #define EXTI_FTSR_TR12_Pos (12U) 6799 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 6800 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 6801 #define EXTI_FTSR_TR13_Pos (13U) 6802 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 6803 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 6804 #define EXTI_FTSR_TR14_Pos (14U) 6805 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 6806 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 6807 #define EXTI_FTSR_TR15_Pos (15U) 6808 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 6809 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 6810 #define EXTI_FTSR_TR16_Pos (16U) 6811 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 6812 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 6813 #define EXTI_FTSR_TR17_Pos (17U) 6814 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 6815 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 6816 #define EXTI_FTSR_TR19_Pos (19U) 6817 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 6818 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 6819 #define EXTI_FTSR_TR20_Pos (20U) 6820 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 6821 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 6822 #define EXTI_FTSR_TR22_Pos (22U) 6823 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 6824 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 6825 #define EXTI_FTSR_TR30_Pos (30U) 6826 #define EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */ 6827 #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */ 6828 6829 /* References Defines */ 6830 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 6831 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 6832 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 6833 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 6834 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 6835 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 6836 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 6837 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 6838 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 6839 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 6840 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 6841 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 6842 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 6843 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 6844 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 6845 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 6846 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 6847 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 6848 #if defined(EXTI_FTSR_TR18) 6849 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 6850 #endif 6851 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 6852 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 6853 #if defined(EXTI_FTSR_TR21) 6854 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 6855 #endif 6856 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 6857 #if defined(EXTI_FTSR_TR23) 6858 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 6859 #endif 6860 #if defined(EXTI_FTSR_TR24) 6861 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24 6862 #endif 6863 #if defined(EXTI_FTSR_TR25) 6864 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25 6865 #endif 6866 #if defined(EXTI_FTSR_TR26) 6867 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26 6868 #endif 6869 #if defined(EXTI_FTSR_TR27) 6870 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27 6871 #endif 6872 #if defined(EXTI_FTSR_TR28) 6873 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28 6874 #endif 6875 #if defined(EXTI_FTSR_TR29) 6876 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29 6877 #endif 6878 #if defined(EXTI_FTSR_TR30) 6879 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30 6880 #endif 6881 #if defined(EXTI_FTSR_TR31) 6882 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31 6883 #endif 6884 6885 /****************** Bit definition for EXTI_SWIER register ******************/ 6886 #define EXTI_SWIER_SWIER0_Pos (0U) 6887 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 6888 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 6889 #define EXTI_SWIER_SWIER1_Pos (1U) 6890 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 6891 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 6892 #define EXTI_SWIER_SWIER2_Pos (2U) 6893 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 6894 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 6895 #define EXTI_SWIER_SWIER3_Pos (3U) 6896 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 6897 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 6898 #define EXTI_SWIER_SWIER4_Pos (4U) 6899 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 6900 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 6901 #define EXTI_SWIER_SWIER5_Pos (5U) 6902 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 6903 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 6904 #define EXTI_SWIER_SWIER6_Pos (6U) 6905 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 6906 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 6907 #define EXTI_SWIER_SWIER7_Pos (7U) 6908 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 6909 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 6910 #define EXTI_SWIER_SWIER8_Pos (8U) 6911 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 6912 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 6913 #define EXTI_SWIER_SWIER9_Pos (9U) 6914 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 6915 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 6916 #define EXTI_SWIER_SWIER10_Pos (10U) 6917 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 6918 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 6919 #define EXTI_SWIER_SWIER11_Pos (11U) 6920 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 6921 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 6922 #define EXTI_SWIER_SWIER12_Pos (12U) 6923 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 6924 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 6925 #define EXTI_SWIER_SWIER13_Pos (13U) 6926 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 6927 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 6928 #define EXTI_SWIER_SWIER14_Pos (14U) 6929 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 6930 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 6931 #define EXTI_SWIER_SWIER15_Pos (15U) 6932 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 6933 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 6934 #define EXTI_SWIER_SWIER16_Pos (16U) 6935 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 6936 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 6937 #define EXTI_SWIER_SWIER17_Pos (17U) 6938 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 6939 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 6940 #define EXTI_SWIER_SWIER19_Pos (19U) 6941 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 6942 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 6943 #define EXTI_SWIER_SWIER20_Pos (20U) 6944 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 6945 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 6946 #define EXTI_SWIER_SWIER22_Pos (22U) 6947 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 6948 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 6949 #define EXTI_SWIER_SWIER30_Pos (30U) 6950 #define EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */ 6951 #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */ 6952 6953 /* References Defines */ 6954 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 6955 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 6956 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 6957 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 6958 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 6959 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 6960 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 6961 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 6962 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 6963 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 6964 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 6965 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 6966 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 6967 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 6968 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 6969 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 6970 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 6971 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 6972 #if defined(EXTI_SWIER_SWIER18) 6973 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 6974 #endif 6975 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 6976 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 6977 #if defined(EXTI_SWIER_SWIER21) 6978 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 6979 #endif 6980 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 6981 #if defined(EXTI_SWIER_SWIER23) 6982 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 6983 #endif 6984 #if defined(EXTI_SWIER_SWIER24) 6985 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24 6986 #endif 6987 #if defined(EXTI_SWIER_SWIER25) 6988 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25 6989 #endif 6990 #if defined(EXTI_SWIER_SWIER26) 6991 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26 6992 #endif 6993 #if defined(EXTI_SWIER_SWIER27) 6994 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27 6995 #endif 6996 #if defined(EXTI_SWIER_SWIER28) 6997 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28 6998 #endif 6999 #if defined(EXTI_SWIER_SWIER29) 7000 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29 7001 #endif 7002 #if defined(EXTI_SWIER_SWIER30) 7003 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30 7004 #endif 7005 #if defined(EXTI_SWIER_SWIER31) 7006 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 7007 #endif 7008 7009 /******************* Bit definition for EXTI_PR register ********************/ 7010 #define EXTI_PR_PR0_Pos (0U) 7011 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 7012 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 7013 #define EXTI_PR_PR1_Pos (1U) 7014 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 7015 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 7016 #define EXTI_PR_PR2_Pos (2U) 7017 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 7018 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 7019 #define EXTI_PR_PR3_Pos (3U) 7020 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 7021 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 7022 #define EXTI_PR_PR4_Pos (4U) 7023 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 7024 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 7025 #define EXTI_PR_PR5_Pos (5U) 7026 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 7027 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 7028 #define EXTI_PR_PR6_Pos (6U) 7029 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 7030 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 7031 #define EXTI_PR_PR7_Pos (7U) 7032 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 7033 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 7034 #define EXTI_PR_PR8_Pos (8U) 7035 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 7036 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 7037 #define EXTI_PR_PR9_Pos (9U) 7038 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 7039 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 7040 #define EXTI_PR_PR10_Pos (10U) 7041 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 7042 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 7043 #define EXTI_PR_PR11_Pos (11U) 7044 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 7045 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 7046 #define EXTI_PR_PR12_Pos (12U) 7047 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 7048 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 7049 #define EXTI_PR_PR13_Pos (13U) 7050 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 7051 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 7052 #define EXTI_PR_PR14_Pos (14U) 7053 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 7054 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 7055 #define EXTI_PR_PR15_Pos (15U) 7056 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 7057 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 7058 #define EXTI_PR_PR16_Pos (16U) 7059 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 7060 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 7061 #define EXTI_PR_PR17_Pos (17U) 7062 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 7063 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 7064 #define EXTI_PR_PR19_Pos (19U) 7065 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 7066 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 7067 #define EXTI_PR_PR20_Pos (20U) 7068 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 7069 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 7070 #define EXTI_PR_PR22_Pos (22U) 7071 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 7072 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 7073 #define EXTI_PR_PR30_Pos (30U) 7074 #define EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos) /*!< 0x40000000 */ 7075 #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */ 7076 7077 /* References Defines */ 7078 #define EXTI_PR_PIF0 EXTI_PR_PR0 7079 #define EXTI_PR_PIF1 EXTI_PR_PR1 7080 #define EXTI_PR_PIF2 EXTI_PR_PR2 7081 #define EXTI_PR_PIF3 EXTI_PR_PR3 7082 #define EXTI_PR_PIF4 EXTI_PR_PR4 7083 #define EXTI_PR_PIF5 EXTI_PR_PR5 7084 #define EXTI_PR_PIF6 EXTI_PR_PR6 7085 #define EXTI_PR_PIF6 EXTI_PR_PR6 7086 #define EXTI_PR_PIF7 EXTI_PR_PR7 7087 #define EXTI_PR_PIF8 EXTI_PR_PR8 7088 #define EXTI_PR_PIF9 EXTI_PR_PR9 7089 #define EXTI_PR_PIF10 EXTI_PR_PR10 7090 #define EXTI_PR_PIF11 EXTI_PR_PR11 7091 #define EXTI_PR_PIF12 EXTI_PR_PR12 7092 #define EXTI_PR_PIF13 EXTI_PR_PR13 7093 #define EXTI_PR_PIF14 EXTI_PR_PR14 7094 #define EXTI_PR_PIF15 EXTI_PR_PR15 7095 #define EXTI_PR_PIF16 EXTI_PR_PR16 7096 #define EXTI_PR_PIF17 EXTI_PR_PR17 7097 #if defined(EXTI_PR_PR18) 7098 #define EXTI_PR_PIF18 EXTI_PR_PR18 7099 #endif 7100 #define EXTI_PR_PIF19 EXTI_PR_PR19 7101 #define EXTI_PR_PIF20 EXTI_PR_PR20 7102 #if defined(EXTI_PR_PR21) 7103 #define EXTI_PR_PIF21 EXTI_PR_PR21 7104 #endif 7105 #define EXTI_PR_PIF22 EXTI_PR_PR22 7106 #if defined(EXTI_PR_PR23) 7107 #define EXTI_PR_PIF23 EXTI_PR_PR23 7108 #endif 7109 #if defined(EXTI_PR_PR24) 7110 #define EXTI_PR_PIF24 EXTI_PR_PR24 7111 #endif 7112 #if defined(EXTI_PR_PR25) 7113 #define EXTI_PR_PIF25 EXTI_PR_PR25 7114 #endif 7115 #if defined(EXTI_PR_PR26) 7116 #define EXTI_PR_PIF26 EXTI_PR_PR26 7117 #endif 7118 #if defined(EXTI_PR_PR27) 7119 #define EXTI_PR_PIF27 EXTI_PR_PR27 7120 #endif 7121 #if defined(EXTI_PR_PR28) 7122 #define EXTI_PR_PIF28 EXTI_PR_PR28 7123 #endif 7124 #if defined(EXTI_PR_PR29) 7125 #define EXTI_PR_PIF29 EXTI_PR_PR29 7126 #endif 7127 #if defined(EXTI_PR_PR30) 7128 #define EXTI_PR_PIF30 EXTI_PR_PR30 7129 #endif 7130 #if defined(EXTI_PR_PR31) 7131 #define EXTI_PR_PIF31 EXTI_PR_PR31 7132 #endif 7133 7134 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */ 7135 7136 /******************* Bit definition for EXTI_IMR2 register ******************/ 7137 #define EXTI_IMR2_MR32_Pos (0U) 7138 #define EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */ 7139 #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */ 7140 7141 /* References Defines */ 7142 7143 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32 7144 #if defined(EXTI_IMR2_MR33) 7145 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33 7146 #endif 7147 #if defined(EXTI_IMR2_MR34) 7148 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34 7149 #endif 7150 #if defined(EXTI_IMR2_MR35) 7151 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35 7152 #endif 7153 7154 #if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35) 7155 #define EXTI_IMR2_IM_Pos (0U) 7156 #define EXTI_IMR2_IM_Msk (0xFUL << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ 7157 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 7158 #elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35) 7159 #define EXTI_IMR2_IM_Pos (0U) 7160 #define EXTI_IMR2_IM_Msk (0xDUL << EXTI_IMR2_IM_Pos) /*!< 0x0000000D */ 7161 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 7162 #else 7163 #define EXTI_IMR2_IM_Pos (0U) 7164 #define EXTI_IMR2_IM_Msk (0x1UL << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */ 7165 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk 7166 #endif 7167 7168 /******************* Bit definition for EXTI_EMR2 ****************************/ 7169 #define EXTI_EMR2_MR32_Pos (0U) 7170 #define EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */ 7171 #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */ 7172 7173 /* References Defines */ 7174 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32 7175 #if defined(EXTI_EMR2_MR33) 7176 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33 7177 #endif 7178 #if defined(EXTI_EMR2_MR34) 7179 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34 7180 #endif 7181 #if defined(EXTI_EMR2_MR35) 7182 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35 7183 #endif 7184 7185 #if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35) 7186 #define EXTI_EMR2_EM_Pos (0U) 7187 #define EXTI_EMR2_EM_Msk (0xFUL << EXTI_EMR2_EM_Pos) /*!< 0x0000000F */ 7188 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 7189 #elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35) 7190 #define EXTI_EMR2_EM_Pos (0U) 7191 #define EXTI_EMR2_EM_Msk (0xDUL << EXTI_EMR2_EM_Pos) /*!< 0x0000000D */ 7192 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 7193 #else 7194 #define EXTI_EMR2_EM_Pos (0U) 7195 #define EXTI_EMR2_EM_Msk (0x1UL << EXTI_EMR2_EM_Pos) /*!< 0x00000001 */ 7196 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk 7197 #endif 7198 7199 /****************** Bit definition for EXTI_RTSR2 register ********************/ 7200 #define EXTI_RTSR2_TR32_Pos (0U) 7201 #define EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ 7202 #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */ 7203 7204 /* References Defines */ 7205 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32 7206 #if defined(EXTI_RTSR2_TR33) 7207 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33 7208 #endif 7209 #if defined(EXTI_RTSR2_TR34) 7210 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34 7211 #endif 7212 #if defined(EXTI_RTSR2_TR35) 7213 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35 7214 #endif 7215 7216 /****************** Bit definition for EXTI_FTSR2 register ******************/ 7217 #define EXTI_FTSR2_TR32_Pos (0U) 7218 #define EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */ 7219 #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */ 7220 7221 /* References Defines */ 7222 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32 7223 #if defined(EXTI_FTSR2_TR33) 7224 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33 7225 #endif 7226 #if defined(EXTI_FTSR2_TR34) 7227 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34 7228 #endif 7229 #if defined(EXTI_FTSR2_TR35) 7230 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35 7231 #endif 7232 7233 /****************** Bit definition for EXTI_SWIER2 register *****************/ 7234 #define EXTI_SWIER2_SWIER32_Pos (0U) 7235 #define EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */ 7236 #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */ 7237 7238 /* References Defines */ 7239 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32 7240 #if defined(EXTI_SWIER2_SWIER33) 7241 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33 7242 #endif 7243 #if defined(EXTI_SWIER2_SWIER34) 7244 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34 7245 #endif 7246 #if defined(EXTI_SWIER2_SWIER35) 7247 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35 7248 #endif 7249 7250 /******************* Bit definition for EXTI_PR2 register *******************/ 7251 #define EXTI_PR2_PR32_Pos (0U) 7252 #define EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */ 7253 #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */ 7254 7255 /* References Defines */ 7256 #define EXTI_PR2_PIF32 EXTI_PR2_PR32 7257 #if defined(EXTI_PR2_PR33) 7258 #define EXTI_PR2_PIF33 EXTI_PR2_PR33 7259 #endif 7260 #if defined(EXTI_PR2_PR34) 7261 #define EXTI_PR2_PIF34 EXTI_PR2_PR34 7262 #endif 7263 #if defined(EXTI_PR2_PR35) 7264 #define EXTI_PR2_PIF35 EXTI_PR2_PR35 7265 #endif 7266 7267 7268 /******************************************************************************/ 7269 /* */ 7270 /* FLASH */ 7271 /* */ 7272 /******************************************************************************/ 7273 /******************* Bit definition for FLASH_ACR register ******************/ 7274 #define FLASH_ACR_LATENCY_Pos (0U) 7275 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 7276 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ 7277 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 7278 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 7279 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 7280 7281 #define FLASH_ACR_HLFCYA_Pos (3U) 7282 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 7283 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 7284 #define FLASH_ACR_PRFTBE_Pos (4U) 7285 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 7286 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 7287 #define FLASH_ACR_PRFTBS_Pos (5U) 7288 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 7289 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 7290 7291 /****************** Bit definition for FLASH_KEYR register ******************/ 7292 #define FLASH_KEYR_FKEYR_Pos (0U) 7293 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 7294 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 7295 7296 #define RDP_KEY_Pos (0U) 7297 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ 7298 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 7299 #define FLASH_KEY1_Pos (0U) 7300 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 7301 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 7302 #define FLASH_KEY2_Pos (0U) 7303 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 7304 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 7305 7306 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 7307 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 7308 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 7309 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 7310 7311 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 7312 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 7313 7314 /****************** Bit definition for FLASH_SR register *******************/ 7315 #define FLASH_SR_BSY_Pos (0U) 7316 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 7317 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 7318 #define FLASH_SR_PGERR_Pos (2U) 7319 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 7320 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 7321 #define FLASH_SR_WRPERR_Pos (4U) 7322 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 7323 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write Protection Error */ 7324 #define FLASH_SR_EOP_Pos (5U) 7325 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 7326 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 7327 7328 /******************* Bit definition for FLASH_CR register *******************/ 7329 #define FLASH_CR_PG_Pos (0U) 7330 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 7331 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 7332 #define FLASH_CR_PER_Pos (1U) 7333 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 7334 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 7335 #define FLASH_CR_MER_Pos (2U) 7336 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 7337 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 7338 #define FLASH_CR_OPTPG_Pos (4U) 7339 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 7340 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 7341 #define FLASH_CR_OPTER_Pos (5U) 7342 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 7343 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 7344 #define FLASH_CR_STRT_Pos (6U) 7345 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 7346 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 7347 #define FLASH_CR_LOCK_Pos (7U) 7348 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 7349 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 7350 #define FLASH_CR_OPTWRE_Pos (9U) 7351 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 7352 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 7353 #define FLASH_CR_ERRIE_Pos (10U) 7354 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 7355 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 7356 #define FLASH_CR_EOPIE_Pos (12U) 7357 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 7358 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 7359 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 7360 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 7361 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< OptionBytes Loader Launch */ 7362 7363 /******************* Bit definition for FLASH_AR register *******************/ 7364 #define FLASH_AR_FAR_Pos (0U) 7365 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 7366 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 7367 7368 /****************** Bit definition for FLASH_OBR register *******************/ 7369 #define FLASH_OBR_OPTERR_Pos (0U) 7370 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 7371 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 7372 #define FLASH_OBR_RDPRT_Pos (1U) 7373 #define FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ 7374 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 7375 #define FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 7376 #define FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000006 */ 7377 7378 #define FLASH_OBR_USER_Pos (8U) 7379 #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ 7380 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 7381 #define FLASH_OBR_IWDG_SW_Pos (8U) 7382 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 7383 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 7384 #define FLASH_OBR_nRST_STOP_Pos (9U) 7385 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 7386 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 7387 #define FLASH_OBR_nRST_STDBY_Pos (10U) 7388 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 7389 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 7390 #define FLASH_OBR_nBOOT1_Pos (12U) 7391 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 7392 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 7393 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 7394 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 7395 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA_MONITOR */ 7396 #define FLASH_OBR_SRAM_PE_Pos (14U) 7397 #define FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos) /*!< 0x00004000 */ 7398 #define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk /*!< SRAM_PE */ 7399 #define FLASH_OBR_DATA0_Pos (16U) 7400 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 7401 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 7402 #define FLASH_OBR_DATA1_Pos (24U) 7403 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 7404 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 7405 7406 /* Legacy defines */ 7407 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW 7408 7409 /****************** Bit definition for FLASH_WRPR register ******************/ 7410 #define FLASH_WRPR_WRP_Pos (0U) 7411 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 7412 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 7413 7414 /*----------------------------------------------------------------------------*/ 7415 7416 /****************** Bit definition for OB_RDP register **********************/ 7417 #define OB_RDP_RDP_Pos (0U) 7418 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 7419 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 7420 #define OB_RDP_nRDP_Pos (8U) 7421 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 7422 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 7423 7424 /****************** Bit definition for OB_USER register *********************/ 7425 #define OB_USER_USER_Pos (16U) 7426 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 7427 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 7428 #define OB_USER_nUSER_Pos (24U) 7429 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 7430 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 7431 7432 /****************** Bit definition for FLASH_WRP0 register ******************/ 7433 #define OB_WRP0_WRP0_Pos (0U) 7434 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 7435 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 7436 #define OB_WRP0_nWRP0_Pos (8U) 7437 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 7438 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 7439 7440 /****************** Bit definition for FLASH_WRP1 register ******************/ 7441 #define OB_WRP1_WRP1_Pos (16U) 7442 #define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 7443 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 7444 #define OB_WRP1_nWRP1_Pos (24U) 7445 #define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 7446 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 7447 7448 7449 /******************************************************************************/ 7450 /* */ 7451 /* General Purpose I/O (GPIO) */ 7452 /* */ 7453 /******************************************************************************/ 7454 /******************* Bit definition for GPIO_MODER register *****************/ 7455 #define GPIO_MODER_MODER0_Pos (0U) 7456 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 7457 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 7458 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 7459 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 7460 #define GPIO_MODER_MODER1_Pos (2U) 7461 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 7462 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 7463 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 7464 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 7465 #define GPIO_MODER_MODER2_Pos (4U) 7466 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 7467 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 7468 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 7469 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 7470 #define GPIO_MODER_MODER3_Pos (6U) 7471 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 7472 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 7473 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 7474 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 7475 #define GPIO_MODER_MODER4_Pos (8U) 7476 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 7477 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 7478 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 7479 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 7480 #define GPIO_MODER_MODER5_Pos (10U) 7481 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 7482 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 7483 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 7484 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 7485 #define GPIO_MODER_MODER6_Pos (12U) 7486 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 7487 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 7488 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 7489 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 7490 #define GPIO_MODER_MODER7_Pos (14U) 7491 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 7492 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 7493 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 7494 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 7495 #define GPIO_MODER_MODER8_Pos (16U) 7496 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 7497 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 7498 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 7499 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 7500 #define GPIO_MODER_MODER9_Pos (18U) 7501 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 7502 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 7503 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 7504 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 7505 #define GPIO_MODER_MODER10_Pos (20U) 7506 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 7507 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 7508 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 7509 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 7510 #define GPIO_MODER_MODER11_Pos (22U) 7511 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 7512 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 7513 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 7514 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 7515 #define GPIO_MODER_MODER12_Pos (24U) 7516 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 7517 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 7518 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 7519 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 7520 #define GPIO_MODER_MODER13_Pos (26U) 7521 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 7522 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 7523 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 7524 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 7525 #define GPIO_MODER_MODER14_Pos (28U) 7526 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 7527 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 7528 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 7529 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 7530 #define GPIO_MODER_MODER15_Pos (30U) 7531 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 7532 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 7533 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 7534 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 7535 7536 /****************** Bit definition for GPIO_OTYPER register *****************/ 7537 #define GPIO_OTYPER_OT_0 (0x00000001U) 7538 #define GPIO_OTYPER_OT_1 (0x00000002U) 7539 #define GPIO_OTYPER_OT_2 (0x00000004U) 7540 #define GPIO_OTYPER_OT_3 (0x00000008U) 7541 #define GPIO_OTYPER_OT_4 (0x00000010U) 7542 #define GPIO_OTYPER_OT_5 (0x00000020U) 7543 #define GPIO_OTYPER_OT_6 (0x00000040U) 7544 #define GPIO_OTYPER_OT_7 (0x00000080U) 7545 #define GPIO_OTYPER_OT_8 (0x00000100U) 7546 #define GPIO_OTYPER_OT_9 (0x00000200U) 7547 #define GPIO_OTYPER_OT_10 (0x00000400U) 7548 #define GPIO_OTYPER_OT_11 (0x00000800U) 7549 #define GPIO_OTYPER_OT_12 (0x00001000U) 7550 #define GPIO_OTYPER_OT_13 (0x00002000U) 7551 #define GPIO_OTYPER_OT_14 (0x00004000U) 7552 #define GPIO_OTYPER_OT_15 (0x00008000U) 7553 7554 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 7555 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 7556 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 7557 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 7558 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 7559 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 7560 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 7561 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 7562 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 7563 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 7564 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 7565 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 7566 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 7567 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 7568 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 7569 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 7570 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 7571 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 7572 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 7573 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 7574 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 7575 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 7576 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 7577 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 7578 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 7579 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 7580 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 7581 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 7582 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 7583 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 7584 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 7585 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 7586 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 7587 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 7588 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 7589 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 7590 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 7591 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 7592 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 7593 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 7594 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 7595 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 7596 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 7597 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 7598 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 7599 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 7600 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 7601 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 7602 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 7603 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 7604 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 7605 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 7606 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 7607 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 7608 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 7609 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 7610 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 7611 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 7612 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 7613 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 7614 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 7615 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 7616 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 7617 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 7618 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 7619 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 7620 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 7621 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 7622 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 7623 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 7624 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 7625 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 7626 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 7627 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 7628 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 7629 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 7630 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 7631 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 7632 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 7633 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 7634 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 7635 7636 /******************* Bit definition for GPIO_PUPDR register ******************/ 7637 #define GPIO_PUPDR_PUPDR0_Pos (0U) 7638 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 7639 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 7640 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 7641 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 7642 #define GPIO_PUPDR_PUPDR1_Pos (2U) 7643 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 7644 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 7645 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 7646 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 7647 #define GPIO_PUPDR_PUPDR2_Pos (4U) 7648 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 7649 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 7650 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 7651 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 7652 #define GPIO_PUPDR_PUPDR3_Pos (6U) 7653 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 7654 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 7655 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 7656 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 7657 #define GPIO_PUPDR_PUPDR4_Pos (8U) 7658 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 7659 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 7660 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 7661 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 7662 #define GPIO_PUPDR_PUPDR5_Pos (10U) 7663 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 7664 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 7665 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 7666 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 7667 #define GPIO_PUPDR_PUPDR6_Pos (12U) 7668 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 7669 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 7670 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 7671 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 7672 #define GPIO_PUPDR_PUPDR7_Pos (14U) 7673 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 7674 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 7675 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 7676 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 7677 #define GPIO_PUPDR_PUPDR8_Pos (16U) 7678 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 7679 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 7680 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 7681 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 7682 #define GPIO_PUPDR_PUPDR9_Pos (18U) 7683 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 7684 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 7685 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 7686 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 7687 #define GPIO_PUPDR_PUPDR10_Pos (20U) 7688 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 7689 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 7690 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 7691 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 7692 #define GPIO_PUPDR_PUPDR11_Pos (22U) 7693 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 7694 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 7695 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 7696 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 7697 #define GPIO_PUPDR_PUPDR12_Pos (24U) 7698 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 7699 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 7700 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 7701 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 7702 #define GPIO_PUPDR_PUPDR13_Pos (26U) 7703 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 7704 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 7705 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 7706 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 7707 #define GPIO_PUPDR_PUPDR14_Pos (28U) 7708 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 7709 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 7710 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 7711 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 7712 #define GPIO_PUPDR_PUPDR15_Pos (30U) 7713 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 7714 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 7715 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 7716 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 7717 7718 /******************* Bit definition for GPIO_IDR register *******************/ 7719 #define GPIO_IDR_0 (0x00000001U) 7720 #define GPIO_IDR_1 (0x00000002U) 7721 #define GPIO_IDR_2 (0x00000004U) 7722 #define GPIO_IDR_3 (0x00000008U) 7723 #define GPIO_IDR_4 (0x00000010U) 7724 #define GPIO_IDR_5 (0x00000020U) 7725 #define GPIO_IDR_6 (0x00000040U) 7726 #define GPIO_IDR_7 (0x00000080U) 7727 #define GPIO_IDR_8 (0x00000100U) 7728 #define GPIO_IDR_9 (0x00000200U) 7729 #define GPIO_IDR_10 (0x00000400U) 7730 #define GPIO_IDR_11 (0x00000800U) 7731 #define GPIO_IDR_12 (0x00001000U) 7732 #define GPIO_IDR_13 (0x00002000U) 7733 #define GPIO_IDR_14 (0x00004000U) 7734 #define GPIO_IDR_15 (0x00008000U) 7735 7736 /****************** Bit definition for GPIO_ODR register ********************/ 7737 #define GPIO_ODR_0 (0x00000001U) 7738 #define GPIO_ODR_1 (0x00000002U) 7739 #define GPIO_ODR_2 (0x00000004U) 7740 #define GPIO_ODR_3 (0x00000008U) 7741 #define GPIO_ODR_4 (0x00000010U) 7742 #define GPIO_ODR_5 (0x00000020U) 7743 #define GPIO_ODR_6 (0x00000040U) 7744 #define GPIO_ODR_7 (0x00000080U) 7745 #define GPIO_ODR_8 (0x00000100U) 7746 #define GPIO_ODR_9 (0x00000200U) 7747 #define GPIO_ODR_10 (0x00000400U) 7748 #define GPIO_ODR_11 (0x00000800U) 7749 #define GPIO_ODR_12 (0x00001000U) 7750 #define GPIO_ODR_13 (0x00002000U) 7751 #define GPIO_ODR_14 (0x00004000U) 7752 #define GPIO_ODR_15 (0x00008000U) 7753 7754 /****************** Bit definition for GPIO_BSRR register ********************/ 7755 #define GPIO_BSRR_BS_0 (0x00000001U) 7756 #define GPIO_BSRR_BS_1 (0x00000002U) 7757 #define GPIO_BSRR_BS_2 (0x00000004U) 7758 #define GPIO_BSRR_BS_3 (0x00000008U) 7759 #define GPIO_BSRR_BS_4 (0x00000010U) 7760 #define GPIO_BSRR_BS_5 (0x00000020U) 7761 #define GPIO_BSRR_BS_6 (0x00000040U) 7762 #define GPIO_BSRR_BS_7 (0x00000080U) 7763 #define GPIO_BSRR_BS_8 (0x00000100U) 7764 #define GPIO_BSRR_BS_9 (0x00000200U) 7765 #define GPIO_BSRR_BS_10 (0x00000400U) 7766 #define GPIO_BSRR_BS_11 (0x00000800U) 7767 #define GPIO_BSRR_BS_12 (0x00001000U) 7768 #define GPIO_BSRR_BS_13 (0x00002000U) 7769 #define GPIO_BSRR_BS_14 (0x00004000U) 7770 #define GPIO_BSRR_BS_15 (0x00008000U) 7771 #define GPIO_BSRR_BR_0 (0x00010000U) 7772 #define GPIO_BSRR_BR_1 (0x00020000U) 7773 #define GPIO_BSRR_BR_2 (0x00040000U) 7774 #define GPIO_BSRR_BR_3 (0x00080000U) 7775 #define GPIO_BSRR_BR_4 (0x00100000U) 7776 #define GPIO_BSRR_BR_5 (0x00200000U) 7777 #define GPIO_BSRR_BR_6 (0x00400000U) 7778 #define GPIO_BSRR_BR_7 (0x00800000U) 7779 #define GPIO_BSRR_BR_8 (0x01000000U) 7780 #define GPIO_BSRR_BR_9 (0x02000000U) 7781 #define GPIO_BSRR_BR_10 (0x04000000U) 7782 #define GPIO_BSRR_BR_11 (0x08000000U) 7783 #define GPIO_BSRR_BR_12 (0x10000000U) 7784 #define GPIO_BSRR_BR_13 (0x20000000U) 7785 #define GPIO_BSRR_BR_14 (0x40000000U) 7786 #define GPIO_BSRR_BR_15 (0x80000000U) 7787 7788 /****************** Bit definition for GPIO_LCKR register ********************/ 7789 #define GPIO_LCKR_LCK0_Pos (0U) 7790 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 7791 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 7792 #define GPIO_LCKR_LCK1_Pos (1U) 7793 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 7794 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 7795 #define GPIO_LCKR_LCK2_Pos (2U) 7796 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 7797 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 7798 #define GPIO_LCKR_LCK3_Pos (3U) 7799 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 7800 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 7801 #define GPIO_LCKR_LCK4_Pos (4U) 7802 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 7803 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 7804 #define GPIO_LCKR_LCK5_Pos (5U) 7805 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 7806 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 7807 #define GPIO_LCKR_LCK6_Pos (6U) 7808 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 7809 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 7810 #define GPIO_LCKR_LCK7_Pos (7U) 7811 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 7812 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 7813 #define GPIO_LCKR_LCK8_Pos (8U) 7814 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 7815 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 7816 #define GPIO_LCKR_LCK9_Pos (9U) 7817 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 7818 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 7819 #define GPIO_LCKR_LCK10_Pos (10U) 7820 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 7821 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 7822 #define GPIO_LCKR_LCK11_Pos (11U) 7823 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 7824 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 7825 #define GPIO_LCKR_LCK12_Pos (12U) 7826 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 7827 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 7828 #define GPIO_LCKR_LCK13_Pos (13U) 7829 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 7830 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 7831 #define GPIO_LCKR_LCK14_Pos (14U) 7832 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 7833 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 7834 #define GPIO_LCKR_LCK15_Pos (15U) 7835 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 7836 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 7837 #define GPIO_LCKR_LCKK_Pos (16U) 7838 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 7839 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 7840 7841 /****************** Bit definition for GPIO_AFRL register ********************/ 7842 #define GPIO_AFRL_AFRL0_Pos (0U) 7843 #define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ 7844 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk 7845 #define GPIO_AFRL_AFRL1_Pos (4U) 7846 #define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ 7847 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk 7848 #define GPIO_AFRL_AFRL2_Pos (8U) 7849 #define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ 7850 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk 7851 #define GPIO_AFRL_AFRL3_Pos (12U) 7852 #define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ 7853 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk 7854 #define GPIO_AFRL_AFRL4_Pos (16U) 7855 #define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ 7856 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk 7857 #define GPIO_AFRL_AFRL5_Pos (20U) 7858 #define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ 7859 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk 7860 #define GPIO_AFRL_AFRL6_Pos (24U) 7861 #define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ 7862 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk 7863 #define GPIO_AFRL_AFRL7_Pos (28U) 7864 #define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ 7865 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk 7866 7867 /****************** Bit definition for GPIO_AFRH register ********************/ 7868 #define GPIO_AFRH_AFRH0_Pos (0U) 7869 #define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ 7870 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk 7871 #define GPIO_AFRH_AFRH1_Pos (4U) 7872 #define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ 7873 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk 7874 #define GPIO_AFRH_AFRH2_Pos (8U) 7875 #define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ 7876 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk 7877 #define GPIO_AFRH_AFRH3_Pos (12U) 7878 #define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ 7879 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk 7880 #define GPIO_AFRH_AFRH4_Pos (16U) 7881 #define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ 7882 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk 7883 #define GPIO_AFRH_AFRH5_Pos (20U) 7884 #define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ 7885 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk 7886 #define GPIO_AFRH_AFRH6_Pos (24U) 7887 #define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ 7888 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk 7889 #define GPIO_AFRH_AFRH7_Pos (28U) 7890 #define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ 7891 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk 7892 7893 /****************** Bit definition for GPIO_BRR register *********************/ 7894 #define GPIO_BRR_BR_0 (0x00000001U) 7895 #define GPIO_BRR_BR_1 (0x00000002U) 7896 #define GPIO_BRR_BR_2 (0x00000004U) 7897 #define GPIO_BRR_BR_3 (0x00000008U) 7898 #define GPIO_BRR_BR_4 (0x00000010U) 7899 #define GPIO_BRR_BR_5 (0x00000020U) 7900 #define GPIO_BRR_BR_6 (0x00000040U) 7901 #define GPIO_BRR_BR_7 (0x00000080U) 7902 #define GPIO_BRR_BR_8 (0x00000100U) 7903 #define GPIO_BRR_BR_9 (0x00000200U) 7904 #define GPIO_BRR_BR_10 (0x00000400U) 7905 #define GPIO_BRR_BR_11 (0x00000800U) 7906 #define GPIO_BRR_BR_12 (0x00001000U) 7907 #define GPIO_BRR_BR_13 (0x00002000U) 7908 #define GPIO_BRR_BR_14 (0x00004000U) 7909 #define GPIO_BRR_BR_15 (0x00008000U) 7910 7911 /******************************************************************************/ 7912 /* */ 7913 /* Inter-integrated Circuit Interface (I2C) */ 7914 /* */ 7915 /******************************************************************************/ 7916 /******************* Bit definition for I2C_CR1 register *******************/ 7917 #define I2C_CR1_PE_Pos (0U) 7918 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 7919 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 7920 #define I2C_CR1_TXIE_Pos (1U) 7921 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 7922 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 7923 #define I2C_CR1_RXIE_Pos (2U) 7924 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 7925 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 7926 #define I2C_CR1_ADDRIE_Pos (3U) 7927 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 7928 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 7929 #define I2C_CR1_NACKIE_Pos (4U) 7930 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 7931 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 7932 #define I2C_CR1_STOPIE_Pos (5U) 7933 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 7934 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 7935 #define I2C_CR1_TCIE_Pos (6U) 7936 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 7937 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 7938 #define I2C_CR1_ERRIE_Pos (7U) 7939 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 7940 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 7941 #define I2C_CR1_DNF_Pos (8U) 7942 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 7943 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 7944 #define I2C_CR1_ANFOFF_Pos (12U) 7945 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 7946 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 7947 #define I2C_CR1_SWRST_Pos (13U) 7948 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 7949 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 7950 #define I2C_CR1_TXDMAEN_Pos (14U) 7951 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 7952 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 7953 #define I2C_CR1_RXDMAEN_Pos (15U) 7954 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 7955 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 7956 #define I2C_CR1_SBC_Pos (16U) 7957 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 7958 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 7959 #define I2C_CR1_NOSTRETCH_Pos (17U) 7960 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 7961 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 7962 #define I2C_CR1_WUPEN_Pos (18U) 7963 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 7964 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 7965 #define I2C_CR1_GCEN_Pos (19U) 7966 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 7967 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 7968 #define I2C_CR1_SMBHEN_Pos (20U) 7969 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 7970 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 7971 #define I2C_CR1_SMBDEN_Pos (21U) 7972 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 7973 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 7974 #define I2C_CR1_ALERTEN_Pos (22U) 7975 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 7976 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 7977 #define I2C_CR1_PECEN_Pos (23U) 7978 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 7979 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 7980 7981 /* Legacy defines */ 7982 #define I2C_CR1_DFN I2C_CR1_DNF 7983 7984 /****************** Bit definition for I2C_CR2 register ********************/ 7985 #define I2C_CR2_SADD_Pos (0U) 7986 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 7987 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 7988 #define I2C_CR2_RD_WRN_Pos (10U) 7989 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 7990 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 7991 #define I2C_CR2_ADD10_Pos (11U) 7992 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 7993 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 7994 #define I2C_CR2_HEAD10R_Pos (12U) 7995 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 7996 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 7997 #define I2C_CR2_START_Pos (13U) 7998 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 7999 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 8000 #define I2C_CR2_STOP_Pos (14U) 8001 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 8002 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 8003 #define I2C_CR2_NACK_Pos (15U) 8004 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 8005 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 8006 #define I2C_CR2_NBYTES_Pos (16U) 8007 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 8008 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 8009 #define I2C_CR2_RELOAD_Pos (24U) 8010 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 8011 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 8012 #define I2C_CR2_AUTOEND_Pos (25U) 8013 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 8014 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 8015 #define I2C_CR2_PECBYTE_Pos (26U) 8016 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 8017 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 8018 8019 /******************* Bit definition for I2C_OAR1 register ******************/ 8020 #define I2C_OAR1_OA1_Pos (0U) 8021 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 8022 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 8023 #define I2C_OAR1_OA1MODE_Pos (10U) 8024 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 8025 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 8026 #define I2C_OAR1_OA1EN_Pos (15U) 8027 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 8028 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 8029 8030 /******************* Bit definition for I2C_OAR2 register *******************/ 8031 #define I2C_OAR2_OA2_Pos (1U) 8032 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 8033 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 8034 #define I2C_OAR2_OA2MSK_Pos (8U) 8035 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 8036 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 8037 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 8038 #define I2C_OAR2_OA2MASK01_Pos (8U) 8039 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 8040 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 8041 #define I2C_OAR2_OA2MASK02_Pos (9U) 8042 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 8043 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 8044 #define I2C_OAR2_OA2MASK03_Pos (8U) 8045 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 8046 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 8047 #define I2C_OAR2_OA2MASK04_Pos (10U) 8048 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 8049 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 8050 #define I2C_OAR2_OA2MASK05_Pos (8U) 8051 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 8052 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 8053 #define I2C_OAR2_OA2MASK06_Pos (9U) 8054 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 8055 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 8056 #define I2C_OAR2_OA2MASK07_Pos (8U) 8057 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 8058 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 8059 #define I2C_OAR2_OA2EN_Pos (15U) 8060 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 8061 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 8062 8063 /******************* Bit definition for I2C_TIMINGR register *****************/ 8064 #define I2C_TIMINGR_SCLL_Pos (0U) 8065 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 8066 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 8067 #define I2C_TIMINGR_SCLH_Pos (8U) 8068 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 8069 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 8070 #define I2C_TIMINGR_SDADEL_Pos (16U) 8071 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 8072 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 8073 #define I2C_TIMINGR_SCLDEL_Pos (20U) 8074 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 8075 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 8076 #define I2C_TIMINGR_PRESC_Pos (28U) 8077 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 8078 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 8079 8080 /******************* Bit definition for I2C_TIMEOUTR register *****************/ 8081 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 8082 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 8083 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 8084 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 8085 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 8086 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 8087 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 8088 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 8089 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 8090 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 8091 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 8092 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 8093 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 8094 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 8095 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 8096 8097 /****************** Bit definition for I2C_ISR register *********************/ 8098 #define I2C_ISR_TXE_Pos (0U) 8099 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 8100 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 8101 #define I2C_ISR_TXIS_Pos (1U) 8102 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 8103 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 8104 #define I2C_ISR_RXNE_Pos (2U) 8105 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 8106 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 8107 #define I2C_ISR_ADDR_Pos (3U) 8108 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 8109 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 8110 #define I2C_ISR_NACKF_Pos (4U) 8111 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 8112 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 8113 #define I2C_ISR_STOPF_Pos (5U) 8114 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 8115 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 8116 #define I2C_ISR_TC_Pos (6U) 8117 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 8118 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 8119 #define I2C_ISR_TCR_Pos (7U) 8120 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 8121 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 8122 #define I2C_ISR_BERR_Pos (8U) 8123 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 8124 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 8125 #define I2C_ISR_ARLO_Pos (9U) 8126 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 8127 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 8128 #define I2C_ISR_OVR_Pos (10U) 8129 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 8130 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 8131 #define I2C_ISR_PECERR_Pos (11U) 8132 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 8133 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 8134 #define I2C_ISR_TIMEOUT_Pos (12U) 8135 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 8136 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 8137 #define I2C_ISR_ALERT_Pos (13U) 8138 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 8139 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 8140 #define I2C_ISR_BUSY_Pos (15U) 8141 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 8142 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 8143 #define I2C_ISR_DIR_Pos (16U) 8144 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 8145 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 8146 #define I2C_ISR_ADDCODE_Pos (17U) 8147 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 8148 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 8149 8150 /****************** Bit definition for I2C_ICR register *********************/ 8151 #define I2C_ICR_ADDRCF_Pos (3U) 8152 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 8153 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 8154 #define I2C_ICR_NACKCF_Pos (4U) 8155 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 8156 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 8157 #define I2C_ICR_STOPCF_Pos (5U) 8158 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 8159 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 8160 #define I2C_ICR_BERRCF_Pos (8U) 8161 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 8162 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 8163 #define I2C_ICR_ARLOCF_Pos (9U) 8164 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 8165 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 8166 #define I2C_ICR_OVRCF_Pos (10U) 8167 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 8168 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 8169 #define I2C_ICR_PECCF_Pos (11U) 8170 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 8171 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 8172 #define I2C_ICR_TIMOUTCF_Pos (12U) 8173 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 8174 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 8175 #define I2C_ICR_ALERTCF_Pos (13U) 8176 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 8177 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 8178 8179 /****************** Bit definition for I2C_PECR register ********************/ 8180 #define I2C_PECR_PEC_Pos (0U) 8181 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 8182 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 8183 8184 /****************** Bit definition for I2C_RXDR register *********************/ 8185 #define I2C_RXDR_RXDATA_Pos (0U) 8186 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 8187 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 8188 8189 /****************** Bit definition for I2C_TXDR register *********************/ 8190 #define I2C_TXDR_TXDATA_Pos (0U) 8191 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 8192 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 8193 8194 8195 /******************************************************************************/ 8196 /* */ 8197 /* Independent WATCHDOG (IWDG) */ 8198 /* */ 8199 /******************************************************************************/ 8200 /******************* Bit definition for IWDG_KR register ********************/ 8201 #define IWDG_KR_KEY_Pos (0U) 8202 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 8203 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 8204 8205 /******************* Bit definition for IWDG_PR register ********************/ 8206 #define IWDG_PR_PR_Pos (0U) 8207 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 8208 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 8209 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 8210 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 8211 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 8212 8213 /******************* Bit definition for IWDG_RLR register *******************/ 8214 #define IWDG_RLR_RL_Pos (0U) 8215 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 8216 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 8217 8218 /******************* Bit definition for IWDG_SR register ********************/ 8219 #define IWDG_SR_PVU_Pos (0U) 8220 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 8221 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 8222 #define IWDG_SR_RVU_Pos (1U) 8223 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 8224 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 8225 #define IWDG_SR_WVU_Pos (2U) 8226 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 8227 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 8228 8229 /******************* Bit definition for IWDG_KR register ********************/ 8230 #define IWDG_WINR_WIN_Pos (0U) 8231 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 8232 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 8233 8234 /******************************************************************************/ 8235 /* */ 8236 /* Power Control */ 8237 /* */ 8238 /******************************************************************************/ 8239 /* Note: No specific macro feature on this device */ 8240 /******************** Bit definition for PWR_CR register ********************/ 8241 #define PWR_CR_LPDS_Pos (0U) 8242 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 8243 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 8244 #define PWR_CR_PDDS_Pos (1U) 8245 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 8246 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 8247 #define PWR_CR_CWUF_Pos (2U) 8248 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 8249 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 8250 #define PWR_CR_CSBF_Pos (3U) 8251 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 8252 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 8253 8254 #define PWR_CR_DBP_Pos (8U) 8255 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 8256 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 8257 8258 /******************* Bit definition for PWR_CSR register ********************/ 8259 #define PWR_CSR_WUF_Pos (0U) 8260 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 8261 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 8262 #define PWR_CSR_SBF_Pos (1U) 8263 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 8264 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 8265 8266 #define PWR_CSR_EWUP1_Pos (8U) 8267 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 8268 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 8269 #define PWR_CSR_EWUP2_Pos (9U) 8270 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 8271 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 8272 #define PWR_CSR_EWUP3_Pos (10U) 8273 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 8274 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 8275 8276 /******************************************************************************/ 8277 /* */ 8278 /* Reset and Clock Control */ 8279 /* */ 8280 /******************************************************************************/ 8281 /* 8282 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 8283 */ 8284 8285 /******************** Bit definition for RCC_CR register ********************/ 8286 #define RCC_CR_HSION_Pos (0U) 8287 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 8288 #define RCC_CR_HSION RCC_CR_HSION_Msk 8289 #define RCC_CR_HSIRDY_Pos (1U) 8290 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 8291 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk 8292 8293 #define RCC_CR_HSITRIM_Pos (3U) 8294 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 8295 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk 8296 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 8297 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 8298 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 8299 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 8300 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 8301 8302 #define RCC_CR_HSICAL_Pos (8U) 8303 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 8304 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk 8305 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 8306 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 8307 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 8308 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 8309 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 8310 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 8311 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 8312 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 8313 8314 #define RCC_CR_HSEON_Pos (16U) 8315 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 8316 #define RCC_CR_HSEON RCC_CR_HSEON_Msk 8317 #define RCC_CR_HSERDY_Pos (17U) 8318 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 8319 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk 8320 #define RCC_CR_HSEBYP_Pos (18U) 8321 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 8322 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk 8323 #define RCC_CR_CSSON_Pos (19U) 8324 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 8325 #define RCC_CR_CSSON RCC_CR_CSSON_Msk 8326 #define RCC_CR_PLLON_Pos (24U) 8327 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 8328 #define RCC_CR_PLLON RCC_CR_PLLON_Msk 8329 #define RCC_CR_PLLRDY_Pos (25U) 8330 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 8331 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk 8332 8333 /******************** Bit definition for RCC_CFGR register ******************/ 8334 /*!< SW configuration */ 8335 #define RCC_CFGR_SW_Pos (0U) 8336 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 8337 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 8338 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 8339 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 8340 8341 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 8342 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 8343 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 8344 8345 /*!< SWS configuration */ 8346 #define RCC_CFGR_SWS_Pos (2U) 8347 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 8348 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 8349 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 8350 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 8351 8352 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 8353 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 8354 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 8355 8356 /*!< HPRE configuration */ 8357 #define RCC_CFGR_HPRE_Pos (4U) 8358 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 8359 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 8360 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 8361 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 8362 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 8363 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 8364 8365 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 8366 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 8367 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 8368 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 8369 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 8370 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 8371 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 8372 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 8373 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 8374 8375 /*!< PPRE1 configuration */ 8376 #define RCC_CFGR_PPRE1_Pos (8U) 8377 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 8378 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 8379 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 8380 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 8381 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 8382 8383 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 8384 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 8385 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 8386 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 8387 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 8388 8389 /*!< PPRE2 configuration */ 8390 #define RCC_CFGR_PPRE2_Pos (11U) 8391 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 8392 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 8393 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 8394 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 8395 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 8396 8397 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 8398 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 8399 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 8400 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 8401 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 8402 8403 #define RCC_CFGR_PLLSRC_Pos (16U) 8404 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 8405 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 8406 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 8407 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 8408 8409 #define RCC_CFGR_PLLXTPRE_Pos (17U) 8410 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 8411 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 8412 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 8413 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 8414 8415 /*!< PLLMUL configuration */ 8416 #define RCC_CFGR_PLLMUL_Pos (18U) 8417 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 8418 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 8419 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 8420 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 8421 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 8422 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 8423 8424 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 8425 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 8426 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 8427 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 8428 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 8429 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 8430 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 8431 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 8432 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 8433 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 8434 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 8435 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 8436 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 8437 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 8438 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 8439 8440 /*!< MCO configuration */ 8441 #define RCC_CFGR_MCO_Pos (24U) 8442 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 8443 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 8444 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 8445 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 8446 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 8447 8448 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 8449 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 8450 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 8451 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 8452 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 8453 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 8454 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 8455 8456 #define RCC_CFGR_MCOPRE_Pos (28U) 8457 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 8458 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */ 8459 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 8460 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 8461 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 8462 8463 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 8464 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 8465 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 8466 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 8467 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 8468 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */ 8469 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */ 8470 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */ 8471 8472 #define RCC_CFGR_PLLNODIV_Pos (31U) 8473 #define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */ 8474 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< Do not divide PLL to MCO */ 8475 8476 /* Reference defines */ 8477 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 8478 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 8479 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 8480 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 8481 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 8482 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 8483 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 8484 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 8485 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 8486 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 8487 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 8488 8489 /********************* Bit definition for RCC_CIR register ********************/ 8490 #define RCC_CIR_LSIRDYF_Pos (0U) 8491 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 8492 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 8493 #define RCC_CIR_LSERDYF_Pos (1U) 8494 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 8495 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 8496 #define RCC_CIR_HSIRDYF_Pos (2U) 8497 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 8498 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 8499 #define RCC_CIR_HSERDYF_Pos (3U) 8500 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 8501 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 8502 #define RCC_CIR_PLLRDYF_Pos (4U) 8503 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 8504 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 8505 #define RCC_CIR_CSSF_Pos (7U) 8506 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 8507 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 8508 #define RCC_CIR_LSIRDYIE_Pos (8U) 8509 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 8510 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 8511 #define RCC_CIR_LSERDYIE_Pos (9U) 8512 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 8513 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 8514 #define RCC_CIR_HSIRDYIE_Pos (10U) 8515 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 8516 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 8517 #define RCC_CIR_HSERDYIE_Pos (11U) 8518 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 8519 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 8520 #define RCC_CIR_PLLRDYIE_Pos (12U) 8521 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 8522 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 8523 #define RCC_CIR_LSIRDYC_Pos (16U) 8524 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 8525 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 8526 #define RCC_CIR_LSERDYC_Pos (17U) 8527 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 8528 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 8529 #define RCC_CIR_HSIRDYC_Pos (18U) 8530 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 8531 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 8532 #define RCC_CIR_HSERDYC_Pos (19U) 8533 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 8534 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 8535 #define RCC_CIR_PLLRDYC_Pos (20U) 8536 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 8537 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 8538 #define RCC_CIR_CSSC_Pos (23U) 8539 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 8540 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 8541 8542 /****************** Bit definition for RCC_APB2RSTR register *****************/ 8543 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 8544 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 8545 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 8546 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 8547 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 8548 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 8549 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 8550 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 8551 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 8552 #define RCC_APB2RSTR_USART1RST_Pos (14U) 8553 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 8554 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 8555 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 8556 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 8557 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ 8558 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 8559 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 8560 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 8561 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 8562 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 8563 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 8564 8565 /****************** Bit definition for RCC_APB1RSTR register ******************/ 8566 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 8567 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 8568 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 8569 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 8570 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 8571 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 8572 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 8573 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 8574 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 8575 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 8576 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 8577 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 8578 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 8579 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 8580 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 8581 #define RCC_APB1RSTR_USART2RST_Pos (17U) 8582 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 8583 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 8584 #define RCC_APB1RSTR_USART3RST_Pos (18U) 8585 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 8586 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 8587 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 8588 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 8589 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 8590 #define RCC_APB1RSTR_CANRST_Pos (25U) 8591 #define RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */ 8592 #define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk /*!< CAN reset */ 8593 #define RCC_APB1RSTR_DAC2RST_Pos (26U) 8594 #define RCC_APB1RSTR_DAC2RST_Msk (0x1UL << RCC_APB1RSTR_DAC2RST_Pos) /*!< 0x04000000 */ 8595 #define RCC_APB1RSTR_DAC2RST RCC_APB1RSTR_DAC2RST_Msk /*!< DAC 2 reset */ 8596 #define RCC_APB1RSTR_PWRRST_Pos (28U) 8597 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 8598 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 8599 #define RCC_APB1RSTR_DAC1RST_Pos (29U) 8600 #define RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */ 8601 #define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk /*!< DAC 1 reset */ 8602 8603 /****************** Bit definition for RCC_AHBENR register ******************/ 8604 #define RCC_AHBENR_DMA1EN_Pos (0U) 8605 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 8606 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 8607 #define RCC_AHBENR_SRAMEN_Pos (2U) 8608 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 8609 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 8610 #define RCC_AHBENR_FLITFEN_Pos (4U) 8611 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 8612 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 8613 #define RCC_AHBENR_CRCEN_Pos (6U) 8614 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 8615 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 8616 #define RCC_AHBENR_GPIOAEN_Pos (17U) 8617 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 8618 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 8619 #define RCC_AHBENR_GPIOBEN_Pos (18U) 8620 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 8621 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 8622 #define RCC_AHBENR_GPIOCEN_Pos (19U) 8623 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 8624 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 8625 #define RCC_AHBENR_GPIODEN_Pos (20U) 8626 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ 8627 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ 8628 #define RCC_AHBENR_GPIOFEN_Pos (22U) 8629 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 8630 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 8631 #define RCC_AHBENR_TSCEN_Pos (24U) 8632 #define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */ 8633 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS clock enable */ 8634 #define RCC_AHBENR_ADC12EN_Pos (28U) 8635 #define RCC_AHBENR_ADC12EN_Msk (0x1UL << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */ 8636 #define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk /*!< ADC1/ ADC2 clock enable */ 8637 8638 /***************** Bit definition for RCC_APB2ENR register ******************/ 8639 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 8640 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 8641 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ 8642 #define RCC_APB2ENR_TIM1EN_Pos (11U) 8643 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 8644 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 8645 #define RCC_APB2ENR_SPI1EN_Pos (12U) 8646 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 8647 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 8648 #define RCC_APB2ENR_USART1EN_Pos (14U) 8649 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 8650 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 8651 #define RCC_APB2ENR_TIM15EN_Pos (16U) 8652 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 8653 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ 8654 #define RCC_APB2ENR_TIM16EN_Pos (17U) 8655 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 8656 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 8657 #define RCC_APB2ENR_TIM17EN_Pos (18U) 8658 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 8659 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 8660 8661 /****************** Bit definition for RCC_APB1ENR register ******************/ 8662 #define RCC_APB1ENR_TIM2EN_Pos (0U) 8663 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 8664 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 8665 #define RCC_APB1ENR_TIM3EN_Pos (1U) 8666 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 8667 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 8668 #define RCC_APB1ENR_TIM6EN_Pos (4U) 8669 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 8670 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 8671 #define RCC_APB1ENR_TIM7EN_Pos (5U) 8672 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 8673 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 8674 #define RCC_APB1ENR_WWDGEN_Pos (11U) 8675 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 8676 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 8677 #define RCC_APB1ENR_USART2EN_Pos (17U) 8678 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 8679 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 8680 #define RCC_APB1ENR_USART3EN_Pos (18U) 8681 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 8682 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 8683 #define RCC_APB1ENR_I2C1EN_Pos (21U) 8684 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 8685 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 8686 #define RCC_APB1ENR_CANEN_Pos (25U) 8687 #define RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */ 8688 #define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk /*!< CAN clock enable */ 8689 #define RCC_APB1ENR_DAC2EN_Pos (26U) 8690 #define RCC_APB1ENR_DAC2EN_Msk (0x1UL << RCC_APB1ENR_DAC2EN_Pos) /*!< 0x04000000 */ 8691 #define RCC_APB1ENR_DAC2EN RCC_APB1ENR_DAC2EN_Msk /*!< DAC 2 clock enable */ 8692 #define RCC_APB1ENR_PWREN_Pos (28U) 8693 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 8694 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 8695 #define RCC_APB1ENR_DAC1EN_Pos (29U) 8696 #define RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */ 8697 #define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk /*!< DAC 1 clock enable */ 8698 8699 /******************** Bit definition for RCC_BDCR register ******************/ 8700 #define RCC_BDCR_LSE_Pos (0U) 8701 #define RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos) /*!< 0x00000007 */ 8702 #define RCC_BDCR_LSE RCC_BDCR_LSE_Msk /*!< External Low Speed oscillator [2:0] bits */ 8703 #define RCC_BDCR_LSEON_Pos (0U) 8704 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 8705 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 8706 #define RCC_BDCR_LSERDY_Pos (1U) 8707 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 8708 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 8709 #define RCC_BDCR_LSEBYP_Pos (2U) 8710 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 8711 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 8712 8713 #define RCC_BDCR_LSEDRV_Pos (3U) 8714 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 8715 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 8716 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 8717 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 8718 8719 #define RCC_BDCR_RTCSEL_Pos (8U) 8720 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 8721 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 8722 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 8723 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 8724 8725 /*!< RTC configuration */ 8726 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 8727 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 8728 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 8729 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 8730 8731 #define RCC_BDCR_RTCEN_Pos (15U) 8732 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 8733 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 8734 #define RCC_BDCR_BDRST_Pos (16U) 8735 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 8736 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 8737 8738 /******************** Bit definition for RCC_CSR register *******************/ 8739 #define RCC_CSR_LSION_Pos (0U) 8740 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 8741 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 8742 #define RCC_CSR_LSIRDY_Pos (1U) 8743 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 8744 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 8745 #define RCC_CSR_RMVF_Pos (24U) 8746 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 8747 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 8748 #define RCC_CSR_OBLRSTF_Pos (25U) 8749 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 8750 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 8751 #define RCC_CSR_PINRSTF_Pos (26U) 8752 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 8753 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 8754 #define RCC_CSR_PORRSTF_Pos (27U) 8755 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 8756 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 8757 #define RCC_CSR_SFTRSTF_Pos (28U) 8758 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 8759 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 8760 #define RCC_CSR_IWDGRSTF_Pos (29U) 8761 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 8762 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 8763 #define RCC_CSR_WWDGRSTF_Pos (30U) 8764 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 8765 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 8766 #define RCC_CSR_LPWRRSTF_Pos (31U) 8767 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 8768 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 8769 8770 /******************* Bit definition for RCC_AHBRSTR register ****************/ 8771 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 8772 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 8773 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 8774 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 8775 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 8776 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 8777 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 8778 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 8779 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 8780 #define RCC_AHBRSTR_GPIODRST_Pos (20U) 8781 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ 8782 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ 8783 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 8784 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 8785 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 8786 #define RCC_AHBRSTR_TSCRST_Pos (24U) 8787 #define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */ 8788 #define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */ 8789 #define RCC_AHBRSTR_ADC12RST_Pos (28U) 8790 #define RCC_AHBRSTR_ADC12RST_Msk (0x1UL << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */ 8791 #define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk /*!< ADC1 & ADC2 reset */ 8792 8793 /******************* Bit definition for RCC_CFGR2 register ******************/ 8794 /*!< PREDIV configuration */ 8795 #define RCC_CFGR2_PREDIV_Pos (0U) 8796 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 8797 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 8798 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 8799 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 8800 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 8801 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 8802 8803 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 8804 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 8805 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 8806 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 8807 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 8808 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 8809 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 8810 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 8811 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 8812 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 8813 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 8814 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 8815 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 8816 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 8817 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 8818 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 8819 8820 /*!< ADCPRE12 configuration */ 8821 #define RCC_CFGR2_ADCPRE12_Pos (4U) 8822 #define RCC_CFGR2_ADCPRE12_Msk (0x1FUL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */ 8823 #define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk /*!< ADCPRE12[8:4] bits */ 8824 #define RCC_CFGR2_ADCPRE12_0 (0x01UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */ 8825 #define RCC_CFGR2_ADCPRE12_1 (0x02UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */ 8826 #define RCC_CFGR2_ADCPRE12_2 (0x04UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */ 8827 #define RCC_CFGR2_ADCPRE12_3 (0x08UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */ 8828 #define RCC_CFGR2_ADCPRE12_4 (0x10UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */ 8829 8830 #define RCC_CFGR2_ADCPRE12_NO (0x00000000U) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ 8831 #define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U) /*!< ADC12 PLL clock divided by 1 */ 8832 #define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U) /*!< ADC12 PLL clock divided by 2 */ 8833 #define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U) /*!< ADC12 PLL clock divided by 4 */ 8834 #define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U) /*!< ADC12 PLL clock divided by 6 */ 8835 #define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U) /*!< ADC12 PLL clock divided by 8 */ 8836 #define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U) /*!< ADC12 PLL clock divided by 10 */ 8837 #define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U) /*!< ADC12 PLL clock divided by 12 */ 8838 #define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U) /*!< ADC12 PLL clock divided by 16 */ 8839 #define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U) /*!< ADC12 PLL clock divided by 32 */ 8840 #define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U) /*!< ADC12 PLL clock divided by 64 */ 8841 #define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U) /*!< ADC12 PLL clock divided by 128 */ 8842 #define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U) /*!< ADC12 PLL clock divided by 256 */ 8843 8844 /******************* Bit definition for RCC_CFGR3 register ******************/ 8845 #define RCC_CFGR3_USART1SW_Pos (0U) 8846 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 8847 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 8848 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 8849 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 8850 8851 #define RCC_CFGR3_USART1SW_PCLK1 (0x00000000U) /*!< PCLK1 clock used as USART1 clock source */ 8852 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 8853 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 8854 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 8855 /* Legacy defines */ 8856 #define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1 8857 8858 #define RCC_CFGR3_I2CSW_Pos (4U) 8859 #define RCC_CFGR3_I2CSW_Msk (0x1UL << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000010 */ 8860 #define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk /*!< I2CSW bits */ 8861 #define RCC_CFGR3_I2C1SW_Pos (4U) 8862 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 8863 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 8864 8865 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 8866 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 8867 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 8868 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 8869 #define RCC_CFGR3_TIMSW_Pos (8U) 8870 #define RCC_CFGR3_TIMSW_Msk (0x1UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */ 8871 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */ 8872 #define RCC_CFGR3_TIM1SW_Pos (8U) 8873 #define RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */ 8874 #define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk /*!< TIM1SW bits */ 8875 #define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U) /*!< PCLK2 used as TIM1 clock source */ 8876 #define RCC_CFGR3_TIM1SW_PLL_Pos (8U) 8877 #define RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */ 8878 #define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk /*!< PLL clock used as TIM1 clock source */ 8879 8880 /* Legacy defines */ 8881 #define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2 8882 8883 /******************************************************************************/ 8884 /* */ 8885 /* Real-Time Clock (RTC) */ 8886 /* */ 8887 /******************************************************************************/ 8888 /* 8889 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 8890 */ 8891 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 8892 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 8893 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 8894 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 8895 8896 /******************** Bits definition for RTC_TR register *******************/ 8897 #define RTC_TR_PM_Pos (22U) 8898 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 8899 #define RTC_TR_PM RTC_TR_PM_Msk 8900 #define RTC_TR_HT_Pos (20U) 8901 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 8902 #define RTC_TR_HT RTC_TR_HT_Msk 8903 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 8904 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 8905 #define RTC_TR_HU_Pos (16U) 8906 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 8907 #define RTC_TR_HU RTC_TR_HU_Msk 8908 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 8909 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 8910 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 8911 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 8912 #define RTC_TR_MNT_Pos (12U) 8913 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 8914 #define RTC_TR_MNT RTC_TR_MNT_Msk 8915 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 8916 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 8917 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 8918 #define RTC_TR_MNU_Pos (8U) 8919 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 8920 #define RTC_TR_MNU RTC_TR_MNU_Msk 8921 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 8922 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 8923 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 8924 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 8925 #define RTC_TR_ST_Pos (4U) 8926 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 8927 #define RTC_TR_ST RTC_TR_ST_Msk 8928 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 8929 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 8930 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 8931 #define RTC_TR_SU_Pos (0U) 8932 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 8933 #define RTC_TR_SU RTC_TR_SU_Msk 8934 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 8935 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 8936 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 8937 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 8938 8939 /******************** Bits definition for RTC_DR register *******************/ 8940 #define RTC_DR_YT_Pos (20U) 8941 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 8942 #define RTC_DR_YT RTC_DR_YT_Msk 8943 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 8944 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 8945 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 8946 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 8947 #define RTC_DR_YU_Pos (16U) 8948 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 8949 #define RTC_DR_YU RTC_DR_YU_Msk 8950 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 8951 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 8952 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 8953 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 8954 #define RTC_DR_WDU_Pos (13U) 8955 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 8956 #define RTC_DR_WDU RTC_DR_WDU_Msk 8957 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 8958 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 8959 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 8960 #define RTC_DR_MT_Pos (12U) 8961 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 8962 #define RTC_DR_MT RTC_DR_MT_Msk 8963 #define RTC_DR_MU_Pos (8U) 8964 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 8965 #define RTC_DR_MU RTC_DR_MU_Msk 8966 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 8967 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 8968 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 8969 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 8970 #define RTC_DR_DT_Pos (4U) 8971 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 8972 #define RTC_DR_DT RTC_DR_DT_Msk 8973 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 8974 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 8975 #define RTC_DR_DU_Pos (0U) 8976 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 8977 #define RTC_DR_DU RTC_DR_DU_Msk 8978 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 8979 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 8980 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 8981 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 8982 8983 /******************** Bits definition for RTC_CR register *******************/ 8984 #define RTC_CR_COE_Pos (23U) 8985 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 8986 #define RTC_CR_COE RTC_CR_COE_Msk 8987 #define RTC_CR_OSEL_Pos (21U) 8988 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 8989 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 8990 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 8991 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 8992 #define RTC_CR_POL_Pos (20U) 8993 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 8994 #define RTC_CR_POL RTC_CR_POL_Msk 8995 #define RTC_CR_COSEL_Pos (19U) 8996 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 8997 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 8998 #define RTC_CR_BKP_Pos (18U) 8999 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 9000 #define RTC_CR_BKP RTC_CR_BKP_Msk 9001 #define RTC_CR_SUB1H_Pos (17U) 9002 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 9003 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 9004 #define RTC_CR_ADD1H_Pos (16U) 9005 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 9006 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 9007 #define RTC_CR_TSIE_Pos (15U) 9008 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 9009 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 9010 #define RTC_CR_WUTIE_Pos (14U) 9011 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 9012 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 9013 #define RTC_CR_ALRBIE_Pos (13U) 9014 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 9015 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 9016 #define RTC_CR_ALRAIE_Pos (12U) 9017 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 9018 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 9019 #define RTC_CR_TSE_Pos (11U) 9020 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 9021 #define RTC_CR_TSE RTC_CR_TSE_Msk 9022 #define RTC_CR_WUTE_Pos (10U) 9023 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 9024 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 9025 #define RTC_CR_ALRBE_Pos (9U) 9026 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 9027 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 9028 #define RTC_CR_ALRAE_Pos (8U) 9029 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 9030 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 9031 #define RTC_CR_FMT_Pos (6U) 9032 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 9033 #define RTC_CR_FMT RTC_CR_FMT_Msk 9034 #define RTC_CR_BYPSHAD_Pos (5U) 9035 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 9036 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 9037 #define RTC_CR_REFCKON_Pos (4U) 9038 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 9039 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 9040 #define RTC_CR_TSEDGE_Pos (3U) 9041 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 9042 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 9043 #define RTC_CR_WUCKSEL_Pos (0U) 9044 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 9045 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 9046 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 9047 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 9048 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 9049 9050 /* Legacy defines */ 9051 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 9052 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 9053 #define RTC_CR_BCK RTC_CR_BKP 9054 9055 /******************** Bits definition for RTC_ISR register ******************/ 9056 #define RTC_ISR_RECALPF_Pos (16U) 9057 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 9058 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 9059 #define RTC_ISR_TAMP2F_Pos (14U) 9060 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 9061 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 9062 #define RTC_ISR_TAMP1F_Pos (13U) 9063 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 9064 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 9065 #define RTC_ISR_TSOVF_Pos (12U) 9066 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 9067 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 9068 #define RTC_ISR_TSF_Pos (11U) 9069 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 9070 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 9071 #define RTC_ISR_WUTF_Pos (10U) 9072 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 9073 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 9074 #define RTC_ISR_ALRBF_Pos (9U) 9075 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 9076 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 9077 #define RTC_ISR_ALRAF_Pos (8U) 9078 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 9079 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 9080 #define RTC_ISR_INIT_Pos (7U) 9081 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 9082 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 9083 #define RTC_ISR_INITF_Pos (6U) 9084 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 9085 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 9086 #define RTC_ISR_RSF_Pos (5U) 9087 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 9088 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 9089 #define RTC_ISR_INITS_Pos (4U) 9090 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 9091 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 9092 #define RTC_ISR_SHPF_Pos (3U) 9093 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 9094 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 9095 #define RTC_ISR_WUTWF_Pos (2U) 9096 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 9097 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 9098 #define RTC_ISR_ALRBWF_Pos (1U) 9099 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 9100 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 9101 #define RTC_ISR_ALRAWF_Pos (0U) 9102 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 9103 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 9104 9105 /******************** Bits definition for RTC_PRER register *****************/ 9106 #define RTC_PRER_PREDIV_A_Pos (16U) 9107 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 9108 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 9109 #define RTC_PRER_PREDIV_S_Pos (0U) 9110 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 9111 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 9112 9113 /******************** Bits definition for RTC_WUTR register *****************/ 9114 #define RTC_WUTR_WUT_Pos (0U) 9115 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 9116 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 9117 9118 /******************** Bits definition for RTC_ALRMAR register ***************/ 9119 #define RTC_ALRMAR_MSK4_Pos (31U) 9120 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 9121 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 9122 #define RTC_ALRMAR_WDSEL_Pos (30U) 9123 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 9124 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 9125 #define RTC_ALRMAR_DT_Pos (28U) 9126 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 9127 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 9128 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 9129 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 9130 #define RTC_ALRMAR_DU_Pos (24U) 9131 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 9132 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 9133 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 9134 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 9135 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 9136 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 9137 #define RTC_ALRMAR_MSK3_Pos (23U) 9138 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 9139 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 9140 #define RTC_ALRMAR_PM_Pos (22U) 9141 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 9142 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 9143 #define RTC_ALRMAR_HT_Pos (20U) 9144 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 9145 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 9146 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 9147 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 9148 #define RTC_ALRMAR_HU_Pos (16U) 9149 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 9150 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 9151 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 9152 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 9153 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 9154 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 9155 #define RTC_ALRMAR_MSK2_Pos (15U) 9156 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 9157 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 9158 #define RTC_ALRMAR_MNT_Pos (12U) 9159 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 9160 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 9161 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 9162 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 9163 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 9164 #define RTC_ALRMAR_MNU_Pos (8U) 9165 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 9166 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 9167 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 9168 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 9169 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 9170 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 9171 #define RTC_ALRMAR_MSK1_Pos (7U) 9172 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 9173 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 9174 #define RTC_ALRMAR_ST_Pos (4U) 9175 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 9176 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 9177 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 9178 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 9179 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 9180 #define RTC_ALRMAR_SU_Pos (0U) 9181 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 9182 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 9183 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 9184 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 9185 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 9186 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 9187 9188 /******************** Bits definition for RTC_ALRMBR register ***************/ 9189 #define RTC_ALRMBR_MSK4_Pos (31U) 9190 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 9191 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 9192 #define RTC_ALRMBR_WDSEL_Pos (30U) 9193 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 9194 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 9195 #define RTC_ALRMBR_DT_Pos (28U) 9196 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 9197 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 9198 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 9199 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 9200 #define RTC_ALRMBR_DU_Pos (24U) 9201 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 9202 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 9203 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 9204 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 9205 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 9206 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 9207 #define RTC_ALRMBR_MSK3_Pos (23U) 9208 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 9209 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 9210 #define RTC_ALRMBR_PM_Pos (22U) 9211 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 9212 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 9213 #define RTC_ALRMBR_HT_Pos (20U) 9214 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 9215 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 9216 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 9217 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 9218 #define RTC_ALRMBR_HU_Pos (16U) 9219 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 9220 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 9221 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 9222 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 9223 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 9224 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 9225 #define RTC_ALRMBR_MSK2_Pos (15U) 9226 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 9227 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 9228 #define RTC_ALRMBR_MNT_Pos (12U) 9229 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 9230 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 9231 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 9232 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 9233 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 9234 #define RTC_ALRMBR_MNU_Pos (8U) 9235 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 9236 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 9237 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 9238 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 9239 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 9240 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 9241 #define RTC_ALRMBR_MSK1_Pos (7U) 9242 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 9243 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 9244 #define RTC_ALRMBR_ST_Pos (4U) 9245 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 9246 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 9247 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 9248 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 9249 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 9250 #define RTC_ALRMBR_SU_Pos (0U) 9251 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 9252 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 9253 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 9254 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 9255 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 9256 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 9257 9258 /******************** Bits definition for RTC_WPR register ******************/ 9259 #define RTC_WPR_KEY_Pos (0U) 9260 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 9261 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 9262 9263 /******************** Bits definition for RTC_SSR register ******************/ 9264 #define RTC_SSR_SS_Pos (0U) 9265 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 9266 #define RTC_SSR_SS RTC_SSR_SS_Msk 9267 9268 /******************** Bits definition for RTC_SHIFTR register ***************/ 9269 #define RTC_SHIFTR_SUBFS_Pos (0U) 9270 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 9271 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 9272 #define RTC_SHIFTR_ADD1S_Pos (31U) 9273 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 9274 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 9275 9276 /******************** Bits definition for RTC_TSTR register *****************/ 9277 #define RTC_TSTR_PM_Pos (22U) 9278 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 9279 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 9280 #define RTC_TSTR_HT_Pos (20U) 9281 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 9282 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 9283 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 9284 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 9285 #define RTC_TSTR_HU_Pos (16U) 9286 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 9287 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 9288 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 9289 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 9290 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 9291 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 9292 #define RTC_TSTR_MNT_Pos (12U) 9293 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 9294 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 9295 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 9296 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 9297 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 9298 #define RTC_TSTR_MNU_Pos (8U) 9299 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 9300 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 9301 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 9302 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 9303 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 9304 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 9305 #define RTC_TSTR_ST_Pos (4U) 9306 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 9307 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 9308 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 9309 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 9310 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 9311 #define RTC_TSTR_SU_Pos (0U) 9312 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 9313 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 9314 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 9315 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 9316 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 9317 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 9318 9319 /******************** Bits definition for RTC_TSDR register *****************/ 9320 #define RTC_TSDR_WDU_Pos (13U) 9321 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 9322 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 9323 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 9324 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 9325 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 9326 #define RTC_TSDR_MT_Pos (12U) 9327 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 9328 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 9329 #define RTC_TSDR_MU_Pos (8U) 9330 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 9331 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 9332 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 9333 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 9334 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 9335 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 9336 #define RTC_TSDR_DT_Pos (4U) 9337 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 9338 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 9339 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 9340 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 9341 #define RTC_TSDR_DU_Pos (0U) 9342 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 9343 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 9344 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 9345 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 9346 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 9347 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 9348 9349 /******************** Bits definition for RTC_TSSSR register ****************/ 9350 #define RTC_TSSSR_SS_Pos (0U) 9351 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 9352 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 9353 9354 /******************** Bits definition for RTC_CAL register *****************/ 9355 #define RTC_CALR_CALP_Pos (15U) 9356 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 9357 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 9358 #define RTC_CALR_CALW8_Pos (14U) 9359 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 9360 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 9361 #define RTC_CALR_CALW16_Pos (13U) 9362 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 9363 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 9364 #define RTC_CALR_CALM_Pos (0U) 9365 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 9366 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 9367 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 9368 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 9369 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 9370 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 9371 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 9372 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 9373 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 9374 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 9375 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 9376 9377 /******************** Bits definition for RTC_TAFCR register ****************/ 9378 #define RTC_TAFCR_PC15MODE_Pos (23U) 9379 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 9380 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 9381 #define RTC_TAFCR_PC15VALUE_Pos (22U) 9382 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 9383 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 9384 #define RTC_TAFCR_PC14MODE_Pos (21U) 9385 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 9386 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 9387 #define RTC_TAFCR_PC14VALUE_Pos (20U) 9388 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 9389 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 9390 #define RTC_TAFCR_PC13MODE_Pos (19U) 9391 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 9392 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 9393 #define RTC_TAFCR_PC13VALUE_Pos (18U) 9394 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 9395 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 9396 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 9397 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 9398 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 9399 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 9400 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 9401 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 9402 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 9403 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 9404 #define RTC_TAFCR_TAMPFLT_Pos (11U) 9405 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 9406 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 9407 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 9408 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 9409 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 9410 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 9411 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 9412 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 9413 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 9414 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 9415 #define RTC_TAFCR_TAMPTS_Pos (7U) 9416 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 9417 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 9418 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 9419 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 9420 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 9421 #define RTC_TAFCR_TAMP2E_Pos (3U) 9422 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 9423 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 9424 #define RTC_TAFCR_TAMPIE_Pos (2U) 9425 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 9426 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 9427 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 9428 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 9429 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 9430 #define RTC_TAFCR_TAMP1E_Pos (0U) 9431 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 9432 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 9433 9434 /* Reference defines */ 9435 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 9436 9437 /******************** Bits definition for RTC_ALRMASSR register *************/ 9438 #define RTC_ALRMASSR_MASKSS_Pos (24U) 9439 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 9440 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 9441 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 9442 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 9443 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 9444 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 9445 #define RTC_ALRMASSR_SS_Pos (0U) 9446 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 9447 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 9448 9449 /******************** Bits definition for RTC_ALRMBSSR register *************/ 9450 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 9451 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 9452 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 9453 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 9454 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 9455 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 9456 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 9457 #define RTC_ALRMBSSR_SS_Pos (0U) 9458 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 9459 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 9460 9461 /******************** Bits definition for RTC_BKP0R register ****************/ 9462 #define RTC_BKP0R_Pos (0U) 9463 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 9464 #define RTC_BKP0R RTC_BKP0R_Msk 9465 9466 /******************** Bits definition for RTC_BKP1R register ****************/ 9467 #define RTC_BKP1R_Pos (0U) 9468 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 9469 #define RTC_BKP1R RTC_BKP1R_Msk 9470 9471 /******************** Bits definition for RTC_BKP2R register ****************/ 9472 #define RTC_BKP2R_Pos (0U) 9473 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 9474 #define RTC_BKP2R RTC_BKP2R_Msk 9475 9476 /******************** Bits definition for RTC_BKP3R register ****************/ 9477 #define RTC_BKP3R_Pos (0U) 9478 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 9479 #define RTC_BKP3R RTC_BKP3R_Msk 9480 9481 /******************** Bits definition for RTC_BKP4R register ****************/ 9482 #define RTC_BKP4R_Pos (0U) 9483 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 9484 #define RTC_BKP4R RTC_BKP4R_Msk 9485 9486 /******************** Number of backup registers ******************************/ 9487 #define RTC_BKP_NUMBER 5 9488 9489 /******************************************************************************/ 9490 /* */ 9491 /* Serial Peripheral Interface (SPI) */ 9492 /* */ 9493 /******************************************************************************/ 9494 9495 /* 9496 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 9497 */ 9498 /* Note: No specific macro feature on this device */ 9499 9500 /******************* Bit definition for SPI_CR1 register ********************/ 9501 #define SPI_CR1_CPHA_Pos (0U) 9502 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 9503 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 9504 #define SPI_CR1_CPOL_Pos (1U) 9505 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 9506 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 9507 #define SPI_CR1_MSTR_Pos (2U) 9508 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 9509 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 9510 #define SPI_CR1_BR_Pos (3U) 9511 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 9512 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 9513 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 9514 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 9515 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 9516 #define SPI_CR1_SPE_Pos (6U) 9517 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 9518 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 9519 #define SPI_CR1_LSBFIRST_Pos (7U) 9520 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 9521 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 9522 #define SPI_CR1_SSI_Pos (8U) 9523 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 9524 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 9525 #define SPI_CR1_SSM_Pos (9U) 9526 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 9527 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 9528 #define SPI_CR1_RXONLY_Pos (10U) 9529 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 9530 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 9531 #define SPI_CR1_CRCL_Pos (11U) 9532 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 9533 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 9534 #define SPI_CR1_CRCNEXT_Pos (12U) 9535 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 9536 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 9537 #define SPI_CR1_CRCEN_Pos (13U) 9538 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 9539 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 9540 #define SPI_CR1_BIDIOE_Pos (14U) 9541 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 9542 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 9543 #define SPI_CR1_BIDIMODE_Pos (15U) 9544 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 9545 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 9546 9547 /******************* Bit definition for SPI_CR2 register ********************/ 9548 #define SPI_CR2_RXDMAEN_Pos (0U) 9549 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 9550 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 9551 #define SPI_CR2_TXDMAEN_Pos (1U) 9552 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 9553 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 9554 #define SPI_CR2_SSOE_Pos (2U) 9555 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 9556 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 9557 #define SPI_CR2_NSSP_Pos (3U) 9558 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 9559 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 9560 #define SPI_CR2_FRF_Pos (4U) 9561 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 9562 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 9563 #define SPI_CR2_ERRIE_Pos (5U) 9564 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 9565 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 9566 #define SPI_CR2_RXNEIE_Pos (6U) 9567 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 9568 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 9569 #define SPI_CR2_TXEIE_Pos (7U) 9570 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 9571 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 9572 #define SPI_CR2_DS_Pos (8U) 9573 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 9574 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 9575 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 9576 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 9577 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 9578 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 9579 #define SPI_CR2_FRXTH_Pos (12U) 9580 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 9581 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 9582 #define SPI_CR2_LDMARX_Pos (13U) 9583 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 9584 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 9585 #define SPI_CR2_LDMATX_Pos (14U) 9586 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 9587 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 9588 9589 /******************** Bit definition for SPI_SR register ********************/ 9590 #define SPI_SR_RXNE_Pos (0U) 9591 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 9592 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 9593 #define SPI_SR_TXE_Pos (1U) 9594 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 9595 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 9596 #define SPI_SR_CRCERR_Pos (4U) 9597 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 9598 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 9599 #define SPI_SR_MODF_Pos (5U) 9600 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 9601 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 9602 #define SPI_SR_OVR_Pos (6U) 9603 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 9604 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 9605 #define SPI_SR_BSY_Pos (7U) 9606 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 9607 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 9608 #define SPI_SR_FRE_Pos (8U) 9609 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 9610 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 9611 #define SPI_SR_FRLVL_Pos (9U) 9612 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 9613 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 9614 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 9615 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 9616 #define SPI_SR_FTLVL_Pos (11U) 9617 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 9618 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 9619 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 9620 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 9621 9622 /******************** Bit definition for SPI_DR register ********************/ 9623 #define SPI_DR_DR_Pos (0U) 9624 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 9625 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 9626 9627 /******************* Bit definition for SPI_CRCPR register ******************/ 9628 #define SPI_CRCPR_CRCPOLY_Pos (0U) 9629 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 9630 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 9631 9632 /****************** Bit definition for SPI_RXCRCR register ******************/ 9633 #define SPI_RXCRCR_RXCRC_Pos (0U) 9634 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 9635 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 9636 9637 /****************** Bit definition for SPI_TXCRCR register ******************/ 9638 #define SPI_TXCRCR_TXCRC_Pos (0U) 9639 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 9640 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 9641 9642 /******************************************************************************/ 9643 /* */ 9644 /* System Configuration(SYSCFG) */ 9645 /* */ 9646 /******************************************************************************/ 9647 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 9648 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 9649 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 9650 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 9651 #define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U) /*!< Bit 0 */ 9652 #define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U) /*!< Bit 1 */ 9653 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U) 9654 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */ 9655 #define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */ 9656 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U) 9657 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */ 9658 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */ 9659 #define SYSCFG_CFGR1_DMA_RMP_Pos (11U) 9660 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x0000F800 */ 9661 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */ 9662 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U) 9663 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */ 9664 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */ 9665 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U) 9666 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */ 9667 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */ 9668 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U) 9669 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */ 9670 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */ 9671 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U) 9672 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */ 9673 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */ 9674 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos (15U) 9675 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos) /*!< 0x00008000 */ 9676 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk /*!< DAC2 CH1 DMA remap */ 9677 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 9678 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 9679 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 9680 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 9681 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 9682 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 9683 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 9684 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 9685 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 9686 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 9687 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 9688 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 9689 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 9690 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 9691 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 9692 #define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U) 9693 #define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */ 9694 #define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */ 9695 #define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */ 9696 #define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */ 9697 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U) 9698 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */ 9699 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 9700 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U) 9701 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */ 9702 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 9703 #define SYSCFG_CFGR1_FPU_IE_Pos (26U) 9704 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */ 9705 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Floating Point Unit Interrupt Enable */ 9706 #define SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */ 9707 #define SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */ 9708 #define SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */ 9709 #define SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */ 9710 #define SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */ 9711 #define SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */ 9712 9713 /***************** Bit definition for SYSCFG_RCR register *******************/ 9714 #define SYSCFG_RCR_PAGE0_Pos (0U) 9715 #define SYSCFG_RCR_PAGE0_Msk (0x1UL << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */ 9716 #define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk /*!< ICODE SRAM Write protection page 0 */ 9717 #define SYSCFG_RCR_PAGE1_Pos (1U) 9718 #define SYSCFG_RCR_PAGE1_Msk (0x1UL << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */ 9719 #define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk /*!< ICODE SRAM Write protection page 1 */ 9720 #define SYSCFG_RCR_PAGE2_Pos (2U) 9721 #define SYSCFG_RCR_PAGE2_Msk (0x1UL << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */ 9722 #define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk /*!< ICODE SRAM Write protection page 2 */ 9723 #define SYSCFG_RCR_PAGE3_Pos (3U) 9724 #define SYSCFG_RCR_PAGE3_Msk (0x1UL << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */ 9725 #define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk /*!< ICODE SRAM Write protection page 3 */ 9726 9727 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 9728 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 9729 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 9730 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 9731 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 9732 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 9733 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 9734 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 9735 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 9736 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 9737 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 9738 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 9739 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 9740 9741 /*!<* 9742 * @brief EXTI0 configuration 9743 */ 9744 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 9745 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 9746 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 9747 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 9748 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 9749 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 9750 9751 /*!<* 9752 * @brief EXTI1 configuration 9753 */ 9754 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 9755 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 9756 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 9757 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 9758 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 9759 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 9760 9761 /*!<* 9762 * @brief EXTI2 configuration 9763 */ 9764 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 9765 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 9766 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 9767 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 9768 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 9769 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 9770 9771 /*!<* 9772 * @brief EXTI3 configuration 9773 */ 9774 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 9775 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 9776 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 9777 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 9778 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 9779 9780 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 9781 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 9782 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 9783 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 9784 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 9785 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 9786 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 9787 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 9788 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 9789 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 9790 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 9791 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 9792 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 9793 9794 /*!<* 9795 * @brief EXTI4 configuration 9796 */ 9797 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 9798 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 9799 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 9800 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 9801 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 9802 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 9803 9804 /*!<* 9805 * @brief EXTI5 configuration 9806 */ 9807 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 9808 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 9809 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 9810 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 9811 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 9812 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 9813 9814 /*!<* 9815 * @brief EXTI6 configuration 9816 */ 9817 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 9818 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 9819 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 9820 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 9821 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 9822 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 9823 9824 /*!<* 9825 * @brief EXTI7 configuration 9826 */ 9827 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 9828 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 9829 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 9830 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 9831 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 9832 9833 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 9834 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 9835 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 9836 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 9837 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 9838 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 9839 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 9840 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 9841 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 9842 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 9843 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 9844 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 9845 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 9846 9847 /*!<* 9848 * @brief EXTI8 configuration 9849 */ 9850 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 9851 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 9852 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 9853 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 9854 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 9855 9856 /*!<* 9857 * @brief EXTI9 configuration 9858 */ 9859 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 9860 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 9861 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 9862 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 9863 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 9864 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 9865 9866 /*!<* 9867 * @brief EXTI10 configuration 9868 */ 9869 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 9870 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 9871 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 9872 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 9873 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 9874 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 9875 9876 /*!<* 9877 * @brief EXTI11 configuration 9878 */ 9879 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 9880 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 9881 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 9882 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 9883 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 9884 9885 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 9886 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 9887 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 9888 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 9889 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 9890 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 9891 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 9892 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 9893 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 9894 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 9895 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 9896 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 9897 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 9898 9899 /*!<* 9900 * @brief EXTI12 configuration 9901 */ 9902 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 9903 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 9904 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 9905 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 9906 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 9907 9908 /*!<* 9909 * @brief EXTI13 configuration 9910 */ 9911 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 9912 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 9913 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 9914 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 9915 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 9916 9917 /*!<* 9918 * @brief EXTI14 configuration 9919 */ 9920 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 9921 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 9922 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 9923 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 9924 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 9925 9926 /*!<* 9927 * @brief EXTI15 configuration 9928 */ 9929 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 9930 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 9931 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 9932 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 9933 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 9934 9935 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 9936 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 9937 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 9938 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */ 9939 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) 9940 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ 9941 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */ 9942 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U) 9943 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */ 9944 #define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the address parity check on RAM */ 9945 #define SYSCFG_CFGR2_SRAM_PE_Pos (8U) 9946 #define SYSCFG_CFGR2_SRAM_PE_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */ 9947 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk /*!< SRAM Parity error flag */ 9948 9949 /***************** Bit definition for SYSCFG_CFGR3 register *****************/ 9950 #define SYSCFG_CFGR3_DMA_RMP_Pos (0U) 9951 #define SYSCFG_CFGR3_DMA_RMP_Msk (0x3FFUL << SYSCFG_CFGR3_DMA_RMP_Pos) /*!< 0x000003FF */ 9952 #define SYSCFG_CFGR3_DMA_RMP SYSCFG_CFGR3_DMA_RMP_Msk /*!< DMA remap mask */ 9953 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos (0U) 9954 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000003 */ 9955 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk /*!< SPI1 RX DMA remap */ 9956 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000001 */ 9957 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos) /*!< 0x00000002 */ 9958 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos (2U) 9959 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x0000000C */ 9960 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk /*!< SPI1 TX DMA remap */ 9961 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000004 */ 9962 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos) /*!< 0x00000008 */ 9963 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos (4U) 9964 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000030 */ 9965 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */ 9966 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000010 */ 9967 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos) /*!< 0x00000020 */ 9968 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos (6U) 9969 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x000000C0 */ 9970 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk /*!< I2C1 RX DMA remap */ 9971 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000040 */ 9972 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos) /*!< 0x00000080 */ 9973 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Pos (8U) 9974 #define SYSCFG_CFGR3_ADC2_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000300 */ 9975 #define SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */ 9976 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */ 9977 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */ 9978 9979 /******************************************************************************/ 9980 /* */ 9981 /* TIM */ 9982 /* */ 9983 /******************************************************************************/ 9984 /******************* Bit definition for TIM_CR1 register ********************/ 9985 #define TIM_CR1_CEN_Pos (0U) 9986 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 9987 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 9988 #define TIM_CR1_UDIS_Pos (1U) 9989 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 9990 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 9991 #define TIM_CR1_URS_Pos (2U) 9992 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 9993 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 9994 #define TIM_CR1_OPM_Pos (3U) 9995 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 9996 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 9997 #define TIM_CR1_DIR_Pos (4U) 9998 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 9999 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 10000 10001 #define TIM_CR1_CMS_Pos (5U) 10002 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 10003 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 10004 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 10005 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 10006 10007 #define TIM_CR1_ARPE_Pos (7U) 10008 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 10009 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 10010 10011 #define TIM_CR1_CKD_Pos (8U) 10012 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 10013 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 10014 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 10015 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 10016 10017 #define TIM_CR1_UIFREMAP_Pos (11U) 10018 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 10019 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 10020 10021 /******************* Bit definition for TIM_CR2 register ********************/ 10022 #define TIM_CR2_CCPC_Pos (0U) 10023 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 10024 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 10025 #define TIM_CR2_CCUS_Pos (2U) 10026 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 10027 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 10028 #define TIM_CR2_CCDS_Pos (3U) 10029 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 10030 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 10031 10032 #define TIM_CR2_MMS_Pos (4U) 10033 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 10034 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 10035 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 10036 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 10037 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 10038 10039 #define TIM_CR2_TI1S_Pos (7U) 10040 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 10041 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 10042 #define TIM_CR2_OIS1_Pos (8U) 10043 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 10044 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 10045 #define TIM_CR2_OIS1N_Pos (9U) 10046 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 10047 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 10048 #define TIM_CR2_OIS2_Pos (10U) 10049 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 10050 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 10051 #define TIM_CR2_OIS2N_Pos (11U) 10052 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 10053 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 10054 #define TIM_CR2_OIS3_Pos (12U) 10055 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 10056 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 10057 #define TIM_CR2_OIS3N_Pos (13U) 10058 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 10059 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 10060 #define TIM_CR2_OIS4_Pos (14U) 10061 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 10062 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 10063 10064 #define TIM_CR2_OIS5_Pos (16U) 10065 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 10066 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */ 10067 #define TIM_CR2_OIS6_Pos (18U) 10068 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 10069 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */ 10070 10071 #define TIM_CR2_MMS2_Pos (20U) 10072 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 10073 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 10074 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 10075 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 10076 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 10077 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 10078 10079 /******************* Bit definition for TIM_SMCR register *******************/ 10080 #define TIM_SMCR_SMS_Pos (0U) 10081 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 10082 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 10083 #define TIM_SMCR_SMS_0 (0x00000001U) /*!<Bit 0 */ 10084 #define TIM_SMCR_SMS_1 (0x00000002U) /*!<Bit 1 */ 10085 #define TIM_SMCR_SMS_2 (0x00000004U) /*!<Bit 2 */ 10086 #define TIM_SMCR_SMS_3 (0x00010000U) /*!<Bit 3 */ 10087 10088 #define TIM_SMCR_OCCS_Pos (3U) 10089 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 10090 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 10091 10092 #define TIM_SMCR_TS_Pos (4U) 10093 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 10094 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 10095 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 10096 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 10097 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 10098 10099 #define TIM_SMCR_MSM_Pos (7U) 10100 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 10101 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 10102 10103 #define TIM_SMCR_ETF_Pos (8U) 10104 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 10105 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 10106 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 10107 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 10108 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 10109 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 10110 10111 #define TIM_SMCR_ETPS_Pos (12U) 10112 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 10113 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 10114 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 10115 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 10116 10117 #define TIM_SMCR_ECE_Pos (14U) 10118 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 10119 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 10120 #define TIM_SMCR_ETP_Pos (15U) 10121 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 10122 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 10123 10124 /******************* Bit definition for TIM_DIER register *******************/ 10125 #define TIM_DIER_UIE_Pos (0U) 10126 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 10127 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 10128 #define TIM_DIER_CC1IE_Pos (1U) 10129 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 10130 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 10131 #define TIM_DIER_CC2IE_Pos (2U) 10132 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 10133 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 10134 #define TIM_DIER_CC3IE_Pos (3U) 10135 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 10136 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 10137 #define TIM_DIER_CC4IE_Pos (4U) 10138 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 10139 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 10140 #define TIM_DIER_COMIE_Pos (5U) 10141 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 10142 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 10143 #define TIM_DIER_TIE_Pos (6U) 10144 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 10145 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 10146 #define TIM_DIER_BIE_Pos (7U) 10147 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 10148 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 10149 #define TIM_DIER_UDE_Pos (8U) 10150 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 10151 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 10152 #define TIM_DIER_CC1DE_Pos (9U) 10153 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 10154 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 10155 #define TIM_DIER_CC2DE_Pos (10U) 10156 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 10157 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 10158 #define TIM_DIER_CC3DE_Pos (11U) 10159 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 10160 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 10161 #define TIM_DIER_CC4DE_Pos (12U) 10162 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 10163 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 10164 #define TIM_DIER_COMDE_Pos (13U) 10165 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 10166 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 10167 #define TIM_DIER_TDE_Pos (14U) 10168 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 10169 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 10170 10171 /******************** Bit definition for TIM_SR register ********************/ 10172 #define TIM_SR_UIF_Pos (0U) 10173 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 10174 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 10175 #define TIM_SR_CC1IF_Pos (1U) 10176 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 10177 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 10178 #define TIM_SR_CC2IF_Pos (2U) 10179 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 10180 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 10181 #define TIM_SR_CC3IF_Pos (3U) 10182 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 10183 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 10184 #define TIM_SR_CC4IF_Pos (4U) 10185 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 10186 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 10187 #define TIM_SR_COMIF_Pos (5U) 10188 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 10189 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 10190 #define TIM_SR_TIF_Pos (6U) 10191 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 10192 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 10193 #define TIM_SR_BIF_Pos (7U) 10194 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 10195 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 10196 #define TIM_SR_B2IF_Pos (8U) 10197 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 10198 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */ 10199 #define TIM_SR_CC1OF_Pos (9U) 10200 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 10201 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 10202 #define TIM_SR_CC2OF_Pos (10U) 10203 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 10204 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 10205 #define TIM_SR_CC3OF_Pos (11U) 10206 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 10207 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 10208 #define TIM_SR_CC4OF_Pos (12U) 10209 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 10210 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 10211 #define TIM_SR_CC5IF_Pos (16U) 10212 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 10213 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 10214 #define TIM_SR_CC6IF_Pos (17U) 10215 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 10216 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 10217 10218 /******************* Bit definition for TIM_EGR register ********************/ 10219 #define TIM_EGR_UG_Pos (0U) 10220 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 10221 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 10222 #define TIM_EGR_CC1G_Pos (1U) 10223 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 10224 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 10225 #define TIM_EGR_CC2G_Pos (2U) 10226 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 10227 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 10228 #define TIM_EGR_CC3G_Pos (3U) 10229 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 10230 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 10231 #define TIM_EGR_CC4G_Pos (4U) 10232 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 10233 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 10234 #define TIM_EGR_COMG_Pos (5U) 10235 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 10236 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 10237 #define TIM_EGR_TG_Pos (6U) 10238 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 10239 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 10240 #define TIM_EGR_BG_Pos (7U) 10241 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 10242 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 10243 #define TIM_EGR_B2G_Pos (8U) 10244 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 10245 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */ 10246 10247 /****************** Bit definition for TIM_CCMR1 register *******************/ 10248 #define TIM_CCMR1_CC1S_Pos (0U) 10249 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 10250 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 10251 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 10252 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 10253 10254 #define TIM_CCMR1_OC1FE_Pos (2U) 10255 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 10256 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 10257 #define TIM_CCMR1_OC1PE_Pos (3U) 10258 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 10259 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 10260 10261 #define TIM_CCMR1_OC1M_Pos (4U) 10262 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 10263 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 10264 #define TIM_CCMR1_OC1M_0 (0x00000010U) /*!<Bit 0 */ 10265 #define TIM_CCMR1_OC1M_1 (0x00000020U) /*!<Bit 1 */ 10266 #define TIM_CCMR1_OC1M_2 (0x00000040U) /*!<Bit 2 */ 10267 #define TIM_CCMR1_OC1M_3 (0x00010000U) /*!<Bit 3 */ 10268 10269 #define TIM_CCMR1_OC1CE_Pos (7U) 10270 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 10271 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 10272 10273 #define TIM_CCMR1_CC2S_Pos (8U) 10274 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 10275 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 10276 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 10277 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 10278 10279 #define TIM_CCMR1_OC2FE_Pos (10U) 10280 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 10281 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 10282 #define TIM_CCMR1_OC2PE_Pos (11U) 10283 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 10284 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 10285 10286 #define TIM_CCMR1_OC2M_Pos (12U) 10287 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 10288 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 10289 #define TIM_CCMR1_OC2M_0 (0x00001000U) /*!<Bit 0 */ 10290 #define TIM_CCMR1_OC2M_1 (0x00002000U) /*!<Bit 1 */ 10291 #define TIM_CCMR1_OC2M_2 (0x00004000U) /*!<Bit 2 */ 10292 #define TIM_CCMR1_OC2M_3 (0x01000000U) /*!<Bit 3 */ 10293 10294 #define TIM_CCMR1_OC2CE_Pos (15U) 10295 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 10296 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 10297 10298 /*----------------------------------------------------------------------------*/ 10299 10300 #define TIM_CCMR1_IC1PSC_Pos (2U) 10301 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 10302 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 10303 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 10304 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 10305 10306 #define TIM_CCMR1_IC1F_Pos (4U) 10307 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 10308 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 10309 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 10310 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 10311 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 10312 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 10313 10314 #define TIM_CCMR1_IC2PSC_Pos (10U) 10315 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 10316 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 10317 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 10318 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 10319 10320 #define TIM_CCMR1_IC2F_Pos (12U) 10321 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 10322 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 10323 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 10324 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 10325 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 10326 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 10327 10328 /****************** Bit definition for TIM_CCMR2 register *******************/ 10329 #define TIM_CCMR2_CC3S_Pos (0U) 10330 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 10331 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 10332 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 10333 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 10334 10335 #define TIM_CCMR2_OC3FE_Pos (2U) 10336 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 10337 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 10338 #define TIM_CCMR2_OC3PE_Pos (3U) 10339 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 10340 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 10341 10342 #define TIM_CCMR2_OC3M_Pos (4U) 10343 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 10344 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 10345 #define TIM_CCMR2_OC3M_0 (0x00000010U) /*!<Bit 0 */ 10346 #define TIM_CCMR2_OC3M_1 (0x00000020U) /*!<Bit 1 */ 10347 #define TIM_CCMR2_OC3M_2 (0x00000040U) /*!<Bit 2 */ 10348 #define TIM_CCMR2_OC3M_3 (0x00010000U) /*!<Bit 3 */ 10349 10350 #define TIM_CCMR2_OC3CE_Pos (7U) 10351 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 10352 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 10353 10354 #define TIM_CCMR2_CC4S_Pos (8U) 10355 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 10356 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 10357 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 10358 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 10359 10360 #define TIM_CCMR2_OC4FE_Pos (10U) 10361 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 10362 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 10363 #define TIM_CCMR2_OC4PE_Pos (11U) 10364 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 10365 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 10366 10367 #define TIM_CCMR2_OC4M_Pos (12U) 10368 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 10369 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 10370 #define TIM_CCMR2_OC4M_0 (0x00001000U) /*!<Bit 0 */ 10371 #define TIM_CCMR2_OC4M_1 (0x00002000U) /*!<Bit 1 */ 10372 #define TIM_CCMR2_OC4M_2 (0x00004000U) /*!<Bit 2 */ 10373 #define TIM_CCMR2_OC4M_3 (0x01000000U) /*!<Bit 3 */ 10374 10375 #define TIM_CCMR2_OC4CE_Pos (15U) 10376 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 10377 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 10378 10379 /*----------------------------------------------------------------------------*/ 10380 10381 #define TIM_CCMR2_IC3PSC_Pos (2U) 10382 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 10383 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 10384 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 10385 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 10386 10387 #define TIM_CCMR2_IC3F_Pos (4U) 10388 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 10389 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 10390 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 10391 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 10392 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 10393 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 10394 10395 #define TIM_CCMR2_IC4PSC_Pos (10U) 10396 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 10397 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 10398 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 10399 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 10400 10401 #define TIM_CCMR2_IC4F_Pos (12U) 10402 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 10403 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 10404 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 10405 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 10406 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 10407 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 10408 10409 /******************* Bit definition for TIM_CCER register *******************/ 10410 #define TIM_CCER_CC1E_Pos (0U) 10411 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 10412 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 10413 #define TIM_CCER_CC1P_Pos (1U) 10414 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 10415 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 10416 #define TIM_CCER_CC1NE_Pos (2U) 10417 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 10418 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 10419 #define TIM_CCER_CC1NP_Pos (3U) 10420 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 10421 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 10422 #define TIM_CCER_CC2E_Pos (4U) 10423 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 10424 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 10425 #define TIM_CCER_CC2P_Pos (5U) 10426 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 10427 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 10428 #define TIM_CCER_CC2NE_Pos (6U) 10429 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 10430 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 10431 #define TIM_CCER_CC2NP_Pos (7U) 10432 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 10433 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 10434 #define TIM_CCER_CC3E_Pos (8U) 10435 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 10436 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 10437 #define TIM_CCER_CC3P_Pos (9U) 10438 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 10439 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 10440 #define TIM_CCER_CC3NE_Pos (10U) 10441 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 10442 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 10443 #define TIM_CCER_CC3NP_Pos (11U) 10444 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 10445 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 10446 #define TIM_CCER_CC4E_Pos (12U) 10447 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 10448 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 10449 #define TIM_CCER_CC4P_Pos (13U) 10450 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 10451 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 10452 #define TIM_CCER_CC4NP_Pos (15U) 10453 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 10454 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 10455 #define TIM_CCER_CC5E_Pos (16U) 10456 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 10457 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 10458 #define TIM_CCER_CC5P_Pos (17U) 10459 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 10460 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 10461 #define TIM_CCER_CC6E_Pos (20U) 10462 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 10463 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 10464 #define TIM_CCER_CC6P_Pos (21U) 10465 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 10466 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 10467 10468 /******************* Bit definition for TIM_CNT register ********************/ 10469 #define TIM_CNT_CNT_Pos (0U) 10470 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 10471 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 10472 #define TIM_CNT_UIFCPY_Pos (31U) 10473 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 10474 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */ 10475 10476 /******************* Bit definition for TIM_PSC register ********************/ 10477 #define TIM_PSC_PSC_Pos (0U) 10478 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 10479 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 10480 10481 /******************* Bit definition for TIM_ARR register ********************/ 10482 #define TIM_ARR_ARR_Pos (0U) 10483 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 10484 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 10485 10486 /******************* Bit definition for TIM_RCR register ********************/ 10487 #define TIM_RCR_REP_Pos (0U) 10488 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 10489 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 10490 10491 /******************* Bit definition for TIM_CCR1 register *******************/ 10492 #define TIM_CCR1_CCR1_Pos (0U) 10493 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 10494 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 10495 10496 /******************* Bit definition for TIM_CCR2 register *******************/ 10497 #define TIM_CCR2_CCR2_Pos (0U) 10498 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 10499 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 10500 10501 /******************* Bit definition for TIM_CCR3 register *******************/ 10502 #define TIM_CCR3_CCR3_Pos (0U) 10503 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 10504 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 10505 10506 /******************* Bit definition for TIM_CCR4 register *******************/ 10507 #define TIM_CCR4_CCR4_Pos (0U) 10508 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 10509 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 10510 10511 /******************* Bit definition for TIM_CCR5 register *******************/ 10512 #define TIM_CCR5_CCR5_Pos (0U) 10513 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 10514 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 10515 #define TIM_CCR5_GC5C1_Pos (29U) 10516 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 10517 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 10518 #define TIM_CCR5_GC5C2_Pos (30U) 10519 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 10520 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 10521 #define TIM_CCR5_GC5C3_Pos (31U) 10522 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 10523 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 10524 10525 /******************* Bit definition for TIM_CCR6 register *******************/ 10526 #define TIM_CCR6_CCR6_Pos (0U) 10527 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 10528 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 10529 10530 /******************* Bit definition for TIM_BDTR register *******************/ 10531 #define TIM_BDTR_DTG_Pos (0U) 10532 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 10533 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 10534 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 10535 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 10536 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 10537 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 10538 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 10539 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 10540 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 10541 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 10542 10543 #define TIM_BDTR_LOCK_Pos (8U) 10544 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 10545 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 10546 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 10547 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 10548 10549 #define TIM_BDTR_OSSI_Pos (10U) 10550 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 10551 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 10552 #define TIM_BDTR_OSSR_Pos (11U) 10553 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 10554 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 10555 #define TIM_BDTR_BKE_Pos (12U) 10556 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 10557 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */ 10558 #define TIM_BDTR_BKP_Pos (13U) 10559 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 10560 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */ 10561 #define TIM_BDTR_AOE_Pos (14U) 10562 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 10563 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 10564 #define TIM_BDTR_MOE_Pos (15U) 10565 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 10566 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 10567 10568 #define TIM_BDTR_BKF_Pos (16U) 10569 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 10570 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */ 10571 #define TIM_BDTR_BK2F_Pos (20U) 10572 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 10573 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */ 10574 10575 #define TIM_BDTR_BK2E_Pos (24U) 10576 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 10577 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */ 10578 #define TIM_BDTR_BK2P_Pos (25U) 10579 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 10580 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */ 10581 10582 /******************* Bit definition for TIM_DCR register ********************/ 10583 #define TIM_DCR_DBA_Pos (0U) 10584 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 10585 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 10586 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 10587 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 10588 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 10589 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 10590 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 10591 10592 #define TIM_DCR_DBL_Pos (8U) 10593 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 10594 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 10595 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 10596 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 10597 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 10598 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 10599 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 10600 10601 /******************* Bit definition for TIM_DMAR register *******************/ 10602 #define TIM_DMAR_DMAB_Pos (0U) 10603 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 10604 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 10605 10606 /******************* Bit definition for TIM16_OR register *********************/ 10607 #define TIM16_OR_TI1_RMP_Pos (0U) 10608 #define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 10609 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ 10610 #define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 10611 #define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 10612 10613 /******************* Bit definition for TIM1_OR register *********************/ 10614 #define TIM1_OR_ETR_RMP_Pos (0U) 10615 #define TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos) /*!< 0x0000000F */ 10616 #define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ 10617 #define TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 10618 #define TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 10619 #define TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 10620 #define TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos) /*!< 0x00000008 */ 10621 10622 /****************** Bit definition for TIM_CCMR3 register *******************/ 10623 #define TIM_CCMR3_OC5FE_Pos (2U) 10624 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 10625 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 10626 #define TIM_CCMR3_OC5PE_Pos (3U) 10627 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 10628 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 10629 10630 #define TIM_CCMR3_OC5M_Pos (4U) 10631 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 10632 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ 10633 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 10634 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 10635 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 10636 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 10637 10638 #define TIM_CCMR3_OC5CE_Pos (7U) 10639 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 10640 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 10641 10642 #define TIM_CCMR3_OC6FE_Pos (10U) 10643 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 10644 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 10645 #define TIM_CCMR3_OC6PE_Pos (11U) 10646 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 10647 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 10648 10649 #define TIM_CCMR3_OC6M_Pos (12U) 10650 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 10651 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[2:0] bits (Output Compare 6 Mode) */ 10652 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 10653 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 10654 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 10655 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 10656 10657 #define TIM_CCMR3_OC6CE_Pos (15U) 10658 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 10659 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 10660 10661 /******************************************************************************/ 10662 /* */ 10663 /* Touch Sensing Controller (TSC) */ 10664 /* */ 10665 /******************************************************************************/ 10666 /******************* Bit definition for TSC_CR register *********************/ 10667 #define TSC_CR_TSCE_Pos (0U) 10668 #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ 10669 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ 10670 #define TSC_CR_START_Pos (1U) 10671 #define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */ 10672 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ 10673 #define TSC_CR_AM_Pos (2U) 10674 #define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */ 10675 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ 10676 #define TSC_CR_SYNCPOL_Pos (3U) 10677 #define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ 10678 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ 10679 #define TSC_CR_IODEF_Pos (4U) 10680 #define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ 10681 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ 10682 10683 #define TSC_CR_MCV_Pos (5U) 10684 #define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ 10685 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ 10686 #define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */ 10687 #define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */ 10688 #define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */ 10689 10690 #define TSC_CR_PGPSC_Pos (12U) 10691 #define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ 10692 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ 10693 #define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ 10694 #define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ 10695 #define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ 10696 10697 #define TSC_CR_SSPSC_Pos (15U) 10698 #define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ 10699 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ 10700 #define TSC_CR_SSE_Pos (16U) 10701 #define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */ 10702 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ 10703 10704 #define TSC_CR_SSD_Pos (17U) 10705 #define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ 10706 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ 10707 #define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */ 10708 #define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */ 10709 #define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */ 10710 #define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */ 10711 #define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */ 10712 #define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */ 10713 #define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */ 10714 10715 #define TSC_CR_CTPL_Pos (24U) 10716 #define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ 10717 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ 10718 #define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ 10719 #define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ 10720 #define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ 10721 #define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ 10722 10723 #define TSC_CR_CTPH_Pos (28U) 10724 #define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ 10725 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ 10726 #define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ 10727 #define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ 10728 #define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ 10729 #define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ 10730 10731 /******************* Bit definition for TSC_IER register ********************/ 10732 #define TSC_IER_EOAIE_Pos (0U) 10733 #define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ 10734 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ 10735 #define TSC_IER_MCEIE_Pos (1U) 10736 #define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ 10737 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ 10738 10739 /******************* Bit definition for TSC_ICR register ********************/ 10740 #define TSC_ICR_EOAIC_Pos (0U) 10741 #define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ 10742 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ 10743 #define TSC_ICR_MCEIC_Pos (1U) 10744 #define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ 10745 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ 10746 10747 /******************* Bit definition for TSC_ISR register ********************/ 10748 #define TSC_ISR_EOAF_Pos (0U) 10749 #define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ 10750 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ 10751 #define TSC_ISR_MCEF_Pos (1U) 10752 #define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ 10753 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ 10754 10755 /******************* Bit definition for TSC_IOHCR register ******************/ 10756 #define TSC_IOHCR_G1_IO1_Pos (0U) 10757 #define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ 10758 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ 10759 #define TSC_IOHCR_G1_IO2_Pos (1U) 10760 #define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ 10761 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ 10762 #define TSC_IOHCR_G1_IO3_Pos (2U) 10763 #define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ 10764 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ 10765 #define TSC_IOHCR_G1_IO4_Pos (3U) 10766 #define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ 10767 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ 10768 #define TSC_IOHCR_G2_IO1_Pos (4U) 10769 #define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ 10770 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ 10771 #define TSC_IOHCR_G2_IO2_Pos (5U) 10772 #define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ 10773 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ 10774 #define TSC_IOHCR_G2_IO3_Pos (6U) 10775 #define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ 10776 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ 10777 #define TSC_IOHCR_G2_IO4_Pos (7U) 10778 #define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ 10779 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ 10780 #define TSC_IOHCR_G3_IO1_Pos (8U) 10781 #define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ 10782 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ 10783 #define TSC_IOHCR_G3_IO2_Pos (9U) 10784 #define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ 10785 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ 10786 #define TSC_IOHCR_G3_IO3_Pos (10U) 10787 #define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ 10788 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ 10789 #define TSC_IOHCR_G3_IO4_Pos (11U) 10790 #define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ 10791 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ 10792 #define TSC_IOHCR_G4_IO1_Pos (12U) 10793 #define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ 10794 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ 10795 #define TSC_IOHCR_G4_IO2_Pos (13U) 10796 #define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ 10797 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ 10798 #define TSC_IOHCR_G4_IO3_Pos (14U) 10799 #define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ 10800 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ 10801 #define TSC_IOHCR_G4_IO4_Pos (15U) 10802 #define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ 10803 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ 10804 #define TSC_IOHCR_G5_IO1_Pos (16U) 10805 #define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ 10806 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ 10807 #define TSC_IOHCR_G5_IO2_Pos (17U) 10808 #define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ 10809 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ 10810 #define TSC_IOHCR_G5_IO3_Pos (18U) 10811 #define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ 10812 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ 10813 #define TSC_IOHCR_G5_IO4_Pos (19U) 10814 #define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ 10815 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ 10816 #define TSC_IOHCR_G6_IO1_Pos (20U) 10817 #define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ 10818 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ 10819 #define TSC_IOHCR_G6_IO2_Pos (21U) 10820 #define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ 10821 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ 10822 #define TSC_IOHCR_G6_IO3_Pos (22U) 10823 #define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ 10824 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ 10825 #define TSC_IOHCR_G6_IO4_Pos (23U) 10826 #define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ 10827 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ 10828 #define TSC_IOHCR_G7_IO1_Pos (24U) 10829 #define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ 10830 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ 10831 #define TSC_IOHCR_G7_IO2_Pos (25U) 10832 #define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ 10833 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ 10834 #define TSC_IOHCR_G7_IO3_Pos (26U) 10835 #define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ 10836 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ 10837 #define TSC_IOHCR_G7_IO4_Pos (27U) 10838 #define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ 10839 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ 10840 #define TSC_IOHCR_G8_IO1_Pos (28U) 10841 #define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ 10842 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ 10843 #define TSC_IOHCR_G8_IO2_Pos (29U) 10844 #define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ 10845 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ 10846 #define TSC_IOHCR_G8_IO3_Pos (30U) 10847 #define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ 10848 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ 10849 #define TSC_IOHCR_G8_IO4_Pos (31U) 10850 #define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ 10851 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ 10852 10853 /******************* Bit definition for TSC_IOASCR register *****************/ 10854 #define TSC_IOASCR_G1_IO1_Pos (0U) 10855 #define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ 10856 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ 10857 #define TSC_IOASCR_G1_IO2_Pos (1U) 10858 #define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ 10859 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ 10860 #define TSC_IOASCR_G1_IO3_Pos (2U) 10861 #define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ 10862 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ 10863 #define TSC_IOASCR_G1_IO4_Pos (3U) 10864 #define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ 10865 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ 10866 #define TSC_IOASCR_G2_IO1_Pos (4U) 10867 #define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ 10868 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ 10869 #define TSC_IOASCR_G2_IO2_Pos (5U) 10870 #define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ 10871 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ 10872 #define TSC_IOASCR_G2_IO3_Pos (6U) 10873 #define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ 10874 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ 10875 #define TSC_IOASCR_G2_IO4_Pos (7U) 10876 #define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ 10877 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ 10878 #define TSC_IOASCR_G3_IO1_Pos (8U) 10879 #define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ 10880 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ 10881 #define TSC_IOASCR_G3_IO2_Pos (9U) 10882 #define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ 10883 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ 10884 #define TSC_IOASCR_G3_IO3_Pos (10U) 10885 #define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ 10886 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ 10887 #define TSC_IOASCR_G3_IO4_Pos (11U) 10888 #define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ 10889 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ 10890 #define TSC_IOASCR_G4_IO1_Pos (12U) 10891 #define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ 10892 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ 10893 #define TSC_IOASCR_G4_IO2_Pos (13U) 10894 #define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ 10895 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ 10896 #define TSC_IOASCR_G4_IO3_Pos (14U) 10897 #define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ 10898 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ 10899 #define TSC_IOASCR_G4_IO4_Pos (15U) 10900 #define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ 10901 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ 10902 #define TSC_IOASCR_G5_IO1_Pos (16U) 10903 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ 10904 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ 10905 #define TSC_IOASCR_G5_IO2_Pos (17U) 10906 #define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ 10907 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ 10908 #define TSC_IOASCR_G5_IO3_Pos (18U) 10909 #define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ 10910 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ 10911 #define TSC_IOASCR_G5_IO4_Pos (19U) 10912 #define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ 10913 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ 10914 #define TSC_IOASCR_G6_IO1_Pos (20U) 10915 #define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ 10916 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ 10917 #define TSC_IOASCR_G6_IO2_Pos (21U) 10918 #define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ 10919 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ 10920 #define TSC_IOASCR_G6_IO3_Pos (22U) 10921 #define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ 10922 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ 10923 #define TSC_IOASCR_G6_IO4_Pos (23U) 10924 #define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ 10925 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ 10926 #define TSC_IOASCR_G7_IO1_Pos (24U) 10927 #define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ 10928 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ 10929 #define TSC_IOASCR_G7_IO2_Pos (25U) 10930 #define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ 10931 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ 10932 #define TSC_IOASCR_G7_IO3_Pos (26U) 10933 #define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ 10934 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ 10935 #define TSC_IOASCR_G7_IO4_Pos (27U) 10936 #define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ 10937 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ 10938 #define TSC_IOASCR_G8_IO1_Pos (28U) 10939 #define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ 10940 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ 10941 #define TSC_IOASCR_G8_IO2_Pos (29U) 10942 #define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ 10943 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ 10944 #define TSC_IOASCR_G8_IO3_Pos (30U) 10945 #define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ 10946 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ 10947 #define TSC_IOASCR_G8_IO4_Pos (31U) 10948 #define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ 10949 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ 10950 10951 /******************* Bit definition for TSC_IOSCR register ******************/ 10952 #define TSC_IOSCR_G1_IO1_Pos (0U) 10953 #define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ 10954 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ 10955 #define TSC_IOSCR_G1_IO2_Pos (1U) 10956 #define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ 10957 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ 10958 #define TSC_IOSCR_G1_IO3_Pos (2U) 10959 #define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ 10960 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ 10961 #define TSC_IOSCR_G1_IO4_Pos (3U) 10962 #define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ 10963 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ 10964 #define TSC_IOSCR_G2_IO1_Pos (4U) 10965 #define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ 10966 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ 10967 #define TSC_IOSCR_G2_IO2_Pos (5U) 10968 #define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ 10969 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ 10970 #define TSC_IOSCR_G2_IO3_Pos (6U) 10971 #define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ 10972 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ 10973 #define TSC_IOSCR_G2_IO4_Pos (7U) 10974 #define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ 10975 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ 10976 #define TSC_IOSCR_G3_IO1_Pos (8U) 10977 #define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ 10978 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ 10979 #define TSC_IOSCR_G3_IO2_Pos (9U) 10980 #define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ 10981 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ 10982 #define TSC_IOSCR_G3_IO3_Pos (10U) 10983 #define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ 10984 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ 10985 #define TSC_IOSCR_G3_IO4_Pos (11U) 10986 #define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ 10987 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ 10988 #define TSC_IOSCR_G4_IO1_Pos (12U) 10989 #define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ 10990 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ 10991 #define TSC_IOSCR_G4_IO2_Pos (13U) 10992 #define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ 10993 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ 10994 #define TSC_IOSCR_G4_IO3_Pos (14U) 10995 #define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ 10996 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ 10997 #define TSC_IOSCR_G4_IO4_Pos (15U) 10998 #define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ 10999 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ 11000 #define TSC_IOSCR_G5_IO1_Pos (16U) 11001 #define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ 11002 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ 11003 #define TSC_IOSCR_G5_IO2_Pos (17U) 11004 #define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ 11005 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ 11006 #define TSC_IOSCR_G5_IO3_Pos (18U) 11007 #define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ 11008 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ 11009 #define TSC_IOSCR_G5_IO4_Pos (19U) 11010 #define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ 11011 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ 11012 #define TSC_IOSCR_G6_IO1_Pos (20U) 11013 #define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ 11014 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ 11015 #define TSC_IOSCR_G6_IO2_Pos (21U) 11016 #define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ 11017 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ 11018 #define TSC_IOSCR_G6_IO3_Pos (22U) 11019 #define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ 11020 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ 11021 #define TSC_IOSCR_G6_IO4_Pos (23U) 11022 #define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ 11023 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ 11024 #define TSC_IOSCR_G7_IO1_Pos (24U) 11025 #define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ 11026 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ 11027 #define TSC_IOSCR_G7_IO2_Pos (25U) 11028 #define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ 11029 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ 11030 #define TSC_IOSCR_G7_IO3_Pos (26U) 11031 #define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ 11032 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ 11033 #define TSC_IOSCR_G7_IO4_Pos (27U) 11034 #define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ 11035 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ 11036 #define TSC_IOSCR_G8_IO1_Pos (28U) 11037 #define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ 11038 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ 11039 #define TSC_IOSCR_G8_IO2_Pos (29U) 11040 #define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ 11041 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ 11042 #define TSC_IOSCR_G8_IO3_Pos (30U) 11043 #define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ 11044 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ 11045 #define TSC_IOSCR_G8_IO4_Pos (31U) 11046 #define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ 11047 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ 11048 11049 /******************* Bit definition for TSC_IOCCR register ******************/ 11050 #define TSC_IOCCR_G1_IO1_Pos (0U) 11051 #define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ 11052 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ 11053 #define TSC_IOCCR_G1_IO2_Pos (1U) 11054 #define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ 11055 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ 11056 #define TSC_IOCCR_G1_IO3_Pos (2U) 11057 #define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ 11058 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ 11059 #define TSC_IOCCR_G1_IO4_Pos (3U) 11060 #define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ 11061 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ 11062 #define TSC_IOCCR_G2_IO1_Pos (4U) 11063 #define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ 11064 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ 11065 #define TSC_IOCCR_G2_IO2_Pos (5U) 11066 #define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ 11067 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ 11068 #define TSC_IOCCR_G2_IO3_Pos (6U) 11069 #define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ 11070 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ 11071 #define TSC_IOCCR_G2_IO4_Pos (7U) 11072 #define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ 11073 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ 11074 #define TSC_IOCCR_G3_IO1_Pos (8U) 11075 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ 11076 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ 11077 #define TSC_IOCCR_G3_IO2_Pos (9U) 11078 #define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ 11079 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ 11080 #define TSC_IOCCR_G3_IO3_Pos (10U) 11081 #define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ 11082 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ 11083 #define TSC_IOCCR_G3_IO4_Pos (11U) 11084 #define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ 11085 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ 11086 #define TSC_IOCCR_G4_IO1_Pos (12U) 11087 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ 11088 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ 11089 #define TSC_IOCCR_G4_IO2_Pos (13U) 11090 #define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ 11091 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ 11092 #define TSC_IOCCR_G4_IO3_Pos (14U) 11093 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ 11094 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ 11095 #define TSC_IOCCR_G4_IO4_Pos (15U) 11096 #define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ 11097 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ 11098 #define TSC_IOCCR_G5_IO1_Pos (16U) 11099 #define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ 11100 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ 11101 #define TSC_IOCCR_G5_IO2_Pos (17U) 11102 #define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ 11103 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ 11104 #define TSC_IOCCR_G5_IO3_Pos (18U) 11105 #define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ 11106 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ 11107 #define TSC_IOCCR_G5_IO4_Pos (19U) 11108 #define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ 11109 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ 11110 #define TSC_IOCCR_G6_IO1_Pos (20U) 11111 #define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ 11112 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ 11113 #define TSC_IOCCR_G6_IO2_Pos (21U) 11114 #define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ 11115 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ 11116 #define TSC_IOCCR_G6_IO3_Pos (22U) 11117 #define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ 11118 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ 11119 #define TSC_IOCCR_G6_IO4_Pos (23U) 11120 #define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ 11121 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ 11122 #define TSC_IOCCR_G7_IO1_Pos (24U) 11123 #define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ 11124 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ 11125 #define TSC_IOCCR_G7_IO2_Pos (25U) 11126 #define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ 11127 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ 11128 #define TSC_IOCCR_G7_IO3_Pos (26U) 11129 #define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ 11130 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ 11131 #define TSC_IOCCR_G7_IO4_Pos (27U) 11132 #define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ 11133 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ 11134 #define TSC_IOCCR_G8_IO1_Pos (28U) 11135 #define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ 11136 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ 11137 #define TSC_IOCCR_G8_IO2_Pos (29U) 11138 #define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ 11139 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ 11140 #define TSC_IOCCR_G8_IO3_Pos (30U) 11141 #define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ 11142 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ 11143 #define TSC_IOCCR_G8_IO4_Pos (31U) 11144 #define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ 11145 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ 11146 11147 /******************* Bit definition for TSC_IOGCSR register *****************/ 11148 #define TSC_IOGCSR_G1E_Pos (0U) 11149 #define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ 11150 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ 11151 #define TSC_IOGCSR_G2E_Pos (1U) 11152 #define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ 11153 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ 11154 #define TSC_IOGCSR_G3E_Pos (2U) 11155 #define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ 11156 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ 11157 #define TSC_IOGCSR_G4E_Pos (3U) 11158 #define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ 11159 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ 11160 #define TSC_IOGCSR_G5E_Pos (4U) 11161 #define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ 11162 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ 11163 #define TSC_IOGCSR_G6E_Pos (5U) 11164 #define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ 11165 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ 11166 #define TSC_IOGCSR_G7E_Pos (6U) 11167 #define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ 11168 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ 11169 #define TSC_IOGCSR_G8E_Pos (7U) 11170 #define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ 11171 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ 11172 #define TSC_IOGCSR_G1S_Pos (16U) 11173 #define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ 11174 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ 11175 #define TSC_IOGCSR_G2S_Pos (17U) 11176 #define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ 11177 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ 11178 #define TSC_IOGCSR_G3S_Pos (18U) 11179 #define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ 11180 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ 11181 #define TSC_IOGCSR_G4S_Pos (19U) 11182 #define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ 11183 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ 11184 #define TSC_IOGCSR_G5S_Pos (20U) 11185 #define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ 11186 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ 11187 #define TSC_IOGCSR_G6S_Pos (21U) 11188 #define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ 11189 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ 11190 #define TSC_IOGCSR_G7S_Pos (22U) 11191 #define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ 11192 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ 11193 #define TSC_IOGCSR_G8S_Pos (23U) 11194 #define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ 11195 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ 11196 11197 /******************* Bit definition for TSC_IOGXCR register *****************/ 11198 #define TSC_IOGXCR_CNT_Pos (0U) 11199 #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ 11200 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ 11201 11202 /******************************************************************************/ 11203 /* */ 11204 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 11205 /* */ 11206 /******************************************************************************/ 11207 11208 /* 11209 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series) 11210 */ 11211 11212 /* Support of 7 bits data length feature */ 11213 #define USART_7BITS_SUPPORT 11214 11215 /****************** Bit definition for USART_CR1 register *******************/ 11216 #define USART_CR1_UE_Pos (0U) 11217 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 11218 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 11219 #define USART_CR1_UESM_Pos (1U) 11220 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 11221 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 11222 #define USART_CR1_RE_Pos (2U) 11223 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 11224 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 11225 #define USART_CR1_TE_Pos (3U) 11226 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 11227 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 11228 #define USART_CR1_IDLEIE_Pos (4U) 11229 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 11230 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 11231 #define USART_CR1_RXNEIE_Pos (5U) 11232 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 11233 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 11234 #define USART_CR1_TCIE_Pos (6U) 11235 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 11236 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 11237 #define USART_CR1_TXEIE_Pos (7U) 11238 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 11239 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 11240 #define USART_CR1_PEIE_Pos (8U) 11241 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 11242 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 11243 #define USART_CR1_PS_Pos (9U) 11244 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 11245 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 11246 #define USART_CR1_PCE_Pos (10U) 11247 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 11248 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 11249 #define USART_CR1_WAKE_Pos (11U) 11250 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 11251 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 11252 #define USART_CR1_M0_Pos (12U) 11253 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 11254 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */ 11255 #define USART_CR1_MME_Pos (13U) 11256 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 11257 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 11258 #define USART_CR1_CMIE_Pos (14U) 11259 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 11260 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 11261 #define USART_CR1_OVER8_Pos (15U) 11262 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 11263 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 11264 #define USART_CR1_DEDT_Pos (16U) 11265 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 11266 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 11267 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 11268 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 11269 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 11270 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 11271 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 11272 #define USART_CR1_DEAT_Pos (21U) 11273 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 11274 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 11275 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 11276 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 11277 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 11278 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 11279 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 11280 #define USART_CR1_RTOIE_Pos (26U) 11281 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 11282 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 11283 #define USART_CR1_EOBIE_Pos (27U) 11284 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 11285 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 11286 #define USART_CR1_M1_Pos (28U) 11287 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 11288 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */ 11289 #define USART_CR1_M_Pos (12U) 11290 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 11291 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */ 11292 11293 /****************** Bit definition for USART_CR2 register *******************/ 11294 #define USART_CR2_ADDM7_Pos (4U) 11295 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 11296 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 11297 #define USART_CR2_LBDL_Pos (5U) 11298 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 11299 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 11300 #define USART_CR2_LBDIE_Pos (6U) 11301 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 11302 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 11303 #define USART_CR2_LBCL_Pos (8U) 11304 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 11305 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 11306 #define USART_CR2_CPHA_Pos (9U) 11307 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 11308 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 11309 #define USART_CR2_CPOL_Pos (10U) 11310 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 11311 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 11312 #define USART_CR2_CLKEN_Pos (11U) 11313 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 11314 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 11315 #define USART_CR2_STOP_Pos (12U) 11316 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 11317 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 11318 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 11319 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 11320 #define USART_CR2_LINEN_Pos (14U) 11321 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 11322 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 11323 #define USART_CR2_SWAP_Pos (15U) 11324 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 11325 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 11326 #define USART_CR2_RXINV_Pos (16U) 11327 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 11328 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 11329 #define USART_CR2_TXINV_Pos (17U) 11330 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 11331 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 11332 #define USART_CR2_DATAINV_Pos (18U) 11333 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 11334 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 11335 #define USART_CR2_MSBFIRST_Pos (19U) 11336 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 11337 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 11338 #define USART_CR2_ABREN_Pos (20U) 11339 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 11340 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 11341 #define USART_CR2_ABRMODE_Pos (21U) 11342 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 11343 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 11344 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 11345 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 11346 #define USART_CR2_RTOEN_Pos (23U) 11347 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 11348 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 11349 #define USART_CR2_ADD_Pos (24U) 11350 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 11351 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 11352 11353 /****************** Bit definition for USART_CR3 register *******************/ 11354 #define USART_CR3_EIE_Pos (0U) 11355 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 11356 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 11357 #define USART_CR3_IREN_Pos (1U) 11358 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 11359 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 11360 #define USART_CR3_IRLP_Pos (2U) 11361 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 11362 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 11363 #define USART_CR3_HDSEL_Pos (3U) 11364 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 11365 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 11366 #define USART_CR3_NACK_Pos (4U) 11367 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 11368 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 11369 #define USART_CR3_SCEN_Pos (5U) 11370 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 11371 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 11372 #define USART_CR3_DMAR_Pos (6U) 11373 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 11374 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 11375 #define USART_CR3_DMAT_Pos (7U) 11376 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 11377 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 11378 #define USART_CR3_RTSE_Pos (8U) 11379 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 11380 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 11381 #define USART_CR3_CTSE_Pos (9U) 11382 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 11383 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 11384 #define USART_CR3_CTSIE_Pos (10U) 11385 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 11386 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 11387 #define USART_CR3_ONEBIT_Pos (11U) 11388 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 11389 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 11390 #define USART_CR3_OVRDIS_Pos (12U) 11391 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 11392 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 11393 #define USART_CR3_DDRE_Pos (13U) 11394 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 11395 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 11396 #define USART_CR3_DEM_Pos (14U) 11397 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 11398 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 11399 #define USART_CR3_DEP_Pos (15U) 11400 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 11401 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 11402 #define USART_CR3_SCARCNT_Pos (17U) 11403 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 11404 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 11405 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 11406 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 11407 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 11408 #define USART_CR3_WUS_Pos (20U) 11409 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 11410 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 11411 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 11412 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 11413 #define USART_CR3_WUFIE_Pos (22U) 11414 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 11415 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 11416 11417 /****************** Bit definition for USART_BRR register *******************/ 11418 #define USART_BRR_DIV_FRACTION_Pos (0U) 11419 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 11420 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 11421 #define USART_BRR_DIV_MANTISSA_Pos (4U) 11422 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 11423 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 11424 11425 /****************** Bit definition for USART_GTPR register ******************/ 11426 #define USART_GTPR_PSC_Pos (0U) 11427 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 11428 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 11429 #define USART_GTPR_GT_Pos (8U) 11430 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 11431 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 11432 11433 11434 /******************* Bit definition for USART_RTOR register *****************/ 11435 #define USART_RTOR_RTO_Pos (0U) 11436 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 11437 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 11438 #define USART_RTOR_BLEN_Pos (24U) 11439 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 11440 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 11441 11442 /******************* Bit definition for USART_RQR register ******************/ 11443 #define USART_RQR_ABRRQ_Pos (0U) 11444 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 11445 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 11446 #define USART_RQR_SBKRQ_Pos (1U) 11447 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 11448 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 11449 #define USART_RQR_MMRQ_Pos (2U) 11450 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 11451 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 11452 #define USART_RQR_RXFRQ_Pos (3U) 11453 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 11454 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 11455 #define USART_RQR_TXFRQ_Pos (4U) 11456 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 11457 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 11458 11459 /******************* Bit definition for USART_ISR register ******************/ 11460 #define USART_ISR_PE_Pos (0U) 11461 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 11462 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 11463 #define USART_ISR_FE_Pos (1U) 11464 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 11465 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 11466 #define USART_ISR_NE_Pos (2U) 11467 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 11468 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 11469 #define USART_ISR_ORE_Pos (3U) 11470 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 11471 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 11472 #define USART_ISR_IDLE_Pos (4U) 11473 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 11474 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 11475 #define USART_ISR_RXNE_Pos (5U) 11476 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 11477 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 11478 #define USART_ISR_TC_Pos (6U) 11479 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 11480 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 11481 #define USART_ISR_TXE_Pos (7U) 11482 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 11483 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 11484 #define USART_ISR_LBDF_Pos (8U) 11485 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 11486 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 11487 #define USART_ISR_CTSIF_Pos (9U) 11488 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 11489 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 11490 #define USART_ISR_CTS_Pos (10U) 11491 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 11492 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 11493 #define USART_ISR_RTOF_Pos (11U) 11494 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 11495 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 11496 #define USART_ISR_EOBF_Pos (12U) 11497 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 11498 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 11499 #define USART_ISR_ABRE_Pos (14U) 11500 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 11501 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 11502 #define USART_ISR_ABRF_Pos (15U) 11503 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 11504 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 11505 #define USART_ISR_BUSY_Pos (16U) 11506 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 11507 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 11508 #define USART_ISR_CMF_Pos (17U) 11509 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 11510 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 11511 #define USART_ISR_SBKF_Pos (18U) 11512 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 11513 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 11514 #define USART_ISR_RWU_Pos (19U) 11515 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 11516 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 11517 #define USART_ISR_WUF_Pos (20U) 11518 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 11519 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 11520 #define USART_ISR_TEACK_Pos (21U) 11521 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 11522 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 11523 #define USART_ISR_REACK_Pos (22U) 11524 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 11525 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 11526 11527 /******************* Bit definition for USART_ICR register ******************/ 11528 #define USART_ICR_PECF_Pos (0U) 11529 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 11530 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 11531 #define USART_ICR_FECF_Pos (1U) 11532 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 11533 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 11534 #define USART_ICR_NCF_Pos (2U) 11535 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 11536 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 11537 #define USART_ICR_ORECF_Pos (3U) 11538 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 11539 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 11540 #define USART_ICR_IDLECF_Pos (4U) 11541 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 11542 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 11543 #define USART_ICR_TCCF_Pos (6U) 11544 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 11545 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 11546 #define USART_ICR_LBDCF_Pos (8U) 11547 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 11548 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 11549 #define USART_ICR_CTSCF_Pos (9U) 11550 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 11551 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 11552 #define USART_ICR_RTOCF_Pos (11U) 11553 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 11554 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 11555 #define USART_ICR_EOBCF_Pos (12U) 11556 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 11557 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 11558 #define USART_ICR_CMCF_Pos (17U) 11559 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 11560 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 11561 #define USART_ICR_WUCF_Pos (20U) 11562 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 11563 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 11564 11565 /******************* Bit definition for USART_RDR register ******************/ 11566 #define USART_RDR_RDR_Pos (0U) 11567 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 11568 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 11569 11570 /******************* Bit definition for USART_TDR register ******************/ 11571 #define USART_TDR_TDR_Pos (0U) 11572 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 11573 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 11574 11575 /******************************************************************************/ 11576 /* */ 11577 /* Window WATCHDOG */ 11578 /* */ 11579 /******************************************************************************/ 11580 /******************* Bit definition for WWDG_CR register ********************/ 11581 #define WWDG_CR_T_Pos (0U) 11582 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 11583 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 11584 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 11585 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 11586 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 11587 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 11588 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 11589 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 11590 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 11591 11592 /* Legacy defines */ 11593 #define WWDG_CR_T0 WWDG_CR_T_0 11594 #define WWDG_CR_T1 WWDG_CR_T_1 11595 #define WWDG_CR_T2 WWDG_CR_T_2 11596 #define WWDG_CR_T3 WWDG_CR_T_3 11597 #define WWDG_CR_T4 WWDG_CR_T_4 11598 #define WWDG_CR_T5 WWDG_CR_T_5 11599 #define WWDG_CR_T6 WWDG_CR_T_6 11600 11601 #define WWDG_CR_WDGA_Pos (7U) 11602 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 11603 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 11604 11605 /******************* Bit definition for WWDG_CFR register *******************/ 11606 #define WWDG_CFR_W_Pos (0U) 11607 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 11608 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 11609 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 11610 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 11611 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 11612 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 11613 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 11614 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 11615 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 11616 11617 /* Legacy defines */ 11618 #define WWDG_CFR_W0 WWDG_CFR_W_0 11619 #define WWDG_CFR_W1 WWDG_CFR_W_1 11620 #define WWDG_CFR_W2 WWDG_CFR_W_2 11621 #define WWDG_CFR_W3 WWDG_CFR_W_3 11622 #define WWDG_CFR_W4 WWDG_CFR_W_4 11623 #define WWDG_CFR_W5 WWDG_CFR_W_5 11624 #define WWDG_CFR_W6 WWDG_CFR_W_6 11625 11626 #define WWDG_CFR_WDGTB_Pos (7U) 11627 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 11628 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 11629 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 11630 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 11631 11632 /* Legacy defines */ 11633 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 11634 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 11635 11636 #define WWDG_CFR_EWI_Pos (9U) 11637 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 11638 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 11639 11640 /******************* Bit definition for WWDG_SR register ********************/ 11641 #define WWDG_SR_EWIF_Pos (0U) 11642 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 11643 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 11644 11645 /** 11646 * @} 11647 */ 11648 11649 /** 11650 * @} 11651 */ 11652 11653 /** @addtogroup Exported_macros 11654 * @{ 11655 */ 11656 11657 /****************************** ADC Instances *********************************/ 11658 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ 11659 ((INSTANCE) == ADC2)) 11660 11661 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) 11662 11663 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) 11664 /****************************** CAN Instances *********************************/ 11665 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN) 11666 11667 /****************************** COMP Instances ********************************/ 11668 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \ 11669 ((INSTANCE) == COMP4) || \ 11670 ((INSTANCE) == COMP6)) 11671 11672 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U) 11673 11674 /******************** COMP Instances with switch on DAC1 Channel1 output ******/ 11675 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0U) 11676 11677 /******************** COMP Instances with window mode capability **************/ 11678 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U) 11679 11680 /****************************** CRC Instances *********************************/ 11681 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 11682 11683 /****************************** DAC Instances *********************************/ 11684 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \ 11685 ((INSTANCE) == DAC2)) 11686 11687 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \ 11688 ((((INSTANCE) == DAC1) && \ 11689 (((CHANNEL) == DAC_CHANNEL_1) || \ 11690 ((CHANNEL) == DAC_CHANNEL_2))) \ 11691 || \ 11692 (((INSTANCE) == DAC2) && \ 11693 (((CHANNEL) == DAC_CHANNEL_1)))) 11694 11695 /****************************** DMA Instances *********************************/ 11696 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 11697 ((INSTANCE) == DMA1_Channel2) || \ 11698 ((INSTANCE) == DMA1_Channel3) || \ 11699 ((INSTANCE) == DMA1_Channel4) || \ 11700 ((INSTANCE) == DMA1_Channel5) || \ 11701 ((INSTANCE) == DMA1_Channel6) || \ 11702 ((INSTANCE) == DMA1_Channel7)) 11703 11704 /****************************** GPIO Instances ********************************/ 11705 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 11706 ((INSTANCE) == GPIOB) || \ 11707 ((INSTANCE) == GPIOC) || \ 11708 ((INSTANCE) == GPIOD) || \ 11709 ((INSTANCE) == GPIOF)) 11710 11711 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 11712 ((INSTANCE) == GPIOB) || \ 11713 ((INSTANCE) == GPIOC) || \ 11714 ((INSTANCE) == GPIOD) || \ 11715 ((INSTANCE) == GPIOF)) 11716 11717 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 11718 ((INSTANCE) == GPIOB) || \ 11719 ((INSTANCE) == GPIOC) || \ 11720 ((INSTANCE) == GPIOD) || \ 11721 ((INSTANCE) == GPIOF)) 11722 11723 /****************************** I2C Instances *********************************/ 11724 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 11725 11726 /****************** I2C Instances : wakeup capability from stop modes *********/ 11727 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 11728 11729 11730 /****************************** OPAMP Instances *******************************/ 11731 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2) 11732 11733 /****************************** IWDG Instances ********************************/ 11734 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 11735 11736 /****************************** RTC Instances *********************************/ 11737 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 11738 11739 /****************************** SMBUS Instances *******************************/ 11740 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 11741 11742 /****************************** SPI Instances *********************************/ 11743 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 11744 11745 /******************* TIM Instances : All supported instances ******************/ 11746 #define IS_TIM_INSTANCE(INSTANCE)\ 11747 (((INSTANCE) == TIM1) || \ 11748 ((INSTANCE) == TIM2) || \ 11749 ((INSTANCE) == TIM3) || \ 11750 ((INSTANCE) == TIM6) || \ 11751 ((INSTANCE) == TIM7) || \ 11752 ((INSTANCE) == TIM15) || \ 11753 ((INSTANCE) == TIM16) || \ 11754 ((INSTANCE) == TIM17)) 11755 11756 /******************* TIM Instances : at least 1 capture/compare channel *******/ 11757 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 11758 (((INSTANCE) == TIM1) || \ 11759 ((INSTANCE) == TIM2) || \ 11760 ((INSTANCE) == TIM3) || \ 11761 ((INSTANCE) == TIM15) || \ 11762 ((INSTANCE) == TIM16) || \ 11763 ((INSTANCE) == TIM17)) 11764 11765 /****************** TIM Instances : at least 2 capture/compare channels *******/ 11766 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 11767 (((INSTANCE) == TIM1) || \ 11768 ((INSTANCE) == TIM2) || \ 11769 ((INSTANCE) == TIM3) || \ 11770 ((INSTANCE) == TIM15)) 11771 11772 /****************** TIM Instances : at least 3 capture/compare channels *******/ 11773 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 11774 (((INSTANCE) == TIM1) || \ 11775 ((INSTANCE) == TIM2) || \ 11776 ((INSTANCE) == TIM3)) 11777 11778 /****************** TIM Instances : at least 4 capture/compare channels *******/ 11779 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 11780 (((INSTANCE) == TIM1) || \ 11781 ((INSTANCE) == TIM2) || \ 11782 ((INSTANCE) == TIM3)) 11783 11784 /****************** TIM Instances : at least 5 capture/compare channels *******/ 11785 #define IS_TIM_CC5_INSTANCE(INSTANCE)\ 11786 (((INSTANCE) == TIM1)) 11787 11788 /****************** TIM Instances : at least 6 capture/compare channels *******/ 11789 #define IS_TIM_CC6_INSTANCE(INSTANCE)\ 11790 (((INSTANCE) == TIM1)) 11791 11792 /************************** TIM Instances : Advanced-control timers ***********/ 11793 11794 /****************** TIM Instances : Advanced timer instances *******************/ 11795 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 11796 ((INSTANCE) == TIM1) 11797 11798 /****************** TIM Instances : supporting clock selection ****************/ 11799 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\ 11800 (((INSTANCE) == TIM1) || \ 11801 ((INSTANCE) == TIM2) || \ 11802 ((INSTANCE) == TIM3) || \ 11803 ((INSTANCE) == TIM15)) 11804 11805 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */ 11806 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 11807 (((INSTANCE) == TIM1) || \ 11808 ((INSTANCE) == TIM2) || \ 11809 ((INSTANCE) == TIM3)) 11810 11811 /****************** TIM Instances : supporting external clock mode 2 **********/ 11812 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 11813 (((INSTANCE) == TIM1) || \ 11814 ((INSTANCE) == TIM2) || \ 11815 ((INSTANCE) == TIM3)) 11816 11817 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 11818 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 11819 (((INSTANCE) == TIM1) || \ 11820 ((INSTANCE) == TIM2) || \ 11821 ((INSTANCE) == TIM3) || \ 11822 ((INSTANCE) == TIM15)) 11823 11824 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 11825 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 11826 (((INSTANCE) == TIM1) || \ 11827 ((INSTANCE) == TIM2) || \ 11828 ((INSTANCE) == TIM3) || \ 11829 ((INSTANCE) == TIM15)) 11830 11831 /****************** TIM Instances : supporting OCxREF clear *******************/ 11832 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 11833 (((INSTANCE) == TIM1) || \ 11834 ((INSTANCE) == TIM2) || \ 11835 ((INSTANCE) == TIM3)) 11836 11837 /****************** TIM Instances : supporting encoder interface **************/ 11838 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 11839 (((INSTANCE) == TIM1) || \ 11840 ((INSTANCE) == TIM2) || \ 11841 ((INSTANCE) == TIM3)) 11842 11843 /****************** TIM Instances : supporting Hall interface *****************/ 11844 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 11845 (((INSTANCE) == TIM1)) 11846 11847 /**************** TIM Instances : external trigger input available ************/ 11848 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11849 ((INSTANCE) == TIM2) || \ 11850 ((INSTANCE) == TIM3)) 11851 11852 /****************** TIM Instances : supporting input XOR function *************/ 11853 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 11854 (((INSTANCE) == TIM1) || \ 11855 ((INSTANCE) == TIM2) || \ 11856 ((INSTANCE) == TIM3) || \ 11857 ((INSTANCE) == TIM15)) 11858 11859 /****************** TIM Instances : supporting master mode ********************/ 11860 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 11861 (((INSTANCE) == TIM1) || \ 11862 ((INSTANCE) == TIM2) || \ 11863 ((INSTANCE) == TIM3) || \ 11864 ((INSTANCE) == TIM6) || \ 11865 ((INSTANCE) == TIM7) || \ 11866 ((INSTANCE) == TIM15)) 11867 11868 /****************** TIM Instances : supporting slave mode *********************/ 11869 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 11870 (((INSTANCE) == TIM1) || \ 11871 ((INSTANCE) == TIM2) || \ 11872 ((INSTANCE) == TIM3) || \ 11873 ((INSTANCE) == TIM15)) 11874 11875 /****************** TIM Instances : supporting 32 bits counter ****************/ 11876 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ 11877 ((INSTANCE) == TIM2) 11878 11879 /****************** TIM Instances : supporting DMA burst **********************/ 11880 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 11881 (((INSTANCE) == TIM1) || \ 11882 ((INSTANCE) == TIM2) || \ 11883 ((INSTANCE) == TIM3) || \ 11884 ((INSTANCE) == TIM15) || \ 11885 ((INSTANCE) == TIM16) || \ 11886 ((INSTANCE) == TIM17)) 11887 11888 /****************** TIM Instances : supporting the break function *************/ 11889 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 11890 (((INSTANCE) == TIM1) || \ 11891 ((INSTANCE) == TIM15) || \ 11892 ((INSTANCE) == TIM16) || \ 11893 ((INSTANCE) == TIM17)) 11894 11895 /****************** TIM Instances : supporting input/output channel(s) ********/ 11896 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 11897 ((((INSTANCE) == TIM1) && \ 11898 (((CHANNEL) == TIM_CHANNEL_1) || \ 11899 ((CHANNEL) == TIM_CHANNEL_2) || \ 11900 ((CHANNEL) == TIM_CHANNEL_3) || \ 11901 ((CHANNEL) == TIM_CHANNEL_4) || \ 11902 ((CHANNEL) == TIM_CHANNEL_5) || \ 11903 ((CHANNEL) == TIM_CHANNEL_6))) \ 11904 || \ 11905 (((INSTANCE) == TIM2) && \ 11906 (((CHANNEL) == TIM_CHANNEL_1) || \ 11907 ((CHANNEL) == TIM_CHANNEL_2) || \ 11908 ((CHANNEL) == TIM_CHANNEL_3) || \ 11909 ((CHANNEL) == TIM_CHANNEL_4))) \ 11910 || \ 11911 (((INSTANCE) == TIM3) && \ 11912 (((CHANNEL) == TIM_CHANNEL_1) || \ 11913 ((CHANNEL) == TIM_CHANNEL_2) || \ 11914 ((CHANNEL) == TIM_CHANNEL_3) || \ 11915 ((CHANNEL) == TIM_CHANNEL_4))) \ 11916 || \ 11917 (((INSTANCE) == TIM15) && \ 11918 (((CHANNEL) == TIM_CHANNEL_1) || \ 11919 ((CHANNEL) == TIM_CHANNEL_2))) \ 11920 || \ 11921 (((INSTANCE) == TIM16) && \ 11922 (((CHANNEL) == TIM_CHANNEL_1))) \ 11923 || \ 11924 (((INSTANCE) == TIM17) && \ 11925 (((CHANNEL) == TIM_CHANNEL_1)))) 11926 11927 /****************** TIM Instances : supporting complementary output(s) ********/ 11928 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 11929 ((((INSTANCE) == TIM1) && \ 11930 (((CHANNEL) == TIM_CHANNEL_1) || \ 11931 ((CHANNEL) == TIM_CHANNEL_2) || \ 11932 ((CHANNEL) == TIM_CHANNEL_3))) \ 11933 || \ 11934 (((INSTANCE) == TIM15) && \ 11935 ((CHANNEL) == TIM_CHANNEL_1)) \ 11936 || \ 11937 (((INSTANCE) == TIM16) && \ 11938 ((CHANNEL) == TIM_CHANNEL_1)) \ 11939 || \ 11940 (((INSTANCE) == TIM17) && \ 11941 ((CHANNEL) == TIM_CHANNEL_1))) 11942 11943 /****************** TIM Instances : supporting counting mode selection ********/ 11944 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 11945 (((INSTANCE) == TIM1) || \ 11946 ((INSTANCE) == TIM2) || \ 11947 ((INSTANCE) == TIM3)) 11948 11949 /****************** TIM Instances : supporting repetition counter *************/ 11950 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 11951 (((INSTANCE) == TIM1) || \ 11952 ((INSTANCE) == TIM15) || \ 11953 ((INSTANCE) == TIM16) || \ 11954 ((INSTANCE) == TIM17)) 11955 11956 /****************** TIM Instances : supporting clock division *****************/ 11957 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 11958 (((INSTANCE) == TIM1) || \ 11959 ((INSTANCE) == TIM2) || \ 11960 ((INSTANCE) == TIM3) || \ 11961 ((INSTANCE) == TIM15) || \ 11962 ((INSTANCE) == TIM16) || \ 11963 ((INSTANCE) == TIM17)) 11964 11965 /****************** TIM Instances : supporting 2 break inputs *****************/ 11966 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\ 11967 (((INSTANCE) == TIM1)) 11968 11969 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 11970 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\ 11971 (((INSTANCE) == TIM1)) 11972 11973 /****************** TIM Instances : supporting DMA generation on Update events*/ 11974 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 11975 (((INSTANCE) == TIM1) || \ 11976 ((INSTANCE) == TIM2) || \ 11977 ((INSTANCE) == TIM3) || \ 11978 ((INSTANCE) == TIM6) || \ 11979 ((INSTANCE) == TIM7) || \ 11980 ((INSTANCE) == TIM15) || \ 11981 ((INSTANCE) == TIM16) || \ 11982 ((INSTANCE) == TIM17)) 11983 11984 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */ 11985 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 11986 (((INSTANCE) == TIM1) || \ 11987 ((INSTANCE) == TIM2) || \ 11988 ((INSTANCE) == TIM3) || \ 11989 ((INSTANCE) == TIM15) || \ 11990 ((INSTANCE) == TIM16) || \ 11991 ((INSTANCE) == TIM17)) 11992 11993 /****************** TIM Instances : supporting commutation event generation ***/ 11994 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 11995 (((INSTANCE) == TIM1) || \ 11996 ((INSTANCE) == TIM15) || \ 11997 ((INSTANCE) == TIM16) || \ 11998 ((INSTANCE) == TIM17)) 11999 12000 /****************** TIM Instances : supporting remapping capability ***********/ 12001 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 12002 (((INSTANCE) == TIM1) || \ 12003 ((INSTANCE) == TIM16)) 12004 12005 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 12006 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \ 12007 (((INSTANCE) == TIM1)) 12008 12009 /****************************** TSC Instances *********************************/ 12010 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) 12011 12012 /******************** USART Instances : Synchronous mode **********************/ 12013 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 12014 ((INSTANCE) == USART2) || \ 12015 ((INSTANCE) == USART3)) 12016 12017 /****************** USART Instances : Auto Baud Rate detection ****************/ 12018 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12019 12020 /******************** UART Instances : Asynchronous mode **********************/ 12021 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 12022 ((INSTANCE) == USART2) || \ 12023 ((INSTANCE) == USART3)) 12024 12025 /******************** UART Instances : Half-Duplex mode **********************/ 12026 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 12027 ((INSTANCE) == USART2) || \ 12028 ((INSTANCE) == USART3)) 12029 12030 /******************** UART Instances : LIN mode **********************/ 12031 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12032 12033 /******************** UART Instances : Wake-up from Stop mode **********************/ 12034 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12035 12036 /****************** UART Instances : Hardware Flow control ********************/ 12037 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 12038 ((INSTANCE) == USART2) || \ 12039 ((INSTANCE) == USART3)) 12040 12041 /****************** UART Instances : Auto Baud Rate detection *****************/ 12042 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12043 12044 /****************** UART Instances : Driver Enable ****************************/ 12045 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 12046 ((INSTANCE) == USART2) || \ 12047 ((INSTANCE) == USART3)) 12048 12049 /********************* UART Instances : Smard card mode ***********************/ 12050 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12051 12052 /*********************** UART Instances : IRDA mode ***************************/ 12053 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 12054 12055 /******************** UART Instances : Support of continuous communication using DMA ****/ 12056 #define IS_UART_DMA_INSTANCE(INSTANCE) (1) 12057 /****************************** WWDG Instances ********************************/ 12058 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 12059 12060 /** 12061 * @} 12062 */ 12063 12064 12065 /******************************************************************************/ 12066 /* For a painless codes migration between the STM32F3xx device product */ 12067 /* lines, the aliases defined below are put in place to overcome the */ 12068 /* differences in the interrupt handlers and IRQn definitions. */ 12069 /* No need to update developed interrupt code when moving across */ 12070 /* product lines within the same STM32F3 Family */ 12071 /******************************************************************************/ 12072 12073 /* Aliases for __IRQn */ 12074 #define ADC1_IRQn ADC1_2_IRQn 12075 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn 12076 #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn 12077 #define COMP1_2_IRQn COMP2_IRQn 12078 #define COMP_IRQn COMP2_IRQn 12079 #define COMP1_2_3_IRQn COMP2_IRQn 12080 #define COMP4_5_6_IRQn COMP4_6_IRQn 12081 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn 12082 #define TIM18_DAC2_IRQn TIM1_CC_IRQn 12083 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn 12084 #define TIM16_IRQn TIM1_UP_TIM16_IRQn 12085 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn 12086 #define TIM7_IRQn TIM7_DAC2_IRQn 12087 12088 12089 /* Aliases for __IRQHandler */ 12090 #define ADC1_IRQHandler ADC1_2_IRQHandler 12091 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler 12092 #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler 12093 #define COMP1_2_IRQHandler COMP2_IRQHandler 12094 #define COMP_IRQHandler COMP2_IRQHandler 12095 #define COMP1_2_3_IRQHandler COMP2_IRQHandler 12096 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler 12097 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler 12098 #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler 12099 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 12100 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler 12101 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler 12102 #define TIM7_IRQHandler TIM7_DAC2_IRQHandler 12103 12104 12105 #ifdef __cplusplus 12106 } 12107 #endif /* __cplusplus */ 12108 12109 #endif /* __STM32F328xx_H */ 12110 12111 /** 12112 * @} 12113 */ 12114 12115 /** 12116 * @} 12117 */ 12118
