1 /**
2   ******************************************************************************
3   * @file    stm32f358xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2016 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32f358xx
30   * @{
31   */
32 
33 #ifndef __STM32F358xx_H
34 #define __STM32F358xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46  */
47 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
48 #define __MPU_PRESENT             1U       /*!< STM32F358xx devices provide an MPU */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32F358xx devices use 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used */
51 #define __FPU_PRESENT             1U       /*!< STM32F358xx devices provide an FPU */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32F358xx devices Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
80   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
81   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
82   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
83   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
84   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
85   EXTI2_TSC_IRQn              = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt         */
86   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
87   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
88   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
89   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
90   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
91   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
92   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
93   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
94   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
95   ADC1_2_IRQn                 = 18,     /*!< ADC1 & ADC2 Interrupts                                            */
96   CAN_TX_IRQn                 = 19,     /*!< CAN TX Interrupt                                                  */
97   CAN_RX0_IRQn                = 20,     /*!< CAN RX0 Interrupt                                                 */
98   CAN_RX1_IRQn                = 21,     /*!< CAN RX1 Interrupt                                                 */
99   CAN_SCE_IRQn                = 22,     /*!< CAN SCE Interrupt                                                 */
100   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
101   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                                   */
102   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                                  */
103   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt                  */
104   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
105   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
106   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
107   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
108   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup)        */
109   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
110   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup)        */
111   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
112   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
113   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
114   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup)   */
115   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup)   */
116   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup)   */
117   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
118   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt                 */
119   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
120   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
121   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
122   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
123   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                             */
124   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
125   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup)     */
126   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup)     */
127   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC underrun error Interrupt             */
128   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
129   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
130   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
131   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
132   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
133   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
134   ADC4_IRQn                   = 61,     /*!< ADC4  global Interrupt                                            */
135   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
136   COMP4_5_6_IRQn              = 65,     /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
137   COMP7_IRQn                  = 66,     /*!< COMP7 global Interrupt via EXTI Line33                            */
138   FPU_IRQn                    = 81,      /*!< Floating point Interrupt                                          */
139 } IRQn_Type;
140 
141 /**
142   * @}
143   */
144 
145 #include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
146 #include "system_stm32f3xx.h"    /* STM32F3xx System Header */
147 #include <stdint.h>
148 
149 /** @addtogroup Peripheral_registers_structures
150   * @{
151   */
152 
153 /**
154   * @brief Analog to Digital Converter
155   */
156 
157 typedef struct
158 {
159   __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
160   __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */
161   __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
162   __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
163   uint32_t      RESERVED0;        /*!< Reserved, 0x010                                                         */
164   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
165   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
166   uint32_t      RESERVED1;        /*!< Reserved, 0x01C                                                         */
167   __IO uint32_t TR1;              /*!< ADC watchdog threshold register 1,                 Address offset: 0x20 */
168   __IO uint32_t TR2;              /*!< ADC watchdog threshold register 2,                 Address offset: 0x24 */
169   __IO uint32_t TR3;              /*!< ADC watchdog threshold register 3,                 Address offset: 0x28 */
170   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
171   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
172   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
173   __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
174   __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
175   __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
176   uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
177   uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
178   __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
179   uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
180   __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
181   __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
182   __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
183   __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
184   uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
185   __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
186   __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
187   __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
188   __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
189   uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */
190   __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
191   __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
192   uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
193   uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */
194   __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xB0 */
195   __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xB4 */
196 
197 } ADC_TypeDef;
198 
199 typedef struct
200 {
201   __IO uint32_t CSR;            /*!< ADC Common status register,                  Address offset: ADC1/3 base address + 0x300 */
202   uint32_t      RESERVED;       /*!< Reserved, ADC1/3 base address + 0x304                                                    */
203   __IO uint32_t CCR;            /*!< ADC common control register,                 Address offset: ADC1/3 base address + 0x308 */
204   __IO uint32_t CDR;            /*!< ADC common regular data register for dual
205                                      AND triple modes,                            Address offset: ADC1/3 base address + 0x30C */
206 } ADC_Common_TypeDef;
207 
208 /**
209   * @brief Controller Area Network TxMailBox
210   */
211 typedef struct
212 {
213   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
214   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
215   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
216   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
217 } CAN_TxMailBox_TypeDef;
218 
219 /**
220   * @brief Controller Area Network FIFOMailBox
221   */
222 typedef struct
223 {
224   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
225   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
226   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
227   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
228 } CAN_FIFOMailBox_TypeDef;
229 
230 /**
231   * @brief Controller Area Network FilterRegister
232   */
233 typedef struct
234 {
235   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
236   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
237 } CAN_FilterRegister_TypeDef;
238 
239 /**
240   * @brief Controller Area Network
241   */
242 typedef struct
243 {
244   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
245   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
246   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
247   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
248   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
249   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
250   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
251   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
252   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
253   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
254   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
255   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
256   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
257   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
258   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
259   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
260   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
261   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
262   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
263   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
264   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
265   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
266 } CAN_TypeDef;
267 
268 /**
269   * @brief Analog Comparators
270   */
271 typedef struct
272 {
273   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
274 } COMP_TypeDef;
275 
276 typedef struct
277 {
278   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
279 } COMP_Common_TypeDef;
280 
281 /**
282   * @brief CRC calculation unit
283   */
284 
285 typedef struct
286 {
287   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
288   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
289   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
290   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
291   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
292   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
293   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
294   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
295 } CRC_TypeDef;
296 
297 /**
298   * @brief Digital to Analog Converter
299   */
300 
301 typedef struct
302 {
303   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
304   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
305   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
306   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
307   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
308   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
309   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
310   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
311   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
312   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
313   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
314   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
315   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
316   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
317 } DAC_TypeDef;
318 
319 /**
320   * @brief Debug MCU
321   */
322 
323 typedef struct
324 {
325   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
326   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
327   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
328   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
329 }DBGMCU_TypeDef;
330 
331 /**
332   * @brief DMA Controller
333   */
334 
335 typedef struct
336 {
337   __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
338   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
339   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
340   __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
341 } DMA_Channel_TypeDef;
342 
343 typedef struct
344 {
345   __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
346   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
347 } DMA_TypeDef;
348 
349 /**
350   * @brief External Interrupt/Event Controller
351   */
352 
353 typedef struct
354 {
355   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
356   __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
357   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
358   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
359   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
360   __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
361   uint32_t      RESERVED1;    /*!< Reserved, 0x18                                                                */
362   uint32_t      RESERVED2;    /*!< Reserved, 0x1C                                                                */
363   __IO uint32_t IMR2;         /*!< EXTI Interrupt mask register,                            Address offset: 0x20 */
364   __IO uint32_t EMR2;         /*!< EXTI Event mask register,                                Address offset: 0x24 */
365   __IO uint32_t RTSR2;        /*!< EXTI Rising trigger selection register,                  Address offset: 0x28 */
366   __IO uint32_t FTSR2;        /*!< EXTI Falling trigger selection register,                 Address offset: 0x2C */
367   __IO uint32_t SWIER2;       /*!< EXTI Software interrupt event register,                  Address offset: 0x30 */
368   __IO uint32_t PR2;          /*!< EXTI Pending register,                                   Address offset: 0x34 */
369 }EXTI_TypeDef;
370 
371 /**
372   * @brief FLASH Registers
373   */
374 
375 typedef struct
376 {
377   __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
378   __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
379   __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
380   __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
381   __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
382   __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
383   uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
384   __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
385   __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
386 
387 } FLASH_TypeDef;
388 
389 /**
390   * @brief Option Bytes Registers
391   */
392 typedef struct
393 {
394   __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
395   __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
396   __IO uint16_t Data0;        /*!<FLASH option byte Data0 options,               Address offset: 0x04 */
397   __IO uint16_t Data1;        /*!<FLASH option byte Data1 options,               Address offset: 0x06 */
398   __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
399   __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
400   __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
401   __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
402 } OB_TypeDef;
403 
404 /**
405   * @brief General Purpose I/O
406   */
407 
408 typedef struct
409 {
410   __IO uint32_t MODER;        /*!< GPIO port mode register,               Address offset: 0x00      */
411   __IO uint32_t OTYPER;       /*!< GPIO port output type register,        Address offset: 0x04      */
412   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,       Address offset: 0x08      */
413   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
414   __IO uint32_t IDR;          /*!< GPIO port input data register,         Address offset: 0x10      */
415   __IO uint32_t ODR;          /*!< GPIO port output data register,        Address offset: 0x14      */
416   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
417   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register, Address offset: 0x1C      */
418   __IO uint32_t AFR[2];       /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
419   __IO uint32_t BRR;          /*!< GPIO bit reset register,               Address offset: 0x28 */
420 }GPIO_TypeDef;
421 
422 /**
423   * @brief Operational Amplifier (OPAMP)
424   */
425 
426 typedef struct
427 {
428   __IO uint32_t CSR;        /*!< OPAMP control and status register,            Address offset: 0x00 */
429 } OPAMP_TypeDef;
430 
431 /**
432   * @brief System configuration controller
433   */
434 
435 typedef struct
436 {
437   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
438   __IO uint32_t RCR;        /*!< SYSCFG CCM SRAM protection register,               Address offset: 0x04 */
439   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
440   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
441 } SYSCFG_TypeDef;
442 
443 /**
444   * @brief Inter-integrated Circuit Interface
445   */
446 
447 typedef struct
448 {
449   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
450   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
451   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
452   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
453   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
454   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
455   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
456   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
457   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
458   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
459   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
460 }I2C_TypeDef;
461 
462 /**
463   * @brief Independent WATCHDOG
464   */
465 
466 typedef struct
467 {
468   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
469   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
470   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
471   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
472   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
473 } IWDG_TypeDef;
474 
475 /**
476   * @brief Power Control
477   */
478 
479 typedef struct
480 {
481   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
482   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
483 } PWR_TypeDef;
484 
485 /**
486   * @brief Reset and Clock Control
487   */
488 typedef struct
489 {
490   __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
491   __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
492   __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
493   __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
494   __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
495   __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
496   __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
497   __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
498   __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
499   __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
500   __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
501   __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
502   __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
503 } RCC_TypeDef;
504 
505 /**
506   * @brief Real-Time Clock
507   */
508 
509 typedef struct
510 {
511   __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
512   __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
513   __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
514   __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
515   __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
516   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
517   uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
518   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
519   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
520   __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
521   __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
522   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
523   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
524   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
525   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
526   __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
527   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
528   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
529   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
530   uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
531   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
532   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
533   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
534   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
535   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
536   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
537   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
538   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
539   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
540   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
541   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
542   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
543   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
544   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
545   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
546   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
547 } RTC_TypeDef;
548 
549 
550 /**
551   * @brief Serial Peripheral Interface
552   */
553 
554 typedef struct
555 {
556   __IO uint32_t CR1;      /*!< SPI Control register 1,                              Address offset: 0x00 */
557   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
558   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
559   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
560   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
561   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
562   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
563   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
564   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
565 } SPI_TypeDef;
566 
567 /**
568   * @brief TIM
569   */
570 typedef struct
571 {
572   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
573   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
574   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
575   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
576   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
577   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
578   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
579   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
580   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
581   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
582   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
583   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
584   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
585   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
586   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
587   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
588   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
589   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
590   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
591   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
592   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
593   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
594   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,       Address offset: 0x58 */
595   __IO uint32_t CCR6;        /*!< TIM capture/compare register 4,      Address offset: 0x5C */
596 } TIM_TypeDef;
597 
598 /**
599   * @brief Touch Sensing Controller (TSC)
600   */
601 typedef struct
602 {
603   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
604   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
605   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
606   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
607   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
608   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
609   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
610   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
611   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
612   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
613   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
614   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
615   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
616   __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
617 } TSC_TypeDef;
618 
619 /**
620   * @brief Universal Synchronous Asynchronous Receiver Transmitter
621   */
622 
623 typedef struct
624 {
625   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
626   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
627   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
628   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
629   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
630   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
631   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
632   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
633   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
634   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
635   uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
636   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
637   uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
638 } USART_TypeDef;
639 
640 /**
641   * @brief Window WATCHDOG
642   */
643 typedef struct
644 {
645   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
646   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
647   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
648 } WWDG_TypeDef;
649 
650 /**
651   * @}
652   */
653 
654 /** @addtogroup Peripheral_memory_map
655   * @{
656   */
657 
658 #define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
659 #define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM base address in the alias region     */
660 #define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
661 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
662 #define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
663 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
664 
665 
666 /*!< Peripheral memory map */
667 #define APB1PERIPH_BASE       PERIPH_BASE
668 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
669 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
670 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
671 #define AHB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
672 
673 /*!< APB1 peripherals */
674 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
675 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
676 #define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
677 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
678 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
679 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
680 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
681 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
682 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x00003400UL)
683 #define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
684 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
685 #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x00004000UL)
686 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
687 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
688 #define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
689 #define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
690 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
691 #define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
692 #define CAN_BASE              (APB1PERIPH_BASE + 0x00006400UL)
693 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
694 #define DAC1_BASE             (APB1PERIPH_BASE + 0x00007400UL)
695 #define DAC_BASE               DAC1_BASE
696 
697 /*!< APB2 peripherals */
698 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000UL)
699 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0000001CUL)
700 #define COMP2_BASE            (APB2PERIPH_BASE + 0x00000020UL)
701 #define COMP3_BASE            (APB2PERIPH_BASE + 0x00000024UL)
702 #define COMP4_BASE            (APB2PERIPH_BASE + 0x00000028UL)
703 #define COMP5_BASE            (APB2PERIPH_BASE + 0x0000002CUL)
704 #define COMP6_BASE            (APB2PERIPH_BASE + 0x00000030UL)
705 #define COMP7_BASE            (APB2PERIPH_BASE + 0x00000034UL)
706 #define COMP_BASE             COMP1_BASE
707 #define OPAMP1_BASE           (APB2PERIPH_BASE + 0x00000038UL)
708 #define OPAMP2_BASE           (APB2PERIPH_BASE + 0x0000003CUL)
709 #define OPAMP3_BASE           (APB2PERIPH_BASE + 0x00000040UL)
710 #define OPAMP4_BASE           (APB2PERIPH_BASE + 0x00000044UL)
711 #define OPAMP_BASE            OPAMP1_BASE
712 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
713 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
714 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
715 #define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400UL)
716 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
717 #define TIM15_BASE            (APB2PERIPH_BASE + 0x00004000UL)
718 #define TIM16_BASE            (APB2PERIPH_BASE + 0x00004400UL)
719 #define TIM17_BASE            (APB2PERIPH_BASE + 0x00004800UL)
720 
721 /*!< AHB1 peripherals */
722 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x00000000UL)
723 #define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000008UL)
724 #define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000001CUL)
725 #define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000030UL)
726 #define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000044UL)
727 #define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000058UL)
728 #define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x0000006CUL)
729 #define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x00000080UL)
730 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x00000400UL)
731 #define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x00000408UL)
732 #define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x0000041CUL)
733 #define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x00000430UL)
734 #define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x00000444UL)
735 #define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x00000458UL)
736 #define RCC_BASE              (AHB1PERIPH_BASE + 0x00001000UL)
737 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
738 #define OB_BASE               0x1FFFF800UL         /*!< Flash Option Bytes base address */
739 #define FLASHSIZE_BASE        0x1FFFF7CCUL         /*!< FLASH Size register base address */
740 #define UID_BASE              0x1FFFF7ACUL         /*!< Unique device ID register base address */
741 #define CRC_BASE              (AHB1PERIPH_BASE + 0x00003000UL)
742 #define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000UL)
743 
744 /*!< AHB2 peripherals */
745 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000UL)
746 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400UL)
747 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800UL)
748 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00UL)
749 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x00001000UL)
750 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400UL)
751 
752 /*!< AHB3 peripherals */
753 #define ADC1_BASE             (AHB3PERIPH_BASE + 0x00000000UL)
754 #define ADC2_BASE             (AHB3PERIPH_BASE + 0x00000100UL)
755 #define ADC1_2_COMMON_BASE    (AHB3PERIPH_BASE + 0x00000300UL)
756 #define ADC3_BASE             (AHB3PERIPH_BASE + 0x00000400UL)
757 #define ADC4_BASE             (AHB3PERIPH_BASE + 0x00000500UL)
758 #define ADC3_4_COMMON_BASE    (AHB3PERIPH_BASE + 0x00000700UL)
759 
760 #define DBGMCU_BASE           0xE0042000UL /*!< Debug MCU registers base address */
761 /**
762   * @}
763   */
764 
765 /** @addtogroup Peripheral_declaration
766   * @{
767   */
768 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
769 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
770 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
771 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
772 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
773 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
774 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
775 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
776 #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
777 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
778 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
779 #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
780 #define USART2              ((USART_TypeDef *) USART2_BASE)
781 #define USART3              ((USART_TypeDef *) USART3_BASE)
782 #define UART4               ((USART_TypeDef *) UART4_BASE)
783 #define UART5               ((USART_TypeDef *) UART5_BASE)
784 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
785 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
786 #define CAN                 ((CAN_TypeDef *) CAN_BASE)
787 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
788 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
789 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
790 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
791 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
792 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
793 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
794 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
795 #define COMP34_COMMON       ((COMP_Common_TypeDef *) COMP4_BASE)
796 #define COMP5               ((COMP_TypeDef *) COMP5_BASE)
797 #define COMP6               ((COMP_TypeDef *) COMP6_BASE)
798 #define COMP56_COMMON       ((COMP_Common_TypeDef *) COMP6_BASE)
799 #define COMP7               ((COMP_TypeDef *) COMP7_BASE)
800 /* Legacy define */
801 #define COMP                ((COMP_TypeDef *) COMP_BASE)
802 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
803 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
804 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
805 #define OPAMP3              ((OPAMP_TypeDef *) OPAMP3_BASE)
806 #define OPAMP4              ((OPAMP_TypeDef *) OPAMP4_BASE)
807 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
808 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
809 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
810 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
811 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
812 #define USART1              ((USART_TypeDef *) USART1_BASE)
813 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
814 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
815 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
816 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
817 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
818 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
819 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
820 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
821 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
822 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
823 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
824 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
825 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
826 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
827 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
828 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
829 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
830 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
831 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
832 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
833 #define OB                  ((OB_TypeDef *) OB_BASE)
834 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
835 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
836 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
837 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
838 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
839 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
840 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
841 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
842 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
843 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
844 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
845 #define ADC4                ((ADC_TypeDef *) ADC4_BASE)
846 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
847 #define ADC34_COMMON        ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
848 /* Legacy defines */
849 #define ADC1_2_COMMON       ADC12_COMMON
850 #define ADC3_4_COMMON       ADC34_COMMON
851 
852 /**
853   * @}
854   */
855 
856 /** @addtogroup Exported_constants
857   * @{
858   */
859 
860   /** @addtogroup Hardware_Constant_Definition
861     * @{
862     */
863 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
864 
865   /**
866     * @}
867     */
868 
869   /** @addtogroup Peripheral_Registers_Bits_Definition
870   * @{
871   */
872 
873 /******************************************************************************/
874 /*                         Peripheral Registers_Bits_Definition               */
875 /******************************************************************************/
876 
877 /******************************************************************************/
878 /*                                                                            */
879 /*                        Analog to Digital Converter SAR (ADC)               */
880 /*                                                                            */
881 /******************************************************************************/
882 
883 #define ADC5_V1_1                                      /*!< ADC IP version */
884 
885 /*
886  * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
887  */
888 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
889 
890 /********************  Bit definition for ADC_ISR register  ********************/
891 #define ADC_ISR_ADRDY_Pos              (0U)
892 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
893 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
894 #define ADC_ISR_EOSMP_Pos              (1U)
895 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
896 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
897 #define ADC_ISR_EOC_Pos                (2U)
898 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
899 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
900 #define ADC_ISR_EOS_Pos                (3U)
901 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
902 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
903 #define ADC_ISR_OVR_Pos                (4U)
904 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
905 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
906 #define ADC_ISR_JEOC_Pos               (5U)
907 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
908 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
909 #define ADC_ISR_JEOS_Pos               (6U)
910 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
911 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
912 #define ADC_ISR_AWD1_Pos               (7U)
913 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
914 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
915 #define ADC_ISR_AWD2_Pos               (8U)
916 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
917 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
918 #define ADC_ISR_AWD3_Pos               (9U)
919 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
920 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
921 #define ADC_ISR_JQOVF_Pos              (10U)
922 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
923 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
924 
925 /* Legacy defines */
926 #define ADC_ISR_ADRD            (ADC_ISR_ADRDY)
927 
928 /********************  Bit definition for ADC_IER register  ********************/
929 #define ADC_IER_ADRDYIE_Pos            (0U)
930 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
931 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
932 #define ADC_IER_EOSMPIE_Pos            (1U)
933 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
934 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
935 #define ADC_IER_EOCIE_Pos              (2U)
936 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
937 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
938 #define ADC_IER_EOSIE_Pos              (3U)
939 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
940 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
941 #define ADC_IER_OVRIE_Pos              (4U)
942 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
943 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
944 #define ADC_IER_JEOCIE_Pos             (5U)
945 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
946 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
947 #define ADC_IER_JEOSIE_Pos             (6U)
948 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
949 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
950 #define ADC_IER_AWD1IE_Pos             (7U)
951 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
952 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
953 #define ADC_IER_AWD2IE_Pos             (8U)
954 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
955 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
956 #define ADC_IER_AWD3IE_Pos             (9U)
957 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
958 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
959 #define ADC_IER_JQOVFIE_Pos            (10U)
960 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
961 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
962 
963 /* Legacy defines */
964 #define ADC_IER_RDY             (ADC_IER_ADRDYIE)
965 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
966 #define ADC_IER_EOC             (ADC_IER_EOCIE)
967 #define ADC_IER_EOS             (ADC_IER_EOSIE)
968 #define ADC_IER_OVR             (ADC_IER_OVRIE)
969 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
970 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
971 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
972 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
973 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
974 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
975 
976 /********************  Bit definition for ADC_CR register  ********************/
977 #define ADC_CR_ADEN_Pos                (0U)
978 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
979 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
980 #define ADC_CR_ADDIS_Pos               (1U)
981 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
982 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
983 #define ADC_CR_ADSTART_Pos             (2U)
984 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
985 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
986 #define ADC_CR_JADSTART_Pos            (3U)
987 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
988 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
989 #define ADC_CR_ADSTP_Pos               (4U)
990 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
991 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
992 #define ADC_CR_JADSTP_Pos              (5U)
993 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
994 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
995 #define ADC_CR_ADVREGEN_Pos            (28U)
996 #define ADC_CR_ADVREGEN_Msk            (0x3UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x30000000 */
997 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
998 #define ADC_CR_ADVREGEN_0              (0x1UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
999 #define ADC_CR_ADVREGEN_1              (0x2UL << ADC_CR_ADVREGEN_Pos)           /*!< 0x20000000 */
1000 #define ADC_CR_ADCALDIF_Pos            (30U)
1001 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
1002 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1003 #define ADC_CR_ADCAL_Pos               (31U)
1004 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
1005 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1006 
1007 /********************  Bit definition for ADC_CFGR register  ******************/
1008 #define ADC_CFGR_DMAEN_Pos             (0U)
1009 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
1010 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA enable */
1011 #define ADC_CFGR_DMACFG_Pos            (1U)
1012 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
1013 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA configuration */
1014 
1015 #define ADC_CFGR_RES_Pos               (3U)
1016 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
1017 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1018 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
1019 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
1020 
1021 #define ADC_CFGR_ALIGN_Pos             (5U)
1022 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
1023 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1024 
1025 #define ADC_CFGR_EXTSEL_Pos            (6U)
1026 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
1027 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1028 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
1029 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
1030 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
1031 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
1032 
1033 #define ADC_CFGR_EXTEN_Pos             (10U)
1034 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
1035 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1036 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
1037 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
1038 
1039 #define ADC_CFGR_OVRMOD_Pos            (12U)
1040 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
1041 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1042 #define ADC_CFGR_CONT_Pos              (13U)
1043 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
1044 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1045 #define ADC_CFGR_AUTDLY_Pos            (14U)
1046 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
1047 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1048 
1049 #define ADC_CFGR_DISCEN_Pos            (16U)
1050 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
1051 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1052 
1053 #define ADC_CFGR_DISCNUM_Pos           (17U)
1054 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
1055 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC Discontinuous mode channel count */
1056 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
1057 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
1058 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
1059 
1060 #define ADC_CFGR_JDISCEN_Pos           (20U)
1061 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
1062 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC Discontinuous mode on injected channels */
1063 #define ADC_CFGR_JQM_Pos               (21U)
1064 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
1065 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1066 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1067 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
1068 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1069 #define ADC_CFGR_AWD1EN_Pos            (23U)
1070 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
1071 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1072 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1073 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
1074 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1075 #define ADC_CFGR_JAUTO_Pos             (25U)
1076 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
1077 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1078 
1079 #define ADC_CFGR_AWD1CH_Pos            (26U)
1080 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
1081 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1082 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
1083 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
1084 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
1085 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
1086 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
1087 
1088 /* Legacy defines */
1089 #define ADC_CFGR_AUTOFF_Pos            (15U)
1090 #define ADC_CFGR_AUTOFF_Msk            (0x1UL << ADC_CFGR_AUTOFF_Pos)           /*!< 0x00008000 */
1091 #define ADC_CFGR_AUTOFF                ADC_CFGR_AUTOFF_Msk                     /*!< ADC low power auto power off */
1092 
1093 /********************  Bit definition for ADC_SMPR1 register  *****************/
1094 #define ADC_SMPR1_SMP0_Pos             (0U)
1095 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
1096 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1097 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
1098 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
1099 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
1100 
1101 #define ADC_SMPR1_SMP1_Pos             (3U)
1102 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
1103 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1104 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
1105 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
1106 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
1107 
1108 #define ADC_SMPR1_SMP2_Pos             (6U)
1109 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
1110 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1111 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
1112 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
1113 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
1114 
1115 #define ADC_SMPR1_SMP3_Pos             (9U)
1116 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
1117 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1118 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
1119 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
1120 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
1121 
1122 #define ADC_SMPR1_SMP4_Pos             (12U)
1123 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
1124 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1125 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
1126 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
1127 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
1128 
1129 #define ADC_SMPR1_SMP5_Pos             (15U)
1130 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
1131 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1132 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
1133 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
1134 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
1135 
1136 #define ADC_SMPR1_SMP6_Pos             (18U)
1137 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
1138 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1139 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
1140 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
1141 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
1142 
1143 #define ADC_SMPR1_SMP7_Pos             (21U)
1144 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
1145 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1146 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
1147 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
1148 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
1149 
1150 #define ADC_SMPR1_SMP8_Pos             (24U)
1151 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
1152 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1153 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
1154 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
1155 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
1156 
1157 #define ADC_SMPR1_SMP9_Pos             (27U)
1158 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
1159 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1160 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
1161 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
1162 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
1163 
1164 /********************  Bit definition for ADC_SMPR2 register  *****************/
1165 #define ADC_SMPR2_SMP10_Pos            (0U)
1166 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
1167 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1168 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
1169 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
1170 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
1171 
1172 #define ADC_SMPR2_SMP11_Pos            (3U)
1173 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
1174 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1175 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
1176 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
1177 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
1178 
1179 #define ADC_SMPR2_SMP12_Pos            (6U)
1180 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
1181 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1182 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
1183 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
1184 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
1185 
1186 #define ADC_SMPR2_SMP13_Pos            (9U)
1187 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
1188 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1189 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
1190 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
1191 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
1192 
1193 #define ADC_SMPR2_SMP14_Pos            (12U)
1194 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
1195 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1196 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
1197 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
1198 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
1199 
1200 #define ADC_SMPR2_SMP15_Pos            (15U)
1201 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
1202 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1203 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
1204 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
1205 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
1206 
1207 #define ADC_SMPR2_SMP16_Pos            (18U)
1208 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
1209 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1210 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
1211 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
1212 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
1213 
1214 #define ADC_SMPR2_SMP17_Pos            (21U)
1215 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
1216 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1217 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
1218 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
1219 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
1220 
1221 #define ADC_SMPR2_SMP18_Pos            (24U)
1222 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
1223 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1224 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
1225 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
1226 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
1227 
1228 /********************  Bit definition for ADC_TR1 register  *******************/
1229 #define ADC_TR1_LT1_Pos                (0U)
1230 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
1231 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1232 #define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
1233 #define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
1234 #define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
1235 #define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
1236 #define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
1237 #define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
1238 #define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
1239 #define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
1240 #define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
1241 #define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
1242 #define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
1243 #define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
1244 
1245 #define ADC_TR1_HT1_Pos                (16U)
1246 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
1247 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
1248 #define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
1249 #define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
1250 #define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
1251 #define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
1252 #define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
1253 #define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
1254 #define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
1255 #define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
1256 #define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
1257 #define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
1258 #define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
1259 #define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
1260 
1261 /********************  Bit definition for ADC_TR2 register  *******************/
1262 #define ADC_TR2_LT2_Pos                (0U)
1263 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
1264 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1265 #define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
1266 #define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
1267 #define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
1268 #define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
1269 #define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
1270 #define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
1271 #define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
1272 #define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
1273 
1274 #define ADC_TR2_HT2_Pos                (16U)
1275 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
1276 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1277 #define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
1278 #define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
1279 #define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
1280 #define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
1281 #define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
1282 #define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
1283 #define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
1284 #define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
1285 
1286 /********************  Bit definition for ADC_TR3 register  *******************/
1287 #define ADC_TR3_LT3_Pos                (0U)
1288 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
1289 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1290 #define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
1291 #define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
1292 #define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
1293 #define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
1294 #define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
1295 #define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
1296 #define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
1297 #define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
1298 
1299 #define ADC_TR3_HT3_Pos                (16U)
1300 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
1301 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1302 #define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
1303 #define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
1304 #define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
1305 #define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
1306 #define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
1307 #define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
1308 #define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
1309 #define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
1310 
1311 /********************  Bit definition for ADC_SQR1 register  ******************/
1312 #define ADC_SQR1_L_Pos                 (0U)
1313 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
1314 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1315 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
1316 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
1317 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
1318 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
1319 
1320 #define ADC_SQR1_SQ1_Pos               (6U)
1321 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
1322 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1323 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
1324 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
1325 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
1326 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
1327 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
1328 
1329 #define ADC_SQR1_SQ2_Pos               (12U)
1330 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
1331 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1332 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
1333 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
1334 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
1335 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
1336 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
1337 
1338 #define ADC_SQR1_SQ3_Pos               (18U)
1339 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
1340 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1341 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
1342 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
1343 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
1344 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
1345 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1346 
1347 #define ADC_SQR1_SQ4_Pos               (24U)
1348 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
1349 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1350 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
1351 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
1352 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
1353 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
1354 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
1355 
1356 /********************  Bit definition for ADC_SQR2 register  ******************/
1357 #define ADC_SQR2_SQ5_Pos               (0U)
1358 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
1359 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1360 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
1361 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
1362 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
1363 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
1364 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
1365 
1366 #define ADC_SQR2_SQ6_Pos               (6U)
1367 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
1368 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1369 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
1370 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
1371 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
1372 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
1373 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
1374 
1375 #define ADC_SQR2_SQ7_Pos               (12U)
1376 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
1377 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1378 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
1379 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
1380 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
1381 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
1382 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
1383 
1384 #define ADC_SQR2_SQ8_Pos               (18U)
1385 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
1386 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1387 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
1388 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
1389 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
1390 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
1391 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
1392 
1393 #define ADC_SQR2_SQ9_Pos               (24U)
1394 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
1395 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1396 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
1397 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
1398 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
1399 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
1400 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
1401 
1402 /********************  Bit definition for ADC_SQR3 register  ******************/
1403 #define ADC_SQR3_SQ10_Pos              (0U)
1404 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
1405 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1406 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
1407 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
1408 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
1409 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
1410 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
1411 
1412 #define ADC_SQR3_SQ11_Pos              (6U)
1413 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
1414 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1415 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
1416 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
1417 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
1418 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
1419 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
1420 
1421 #define ADC_SQR3_SQ12_Pos              (12U)
1422 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
1423 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1424 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
1425 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
1426 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
1427 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
1428 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
1429 
1430 #define ADC_SQR3_SQ13_Pos              (18U)
1431 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
1432 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1433 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
1434 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
1435 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
1436 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
1437 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
1438 
1439 #define ADC_SQR3_SQ14_Pos              (24U)
1440 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
1441 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1442 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
1443 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
1444 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
1445 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
1446 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
1447 
1448 /********************  Bit definition for ADC_SQR4 register  ******************/
1449 #define ADC_SQR4_SQ15_Pos              (0U)
1450 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
1451 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1452 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
1453 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
1454 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
1455 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
1456 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
1457 
1458 #define ADC_SQR4_SQ16_Pos              (6U)
1459 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
1460 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1461 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
1462 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
1463 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
1464 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
1465 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
1466 
1467 /********************  Bit definition for ADC_DR register  ********************/
1468 #define ADC_DR_RDATA_Pos               (0U)
1469 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
1470 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1471 #define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
1472 #define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
1473 #define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
1474 #define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
1475 #define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
1476 #define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
1477 #define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
1478 #define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
1479 #define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
1480 #define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
1481 #define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
1482 #define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
1483 #define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
1484 #define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
1485 #define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
1486 #define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
1487 
1488 /********************  Bit definition for ADC_JSQR register  ******************/
1489 #define ADC_JSQR_JL_Pos                (0U)
1490 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
1491 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1492 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
1493 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
1494 
1495 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1496 #define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
1497 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1498 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
1499 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
1500 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
1501 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
1502 
1503 #define ADC_JSQR_JEXTEN_Pos            (6U)
1504 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
1505 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1506 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
1507 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
1508 
1509 #define ADC_JSQR_JSQ1_Pos              (8U)
1510 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
1511 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1512 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
1513 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
1514 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
1515 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
1516 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
1517 
1518 #define ADC_JSQR_JSQ2_Pos              (14U)
1519 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
1520 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1521 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
1522 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
1523 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
1524 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
1525 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
1526 
1527 #define ADC_JSQR_JSQ3_Pos              (20U)
1528 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
1529 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1530 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
1531 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
1532 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
1533 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
1534 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
1535 
1536 #define ADC_JSQR_JSQ4_Pos              (26U)
1537 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
1538 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1539 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
1540 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
1541 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
1542 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
1543 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
1544 
1545 
1546 /********************  Bit definition for ADC_OFR1 register  ******************/
1547 #define ADC_OFR1_OFFSET1_Pos           (0U)
1548 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
1549 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1550 #define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
1551 #define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
1552 #define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
1553 #define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
1554 #define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
1555 #define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
1556 #define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
1557 #define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
1558 #define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
1559 #define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
1560 #define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
1561 #define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
1562 
1563 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1564 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
1565 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1566 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
1567 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
1568 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
1569 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
1570 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
1571 
1572 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1573 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
1574 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1575 
1576 /********************  Bit definition for ADC_OFR2 register  ******************/
1577 #define ADC_OFR2_OFFSET2_Pos           (0U)
1578 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
1579 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1580 #define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
1581 #define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
1582 #define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
1583 #define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
1584 #define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
1585 #define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
1586 #define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
1587 #define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
1588 #define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
1589 #define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
1590 #define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
1591 #define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
1592 
1593 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1594 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
1595 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1596 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
1597 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
1598 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
1599 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
1600 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
1601 
1602 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1603 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
1604 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1605 
1606 /********************  Bit definition for ADC_OFR3 register  ******************/
1607 #define ADC_OFR3_OFFSET3_Pos           (0U)
1608 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
1609 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1610 #define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
1611 #define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
1612 #define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
1613 #define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
1614 #define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
1615 #define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
1616 #define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
1617 #define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
1618 #define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
1619 #define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
1620 #define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
1621 #define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
1622 
1623 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1624 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
1625 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1626 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
1627 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
1628 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
1629 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
1630 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
1631 
1632 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1633 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
1634 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1635 
1636 /********************  Bit definition for ADC_OFR4 register  ******************/
1637 #define ADC_OFR4_OFFSET4_Pos           (0U)
1638 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
1639 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1640 #define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
1641 #define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
1642 #define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
1643 #define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
1644 #define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
1645 #define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
1646 #define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
1647 #define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
1648 #define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
1649 #define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
1650 #define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
1651 #define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
1652 
1653 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1654 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
1655 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1656 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
1657 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
1658 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
1659 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
1660 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
1661 
1662 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1663 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
1664 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1665 
1666 /********************  Bit definition for ADC_JDR1 register  ******************/
1667 #define ADC_JDR1_JDATA_Pos             (0U)
1668 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
1669 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1670 #define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
1671 #define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
1672 #define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
1673 #define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
1674 #define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
1675 #define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
1676 #define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
1677 #define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
1678 #define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
1679 #define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
1680 #define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
1681 #define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
1682 #define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
1683 #define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
1684 #define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
1685 #define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
1686 
1687 /********************  Bit definition for ADC_JDR2 register  ******************/
1688 #define ADC_JDR2_JDATA_Pos             (0U)
1689 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
1690 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1691 #define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
1692 #define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
1693 #define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
1694 #define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
1695 #define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
1696 #define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
1697 #define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
1698 #define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
1699 #define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
1700 #define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
1701 #define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
1702 #define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
1703 #define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
1704 #define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
1705 #define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
1706 #define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
1707 
1708 /********************  Bit definition for ADC_JDR3 register  ******************/
1709 #define ADC_JDR3_JDATA_Pos             (0U)
1710 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
1711 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
1712 #define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
1713 #define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
1714 #define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
1715 #define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
1716 #define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
1717 #define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
1718 #define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
1719 #define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
1720 #define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
1721 #define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
1722 #define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
1723 #define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
1724 #define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
1725 #define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
1726 #define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
1727 #define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
1728 
1729 /********************  Bit definition for ADC_JDR4 register  ******************/
1730 #define ADC_JDR4_JDATA_Pos             (0U)
1731 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
1732 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
1733 #define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
1734 #define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
1735 #define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
1736 #define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
1737 #define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
1738 #define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
1739 #define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
1740 #define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
1741 #define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
1742 #define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
1743 #define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
1744 #define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
1745 #define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
1746 #define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
1747 #define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
1748 #define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
1749 
1750 /********************  Bit definition for ADC_AWD2CR register  ****************/
1751 #define ADC_AWD2CR_AWD2CH_Pos          (1U)
1752 #define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0003FFFF */
1753 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1754 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
1755 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
1756 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
1757 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
1758 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
1759 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
1760 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
1761 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
1762 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
1763 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
1764 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
1765 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
1766 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
1767 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
1768 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
1769 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
1770 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
1771 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
1772 
1773 /********************  Bit definition for ADC_AWD3CR register  ****************/
1774 #define ADC_AWD3CR_AWD3CH_Pos          (1U)
1775 #define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0003FFFF */
1776 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1777 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
1778 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
1779 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
1780 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
1781 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
1782 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
1783 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
1784 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
1785 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
1786 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
1787 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
1788 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
1789 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
1790 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
1791 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
1792 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
1793 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
1794 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
1795 
1796 /********************  Bit definition for ADC_DIFSEL register  ****************/
1797 #define ADC_DIFSEL_DIFSEL_Pos          (1U)
1798 #define ADC_DIFSEL_DIFSEL_Msk          (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0003FFFF */
1799 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
1800 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
1801 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
1802 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
1803 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
1804 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
1805 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
1806 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
1807 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
1808 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
1809 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
1810 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
1811 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
1812 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
1813 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
1814 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
1815 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
1816 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
1817 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
1818 
1819 /********************  Bit definition for ADC_CALFACT register  ***************/
1820 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
1821 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
1822 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
1823 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
1824 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
1825 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
1826 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
1827 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
1828 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
1829 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
1830 
1831 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
1832 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
1833 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
1834 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
1835 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
1836 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
1837 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
1838 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
1839 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
1840 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
1841 
1842 /*************************  ADC Common registers  *****************************/
1843 /***************  Bit definition for ADC12_COMMON_CSR register  ***************/
1844 #define ADC12_CSR_ADRDY_MST_Pos          (0U)
1845 #define ADC12_CSR_ADRDY_MST_Msk          (0x1UL << ADC12_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
1846 #define ADC12_CSR_ADRDY_MST              ADC12_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
1847 #define ADC12_CSR_ADRDY_EOSMP_MST_Pos    (1U)
1848 #define ADC12_CSR_ADRDY_EOSMP_MST_Msk    (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
1849 #define ADC12_CSR_ADRDY_EOSMP_MST        ADC12_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
1850 #define ADC12_CSR_ADRDY_EOC_MST_Pos      (2U)
1851 #define ADC12_CSR_ADRDY_EOC_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
1852 #define ADC12_CSR_ADRDY_EOC_MST          ADC12_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
1853 #define ADC12_CSR_ADRDY_EOS_MST_Pos      (3U)
1854 #define ADC12_CSR_ADRDY_EOS_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
1855 #define ADC12_CSR_ADRDY_EOS_MST          ADC12_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
1856 #define ADC12_CSR_ADRDY_OVR_MST_Pos      (4U)
1857 #define ADC12_CSR_ADRDY_OVR_MST_Msk      (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
1858 #define ADC12_CSR_ADRDY_OVR_MST          ADC12_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
1859 #define ADC12_CSR_ADRDY_JEOC_MST_Pos     (5U)
1860 #define ADC12_CSR_ADRDY_JEOC_MST_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
1861 #define ADC12_CSR_ADRDY_JEOC_MST         ADC12_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
1862 #define ADC12_CSR_ADRDY_JEOS_MST_Pos     (6U)
1863 #define ADC12_CSR_ADRDY_JEOS_MST_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
1864 #define ADC12_CSR_ADRDY_JEOS_MST         ADC12_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
1865 #define ADC12_CSR_AWD1_MST_Pos           (7U)
1866 #define ADC12_CSR_AWD1_MST_Msk           (0x1UL << ADC12_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
1867 #define ADC12_CSR_AWD1_MST               ADC12_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
1868 #define ADC12_CSR_AWD2_MST_Pos           (8U)
1869 #define ADC12_CSR_AWD2_MST_Msk           (0x1UL << ADC12_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
1870 #define ADC12_CSR_AWD2_MST               ADC12_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
1871 #define ADC12_CSR_AWD3_MST_Pos           (9U)
1872 #define ADC12_CSR_AWD3_MST_Msk           (0x1UL << ADC12_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
1873 #define ADC12_CSR_AWD3_MST               ADC12_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
1874 #define ADC12_CSR_JQOVF_MST_Pos          (10U)
1875 #define ADC12_CSR_JQOVF_MST_Msk          (0x1UL << ADC12_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
1876 #define ADC12_CSR_JQOVF_MST              ADC12_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
1877 #define ADC12_CSR_ADRDY_SLV_Pos          (16U)
1878 #define ADC12_CSR_ADRDY_SLV_Msk          (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
1879 #define ADC12_CSR_ADRDY_SLV              ADC12_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
1880 #define ADC12_CSR_ADRDY_EOSMP_SLV_Pos    (17U)
1881 #define ADC12_CSR_ADRDY_EOSMP_SLV_Msk    (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
1882 #define ADC12_CSR_ADRDY_EOSMP_SLV        ADC12_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
1883 #define ADC12_CSR_ADRDY_EOC_SLV_Pos      (18U)
1884 #define ADC12_CSR_ADRDY_EOC_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
1885 #define ADC12_CSR_ADRDY_EOC_SLV          ADC12_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
1886 #define ADC12_CSR_ADRDY_EOS_SLV_Pos      (19U)
1887 #define ADC12_CSR_ADRDY_EOS_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
1888 #define ADC12_CSR_ADRDY_EOS_SLV          ADC12_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
1889 #define ADC12_CSR_ADRDY_OVR_SLV_Pos      (20U)
1890 #define ADC12_CSR_ADRDY_OVR_SLV_Msk      (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
1891 #define ADC12_CSR_ADRDY_OVR_SLV          ADC12_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
1892 #define ADC12_CSR_ADRDY_JEOC_SLV_Pos     (21U)
1893 #define ADC12_CSR_ADRDY_JEOC_SLV_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
1894 #define ADC12_CSR_ADRDY_JEOC_SLV         ADC12_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
1895 #define ADC12_CSR_ADRDY_JEOS_SLV_Pos     (22U)
1896 #define ADC12_CSR_ADRDY_JEOS_SLV_Msk     (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
1897 #define ADC12_CSR_ADRDY_JEOS_SLV         ADC12_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
1898 #define ADC12_CSR_AWD1_SLV_Pos           (23U)
1899 #define ADC12_CSR_AWD1_SLV_Msk           (0x1UL << ADC12_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
1900 #define ADC12_CSR_AWD1_SLV               ADC12_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
1901 #define ADC12_CSR_AWD2_SLV_Pos           (24U)
1902 #define ADC12_CSR_AWD2_SLV_Msk           (0x1UL << ADC12_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
1903 #define ADC12_CSR_AWD2_SLV               ADC12_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
1904 #define ADC12_CSR_AWD3_SLV_Pos           (25U)
1905 #define ADC12_CSR_AWD3_SLV_Msk           (0x1UL << ADC12_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
1906 #define ADC12_CSR_AWD3_SLV               ADC12_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
1907 #define ADC12_CSR_JQOVF_SLV_Pos          (26U)
1908 #define ADC12_CSR_JQOVF_SLV_Msk          (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
1909 #define ADC12_CSR_JQOVF_SLV              ADC12_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
1910 
1911 /***************  Bit definition for ADC34_COMMON_CSR register  ***************/
1912 #define ADC34_CSR_ADRDY_MST_Pos          (0U)
1913 #define ADC34_CSR_ADRDY_MST_Msk          (0x1UL << ADC34_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
1914 #define ADC34_CSR_ADRDY_MST              ADC34_CSR_ADRDY_MST_Msk               /*!< Master ADC ready */
1915 #define ADC34_CSR_ADRDY_EOSMP_MST_Pos    (1U)
1916 #define ADC34_CSR_ADRDY_EOSMP_MST_Msk    (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos) /*!< 0x00000002 */
1917 #define ADC34_CSR_ADRDY_EOSMP_MST        ADC34_CSR_ADRDY_EOSMP_MST_Msk         /*!< End of sampling phase flag of the master ADC */
1918 #define ADC34_CSR_ADRDY_EOC_MST_Pos      (2U)
1919 #define ADC34_CSR_ADRDY_EOC_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos) /*!< 0x00000004 */
1920 #define ADC34_CSR_ADRDY_EOC_MST          ADC34_CSR_ADRDY_EOC_MST_Msk           /*!< End of regular conversion of the master ADC */
1921 #define ADC34_CSR_ADRDY_EOS_MST_Pos      (3U)
1922 #define ADC34_CSR_ADRDY_EOS_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos) /*!< 0x00000008 */
1923 #define ADC34_CSR_ADRDY_EOS_MST          ADC34_CSR_ADRDY_EOS_MST_Msk           /*!< End of regular sequence flag of the master ADC */
1924 #define ADC34_CSR_ADRDY_OVR_MST_Pos      (4U)
1925 #define ADC34_CSR_ADRDY_OVR_MST_Msk      (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos) /*!< 0x00000010 */
1926 #define ADC34_CSR_ADRDY_OVR_MST          ADC34_CSR_ADRDY_OVR_MST_Msk           /*!< Overrun flag of the master ADC */
1927 #define ADC34_CSR_ADRDY_JEOC_MST_Pos     (5U)
1928 #define ADC34_CSR_ADRDY_JEOC_MST_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos) /*!< 0x00000020 */
1929 #define ADC34_CSR_ADRDY_JEOC_MST         ADC34_CSR_ADRDY_JEOC_MST_Msk          /*!< End of injected conversion of the master ADC */
1930 #define ADC34_CSR_ADRDY_JEOS_MST_Pos     (6U)
1931 #define ADC34_CSR_ADRDY_JEOS_MST_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos) /*!< 0x00000040 */
1932 #define ADC34_CSR_ADRDY_JEOS_MST         ADC34_CSR_ADRDY_JEOS_MST_Msk          /*!< End of injected sequence flag of the master ADC */
1933 #define ADC34_CSR_AWD1_MST_Pos           (7U)
1934 #define ADC34_CSR_AWD1_MST_Msk           (0x1UL << ADC34_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
1935 #define ADC34_CSR_AWD1_MST               ADC34_CSR_AWD1_MST_Msk                /*!< Analog watchdog 1 flag of the master ADC */
1936 #define ADC34_CSR_AWD2_MST_Pos           (8U)
1937 #define ADC34_CSR_AWD2_MST_Msk           (0x1UL << ADC34_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
1938 #define ADC34_CSR_AWD2_MST               ADC34_CSR_AWD2_MST_Msk                /*!< Analog watchdog 2 flag of the master ADC */
1939 #define ADC34_CSR_AWD3_MST_Pos           (9U)
1940 #define ADC34_CSR_AWD3_MST_Msk           (0x1UL << ADC34_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
1941 #define ADC34_CSR_AWD3_MST               ADC34_CSR_AWD3_MST_Msk                /*!< Analog watchdog 3 flag of the master ADC */
1942 #define ADC34_CSR_JQOVF_MST_Pos          (10U)
1943 #define ADC34_CSR_JQOVF_MST_Msk          (0x1UL << ADC34_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
1944 #define ADC34_CSR_JQOVF_MST              ADC34_CSR_JQOVF_MST_Msk               /*!< Injected context queue overflow flag of the master ADC */
1945 #define ADC34_CSR_ADRDY_SLV_Pos          (16U)
1946 #define ADC34_CSR_ADRDY_SLV_Msk          (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
1947 #define ADC34_CSR_ADRDY_SLV              ADC34_CSR_ADRDY_SLV_Msk               /*!< Slave ADC ready */
1948 #define ADC34_CSR_ADRDY_EOSMP_SLV_Pos    (17U)
1949 #define ADC34_CSR_ADRDY_EOSMP_SLV_Msk    (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos) /*!< 0x00020000 */
1950 #define ADC34_CSR_ADRDY_EOSMP_SLV        ADC34_CSR_ADRDY_EOSMP_SLV_Msk         /*!< End of sampling phase flag of the slave ADC */
1951 #define ADC34_CSR_ADRDY_EOC_SLV_Pos      (18U)
1952 #define ADC34_CSR_ADRDY_EOC_SLV_Msk      (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos) /*!< 0x00040000 */
1953 #define ADC34_CSR_ADRDY_EOC_SLV          ADC34_CSR_ADRDY_EOC_SLV_Msk           /*!< End of regular conversion of the slave ADC */
1954 #define ADC34_CSR_ADRDY_EOS_SLV_Pos      (19U)
1955 #define ADC34_CSR_ADRDY_EOS_SLV_Msk      (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos) /*!< 0x00080000 */
1956 #define ADC34_CSR_ADRDY_EOS_SLV          ADC34_CSR_ADRDY_EOS_SLV_Msk           /*!< End of regular sequence flag of the slave ADC */
1957 #define ADC34_CSR_ADRDY_OVR_SLV_Pos      (20U)
1958 #define ADC34_CSR_ADRDY_OVR_SLV_Msk      (0x1UL << ADC34_CSR_ADRDY_OVR_SLV_Pos) /*!< 0x00100000 */
1959 #define ADC34_CSR_ADRDY_OVR_SLV          ADC34_CSR_ADRDY_OVR_SLV_Msk           /*!< Overrun flag of the slave ADC */
1960 #define ADC34_CSR_ADRDY_JEOC_SLV_Pos     (21U)
1961 #define ADC34_CSR_ADRDY_JEOC_SLV_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos) /*!< 0x00200000 */
1962 #define ADC34_CSR_ADRDY_JEOC_SLV         ADC34_CSR_ADRDY_JEOC_SLV_Msk          /*!< End of injected conversion of the slave ADC */
1963 #define ADC34_CSR_ADRDY_JEOS_SLV_Pos     (22U)
1964 #define ADC34_CSR_ADRDY_JEOS_SLV_Msk     (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos) /*!< 0x00400000 */
1965 #define ADC34_CSR_ADRDY_JEOS_SLV         ADC34_CSR_ADRDY_JEOS_SLV_Msk          /*!< End of injected sequence flag of the slave ADC */
1966 #define ADC34_CSR_AWD1_SLV_Pos           (23U)
1967 #define ADC34_CSR_AWD1_SLV_Msk           (0x1UL << ADC34_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
1968 #define ADC34_CSR_AWD1_SLV               ADC34_CSR_AWD1_SLV_Msk                /*!< Analog watchdog 1 flag of the slave ADC */
1969 #define ADC34_CSR_AWD2_SLV_Pos           (24U)
1970 #define ADC34_CSR_AWD2_SLV_Msk           (0x1UL << ADC34_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
1971 #define ADC34_CSR_AWD2_SLV               ADC34_CSR_AWD2_SLV_Msk                /*!< Analog watchdog 2 flag of the slave ADC */
1972 #define ADC34_CSR_AWD3_SLV_Pos           (25U)
1973 #define ADC34_CSR_AWD3_SLV_Msk           (0x1UL << ADC34_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
1974 #define ADC34_CSR_AWD3_SLV               ADC34_CSR_AWD3_SLV_Msk                /*!< Analog watchdog 3 flag of the slave ADC */
1975 #define ADC34_CSR_JQOVF_SLV_Pos          (26U)
1976 #define ADC34_CSR_JQOVF_SLV_Msk          (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
1977 #define ADC34_CSR_JQOVF_SLV              ADC34_CSR_JQOVF_SLV_Msk               /*!< Injected context queue overflow flag of the slave ADC */
1978 
1979 /***************  Bit definition for ADC12_COMMON_CCR register  ***************/
1980 #define ADC12_CCR_MULTI_Pos              (0U)
1981 #define ADC12_CCR_MULTI_Msk              (0x1FUL << ADC12_CCR_MULTI_Pos)        /*!< 0x0000001F */
1982 #define ADC12_CCR_MULTI                  ADC12_CCR_MULTI_Msk                   /*!< Multi ADC mode selection */
1983 #define ADC12_CCR_MULTI_0                (0x01UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000001 */
1984 #define ADC12_CCR_MULTI_1                (0x02UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000002 */
1985 #define ADC12_CCR_MULTI_2                (0x04UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000004 */
1986 #define ADC12_CCR_MULTI_3                (0x08UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000008 */
1987 #define ADC12_CCR_MULTI_4                (0x10UL << ADC12_CCR_MULTI_Pos)        /*!< 0x00000010 */
1988 #define ADC12_CCR_DELAY_Pos              (8U)
1989 #define ADC12_CCR_DELAY_Msk              (0xFUL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000F00 */
1990 #define ADC12_CCR_DELAY                  ADC12_CCR_DELAY_Msk                   /*!< Delay between 2 sampling phases */
1991 #define ADC12_CCR_DELAY_0                (0x1UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000100 */
1992 #define ADC12_CCR_DELAY_1                (0x2UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000200 */
1993 #define ADC12_CCR_DELAY_2                (0x4UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000400 */
1994 #define ADC12_CCR_DELAY_3                (0x8UL << ADC12_CCR_DELAY_Pos)         /*!< 0x00000800 */
1995 #define ADC12_CCR_DMACFG_Pos             (13U)
1996 #define ADC12_CCR_DMACFG_Msk             (0x1UL << ADC12_CCR_DMACFG_Pos)        /*!< 0x00002000 */
1997 #define ADC12_CCR_DMACFG                 ADC12_CCR_DMACFG_Msk                  /*!< DMA configuration for multi-ADC mode */
1998 #define ADC12_CCR_MDMA_Pos               (14U)
1999 #define ADC12_CCR_MDMA_Msk               (0x3UL << ADC12_CCR_MDMA_Pos)          /*!< 0x0000C000 */
2000 #define ADC12_CCR_MDMA                   ADC12_CCR_MDMA_Msk                    /*!< DMA mode for multi-ADC mode */
2001 #define ADC12_CCR_MDMA_0                 (0x1UL << ADC12_CCR_MDMA_Pos)          /*!< 0x00004000 */
2002 #define ADC12_CCR_MDMA_1                 (0x2UL << ADC12_CCR_MDMA_Pos)          /*!< 0x00008000 */
2003 #define ADC12_CCR_CKMODE_Pos             (16U)
2004 #define ADC12_CCR_CKMODE_Msk             (0x3UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00030000 */
2005 #define ADC12_CCR_CKMODE                 ADC12_CCR_CKMODE_Msk                  /*!< ADC clock mode */
2006 #define ADC12_CCR_CKMODE_0               (0x1UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00010000 */
2007 #define ADC12_CCR_CKMODE_1               (0x2UL << ADC12_CCR_CKMODE_Pos)        /*!< 0x00020000 */
2008 #define ADC12_CCR_VREFEN_Pos             (22U)
2009 #define ADC12_CCR_VREFEN_Msk             (0x1UL << ADC12_CCR_VREFEN_Pos)        /*!< 0x00400000 */
2010 #define ADC12_CCR_VREFEN                 ADC12_CCR_VREFEN_Msk                  /*!< VREFINT enable */
2011 #define ADC12_CCR_TSEN_Pos               (23U)
2012 #define ADC12_CCR_TSEN_Msk               (0x1UL << ADC12_CCR_TSEN_Pos)          /*!< 0x00800000 */
2013 #define ADC12_CCR_TSEN                   ADC12_CCR_TSEN_Msk                    /*!< Temperature sensor enable */
2014 #define ADC12_CCR_VBATEN_Pos             (24U)
2015 #define ADC12_CCR_VBATEN_Msk             (0x1UL << ADC12_CCR_VBATEN_Pos)        /*!< 0x01000000 */
2016 #define ADC12_CCR_VBATEN                 ADC12_CCR_VBATEN_Msk                  /*!< VBAT enable */
2017 
2018 /***************  Bit definition for ADC34_COMMON_CCR register  ***************/
2019 #define ADC34_CCR_MULTI_Pos              (0U)
2020 #define ADC34_CCR_MULTI_Msk              (0x1FUL << ADC34_CCR_MULTI_Pos)        /*!< 0x0000001F */
2021 #define ADC34_CCR_MULTI                  ADC34_CCR_MULTI_Msk                   /*!< Multi ADC mode selection */
2022 #define ADC34_CCR_MULTI_0                (0x01UL << ADC34_CCR_MULTI_Pos)        /*!< 0x00000001 */
2023 #define ADC34_CCR_MULTI_1                (0x02UL << ADC34_CCR_MULTI_Pos)        /*!< 0x00000002 */
2024 #define ADC34_CCR_MULTI_2                (0x04UL << ADC34_CCR_MULTI_Pos)        /*!< 0x00000004 */
2025 #define ADC34_CCR_MULTI_3                (0x08UL << ADC34_CCR_MULTI_Pos)        /*!< 0x00000008 */
2026 #define ADC34_CCR_MULTI_4                (0x10UL << ADC34_CCR_MULTI_Pos)        /*!< 0x00000010 */
2027 
2028 #define ADC34_CCR_DELAY_Pos              (8U)
2029 #define ADC34_CCR_DELAY_Msk              (0xFUL << ADC34_CCR_DELAY_Pos)         /*!< 0x00000F00 */
2030 #define ADC34_CCR_DELAY                  ADC34_CCR_DELAY_Msk                   /*!< Delay between 2 sampling phases */
2031 #define ADC34_CCR_DELAY_0                (0x1UL << ADC34_CCR_DELAY_Pos)         /*!< 0x00000100 */
2032 #define ADC34_CCR_DELAY_1                (0x2UL << ADC34_CCR_DELAY_Pos)         /*!< 0x00000200 */
2033 #define ADC34_CCR_DELAY_2                (0x4UL << ADC34_CCR_DELAY_Pos)         /*!< 0x00000400 */
2034 #define ADC34_CCR_DELAY_3                (0x8UL << ADC34_CCR_DELAY_Pos)         /*!< 0x00000800 */
2035 
2036 #define ADC34_CCR_DMACFG_Pos             (13U)
2037 #define ADC34_CCR_DMACFG_Msk             (0x1UL << ADC34_CCR_DMACFG_Pos)        /*!< 0x00002000 */
2038 #define ADC34_CCR_DMACFG                 ADC34_CCR_DMACFG_Msk                  /*!< DMA configuration for multi-ADC mode */
2039 #define ADC34_CCR_MDMA_Pos               (14U)
2040 #define ADC34_CCR_MDMA_Msk               (0x3UL << ADC34_CCR_MDMA_Pos)          /*!< 0x0000C000 */
2041 #define ADC34_CCR_MDMA                   ADC34_CCR_MDMA_Msk                    /*!< DMA mode for multi-ADC mode */
2042 #define ADC34_CCR_MDMA_0                 (0x1UL << ADC34_CCR_MDMA_Pos)          /*!< 0x00004000 */
2043 #define ADC34_CCR_MDMA_1                 (0x2UL << ADC34_CCR_MDMA_Pos)          /*!< 0x00008000 */
2044 
2045 #define ADC34_CCR_CKMODE_Pos             (16U)
2046 #define ADC34_CCR_CKMODE_Msk             (0x3UL << ADC34_CCR_CKMODE_Pos)        /*!< 0x00030000 */
2047 #define ADC34_CCR_CKMODE                 ADC34_CCR_CKMODE_Msk                  /*!< ADC clock mode */
2048 #define ADC34_CCR_CKMODE_0               (0x1UL << ADC34_CCR_CKMODE_Pos)        /*!< 0x00010000 */
2049 #define ADC34_CCR_CKMODE_1               (0x2UL << ADC34_CCR_CKMODE_Pos)        /*!< 0x00020000 */
2050 
2051 #define ADC34_CCR_VREFEN_Pos             (22U)
2052 #define ADC34_CCR_VREFEN_Msk             (0x1UL << ADC34_CCR_VREFEN_Pos)        /*!< 0x00400000 */
2053 #define ADC34_CCR_VREFEN                 ADC34_CCR_VREFEN_Msk                  /*!< VREFINT enable */
2054 #define ADC34_CCR_TSEN_Pos               (23U)
2055 #define ADC34_CCR_TSEN_Msk               (0x1UL << ADC34_CCR_TSEN_Pos)          /*!< 0x00800000 */
2056 #define ADC34_CCR_TSEN                   ADC34_CCR_TSEN_Msk                    /*!< Temperature sensor enable */
2057 #define ADC34_CCR_VBATEN_Pos             (24U)
2058 #define ADC34_CCR_VBATEN_Msk             (0x1UL << ADC34_CCR_VBATEN_Pos)        /*!< 0x01000000 */
2059 #define ADC34_CCR_VBATEN                 ADC34_CCR_VBATEN_Msk                  /*!< VBAT enable */
2060 
2061 /***************  Bit definition for ADC12_COMMON_CDR register  ***************/
2062 #define ADC12_CDR_RDATA_MST_Pos          (0U)
2063 #define ADC12_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x0000FFFF */
2064 #define ADC12_CDR_RDATA_MST              ADC12_CDR_RDATA_MST_Msk               /*!< Regular Data of the master ADC */
2065 #define ADC12_CDR_RDATA_MST_0            (0x0001UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000001 */
2066 #define ADC12_CDR_RDATA_MST_1            (0x0002UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000002 */
2067 #define ADC12_CDR_RDATA_MST_2            (0x0004UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000004 */
2068 #define ADC12_CDR_RDATA_MST_3            (0x0008UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000008 */
2069 #define ADC12_CDR_RDATA_MST_4            (0x0010UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000010 */
2070 #define ADC12_CDR_RDATA_MST_5            (0x0020UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000020 */
2071 #define ADC12_CDR_RDATA_MST_6            (0x0040UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000040 */
2072 #define ADC12_CDR_RDATA_MST_7            (0x0080UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000080 */
2073 #define ADC12_CDR_RDATA_MST_8            (0x0100UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000100 */
2074 #define ADC12_CDR_RDATA_MST_9            (0x0200UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000200 */
2075 #define ADC12_CDR_RDATA_MST_10           (0x0400UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000400 */
2076 #define ADC12_CDR_RDATA_MST_11           (0x0800UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00000800 */
2077 #define ADC12_CDR_RDATA_MST_12           (0x1000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00001000 */
2078 #define ADC12_CDR_RDATA_MST_13           (0x2000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00002000 */
2079 #define ADC12_CDR_RDATA_MST_14           (0x4000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00004000 */
2080 #define ADC12_CDR_RDATA_MST_15           (0x8000UL << ADC12_CDR_RDATA_MST_Pos)  /*!< 0x00008000 */
2081 
2082 #define ADC12_CDR_RDATA_SLV_Pos          (16U)
2083 #define ADC12_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0xFFFF0000 */
2084 #define ADC12_CDR_RDATA_SLV              ADC12_CDR_RDATA_SLV_Msk               /*!< Regular Data of the master ADC */
2085 #define ADC12_CDR_RDATA_SLV_0            (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00010000 */
2086 #define ADC12_CDR_RDATA_SLV_1            (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00020000 */
2087 #define ADC12_CDR_RDATA_SLV_2            (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00040000 */
2088 #define ADC12_CDR_RDATA_SLV_3            (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00080000 */
2089 #define ADC12_CDR_RDATA_SLV_4            (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00100000 */
2090 #define ADC12_CDR_RDATA_SLV_5            (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00200000 */
2091 #define ADC12_CDR_RDATA_SLV_6            (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00400000 */
2092 #define ADC12_CDR_RDATA_SLV_7            (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x00800000 */
2093 #define ADC12_CDR_RDATA_SLV_8            (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x01000000 */
2094 #define ADC12_CDR_RDATA_SLV_9            (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x02000000 */
2095 #define ADC12_CDR_RDATA_SLV_10           (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x04000000 */
2096 #define ADC12_CDR_RDATA_SLV_11           (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x08000000 */
2097 #define ADC12_CDR_RDATA_SLV_12           (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x10000000 */
2098 #define ADC12_CDR_RDATA_SLV_13           (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x20000000 */
2099 #define ADC12_CDR_RDATA_SLV_14           (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x40000000 */
2100 #define ADC12_CDR_RDATA_SLV_15           (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)  /*!< 0x80000000 */
2101 
2102 /***************  Bit definition for ADC34_COMMON_CDR register  ***************/
2103 #define ADC34_CDR_RDATA_MST_Pos          (0U)
2104 #define ADC34_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x0000FFFF */
2105 #define ADC34_CDR_RDATA_MST              ADC34_CDR_RDATA_MST_Msk               /*!< Regular Data of the master ADC */
2106 #define ADC34_CDR_RDATA_MST_0            (0x0001UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000001 */
2107 #define ADC34_CDR_RDATA_MST_1            (0x0002UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000002 */
2108 #define ADC34_CDR_RDATA_MST_2            (0x0004UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000004 */
2109 #define ADC34_CDR_RDATA_MST_3            (0x0008UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000008 */
2110 #define ADC34_CDR_RDATA_MST_4            (0x0010UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000010 */
2111 #define ADC34_CDR_RDATA_MST_5            (0x0020UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000020 */
2112 #define ADC34_CDR_RDATA_MST_6            (0x0040UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000040 */
2113 #define ADC34_CDR_RDATA_MST_7            (0x0080UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000080 */
2114 #define ADC34_CDR_RDATA_MST_8            (0x0100UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000100 */
2115 #define ADC34_CDR_RDATA_MST_9            (0x0200UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000200 */
2116 #define ADC34_CDR_RDATA_MST_10           (0x0400UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000400 */
2117 #define ADC34_CDR_RDATA_MST_11           (0x0800UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00000800 */
2118 #define ADC34_CDR_RDATA_MST_12           (0x1000UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00001000 */
2119 #define ADC34_CDR_RDATA_MST_13           (0x2000UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00002000 */
2120 #define ADC34_CDR_RDATA_MST_14           (0x4000UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00004000 */
2121 #define ADC34_CDR_RDATA_MST_15           (0x8000UL << ADC34_CDR_RDATA_MST_Pos)  /*!< 0x00008000 */
2122 
2123 #define ADC34_CDR_RDATA_SLV_Pos          (16U)
2124 #define ADC34_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0xFFFF0000 */
2125 #define ADC34_CDR_RDATA_SLV              ADC34_CDR_RDATA_SLV_Msk               /*!< Regular Data of the master ADC */
2126 #define ADC34_CDR_RDATA_SLV_0            (0x0001UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00010000 */
2127 #define ADC34_CDR_RDATA_SLV_1            (0x0002UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00020000 */
2128 #define ADC34_CDR_RDATA_SLV_2            (0x0004UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00040000 */
2129 #define ADC34_CDR_RDATA_SLV_3            (0x0008UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00080000 */
2130 #define ADC34_CDR_RDATA_SLV_4            (0x0010UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00100000 */
2131 #define ADC34_CDR_RDATA_SLV_5            (0x0020UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00200000 */
2132 #define ADC34_CDR_RDATA_SLV_6            (0x0040UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00400000 */
2133 #define ADC34_CDR_RDATA_SLV_7            (0x0080UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x00800000 */
2134 #define ADC34_CDR_RDATA_SLV_8            (0x0100UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x01000000 */
2135 #define ADC34_CDR_RDATA_SLV_9            (0x0200UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x02000000 */
2136 #define ADC34_CDR_RDATA_SLV_10           (0x0400UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x04000000 */
2137 #define ADC34_CDR_RDATA_SLV_11           (0x0800UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x08000000 */
2138 #define ADC34_CDR_RDATA_SLV_12           (0x1000UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x10000000 */
2139 #define ADC34_CDR_RDATA_SLV_13           (0x2000UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x20000000 */
2140 #define ADC34_CDR_RDATA_SLV_14           (0x4000UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x40000000 */
2141 #define ADC34_CDR_RDATA_SLV_15           (0x8000UL << ADC34_CDR_RDATA_SLV_Pos)  /*!< 0x80000000 */
2142 
2143 /********************  Bit definition for ADC_CSR register  *******************/
2144 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2145 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
2146 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2147 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2148 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
2149 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2150 #define ADC_CSR_EOC_MST_Pos            (2U)
2151 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
2152 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2153 #define ADC_CSR_EOS_MST_Pos            (3U)
2154 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
2155 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2156 #define ADC_CSR_OVR_MST_Pos            (4U)
2157 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
2158 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2159 #define ADC_CSR_JEOC_MST_Pos           (5U)
2160 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
2161 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2162 #define ADC_CSR_JEOS_MST_Pos           (6U)
2163 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
2164 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2165 #define ADC_CSR_AWD1_MST_Pos           (7U)
2166 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
2167 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2168 #define ADC_CSR_AWD2_MST_Pos           (8U)
2169 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
2170 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2171 #define ADC_CSR_AWD3_MST_Pos           (9U)
2172 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
2173 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2174 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2175 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
2176 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2177 
2178 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2179 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
2180 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2181 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2182 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
2183 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2184 #define ADC_CSR_EOC_SLV_Pos            (18U)
2185 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
2186 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2187 #define ADC_CSR_EOS_SLV_Pos            (19U)
2188 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
2189 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2190 #define ADC_CSR_OVR_SLV_Pos            (20U)
2191 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
2192 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2193 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2194 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
2195 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2196 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2197 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
2198 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2199 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2200 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
2201 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2202 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2203 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
2204 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2205 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2206 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
2207 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2208 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2209 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
2210 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2211 
2212 /* Legacy defines */
2213 #define ADC_CSR_ADRDY_EOSMP_MST   ADC_CSR_EOSMP_MST
2214 #define ADC_CSR_ADRDY_EOC_MST     ADC_CSR_EOC_MST
2215 #define ADC_CSR_ADRDY_EOS_MST     ADC_CSR_EOS_MST
2216 #define ADC_CSR_ADRDY_OVR_MST     ADC_CSR_OVR_MST
2217 #define ADC_CSR_ADRDY_JEOC_MST    ADC_CSR_JEOC_MST
2218 #define ADC_CSR_ADRDY_JEOS_MST    ADC_CSR_JEOS_MST
2219 
2220 #define ADC_CSR_ADRDY_EOSMP_SLV   ADC_CSR_EOSMP_SLV
2221 #define ADC_CSR_ADRDY_EOC_SLV     ADC_CSR_EOC_SLV
2222 #define ADC_CSR_ADRDY_EOS_SLV     ADC_CSR_EOS_SLV
2223 #define ADC_CSR_ADRDY_OVR_SLV     ADC_CSR_OVR_SLV
2224 #define ADC_CSR_ADRDY_JEOC_SLV    ADC_CSR_JEOC_SLV
2225 #define ADC_CSR_ADRDY_JEOS_SLV    ADC_CSR_JEOS_SLV
2226 
2227 /********************  Bit definition for ADC_CCR register  *******************/
2228 #define ADC_CCR_DUAL_Pos               (0U)
2229 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
2230 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2231 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
2232 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
2233 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
2234 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
2235 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
2236 
2237 #define ADC_CCR_DELAY_Pos              (8U)
2238 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
2239 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2240 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
2241 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
2242 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
2243 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
2244 
2245 #define ADC_CCR_DMACFG_Pos             (13U)
2246 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
2247 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2248 
2249 #define ADC_CCR_MDMA_Pos               (14U)
2250 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
2251 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2252 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
2253 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
2254 
2255 #define ADC_CCR_CKMODE_Pos             (16U)
2256 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
2257 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2258 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
2259 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
2260 
2261 #define ADC_CCR_VREFEN_Pos             (22U)
2262 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
2263 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2264 #define ADC_CCR_TSEN_Pos               (23U)
2265 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
2266 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2267 #define ADC_CCR_VBATEN_Pos             (24U)
2268 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
2269 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2270 
2271 /* Legacy defines */
2272 #define ADC_CCR_MULTI           (ADC_CCR_DUAL)
2273 #define ADC_CCR_MULTI_0         (ADC_CCR_DUAL_0)
2274 #define ADC_CCR_MULTI_1         (ADC_CCR_DUAL_1)
2275 #define ADC_CCR_MULTI_2         (ADC_CCR_DUAL_2)
2276 #define ADC_CCR_MULTI_3         (ADC_CCR_DUAL_3)
2277 #define ADC_CCR_MULTI_4         (ADC_CCR_DUAL_4)
2278 
2279 /********************  Bit definition for ADC_CDR register  *******************/
2280 #define ADC_CDR_RDATA_MST_Pos          (0U)
2281 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
2282 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2283 #define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
2284 #define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
2285 #define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
2286 #define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
2287 #define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
2288 #define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
2289 #define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
2290 #define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
2291 #define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
2292 #define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
2293 #define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
2294 #define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
2295 #define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
2296 #define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
2297 #define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
2298 #define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
2299 
2300 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2301 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
2302 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2303 #define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
2304 #define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
2305 #define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
2306 #define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
2307 #define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
2308 #define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
2309 #define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
2310 #define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
2311 #define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
2312 #define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
2313 #define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
2314 #define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
2315 #define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
2316 #define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
2317 #define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
2318 #define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
2319 
2320 /******************************************************************************/
2321 /*                                                                            */
2322 /*                      Analog Comparators (COMP)                             */
2323 /*                                                                            */
2324 /******************************************************************************/
2325 
2326 #define COMP_V1_3_0_0                                  /*!< Comparator IP version */
2327 
2328 /**********************  Bit definition for COMP1_CSR register  ***************/
2329 #define COMP1_CSR_COMP1EN_Pos            (0U)
2330 #define COMP1_CSR_COMP1EN_Msk            (0x1UL << COMP1_CSR_COMP1EN_Pos)       /*!< 0x00000001 */
2331 #define COMP1_CSR_COMP1EN                COMP1_CSR_COMP1EN_Msk                 /*!< COMP1 enable */
2332 #define COMP1_CSR_COMP1SW1_Pos           (1U)
2333 #define COMP1_CSR_COMP1SW1_Msk           (0x1UL << COMP1_CSR_COMP1SW1_Pos)      /*!< 0x00000002 */
2334 #define COMP1_CSR_COMP1SW1               COMP1_CSR_COMP1SW1_Msk                /*!< COMP1 SW1 switch control */
2335 /* Legacy defines */
2336 #define COMP_CSR_COMP1SW1                COMP1_CSR_COMP1SW1
2337 #define COMP1_CSR_COMP1MODE_Pos          (2U)
2338 #define COMP1_CSR_COMP1MODE_Msk          (0x3UL << COMP1_CSR_COMP1MODE_Pos)     /*!< 0x0000000C */
2339 #define COMP1_CSR_COMP1MODE              COMP1_CSR_COMP1MODE_Msk               /*!< COMP1 power mode */
2340 #define COMP1_CSR_COMP1MODE_0            (0x1UL << COMP1_CSR_COMP1MODE_Pos)     /*!< 0x00000004 */
2341 #define COMP1_CSR_COMP1MODE_1            (0x2UL << COMP1_CSR_COMP1MODE_Pos)     /*!< 0x00000008 */
2342 #define COMP1_CSR_COMP1INSEL_Pos         (4U)
2343 #define COMP1_CSR_COMP1INSEL_Msk         (0x7UL << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000070 */
2344 #define COMP1_CSR_COMP1INSEL             COMP1_CSR_COMP1INSEL_Msk              /*!< COMP1 inverting input select */
2345 #define COMP1_CSR_COMP1INSEL_0           (0x1UL << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000010 */
2346 #define COMP1_CSR_COMP1INSEL_1           (0x2UL << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000020 */
2347 #define COMP1_CSR_COMP1INSEL_2           (0x4UL << COMP1_CSR_COMP1INSEL_Pos)    /*!< 0x00000040 */
2348 #define COMP1_CSR_COMP1OUTSEL_Pos        (10U)
2349 #define COMP1_CSR_COMP1OUTSEL_Msk        (0xFUL << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00003C00 */
2350 #define COMP1_CSR_COMP1OUTSEL            COMP1_CSR_COMP1OUTSEL_Msk             /*!< COMP1 output select */
2351 #define COMP1_CSR_COMP1OUTSEL_0          (0x1UL << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00000400 */
2352 #define COMP1_CSR_COMP1OUTSEL_1          (0x2UL << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00000800 */
2353 #define COMP1_CSR_COMP1OUTSEL_2          (0x4UL << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00001000 */
2354 #define COMP1_CSR_COMP1OUTSEL_3          (0x8UL << COMP1_CSR_COMP1OUTSEL_Pos)   /*!< 0x00002000 */
2355 #define COMP1_CSR_COMP1POL_Pos           (15U)
2356 #define COMP1_CSR_COMP1POL_Msk           (0x1UL << COMP1_CSR_COMP1POL_Pos)      /*!< 0x00008000 */
2357 #define COMP1_CSR_COMP1POL               COMP1_CSR_COMP1POL_Msk                /*!< COMP1 output polarity */
2358 #define COMP1_CSR_COMP1HYST_Pos          (16U)
2359 #define COMP1_CSR_COMP1HYST_Msk          (0x3UL << COMP1_CSR_COMP1HYST_Pos)     /*!< 0x00030000 */
2360 #define COMP1_CSR_COMP1HYST              COMP1_CSR_COMP1HYST_Msk               /*!< COMP1 hysteresis */
2361 #define COMP1_CSR_COMP1HYST_0            (0x1UL << COMP1_CSR_COMP1HYST_Pos)     /*!< 0x00010000 */
2362 #define COMP1_CSR_COMP1HYST_1            (0x2UL << COMP1_CSR_COMP1HYST_Pos)     /*!< 0x00020000 */
2363 #define COMP1_CSR_COMP1BLANKING_Pos      (18U)
2364 #define COMP1_CSR_COMP1BLANKING_Msk      (0x3UL << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x000C0000 */
2365 #define COMP1_CSR_COMP1BLANKING          COMP1_CSR_COMP1BLANKING_Msk           /*!< COMP1 blanking */
2366 #define COMP1_CSR_COMP1BLANKING_0        (0x1UL << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00040000 */
2367 #define COMP1_CSR_COMP1BLANKING_1        (0x2UL << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00080000 */
2368 #define COMP1_CSR_COMP1BLANKING_2        (0x4UL << COMP1_CSR_COMP1BLANKING_Pos) /*!< 0x00100000 */
2369 #define COMP1_CSR_COMP1OUT_Pos           (30U)
2370 #define COMP1_CSR_COMP1OUT_Msk           (0x1UL << COMP1_CSR_COMP1OUT_Pos)      /*!< 0x40000000 */
2371 #define COMP1_CSR_COMP1OUT               COMP1_CSR_COMP1OUT_Msk                /*!< COMP1 output level */
2372 #define COMP1_CSR_COMP1LOCK_Pos          (31U)
2373 #define COMP1_CSR_COMP1LOCK_Msk          (0x1UL << COMP1_CSR_COMP1LOCK_Pos)     /*!< 0x80000000 */
2374 #define COMP1_CSR_COMP1LOCK              COMP1_CSR_COMP1LOCK_Msk               /*!< COMP1 lock */
2375 
2376 /**********************  Bit definition for COMP2_CSR register  ***************/
2377 #define COMP2_CSR_COMP2EN_Pos            (0U)
2378 #define COMP2_CSR_COMP2EN_Msk            (0x1UL << COMP2_CSR_COMP2EN_Pos)       /*!< 0x00000001 */
2379 #define COMP2_CSR_COMP2EN                COMP2_CSR_COMP2EN_Msk                 /*!< COMP2 enable */
2380 #define COMP2_CSR_COMP2MODE_Pos          (2U)
2381 #define COMP2_CSR_COMP2MODE_Msk          (0x3UL << COMP2_CSR_COMP2MODE_Pos)     /*!< 0x0000000C */
2382 #define COMP2_CSR_COMP2MODE              COMP2_CSR_COMP2MODE_Msk               /*!< COMP2 power mode */
2383 #define COMP2_CSR_COMP2MODE_0            (0x1UL << COMP2_CSR_COMP2MODE_Pos)     /*!< 0x00000004 */
2384 #define COMP2_CSR_COMP2MODE_1            (0x2UL << COMP2_CSR_COMP2MODE_Pos)     /*!< 0x00000008 */
2385 #define COMP2_CSR_COMP2INSEL_Pos         (4U)
2386 #define COMP2_CSR_COMP2INSEL_Msk         (0x7UL << COMP2_CSR_COMP2INSEL_Pos)    /*!< 0x00000070 */
2387 #define COMP2_CSR_COMP2INSEL             COMP2_CSR_COMP2INSEL_Msk              /*!< COMP2 inverting input select */
2388 #define COMP2_CSR_COMP2INSEL_0           (0x00000010U)                         /*!< COMP2 inverting input select bit 0 */
2389 #define COMP2_CSR_COMP2INSEL_1           (0x00000020U)                         /*!< COMP2 inverting input select bit 1 */
2390 #define COMP2_CSR_COMP2INSEL_2           (0x00000040U)                         /*!< COMP2 inverting input select bit 2 */
2391 #define COMP2_CSR_COMP2NONINSEL_Pos      (7U)
2392 #define COMP2_CSR_COMP2NONINSEL_Msk      (0x1UL << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
2393 #define COMP2_CSR_COMP2NONINSEL          COMP2_CSR_COMP2NONINSEL_Msk           /*!< COMP2 non inverting input select */
2394 #define COMP2_CSR_COMP2WNDWEN_Pos        (9U)
2395 #define COMP2_CSR_COMP2WNDWEN_Msk        (0x1UL << COMP2_CSR_COMP2WNDWEN_Pos)   /*!< 0x00000200 */
2396 #define COMP2_CSR_COMP2WNDWEN            COMP2_CSR_COMP2WNDWEN_Msk             /*!< COMP2 window mode enable */
2397 #define COMP2_CSR_COMP2OUTSEL_Pos        (10U)
2398 #define COMP2_CSR_COMP2OUTSEL_Msk        (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00003C00 */
2399 #define COMP2_CSR_COMP2OUTSEL            COMP2_CSR_COMP2OUTSEL_Msk             /*!< COMP2 output select */
2400 #define COMP2_CSR_COMP2OUTSEL_0          (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000400 */
2401 #define COMP2_CSR_COMP2OUTSEL_1          (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00000800 */
2402 #define COMP2_CSR_COMP2OUTSEL_2          (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00001000 */
2403 #define COMP2_CSR_COMP2OUTSEL_3          (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)   /*!< 0x00002000 */
2404 #define COMP2_CSR_COMP2POL_Pos           (15U)
2405 #define COMP2_CSR_COMP2POL_Msk           (0x1UL << COMP2_CSR_COMP2POL_Pos)      /*!< 0x00008000 */
2406 #define COMP2_CSR_COMP2POL               COMP2_CSR_COMP2POL_Msk                /*!< COMP2 output polarity */
2407 #define COMP2_CSR_COMP2HYST_Pos          (16U)
2408 #define COMP2_CSR_COMP2HYST_Msk          (0x3UL << COMP2_CSR_COMP2HYST_Pos)     /*!< 0x00030000 */
2409 #define COMP2_CSR_COMP2HYST              COMP2_CSR_COMP2HYST_Msk               /*!< COMP2 hysteresis */
2410 #define COMP2_CSR_COMP2HYST_0            (0x1UL << COMP2_CSR_COMP2HYST_Pos)     /*!< 0x00010000 */
2411 #define COMP2_CSR_COMP2HYST_1            (0x2UL << COMP2_CSR_COMP2HYST_Pos)     /*!< 0x00020000 */
2412 #define COMP2_CSR_COMP2BLANKING_Pos      (18U)
2413 #define COMP2_CSR_COMP2BLANKING_Msk      (0x3UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x000C0000 */
2414 #define COMP2_CSR_COMP2BLANKING          COMP2_CSR_COMP2BLANKING_Msk           /*!< COMP2 blanking */
2415 #define COMP2_CSR_COMP2BLANKING_0        (0x1UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00040000 */
2416 #define COMP2_CSR_COMP2BLANKING_1        (0x2UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00080000 */
2417 #define COMP2_CSR_COMP2BLANKING_2        (0x4UL << COMP2_CSR_COMP2BLANKING_Pos) /*!< 0x00100000 */
2418 #define COMP2_CSR_COMP2OUT_Pos           (30U)
2419 #define COMP2_CSR_COMP2OUT_Msk           (0x1UL << COMP2_CSR_COMP2OUT_Pos)      /*!< 0x40000000 */
2420 #define COMP2_CSR_COMP2OUT               COMP2_CSR_COMP2OUT_Msk                /*!< COMP2 output level */
2421 #define COMP2_CSR_COMP2LOCK_Pos          (31U)
2422 #define COMP2_CSR_COMP2LOCK_Msk          (0x1UL << COMP2_CSR_COMP2LOCK_Pos)     /*!< 0x80000000 */
2423 #define COMP2_CSR_COMP2LOCK              COMP2_CSR_COMP2LOCK_Msk               /*!< COMP2 lock */
2424 
2425 /**********************  Bit definition for COMP3_CSR register  ***************/
2426 #define COMP3_CSR_COMP3EN_Pos            (0U)
2427 #define COMP3_CSR_COMP3EN_Msk            (0x1UL << COMP3_CSR_COMP3EN_Pos)       /*!< 0x00000001 */
2428 #define COMP3_CSR_COMP3EN                COMP3_CSR_COMP3EN_Msk                 /*!< COMP3 enable */
2429 #define COMP3_CSR_COMP3MODE_Pos          (2U)
2430 #define COMP3_CSR_COMP3MODE_Msk          (0x3UL << COMP3_CSR_COMP3MODE_Pos)     /*!< 0x0000000C */
2431 #define COMP3_CSR_COMP3MODE              COMP3_CSR_COMP3MODE_Msk               /*!< COMP3 power mode */
2432 #define COMP3_CSR_COMP3MODE_0            (0x1UL << COMP3_CSR_COMP3MODE_Pos)     /*!< 0x00000004 */
2433 #define COMP3_CSR_COMP3MODE_1            (0x2UL << COMP3_CSR_COMP3MODE_Pos)     /*!< 0x00000008 */
2434 #define COMP3_CSR_COMP3INSEL_Pos         (4U)
2435 #define COMP3_CSR_COMP3INSEL_Msk         (0x7UL << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000070 */
2436 #define COMP3_CSR_COMP3INSEL             COMP3_CSR_COMP3INSEL_Msk              /*!< COMP3 inverting input select */
2437 #define COMP3_CSR_COMP3INSEL_0           (0x1UL << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000010 */
2438 #define COMP3_CSR_COMP3INSEL_1           (0x2UL << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000020 */
2439 #define COMP3_CSR_COMP3INSEL_2           (0x4UL << COMP3_CSR_COMP3INSEL_Pos)    /*!< 0x00000040 */
2440 #define COMP3_CSR_COMP3NONINSEL_Pos      (7U)
2441 #define COMP3_CSR_COMP3NONINSEL_Msk      (0x1UL << COMP3_CSR_COMP3NONINSEL_Pos) /*!< 0x00000080 */
2442 #define COMP3_CSR_COMP3NONINSEL          COMP3_CSR_COMP3NONINSEL_Msk           /*!< COMP3 non inverting input select */
2443 #define COMP3_CSR_COMP3OUTSEL_Pos        (10U)
2444 #define COMP3_CSR_COMP3OUTSEL_Msk        (0xFUL << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00003C00 */
2445 #define COMP3_CSR_COMP3OUTSEL            COMP3_CSR_COMP3OUTSEL_Msk             /*!< COMP3 output select */
2446 #define COMP3_CSR_COMP3OUTSEL_0          (0x1UL << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00000400 */
2447 #define COMP3_CSR_COMP3OUTSEL_1          (0x2UL << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00000800 */
2448 #define COMP3_CSR_COMP3OUTSEL_2          (0x4UL << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00001000 */
2449 #define COMP3_CSR_COMP3OUTSEL_3          (0x8UL << COMP3_CSR_COMP3OUTSEL_Pos)   /*!< 0x00002000 */
2450 #define COMP3_CSR_COMP3POL_Pos           (15U)
2451 #define COMP3_CSR_COMP3POL_Msk           (0x1UL << COMP3_CSR_COMP3POL_Pos)      /*!< 0x00008000 */
2452 #define COMP3_CSR_COMP3POL               COMP3_CSR_COMP3POL_Msk                /*!< COMP3 output polarity */
2453 #define COMP3_CSR_COMP3HYST_Pos          (16U)
2454 #define COMP3_CSR_COMP3HYST_Msk          (0x3UL << COMP3_CSR_COMP3HYST_Pos)     /*!< 0x00030000 */
2455 #define COMP3_CSR_COMP3HYST              COMP3_CSR_COMP3HYST_Msk               /*!< COMP3 hysteresis */
2456 #define COMP3_CSR_COMP3HYST_0            (0x1UL << COMP3_CSR_COMP3HYST_Pos)     /*!< 0x00010000 */
2457 #define COMP3_CSR_COMP3HYST_1            (0x2UL << COMP3_CSR_COMP3HYST_Pos)     /*!< 0x00020000 */
2458 #define COMP3_CSR_COMP3BLANKING_Pos      (18U)
2459 #define COMP3_CSR_COMP3BLANKING_Msk      (0x3UL << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x000C0000 */
2460 #define COMP3_CSR_COMP3BLANKING          COMP3_CSR_COMP3BLANKING_Msk           /*!< COMP3 blanking */
2461 #define COMP3_CSR_COMP3BLANKING_0        (0x1UL << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00040000 */
2462 #define COMP3_CSR_COMP3BLANKING_1        (0x2UL << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00080000 */
2463 #define COMP3_CSR_COMP3BLANKING_2        (0x4UL << COMP3_CSR_COMP3BLANKING_Pos) /*!< 0x00100000 */
2464 #define COMP3_CSR_COMP3OUT_Pos           (30U)
2465 #define COMP3_CSR_COMP3OUT_Msk           (0x1UL << COMP3_CSR_COMP3OUT_Pos)      /*!< 0x40000000 */
2466 #define COMP3_CSR_COMP3OUT               COMP3_CSR_COMP3OUT_Msk                /*!< COMP3 output level */
2467 #define COMP3_CSR_COMP3LOCK_Pos          (31U)
2468 #define COMP3_CSR_COMP3LOCK_Msk          (0x1UL << COMP3_CSR_COMP3LOCK_Pos)     /*!< 0x80000000 */
2469 #define COMP3_CSR_COMP3LOCK              COMP3_CSR_COMP3LOCK_Msk               /*!< COMP3 lock */
2470 
2471 /**********************  Bit definition for COMP4_CSR register  ***************/
2472 #define COMP4_CSR_COMP4EN_Pos            (0U)
2473 #define COMP4_CSR_COMP4EN_Msk            (0x1UL << COMP4_CSR_COMP4EN_Pos)       /*!< 0x00000001 */
2474 #define COMP4_CSR_COMP4EN                COMP4_CSR_COMP4EN_Msk                 /*!< COMP4 enable */
2475 #define COMP4_CSR_COMP4MODE_Pos          (2U)
2476 #define COMP4_CSR_COMP4MODE_Msk          (0x3UL << COMP4_CSR_COMP4MODE_Pos)     /*!< 0x0000000C */
2477 #define COMP4_CSR_COMP4MODE              COMP4_CSR_COMP4MODE_Msk               /*!< COMP4 power mode */
2478 #define COMP4_CSR_COMP4MODE_0            (0x1UL << COMP4_CSR_COMP4MODE_Pos)     /*!< 0x00000004 */
2479 #define COMP4_CSR_COMP4MODE_1            (0x2UL << COMP4_CSR_COMP4MODE_Pos)     /*!< 0x00000008 */
2480 #define COMP4_CSR_COMP4INSEL_Pos         (4U)
2481 #define COMP4_CSR_COMP4INSEL_Msk         (0x7UL << COMP4_CSR_COMP4INSEL_Pos)    /*!< 0x00000070 */
2482 #define COMP4_CSR_COMP4INSEL             COMP4_CSR_COMP4INSEL_Msk              /*!< COMP4 inverting input select */
2483 #define COMP4_CSR_COMP4INSEL_0           (0x00000010U)                         /*!< COMP4 inverting input select bit 0 */
2484 #define COMP4_CSR_COMP4INSEL_1           (0x00000020U)                         /*!< COMP4 inverting input select bit 1 */
2485 #define COMP4_CSR_COMP4INSEL_2           (0x00000040U)                         /*!< COMP4 inverting input select bit 2 */
2486 #define COMP4_CSR_COMP4NONINSEL_Pos      (7U)
2487 #define COMP4_CSR_COMP4NONINSEL_Msk      (0x1UL << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
2488 #define COMP4_CSR_COMP4NONINSEL          COMP4_CSR_COMP4NONINSEL_Msk           /*!< COMP4 non inverting input select */
2489 #define COMP4_CSR_COMP4WNDWEN_Pos        (9U)
2490 #define COMP4_CSR_COMP4WNDWEN_Msk        (0x1UL << COMP4_CSR_COMP4WNDWEN_Pos)   /*!< 0x00000200 */
2491 #define COMP4_CSR_COMP4WNDWEN            COMP4_CSR_COMP4WNDWEN_Msk             /*!< COMP4 window mode enable */
2492 #define COMP4_CSR_COMP4OUTSEL_Pos        (10U)
2493 #define COMP4_CSR_COMP4OUTSEL_Msk        (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00003C00 */
2494 #define COMP4_CSR_COMP4OUTSEL            COMP4_CSR_COMP4OUTSEL_Msk             /*!< COMP4 output select */
2495 #define COMP4_CSR_COMP4OUTSEL_0          (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000400 */
2496 #define COMP4_CSR_COMP4OUTSEL_1          (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00000800 */
2497 #define COMP4_CSR_COMP4OUTSEL_2          (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00001000 */
2498 #define COMP4_CSR_COMP4OUTSEL_3          (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)   /*!< 0x00002000 */
2499 #define COMP4_CSR_COMP4POL_Pos           (15U)
2500 #define COMP4_CSR_COMP4POL_Msk           (0x1UL << COMP4_CSR_COMP4POL_Pos)      /*!< 0x00008000 */
2501 #define COMP4_CSR_COMP4POL               COMP4_CSR_COMP4POL_Msk                /*!< COMP4 output polarity */
2502 #define COMP4_CSR_COMP4HYST_Pos          (16U)
2503 #define COMP4_CSR_COMP4HYST_Msk          (0x3UL << COMP4_CSR_COMP4HYST_Pos)     /*!< 0x00030000 */
2504 #define COMP4_CSR_COMP4HYST              COMP4_CSR_COMP4HYST_Msk               /*!< COMP4 hysteresis */
2505 #define COMP4_CSR_COMP4HYST_0            (0x1UL << COMP4_CSR_COMP4HYST_Pos)     /*!< 0x00010000 */
2506 #define COMP4_CSR_COMP4HYST_1            (0x2UL << COMP4_CSR_COMP4HYST_Pos)     /*!< 0x00020000 */
2507 #define COMP4_CSR_COMP4BLANKING_Pos      (18U)
2508 #define COMP4_CSR_COMP4BLANKING_Msk      (0x3UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x000C0000 */
2509 #define COMP4_CSR_COMP4BLANKING          COMP4_CSR_COMP4BLANKING_Msk           /*!< COMP4 blanking */
2510 #define COMP4_CSR_COMP4BLANKING_0        (0x1UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00040000 */
2511 #define COMP4_CSR_COMP4BLANKING_1        (0x2UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00080000 */
2512 #define COMP4_CSR_COMP4BLANKING_2        (0x4UL << COMP4_CSR_COMP4BLANKING_Pos) /*!< 0x00100000 */
2513 #define COMP4_CSR_COMP4OUT_Pos           (30U)
2514 #define COMP4_CSR_COMP4OUT_Msk           (0x1UL << COMP4_CSR_COMP4OUT_Pos)      /*!< 0x40000000 */
2515 #define COMP4_CSR_COMP4OUT               COMP4_CSR_COMP4OUT_Msk                /*!< COMP4 output level */
2516 #define COMP4_CSR_COMP4LOCK_Pos          (31U)
2517 #define COMP4_CSR_COMP4LOCK_Msk          (0x1UL << COMP4_CSR_COMP4LOCK_Pos)     /*!< 0x80000000 */
2518 #define COMP4_CSR_COMP4LOCK              COMP4_CSR_COMP4LOCK_Msk               /*!< COMP4 lock */
2519 
2520 /**********************  Bit definition for COMP5_CSR register  ***************/
2521 #define COMP5_CSR_COMP5EN_Pos            (0U)
2522 #define COMP5_CSR_COMP5EN_Msk            (0x1UL << COMP5_CSR_COMP5EN_Pos)       /*!< 0x00000001 */
2523 #define COMP5_CSR_COMP5EN                COMP5_CSR_COMP5EN_Msk                 /*!< COMP5 enable */
2524 #define COMP5_CSR_COMP5MODE_Pos          (2U)
2525 #define COMP5_CSR_COMP5MODE_Msk          (0x3UL << COMP5_CSR_COMP5MODE_Pos)     /*!< 0x0000000C */
2526 #define COMP5_CSR_COMP5MODE              COMP5_CSR_COMP5MODE_Msk               /*!< COMP5 power mode */
2527 #define COMP5_CSR_COMP5MODE_0            (0x1UL << COMP5_CSR_COMP5MODE_Pos)     /*!< 0x00000004 */
2528 #define COMP5_CSR_COMP5MODE_1            (0x2UL << COMP5_CSR_COMP5MODE_Pos)     /*!< 0x00000008 */
2529 #define COMP5_CSR_COMP5INSEL_Pos         (4U)
2530 #define COMP5_CSR_COMP5INSEL_Msk         (0x7UL << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000070 */
2531 #define COMP5_CSR_COMP5INSEL             COMP5_CSR_COMP5INSEL_Msk              /*!< COMP5 inverting input select */
2532 #define COMP5_CSR_COMP5INSEL_0           (0x1UL << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000010 */
2533 #define COMP5_CSR_COMP5INSEL_1           (0x2UL << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000020 */
2534 #define COMP5_CSR_COMP5INSEL_2           (0x4UL << COMP5_CSR_COMP5INSEL_Pos)    /*!< 0x00000040 */
2535 #define COMP5_CSR_COMP5NONINSEL_Pos      (7U)
2536 #define COMP5_CSR_COMP5NONINSEL_Msk      (0x1UL << COMP5_CSR_COMP5NONINSEL_Pos) /*!< 0x00000080 */
2537 #define COMP5_CSR_COMP5NONINSEL          COMP5_CSR_COMP5NONINSEL_Msk           /*!< COMP5 non inverting input select */
2538 #define COMP5_CSR_COMP5OUTSEL_Pos        (10U)
2539 #define COMP5_CSR_COMP5OUTSEL_Msk        (0xFUL << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00003C00 */
2540 #define COMP5_CSR_COMP5OUTSEL            COMP5_CSR_COMP5OUTSEL_Msk             /*!< COMP5 output select */
2541 #define COMP5_CSR_COMP5OUTSEL_0          (0x1UL << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00000400 */
2542 #define COMP5_CSR_COMP5OUTSEL_1          (0x2UL << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00000800 */
2543 #define COMP5_CSR_COMP5OUTSEL_2          (0x4UL << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00001000 */
2544 #define COMP5_CSR_COMP5OUTSEL_3          (0x8UL << COMP5_CSR_COMP5OUTSEL_Pos)   /*!< 0x00002000 */
2545 #define COMP5_CSR_COMP5POL_Pos           (15U)
2546 #define COMP5_CSR_COMP5POL_Msk           (0x1UL << COMP5_CSR_COMP5POL_Pos)      /*!< 0x00008000 */
2547 #define COMP5_CSR_COMP5POL               COMP5_CSR_COMP5POL_Msk                /*!< COMP5 output polarity */
2548 #define COMP5_CSR_COMP5HYST_Pos          (16U)
2549 #define COMP5_CSR_COMP5HYST_Msk          (0x3UL << COMP5_CSR_COMP5HYST_Pos)     /*!< 0x00030000 */
2550 #define COMP5_CSR_COMP5HYST              COMP5_CSR_COMP5HYST_Msk               /*!< COMP5 hysteresis */
2551 #define COMP5_CSR_COMP5HYST_0            (0x1UL << COMP5_CSR_COMP5HYST_Pos)     /*!< 0x00010000 */
2552 #define COMP5_CSR_COMP5HYST_1            (0x2UL << COMP5_CSR_COMP5HYST_Pos)     /*!< 0x00020000 */
2553 #define COMP5_CSR_COMP5BLANKING_Pos      (18U)
2554 #define COMP5_CSR_COMP5BLANKING_Msk      (0x3UL << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x000C0000 */
2555 #define COMP5_CSR_COMP5BLANKING          COMP5_CSR_COMP5BLANKING_Msk           /*!< COMP5 blanking */
2556 #define COMP5_CSR_COMP5BLANKING_0        (0x1UL << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00040000 */
2557 #define COMP5_CSR_COMP5BLANKING_1        (0x2UL << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00080000 */
2558 #define COMP5_CSR_COMP5BLANKING_2        (0x4UL << COMP5_CSR_COMP5BLANKING_Pos) /*!< 0x00100000 */
2559 #define COMP5_CSR_COMP5OUT_Pos           (30U)
2560 #define COMP5_CSR_COMP5OUT_Msk           (0x1UL << COMP5_CSR_COMP5OUT_Pos)      /*!< 0x40000000 */
2561 #define COMP5_CSR_COMP5OUT               COMP5_CSR_COMP5OUT_Msk                /*!< COMP5 output level */
2562 #define COMP5_CSR_COMP5LOCK_Pos          (31U)
2563 #define COMP5_CSR_COMP5LOCK_Msk          (0x1UL << COMP5_CSR_COMP5LOCK_Pos)     /*!< 0x80000000 */
2564 #define COMP5_CSR_COMP5LOCK              COMP5_CSR_COMP5LOCK_Msk               /*!< COMP5 lock */
2565 
2566 /**********************  Bit definition for COMP6_CSR register  ***************/
2567 #define COMP6_CSR_COMP6EN_Pos            (0U)
2568 #define COMP6_CSR_COMP6EN_Msk            (0x1UL << COMP6_CSR_COMP6EN_Pos)       /*!< 0x00000001 */
2569 #define COMP6_CSR_COMP6EN                COMP6_CSR_COMP6EN_Msk                 /*!< COMP6 enable */
2570 #define COMP6_CSR_COMP6MODE_Pos          (2U)
2571 #define COMP6_CSR_COMP6MODE_Msk          (0x3UL << COMP6_CSR_COMP6MODE_Pos)     /*!< 0x0000000C */
2572 #define COMP6_CSR_COMP6MODE              COMP6_CSR_COMP6MODE_Msk               /*!< COMP6 power mode */
2573 #define COMP6_CSR_COMP6MODE_0            (0x1UL << COMP6_CSR_COMP6MODE_Pos)     /*!< 0x00000004 */
2574 #define COMP6_CSR_COMP6MODE_1            (0x2UL << COMP6_CSR_COMP6MODE_Pos)     /*!< 0x00000008 */
2575 #define COMP6_CSR_COMP6INSEL_Pos         (4U)
2576 #define COMP6_CSR_COMP6INSEL_Msk         (0x7UL << COMP6_CSR_COMP6INSEL_Pos)    /*!< 0x00000070 */
2577 #define COMP6_CSR_COMP6INSEL             COMP6_CSR_COMP6INSEL_Msk              /*!< COMP6 inverting input select */
2578 #define COMP6_CSR_COMP6INSEL_0           (0x00000010U)                         /*!< COMP6 inverting input select bit 0 */
2579 #define COMP6_CSR_COMP6INSEL_1           (0x00000020U)                         /*!< COMP6 inverting input select bit 1 */
2580 #define COMP6_CSR_COMP6INSEL_2           (0x00000040U)                         /*!< COMP6 inverting input select bit 2 */
2581 #define COMP6_CSR_COMP6NONINSEL_Pos      (7U)
2582 #define COMP6_CSR_COMP6NONINSEL_Msk      (0x1UL << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
2583 #define COMP6_CSR_COMP6NONINSEL          COMP6_CSR_COMP6NONINSEL_Msk           /*!< COMP6 non inverting input select */
2584 #define COMP6_CSR_COMP6WNDWEN_Pos        (9U)
2585 #define COMP6_CSR_COMP6WNDWEN_Msk        (0x1UL << COMP6_CSR_COMP6WNDWEN_Pos)   /*!< 0x00000200 */
2586 #define COMP6_CSR_COMP6WNDWEN            COMP6_CSR_COMP6WNDWEN_Msk             /*!< COMP6 window mode enable */
2587 #define COMP6_CSR_COMP6OUTSEL_Pos        (10U)
2588 #define COMP6_CSR_COMP6OUTSEL_Msk        (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00003C00 */
2589 #define COMP6_CSR_COMP6OUTSEL            COMP6_CSR_COMP6OUTSEL_Msk             /*!< COMP6 output select */
2590 #define COMP6_CSR_COMP6OUTSEL_0          (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000400 */
2591 #define COMP6_CSR_COMP6OUTSEL_1          (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00000800 */
2592 #define COMP6_CSR_COMP6OUTSEL_2          (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00001000 */
2593 #define COMP6_CSR_COMP6OUTSEL_3          (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)   /*!< 0x00002000 */
2594 #define COMP6_CSR_COMP6POL_Pos           (15U)
2595 #define COMP6_CSR_COMP6POL_Msk           (0x1UL << COMP6_CSR_COMP6POL_Pos)      /*!< 0x00008000 */
2596 #define COMP6_CSR_COMP6POL               COMP6_CSR_COMP6POL_Msk                /*!< COMP6 output polarity */
2597 #define COMP6_CSR_COMP6HYST_Pos          (16U)
2598 #define COMP6_CSR_COMP6HYST_Msk          (0x3UL << COMP6_CSR_COMP6HYST_Pos)     /*!< 0x00030000 */
2599 #define COMP6_CSR_COMP6HYST              COMP6_CSR_COMP6HYST_Msk               /*!< COMP6 hysteresis */
2600 #define COMP6_CSR_COMP6HYST_0            (0x1UL << COMP6_CSR_COMP6HYST_Pos)     /*!< 0x00010000 */
2601 #define COMP6_CSR_COMP6HYST_1            (0x2UL << COMP6_CSR_COMP6HYST_Pos)     /*!< 0x00020000 */
2602 #define COMP6_CSR_COMP6BLANKING_Pos      (18U)
2603 #define COMP6_CSR_COMP6BLANKING_Msk      (0x3UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x000C0000 */
2604 #define COMP6_CSR_COMP6BLANKING          COMP6_CSR_COMP6BLANKING_Msk           /*!< COMP6 blanking */
2605 #define COMP6_CSR_COMP6BLANKING_0        (0x1UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00040000 */
2606 #define COMP6_CSR_COMP6BLANKING_1        (0x2UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00080000 */
2607 #define COMP6_CSR_COMP6BLANKING_2        (0x4UL << COMP6_CSR_COMP6BLANKING_Pos) /*!< 0x00100000 */
2608 #define COMP6_CSR_COMP6OUT_Pos           (30U)
2609 #define COMP6_CSR_COMP6OUT_Msk           (0x1UL << COMP6_CSR_COMP6OUT_Pos)      /*!< 0x40000000 */
2610 #define COMP6_CSR_COMP6OUT               COMP6_CSR_COMP6OUT_Msk                /*!< COMP6 output level */
2611 #define COMP6_CSR_COMP6LOCK_Pos          (31U)
2612 #define COMP6_CSR_COMP6LOCK_Msk          (0x1UL << COMP6_CSR_COMP6LOCK_Pos)     /*!< 0x80000000 */
2613 #define COMP6_CSR_COMP6LOCK              COMP6_CSR_COMP6LOCK_Msk               /*!< COMP6 lock */
2614 
2615 /**********************  Bit definition for COMP7_CSR register  ***************/
2616 #define COMP7_CSR_COMP7EN_Pos            (0U)
2617 #define COMP7_CSR_COMP7EN_Msk            (0x1UL << COMP7_CSR_COMP7EN_Pos)       /*!< 0x00000001 */
2618 #define COMP7_CSR_COMP7EN                COMP7_CSR_COMP7EN_Msk                 /*!< COMP7 enable */
2619 #define COMP7_CSR_COMP7MODE_Pos          (2U)
2620 #define COMP7_CSR_COMP7MODE_Msk          (0x3UL << COMP7_CSR_COMP7MODE_Pos)     /*!< 0x0000000C */
2621 #define COMP7_CSR_COMP7MODE              COMP7_CSR_COMP7MODE_Msk               /*!< COMP7 power mode */
2622 #define COMP7_CSR_COMP7MODE_0            (0x1UL << COMP7_CSR_COMP7MODE_Pos)     /*!< 0x00000004 */
2623 #define COMP7_CSR_COMP7MODE_1            (0x2UL << COMP7_CSR_COMP7MODE_Pos)     /*!< 0x00000008 */
2624 #define COMP7_CSR_COMP7INSEL_Pos         (4U)
2625 #define COMP7_CSR_COMP7INSEL_Msk         (0x7UL << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000070 */
2626 #define COMP7_CSR_COMP7INSEL             COMP7_CSR_COMP7INSEL_Msk              /*!< COMP7 inverting input select */
2627 #define COMP7_CSR_COMP7INSEL_0           (0x1UL << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000010 */
2628 #define COMP7_CSR_COMP7INSEL_1           (0x2UL << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000020 */
2629 #define COMP7_CSR_COMP7INSEL_2           (0x4UL << COMP7_CSR_COMP7INSEL_Pos)    /*!< 0x00000040 */
2630 #define COMP7_CSR_COMP7NONINSEL_Pos      (7U)
2631 #define COMP7_CSR_COMP7NONINSEL_Msk      (0x1UL << COMP7_CSR_COMP7NONINSEL_Pos) /*!< 0x00000080 */
2632 #define COMP7_CSR_COMP7NONINSEL          COMP7_CSR_COMP7NONINSEL_Msk           /*!< COMP7 non inverting input select */
2633 #define COMP7_CSR_COMP7OUTSEL_Pos        (10U)
2634 #define COMP7_CSR_COMP7OUTSEL_Msk        (0xFUL << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00003C00 */
2635 #define COMP7_CSR_COMP7OUTSEL            COMP7_CSR_COMP7OUTSEL_Msk             /*!< COMP7 output select */
2636 #define COMP7_CSR_COMP7OUTSEL_0          (0x1UL << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00000400 */
2637 #define COMP7_CSR_COMP7OUTSEL_1          (0x2UL << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00000800 */
2638 #define COMP7_CSR_COMP7OUTSEL_2          (0x4UL << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00001000 */
2639 #define COMP7_CSR_COMP7OUTSEL_3          (0x8UL << COMP7_CSR_COMP7OUTSEL_Pos)   /*!< 0x00002000 */
2640 #define COMP7_CSR_COMP7POL_Pos           (15U)
2641 #define COMP7_CSR_COMP7POL_Msk           (0x1UL << COMP7_CSR_COMP7POL_Pos)      /*!< 0x00008000 */
2642 #define COMP7_CSR_COMP7POL               COMP7_CSR_COMP7POL_Msk                /*!< COMP7 output polarity */
2643 #define COMP7_CSR_COMP7HYST_Pos          (16U)
2644 #define COMP7_CSR_COMP7HYST_Msk          (0x3UL << COMP7_CSR_COMP7HYST_Pos)     /*!< 0x00030000 */
2645 #define COMP7_CSR_COMP7HYST              COMP7_CSR_COMP7HYST_Msk               /*!< COMP7 hysteresis */
2646 #define COMP7_CSR_COMP7HYST_0            (0x1UL << COMP7_CSR_COMP7HYST_Pos)     /*!< 0x00010000 */
2647 #define COMP7_CSR_COMP7HYST_1            (0x2UL << COMP7_CSR_COMP7HYST_Pos)     /*!< 0x00020000 */
2648 #define COMP7_CSR_COMP7BLANKING_Pos      (18U)
2649 #define COMP7_CSR_COMP7BLANKING_Msk      (0x3UL << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x000C0000 */
2650 #define COMP7_CSR_COMP7BLANKING          COMP7_CSR_COMP7BLANKING_Msk           /*!< COMP7 blanking */
2651 #define COMP7_CSR_COMP7BLANKING_0        (0x1UL << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00040000 */
2652 #define COMP7_CSR_COMP7BLANKING_1        (0x2UL << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00080000 */
2653 #define COMP7_CSR_COMP7BLANKING_2        (0x4UL << COMP7_CSR_COMP7BLANKING_Pos) /*!< 0x00100000 */
2654 #define COMP7_CSR_COMP7OUT_Pos           (30U)
2655 #define COMP7_CSR_COMP7OUT_Msk           (0x1UL << COMP7_CSR_COMP7OUT_Pos)      /*!< 0x40000000 */
2656 #define COMP7_CSR_COMP7OUT               COMP7_CSR_COMP7OUT_Msk                /*!< COMP7 output level */
2657 #define COMP7_CSR_COMP7LOCK_Pos          (31U)
2658 #define COMP7_CSR_COMP7LOCK_Msk          (0x1UL << COMP7_CSR_COMP7LOCK_Pos)     /*!< 0x80000000 */
2659 #define COMP7_CSR_COMP7LOCK              COMP7_CSR_COMP7LOCK_Msk               /*!< COMP7 lock */
2660 
2661 /**********************  Bit definition for COMP_CSR register  ****************/
2662 #define COMP_CSR_COMPxEN_Pos            (0U)
2663 #define COMP_CSR_COMPxEN_Msk            (0x1UL << COMP_CSR_COMPxEN_Pos)         /*!< 0x00000001 */
2664 #define COMP_CSR_COMPxEN                COMP_CSR_COMPxEN_Msk                   /*!< COMPx enable */
2665 #define COMP_CSR_COMPxSW1_Pos           (1U)
2666 #define COMP_CSR_COMPxSW1_Msk           (0x1UL << COMP_CSR_COMPxSW1_Pos)        /*!< 0x00000002 */
2667 #define COMP_CSR_COMPxSW1               COMP_CSR_COMPxSW1_Msk                  /*!< COMPx SW1 switch control */
2668 #define COMP_CSR_COMPxMODE_Pos          (2U)
2669 #define COMP_CSR_COMPxMODE_Msk          (0x3UL << COMP_CSR_COMPxMODE_Pos)       /*!< 0x0000000C */
2670 #define COMP_CSR_COMPxMODE              COMP_CSR_COMPxMODE_Msk                 /*!< COMPx power mode */
2671 #define COMP_CSR_COMPxMODE_0            (0x1UL << COMP_CSR_COMPxMODE_Pos)       /*!< 0x00000004 */
2672 #define COMP_CSR_COMPxMODE_1            (0x2UL << COMP_CSR_COMPxMODE_Pos)       /*!< 0x00000008 */
2673 #define COMP_CSR_COMPxINSEL_Pos         (4U)
2674 #define COMP_CSR_COMPxINSEL_Msk         (0x7UL << COMP_CSR_COMPxINSEL_Pos)      /*!< 0x00000070 */
2675 #define COMP_CSR_COMPxINSEL             COMP_CSR_COMPxINSEL_Msk                /*!< COMPx inverting input select */
2676 #define COMP_CSR_COMPxINSEL_0           (0x00000010U)                          /*!< COMPx inverting input select bit 0 */
2677 #define COMP_CSR_COMPxINSEL_1           (0x00000020U)                          /*!< COMPx inverting input select bit 1 */
2678 #define COMP_CSR_COMPxINSEL_2           (0x00000040U)                          /*!< COMPx inverting input select bit 2 */
2679 #define COMP_CSR_COMPxNONINSEL_Pos      (7U)
2680 #define COMP_CSR_COMPxNONINSEL_Msk      (0x1UL << COMP_CSR_COMPxNONINSEL_Pos)   /*!< 0x00000080 */
2681 #define COMP_CSR_COMPxNONINSEL          COMP_CSR_COMPxNONINSEL_Msk             /*!< COMPx non inverting input select */
2682 #define COMP_CSR_COMPxWNDWEN_Pos        (9U)
2683 #define COMP_CSR_COMPxWNDWEN_Msk        (0x1UL << COMP_CSR_COMPxWNDWEN_Pos)     /*!< 0x00000200 */
2684 #define COMP_CSR_COMPxWNDWEN            COMP_CSR_COMPxWNDWEN_Msk               /*!< COMPx window mode enable */
2685 #define COMP_CSR_COMPxOUTSEL_Pos        (10U)
2686 #define COMP_CSR_COMPxOUTSEL_Msk        (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00003C00 */
2687 #define COMP_CSR_COMPxOUTSEL            COMP_CSR_COMPxOUTSEL_Msk               /*!< COMPx output select */
2688 #define COMP_CSR_COMPxOUTSEL_0          (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000400 */
2689 #define COMP_CSR_COMPxOUTSEL_1          (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00000800 */
2690 #define COMP_CSR_COMPxOUTSEL_2          (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00001000 */
2691 #define COMP_CSR_COMPxOUTSEL_3          (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)     /*!< 0x00002000 */
2692 #define COMP_CSR_COMPxPOL_Pos           (15U)
2693 #define COMP_CSR_COMPxPOL_Msk           (0x1UL << COMP_CSR_COMPxPOL_Pos)        /*!< 0x00008000 */
2694 #define COMP_CSR_COMPxPOL               COMP_CSR_COMPxPOL_Msk                  /*!< COMPx output polarity */
2695 #define COMP_CSR_COMPxHYST_Pos          (16U)
2696 #define COMP_CSR_COMPxHYST_Msk          (0x3UL << COMP_CSR_COMPxHYST_Pos)       /*!< 0x00030000 */
2697 #define COMP_CSR_COMPxHYST              COMP_CSR_COMPxHYST_Msk                 /*!< COMPx hysteresis */
2698 #define COMP_CSR_COMPxHYST_0            (0x1UL << COMP_CSR_COMPxHYST_Pos)       /*!< 0x00010000 */
2699 #define COMP_CSR_COMPxHYST_1            (0x2UL << COMP_CSR_COMPxHYST_Pos)       /*!< 0x00020000 */
2700 #define COMP_CSR_COMPxBLANKING_Pos      (18U)
2701 #define COMP_CSR_COMPxBLANKING_Msk      (0x3UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x000C0000 */
2702 #define COMP_CSR_COMPxBLANKING          COMP_CSR_COMPxBLANKING_Msk             /*!< COMPx blanking */
2703 #define COMP_CSR_COMPxBLANKING_0        (0x1UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00040000 */
2704 #define COMP_CSR_COMPxBLANKING_1        (0x2UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00080000 */
2705 #define COMP_CSR_COMPxBLANKING_2        (0x4UL << COMP_CSR_COMPxBLANKING_Pos)   /*!< 0x00100000 */
2706 #define COMP_CSR_COMPxOUT_Pos           (30U)
2707 #define COMP_CSR_COMPxOUT_Msk           (0x1UL << COMP_CSR_COMPxOUT_Pos)        /*!< 0x40000000 */
2708 #define COMP_CSR_COMPxOUT               COMP_CSR_COMPxOUT_Msk                  /*!< COMPx output level */
2709 #define COMP_CSR_COMPxLOCK_Pos          (31U)
2710 #define COMP_CSR_COMPxLOCK_Msk          (0x1UL << COMP_CSR_COMPxLOCK_Pos)       /*!< 0x80000000 */
2711 #define COMP_CSR_COMPxLOCK              COMP_CSR_COMPxLOCK_Msk                 /*!< COMPx lock */
2712 
2713 /******************************************************************************/
2714 /*                                                                            */
2715 /*                     Operational Amplifier (OPAMP)                          */
2716 /*                                                                            */
2717 /******************************************************************************/
2718 /*********************  Bit definition for OPAMP1_CSR register  ***************/
2719 #define OPAMP1_CSR_OPAMP1EN_Pos       (0U)
2720 #define OPAMP1_CSR_OPAMP1EN_Msk       (0x1UL << OPAMP1_CSR_OPAMP1EN_Pos)        /*!< 0x00000001 */
2721 #define OPAMP1_CSR_OPAMP1EN           OPAMP1_CSR_OPAMP1EN_Msk                  /*!< OPAMP1 enable */
2722 #define OPAMP1_CSR_FORCEVP_Pos        (1U)
2723 #define OPAMP1_CSR_FORCEVP_Msk        (0x1UL << OPAMP1_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
2724 #define OPAMP1_CSR_FORCEVP            OPAMP1_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
2725 #define OPAMP1_CSR_VPSEL_Pos          (2U)
2726 #define OPAMP1_CSR_VPSEL_Msk          (0x3UL << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x0000000C */
2727 #define OPAMP1_CSR_VPSEL              OPAMP1_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
2728 #define OPAMP1_CSR_VPSEL_0            (0x1UL << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x00000004 */
2729 #define OPAMP1_CSR_VPSEL_1            (0x2UL << OPAMP1_CSR_VPSEL_Pos)           /*!< 0x00000008 */
2730 #define OPAMP1_CSR_VMSEL_Pos          (5U)
2731 #define OPAMP1_CSR_VMSEL_Msk          (0x3UL << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000060 */
2732 #define OPAMP1_CSR_VMSEL              OPAMP1_CSR_VMSEL_Msk                     /*!< Inverting input selection */
2733 #define OPAMP1_CSR_VMSEL_0            (0x1UL << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000020 */
2734 #define OPAMP1_CSR_VMSEL_1            (0x2UL << OPAMP1_CSR_VMSEL_Pos)           /*!< 0x00000040 */
2735 #define OPAMP1_CSR_TCMEN_Pos          (7U)
2736 #define OPAMP1_CSR_TCMEN_Msk          (0x1UL << OPAMP1_CSR_TCMEN_Pos)           /*!< 0x00000080 */
2737 #define OPAMP1_CSR_TCMEN              OPAMP1_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
2738 #define OPAMP1_CSR_VMSSEL_Pos         (8U)
2739 #define OPAMP1_CSR_VMSSEL_Msk         (0x1UL << OPAMP1_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
2740 #define OPAMP1_CSR_VMSSEL             OPAMP1_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
2741 #define OPAMP1_CSR_VPSSEL_Pos         (9U)
2742 #define OPAMP1_CSR_VPSSEL_Msk         (0x3UL << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
2743 #define OPAMP1_CSR_VPSSEL             OPAMP1_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
2744 #define OPAMP1_CSR_VPSSEL_0           (0x1UL << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
2745 #define OPAMP1_CSR_VPSSEL_1           (0x2UL << OPAMP1_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
2746 #define OPAMP1_CSR_CALON_Pos          (11U)
2747 #define OPAMP1_CSR_CALON_Msk          (0x1UL << OPAMP1_CSR_CALON_Pos)           /*!< 0x00000800 */
2748 #define OPAMP1_CSR_CALON              OPAMP1_CSR_CALON_Msk                     /*!< Calibration mode enable */
2749 #define OPAMP1_CSR_CALSEL_Pos         (12U)
2750 #define OPAMP1_CSR_CALSEL_Msk         (0x3UL << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00003000 */
2751 #define OPAMP1_CSR_CALSEL             OPAMP1_CSR_CALSEL_Msk                    /*!< Calibration selection */
2752 #define OPAMP1_CSR_CALSEL_0           (0x1UL << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00001000 */
2753 #define OPAMP1_CSR_CALSEL_1           (0x2UL << OPAMP1_CSR_CALSEL_Pos)          /*!< 0x00002000 */
2754 #define OPAMP1_CSR_PGGAIN_Pos         (14U)
2755 #define OPAMP1_CSR_PGGAIN_Msk         (0xFUL << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
2756 #define OPAMP1_CSR_PGGAIN             OPAMP1_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
2757 #define OPAMP1_CSR_PGGAIN_0           (0x1UL << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
2758 #define OPAMP1_CSR_PGGAIN_1           (0x2UL << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
2759 #define OPAMP1_CSR_PGGAIN_2           (0x4UL << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
2760 #define OPAMP1_CSR_PGGAIN_3           (0x8UL << OPAMP1_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
2761 #define OPAMP1_CSR_USERTRIM_Pos       (18U)
2762 #define OPAMP1_CSR_USERTRIM_Msk       (0x1UL << OPAMP1_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
2763 #define OPAMP1_CSR_USERTRIM           OPAMP1_CSR_USERTRIM_Msk                  /*!< User trimming enable */
2764 #define OPAMP1_CSR_TRIMOFFSETP_Pos    (19U)
2765 #define OPAMP1_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP1_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
2766 #define OPAMP1_CSR_TRIMOFFSETP        OPAMP1_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
2767 #define OPAMP1_CSR_TRIMOFFSETN_Pos    (24U)
2768 #define OPAMP1_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP1_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
2769 #define OPAMP1_CSR_TRIMOFFSETN        OPAMP1_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
2770 #define OPAMP1_CSR_TSTREF_Pos         (29U)
2771 #define OPAMP1_CSR_TSTREF_Msk         (0x1UL << OPAMP1_CSR_TSTREF_Pos)          /*!< 0x20000000 */
2772 #define OPAMP1_CSR_TSTREF             OPAMP1_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
2773 #define OPAMP1_CSR_OUTCAL_Pos         (30U)
2774 #define OPAMP1_CSR_OUTCAL_Msk         (0x1UL << OPAMP1_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
2775 #define OPAMP1_CSR_OUTCAL             OPAMP1_CSR_OUTCAL_Msk                    /*!< OPAMP output status flag */
2776 #define OPAMP1_CSR_LOCK_Pos           (31U)
2777 #define OPAMP1_CSR_LOCK_Msk           (0x1UL << OPAMP1_CSR_LOCK_Pos)            /*!< 0x80000000 */
2778 #define OPAMP1_CSR_LOCK               OPAMP1_CSR_LOCK_Msk                      /*!< OPAMP lock */
2779 
2780 /*********************  Bit definition for OPAMP2_CSR register  ***************/
2781 #define OPAMP2_CSR_OPAMP2EN_Pos       (0U)
2782 #define OPAMP2_CSR_OPAMP2EN_Msk       (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)        /*!< 0x00000001 */
2783 #define OPAMP2_CSR_OPAMP2EN           OPAMP2_CSR_OPAMP2EN_Msk                  /*!< OPAMP2 enable */
2784 #define OPAMP2_CSR_FORCEVP_Pos        (1U)
2785 #define OPAMP2_CSR_FORCEVP_Msk        (0x1UL << OPAMP2_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
2786 #define OPAMP2_CSR_FORCEVP            OPAMP2_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
2787 #define OPAMP2_CSR_VPSEL_Pos          (2U)
2788 #define OPAMP2_CSR_VPSEL_Msk          (0x3UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x0000000C */
2789 #define OPAMP2_CSR_VPSEL              OPAMP2_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
2790 #define OPAMP2_CSR_VPSEL_0            (0x1UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000004 */
2791 #define OPAMP2_CSR_VPSEL_1            (0x2UL << OPAMP2_CSR_VPSEL_Pos)           /*!< 0x00000008 */
2792 #define OPAMP2_CSR_VMSEL_Pos          (5U)
2793 #define OPAMP2_CSR_VMSEL_Msk          (0x3UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000060 */
2794 #define OPAMP2_CSR_VMSEL              OPAMP2_CSR_VMSEL_Msk                     /*!< Inverting input selection */
2795 #define OPAMP2_CSR_VMSEL_0            (0x1UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000020 */
2796 #define OPAMP2_CSR_VMSEL_1            (0x2UL << OPAMP2_CSR_VMSEL_Pos)           /*!< 0x00000040 */
2797 #define OPAMP2_CSR_TCMEN_Pos          (7U)
2798 #define OPAMP2_CSR_TCMEN_Msk          (0x1UL << OPAMP2_CSR_TCMEN_Pos)           /*!< 0x00000080 */
2799 #define OPAMP2_CSR_TCMEN              OPAMP2_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
2800 #define OPAMP2_CSR_VMSSEL_Pos         (8U)
2801 #define OPAMP2_CSR_VMSSEL_Msk         (0x1UL << OPAMP2_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
2802 #define OPAMP2_CSR_VMSSEL             OPAMP2_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
2803 #define OPAMP2_CSR_VPSSEL_Pos         (9U)
2804 #define OPAMP2_CSR_VPSSEL_Msk         (0x3UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
2805 #define OPAMP2_CSR_VPSSEL             OPAMP2_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
2806 #define OPAMP2_CSR_VPSSEL_0           (0x1UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
2807 #define OPAMP2_CSR_VPSSEL_1           (0x2UL << OPAMP2_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
2808 #define OPAMP2_CSR_CALON_Pos          (11U)
2809 #define OPAMP2_CSR_CALON_Msk          (0x1UL << OPAMP2_CSR_CALON_Pos)           /*!< 0x00000800 */
2810 #define OPAMP2_CSR_CALON              OPAMP2_CSR_CALON_Msk                     /*!< Calibration mode enable */
2811 #define OPAMP2_CSR_CALSEL_Pos         (12U)
2812 #define OPAMP2_CSR_CALSEL_Msk         (0x3UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00003000 */
2813 #define OPAMP2_CSR_CALSEL             OPAMP2_CSR_CALSEL_Msk                    /*!< Calibration selection */
2814 #define OPAMP2_CSR_CALSEL_0           (0x1UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00001000 */
2815 #define OPAMP2_CSR_CALSEL_1           (0x2UL << OPAMP2_CSR_CALSEL_Pos)          /*!< 0x00002000 */
2816 #define OPAMP2_CSR_PGGAIN_Pos         (14U)
2817 #define OPAMP2_CSR_PGGAIN_Msk         (0xFUL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
2818 #define OPAMP2_CSR_PGGAIN             OPAMP2_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
2819 #define OPAMP2_CSR_PGGAIN_0           (0x1UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
2820 #define OPAMP2_CSR_PGGAIN_1           (0x2UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
2821 #define OPAMP2_CSR_PGGAIN_2           (0x4UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
2822 #define OPAMP2_CSR_PGGAIN_3           (0x8UL << OPAMP2_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
2823 #define OPAMP2_CSR_USERTRIM_Pos       (18U)
2824 #define OPAMP2_CSR_USERTRIM_Msk       (0x1UL << OPAMP2_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
2825 #define OPAMP2_CSR_USERTRIM           OPAMP2_CSR_USERTRIM_Msk                  /*!< User trimming enable */
2826 #define OPAMP2_CSR_TRIMOFFSETP_Pos    (19U)
2827 #define OPAMP2_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
2828 #define OPAMP2_CSR_TRIMOFFSETP        OPAMP2_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
2829 #define OPAMP2_CSR_TRIMOFFSETN_Pos    (24U)
2830 #define OPAMP2_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
2831 #define OPAMP2_CSR_TRIMOFFSETN        OPAMP2_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
2832 #define OPAMP2_CSR_TSTREF_Pos         (29U)
2833 #define OPAMP2_CSR_TSTREF_Msk         (0x1UL << OPAMP2_CSR_TSTREF_Pos)          /*!< 0x20000000 */
2834 #define OPAMP2_CSR_TSTREF             OPAMP2_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
2835 #define OPAMP2_CSR_OUTCAL_Pos         (30U)
2836 #define OPAMP2_CSR_OUTCAL_Msk         (0x1UL << OPAMP2_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
2837 #define OPAMP2_CSR_OUTCAL             OPAMP2_CSR_OUTCAL_Msk                    /*!< OPAMP output status flag */
2838 #define OPAMP2_CSR_LOCK_Pos           (31U)
2839 #define OPAMP2_CSR_LOCK_Msk           (0x1UL << OPAMP2_CSR_LOCK_Pos)            /*!< 0x80000000 */
2840 #define OPAMP2_CSR_LOCK               OPAMP2_CSR_LOCK_Msk                      /*!< OPAMP lock */
2841 
2842 /*********************  Bit definition for OPAMP3_CSR register  ***************/
2843 #define OPAMP3_CSR_OPAMP3EN_Pos       (0U)
2844 #define OPAMP3_CSR_OPAMP3EN_Msk       (0x1UL << OPAMP3_CSR_OPAMP3EN_Pos)        /*!< 0x00000001 */
2845 #define OPAMP3_CSR_OPAMP3EN           OPAMP3_CSR_OPAMP3EN_Msk                  /*!< OPAMP3 enable */
2846 #define OPAMP3_CSR_FORCEVP_Pos        (1U)
2847 #define OPAMP3_CSR_FORCEVP_Msk        (0x1UL << OPAMP3_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
2848 #define OPAMP3_CSR_FORCEVP            OPAMP3_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
2849 #define OPAMP3_CSR_VPSEL_Pos          (2U)
2850 #define OPAMP3_CSR_VPSEL_Msk          (0x3UL << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x0000000C */
2851 #define OPAMP3_CSR_VPSEL              OPAMP3_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
2852 #define OPAMP3_CSR_VPSEL_0            (0x1UL << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x00000004 */
2853 #define OPAMP3_CSR_VPSEL_1            (0x2UL << OPAMP3_CSR_VPSEL_Pos)           /*!< 0x00000008 */
2854 #define OPAMP3_CSR_VMSEL_Pos          (5U)
2855 #define OPAMP3_CSR_VMSEL_Msk          (0x3UL << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000060 */
2856 #define OPAMP3_CSR_VMSEL              OPAMP3_CSR_VMSEL_Msk                     /*!< Inverting input selection */
2857 #define OPAMP3_CSR_VMSEL_0            (0x1UL << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000020 */
2858 #define OPAMP3_CSR_VMSEL_1            (0x2UL << OPAMP3_CSR_VMSEL_Pos)           /*!< 0x00000040 */
2859 #define OPAMP3_CSR_TCMEN_Pos          (7U)
2860 #define OPAMP3_CSR_TCMEN_Msk          (0x1UL << OPAMP3_CSR_TCMEN_Pos)           /*!< 0x00000080 */
2861 #define OPAMP3_CSR_TCMEN              OPAMP3_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
2862 #define OPAMP3_CSR_VMSSEL_Pos         (8U)
2863 #define OPAMP3_CSR_VMSSEL_Msk         (0x1UL << OPAMP3_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
2864 #define OPAMP3_CSR_VMSSEL             OPAMP3_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
2865 #define OPAMP3_CSR_VPSSEL_Pos         (9U)
2866 #define OPAMP3_CSR_VPSSEL_Msk         (0x3UL << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
2867 #define OPAMP3_CSR_VPSSEL             OPAMP3_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
2868 #define OPAMP3_CSR_VPSSEL_0           (0x1UL << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
2869 #define OPAMP3_CSR_VPSSEL_1           (0x2UL << OPAMP3_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
2870 #define OPAMP3_CSR_CALON_Pos          (11U)
2871 #define OPAMP3_CSR_CALON_Msk          (0x1UL << OPAMP3_CSR_CALON_Pos)           /*!< 0x00000800 */
2872 #define OPAMP3_CSR_CALON              OPAMP3_CSR_CALON_Msk                     /*!< Calibration mode enable */
2873 #define OPAMP3_CSR_CALSEL_Pos         (12U)
2874 #define OPAMP3_CSR_CALSEL_Msk         (0x3UL << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00003000 */
2875 #define OPAMP3_CSR_CALSEL             OPAMP3_CSR_CALSEL_Msk                    /*!< Calibration selection */
2876 #define OPAMP3_CSR_CALSEL_0           (0x1UL << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00001000 */
2877 #define OPAMP3_CSR_CALSEL_1           (0x2UL << OPAMP3_CSR_CALSEL_Pos)          /*!< 0x00002000 */
2878 #define OPAMP3_CSR_PGGAIN_Pos         (14U)
2879 #define OPAMP3_CSR_PGGAIN_Msk         (0xFUL << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
2880 #define OPAMP3_CSR_PGGAIN             OPAMP3_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
2881 #define OPAMP3_CSR_PGGAIN_0           (0x1UL << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
2882 #define OPAMP3_CSR_PGGAIN_1           (0x2UL << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
2883 #define OPAMP3_CSR_PGGAIN_2           (0x4UL << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
2884 #define OPAMP3_CSR_PGGAIN_3           (0x8UL << OPAMP3_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
2885 #define OPAMP3_CSR_USERTRIM_Pos       (18U)
2886 #define OPAMP3_CSR_USERTRIM_Msk       (0x1UL << OPAMP3_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
2887 #define OPAMP3_CSR_USERTRIM           OPAMP3_CSR_USERTRIM_Msk                  /*!< User trimming enable */
2888 #define OPAMP3_CSR_TRIMOFFSETP_Pos    (19U)
2889 #define OPAMP3_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP3_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
2890 #define OPAMP3_CSR_TRIMOFFSETP        OPAMP3_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
2891 #define OPAMP3_CSR_TRIMOFFSETN_Pos    (24U)
2892 #define OPAMP3_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP3_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
2893 #define OPAMP3_CSR_TRIMOFFSETN        OPAMP3_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
2894 #define OPAMP3_CSR_TSTREF_Pos         (29U)
2895 #define OPAMP3_CSR_TSTREF_Msk         (0x1UL << OPAMP3_CSR_TSTREF_Pos)          /*!< 0x20000000 */
2896 #define OPAMP3_CSR_TSTREF             OPAMP3_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
2897 #define OPAMP3_CSR_OUTCAL_Pos         (30U)
2898 #define OPAMP3_CSR_OUTCAL_Msk         (0x1UL << OPAMP3_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
2899 #define OPAMP3_CSR_OUTCAL             OPAMP3_CSR_OUTCAL_Msk                    /*!< OPAMP output status flag */
2900 #define OPAMP3_CSR_LOCK_Pos           (31U)
2901 #define OPAMP3_CSR_LOCK_Msk           (0x1UL << OPAMP3_CSR_LOCK_Pos)            /*!< 0x80000000 */
2902 #define OPAMP3_CSR_LOCK               OPAMP3_CSR_LOCK_Msk                      /*!< OPAMP lock */
2903 
2904 /*********************  Bit definition for OPAMP4_CSR register  ***************/
2905 #define OPAMP4_CSR_OPAMP4EN_Pos       (0U)
2906 #define OPAMP4_CSR_OPAMP4EN_Msk       (0x1UL << OPAMP4_CSR_OPAMP4EN_Pos)        /*!< 0x00000001 */
2907 #define OPAMP4_CSR_OPAMP4EN           OPAMP4_CSR_OPAMP4EN_Msk                  /*!< OPAMP4 enable */
2908 #define OPAMP4_CSR_FORCEVP_Pos        (1U)
2909 #define OPAMP4_CSR_FORCEVP_Msk        (0x1UL << OPAMP4_CSR_FORCEVP_Pos)         /*!< 0x00000002 */
2910 #define OPAMP4_CSR_FORCEVP            OPAMP4_CSR_FORCEVP_Msk                   /*!< Connect the internal references to the plus input of the OPAMPX */
2911 #define OPAMP4_CSR_VPSEL_Pos          (2U)
2912 #define OPAMP4_CSR_VPSEL_Msk          (0x3UL << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x0000000C */
2913 #define OPAMP4_CSR_VPSEL              OPAMP4_CSR_VPSEL_Msk                     /*!< Non inverting input selection */
2914 #define OPAMP4_CSR_VPSEL_0            (0x1UL << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x00000004 */
2915 #define OPAMP4_CSR_VPSEL_1            (0x2UL << OPAMP4_CSR_VPSEL_Pos)           /*!< 0x00000008 */
2916 #define OPAMP4_CSR_VMSEL_Pos          (5U)
2917 #define OPAMP4_CSR_VMSEL_Msk          (0x3UL << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000060 */
2918 #define OPAMP4_CSR_VMSEL              OPAMP4_CSR_VMSEL_Msk                     /*!< Inverting input selection */
2919 #define OPAMP4_CSR_VMSEL_0            (0x1UL << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000020 */
2920 #define OPAMP4_CSR_VMSEL_1            (0x2UL << OPAMP4_CSR_VMSEL_Pos)           /*!< 0x00000040 */
2921 #define OPAMP4_CSR_TCMEN_Pos          (7U)
2922 #define OPAMP4_CSR_TCMEN_Msk          (0x1UL << OPAMP4_CSR_TCMEN_Pos)           /*!< 0x00000080 */
2923 #define OPAMP4_CSR_TCMEN              OPAMP4_CSR_TCMEN_Msk                     /*!< Timer-Controlled Mux mode enable */
2924 #define OPAMP4_CSR_VMSSEL_Pos         (8U)
2925 #define OPAMP4_CSR_VMSSEL_Msk         (0x1UL << OPAMP4_CSR_VMSSEL_Pos)          /*!< 0x00000100 */
2926 #define OPAMP4_CSR_VMSSEL             OPAMP4_CSR_VMSSEL_Msk                    /*!< Inverting input secondary selection */
2927 #define OPAMP4_CSR_VPSSEL_Pos         (9U)
2928 #define OPAMP4_CSR_VPSSEL_Msk         (0x3UL << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000600 */
2929 #define OPAMP4_CSR_VPSSEL             OPAMP4_CSR_VPSSEL_Msk                    /*!< Non inverting input secondary selection */
2930 #define OPAMP4_CSR_VPSSEL_0           (0x1UL << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000200 */
2931 #define OPAMP4_CSR_VPSSEL_1           (0x2UL << OPAMP4_CSR_VPSSEL_Pos)          /*!< 0x00000400 */
2932 #define OPAMP4_CSR_CALON_Pos          (11U)
2933 #define OPAMP4_CSR_CALON_Msk          (0x1UL << OPAMP4_CSR_CALON_Pos)           /*!< 0x00000800 */
2934 #define OPAMP4_CSR_CALON              OPAMP4_CSR_CALON_Msk                     /*!< Calibration mode enable */
2935 #define OPAMP4_CSR_CALSEL_Pos         (12U)
2936 #define OPAMP4_CSR_CALSEL_Msk         (0x3UL << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00003000 */
2937 #define OPAMP4_CSR_CALSEL             OPAMP4_CSR_CALSEL_Msk                    /*!< Calibration selection */
2938 #define OPAMP4_CSR_CALSEL_0           (0x1UL << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00001000 */
2939 #define OPAMP4_CSR_CALSEL_1           (0x2UL << OPAMP4_CSR_CALSEL_Pos)          /*!< 0x00002000 */
2940 #define OPAMP4_CSR_PGGAIN_Pos         (14U)
2941 #define OPAMP4_CSR_PGGAIN_Msk         (0xFUL << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x0003C000 */
2942 #define OPAMP4_CSR_PGGAIN             OPAMP4_CSR_PGGAIN_Msk                    /*!< Gain in PGA mode */
2943 #define OPAMP4_CSR_PGGAIN_0           (0x1UL << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00004000 */
2944 #define OPAMP4_CSR_PGGAIN_1           (0x2UL << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00008000 */
2945 #define OPAMP4_CSR_PGGAIN_2           (0x4UL << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00010000 */
2946 #define OPAMP4_CSR_PGGAIN_3           (0x8UL << OPAMP4_CSR_PGGAIN_Pos)          /*!< 0x00020000 */
2947 #define OPAMP4_CSR_USERTRIM_Pos       (18U)
2948 #define OPAMP4_CSR_USERTRIM_Msk       (0x1UL << OPAMP4_CSR_USERTRIM_Pos)        /*!< 0x00040000 */
2949 #define OPAMP4_CSR_USERTRIM           OPAMP4_CSR_USERTRIM_Msk                  /*!< User trimming enable */
2950 #define OPAMP4_CSR_TRIMOFFSETP_Pos    (19U)
2951 #define OPAMP4_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP4_CSR_TRIMOFFSETP_Pos)    /*!< 0x00F80000 */
2952 #define OPAMP4_CSR_TRIMOFFSETP        OPAMP4_CSR_TRIMOFFSETP_Msk               /*!< Offset trimming value (PMOS) */
2953 #define OPAMP4_CSR_TRIMOFFSETN_Pos    (24U)
2954 #define OPAMP4_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP4_CSR_TRIMOFFSETN_Pos)    /*!< 0x1F000000 */
2955 #define OPAMP4_CSR_TRIMOFFSETN        OPAMP4_CSR_TRIMOFFSETN_Msk               /*!< Offset trimming value (NMOS) */
2956 #define OPAMP4_CSR_TSTREF_Pos         (29U)
2957 #define OPAMP4_CSR_TSTREF_Msk         (0x1UL << OPAMP4_CSR_TSTREF_Pos)          /*!< 0x20000000 */
2958 #define OPAMP4_CSR_TSTREF             OPAMP4_CSR_TSTREF_Msk                    /*!< It enables the switch to put out the internal reference */
2959 #define OPAMP4_CSR_OUTCAL_Pos         (30U)
2960 #define OPAMP4_CSR_OUTCAL_Msk         (0x1UL << OPAMP4_CSR_OUTCAL_Pos)          /*!< 0x40000000 */
2961 #define OPAMP4_CSR_OUTCAL             OPAMP4_CSR_OUTCAL_Msk                    /*!< OPAMP output status flag */
2962 #define OPAMP4_CSR_LOCK_Pos           (31U)
2963 #define OPAMP4_CSR_LOCK_Msk           (0x1UL << OPAMP4_CSR_LOCK_Pos)            /*!< 0x80000000 */
2964 #define OPAMP4_CSR_LOCK               OPAMP4_CSR_LOCK_Msk                      /*!< OPAMP lock */
2965 
2966 /*********************  Bit definition for OPAMPx_CSR register  ***************/
2967 #define OPAMP_CSR_OPAMPxEN_Pos       (0U)
2968 #define OPAMP_CSR_OPAMPxEN_Msk       (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)          /*!< 0x00000001 */
2969 #define OPAMP_CSR_OPAMPxEN           OPAMP_CSR_OPAMPxEN_Msk                    /*!< OPAMP enable */
2970 #define OPAMP_CSR_FORCEVP_Pos        (1U)
2971 #define OPAMP_CSR_FORCEVP_Msk        (0x1UL << OPAMP_CSR_FORCEVP_Pos)           /*!< 0x00000002 */
2972 #define OPAMP_CSR_FORCEVP            OPAMP_CSR_FORCEVP_Msk                     /*!< Connect the internal references to the plus input of the OPAMPX */
2973 #define OPAMP_CSR_VPSEL_Pos          (2U)
2974 #define OPAMP_CSR_VPSEL_Msk          (0x3UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x0000000C */
2975 #define OPAMP_CSR_VPSEL              OPAMP_CSR_VPSEL_Msk                       /*!< Non inverting input selection */
2976 #define OPAMP_CSR_VPSEL_0            (0x1UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000004 */
2977 #define OPAMP_CSR_VPSEL_1            (0x2UL << OPAMP_CSR_VPSEL_Pos)             /*!< 0x00000008 */
2978 #define OPAMP_CSR_VMSEL_Pos          (5U)
2979 #define OPAMP_CSR_VMSEL_Msk          (0x3UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000060 */
2980 #define OPAMP_CSR_VMSEL              OPAMP_CSR_VMSEL_Msk                       /*!< Inverting input selection */
2981 #define OPAMP_CSR_VMSEL_0            (0x1UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000020 */
2982 #define OPAMP_CSR_VMSEL_1            (0x2UL << OPAMP_CSR_VMSEL_Pos)             /*!< 0x00000040 */
2983 #define OPAMP_CSR_TCMEN_Pos          (7U)
2984 #define OPAMP_CSR_TCMEN_Msk          (0x1UL << OPAMP_CSR_TCMEN_Pos)             /*!< 0x00000080 */
2985 #define OPAMP_CSR_TCMEN              OPAMP_CSR_TCMEN_Msk                       /*!< Timer-Controlled Mux mode enable */
2986 #define OPAMP_CSR_VMSSEL_Pos         (8U)
2987 #define OPAMP_CSR_VMSSEL_Msk         (0x1UL << OPAMP_CSR_VMSSEL_Pos)            /*!< 0x00000100 */
2988 #define OPAMP_CSR_VMSSEL             OPAMP_CSR_VMSSEL_Msk                      /*!< Inverting input secondary selection */
2989 #define OPAMP_CSR_VPSSEL_Pos         (9U)
2990 #define OPAMP_CSR_VPSSEL_Msk         (0x3UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000600 */
2991 #define OPAMP_CSR_VPSSEL             OPAMP_CSR_VPSSEL_Msk                      /*!< Non inverting input secondary selection */
2992 #define OPAMP_CSR_VPSSEL_0           (0x1UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000200 */
2993 #define OPAMP_CSR_VPSSEL_1           (0x2UL << OPAMP_CSR_VPSSEL_Pos)            /*!< 0x00000400 */
2994 #define OPAMP_CSR_CALON_Pos          (11U)
2995 #define OPAMP_CSR_CALON_Msk          (0x1UL << OPAMP_CSR_CALON_Pos)             /*!< 0x00000800 */
2996 #define OPAMP_CSR_CALON              OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
2997 #define OPAMP_CSR_CALSEL_Pos         (12U)
2998 #define OPAMP_CSR_CALSEL_Msk         (0x3UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00003000 */
2999 #define OPAMP_CSR_CALSEL             OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
3000 #define OPAMP_CSR_CALSEL_0           (0x1UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00001000 */
3001 #define OPAMP_CSR_CALSEL_1           (0x2UL << OPAMP_CSR_CALSEL_Pos)            /*!< 0x00002000 */
3002 #define OPAMP_CSR_PGGAIN_Pos         (14U)
3003 #define OPAMP_CSR_PGGAIN_Msk         (0xFUL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x0003C000 */
3004 #define OPAMP_CSR_PGGAIN             OPAMP_CSR_PGGAIN_Msk                      /*!< Gain in PGA mode */
3005 #define OPAMP_CSR_PGGAIN_0           (0x1UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00004000 */
3006 #define OPAMP_CSR_PGGAIN_1           (0x2UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00008000 */
3007 #define OPAMP_CSR_PGGAIN_2           (0x4UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00010000 */
3008 #define OPAMP_CSR_PGGAIN_3           (0x8UL << OPAMP_CSR_PGGAIN_Pos)            /*!< 0x00020000 */
3009 #define OPAMP_CSR_USERTRIM_Pos       (18U)
3010 #define OPAMP_CSR_USERTRIM_Msk       (0x1UL << OPAMP_CSR_USERTRIM_Pos)          /*!< 0x00040000 */
3011 #define OPAMP_CSR_USERTRIM           OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
3012 #define OPAMP_CSR_TRIMOFFSETP_Pos    (19U)
3013 #define OPAMP_CSR_TRIMOFFSETP_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)      /*!< 0x00F80000 */
3014 #define OPAMP_CSR_TRIMOFFSETP        OPAMP_CSR_TRIMOFFSETP_Msk                 /*!< Offset trimming value (PMOS) */
3015 #define OPAMP_CSR_TRIMOFFSETN_Pos    (24U)
3016 #define OPAMP_CSR_TRIMOFFSETN_Msk    (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)      /*!< 0x1F000000 */
3017 #define OPAMP_CSR_TRIMOFFSETN        OPAMP_CSR_TRIMOFFSETN_Msk                 /*!< Offset trimming value (NMOS) */
3018 #define OPAMP_CSR_TSTREF_Pos         (29U)
3019 #define OPAMP_CSR_TSTREF_Msk         (0x1UL << OPAMP_CSR_TSTREF_Pos)            /*!< 0x20000000 */
3020 #define OPAMP_CSR_TSTREF             OPAMP_CSR_TSTREF_Msk                      /*!< It enables the switch to put out the internal reference */
3021 #define OPAMP_CSR_OUTCAL_Pos         (30U)
3022 #define OPAMP_CSR_OUTCAL_Msk         (0x1UL << OPAMP_CSR_OUTCAL_Pos)            /*!< 0x40000000 */
3023 #define OPAMP_CSR_OUTCAL             OPAMP_CSR_OUTCAL_Msk                      /*!< OPAMP output status flag */
3024 #define OPAMP_CSR_LOCK_Pos           (31U)
3025 #define OPAMP_CSR_LOCK_Msk           (0x1UL << OPAMP_CSR_LOCK_Pos)              /*!< 0x80000000 */
3026 #define OPAMP_CSR_LOCK               OPAMP_CSR_LOCK_Msk                        /*!< OPAMP lock */
3027 
3028 /******************************************************************************/
3029 /*                                                                            */
3030 /*                   Controller Area Network (CAN )                           */
3031 /*                                                                            */
3032 /******************************************************************************/
3033 /*******************  Bit definition for CAN_MCR register  ********************/
3034 #define CAN_MCR_INRQ_Pos       (0U)
3035 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
3036 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
3037 #define CAN_MCR_SLEEP_Pos      (1U)
3038 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
3039 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
3040 #define CAN_MCR_TXFP_Pos       (2U)
3041 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
3042 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
3043 #define CAN_MCR_RFLM_Pos       (3U)
3044 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
3045 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
3046 #define CAN_MCR_NART_Pos       (4U)
3047 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
3048 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
3049 #define CAN_MCR_AWUM_Pos       (5U)
3050 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
3051 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
3052 #define CAN_MCR_ABOM_Pos       (6U)
3053 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
3054 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
3055 #define CAN_MCR_TTCM_Pos       (7U)
3056 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
3057 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
3058 #define CAN_MCR_RESET_Pos      (15U)
3059 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
3060 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
3061 
3062 /*******************  Bit definition for CAN_MSR register  ********************/
3063 #define CAN_MSR_INAK_Pos       (0U)
3064 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
3065 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
3066 #define CAN_MSR_SLAK_Pos       (1U)
3067 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
3068 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
3069 #define CAN_MSR_ERRI_Pos       (2U)
3070 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
3071 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
3072 #define CAN_MSR_WKUI_Pos       (3U)
3073 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
3074 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
3075 #define CAN_MSR_SLAKI_Pos      (4U)
3076 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
3077 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
3078 #define CAN_MSR_TXM_Pos        (8U)
3079 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
3080 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
3081 #define CAN_MSR_RXM_Pos        (9U)
3082 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
3083 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
3084 #define CAN_MSR_SAMP_Pos       (10U)
3085 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
3086 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
3087 #define CAN_MSR_RX_Pos         (11U)
3088 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
3089 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
3090 
3091 /*******************  Bit definition for CAN_TSR register  ********************/
3092 #define CAN_TSR_RQCP0_Pos      (0U)
3093 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
3094 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
3095 #define CAN_TSR_TXOK0_Pos      (1U)
3096 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
3097 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
3098 #define CAN_TSR_ALST0_Pos      (2U)
3099 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
3100 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
3101 #define CAN_TSR_TERR0_Pos      (3U)
3102 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
3103 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
3104 #define CAN_TSR_ABRQ0_Pos      (7U)
3105 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
3106 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
3107 #define CAN_TSR_RQCP1_Pos      (8U)
3108 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
3109 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
3110 #define CAN_TSR_TXOK1_Pos      (9U)
3111 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
3112 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
3113 #define CAN_TSR_ALST1_Pos      (10U)
3114 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
3115 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
3116 #define CAN_TSR_TERR1_Pos      (11U)
3117 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
3118 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
3119 #define CAN_TSR_ABRQ1_Pos      (15U)
3120 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
3121 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
3122 #define CAN_TSR_RQCP2_Pos      (16U)
3123 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
3124 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
3125 #define CAN_TSR_TXOK2_Pos      (17U)
3126 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
3127 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
3128 #define CAN_TSR_ALST2_Pos      (18U)
3129 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
3130 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
3131 #define CAN_TSR_TERR2_Pos      (19U)
3132 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
3133 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
3134 #define CAN_TSR_ABRQ2_Pos      (23U)
3135 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
3136 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
3137 #define CAN_TSR_CODE_Pos       (24U)
3138 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
3139 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
3140 
3141 #define CAN_TSR_TME_Pos        (26U)
3142 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
3143 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
3144 #define CAN_TSR_TME0_Pos       (26U)
3145 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
3146 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
3147 #define CAN_TSR_TME1_Pos       (27U)
3148 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
3149 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
3150 #define CAN_TSR_TME2_Pos       (28U)
3151 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
3152 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
3153 
3154 #define CAN_TSR_LOW_Pos        (29U)
3155 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
3156 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
3157 #define CAN_TSR_LOW0_Pos       (29U)
3158 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
3159 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
3160 #define CAN_TSR_LOW1_Pos       (30U)
3161 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
3162 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
3163 #define CAN_TSR_LOW2_Pos       (31U)
3164 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
3165 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
3166 
3167 /*******************  Bit definition for CAN_RF0R register  *******************/
3168 #define CAN_RF0R_FMP0_Pos      (0U)
3169 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
3170 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
3171 #define CAN_RF0R_FULL0_Pos     (3U)
3172 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
3173 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
3174 #define CAN_RF0R_FOVR0_Pos     (4U)
3175 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
3176 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
3177 #define CAN_RF0R_RFOM0_Pos     (5U)
3178 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
3179 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
3180 
3181 /*******************  Bit definition for CAN_RF1R register  *******************/
3182 #define CAN_RF1R_FMP1_Pos      (0U)
3183 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
3184 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
3185 #define CAN_RF1R_FULL1_Pos     (3U)
3186 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
3187 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
3188 #define CAN_RF1R_FOVR1_Pos     (4U)
3189 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
3190 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
3191 #define CAN_RF1R_RFOM1_Pos     (5U)
3192 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
3193 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
3194 
3195 /********************  Bit definition for CAN_IER register  *******************/
3196 #define CAN_IER_TMEIE_Pos      (0U)
3197 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
3198 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
3199 #define CAN_IER_FMPIE0_Pos     (1U)
3200 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
3201 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
3202 #define CAN_IER_FFIE0_Pos      (2U)
3203 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
3204 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
3205 #define CAN_IER_FOVIE0_Pos     (3U)
3206 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
3207 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
3208 #define CAN_IER_FMPIE1_Pos     (4U)
3209 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
3210 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
3211 #define CAN_IER_FFIE1_Pos      (5U)
3212 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
3213 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
3214 #define CAN_IER_FOVIE1_Pos     (6U)
3215 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
3216 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
3217 #define CAN_IER_EWGIE_Pos      (8U)
3218 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
3219 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
3220 #define CAN_IER_EPVIE_Pos      (9U)
3221 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
3222 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
3223 #define CAN_IER_BOFIE_Pos      (10U)
3224 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
3225 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
3226 #define CAN_IER_LECIE_Pos      (11U)
3227 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
3228 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
3229 #define CAN_IER_ERRIE_Pos      (15U)
3230 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
3231 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
3232 #define CAN_IER_WKUIE_Pos      (16U)
3233 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
3234 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
3235 #define CAN_IER_SLKIE_Pos      (17U)
3236 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
3237 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
3238 
3239 /********************  Bit definition for CAN_ESR register  *******************/
3240 #define CAN_ESR_EWGF_Pos       (0U)
3241 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
3242 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
3243 #define CAN_ESR_EPVF_Pos       (1U)
3244 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
3245 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
3246 #define CAN_ESR_BOFF_Pos       (2U)
3247 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
3248 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
3249 
3250 #define CAN_ESR_LEC_Pos        (4U)
3251 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
3252 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
3253 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
3254 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
3255 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
3256 
3257 #define CAN_ESR_TEC_Pos        (16U)
3258 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
3259 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
3260 #define CAN_ESR_REC_Pos        (24U)
3261 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
3262 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
3263 
3264 /*******************  Bit definition for CAN_BTR register  ********************/
3265 #define CAN_BTR_BRP_Pos        (0U)
3266 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
3267 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
3268 #define CAN_BTR_TS1_Pos        (16U)
3269 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
3270 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
3271 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
3272 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
3273 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
3274 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
3275 #define CAN_BTR_TS2_Pos        (20U)
3276 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
3277 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
3278 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
3279 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
3280 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
3281 #define CAN_BTR_SJW_Pos        (24U)
3282 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
3283 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
3284 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
3285 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
3286 #define CAN_BTR_LBKM_Pos       (30U)
3287 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
3288 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
3289 #define CAN_BTR_SILM_Pos       (31U)
3290 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
3291 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
3292 
3293 /*!<Mailbox registers */
3294 /******************  Bit definition for CAN_TI0R register  ********************/
3295 #define CAN_TI0R_TXRQ_Pos      (0U)
3296 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
3297 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3298 #define CAN_TI0R_RTR_Pos       (1U)
3299 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
3300 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
3301 #define CAN_TI0R_IDE_Pos       (2U)
3302 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
3303 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
3304 #define CAN_TI0R_EXID_Pos      (3U)
3305 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
3306 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
3307 #define CAN_TI0R_STID_Pos      (21U)
3308 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
3309 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3310 
3311 /******************  Bit definition for CAN_TDT0R register  *******************/
3312 #define CAN_TDT0R_DLC_Pos      (0U)
3313 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
3314 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
3315 #define CAN_TDT0R_TGT_Pos      (8U)
3316 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
3317 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
3318 #define CAN_TDT0R_TIME_Pos     (16U)
3319 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
3320 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
3321 
3322 /******************  Bit definition for CAN_TDL0R register  *******************/
3323 #define CAN_TDL0R_DATA0_Pos    (0U)
3324 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
3325 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
3326 #define CAN_TDL0R_DATA1_Pos    (8U)
3327 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
3328 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
3329 #define CAN_TDL0R_DATA2_Pos    (16U)
3330 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
3331 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
3332 #define CAN_TDL0R_DATA3_Pos    (24U)
3333 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
3334 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
3335 
3336 /******************  Bit definition for CAN_TDH0R register  *******************/
3337 #define CAN_TDH0R_DATA4_Pos    (0U)
3338 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
3339 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
3340 #define CAN_TDH0R_DATA5_Pos    (8U)
3341 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
3342 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
3343 #define CAN_TDH0R_DATA6_Pos    (16U)
3344 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
3345 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
3346 #define CAN_TDH0R_DATA7_Pos    (24U)
3347 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
3348 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
3349 
3350 /*******************  Bit definition for CAN_TI1R register  *******************/
3351 #define CAN_TI1R_TXRQ_Pos      (0U)
3352 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
3353 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3354 #define CAN_TI1R_RTR_Pos       (1U)
3355 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
3356 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
3357 #define CAN_TI1R_IDE_Pos       (2U)
3358 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
3359 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
3360 #define CAN_TI1R_EXID_Pos      (3U)
3361 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
3362 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
3363 #define CAN_TI1R_STID_Pos      (21U)
3364 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
3365 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3366 
3367 /*******************  Bit definition for CAN_TDT1R register  ******************/
3368 #define CAN_TDT1R_DLC_Pos      (0U)
3369 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
3370 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
3371 #define CAN_TDT1R_TGT_Pos      (8U)
3372 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
3373 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
3374 #define CAN_TDT1R_TIME_Pos     (16U)
3375 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
3376 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
3377 
3378 /*******************  Bit definition for CAN_TDL1R register  ******************/
3379 #define CAN_TDL1R_DATA0_Pos    (0U)
3380 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
3381 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
3382 #define CAN_TDL1R_DATA1_Pos    (8U)
3383 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
3384 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
3385 #define CAN_TDL1R_DATA2_Pos    (16U)
3386 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
3387 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
3388 #define CAN_TDL1R_DATA3_Pos    (24U)
3389 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
3390 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
3391 
3392 /*******************  Bit definition for CAN_TDH1R register  ******************/
3393 #define CAN_TDH1R_DATA4_Pos    (0U)
3394 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
3395 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
3396 #define CAN_TDH1R_DATA5_Pos    (8U)
3397 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
3398 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
3399 #define CAN_TDH1R_DATA6_Pos    (16U)
3400 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
3401 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
3402 #define CAN_TDH1R_DATA7_Pos    (24U)
3403 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
3404 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
3405 
3406 /*******************  Bit definition for CAN_TI2R register  *******************/
3407 #define CAN_TI2R_TXRQ_Pos      (0U)
3408 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
3409 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3410 #define CAN_TI2R_RTR_Pos       (1U)
3411 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
3412 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
3413 #define CAN_TI2R_IDE_Pos       (2U)
3414 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
3415 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
3416 #define CAN_TI2R_EXID_Pos      (3U)
3417 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
3418 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
3419 #define CAN_TI2R_STID_Pos      (21U)
3420 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
3421 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3422 
3423 /*******************  Bit definition for CAN_TDT2R register  ******************/
3424 #define CAN_TDT2R_DLC_Pos      (0U)
3425 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
3426 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
3427 #define CAN_TDT2R_TGT_Pos      (8U)
3428 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
3429 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
3430 #define CAN_TDT2R_TIME_Pos     (16U)
3431 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
3432 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
3433 
3434 /*******************  Bit definition for CAN_TDL2R register  ******************/
3435 #define CAN_TDL2R_DATA0_Pos    (0U)
3436 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
3437 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
3438 #define CAN_TDL2R_DATA1_Pos    (8U)
3439 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
3440 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
3441 #define CAN_TDL2R_DATA2_Pos    (16U)
3442 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
3443 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
3444 #define CAN_TDL2R_DATA3_Pos    (24U)
3445 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
3446 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
3447 
3448 /*******************  Bit definition for CAN_TDH2R register  ******************/
3449 #define CAN_TDH2R_DATA4_Pos    (0U)
3450 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
3451 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
3452 #define CAN_TDH2R_DATA5_Pos    (8U)
3453 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
3454 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
3455 #define CAN_TDH2R_DATA6_Pos    (16U)
3456 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
3457 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
3458 #define CAN_TDH2R_DATA7_Pos    (24U)
3459 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
3460 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
3461 
3462 /*******************  Bit definition for CAN_RI0R register  *******************/
3463 #define CAN_RI0R_RTR_Pos       (1U)
3464 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
3465 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
3466 #define CAN_RI0R_IDE_Pos       (2U)
3467 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
3468 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
3469 #define CAN_RI0R_EXID_Pos      (3U)
3470 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
3471 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
3472 #define CAN_RI0R_STID_Pos      (21U)
3473 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
3474 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3475 
3476 /*******************  Bit definition for CAN_RDT0R register  ******************/
3477 #define CAN_RDT0R_DLC_Pos      (0U)
3478 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
3479 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
3480 #define CAN_RDT0R_FMI_Pos      (8U)
3481 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
3482 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
3483 #define CAN_RDT0R_TIME_Pos     (16U)
3484 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
3485 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
3486 
3487 /*******************  Bit definition for CAN_RDL0R register  ******************/
3488 #define CAN_RDL0R_DATA0_Pos    (0U)
3489 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
3490 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
3491 #define CAN_RDL0R_DATA1_Pos    (8U)
3492 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
3493 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
3494 #define CAN_RDL0R_DATA2_Pos    (16U)
3495 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
3496 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
3497 #define CAN_RDL0R_DATA3_Pos    (24U)
3498 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
3499 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
3500 
3501 /*******************  Bit definition for CAN_RDH0R register  ******************/
3502 #define CAN_RDH0R_DATA4_Pos    (0U)
3503 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
3504 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
3505 #define CAN_RDH0R_DATA5_Pos    (8U)
3506 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
3507 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
3508 #define CAN_RDH0R_DATA6_Pos    (16U)
3509 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
3510 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
3511 #define CAN_RDH0R_DATA7_Pos    (24U)
3512 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
3513 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
3514 
3515 /*******************  Bit definition for CAN_RI1R register  *******************/
3516 #define CAN_RI1R_RTR_Pos       (1U)
3517 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
3518 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
3519 #define CAN_RI1R_IDE_Pos       (2U)
3520 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
3521 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
3522 #define CAN_RI1R_EXID_Pos      (3U)
3523 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
3524 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
3525 #define CAN_RI1R_STID_Pos      (21U)
3526 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
3527 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3528 
3529 /*******************  Bit definition for CAN_RDT1R register  ******************/
3530 #define CAN_RDT1R_DLC_Pos      (0U)
3531 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
3532 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
3533 #define CAN_RDT1R_FMI_Pos      (8U)
3534 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
3535 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
3536 #define CAN_RDT1R_TIME_Pos     (16U)
3537 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
3538 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
3539 
3540 /*******************  Bit definition for CAN_RDL1R register  ******************/
3541 #define CAN_RDL1R_DATA0_Pos    (0U)
3542 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
3543 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
3544 #define CAN_RDL1R_DATA1_Pos    (8U)
3545 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
3546 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
3547 #define CAN_RDL1R_DATA2_Pos    (16U)
3548 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
3549 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
3550 #define CAN_RDL1R_DATA3_Pos    (24U)
3551 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
3552 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
3553 
3554 /*******************  Bit definition for CAN_RDH1R register  ******************/
3555 #define CAN_RDH1R_DATA4_Pos    (0U)
3556 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
3557 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
3558 #define CAN_RDH1R_DATA5_Pos    (8U)
3559 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
3560 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
3561 #define CAN_RDH1R_DATA6_Pos    (16U)
3562 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
3563 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
3564 #define CAN_RDH1R_DATA7_Pos    (24U)
3565 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
3566 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
3567 
3568 /*!<CAN filter registers */
3569 /*******************  Bit definition for CAN_FMR register  ********************/
3570 #define CAN_FMR_FINIT_Pos      (0U)
3571 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
3572 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
3573 
3574 /*******************  Bit definition for CAN_FM1R register  *******************/
3575 #define CAN_FM1R_FBM_Pos       (0U)
3576 #define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
3577 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
3578 #define CAN_FM1R_FBM0_Pos      (0U)
3579 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
3580 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
3581 #define CAN_FM1R_FBM1_Pos      (1U)
3582 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
3583 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
3584 #define CAN_FM1R_FBM2_Pos      (2U)
3585 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
3586 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
3587 #define CAN_FM1R_FBM3_Pos      (3U)
3588 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
3589 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
3590 #define CAN_FM1R_FBM4_Pos      (4U)
3591 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
3592 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
3593 #define CAN_FM1R_FBM5_Pos      (5U)
3594 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
3595 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
3596 #define CAN_FM1R_FBM6_Pos      (6U)
3597 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
3598 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
3599 #define CAN_FM1R_FBM7_Pos      (7U)
3600 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
3601 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
3602 #define CAN_FM1R_FBM8_Pos      (8U)
3603 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
3604 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
3605 #define CAN_FM1R_FBM9_Pos      (9U)
3606 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
3607 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
3608 #define CAN_FM1R_FBM10_Pos     (10U)
3609 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
3610 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
3611 #define CAN_FM1R_FBM11_Pos     (11U)
3612 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
3613 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
3614 #define CAN_FM1R_FBM12_Pos     (12U)
3615 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
3616 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
3617 #define CAN_FM1R_FBM13_Pos     (13U)
3618 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
3619 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
3620 
3621 /*******************  Bit definition for CAN_FS1R register  *******************/
3622 #define CAN_FS1R_FSC_Pos       (0U)
3623 #define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
3624 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
3625 #define CAN_FS1R_FSC0_Pos      (0U)
3626 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
3627 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
3628 #define CAN_FS1R_FSC1_Pos      (1U)
3629 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
3630 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
3631 #define CAN_FS1R_FSC2_Pos      (2U)
3632 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
3633 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
3634 #define CAN_FS1R_FSC3_Pos      (3U)
3635 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
3636 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
3637 #define CAN_FS1R_FSC4_Pos      (4U)
3638 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
3639 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
3640 #define CAN_FS1R_FSC5_Pos      (5U)
3641 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
3642 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
3643 #define CAN_FS1R_FSC6_Pos      (6U)
3644 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
3645 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
3646 #define CAN_FS1R_FSC7_Pos      (7U)
3647 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
3648 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
3649 #define CAN_FS1R_FSC8_Pos      (8U)
3650 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
3651 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
3652 #define CAN_FS1R_FSC9_Pos      (9U)
3653 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
3654 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
3655 #define CAN_FS1R_FSC10_Pos     (10U)
3656 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
3657 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
3658 #define CAN_FS1R_FSC11_Pos     (11U)
3659 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
3660 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
3661 #define CAN_FS1R_FSC12_Pos     (12U)
3662 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
3663 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
3664 #define CAN_FS1R_FSC13_Pos     (13U)
3665 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
3666 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
3667 
3668 /******************  Bit definition for CAN_FFA1R register  *******************/
3669 #define CAN_FFA1R_FFA_Pos      (0U)
3670 #define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
3671 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
3672 #define CAN_FFA1R_FFA0_Pos     (0U)
3673 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
3674 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
3675 #define CAN_FFA1R_FFA1_Pos     (1U)
3676 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
3677 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
3678 #define CAN_FFA1R_FFA2_Pos     (2U)
3679 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
3680 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
3681 #define CAN_FFA1R_FFA3_Pos     (3U)
3682 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
3683 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
3684 #define CAN_FFA1R_FFA4_Pos     (4U)
3685 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
3686 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
3687 #define CAN_FFA1R_FFA5_Pos     (5U)
3688 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
3689 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
3690 #define CAN_FFA1R_FFA6_Pos     (6U)
3691 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
3692 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
3693 #define CAN_FFA1R_FFA7_Pos     (7U)
3694 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
3695 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
3696 #define CAN_FFA1R_FFA8_Pos     (8U)
3697 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
3698 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
3699 #define CAN_FFA1R_FFA9_Pos     (9U)
3700 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
3701 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
3702 #define CAN_FFA1R_FFA10_Pos    (10U)
3703 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
3704 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
3705 #define CAN_FFA1R_FFA11_Pos    (11U)
3706 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
3707 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
3708 #define CAN_FFA1R_FFA12_Pos    (12U)
3709 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
3710 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
3711 #define CAN_FFA1R_FFA13_Pos    (13U)
3712 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
3713 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
3714 
3715 /*******************  Bit definition for CAN_FA1R register  *******************/
3716 #define CAN_FA1R_FACT_Pos      (0U)
3717 #define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
3718 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
3719 #define CAN_FA1R_FACT0_Pos     (0U)
3720 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
3721 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
3722 #define CAN_FA1R_FACT1_Pos     (1U)
3723 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
3724 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
3725 #define CAN_FA1R_FACT2_Pos     (2U)
3726 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
3727 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
3728 #define CAN_FA1R_FACT3_Pos     (3U)
3729 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
3730 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
3731 #define CAN_FA1R_FACT4_Pos     (4U)
3732 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
3733 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
3734 #define CAN_FA1R_FACT5_Pos     (5U)
3735 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
3736 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
3737 #define CAN_FA1R_FACT6_Pos     (6U)
3738 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
3739 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
3740 #define CAN_FA1R_FACT7_Pos     (7U)
3741 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
3742 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
3743 #define CAN_FA1R_FACT8_Pos     (8U)
3744 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
3745 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
3746 #define CAN_FA1R_FACT9_Pos     (9U)
3747 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
3748 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
3749 #define CAN_FA1R_FACT10_Pos    (10U)
3750 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
3751 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
3752 #define CAN_FA1R_FACT11_Pos    (11U)
3753 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
3754 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
3755 #define CAN_FA1R_FACT12_Pos    (12U)
3756 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
3757 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
3758 #define CAN_FA1R_FACT13_Pos    (13U)
3759 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
3760 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
3761 
3762 /*******************  Bit definition for CAN_F0R1 register  *******************/
3763 #define CAN_F0R1_FB0_Pos       (0U)
3764 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
3765 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
3766 #define CAN_F0R1_FB1_Pos       (1U)
3767 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
3768 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
3769 #define CAN_F0R1_FB2_Pos       (2U)
3770 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
3771 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
3772 #define CAN_F0R1_FB3_Pos       (3U)
3773 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
3774 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
3775 #define CAN_F0R1_FB4_Pos       (4U)
3776 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
3777 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
3778 #define CAN_F0R1_FB5_Pos       (5U)
3779 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
3780 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
3781 #define CAN_F0R1_FB6_Pos       (6U)
3782 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
3783 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
3784 #define CAN_F0R1_FB7_Pos       (7U)
3785 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
3786 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
3787 #define CAN_F0R1_FB8_Pos       (8U)
3788 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
3789 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
3790 #define CAN_F0R1_FB9_Pos       (9U)
3791 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
3792 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
3793 #define CAN_F0R1_FB10_Pos      (10U)
3794 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
3795 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
3796 #define CAN_F0R1_FB11_Pos      (11U)
3797 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
3798 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
3799 #define CAN_F0R1_FB12_Pos      (12U)
3800 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
3801 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
3802 #define CAN_F0R1_FB13_Pos      (13U)
3803 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
3804 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
3805 #define CAN_F0R1_FB14_Pos      (14U)
3806 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
3807 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
3808 #define CAN_F0R1_FB15_Pos      (15U)
3809 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
3810 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
3811 #define CAN_F0R1_FB16_Pos      (16U)
3812 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
3813 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
3814 #define CAN_F0R1_FB17_Pos      (17U)
3815 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
3816 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
3817 #define CAN_F0R1_FB18_Pos      (18U)
3818 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
3819 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
3820 #define CAN_F0R1_FB19_Pos      (19U)
3821 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
3822 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
3823 #define CAN_F0R1_FB20_Pos      (20U)
3824 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
3825 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
3826 #define CAN_F0R1_FB21_Pos      (21U)
3827 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
3828 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
3829 #define CAN_F0R1_FB22_Pos      (22U)
3830 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
3831 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
3832 #define CAN_F0R1_FB23_Pos      (23U)
3833 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
3834 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
3835 #define CAN_F0R1_FB24_Pos      (24U)
3836 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
3837 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
3838 #define CAN_F0R1_FB25_Pos      (25U)
3839 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
3840 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
3841 #define CAN_F0R1_FB26_Pos      (26U)
3842 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
3843 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
3844 #define CAN_F0R1_FB27_Pos      (27U)
3845 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
3846 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
3847 #define CAN_F0R1_FB28_Pos      (28U)
3848 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
3849 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
3850 #define CAN_F0R1_FB29_Pos      (29U)
3851 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
3852 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
3853 #define CAN_F0R1_FB30_Pos      (30U)
3854 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
3855 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
3856 #define CAN_F0R1_FB31_Pos      (31U)
3857 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
3858 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
3859 
3860 /*******************  Bit definition for CAN_F1R1 register  *******************/
3861 #define CAN_F1R1_FB0_Pos       (0U)
3862 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
3863 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
3864 #define CAN_F1R1_FB1_Pos       (1U)
3865 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
3866 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3867 #define CAN_F1R1_FB2_Pos       (2U)
3868 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
3869 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3870 #define CAN_F1R1_FB3_Pos       (3U)
3871 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
3872 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3873 #define CAN_F1R1_FB4_Pos       (4U)
3874 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
3875 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3876 #define CAN_F1R1_FB5_Pos       (5U)
3877 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
3878 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3879 #define CAN_F1R1_FB6_Pos       (6U)
3880 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
3881 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3882 #define CAN_F1R1_FB7_Pos       (7U)
3883 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
3884 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3885 #define CAN_F1R1_FB8_Pos       (8U)
3886 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
3887 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3888 #define CAN_F1R1_FB9_Pos       (9U)
3889 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
3890 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3891 #define CAN_F1R1_FB10_Pos      (10U)
3892 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
3893 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3894 #define CAN_F1R1_FB11_Pos      (11U)
3895 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
3896 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3897 #define CAN_F1R1_FB12_Pos      (12U)
3898 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
3899 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3900 #define CAN_F1R1_FB13_Pos      (13U)
3901 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
3902 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3903 #define CAN_F1R1_FB14_Pos      (14U)
3904 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
3905 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3906 #define CAN_F1R1_FB15_Pos      (15U)
3907 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
3908 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3909 #define CAN_F1R1_FB16_Pos      (16U)
3910 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
3911 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3912 #define CAN_F1R1_FB17_Pos      (17U)
3913 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
3914 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3915 #define CAN_F1R1_FB18_Pos      (18U)
3916 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
3917 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3918 #define CAN_F1R1_FB19_Pos      (19U)
3919 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
3920 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3921 #define CAN_F1R1_FB20_Pos      (20U)
3922 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
3923 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3924 #define CAN_F1R1_FB21_Pos      (21U)
3925 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
3926 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3927 #define CAN_F1R1_FB22_Pos      (22U)
3928 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
3929 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3930 #define CAN_F1R1_FB23_Pos      (23U)
3931 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
3932 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3933 #define CAN_F1R1_FB24_Pos      (24U)
3934 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
3935 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3936 #define CAN_F1R1_FB25_Pos      (25U)
3937 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3938 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3939 #define CAN_F1R1_FB26_Pos      (26U)
3940 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3941 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3942 #define CAN_F1R1_FB27_Pos      (27U)
3943 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3944 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3945 #define CAN_F1R1_FB28_Pos      (28U)
3946 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3947 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3948 #define CAN_F1R1_FB29_Pos      (29U)
3949 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3950 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3951 #define CAN_F1R1_FB30_Pos      (30U)
3952 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3953 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3954 #define CAN_F1R1_FB31_Pos      (31U)
3955 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3956 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3957 
3958 /*******************  Bit definition for CAN_F2R1 register  *******************/
3959 #define CAN_F2R1_FB0_Pos       (0U)
3960 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3961 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3962 #define CAN_F2R1_FB1_Pos       (1U)
3963 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3964 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3965 #define CAN_F2R1_FB2_Pos       (2U)
3966 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3967 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3968 #define CAN_F2R1_FB3_Pos       (3U)
3969 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3970 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3971 #define CAN_F2R1_FB4_Pos       (4U)
3972 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3973 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3974 #define CAN_F2R1_FB5_Pos       (5U)
3975 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3976 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3977 #define CAN_F2R1_FB6_Pos       (6U)
3978 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3979 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3980 #define CAN_F2R1_FB7_Pos       (7U)
3981 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3982 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3983 #define CAN_F2R1_FB8_Pos       (8U)
3984 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3985 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3986 #define CAN_F2R1_FB9_Pos       (9U)
3987 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3988 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3989 #define CAN_F2R1_FB10_Pos      (10U)
3990 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3991 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3992 #define CAN_F2R1_FB11_Pos      (11U)
3993 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3994 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3995 #define CAN_F2R1_FB12_Pos      (12U)
3996 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3997 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3998 #define CAN_F2R1_FB13_Pos      (13U)
3999 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
4000 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
4001 #define CAN_F2R1_FB14_Pos      (14U)
4002 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
4003 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
4004 #define CAN_F2R1_FB15_Pos      (15U)
4005 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
4006 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
4007 #define CAN_F2R1_FB16_Pos      (16U)
4008 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
4009 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
4010 #define CAN_F2R1_FB17_Pos      (17U)
4011 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
4012 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
4013 #define CAN_F2R1_FB18_Pos      (18U)
4014 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
4015 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
4016 #define CAN_F2R1_FB19_Pos      (19U)
4017 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
4018 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
4019 #define CAN_F2R1_FB20_Pos      (20U)
4020 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
4021 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
4022 #define CAN_F2R1_FB21_Pos      (21U)
4023 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
4024 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
4025 #define CAN_F2R1_FB22_Pos      (22U)
4026 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
4027 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
4028 #define CAN_F2R1_FB23_Pos      (23U)
4029 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
4030 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
4031 #define CAN_F2R1_FB24_Pos      (24U)
4032 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
4033 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
4034 #define CAN_F2R1_FB25_Pos      (25U)
4035 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
4036 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
4037 #define CAN_F2R1_FB26_Pos      (26U)
4038 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
4039 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
4040 #define CAN_F2R1_FB27_Pos      (27U)
4041 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
4042 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
4043 #define CAN_F2R1_FB28_Pos      (28U)
4044 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
4045 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
4046 #define CAN_F2R1_FB29_Pos      (29U)
4047 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
4048 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
4049 #define CAN_F2R1_FB30_Pos      (30U)
4050 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
4051 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
4052 #define CAN_F2R1_FB31_Pos      (31U)
4053 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
4054 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
4055 
4056 /*******************  Bit definition for CAN_F3R1 register  *******************/
4057 #define CAN_F3R1_FB0_Pos       (0U)
4058 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
4059 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
4060 #define CAN_F3R1_FB1_Pos       (1U)
4061 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
4062 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
4063 #define CAN_F3R1_FB2_Pos       (2U)
4064 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
4065 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
4066 #define CAN_F3R1_FB3_Pos       (3U)
4067 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
4068 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
4069 #define CAN_F3R1_FB4_Pos       (4U)
4070 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
4071 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
4072 #define CAN_F3R1_FB5_Pos       (5U)
4073 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
4074 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
4075 #define CAN_F3R1_FB6_Pos       (6U)
4076 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
4077 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
4078 #define CAN_F3R1_FB7_Pos       (7U)
4079 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
4080 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
4081 #define CAN_F3R1_FB8_Pos       (8U)
4082 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
4083 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
4084 #define CAN_F3R1_FB9_Pos       (9U)
4085 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
4086 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
4087 #define CAN_F3R1_FB10_Pos      (10U)
4088 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
4089 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
4090 #define CAN_F3R1_FB11_Pos      (11U)
4091 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
4092 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
4093 #define CAN_F3R1_FB12_Pos      (12U)
4094 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
4095 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
4096 #define CAN_F3R1_FB13_Pos      (13U)
4097 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
4098 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
4099 #define CAN_F3R1_FB14_Pos      (14U)
4100 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
4101 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
4102 #define CAN_F3R1_FB15_Pos      (15U)
4103 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
4104 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
4105 #define CAN_F3R1_FB16_Pos      (16U)
4106 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
4107 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
4108 #define CAN_F3R1_FB17_Pos      (17U)
4109 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
4110 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
4111 #define CAN_F3R1_FB18_Pos      (18U)
4112 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
4113 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
4114 #define CAN_F3R1_FB19_Pos      (19U)
4115 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
4116 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
4117 #define CAN_F3R1_FB20_Pos      (20U)
4118 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
4119 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
4120 #define CAN_F3R1_FB21_Pos      (21U)
4121 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
4122 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
4123 #define CAN_F3R1_FB22_Pos      (22U)
4124 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
4125 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
4126 #define CAN_F3R1_FB23_Pos      (23U)
4127 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
4128 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
4129 #define CAN_F3R1_FB24_Pos      (24U)
4130 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
4131 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
4132 #define CAN_F3R1_FB25_Pos      (25U)
4133 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
4134 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
4135 #define CAN_F3R1_FB26_Pos      (26U)
4136 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
4137 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
4138 #define CAN_F3R1_FB27_Pos      (27U)
4139 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
4140 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
4141 #define CAN_F3R1_FB28_Pos      (28U)
4142 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
4143 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
4144 #define CAN_F3R1_FB29_Pos      (29U)
4145 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
4146 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
4147 #define CAN_F3R1_FB30_Pos      (30U)
4148 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
4149 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
4150 #define CAN_F3R1_FB31_Pos      (31U)
4151 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
4152 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
4153 
4154 /*******************  Bit definition for CAN_F4R1 register  *******************/
4155 #define CAN_F4R1_FB0_Pos       (0U)
4156 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
4157 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
4158 #define CAN_F4R1_FB1_Pos       (1U)
4159 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
4160 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
4161 #define CAN_F4R1_FB2_Pos       (2U)
4162 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
4163 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
4164 #define CAN_F4R1_FB3_Pos       (3U)
4165 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
4166 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
4167 #define CAN_F4R1_FB4_Pos       (4U)
4168 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
4169 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
4170 #define CAN_F4R1_FB5_Pos       (5U)
4171 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
4172 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
4173 #define CAN_F4R1_FB6_Pos       (6U)
4174 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
4175 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
4176 #define CAN_F4R1_FB7_Pos       (7U)
4177 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
4178 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
4179 #define CAN_F4R1_FB8_Pos       (8U)
4180 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
4181 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
4182 #define CAN_F4R1_FB9_Pos       (9U)
4183 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
4184 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
4185 #define CAN_F4R1_FB10_Pos      (10U)
4186 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
4187 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
4188 #define CAN_F4R1_FB11_Pos      (11U)
4189 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
4190 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
4191 #define CAN_F4R1_FB12_Pos      (12U)
4192 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
4193 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
4194 #define CAN_F4R1_FB13_Pos      (13U)
4195 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
4196 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
4197 #define CAN_F4R1_FB14_Pos      (14U)
4198 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
4199 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
4200 #define CAN_F4R1_FB15_Pos      (15U)
4201 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
4202 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
4203 #define CAN_F4R1_FB16_Pos      (16U)
4204 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
4205 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
4206 #define CAN_F4R1_FB17_Pos      (17U)
4207 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
4208 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
4209 #define CAN_F4R1_FB18_Pos      (18U)
4210 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
4211 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
4212 #define CAN_F4R1_FB19_Pos      (19U)
4213 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
4214 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
4215 #define CAN_F4R1_FB20_Pos      (20U)
4216 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
4217 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
4218 #define CAN_F4R1_FB21_Pos      (21U)
4219 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
4220 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
4221 #define CAN_F4R1_FB22_Pos      (22U)
4222 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
4223 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
4224 #define CAN_F4R1_FB23_Pos      (23U)
4225 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
4226 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
4227 #define CAN_F4R1_FB24_Pos      (24U)
4228 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
4229 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
4230 #define CAN_F4R1_FB25_Pos      (25U)
4231 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
4232 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
4233 #define CAN_F4R1_FB26_Pos      (26U)
4234 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
4235 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
4236 #define CAN_F4R1_FB27_Pos      (27U)
4237 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
4238 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
4239 #define CAN_F4R1_FB28_Pos      (28U)
4240 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
4241 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
4242 #define CAN_F4R1_FB29_Pos      (29U)
4243 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
4244 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
4245 #define CAN_F4R1_FB30_Pos      (30U)
4246 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
4247 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
4248 #define CAN_F4R1_FB31_Pos      (31U)
4249 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
4250 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
4251 
4252 /*******************  Bit definition for CAN_F5R1 register  *******************/
4253 #define CAN_F5R1_FB0_Pos       (0U)
4254 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
4255 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
4256 #define CAN_F5R1_FB1_Pos       (1U)
4257 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
4258 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
4259 #define CAN_F5R1_FB2_Pos       (2U)
4260 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
4261 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
4262 #define CAN_F5R1_FB3_Pos       (3U)
4263 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
4264 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
4265 #define CAN_F5R1_FB4_Pos       (4U)
4266 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
4267 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
4268 #define CAN_F5R1_FB5_Pos       (5U)
4269 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
4270 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
4271 #define CAN_F5R1_FB6_Pos       (6U)
4272 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
4273 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
4274 #define CAN_F5R1_FB7_Pos       (7U)
4275 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
4276 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
4277 #define CAN_F5R1_FB8_Pos       (8U)
4278 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
4279 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
4280 #define CAN_F5R1_FB9_Pos       (9U)
4281 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
4282 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
4283 #define CAN_F5R1_FB10_Pos      (10U)
4284 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
4285 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
4286 #define CAN_F5R1_FB11_Pos      (11U)
4287 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
4288 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
4289 #define CAN_F5R1_FB12_Pos      (12U)
4290 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
4291 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
4292 #define CAN_F5R1_FB13_Pos      (13U)
4293 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
4294 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
4295 #define CAN_F5R1_FB14_Pos      (14U)
4296 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
4297 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
4298 #define CAN_F5R1_FB15_Pos      (15U)
4299 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
4300 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
4301 #define CAN_F5R1_FB16_Pos      (16U)
4302 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
4303 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
4304 #define CAN_F5R1_FB17_Pos      (17U)
4305 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
4306 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
4307 #define CAN_F5R1_FB18_Pos      (18U)
4308 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
4309 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
4310 #define CAN_F5R1_FB19_Pos      (19U)
4311 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
4312 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
4313 #define CAN_F5R1_FB20_Pos      (20U)
4314 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
4315 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
4316 #define CAN_F5R1_FB21_Pos      (21U)
4317 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
4318 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
4319 #define CAN_F5R1_FB22_Pos      (22U)
4320 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
4321 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
4322 #define CAN_F5R1_FB23_Pos      (23U)
4323 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
4324 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
4325 #define CAN_F5R1_FB24_Pos      (24U)
4326 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
4327 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
4328 #define CAN_F5R1_FB25_Pos      (25U)
4329 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
4330 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
4331 #define CAN_F5R1_FB26_Pos      (26U)
4332 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
4333 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
4334 #define CAN_F5R1_FB27_Pos      (27U)
4335 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
4336 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
4337 #define CAN_F5R1_FB28_Pos      (28U)
4338 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
4339 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
4340 #define CAN_F5R1_FB29_Pos      (29U)
4341 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
4342 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
4343 #define CAN_F5R1_FB30_Pos      (30U)
4344 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
4345 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
4346 #define CAN_F5R1_FB31_Pos      (31U)
4347 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
4348 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
4349 
4350 /*******************  Bit definition for CAN_F6R1 register  *******************/
4351 #define CAN_F6R1_FB0_Pos       (0U)
4352 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
4353 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
4354 #define CAN_F6R1_FB1_Pos       (1U)
4355 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
4356 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
4357 #define CAN_F6R1_FB2_Pos       (2U)
4358 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
4359 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
4360 #define CAN_F6R1_FB3_Pos       (3U)
4361 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
4362 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
4363 #define CAN_F6R1_FB4_Pos       (4U)
4364 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
4365 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
4366 #define CAN_F6R1_FB5_Pos       (5U)
4367 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
4368 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
4369 #define CAN_F6R1_FB6_Pos       (6U)
4370 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
4371 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
4372 #define CAN_F6R1_FB7_Pos       (7U)
4373 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
4374 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
4375 #define CAN_F6R1_FB8_Pos       (8U)
4376 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
4377 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
4378 #define CAN_F6R1_FB9_Pos       (9U)
4379 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
4380 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
4381 #define CAN_F6R1_FB10_Pos      (10U)
4382 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
4383 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
4384 #define CAN_F6R1_FB11_Pos      (11U)
4385 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
4386 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
4387 #define CAN_F6R1_FB12_Pos      (12U)
4388 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
4389 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
4390 #define CAN_F6R1_FB13_Pos      (13U)
4391 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
4392 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
4393 #define CAN_F6R1_FB14_Pos      (14U)
4394 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
4395 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
4396 #define CAN_F6R1_FB15_Pos      (15U)
4397 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
4398 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
4399 #define CAN_F6R1_FB16_Pos      (16U)
4400 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
4401 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
4402 #define CAN_F6R1_FB17_Pos      (17U)
4403 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
4404 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
4405 #define CAN_F6R1_FB18_Pos      (18U)
4406 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
4407 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
4408 #define CAN_F6R1_FB19_Pos      (19U)
4409 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
4410 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
4411 #define CAN_F6R1_FB20_Pos      (20U)
4412 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
4413 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
4414 #define CAN_F6R1_FB21_Pos      (21U)
4415 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
4416 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
4417 #define CAN_F6R1_FB22_Pos      (22U)
4418 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
4419 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
4420 #define CAN_F6R1_FB23_Pos      (23U)
4421 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
4422 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
4423 #define CAN_F6R1_FB24_Pos      (24U)
4424 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
4425 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
4426 #define CAN_F6R1_FB25_Pos      (25U)
4427 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
4428 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
4429 #define CAN_F6R1_FB26_Pos      (26U)
4430 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
4431 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
4432 #define CAN_F6R1_FB27_Pos      (27U)
4433 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
4434 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
4435 #define CAN_F6R1_FB28_Pos      (28U)
4436 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
4437 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
4438 #define CAN_F6R1_FB29_Pos      (29U)
4439 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
4440 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
4441 #define CAN_F6R1_FB30_Pos      (30U)
4442 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
4443 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
4444 #define CAN_F6R1_FB31_Pos      (31U)
4445 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
4446 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
4447 
4448 /*******************  Bit definition for CAN_F7R1 register  *******************/
4449 #define CAN_F7R1_FB0_Pos       (0U)
4450 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
4451 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
4452 #define CAN_F7R1_FB1_Pos       (1U)
4453 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
4454 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
4455 #define CAN_F7R1_FB2_Pos       (2U)
4456 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
4457 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
4458 #define CAN_F7R1_FB3_Pos       (3U)
4459 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
4460 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
4461 #define CAN_F7R1_FB4_Pos       (4U)
4462 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
4463 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
4464 #define CAN_F7R1_FB5_Pos       (5U)
4465 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
4466 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
4467 #define CAN_F7R1_FB6_Pos       (6U)
4468 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
4469 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
4470 #define CAN_F7R1_FB7_Pos       (7U)
4471 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
4472 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
4473 #define CAN_F7R1_FB8_Pos       (8U)
4474 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
4475 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
4476 #define CAN_F7R1_FB9_Pos       (9U)
4477 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
4478 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
4479 #define CAN_F7R1_FB10_Pos      (10U)
4480 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
4481 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
4482 #define CAN_F7R1_FB11_Pos      (11U)
4483 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
4484 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
4485 #define CAN_F7R1_FB12_Pos      (12U)
4486 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
4487 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
4488 #define CAN_F7R1_FB13_Pos      (13U)
4489 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
4490 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
4491 #define CAN_F7R1_FB14_Pos      (14U)
4492 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
4493 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
4494 #define CAN_F7R1_FB15_Pos      (15U)
4495 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
4496 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
4497 #define CAN_F7R1_FB16_Pos      (16U)
4498 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
4499 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
4500 #define CAN_F7R1_FB17_Pos      (17U)
4501 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
4502 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
4503 #define CAN_F7R1_FB18_Pos      (18U)
4504 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
4505 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
4506 #define CAN_F7R1_FB19_Pos      (19U)
4507 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
4508 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
4509 #define CAN_F7R1_FB20_Pos      (20U)
4510 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
4511 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
4512 #define CAN_F7R1_FB21_Pos      (21U)
4513 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
4514 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
4515 #define CAN_F7R1_FB22_Pos      (22U)
4516 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
4517 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
4518 #define CAN_F7R1_FB23_Pos      (23U)
4519 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
4520 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
4521 #define CAN_F7R1_FB24_Pos      (24U)
4522 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
4523 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
4524 #define CAN_F7R1_FB25_Pos      (25U)
4525 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
4526 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
4527 #define CAN_F7R1_FB26_Pos      (26U)
4528 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
4529 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
4530 #define CAN_F7R1_FB27_Pos      (27U)
4531 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
4532 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
4533 #define CAN_F7R1_FB28_Pos      (28U)
4534 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
4535 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
4536 #define CAN_F7R1_FB29_Pos      (29U)
4537 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
4538 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
4539 #define CAN_F7R1_FB30_Pos      (30U)
4540 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
4541 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
4542 #define CAN_F7R1_FB31_Pos      (31U)
4543 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
4544 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
4545 
4546 /*******************  Bit definition for CAN_F8R1 register  *******************/
4547 #define CAN_F8R1_FB0_Pos       (0U)
4548 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
4549 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
4550 #define CAN_F8R1_FB1_Pos       (1U)
4551 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
4552 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
4553 #define CAN_F8R1_FB2_Pos       (2U)
4554 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
4555 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
4556 #define CAN_F8R1_FB3_Pos       (3U)
4557 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
4558 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
4559 #define CAN_F8R1_FB4_Pos       (4U)
4560 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
4561 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
4562 #define CAN_F8R1_FB5_Pos       (5U)
4563 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
4564 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
4565 #define CAN_F8R1_FB6_Pos       (6U)
4566 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
4567 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
4568 #define CAN_F8R1_FB7_Pos       (7U)
4569 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
4570 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
4571 #define CAN_F8R1_FB8_Pos       (8U)
4572 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
4573 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
4574 #define CAN_F8R1_FB9_Pos       (9U)
4575 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
4576 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
4577 #define CAN_F8R1_FB10_Pos      (10U)
4578 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
4579 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
4580 #define CAN_F8R1_FB11_Pos      (11U)
4581 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
4582 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
4583 #define CAN_F8R1_FB12_Pos      (12U)
4584 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
4585 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
4586 #define CAN_F8R1_FB13_Pos      (13U)
4587 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
4588 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
4589 #define CAN_F8R1_FB14_Pos      (14U)
4590 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
4591 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
4592 #define CAN_F8R1_FB15_Pos      (15U)
4593 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
4594 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
4595 #define CAN_F8R1_FB16_Pos      (16U)
4596 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
4597 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
4598 #define CAN_F8R1_FB17_Pos      (17U)
4599 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
4600 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
4601 #define CAN_F8R1_FB18_Pos      (18U)
4602 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
4603 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
4604 #define CAN_F8R1_FB19_Pos      (19U)
4605 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
4606 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
4607 #define CAN_F8R1_FB20_Pos      (20U)
4608 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
4609 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
4610 #define CAN_F8R1_FB21_Pos      (21U)
4611 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
4612 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
4613 #define CAN_F8R1_FB22_Pos      (22U)
4614 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
4615 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
4616 #define CAN_F8R1_FB23_Pos      (23U)
4617 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
4618 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
4619 #define CAN_F8R1_FB24_Pos      (24U)
4620 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
4621 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
4622 #define CAN_F8R1_FB25_Pos      (25U)
4623 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
4624 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
4625 #define CAN_F8R1_FB26_Pos      (26U)
4626 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
4627 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
4628 #define CAN_F8R1_FB27_Pos      (27U)
4629 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
4630 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
4631 #define CAN_F8R1_FB28_Pos      (28U)
4632 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
4633 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
4634 #define CAN_F8R1_FB29_Pos      (29U)
4635 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
4636 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
4637 #define CAN_F8R1_FB30_Pos      (30U)
4638 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
4639 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
4640 #define CAN_F8R1_FB31_Pos      (31U)
4641 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
4642 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
4643 
4644 /*******************  Bit definition for CAN_F9R1 register  *******************/
4645 #define CAN_F9R1_FB0_Pos       (0U)
4646 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
4647 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
4648 #define CAN_F9R1_FB1_Pos       (1U)
4649 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
4650 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
4651 #define CAN_F9R1_FB2_Pos       (2U)
4652 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
4653 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
4654 #define CAN_F9R1_FB3_Pos       (3U)
4655 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
4656 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
4657 #define CAN_F9R1_FB4_Pos       (4U)
4658 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
4659 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
4660 #define CAN_F9R1_FB5_Pos       (5U)
4661 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
4662 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
4663 #define CAN_F9R1_FB6_Pos       (6U)
4664 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
4665 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
4666 #define CAN_F9R1_FB7_Pos       (7U)
4667 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
4668 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
4669 #define CAN_F9R1_FB8_Pos       (8U)
4670 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
4671 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
4672 #define CAN_F9R1_FB9_Pos       (9U)
4673 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
4674 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
4675 #define CAN_F9R1_FB10_Pos      (10U)
4676 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
4677 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
4678 #define CAN_F9R1_FB11_Pos      (11U)
4679 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
4680 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
4681 #define CAN_F9R1_FB12_Pos      (12U)
4682 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
4683 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
4684 #define CAN_F9R1_FB13_Pos      (13U)
4685 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
4686 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
4687 #define CAN_F9R1_FB14_Pos      (14U)
4688 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
4689 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
4690 #define CAN_F9R1_FB15_Pos      (15U)
4691 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
4692 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
4693 #define CAN_F9R1_FB16_Pos      (16U)
4694 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
4695 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
4696 #define CAN_F9R1_FB17_Pos      (17U)
4697 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
4698 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
4699 #define CAN_F9R1_FB18_Pos      (18U)
4700 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
4701 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
4702 #define CAN_F9R1_FB19_Pos      (19U)
4703 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
4704 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
4705 #define CAN_F9R1_FB20_Pos      (20U)
4706 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
4707 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
4708 #define CAN_F9R1_FB21_Pos      (21U)
4709 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
4710 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
4711 #define CAN_F9R1_FB22_Pos      (22U)
4712 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
4713 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
4714 #define CAN_F9R1_FB23_Pos      (23U)
4715 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
4716 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
4717 #define CAN_F9R1_FB24_Pos      (24U)
4718 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
4719 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
4720 #define CAN_F9R1_FB25_Pos      (25U)
4721 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
4722 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
4723 #define CAN_F9R1_FB26_Pos      (26U)
4724 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
4725 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
4726 #define CAN_F9R1_FB27_Pos      (27U)
4727 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
4728 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
4729 #define CAN_F9R1_FB28_Pos      (28U)
4730 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
4731 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
4732 #define CAN_F9R1_FB29_Pos      (29U)
4733 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
4734 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
4735 #define CAN_F9R1_FB30_Pos      (30U)
4736 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
4737 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
4738 #define CAN_F9R1_FB31_Pos      (31U)
4739 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
4740 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
4741 
4742 /*******************  Bit definition for CAN_F10R1 register  ******************/
4743 #define CAN_F10R1_FB0_Pos      (0U)
4744 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
4745 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
4746 #define CAN_F10R1_FB1_Pos      (1U)
4747 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
4748 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
4749 #define CAN_F10R1_FB2_Pos      (2U)
4750 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
4751 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
4752 #define CAN_F10R1_FB3_Pos      (3U)
4753 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
4754 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
4755 #define CAN_F10R1_FB4_Pos      (4U)
4756 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
4757 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
4758 #define CAN_F10R1_FB5_Pos      (5U)
4759 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
4760 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
4761 #define CAN_F10R1_FB6_Pos      (6U)
4762 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
4763 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
4764 #define CAN_F10R1_FB7_Pos      (7U)
4765 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
4766 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
4767 #define CAN_F10R1_FB8_Pos      (8U)
4768 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
4769 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
4770 #define CAN_F10R1_FB9_Pos      (9U)
4771 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
4772 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
4773 #define CAN_F10R1_FB10_Pos     (10U)
4774 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
4775 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
4776 #define CAN_F10R1_FB11_Pos     (11U)
4777 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
4778 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
4779 #define CAN_F10R1_FB12_Pos     (12U)
4780 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
4781 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
4782 #define CAN_F10R1_FB13_Pos     (13U)
4783 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
4784 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
4785 #define CAN_F10R1_FB14_Pos     (14U)
4786 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
4787 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
4788 #define CAN_F10R1_FB15_Pos     (15U)
4789 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
4790 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
4791 #define CAN_F10R1_FB16_Pos     (16U)
4792 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
4793 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
4794 #define CAN_F10R1_FB17_Pos     (17U)
4795 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
4796 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
4797 #define CAN_F10R1_FB18_Pos     (18U)
4798 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
4799 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
4800 #define CAN_F10R1_FB19_Pos     (19U)
4801 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
4802 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
4803 #define CAN_F10R1_FB20_Pos     (20U)
4804 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
4805 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
4806 #define CAN_F10R1_FB21_Pos     (21U)
4807 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
4808 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
4809 #define CAN_F10R1_FB22_Pos     (22U)
4810 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
4811 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
4812 #define CAN_F10R1_FB23_Pos     (23U)
4813 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
4814 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
4815 #define CAN_F10R1_FB24_Pos     (24U)
4816 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
4817 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
4818 #define CAN_F10R1_FB25_Pos     (25U)
4819 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
4820 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
4821 #define CAN_F10R1_FB26_Pos     (26U)
4822 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
4823 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
4824 #define CAN_F10R1_FB27_Pos     (27U)
4825 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
4826 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
4827 #define CAN_F10R1_FB28_Pos     (28U)
4828 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
4829 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
4830 #define CAN_F10R1_FB29_Pos     (29U)
4831 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
4832 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
4833 #define CAN_F10R1_FB30_Pos     (30U)
4834 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
4835 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
4836 #define CAN_F10R1_FB31_Pos     (31U)
4837 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
4838 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
4839 
4840 /*******************  Bit definition for CAN_F11R1 register  ******************/
4841 #define CAN_F11R1_FB0_Pos      (0U)
4842 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
4843 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
4844 #define CAN_F11R1_FB1_Pos      (1U)
4845 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
4846 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
4847 #define CAN_F11R1_FB2_Pos      (2U)
4848 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
4849 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
4850 #define CAN_F11R1_FB3_Pos      (3U)
4851 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
4852 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
4853 #define CAN_F11R1_FB4_Pos      (4U)
4854 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
4855 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
4856 #define CAN_F11R1_FB5_Pos      (5U)
4857 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
4858 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
4859 #define CAN_F11R1_FB6_Pos      (6U)
4860 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
4861 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
4862 #define CAN_F11R1_FB7_Pos      (7U)
4863 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
4864 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
4865 #define CAN_F11R1_FB8_Pos      (8U)
4866 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
4867 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4868 #define CAN_F11R1_FB9_Pos      (9U)
4869 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
4870 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4871 #define CAN_F11R1_FB10_Pos     (10U)
4872 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
4873 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4874 #define CAN_F11R1_FB11_Pos     (11U)
4875 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
4876 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4877 #define CAN_F11R1_FB12_Pos     (12U)
4878 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
4879 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4880 #define CAN_F11R1_FB13_Pos     (13U)
4881 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
4882 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4883 #define CAN_F11R1_FB14_Pos     (14U)
4884 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
4885 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4886 #define CAN_F11R1_FB15_Pos     (15U)
4887 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
4888 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4889 #define CAN_F11R1_FB16_Pos     (16U)
4890 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
4891 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4892 #define CAN_F11R1_FB17_Pos     (17U)
4893 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
4894 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4895 #define CAN_F11R1_FB18_Pos     (18U)
4896 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
4897 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4898 #define CAN_F11R1_FB19_Pos     (19U)
4899 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
4900 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4901 #define CAN_F11R1_FB20_Pos     (20U)
4902 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
4903 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4904 #define CAN_F11R1_FB21_Pos     (21U)
4905 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
4906 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4907 #define CAN_F11R1_FB22_Pos     (22U)
4908 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
4909 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4910 #define CAN_F11R1_FB23_Pos     (23U)
4911 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
4912 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4913 #define CAN_F11R1_FB24_Pos     (24U)
4914 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
4915 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4916 #define CAN_F11R1_FB25_Pos     (25U)
4917 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
4918 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4919 #define CAN_F11R1_FB26_Pos     (26U)
4920 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
4921 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4922 #define CAN_F11R1_FB27_Pos     (27U)
4923 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
4924 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4925 #define CAN_F11R1_FB28_Pos     (28U)
4926 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
4927 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4928 #define CAN_F11R1_FB29_Pos     (29U)
4929 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
4930 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4931 #define CAN_F11R1_FB30_Pos     (30U)
4932 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
4933 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4934 #define CAN_F11R1_FB31_Pos     (31U)
4935 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4936 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4937 
4938 /*******************  Bit definition for CAN_F12R1 register  ******************/
4939 #define CAN_F12R1_FB0_Pos      (0U)
4940 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4941 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4942 #define CAN_F12R1_FB1_Pos      (1U)
4943 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4944 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4945 #define CAN_F12R1_FB2_Pos      (2U)
4946 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4947 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4948 #define CAN_F12R1_FB3_Pos      (3U)
4949 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4950 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4951 #define CAN_F12R1_FB4_Pos      (4U)
4952 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4953 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4954 #define CAN_F12R1_FB5_Pos      (5U)
4955 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4956 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4957 #define CAN_F12R1_FB6_Pos      (6U)
4958 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4959 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4960 #define CAN_F12R1_FB7_Pos      (7U)
4961 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4962 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4963 #define CAN_F12R1_FB8_Pos      (8U)
4964 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4965 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4966 #define CAN_F12R1_FB9_Pos      (9U)
4967 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4968 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4969 #define CAN_F12R1_FB10_Pos     (10U)
4970 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4971 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4972 #define CAN_F12R1_FB11_Pos     (11U)
4973 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4974 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4975 #define CAN_F12R1_FB12_Pos     (12U)
4976 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4977 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4978 #define CAN_F12R1_FB13_Pos     (13U)
4979 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4980 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4981 #define CAN_F12R1_FB14_Pos     (14U)
4982 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4983 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4984 #define CAN_F12R1_FB15_Pos     (15U)
4985 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4986 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4987 #define CAN_F12R1_FB16_Pos     (16U)
4988 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4989 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4990 #define CAN_F12R1_FB17_Pos     (17U)
4991 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4992 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4993 #define CAN_F12R1_FB18_Pos     (18U)
4994 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4995 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4996 #define CAN_F12R1_FB19_Pos     (19U)
4997 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4998 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4999 #define CAN_F12R1_FB20_Pos     (20U)
5000 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
5001 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
5002 #define CAN_F12R1_FB21_Pos     (21U)
5003 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
5004 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
5005 #define CAN_F12R1_FB22_Pos     (22U)
5006 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
5007 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
5008 #define CAN_F12R1_FB23_Pos     (23U)
5009 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
5010 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
5011 #define CAN_F12R1_FB24_Pos     (24U)
5012 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
5013 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
5014 #define CAN_F12R1_FB25_Pos     (25U)
5015 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
5016 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
5017 #define CAN_F12R1_FB26_Pos     (26U)
5018 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
5019 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
5020 #define CAN_F12R1_FB27_Pos     (27U)
5021 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
5022 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
5023 #define CAN_F12R1_FB28_Pos     (28U)
5024 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
5025 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
5026 #define CAN_F12R1_FB29_Pos     (29U)
5027 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
5028 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
5029 #define CAN_F12R1_FB30_Pos     (30U)
5030 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
5031 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
5032 #define CAN_F12R1_FB31_Pos     (31U)
5033 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
5034 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
5035 
5036 /*******************  Bit definition for CAN_F13R1 register  ******************/
5037 #define CAN_F13R1_FB0_Pos      (0U)
5038 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
5039 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
5040 #define CAN_F13R1_FB1_Pos      (1U)
5041 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
5042 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
5043 #define CAN_F13R1_FB2_Pos      (2U)
5044 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
5045 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
5046 #define CAN_F13R1_FB3_Pos      (3U)
5047 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
5048 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
5049 #define CAN_F13R1_FB4_Pos      (4U)
5050 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
5051 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
5052 #define CAN_F13R1_FB5_Pos      (5U)
5053 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
5054 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
5055 #define CAN_F13R1_FB6_Pos      (6U)
5056 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
5057 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
5058 #define CAN_F13R1_FB7_Pos      (7U)
5059 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
5060 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
5061 #define CAN_F13R1_FB8_Pos      (8U)
5062 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
5063 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
5064 #define CAN_F13R1_FB9_Pos      (9U)
5065 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
5066 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
5067 #define CAN_F13R1_FB10_Pos     (10U)
5068 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
5069 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
5070 #define CAN_F13R1_FB11_Pos     (11U)
5071 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
5072 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
5073 #define CAN_F13R1_FB12_Pos     (12U)
5074 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
5075 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
5076 #define CAN_F13R1_FB13_Pos     (13U)
5077 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
5078 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
5079 #define CAN_F13R1_FB14_Pos     (14U)
5080 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
5081 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
5082 #define CAN_F13R1_FB15_Pos     (15U)
5083 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
5084 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
5085 #define CAN_F13R1_FB16_Pos     (16U)
5086 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
5087 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
5088 #define CAN_F13R1_FB17_Pos     (17U)
5089 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
5090 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
5091 #define CAN_F13R1_FB18_Pos     (18U)
5092 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
5093 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
5094 #define CAN_F13R1_FB19_Pos     (19U)
5095 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
5096 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
5097 #define CAN_F13R1_FB20_Pos     (20U)
5098 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
5099 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
5100 #define CAN_F13R1_FB21_Pos     (21U)
5101 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
5102 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
5103 #define CAN_F13R1_FB22_Pos     (22U)
5104 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
5105 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
5106 #define CAN_F13R1_FB23_Pos     (23U)
5107 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
5108 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
5109 #define CAN_F13R1_FB24_Pos     (24U)
5110 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
5111 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
5112 #define CAN_F13R1_FB25_Pos     (25U)
5113 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
5114 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
5115 #define CAN_F13R1_FB26_Pos     (26U)
5116 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
5117 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
5118 #define CAN_F13R1_FB27_Pos     (27U)
5119 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
5120 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
5121 #define CAN_F13R1_FB28_Pos     (28U)
5122 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
5123 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
5124 #define CAN_F13R1_FB29_Pos     (29U)
5125 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
5126 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
5127 #define CAN_F13R1_FB30_Pos     (30U)
5128 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
5129 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
5130 #define CAN_F13R1_FB31_Pos     (31U)
5131 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
5132 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
5133 
5134 /*******************  Bit definition for CAN_F0R2 register  *******************/
5135 #define CAN_F0R2_FB0_Pos       (0U)
5136 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
5137 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
5138 #define CAN_F0R2_FB1_Pos       (1U)
5139 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
5140 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
5141 #define CAN_F0R2_FB2_Pos       (2U)
5142 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
5143 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
5144 #define CAN_F0R2_FB3_Pos       (3U)
5145 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
5146 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
5147 #define CAN_F0R2_FB4_Pos       (4U)
5148 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
5149 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
5150 #define CAN_F0R2_FB5_Pos       (5U)
5151 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
5152 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
5153 #define CAN_F0R2_FB6_Pos       (6U)
5154 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
5155 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
5156 #define CAN_F0R2_FB7_Pos       (7U)
5157 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
5158 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
5159 #define CAN_F0R2_FB8_Pos       (8U)
5160 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
5161 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
5162 #define CAN_F0R2_FB9_Pos       (9U)
5163 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
5164 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
5165 #define CAN_F0R2_FB10_Pos      (10U)
5166 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
5167 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
5168 #define CAN_F0R2_FB11_Pos      (11U)
5169 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
5170 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
5171 #define CAN_F0R2_FB12_Pos      (12U)
5172 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
5173 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
5174 #define CAN_F0R2_FB13_Pos      (13U)
5175 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
5176 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
5177 #define CAN_F0R2_FB14_Pos      (14U)
5178 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
5179 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
5180 #define CAN_F0R2_FB15_Pos      (15U)
5181 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
5182 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
5183 #define CAN_F0R2_FB16_Pos      (16U)
5184 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
5185 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
5186 #define CAN_F0R2_FB17_Pos      (17U)
5187 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
5188 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
5189 #define CAN_F0R2_FB18_Pos      (18U)
5190 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
5191 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
5192 #define CAN_F0R2_FB19_Pos      (19U)
5193 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
5194 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
5195 #define CAN_F0R2_FB20_Pos      (20U)
5196 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
5197 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
5198 #define CAN_F0R2_FB21_Pos      (21U)
5199 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
5200 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
5201 #define CAN_F0R2_FB22_Pos      (22U)
5202 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
5203 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
5204 #define CAN_F0R2_FB23_Pos      (23U)
5205 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
5206 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
5207 #define CAN_F0R2_FB24_Pos      (24U)
5208 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
5209 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
5210 #define CAN_F0R2_FB25_Pos      (25U)
5211 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
5212 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
5213 #define CAN_F0R2_FB26_Pos      (26U)
5214 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
5215 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
5216 #define CAN_F0R2_FB27_Pos      (27U)
5217 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
5218 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
5219 #define CAN_F0R2_FB28_Pos      (28U)
5220 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
5221 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
5222 #define CAN_F0R2_FB29_Pos      (29U)
5223 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
5224 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
5225 #define CAN_F0R2_FB30_Pos      (30U)
5226 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
5227 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
5228 #define CAN_F0R2_FB31_Pos      (31U)
5229 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
5230 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
5231 
5232 /*******************  Bit definition for CAN_F1R2 register  *******************/
5233 #define CAN_F1R2_FB0_Pos       (0U)
5234 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
5235 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
5236 #define CAN_F1R2_FB1_Pos       (1U)
5237 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
5238 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
5239 #define CAN_F1R2_FB2_Pos       (2U)
5240 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
5241 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
5242 #define CAN_F1R2_FB3_Pos       (3U)
5243 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
5244 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
5245 #define CAN_F1R2_FB4_Pos       (4U)
5246 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
5247 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
5248 #define CAN_F1R2_FB5_Pos       (5U)
5249 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
5250 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
5251 #define CAN_F1R2_FB6_Pos       (6U)
5252 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
5253 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
5254 #define CAN_F1R2_FB7_Pos       (7U)
5255 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
5256 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
5257 #define CAN_F1R2_FB8_Pos       (8U)
5258 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
5259 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
5260 #define CAN_F1R2_FB9_Pos       (9U)
5261 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
5262 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
5263 #define CAN_F1R2_FB10_Pos      (10U)
5264 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
5265 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
5266 #define CAN_F1R2_FB11_Pos      (11U)
5267 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
5268 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
5269 #define CAN_F1R2_FB12_Pos      (12U)
5270 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
5271 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
5272 #define CAN_F1R2_FB13_Pos      (13U)
5273 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
5274 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
5275 #define CAN_F1R2_FB14_Pos      (14U)
5276 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
5277 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
5278 #define CAN_F1R2_FB15_Pos      (15U)
5279 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
5280 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
5281 #define CAN_F1R2_FB16_Pos      (16U)
5282 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
5283 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
5284 #define CAN_F1R2_FB17_Pos      (17U)
5285 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
5286 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
5287 #define CAN_F1R2_FB18_Pos      (18U)
5288 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
5289 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
5290 #define CAN_F1R2_FB19_Pos      (19U)
5291 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
5292 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
5293 #define CAN_F1R2_FB20_Pos      (20U)
5294 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
5295 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
5296 #define CAN_F1R2_FB21_Pos      (21U)
5297 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
5298 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
5299 #define CAN_F1R2_FB22_Pos      (22U)
5300 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
5301 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
5302 #define CAN_F1R2_FB23_Pos      (23U)
5303 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
5304 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
5305 #define CAN_F1R2_FB24_Pos      (24U)
5306 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
5307 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
5308 #define CAN_F1R2_FB25_Pos      (25U)
5309 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
5310 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
5311 #define CAN_F1R2_FB26_Pos      (26U)
5312 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
5313 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
5314 #define CAN_F1R2_FB27_Pos      (27U)
5315 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
5316 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
5317 #define CAN_F1R2_FB28_Pos      (28U)
5318 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
5319 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
5320 #define CAN_F1R2_FB29_Pos      (29U)
5321 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
5322 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
5323 #define CAN_F1R2_FB30_Pos      (30U)
5324 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
5325 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
5326 #define CAN_F1R2_FB31_Pos      (31U)
5327 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
5328 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
5329 
5330 /*******************  Bit definition for CAN_F2R2 register  *******************/
5331 #define CAN_F2R2_FB0_Pos       (0U)
5332 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
5333 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
5334 #define CAN_F2R2_FB1_Pos       (1U)
5335 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
5336 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
5337 #define CAN_F2R2_FB2_Pos       (2U)
5338 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
5339 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
5340 #define CAN_F2R2_FB3_Pos       (3U)
5341 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
5342 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
5343 #define CAN_F2R2_FB4_Pos       (4U)
5344 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
5345 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
5346 #define CAN_F2R2_FB5_Pos       (5U)
5347 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
5348 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
5349 #define CAN_F2R2_FB6_Pos       (6U)
5350 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
5351 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
5352 #define CAN_F2R2_FB7_Pos       (7U)
5353 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
5354 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
5355 #define CAN_F2R2_FB8_Pos       (8U)
5356 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
5357 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
5358 #define CAN_F2R2_FB9_Pos       (9U)
5359 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
5360 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
5361 #define CAN_F2R2_FB10_Pos      (10U)
5362 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
5363 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
5364 #define CAN_F2R2_FB11_Pos      (11U)
5365 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
5366 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
5367 #define CAN_F2R2_FB12_Pos      (12U)
5368 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
5369 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
5370 #define CAN_F2R2_FB13_Pos      (13U)
5371 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
5372 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
5373 #define CAN_F2R2_FB14_Pos      (14U)
5374 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
5375 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
5376 #define CAN_F2R2_FB15_Pos      (15U)
5377 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
5378 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
5379 #define CAN_F2R2_FB16_Pos      (16U)
5380 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
5381 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
5382 #define CAN_F2R2_FB17_Pos      (17U)
5383 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
5384 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
5385 #define CAN_F2R2_FB18_Pos      (18U)
5386 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
5387 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
5388 #define CAN_F2R2_FB19_Pos      (19U)
5389 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
5390 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
5391 #define CAN_F2R2_FB20_Pos      (20U)
5392 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
5393 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
5394 #define CAN_F2R2_FB21_Pos      (21U)
5395 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
5396 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
5397 #define CAN_F2R2_FB22_Pos      (22U)
5398 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
5399 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
5400 #define CAN_F2R2_FB23_Pos      (23U)
5401 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
5402 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
5403 #define CAN_F2R2_FB24_Pos      (24U)
5404 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
5405 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
5406 #define CAN_F2R2_FB25_Pos      (25U)
5407 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
5408 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
5409 #define CAN_F2R2_FB26_Pos      (26U)
5410 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
5411 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
5412 #define CAN_F2R2_FB27_Pos      (27U)
5413 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
5414 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
5415 #define CAN_F2R2_FB28_Pos      (28U)
5416 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
5417 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
5418 #define CAN_F2R2_FB29_Pos      (29U)
5419 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
5420 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
5421 #define CAN_F2R2_FB30_Pos      (30U)
5422 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
5423 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
5424 #define CAN_F2R2_FB31_Pos      (31U)
5425 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
5426 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
5427 
5428 /*******************  Bit definition for CAN_F3R2 register  *******************/
5429 #define CAN_F3R2_FB0_Pos       (0U)
5430 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
5431 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
5432 #define CAN_F3R2_FB1_Pos       (1U)
5433 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
5434 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
5435 #define CAN_F3R2_FB2_Pos       (2U)
5436 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
5437 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
5438 #define CAN_F3R2_FB3_Pos       (3U)
5439 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
5440 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
5441 #define CAN_F3R2_FB4_Pos       (4U)
5442 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
5443 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
5444 #define CAN_F3R2_FB5_Pos       (5U)
5445 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
5446 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
5447 #define CAN_F3R2_FB6_Pos       (6U)
5448 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
5449 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
5450 #define CAN_F3R2_FB7_Pos       (7U)
5451 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
5452 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
5453 #define CAN_F3R2_FB8_Pos       (8U)
5454 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
5455 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
5456 #define CAN_F3R2_FB9_Pos       (9U)
5457 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
5458 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
5459 #define CAN_F3R2_FB10_Pos      (10U)
5460 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
5461 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
5462 #define CAN_F3R2_FB11_Pos      (11U)
5463 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
5464 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
5465 #define CAN_F3R2_FB12_Pos      (12U)
5466 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
5467 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
5468 #define CAN_F3R2_FB13_Pos      (13U)
5469 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
5470 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
5471 #define CAN_F3R2_FB14_Pos      (14U)
5472 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
5473 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
5474 #define CAN_F3R2_FB15_Pos      (15U)
5475 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
5476 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
5477 #define CAN_F3R2_FB16_Pos      (16U)
5478 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
5479 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
5480 #define CAN_F3R2_FB17_Pos      (17U)
5481 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
5482 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
5483 #define CAN_F3R2_FB18_Pos      (18U)
5484 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
5485 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
5486 #define CAN_F3R2_FB19_Pos      (19U)
5487 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
5488 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
5489 #define CAN_F3R2_FB20_Pos      (20U)
5490 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
5491 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
5492 #define CAN_F3R2_FB21_Pos      (21U)
5493 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
5494 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
5495 #define CAN_F3R2_FB22_Pos      (22U)
5496 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
5497 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
5498 #define CAN_F3R2_FB23_Pos      (23U)
5499 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
5500 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
5501 #define CAN_F3R2_FB24_Pos      (24U)
5502 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
5503 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
5504 #define CAN_F3R2_FB25_Pos      (25U)
5505 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
5506 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
5507 #define CAN_F3R2_FB26_Pos      (26U)
5508 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
5509 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
5510 #define CAN_F3R2_FB27_Pos      (27U)
5511 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
5512 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
5513 #define CAN_F3R2_FB28_Pos      (28U)
5514 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
5515 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
5516 #define CAN_F3R2_FB29_Pos      (29U)
5517 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
5518 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
5519 #define CAN_F3R2_FB30_Pos      (30U)
5520 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
5521 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
5522 #define CAN_F3R2_FB31_Pos      (31U)
5523 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
5524 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
5525 
5526 /*******************  Bit definition for CAN_F4R2 register  *******************/
5527 #define CAN_F4R2_FB0_Pos       (0U)
5528 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
5529 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
5530 #define CAN_F4R2_FB1_Pos       (1U)
5531 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
5532 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
5533 #define CAN_F4R2_FB2_Pos       (2U)
5534 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
5535 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
5536 #define CAN_F4R2_FB3_Pos       (3U)
5537 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
5538 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
5539 #define CAN_F4R2_FB4_Pos       (4U)
5540 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
5541 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
5542 #define CAN_F4R2_FB5_Pos       (5U)
5543 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
5544 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
5545 #define CAN_F4R2_FB6_Pos       (6U)
5546 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
5547 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
5548 #define CAN_F4R2_FB7_Pos       (7U)
5549 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
5550 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
5551 #define CAN_F4R2_FB8_Pos       (8U)
5552 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
5553 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
5554 #define CAN_F4R2_FB9_Pos       (9U)
5555 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
5556 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
5557 #define CAN_F4R2_FB10_Pos      (10U)
5558 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
5559 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
5560 #define CAN_F4R2_FB11_Pos      (11U)
5561 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
5562 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
5563 #define CAN_F4R2_FB12_Pos      (12U)
5564 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
5565 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
5566 #define CAN_F4R2_FB13_Pos      (13U)
5567 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
5568 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
5569 #define CAN_F4R2_FB14_Pos      (14U)
5570 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
5571 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
5572 #define CAN_F4R2_FB15_Pos      (15U)
5573 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
5574 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
5575 #define CAN_F4R2_FB16_Pos      (16U)
5576 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
5577 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
5578 #define CAN_F4R2_FB17_Pos      (17U)
5579 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
5580 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
5581 #define CAN_F4R2_FB18_Pos      (18U)
5582 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
5583 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
5584 #define CAN_F4R2_FB19_Pos      (19U)
5585 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
5586 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
5587 #define CAN_F4R2_FB20_Pos      (20U)
5588 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
5589 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
5590 #define CAN_F4R2_FB21_Pos      (21U)
5591 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
5592 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
5593 #define CAN_F4R2_FB22_Pos      (22U)
5594 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
5595 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
5596 #define CAN_F4R2_FB23_Pos      (23U)
5597 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
5598 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
5599 #define CAN_F4R2_FB24_Pos      (24U)
5600 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
5601 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
5602 #define CAN_F4R2_FB25_Pos      (25U)
5603 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
5604 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
5605 #define CAN_F4R2_FB26_Pos      (26U)
5606 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
5607 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
5608 #define CAN_F4R2_FB27_Pos      (27U)
5609 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
5610 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
5611 #define CAN_F4R2_FB28_Pos      (28U)
5612 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
5613 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
5614 #define CAN_F4R2_FB29_Pos      (29U)
5615 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
5616 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
5617 #define CAN_F4R2_FB30_Pos      (30U)
5618 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
5619 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
5620 #define CAN_F4R2_FB31_Pos      (31U)
5621 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
5622 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
5623 
5624 /*******************  Bit definition for CAN_F5R2 register  *******************/
5625 #define CAN_F5R2_FB0_Pos       (0U)
5626 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
5627 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
5628 #define CAN_F5R2_FB1_Pos       (1U)
5629 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
5630 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
5631 #define CAN_F5R2_FB2_Pos       (2U)
5632 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
5633 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
5634 #define CAN_F5R2_FB3_Pos       (3U)
5635 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
5636 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
5637 #define CAN_F5R2_FB4_Pos       (4U)
5638 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
5639 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
5640 #define CAN_F5R2_FB5_Pos       (5U)
5641 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
5642 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
5643 #define CAN_F5R2_FB6_Pos       (6U)
5644 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
5645 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
5646 #define CAN_F5R2_FB7_Pos       (7U)
5647 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
5648 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
5649 #define CAN_F5R2_FB8_Pos       (8U)
5650 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
5651 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
5652 #define CAN_F5R2_FB9_Pos       (9U)
5653 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
5654 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
5655 #define CAN_F5R2_FB10_Pos      (10U)
5656 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
5657 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
5658 #define CAN_F5R2_FB11_Pos      (11U)
5659 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
5660 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
5661 #define CAN_F5R2_FB12_Pos      (12U)
5662 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
5663 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
5664 #define CAN_F5R2_FB13_Pos      (13U)
5665 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
5666 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
5667 #define CAN_F5R2_FB14_Pos      (14U)
5668 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
5669 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
5670 #define CAN_F5R2_FB15_Pos      (15U)
5671 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
5672 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
5673 #define CAN_F5R2_FB16_Pos      (16U)
5674 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
5675 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
5676 #define CAN_F5R2_FB17_Pos      (17U)
5677 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
5678 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
5679 #define CAN_F5R2_FB18_Pos      (18U)
5680 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
5681 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
5682 #define CAN_F5R2_FB19_Pos      (19U)
5683 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
5684 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
5685 #define CAN_F5R2_FB20_Pos      (20U)
5686 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
5687 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
5688 #define CAN_F5R2_FB21_Pos      (21U)
5689 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
5690 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
5691 #define CAN_F5R2_FB22_Pos      (22U)
5692 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
5693 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
5694 #define CAN_F5R2_FB23_Pos      (23U)
5695 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
5696 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
5697 #define CAN_F5R2_FB24_Pos      (24U)
5698 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
5699 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
5700 #define CAN_F5R2_FB25_Pos      (25U)
5701 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
5702 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
5703 #define CAN_F5R2_FB26_Pos      (26U)
5704 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
5705 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
5706 #define CAN_F5R2_FB27_Pos      (27U)
5707 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
5708 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
5709 #define CAN_F5R2_FB28_Pos      (28U)
5710 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
5711 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
5712 #define CAN_F5R2_FB29_Pos      (29U)
5713 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
5714 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
5715 #define CAN_F5R2_FB30_Pos      (30U)
5716 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
5717 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
5718 #define CAN_F5R2_FB31_Pos      (31U)
5719 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
5720 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
5721 
5722 /*******************  Bit definition for CAN_F6R2 register  *******************/
5723 #define CAN_F6R2_FB0_Pos       (0U)
5724 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
5725 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
5726 #define CAN_F6R2_FB1_Pos       (1U)
5727 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
5728 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
5729 #define CAN_F6R2_FB2_Pos       (2U)
5730 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
5731 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
5732 #define CAN_F6R2_FB3_Pos       (3U)
5733 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
5734 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
5735 #define CAN_F6R2_FB4_Pos       (4U)
5736 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
5737 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
5738 #define CAN_F6R2_FB5_Pos       (5U)
5739 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
5740 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
5741 #define CAN_F6R2_FB6_Pos       (6U)
5742 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
5743 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
5744 #define CAN_F6R2_FB7_Pos       (7U)
5745 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
5746 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
5747 #define CAN_F6R2_FB8_Pos       (8U)
5748 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
5749 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
5750 #define CAN_F6R2_FB9_Pos       (9U)
5751 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
5752 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
5753 #define CAN_F6R2_FB10_Pos      (10U)
5754 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
5755 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
5756 #define CAN_F6R2_FB11_Pos      (11U)
5757 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
5758 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
5759 #define CAN_F6R2_FB12_Pos      (12U)
5760 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
5761 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
5762 #define CAN_F6R2_FB13_Pos      (13U)
5763 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
5764 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
5765 #define CAN_F6R2_FB14_Pos      (14U)
5766 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
5767 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
5768 #define CAN_F6R2_FB15_Pos      (15U)
5769 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
5770 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
5771 #define CAN_F6R2_FB16_Pos      (16U)
5772 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
5773 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
5774 #define CAN_F6R2_FB17_Pos      (17U)
5775 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
5776 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
5777 #define CAN_F6R2_FB18_Pos      (18U)
5778 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
5779 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
5780 #define CAN_F6R2_FB19_Pos      (19U)
5781 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
5782 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
5783 #define CAN_F6R2_FB20_Pos      (20U)
5784 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
5785 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
5786 #define CAN_F6R2_FB21_Pos      (21U)
5787 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
5788 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
5789 #define CAN_F6R2_FB22_Pos      (22U)
5790 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
5791 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
5792 #define CAN_F6R2_FB23_Pos      (23U)
5793 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
5794 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
5795 #define CAN_F6R2_FB24_Pos      (24U)
5796 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
5797 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
5798 #define CAN_F6R2_FB25_Pos      (25U)
5799 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
5800 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
5801 #define CAN_F6R2_FB26_Pos      (26U)
5802 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
5803 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
5804 #define CAN_F6R2_FB27_Pos      (27U)
5805 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
5806 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
5807 #define CAN_F6R2_FB28_Pos      (28U)
5808 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
5809 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
5810 #define CAN_F6R2_FB29_Pos      (29U)
5811 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
5812 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
5813 #define CAN_F6R2_FB30_Pos      (30U)
5814 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
5815 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
5816 #define CAN_F6R2_FB31_Pos      (31U)
5817 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
5818 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
5819 
5820 /*******************  Bit definition for CAN_F7R2 register  *******************/
5821 #define CAN_F7R2_FB0_Pos       (0U)
5822 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
5823 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
5824 #define CAN_F7R2_FB1_Pos       (1U)
5825 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
5826 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
5827 #define CAN_F7R2_FB2_Pos       (2U)
5828 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
5829 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
5830 #define CAN_F7R2_FB3_Pos       (3U)
5831 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
5832 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
5833 #define CAN_F7R2_FB4_Pos       (4U)
5834 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
5835 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
5836 #define CAN_F7R2_FB5_Pos       (5U)
5837 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
5838 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
5839 #define CAN_F7R2_FB6_Pos       (6U)
5840 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
5841 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
5842 #define CAN_F7R2_FB7_Pos       (7U)
5843 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
5844 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
5845 #define CAN_F7R2_FB8_Pos       (8U)
5846 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
5847 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
5848 #define CAN_F7R2_FB9_Pos       (9U)
5849 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
5850 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
5851 #define CAN_F7R2_FB10_Pos      (10U)
5852 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
5853 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
5854 #define CAN_F7R2_FB11_Pos      (11U)
5855 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
5856 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
5857 #define CAN_F7R2_FB12_Pos      (12U)
5858 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
5859 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
5860 #define CAN_F7R2_FB13_Pos      (13U)
5861 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
5862 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
5863 #define CAN_F7R2_FB14_Pos      (14U)
5864 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
5865 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5866 #define CAN_F7R2_FB15_Pos      (15U)
5867 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
5868 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5869 #define CAN_F7R2_FB16_Pos      (16U)
5870 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
5871 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5872 #define CAN_F7R2_FB17_Pos      (17U)
5873 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
5874 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5875 #define CAN_F7R2_FB18_Pos      (18U)
5876 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
5877 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5878 #define CAN_F7R2_FB19_Pos      (19U)
5879 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
5880 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5881 #define CAN_F7R2_FB20_Pos      (20U)
5882 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
5883 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5884 #define CAN_F7R2_FB21_Pos      (21U)
5885 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
5886 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5887 #define CAN_F7R2_FB22_Pos      (22U)
5888 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
5889 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5890 #define CAN_F7R2_FB23_Pos      (23U)
5891 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
5892 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5893 #define CAN_F7R2_FB24_Pos      (24U)
5894 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
5895 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5896 #define CAN_F7R2_FB25_Pos      (25U)
5897 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
5898 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5899 #define CAN_F7R2_FB26_Pos      (26U)
5900 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
5901 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5902 #define CAN_F7R2_FB27_Pos      (27U)
5903 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
5904 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5905 #define CAN_F7R2_FB28_Pos      (28U)
5906 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
5907 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5908 #define CAN_F7R2_FB29_Pos      (29U)
5909 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
5910 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5911 #define CAN_F7R2_FB30_Pos      (30U)
5912 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
5913 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5914 #define CAN_F7R2_FB31_Pos      (31U)
5915 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
5916 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5917 
5918 /*******************  Bit definition for CAN_F8R2 register  *******************/
5919 #define CAN_F8R2_FB0_Pos       (0U)
5920 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
5921 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5922 #define CAN_F8R2_FB1_Pos       (1U)
5923 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
5924 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5925 #define CAN_F8R2_FB2_Pos       (2U)
5926 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
5927 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5928 #define CAN_F8R2_FB3_Pos       (3U)
5929 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
5930 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5931 #define CAN_F8R2_FB4_Pos       (4U)
5932 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
5933 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5934 #define CAN_F8R2_FB5_Pos       (5U)
5935 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5936 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5937 #define CAN_F8R2_FB6_Pos       (6U)
5938 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5939 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5940 #define CAN_F8R2_FB7_Pos       (7U)
5941 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5942 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5943 #define CAN_F8R2_FB8_Pos       (8U)
5944 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5945 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5946 #define CAN_F8R2_FB9_Pos       (9U)
5947 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5948 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5949 #define CAN_F8R2_FB10_Pos      (10U)
5950 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5951 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5952 #define CAN_F8R2_FB11_Pos      (11U)
5953 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5954 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5955 #define CAN_F8R2_FB12_Pos      (12U)
5956 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5957 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5958 #define CAN_F8R2_FB13_Pos      (13U)
5959 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5960 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5961 #define CAN_F8R2_FB14_Pos      (14U)
5962 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5963 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5964 #define CAN_F8R2_FB15_Pos      (15U)
5965 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5966 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5967 #define CAN_F8R2_FB16_Pos      (16U)
5968 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5969 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5970 #define CAN_F8R2_FB17_Pos      (17U)
5971 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5972 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5973 #define CAN_F8R2_FB18_Pos      (18U)
5974 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5975 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5976 #define CAN_F8R2_FB19_Pos      (19U)
5977 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5978 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5979 #define CAN_F8R2_FB20_Pos      (20U)
5980 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5981 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5982 #define CAN_F8R2_FB21_Pos      (21U)
5983 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5984 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5985 #define CAN_F8R2_FB22_Pos      (22U)
5986 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5987 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5988 #define CAN_F8R2_FB23_Pos      (23U)
5989 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5990 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5991 #define CAN_F8R2_FB24_Pos      (24U)
5992 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5993 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5994 #define CAN_F8R2_FB25_Pos      (25U)
5995 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5996 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5997 #define CAN_F8R2_FB26_Pos      (26U)
5998 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5999 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
6000 #define CAN_F8R2_FB27_Pos      (27U)
6001 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
6002 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
6003 #define CAN_F8R2_FB28_Pos      (28U)
6004 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
6005 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
6006 #define CAN_F8R2_FB29_Pos      (29U)
6007 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
6008 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
6009 #define CAN_F8R2_FB30_Pos      (30U)
6010 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
6011 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
6012 #define CAN_F8R2_FB31_Pos      (31U)
6013 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
6014 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
6015 
6016 /*******************  Bit definition for CAN_F9R2 register  *******************/
6017 #define CAN_F9R2_FB0_Pos       (0U)
6018 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
6019 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
6020 #define CAN_F9R2_FB1_Pos       (1U)
6021 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
6022 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
6023 #define CAN_F9R2_FB2_Pos       (2U)
6024 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
6025 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
6026 #define CAN_F9R2_FB3_Pos       (3U)
6027 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
6028 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
6029 #define CAN_F9R2_FB4_Pos       (4U)
6030 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
6031 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
6032 #define CAN_F9R2_FB5_Pos       (5U)
6033 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
6034 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
6035 #define CAN_F9R2_FB6_Pos       (6U)
6036 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
6037 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
6038 #define CAN_F9R2_FB7_Pos       (7U)
6039 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
6040 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
6041 #define CAN_F9R2_FB8_Pos       (8U)
6042 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
6043 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
6044 #define CAN_F9R2_FB9_Pos       (9U)
6045 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
6046 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
6047 #define CAN_F9R2_FB10_Pos      (10U)
6048 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
6049 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
6050 #define CAN_F9R2_FB11_Pos      (11U)
6051 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
6052 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
6053 #define CAN_F9R2_FB12_Pos      (12U)
6054 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
6055 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
6056 #define CAN_F9R2_FB13_Pos      (13U)
6057 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
6058 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
6059 #define CAN_F9R2_FB14_Pos      (14U)
6060 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
6061 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
6062 #define CAN_F9R2_FB15_Pos      (15U)
6063 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
6064 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
6065 #define CAN_F9R2_FB16_Pos      (16U)
6066 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
6067 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
6068 #define CAN_F9R2_FB17_Pos      (17U)
6069 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
6070 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
6071 #define CAN_F9R2_FB18_Pos      (18U)
6072 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
6073 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
6074 #define CAN_F9R2_FB19_Pos      (19U)
6075 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
6076 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
6077 #define CAN_F9R2_FB20_Pos      (20U)
6078 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
6079 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
6080 #define CAN_F9R2_FB21_Pos      (21U)
6081 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
6082 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
6083 #define CAN_F9R2_FB22_Pos      (22U)
6084 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
6085 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
6086 #define CAN_F9R2_FB23_Pos      (23U)
6087 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
6088 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
6089 #define CAN_F9R2_FB24_Pos      (24U)
6090 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
6091 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
6092 #define CAN_F9R2_FB25_Pos      (25U)
6093 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
6094 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
6095 #define CAN_F9R2_FB26_Pos      (26U)
6096 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
6097 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
6098 #define CAN_F9R2_FB27_Pos      (27U)
6099 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
6100 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
6101 #define CAN_F9R2_FB28_Pos      (28U)
6102 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
6103 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
6104 #define CAN_F9R2_FB29_Pos      (29U)
6105 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
6106 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
6107 #define CAN_F9R2_FB30_Pos      (30U)
6108 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
6109 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
6110 #define CAN_F9R2_FB31_Pos      (31U)
6111 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
6112 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
6113 
6114 /*******************  Bit definition for CAN_F10R2 register  ******************/
6115 #define CAN_F10R2_FB0_Pos      (0U)
6116 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
6117 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
6118 #define CAN_F10R2_FB1_Pos      (1U)
6119 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
6120 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
6121 #define CAN_F10R2_FB2_Pos      (2U)
6122 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
6123 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
6124 #define CAN_F10R2_FB3_Pos      (3U)
6125 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
6126 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
6127 #define CAN_F10R2_FB4_Pos      (4U)
6128 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
6129 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
6130 #define CAN_F10R2_FB5_Pos      (5U)
6131 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
6132 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
6133 #define CAN_F10R2_FB6_Pos      (6U)
6134 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
6135 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
6136 #define CAN_F10R2_FB7_Pos      (7U)
6137 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
6138 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
6139 #define CAN_F10R2_FB8_Pos      (8U)
6140 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
6141 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
6142 #define CAN_F10R2_FB9_Pos      (9U)
6143 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
6144 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
6145 #define CAN_F10R2_FB10_Pos     (10U)
6146 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
6147 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
6148 #define CAN_F10R2_FB11_Pos     (11U)
6149 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
6150 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
6151 #define CAN_F10R2_FB12_Pos     (12U)
6152 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
6153 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
6154 #define CAN_F10R2_FB13_Pos     (13U)
6155 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
6156 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
6157 #define CAN_F10R2_FB14_Pos     (14U)
6158 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
6159 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
6160 #define CAN_F10R2_FB15_Pos     (15U)
6161 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
6162 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
6163 #define CAN_F10R2_FB16_Pos     (16U)
6164 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
6165 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
6166 #define CAN_F10R2_FB17_Pos     (17U)
6167 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
6168 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
6169 #define CAN_F10R2_FB18_Pos     (18U)
6170 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
6171 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
6172 #define CAN_F10R2_FB19_Pos     (19U)
6173 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
6174 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
6175 #define CAN_F10R2_FB20_Pos     (20U)
6176 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
6177 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
6178 #define CAN_F10R2_FB21_Pos     (21U)
6179 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
6180 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
6181 #define CAN_F10R2_FB22_Pos     (22U)
6182 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
6183 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
6184 #define CAN_F10R2_FB23_Pos     (23U)
6185 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
6186 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
6187 #define CAN_F10R2_FB24_Pos     (24U)
6188 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
6189 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
6190 #define CAN_F10R2_FB25_Pos     (25U)
6191 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
6192 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
6193 #define CAN_F10R2_FB26_Pos     (26U)
6194 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
6195 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
6196 #define CAN_F10R2_FB27_Pos     (27U)
6197 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
6198 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
6199 #define CAN_F10R2_FB28_Pos     (28U)
6200 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
6201 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
6202 #define CAN_F10R2_FB29_Pos     (29U)
6203 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
6204 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
6205 #define CAN_F10R2_FB30_Pos     (30U)
6206 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
6207 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
6208 #define CAN_F10R2_FB31_Pos     (31U)
6209 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
6210 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
6211 
6212 /*******************  Bit definition for CAN_F11R2 register  ******************/
6213 #define CAN_F11R2_FB0_Pos      (0U)
6214 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
6215 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
6216 #define CAN_F11R2_FB1_Pos      (1U)
6217 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
6218 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
6219 #define CAN_F11R2_FB2_Pos      (2U)
6220 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
6221 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
6222 #define CAN_F11R2_FB3_Pos      (3U)
6223 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
6224 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
6225 #define CAN_F11R2_FB4_Pos      (4U)
6226 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
6227 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
6228 #define CAN_F11R2_FB5_Pos      (5U)
6229 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
6230 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
6231 #define CAN_F11R2_FB6_Pos      (6U)
6232 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
6233 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
6234 #define CAN_F11R2_FB7_Pos      (7U)
6235 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
6236 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
6237 #define CAN_F11R2_FB8_Pos      (8U)
6238 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
6239 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
6240 #define CAN_F11R2_FB9_Pos      (9U)
6241 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
6242 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
6243 #define CAN_F11R2_FB10_Pos     (10U)
6244 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
6245 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
6246 #define CAN_F11R2_FB11_Pos     (11U)
6247 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
6248 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
6249 #define CAN_F11R2_FB12_Pos     (12U)
6250 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
6251 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
6252 #define CAN_F11R2_FB13_Pos     (13U)
6253 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
6254 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
6255 #define CAN_F11R2_FB14_Pos     (14U)
6256 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
6257 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
6258 #define CAN_F11R2_FB15_Pos     (15U)
6259 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
6260 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
6261 #define CAN_F11R2_FB16_Pos     (16U)
6262 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
6263 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
6264 #define CAN_F11R2_FB17_Pos     (17U)
6265 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
6266 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
6267 #define CAN_F11R2_FB18_Pos     (18U)
6268 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
6269 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
6270 #define CAN_F11R2_FB19_Pos     (19U)
6271 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
6272 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
6273 #define CAN_F11R2_FB20_Pos     (20U)
6274 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
6275 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
6276 #define CAN_F11R2_FB21_Pos     (21U)
6277 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
6278 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
6279 #define CAN_F11R2_FB22_Pos     (22U)
6280 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
6281 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
6282 #define CAN_F11R2_FB23_Pos     (23U)
6283 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
6284 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
6285 #define CAN_F11R2_FB24_Pos     (24U)
6286 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
6287 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
6288 #define CAN_F11R2_FB25_Pos     (25U)
6289 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
6290 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
6291 #define CAN_F11R2_FB26_Pos     (26U)
6292 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
6293 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
6294 #define CAN_F11R2_FB27_Pos     (27U)
6295 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
6296 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
6297 #define CAN_F11R2_FB28_Pos     (28U)
6298 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
6299 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
6300 #define CAN_F11R2_FB29_Pos     (29U)
6301 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
6302 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
6303 #define CAN_F11R2_FB30_Pos     (30U)
6304 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
6305 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
6306 #define CAN_F11R2_FB31_Pos     (31U)
6307 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
6308 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
6309 
6310 /*******************  Bit definition for CAN_F12R2 register  ******************/
6311 #define CAN_F12R2_FB0_Pos      (0U)
6312 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
6313 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
6314 #define CAN_F12R2_FB1_Pos      (1U)
6315 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
6316 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
6317 #define CAN_F12R2_FB2_Pos      (2U)
6318 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
6319 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
6320 #define CAN_F12R2_FB3_Pos      (3U)
6321 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
6322 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
6323 #define CAN_F12R2_FB4_Pos      (4U)
6324 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
6325 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
6326 #define CAN_F12R2_FB5_Pos      (5U)
6327 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
6328 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
6329 #define CAN_F12R2_FB6_Pos      (6U)
6330 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
6331 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
6332 #define CAN_F12R2_FB7_Pos      (7U)
6333 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
6334 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
6335 #define CAN_F12R2_FB8_Pos      (8U)
6336 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
6337 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
6338 #define CAN_F12R2_FB9_Pos      (9U)
6339 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
6340 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
6341 #define CAN_F12R2_FB10_Pos     (10U)
6342 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
6343 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
6344 #define CAN_F12R2_FB11_Pos     (11U)
6345 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
6346 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
6347 #define CAN_F12R2_FB12_Pos     (12U)
6348 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
6349 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
6350 #define CAN_F12R2_FB13_Pos     (13U)
6351 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
6352 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
6353 #define CAN_F12R2_FB14_Pos     (14U)
6354 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
6355 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
6356 #define CAN_F12R2_FB15_Pos     (15U)
6357 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
6358 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
6359 #define CAN_F12R2_FB16_Pos     (16U)
6360 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
6361 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
6362 #define CAN_F12R2_FB17_Pos     (17U)
6363 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
6364 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
6365 #define CAN_F12R2_FB18_Pos     (18U)
6366 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
6367 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
6368 #define CAN_F12R2_FB19_Pos     (19U)
6369 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
6370 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
6371 #define CAN_F12R2_FB20_Pos     (20U)
6372 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
6373 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
6374 #define CAN_F12R2_FB21_Pos     (21U)
6375 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
6376 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
6377 #define CAN_F12R2_FB22_Pos     (22U)
6378 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
6379 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
6380 #define CAN_F12R2_FB23_Pos     (23U)
6381 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
6382 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
6383 #define CAN_F12R2_FB24_Pos     (24U)
6384 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
6385 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
6386 #define CAN_F12R2_FB25_Pos     (25U)
6387 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
6388 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
6389 #define CAN_F12R2_FB26_Pos     (26U)
6390 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
6391 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
6392 #define CAN_F12R2_FB27_Pos     (27U)
6393 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
6394 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
6395 #define CAN_F12R2_FB28_Pos     (28U)
6396 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
6397 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
6398 #define CAN_F12R2_FB29_Pos     (29U)
6399 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
6400 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
6401 #define CAN_F12R2_FB30_Pos     (30U)
6402 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
6403 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
6404 #define CAN_F12R2_FB31_Pos     (31U)
6405 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
6406 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
6407 
6408 /*******************  Bit definition for CAN_F13R2 register  ******************/
6409 #define CAN_F13R2_FB0_Pos      (0U)
6410 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
6411 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
6412 #define CAN_F13R2_FB1_Pos      (1U)
6413 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
6414 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
6415 #define CAN_F13R2_FB2_Pos      (2U)
6416 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
6417 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
6418 #define CAN_F13R2_FB3_Pos      (3U)
6419 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
6420 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
6421 #define CAN_F13R2_FB4_Pos      (4U)
6422 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
6423 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
6424 #define CAN_F13R2_FB5_Pos      (5U)
6425 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
6426 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
6427 #define CAN_F13R2_FB6_Pos      (6U)
6428 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
6429 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
6430 #define CAN_F13R2_FB7_Pos      (7U)
6431 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
6432 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
6433 #define CAN_F13R2_FB8_Pos      (8U)
6434 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
6435 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
6436 #define CAN_F13R2_FB9_Pos      (9U)
6437 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
6438 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
6439 #define CAN_F13R2_FB10_Pos     (10U)
6440 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
6441 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
6442 #define CAN_F13R2_FB11_Pos     (11U)
6443 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
6444 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
6445 #define CAN_F13R2_FB12_Pos     (12U)
6446 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
6447 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
6448 #define CAN_F13R2_FB13_Pos     (13U)
6449 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
6450 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
6451 #define CAN_F13R2_FB14_Pos     (14U)
6452 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
6453 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
6454 #define CAN_F13R2_FB15_Pos     (15U)
6455 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
6456 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
6457 #define CAN_F13R2_FB16_Pos     (16U)
6458 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
6459 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
6460 #define CAN_F13R2_FB17_Pos     (17U)
6461 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
6462 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
6463 #define CAN_F13R2_FB18_Pos     (18U)
6464 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
6465 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
6466 #define CAN_F13R2_FB19_Pos     (19U)
6467 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
6468 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
6469 #define CAN_F13R2_FB20_Pos     (20U)
6470 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
6471 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
6472 #define CAN_F13R2_FB21_Pos     (21U)
6473 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
6474 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
6475 #define CAN_F13R2_FB22_Pos     (22U)
6476 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
6477 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
6478 #define CAN_F13R2_FB23_Pos     (23U)
6479 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
6480 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
6481 #define CAN_F13R2_FB24_Pos     (24U)
6482 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
6483 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
6484 #define CAN_F13R2_FB25_Pos     (25U)
6485 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
6486 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
6487 #define CAN_F13R2_FB26_Pos     (26U)
6488 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
6489 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
6490 #define CAN_F13R2_FB27_Pos     (27U)
6491 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
6492 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
6493 #define CAN_F13R2_FB28_Pos     (28U)
6494 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
6495 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
6496 #define CAN_F13R2_FB29_Pos     (29U)
6497 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
6498 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
6499 #define CAN_F13R2_FB30_Pos     (30U)
6500 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
6501 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
6502 #define CAN_F13R2_FB31_Pos     (31U)
6503 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
6504 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
6505 
6506 /******************************************************************************/
6507 /*                                                                            */
6508 /*                     CRC calculation unit (CRC)                             */
6509 /*                                                                            */
6510 /******************************************************************************/
6511 /*******************  Bit definition for CRC_DR register  *********************/
6512 #define CRC_DR_DR_Pos            (0U)
6513 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
6514 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
6515 
6516 /*******************  Bit definition for CRC_IDR register  ********************/
6517 #define CRC_IDR_IDR              ((uint8_t)0xFFU)                              /*!< General-purpose 8-bit data register bits */
6518 
6519 /********************  Bit definition for CRC_CR register  ********************/
6520 #define CRC_CR_RESET_Pos         (0U)
6521 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
6522 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
6523 #define CRC_CR_POLYSIZE_Pos      (3U)
6524 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
6525 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
6526 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
6527 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
6528 #define CRC_CR_REV_IN_Pos        (5U)
6529 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
6530 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
6531 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
6532 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
6533 #define CRC_CR_REV_OUT_Pos       (7U)
6534 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
6535 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
6536 
6537 /*******************  Bit definition for CRC_INIT register  *******************/
6538 #define CRC_INIT_INIT_Pos        (0U)
6539 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
6540 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
6541 
6542 /*******************  Bit definition for CRC_POL register  ********************/
6543 #define CRC_POL_POL_Pos          (0U)
6544 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
6545 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
6546 
6547 /******************************************************************************/
6548 /*                                                                            */
6549 /*                 Digital to Analog Converter (DAC)                          */
6550 /*                                                                            */
6551 /******************************************************************************/
6552 
6553 /*
6554  * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
6555  */
6556 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx) */
6557 
6558 
6559 /********************  Bit definition for DAC_CR register  ********************/
6560 #define DAC_CR_EN1_Pos              (0U)
6561 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
6562 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
6563 #define DAC_CR_BOFF1_Pos            (1U)
6564 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
6565 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
6566 #define DAC_CR_TEN1_Pos             (2U)
6567 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
6568 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
6569 
6570 #define DAC_CR_TSEL1_Pos            (3U)
6571 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
6572 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
6573 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
6574 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
6575 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
6576 
6577 #define DAC_CR_WAVE1_Pos            (6U)
6578 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
6579 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6580 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
6581 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
6582 
6583 #define DAC_CR_MAMP1_Pos            (8U)
6584 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
6585 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6586 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
6587 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
6588 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
6589 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
6590 
6591 #define DAC_CR_DMAEN1_Pos           (12U)
6592 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
6593 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
6594 #define DAC_CR_DMAUDRIE1_Pos        (13U)
6595 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
6596 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA underrun IT enable */
6597 #define DAC_CR_EN2_Pos              (16U)
6598 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
6599 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!< DAC channel2 enable */
6600 #define DAC_CR_BOFF2_Pos            (17U)
6601 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
6602 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!< DAC channel2 output buffer disable */
6603 #define DAC_CR_TEN2_Pos             (18U)
6604 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
6605 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!< DAC channel2 Trigger enable */
6606 
6607 #define DAC_CR_TSEL2_Pos            (19U)
6608 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
6609 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
6610 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
6611 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
6612 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
6613 
6614 #define DAC_CR_WAVE2_Pos            (22U)
6615 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
6616 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6617 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
6618 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
6619 
6620 #define DAC_CR_MAMP2_Pos            (24U)
6621 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
6622 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6623 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
6624 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
6625 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
6626 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
6627 
6628 #define DAC_CR_DMAEN2_Pos           (28U)
6629 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
6630 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!< DAC channel2 DMA enabled */
6631 #define DAC_CR_DMAUDRIE2_Pos        (29U)
6632 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
6633 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!< DAC channel2 DMA underrun IT enable */
6634 
6635 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
6636 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
6637 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
6638 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
6639 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
6640 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
6641 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!< DAC channel2 software trigger */
6642 
6643 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
6644 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
6645 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
6646 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
6647 
6648 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
6649 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
6650 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6651 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
6652 
6653 /******************  Bit definition for DAC_DHR8R1 register  ******************/
6654 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
6655 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
6656 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
6657 
6658 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
6659 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
6660 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
6661 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
6662 
6663 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
6664 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
6665 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
6666 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
6667 
6668 /******************  Bit definition for DAC_DHR8R2 register  ******************/
6669 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
6670 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
6671 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
6672 
6673 /*****************  Bit definition for DAC_DHR12RD register  ******************/
6674 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
6675 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
6676 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
6677 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
6678 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
6679 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Right aligned data */
6680 
6681 /*****************  Bit definition for DAC_DHR12LD register  ******************/
6682 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
6683 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6684 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
6685 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
6686 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
6687 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!< DAC channel2 12-bit Left aligned data */
6688 
6689 /******************  Bit definition for DAC_DHR8RD register  ******************/
6690 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
6691 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
6692 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
6693 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
6694 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
6695 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!< DAC channel2 8-bit Right aligned data */
6696 
6697 /*******************  Bit definition for DAC_DOR1 register  *******************/
6698 #define DAC_DOR1_DACC1DOR_Pos       (0U)
6699 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
6700 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
6701 
6702 /*******************  Bit definition for DAC_DOR2 register  *******************/
6703 #define DAC_DOR2_DACC2DOR_Pos       (0U)
6704 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
6705 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!< DAC channel2 data output */
6706 
6707 /********************  Bit definition for DAC_SR register  ********************/
6708 #define DAC_SR_DMAUDR1_Pos          (13U)
6709 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
6710 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
6711 #define DAC_SR_DMAUDR2_Pos          (29U)
6712 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
6713 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!< DAC channel2 DMA underrun flag */
6714 
6715 /******************************************************************************/
6716 /*                                                                            */
6717 /*                                 Debug MCU (DBGMCU)                         */
6718 /*                                                                            */
6719 /******************************************************************************/
6720 /********************  Bit definition for DBGMCU_IDCODE register  *************/
6721 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
6722 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6723 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
6724 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
6725 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6726 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
6727 
6728 /********************  Bit definition for DBGMCU_CR register  *****************/
6729 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
6730 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6731 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
6732 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
6733 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6734 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
6735 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
6736 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6737 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
6738 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
6739 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6740 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
6741 
6742 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
6743 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6744 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
6745 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
6746 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
6747 
6748 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
6749 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
6750 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
6751 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6752 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
6753 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
6754 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6755 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
6756 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
6757 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6758 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
6759 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
6760 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
6761 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
6762 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
6763 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
6764 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
6765 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
6766 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6767 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
6768 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
6769 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6770 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
6771 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
6772 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6773 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
6774 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
6775 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6776 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
6777 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
6778 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6779 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos              (25U)
6780 #define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
6781 #define DBGMCU_APB1_FZ_DBG_CAN_STOP                  DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
6782 
6783 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
6784 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
6785 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
6786 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6787 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
6788 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
6789 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
6790 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos            (2U)
6791 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000004 */
6792 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP                DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
6793 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos            (3U)
6794 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000008 */
6795 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP                DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
6796 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos            (4U)
6797 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000010 */
6798 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP                DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
6799 
6800 /******************************************************************************/
6801 /*                                                                            */
6802 /*                             DMA Controller (DMA)                           */
6803 /*                                                                            */
6804 /******************************************************************************/
6805 /*******************  Bit definition for DMA_ISR register  ********************/
6806 #define DMA_ISR_GIF1_Pos       (0U)
6807 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
6808 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
6809 #define DMA_ISR_TCIF1_Pos      (1U)
6810 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
6811 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
6812 #define DMA_ISR_HTIF1_Pos      (2U)
6813 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
6814 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
6815 #define DMA_ISR_TEIF1_Pos      (3U)
6816 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
6817 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
6818 #define DMA_ISR_GIF2_Pos       (4U)
6819 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
6820 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
6821 #define DMA_ISR_TCIF2_Pos      (5U)
6822 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
6823 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
6824 #define DMA_ISR_HTIF2_Pos      (6U)
6825 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
6826 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
6827 #define DMA_ISR_TEIF2_Pos      (7U)
6828 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
6829 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
6830 #define DMA_ISR_GIF3_Pos       (8U)
6831 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
6832 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
6833 #define DMA_ISR_TCIF3_Pos      (9U)
6834 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
6835 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
6836 #define DMA_ISR_HTIF3_Pos      (10U)
6837 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
6838 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
6839 #define DMA_ISR_TEIF3_Pos      (11U)
6840 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
6841 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
6842 #define DMA_ISR_GIF4_Pos       (12U)
6843 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
6844 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
6845 #define DMA_ISR_TCIF4_Pos      (13U)
6846 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
6847 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
6848 #define DMA_ISR_HTIF4_Pos      (14U)
6849 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
6850 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
6851 #define DMA_ISR_TEIF4_Pos      (15U)
6852 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
6853 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
6854 #define DMA_ISR_GIF5_Pos       (16U)
6855 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
6856 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
6857 #define DMA_ISR_TCIF5_Pos      (17U)
6858 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
6859 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
6860 #define DMA_ISR_HTIF5_Pos      (18U)
6861 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
6862 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
6863 #define DMA_ISR_TEIF5_Pos      (19U)
6864 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
6865 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
6866 #define DMA_ISR_GIF6_Pos       (20U)
6867 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
6868 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
6869 #define DMA_ISR_TCIF6_Pos      (21U)
6870 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
6871 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
6872 #define DMA_ISR_HTIF6_Pos      (22U)
6873 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
6874 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
6875 #define DMA_ISR_TEIF6_Pos      (23U)
6876 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
6877 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
6878 #define DMA_ISR_GIF7_Pos       (24U)
6879 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
6880 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
6881 #define DMA_ISR_TCIF7_Pos      (25U)
6882 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
6883 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
6884 #define DMA_ISR_HTIF7_Pos      (26U)
6885 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
6886 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
6887 #define DMA_ISR_TEIF7_Pos      (27U)
6888 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
6889 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
6890 
6891 /*******************  Bit definition for DMA_IFCR register  *******************/
6892 #define DMA_IFCR_CGIF1_Pos     (0U)
6893 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
6894 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
6895 #define DMA_IFCR_CTCIF1_Pos    (1U)
6896 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
6897 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
6898 #define DMA_IFCR_CHTIF1_Pos    (2U)
6899 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
6900 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
6901 #define DMA_IFCR_CTEIF1_Pos    (3U)
6902 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
6903 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
6904 #define DMA_IFCR_CGIF2_Pos     (4U)
6905 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
6906 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
6907 #define DMA_IFCR_CTCIF2_Pos    (5U)
6908 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
6909 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
6910 #define DMA_IFCR_CHTIF2_Pos    (6U)
6911 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
6912 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
6913 #define DMA_IFCR_CTEIF2_Pos    (7U)
6914 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
6915 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
6916 #define DMA_IFCR_CGIF3_Pos     (8U)
6917 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
6918 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
6919 #define DMA_IFCR_CTCIF3_Pos    (9U)
6920 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
6921 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
6922 #define DMA_IFCR_CHTIF3_Pos    (10U)
6923 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
6924 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
6925 #define DMA_IFCR_CTEIF3_Pos    (11U)
6926 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
6927 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
6928 #define DMA_IFCR_CGIF4_Pos     (12U)
6929 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
6930 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
6931 #define DMA_IFCR_CTCIF4_Pos    (13U)
6932 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
6933 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
6934 #define DMA_IFCR_CHTIF4_Pos    (14U)
6935 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
6936 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
6937 #define DMA_IFCR_CTEIF4_Pos    (15U)
6938 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
6939 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
6940 #define DMA_IFCR_CGIF5_Pos     (16U)
6941 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
6942 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
6943 #define DMA_IFCR_CTCIF5_Pos    (17U)
6944 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
6945 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
6946 #define DMA_IFCR_CHTIF5_Pos    (18U)
6947 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
6948 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
6949 #define DMA_IFCR_CTEIF5_Pos    (19U)
6950 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
6951 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
6952 #define DMA_IFCR_CGIF6_Pos     (20U)
6953 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
6954 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
6955 #define DMA_IFCR_CTCIF6_Pos    (21U)
6956 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
6957 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
6958 #define DMA_IFCR_CHTIF6_Pos    (22U)
6959 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
6960 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
6961 #define DMA_IFCR_CTEIF6_Pos    (23U)
6962 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
6963 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
6964 #define DMA_IFCR_CGIF7_Pos     (24U)
6965 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
6966 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
6967 #define DMA_IFCR_CTCIF7_Pos    (25U)
6968 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
6969 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
6970 #define DMA_IFCR_CHTIF7_Pos    (26U)
6971 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
6972 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
6973 #define DMA_IFCR_CTEIF7_Pos    (27U)
6974 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
6975 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
6976 
6977 /*******************  Bit definition for DMA_CCR register  ********************/
6978 #define DMA_CCR_EN_Pos         (0U)
6979 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
6980 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
6981 #define DMA_CCR_TCIE_Pos       (1U)
6982 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
6983 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
6984 #define DMA_CCR_HTIE_Pos       (2U)
6985 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
6986 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
6987 #define DMA_CCR_TEIE_Pos       (3U)
6988 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
6989 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
6990 #define DMA_CCR_DIR_Pos        (4U)
6991 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
6992 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
6993 #define DMA_CCR_CIRC_Pos       (5U)
6994 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
6995 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
6996 #define DMA_CCR_PINC_Pos       (6U)
6997 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
6998 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
6999 #define DMA_CCR_MINC_Pos       (7U)
7000 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
7001 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
7002 
7003 #define DMA_CCR_PSIZE_Pos      (8U)
7004 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
7005 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
7006 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
7007 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
7008 
7009 #define DMA_CCR_MSIZE_Pos      (10U)
7010 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
7011 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
7012 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
7013 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
7014 
7015 #define DMA_CCR_PL_Pos         (12U)
7016 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
7017 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
7018 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
7019 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
7020 
7021 #define DMA_CCR_MEM2MEM_Pos    (14U)
7022 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
7023 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
7024 
7025 /******************  Bit definition for DMA_CNDTR register  *******************/
7026 #define DMA_CNDTR_NDT_Pos      (0U)
7027 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
7028 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
7029 
7030 /******************  Bit definition for DMA_CPAR register  ********************/
7031 #define DMA_CPAR_PA_Pos        (0U)
7032 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
7033 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
7034 
7035 /******************  Bit definition for DMA_CMAR register  ********************/
7036 #define DMA_CMAR_MA_Pos        (0U)
7037 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
7038 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
7039 
7040 /******************************************************************************/
7041 /*                                                                            */
7042 /*                    External Interrupt/Event Controller (EXTI)              */
7043 /*                                                                            */
7044 /******************************************************************************/
7045 /*******************  Bit definition for EXTI_IMR register  *******************/
7046 #define EXTI_IMR_MR0_Pos           (0U)
7047 #define EXTI_IMR_MR0_Msk           (0x1UL << EXTI_IMR_MR0_Pos)                  /*!< 0x00000001 */
7048 #define EXTI_IMR_MR0               EXTI_IMR_MR0_Msk                            /*!< Interrupt Mask on line 0 */
7049 #define EXTI_IMR_MR1_Pos           (1U)
7050 #define EXTI_IMR_MR1_Msk           (0x1UL << EXTI_IMR_MR1_Pos)                  /*!< 0x00000002 */
7051 #define EXTI_IMR_MR1               EXTI_IMR_MR1_Msk                            /*!< Interrupt Mask on line 1 */
7052 #define EXTI_IMR_MR2_Pos           (2U)
7053 #define EXTI_IMR_MR2_Msk           (0x1UL << EXTI_IMR_MR2_Pos)                  /*!< 0x00000004 */
7054 #define EXTI_IMR_MR2               EXTI_IMR_MR2_Msk                            /*!< Interrupt Mask on line 2 */
7055 #define EXTI_IMR_MR3_Pos           (3U)
7056 #define EXTI_IMR_MR3_Msk           (0x1UL << EXTI_IMR_MR3_Pos)                  /*!< 0x00000008 */
7057 #define EXTI_IMR_MR3               EXTI_IMR_MR3_Msk                            /*!< Interrupt Mask on line 3 */
7058 #define EXTI_IMR_MR4_Pos           (4U)
7059 #define EXTI_IMR_MR4_Msk           (0x1UL << EXTI_IMR_MR4_Pos)                  /*!< 0x00000010 */
7060 #define EXTI_IMR_MR4               EXTI_IMR_MR4_Msk                            /*!< Interrupt Mask on line 4 */
7061 #define EXTI_IMR_MR5_Pos           (5U)
7062 #define EXTI_IMR_MR5_Msk           (0x1UL << EXTI_IMR_MR5_Pos)                  /*!< 0x00000020 */
7063 #define EXTI_IMR_MR5               EXTI_IMR_MR5_Msk                            /*!< Interrupt Mask on line 5 */
7064 #define EXTI_IMR_MR6_Pos           (6U)
7065 #define EXTI_IMR_MR6_Msk           (0x1UL << EXTI_IMR_MR6_Pos)                  /*!< 0x00000040 */
7066 #define EXTI_IMR_MR6               EXTI_IMR_MR6_Msk                            /*!< Interrupt Mask on line 6 */
7067 #define EXTI_IMR_MR7_Pos           (7U)
7068 #define EXTI_IMR_MR7_Msk           (0x1UL << EXTI_IMR_MR7_Pos)                  /*!< 0x00000080 */
7069 #define EXTI_IMR_MR7               EXTI_IMR_MR7_Msk                            /*!< Interrupt Mask on line 7 */
7070 #define EXTI_IMR_MR8_Pos           (8U)
7071 #define EXTI_IMR_MR8_Msk           (0x1UL << EXTI_IMR_MR8_Pos)                  /*!< 0x00000100 */
7072 #define EXTI_IMR_MR8               EXTI_IMR_MR8_Msk                            /*!< Interrupt Mask on line 8 */
7073 #define EXTI_IMR_MR9_Pos           (9U)
7074 #define EXTI_IMR_MR9_Msk           (0x1UL << EXTI_IMR_MR9_Pos)                  /*!< 0x00000200 */
7075 #define EXTI_IMR_MR9               EXTI_IMR_MR9_Msk                            /*!< Interrupt Mask on line 9 */
7076 #define EXTI_IMR_MR10_Pos          (10U)
7077 #define EXTI_IMR_MR10_Msk          (0x1UL << EXTI_IMR_MR10_Pos)                 /*!< 0x00000400 */
7078 #define EXTI_IMR_MR10              EXTI_IMR_MR10_Msk                           /*!< Interrupt Mask on line 10 */
7079 #define EXTI_IMR_MR11_Pos          (11U)
7080 #define EXTI_IMR_MR11_Msk          (0x1UL << EXTI_IMR_MR11_Pos)                 /*!< 0x00000800 */
7081 #define EXTI_IMR_MR11              EXTI_IMR_MR11_Msk                           /*!< Interrupt Mask on line 11 */
7082 #define EXTI_IMR_MR12_Pos          (12U)
7083 #define EXTI_IMR_MR12_Msk          (0x1UL << EXTI_IMR_MR12_Pos)                 /*!< 0x00001000 */
7084 #define EXTI_IMR_MR12              EXTI_IMR_MR12_Msk                           /*!< Interrupt Mask on line 12 */
7085 #define EXTI_IMR_MR13_Pos          (13U)
7086 #define EXTI_IMR_MR13_Msk          (0x1UL << EXTI_IMR_MR13_Pos)                 /*!< 0x00002000 */
7087 #define EXTI_IMR_MR13              EXTI_IMR_MR13_Msk                           /*!< Interrupt Mask on line 13 */
7088 #define EXTI_IMR_MR14_Pos          (14U)
7089 #define EXTI_IMR_MR14_Msk          (0x1UL << EXTI_IMR_MR14_Pos)                 /*!< 0x00004000 */
7090 #define EXTI_IMR_MR14              EXTI_IMR_MR14_Msk                           /*!< Interrupt Mask on line 14 */
7091 #define EXTI_IMR_MR15_Pos          (15U)
7092 #define EXTI_IMR_MR15_Msk          (0x1UL << EXTI_IMR_MR15_Pos)                 /*!< 0x00008000 */
7093 #define EXTI_IMR_MR15              EXTI_IMR_MR15_Msk                           /*!< Interrupt Mask on line 15 */
7094 #define EXTI_IMR_MR16_Pos          (16U)
7095 #define EXTI_IMR_MR16_Msk          (0x1UL << EXTI_IMR_MR16_Pos)                 /*!< 0x00010000 */
7096 #define EXTI_IMR_MR16              EXTI_IMR_MR16_Msk                           /*!< Interrupt Mask on line 16 */
7097 #define EXTI_IMR_MR17_Pos          (17U)
7098 #define EXTI_IMR_MR17_Msk          (0x1UL << EXTI_IMR_MR17_Pos)                 /*!< 0x00020000 */
7099 #define EXTI_IMR_MR17              EXTI_IMR_MR17_Msk                           /*!< Interrupt Mask on line 17 */
7100 #define EXTI_IMR_MR19_Pos          (19U)
7101 #define EXTI_IMR_MR19_Msk          (0x1UL << EXTI_IMR_MR19_Pos)                 /*!< 0x00080000 */
7102 #define EXTI_IMR_MR19              EXTI_IMR_MR19_Msk                           /*!< Interrupt Mask on line 19 */
7103 #define EXTI_IMR_MR20_Pos          (20U)
7104 #define EXTI_IMR_MR20_Msk          (0x1UL << EXTI_IMR_MR20_Pos)                 /*!< 0x00100000 */
7105 #define EXTI_IMR_MR20              EXTI_IMR_MR20_Msk                           /*!< Interrupt Mask on line 20 */
7106 #define EXTI_IMR_MR21_Pos          (21U)
7107 #define EXTI_IMR_MR21_Msk          (0x1UL << EXTI_IMR_MR21_Pos)                 /*!< 0x00200000 */
7108 #define EXTI_IMR_MR21              EXTI_IMR_MR21_Msk                           /*!< Interrupt Mask on line 21 */
7109 #define EXTI_IMR_MR22_Pos          (22U)
7110 #define EXTI_IMR_MR22_Msk          (0x1UL << EXTI_IMR_MR22_Pos)                 /*!< 0x00400000 */
7111 #define EXTI_IMR_MR22              EXTI_IMR_MR22_Msk                           /*!< Interrupt Mask on line 22 */
7112 #define EXTI_IMR_MR23_Pos          (23U)
7113 #define EXTI_IMR_MR23_Msk          (0x1UL << EXTI_IMR_MR23_Pos)                 /*!< 0x00800000 */
7114 #define EXTI_IMR_MR23              EXTI_IMR_MR23_Msk                           /*!< Interrupt Mask on line 23 */
7115 #define EXTI_IMR_MR24_Pos          (24U)
7116 #define EXTI_IMR_MR24_Msk          (0x1UL << EXTI_IMR_MR24_Pos)                 /*!< 0x01000000 */
7117 #define EXTI_IMR_MR24              EXTI_IMR_MR24_Msk                           /*!< Interrupt Mask on line 24 */
7118 #define EXTI_IMR_MR25_Pos          (25U)
7119 #define EXTI_IMR_MR25_Msk          (0x1UL << EXTI_IMR_MR25_Pos)                 /*!< 0x02000000 */
7120 #define EXTI_IMR_MR25              EXTI_IMR_MR25_Msk                           /*!< Interrupt Mask on line 25 */
7121 #define EXTI_IMR_MR26_Pos          (26U)
7122 #define EXTI_IMR_MR26_Msk          (0x1UL << EXTI_IMR_MR26_Pos)                 /*!< 0x04000000 */
7123 #define EXTI_IMR_MR26              EXTI_IMR_MR26_Msk                           /*!< Interrupt Mask on line 26 */
7124 #define EXTI_IMR_MR28_Pos          (28U)
7125 #define EXTI_IMR_MR28_Msk          (0x1UL << EXTI_IMR_MR28_Pos)                 /*!< 0x10000000 */
7126 #define EXTI_IMR_MR28              EXTI_IMR_MR28_Msk                           /*!< Interrupt Mask on line 28 */
7127 #define EXTI_IMR_MR29_Pos          (29U)
7128 #define EXTI_IMR_MR29_Msk          (0x1UL << EXTI_IMR_MR29_Pos)                 /*!< 0x20000000 */
7129 #define EXTI_IMR_MR29              EXTI_IMR_MR29_Msk                           /*!< Interrupt Mask on line 29 */
7130 #define EXTI_IMR_MR30_Pos          (30U)
7131 #define EXTI_IMR_MR30_Msk          (0x1UL << EXTI_IMR_MR30_Pos)                 /*!< 0x40000000 */
7132 #define EXTI_IMR_MR30              EXTI_IMR_MR30_Msk                           /*!< Interrupt Mask on line 30 */
7133 #define EXTI_IMR_MR31_Pos          (31U)
7134 #define EXTI_IMR_MR31_Msk          (0x1UL << EXTI_IMR_MR31_Pos)                 /*!< 0x80000000 */
7135 #define EXTI_IMR_MR31              EXTI_IMR_MR31_Msk                           /*!< Interrupt Mask on line 31 */
7136 
7137 /* References Defines */
7138 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
7139 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
7140 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
7141 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
7142 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
7143 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
7144 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
7145 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
7146 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
7147 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
7148 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
7149 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
7150 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
7151 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
7152 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
7153 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
7154 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
7155 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
7156 #if defined(EXTI_IMR_MR18)
7157 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
7158 #endif
7159 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
7160 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
7161 #if defined(EXTI_IMR_MR21)
7162 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
7163 #endif
7164 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
7165 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
7166 #if defined(EXTI_IMR_MR24)
7167 #define  EXTI_IMR_IM24 EXTI_IMR_MR24
7168 #endif
7169 #define  EXTI_IMR_IM25 EXTI_IMR_MR25
7170 #if defined(EXTI_IMR_MR26)
7171 #define  EXTI_IMR_IM26 EXTI_IMR_MR26
7172 #endif
7173 #if defined(EXTI_IMR_MR27)
7174 #define  EXTI_IMR_IM27 EXTI_IMR_MR27
7175 #endif
7176 #if defined(EXTI_IMR_MR28)
7177 #define  EXTI_IMR_IM28 EXTI_IMR_MR28
7178 #endif
7179 #if defined(EXTI_IMR_MR29)
7180 #define  EXTI_IMR_IM29 EXTI_IMR_MR29
7181 #endif
7182 #if defined(EXTI_IMR_MR30)
7183 #define  EXTI_IMR_IM30 EXTI_IMR_MR30
7184 #endif
7185 #if defined(EXTI_IMR_MR31)
7186 #define  EXTI_IMR_IM31 EXTI_IMR_MR31
7187 #endif
7188 
7189 #define EXTI_IMR_IM_Pos            (0U)
7190 #define EXTI_IMR_IM_Msk            (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)            /*!< 0xFFFFFFFF */
7191 #define EXTI_IMR_IM                EXTI_IMR_IM_Msk                             /*!< Interrupt Mask All */
7192 
7193 /*******************  Bit definition for EXTI_EMR register  *******************/
7194 #define EXTI_EMR_MR0_Pos           (0U)
7195 #define EXTI_EMR_MR0_Msk           (0x1UL << EXTI_EMR_MR0_Pos)                  /*!< 0x00000001 */
7196 #define EXTI_EMR_MR0               EXTI_EMR_MR0_Msk                            /*!< Event Mask on line 0 */
7197 #define EXTI_EMR_MR1_Pos           (1U)
7198 #define EXTI_EMR_MR1_Msk           (0x1UL << EXTI_EMR_MR1_Pos)                  /*!< 0x00000002 */
7199 #define EXTI_EMR_MR1               EXTI_EMR_MR1_Msk                            /*!< Event Mask on line 1 */
7200 #define EXTI_EMR_MR2_Pos           (2U)
7201 #define EXTI_EMR_MR2_Msk           (0x1UL << EXTI_EMR_MR2_Pos)                  /*!< 0x00000004 */
7202 #define EXTI_EMR_MR2               EXTI_EMR_MR2_Msk                            /*!< Event Mask on line 2 */
7203 #define EXTI_EMR_MR3_Pos           (3U)
7204 #define EXTI_EMR_MR3_Msk           (0x1UL << EXTI_EMR_MR3_Pos)                  /*!< 0x00000008 */
7205 #define EXTI_EMR_MR3               EXTI_EMR_MR3_Msk                            /*!< Event Mask on line 3 */
7206 #define EXTI_EMR_MR4_Pos           (4U)
7207 #define EXTI_EMR_MR4_Msk           (0x1UL << EXTI_EMR_MR4_Pos)                  /*!< 0x00000010 */
7208 #define EXTI_EMR_MR4               EXTI_EMR_MR4_Msk                            /*!< Event Mask on line 4 */
7209 #define EXTI_EMR_MR5_Pos           (5U)
7210 #define EXTI_EMR_MR5_Msk           (0x1UL << EXTI_EMR_MR5_Pos)                  /*!< 0x00000020 */
7211 #define EXTI_EMR_MR5               EXTI_EMR_MR5_Msk                            /*!< Event Mask on line 5 */
7212 #define EXTI_EMR_MR6_Pos           (6U)
7213 #define EXTI_EMR_MR6_Msk           (0x1UL << EXTI_EMR_MR6_Pos)                  /*!< 0x00000040 */
7214 #define EXTI_EMR_MR6               EXTI_EMR_MR6_Msk                            /*!< Event Mask on line 6 */
7215 #define EXTI_EMR_MR7_Pos           (7U)
7216 #define EXTI_EMR_MR7_Msk           (0x1UL << EXTI_EMR_MR7_Pos)                  /*!< 0x00000080 */
7217 #define EXTI_EMR_MR7               EXTI_EMR_MR7_Msk                            /*!< Event Mask on line 7 */
7218 #define EXTI_EMR_MR8_Pos           (8U)
7219 #define EXTI_EMR_MR8_Msk           (0x1UL << EXTI_EMR_MR8_Pos)                  /*!< 0x00000100 */
7220 #define EXTI_EMR_MR8               EXTI_EMR_MR8_Msk                            /*!< Event Mask on line 8 */
7221 #define EXTI_EMR_MR9_Pos           (9U)
7222 #define EXTI_EMR_MR9_Msk           (0x1UL << EXTI_EMR_MR9_Pos)                  /*!< 0x00000200 */
7223 #define EXTI_EMR_MR9               EXTI_EMR_MR9_Msk                            /*!< Event Mask on line 9 */
7224 #define EXTI_EMR_MR10_Pos          (10U)
7225 #define EXTI_EMR_MR10_Msk          (0x1UL << EXTI_EMR_MR10_Pos)                 /*!< 0x00000400 */
7226 #define EXTI_EMR_MR10              EXTI_EMR_MR10_Msk                           /*!< Event Mask on line 10 */
7227 #define EXTI_EMR_MR11_Pos          (11U)
7228 #define EXTI_EMR_MR11_Msk          (0x1UL << EXTI_EMR_MR11_Pos)                 /*!< 0x00000800 */
7229 #define EXTI_EMR_MR11              EXTI_EMR_MR11_Msk                           /*!< Event Mask on line 11 */
7230 #define EXTI_EMR_MR12_Pos          (12U)
7231 #define EXTI_EMR_MR12_Msk          (0x1UL << EXTI_EMR_MR12_Pos)                 /*!< 0x00001000 */
7232 #define EXTI_EMR_MR12              EXTI_EMR_MR12_Msk                           /*!< Event Mask on line 12 */
7233 #define EXTI_EMR_MR13_Pos          (13U)
7234 #define EXTI_EMR_MR13_Msk          (0x1UL << EXTI_EMR_MR13_Pos)                 /*!< 0x00002000 */
7235 #define EXTI_EMR_MR13              EXTI_EMR_MR13_Msk                           /*!< Event Mask on line 13 */
7236 #define EXTI_EMR_MR14_Pos          (14U)
7237 #define EXTI_EMR_MR14_Msk          (0x1UL << EXTI_EMR_MR14_Pos)                 /*!< 0x00004000 */
7238 #define EXTI_EMR_MR14              EXTI_EMR_MR14_Msk                           /*!< Event Mask on line 14 */
7239 #define EXTI_EMR_MR15_Pos          (15U)
7240 #define EXTI_EMR_MR15_Msk          (0x1UL << EXTI_EMR_MR15_Pos)                 /*!< 0x00008000 */
7241 #define EXTI_EMR_MR15              EXTI_EMR_MR15_Msk                           /*!< Event Mask on line 15 */
7242 #define EXTI_EMR_MR16_Pos          (16U)
7243 #define EXTI_EMR_MR16_Msk          (0x1UL << EXTI_EMR_MR16_Pos)                 /*!< 0x00010000 */
7244 #define EXTI_EMR_MR16              EXTI_EMR_MR16_Msk                           /*!< Event Mask on line 16 */
7245 #define EXTI_EMR_MR17_Pos          (17U)
7246 #define EXTI_EMR_MR17_Msk          (0x1UL << EXTI_EMR_MR17_Pos)                 /*!< 0x00020000 */
7247 #define EXTI_EMR_MR17              EXTI_EMR_MR17_Msk                           /*!< Event Mask on line 17 */
7248 #define EXTI_EMR_MR19_Pos          (19U)
7249 #define EXTI_EMR_MR19_Msk          (0x1UL << EXTI_EMR_MR19_Pos)                 /*!< 0x00080000 */
7250 #define EXTI_EMR_MR19              EXTI_EMR_MR19_Msk                           /*!< Event Mask on line 19 */
7251 #define EXTI_EMR_MR20_Pos          (20U)
7252 #define EXTI_EMR_MR20_Msk          (0x1UL << EXTI_EMR_MR20_Pos)                 /*!< 0x00100000 */
7253 #define EXTI_EMR_MR20              EXTI_EMR_MR20_Msk                           /*!< Event Mask on line 20 */
7254 #define EXTI_EMR_MR21_Pos          (21U)
7255 #define EXTI_EMR_MR21_Msk          (0x1UL << EXTI_EMR_MR21_Pos)                 /*!< 0x00200000 */
7256 #define EXTI_EMR_MR21              EXTI_EMR_MR21_Msk                           /*!< Event Mask on line 21 */
7257 #define EXTI_EMR_MR22_Pos          (22U)
7258 #define EXTI_EMR_MR22_Msk          (0x1UL << EXTI_EMR_MR22_Pos)                 /*!< 0x00400000 */
7259 #define EXTI_EMR_MR22              EXTI_EMR_MR22_Msk                           /*!< Event Mask on line 22 */
7260 #define EXTI_EMR_MR23_Pos          (23U)
7261 #define EXTI_EMR_MR23_Msk          (0x1UL << EXTI_EMR_MR23_Pos)                 /*!< 0x00800000 */
7262 #define EXTI_EMR_MR23              EXTI_EMR_MR23_Msk                           /*!< Event Mask on line 23 */
7263 #define EXTI_EMR_MR24_Pos          (24U)
7264 #define EXTI_EMR_MR24_Msk          (0x1UL << EXTI_EMR_MR24_Pos)                 /*!< 0x01000000 */
7265 #define EXTI_EMR_MR24              EXTI_EMR_MR24_Msk                           /*!< Event Mask on line 24 */
7266 #define EXTI_EMR_MR25_Pos          (25U)
7267 #define EXTI_EMR_MR25_Msk          (0x1UL << EXTI_EMR_MR25_Pos)                 /*!< 0x02000000 */
7268 #define EXTI_EMR_MR25              EXTI_EMR_MR25_Msk                           /*!< Event Mask on line 25 */
7269 #define EXTI_EMR_MR26_Pos          (26U)
7270 #define EXTI_EMR_MR26_Msk          (0x1UL << EXTI_EMR_MR26_Pos)                 /*!< 0x04000000 */
7271 #define EXTI_EMR_MR26              EXTI_EMR_MR26_Msk                           /*!< Event Mask on line 26 */
7272 #define EXTI_EMR_MR28_Pos          (28U)
7273 #define EXTI_EMR_MR28_Msk          (0x1UL << EXTI_EMR_MR28_Pos)                 /*!< 0x10000000 */
7274 #define EXTI_EMR_MR28              EXTI_EMR_MR28_Msk                           /*!< Event Mask on line 28 */
7275 #define EXTI_EMR_MR29_Pos          (29U)
7276 #define EXTI_EMR_MR29_Msk          (0x1UL << EXTI_EMR_MR29_Pos)                 /*!< 0x20000000 */
7277 #define EXTI_EMR_MR29              EXTI_EMR_MR29_Msk                           /*!< Event Mask on line 29 */
7278 #define EXTI_EMR_MR30_Pos          (30U)
7279 #define EXTI_EMR_MR30_Msk          (0x1UL << EXTI_EMR_MR30_Pos)                 /*!< 0x40000000 */
7280 #define EXTI_EMR_MR30              EXTI_EMR_MR30_Msk                           /*!< Event Mask on line 30 */
7281 #define EXTI_EMR_MR31_Pos          (31U)
7282 #define EXTI_EMR_MR31_Msk          (0x1UL << EXTI_EMR_MR31_Pos)                 /*!< 0x80000000 */
7283 #define EXTI_EMR_MR31              EXTI_EMR_MR31_Msk                           /*!< Event Mask on line 31 */
7284 
7285 /* References Defines */
7286 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
7287 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
7288 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
7289 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
7290 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
7291 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
7292 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
7293 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
7294 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
7295 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
7296 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
7297 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
7298 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
7299 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
7300 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
7301 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
7302 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
7303 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
7304 #if defined(EXTI_EMR_MR18)
7305 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
7306 #endif
7307 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
7308 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
7309 #if defined(EXTI_EMR_MR21)
7310 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
7311 #endif
7312 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
7313 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
7314 #if defined(EXTI_EMR_MR24)
7315 #define  EXTI_EMR_EM24 EXTI_EMR_MR24
7316 #endif
7317 #define  EXTI_EMR_EM25 EXTI_EMR_MR25
7318 #if defined(EXTI_EMR_MR26)
7319 #define  EXTI_EMR_EM26 EXTI_EMR_MR26
7320 #endif
7321 #if defined(EXTI_EMR_MR27)
7322 #define  EXTI_EMR_EM27 EXTI_EMR_MR27
7323 #endif
7324 #if defined(EXTI_EMR_MR28)
7325 #define  EXTI_EMR_EM28 EXTI_EMR_MR28
7326 #endif
7327 #if defined(EXTI_EMR_MR29)
7328 #define  EXTI_EMR_EM29 EXTI_EMR_MR29
7329 #endif
7330 #if defined(EXTI_EMR_MR30)
7331 #define  EXTI_EMR_EM30 EXTI_EMR_MR30
7332 #endif
7333 #if defined(EXTI_EMR_MR31)
7334 #define  EXTI_EMR_EM31 EXTI_EMR_MR31
7335 #endif
7336 
7337 /******************  Bit definition for EXTI_RTSR register  *******************/
7338 #define EXTI_RTSR_TR0_Pos          (0U)
7339 #define EXTI_RTSR_TR0_Msk          (0x1UL << EXTI_RTSR_TR0_Pos)                 /*!< 0x00000001 */
7340 #define EXTI_RTSR_TR0              EXTI_RTSR_TR0_Msk                           /*!< Rising trigger event configuration bit of line 0 */
7341 #define EXTI_RTSR_TR1_Pos          (1U)
7342 #define EXTI_RTSR_TR1_Msk          (0x1UL << EXTI_RTSR_TR1_Pos)                 /*!< 0x00000002 */
7343 #define EXTI_RTSR_TR1              EXTI_RTSR_TR1_Msk                           /*!< Rising trigger event configuration bit of line 1 */
7344 #define EXTI_RTSR_TR2_Pos          (2U)
7345 #define EXTI_RTSR_TR2_Msk          (0x1UL << EXTI_RTSR_TR2_Pos)                 /*!< 0x00000004 */
7346 #define EXTI_RTSR_TR2              EXTI_RTSR_TR2_Msk                           /*!< Rising trigger event configuration bit of line 2 */
7347 #define EXTI_RTSR_TR3_Pos          (3U)
7348 #define EXTI_RTSR_TR3_Msk          (0x1UL << EXTI_RTSR_TR3_Pos)                 /*!< 0x00000008 */
7349 #define EXTI_RTSR_TR3              EXTI_RTSR_TR3_Msk                           /*!< Rising trigger event configuration bit of line 3 */
7350 #define EXTI_RTSR_TR4_Pos          (4U)
7351 #define EXTI_RTSR_TR4_Msk          (0x1UL << EXTI_RTSR_TR4_Pos)                 /*!< 0x00000010 */
7352 #define EXTI_RTSR_TR4              EXTI_RTSR_TR4_Msk                           /*!< Rising trigger event configuration bit of line 4 */
7353 #define EXTI_RTSR_TR5_Pos          (5U)
7354 #define EXTI_RTSR_TR5_Msk          (0x1UL << EXTI_RTSR_TR5_Pos)                 /*!< 0x00000020 */
7355 #define EXTI_RTSR_TR5              EXTI_RTSR_TR5_Msk                           /*!< Rising trigger event configuration bit of line 5 */
7356 #define EXTI_RTSR_TR6_Pos          (6U)
7357 #define EXTI_RTSR_TR6_Msk          (0x1UL << EXTI_RTSR_TR6_Pos)                 /*!< 0x00000040 */
7358 #define EXTI_RTSR_TR6              EXTI_RTSR_TR6_Msk                           /*!< Rising trigger event configuration bit of line 6 */
7359 #define EXTI_RTSR_TR7_Pos          (7U)
7360 #define EXTI_RTSR_TR7_Msk          (0x1UL << EXTI_RTSR_TR7_Pos)                 /*!< 0x00000080 */
7361 #define EXTI_RTSR_TR7              EXTI_RTSR_TR7_Msk                           /*!< Rising trigger event configuration bit of line 7 */
7362 #define EXTI_RTSR_TR8_Pos          (8U)
7363 #define EXTI_RTSR_TR8_Msk          (0x1UL << EXTI_RTSR_TR8_Pos)                 /*!< 0x00000100 */
7364 #define EXTI_RTSR_TR8              EXTI_RTSR_TR8_Msk                           /*!< Rising trigger event configuration bit of line 8 */
7365 #define EXTI_RTSR_TR9_Pos          (9U)
7366 #define EXTI_RTSR_TR9_Msk          (0x1UL << EXTI_RTSR_TR9_Pos)                 /*!< 0x00000200 */
7367 #define EXTI_RTSR_TR9              EXTI_RTSR_TR9_Msk                           /*!< Rising trigger event configuration bit of line 9 */
7368 #define EXTI_RTSR_TR10_Pos         (10U)
7369 #define EXTI_RTSR_TR10_Msk         (0x1UL << EXTI_RTSR_TR10_Pos)                /*!< 0x00000400 */
7370 #define EXTI_RTSR_TR10             EXTI_RTSR_TR10_Msk                          /*!< Rising trigger event configuration bit of line 10 */
7371 #define EXTI_RTSR_TR11_Pos         (11U)
7372 #define EXTI_RTSR_TR11_Msk         (0x1UL << EXTI_RTSR_TR11_Pos)                /*!< 0x00000800 */
7373 #define EXTI_RTSR_TR11             EXTI_RTSR_TR11_Msk                          /*!< Rising trigger event configuration bit of line 11 */
7374 #define EXTI_RTSR_TR12_Pos         (12U)
7375 #define EXTI_RTSR_TR12_Msk         (0x1UL << EXTI_RTSR_TR12_Pos)                /*!< 0x00001000 */
7376 #define EXTI_RTSR_TR12             EXTI_RTSR_TR12_Msk                          /*!< Rising trigger event configuration bit of line 12 */
7377 #define EXTI_RTSR_TR13_Pos         (13U)
7378 #define EXTI_RTSR_TR13_Msk         (0x1UL << EXTI_RTSR_TR13_Pos)                /*!< 0x00002000 */
7379 #define EXTI_RTSR_TR13             EXTI_RTSR_TR13_Msk                          /*!< Rising trigger event configuration bit of line 13 */
7380 #define EXTI_RTSR_TR14_Pos         (14U)
7381 #define EXTI_RTSR_TR14_Msk         (0x1UL << EXTI_RTSR_TR14_Pos)                /*!< 0x00004000 */
7382 #define EXTI_RTSR_TR14             EXTI_RTSR_TR14_Msk                          /*!< Rising trigger event configuration bit of line 14 */
7383 #define EXTI_RTSR_TR15_Pos         (15U)
7384 #define EXTI_RTSR_TR15_Msk         (0x1UL << EXTI_RTSR_TR15_Pos)                /*!< 0x00008000 */
7385 #define EXTI_RTSR_TR15             EXTI_RTSR_TR15_Msk                          /*!< Rising trigger event configuration bit of line 15 */
7386 #define EXTI_RTSR_TR16_Pos         (16U)
7387 #define EXTI_RTSR_TR16_Msk         (0x1UL << EXTI_RTSR_TR16_Pos)                /*!< 0x00010000 */
7388 #define EXTI_RTSR_TR16             EXTI_RTSR_TR16_Msk                          /*!< Rising trigger event configuration bit of line 16 */
7389 #define EXTI_RTSR_TR17_Pos         (17U)
7390 #define EXTI_RTSR_TR17_Msk         (0x1UL << EXTI_RTSR_TR17_Pos)                /*!< 0x00020000 */
7391 #define EXTI_RTSR_TR17             EXTI_RTSR_TR17_Msk                          /*!< Rising trigger event configuration bit of line 17 */
7392 #define EXTI_RTSR_TR19_Pos         (19U)
7393 #define EXTI_RTSR_TR19_Msk         (0x1UL << EXTI_RTSR_TR19_Pos)                /*!< 0x00080000 */
7394 #define EXTI_RTSR_TR19             EXTI_RTSR_TR19_Msk                          /*!< Rising trigger event configuration bit of line 19 */
7395 #define EXTI_RTSR_TR20_Pos         (20U)
7396 #define EXTI_RTSR_TR20_Msk         (0x1UL << EXTI_RTSR_TR20_Pos)                /*!< 0x00100000 */
7397 #define EXTI_RTSR_TR20             EXTI_RTSR_TR20_Msk                          /*!< Rising trigger event configuration bit of line 20 */
7398 #define EXTI_RTSR_TR21_Pos         (21U)
7399 #define EXTI_RTSR_TR21_Msk         (0x1UL << EXTI_RTSR_TR21_Pos)                /*!< 0x00200000 */
7400 #define EXTI_RTSR_TR21             EXTI_RTSR_TR21_Msk                          /*!< Rising trigger event configuration bit of line 21 */
7401 #define EXTI_RTSR_TR22_Pos         (22U)
7402 #define EXTI_RTSR_TR22_Msk         (0x1UL << EXTI_RTSR_TR22_Pos)                /*!< 0x00400000 */
7403 #define EXTI_RTSR_TR22             EXTI_RTSR_TR22_Msk                          /*!< Rising trigger event configuration bit of line 22 */
7404 #define EXTI_RTSR_TR29_Pos         (29U)
7405 #define EXTI_RTSR_TR29_Msk         (0x1UL << EXTI_RTSR_TR29_Pos)                /*!< 0x20000000 */
7406 #define EXTI_RTSR_TR29             EXTI_RTSR_TR29_Msk                          /*!< Rising trigger event configuration bit of line 29 */
7407 #define EXTI_RTSR_TR30_Pos         (30U)
7408 #define EXTI_RTSR_TR30_Msk         (0x1UL << EXTI_RTSR_TR30_Pos)                /*!< 0x40000000 */
7409 #define EXTI_RTSR_TR30             EXTI_RTSR_TR30_Msk                          /*!< Rising trigger event configuration bit of line 30 */
7410 #define EXTI_RTSR_TR31_Pos         (31U)
7411 #define EXTI_RTSR_TR31_Msk         (0x1UL << EXTI_RTSR_TR31_Pos)                /*!< 0x80000000 */
7412 #define EXTI_RTSR_TR31             EXTI_RTSR_TR31_Msk                          /*!< Rising trigger event configuration bit of line 31 */
7413 
7414 /* References Defines */
7415 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
7416 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
7417 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
7418 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
7419 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
7420 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
7421 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
7422 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
7423 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
7424 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
7425 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
7426 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
7427 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
7428 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
7429 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
7430 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
7431 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
7432 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
7433 #if defined(EXTI_RTSR_TR18)
7434 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
7435 #endif
7436 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
7437 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
7438 #if defined(EXTI_RTSR_TR21)
7439 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
7440 #endif
7441 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
7442 #if defined(EXTI_RTSR_TR23)
7443 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
7444 #endif
7445 #if defined(EXTI_RTSR_TR24)
7446 #define EXTI_RTSR_RT24 EXTI_RTSR_TR24
7447 #endif
7448 #if defined(EXTI_RTSR_TR25)
7449 #define EXTI_RTSR_RT25 EXTI_RTSR_TR25
7450 #endif
7451 #if defined(EXTI_RTSR_TR26)
7452 #define EXTI_RTSR_RT26 EXTI_RTSR_TR26
7453 #endif
7454 #if defined(EXTI_RTSR_TR27)
7455 #define EXTI_RTSR_RT27 EXTI_RTSR_TR27
7456 #endif
7457 #if defined(EXTI_RTSR_TR28)
7458 #define EXTI_RTSR_RT28 EXTI_RTSR_TR28
7459 #endif
7460 #if defined(EXTI_RTSR_TR29)
7461 #define EXTI_RTSR_RT29 EXTI_RTSR_TR29
7462 #endif
7463 #if defined(EXTI_RTSR_TR30)
7464 #define EXTI_RTSR_RT30 EXTI_RTSR_TR30
7465 #endif
7466 #if defined(EXTI_RTSR_TR31)
7467 #define EXTI_RTSR_RT31 EXTI_RTSR_TR31
7468 #endif
7469 
7470 /******************  Bit definition for EXTI_FTSR register  *******************/
7471 #define EXTI_FTSR_TR0_Pos          (0U)
7472 #define EXTI_FTSR_TR0_Msk          (0x1UL << EXTI_FTSR_TR0_Pos)                 /*!< 0x00000001 */
7473 #define EXTI_FTSR_TR0              EXTI_FTSR_TR0_Msk                           /*!< Falling trigger event configuration bit of line 0 */
7474 #define EXTI_FTSR_TR1_Pos          (1U)
7475 #define EXTI_FTSR_TR1_Msk          (0x1UL << EXTI_FTSR_TR1_Pos)                 /*!< 0x00000002 */
7476 #define EXTI_FTSR_TR1              EXTI_FTSR_TR1_Msk                           /*!< Falling trigger event configuration bit of line 1 */
7477 #define EXTI_FTSR_TR2_Pos          (2U)
7478 #define EXTI_FTSR_TR2_Msk          (0x1UL << EXTI_FTSR_TR2_Pos)                 /*!< 0x00000004 */
7479 #define EXTI_FTSR_TR2              EXTI_FTSR_TR2_Msk                           /*!< Falling trigger event configuration bit of line 2 */
7480 #define EXTI_FTSR_TR3_Pos          (3U)
7481 #define EXTI_FTSR_TR3_Msk          (0x1UL << EXTI_FTSR_TR3_Pos)                 /*!< 0x00000008 */
7482 #define EXTI_FTSR_TR3              EXTI_FTSR_TR3_Msk                           /*!< Falling trigger event configuration bit of line 3 */
7483 #define EXTI_FTSR_TR4_Pos          (4U)
7484 #define EXTI_FTSR_TR4_Msk          (0x1UL << EXTI_FTSR_TR4_Pos)                 /*!< 0x00000010 */
7485 #define EXTI_FTSR_TR4              EXTI_FTSR_TR4_Msk                           /*!< Falling trigger event configuration bit of line 4 */
7486 #define EXTI_FTSR_TR5_Pos          (5U)
7487 #define EXTI_FTSR_TR5_Msk          (0x1UL << EXTI_FTSR_TR5_Pos)                 /*!< 0x00000020 */
7488 #define EXTI_FTSR_TR5              EXTI_FTSR_TR5_Msk                           /*!< Falling trigger event configuration bit of line 5 */
7489 #define EXTI_FTSR_TR6_Pos          (6U)
7490 #define EXTI_FTSR_TR6_Msk          (0x1UL << EXTI_FTSR_TR6_Pos)                 /*!< 0x00000040 */
7491 #define EXTI_FTSR_TR6              EXTI_FTSR_TR6_Msk                           /*!< Falling trigger event configuration bit of line 6 */
7492 #define EXTI_FTSR_TR7_Pos          (7U)
7493 #define EXTI_FTSR_TR7_Msk          (0x1UL << EXTI_FTSR_TR7_Pos)                 /*!< 0x00000080 */
7494 #define EXTI_FTSR_TR7              EXTI_FTSR_TR7_Msk                           /*!< Falling trigger event configuration bit of line 7 */
7495 #define EXTI_FTSR_TR8_Pos          (8U)
7496 #define EXTI_FTSR_TR8_Msk          (0x1UL << EXTI_FTSR_TR8_Pos)                 /*!< 0x00000100 */
7497 #define EXTI_FTSR_TR8              EXTI_FTSR_TR8_Msk                           /*!< Falling trigger event configuration bit of line 8 */
7498 #define EXTI_FTSR_TR9_Pos          (9U)
7499 #define EXTI_FTSR_TR9_Msk          (0x1UL << EXTI_FTSR_TR9_Pos)                 /*!< 0x00000200 */
7500 #define EXTI_FTSR_TR9              EXTI_FTSR_TR9_Msk                           /*!< Falling trigger event configuration bit of line 9 */
7501 #define EXTI_FTSR_TR10_Pos         (10U)
7502 #define EXTI_FTSR_TR10_Msk         (0x1UL << EXTI_FTSR_TR10_Pos)                /*!< 0x00000400 */
7503 #define EXTI_FTSR_TR10             EXTI_FTSR_TR10_Msk                          /*!< Falling trigger event configuration bit of line 10 */
7504 #define EXTI_FTSR_TR11_Pos         (11U)
7505 #define EXTI_FTSR_TR11_Msk         (0x1UL << EXTI_FTSR_TR11_Pos)                /*!< 0x00000800 */
7506 #define EXTI_FTSR_TR11             EXTI_FTSR_TR11_Msk                          /*!< Falling trigger event configuration bit of line 11 */
7507 #define EXTI_FTSR_TR12_Pos         (12U)
7508 #define EXTI_FTSR_TR12_Msk         (0x1UL << EXTI_FTSR_TR12_Pos)                /*!< 0x00001000 */
7509 #define EXTI_FTSR_TR12             EXTI_FTSR_TR12_Msk                          /*!< Falling trigger event configuration bit of line 12 */
7510 #define EXTI_FTSR_TR13_Pos         (13U)
7511 #define EXTI_FTSR_TR13_Msk         (0x1UL << EXTI_FTSR_TR13_Pos)                /*!< 0x00002000 */
7512 #define EXTI_FTSR_TR13             EXTI_FTSR_TR13_Msk                          /*!< Falling trigger event configuration bit of line 13 */
7513 #define EXTI_FTSR_TR14_Pos         (14U)
7514 #define EXTI_FTSR_TR14_Msk         (0x1UL << EXTI_FTSR_TR14_Pos)                /*!< 0x00004000 */
7515 #define EXTI_FTSR_TR14             EXTI_FTSR_TR14_Msk                          /*!< Falling trigger event configuration bit of line 14 */
7516 #define EXTI_FTSR_TR15_Pos         (15U)
7517 #define EXTI_FTSR_TR15_Msk         (0x1UL << EXTI_FTSR_TR15_Pos)                /*!< 0x00008000 */
7518 #define EXTI_FTSR_TR15             EXTI_FTSR_TR15_Msk                          /*!< Falling trigger event configuration bit of line 15 */
7519 #define EXTI_FTSR_TR16_Pos         (16U)
7520 #define EXTI_FTSR_TR16_Msk         (0x1UL << EXTI_FTSR_TR16_Pos)                /*!< 0x00010000 */
7521 #define EXTI_FTSR_TR16             EXTI_FTSR_TR16_Msk                          /*!< Falling trigger event configuration bit of line 16 */
7522 #define EXTI_FTSR_TR17_Pos         (17U)
7523 #define EXTI_FTSR_TR17_Msk         (0x1UL << EXTI_FTSR_TR17_Pos)                /*!< 0x00020000 */
7524 #define EXTI_FTSR_TR17             EXTI_FTSR_TR17_Msk                          /*!< Falling trigger event configuration bit of line 17 */
7525 #define EXTI_FTSR_TR19_Pos         (19U)
7526 #define EXTI_FTSR_TR19_Msk         (0x1UL << EXTI_FTSR_TR19_Pos)                /*!< 0x00080000 */
7527 #define EXTI_FTSR_TR19             EXTI_FTSR_TR19_Msk                          /*!< Falling trigger event configuration bit of line 19 */
7528 #define EXTI_FTSR_TR20_Pos         (20U)
7529 #define EXTI_FTSR_TR20_Msk         (0x1UL << EXTI_FTSR_TR20_Pos)                /*!< 0x00100000 */
7530 #define EXTI_FTSR_TR20             EXTI_FTSR_TR20_Msk                          /*!< Falling trigger event configuration bit of line 20 */
7531 #define EXTI_FTSR_TR21_Pos         (21U)
7532 #define EXTI_FTSR_TR21_Msk         (0x1UL << EXTI_FTSR_TR21_Pos)                /*!< 0x00200000 */
7533 #define EXTI_FTSR_TR21             EXTI_FTSR_TR21_Msk                          /*!< Falling trigger event configuration bit of line 21 */
7534 #define EXTI_FTSR_TR22_Pos         (22U)
7535 #define EXTI_FTSR_TR22_Msk         (0x1UL << EXTI_FTSR_TR22_Pos)                /*!< 0x00400000 */
7536 #define EXTI_FTSR_TR22             EXTI_FTSR_TR22_Msk                          /*!< Falling trigger event configuration bit of line 22 */
7537 #define EXTI_FTSR_TR29_Pos         (29U)
7538 #define EXTI_FTSR_TR29_Msk         (0x1UL << EXTI_FTSR_TR29_Pos)                /*!< 0x20000000 */
7539 #define EXTI_FTSR_TR29             EXTI_FTSR_TR29_Msk                          /*!< Falling trigger event configuration bit of line 29 */
7540 #define EXTI_FTSR_TR30_Pos         (30U)
7541 #define EXTI_FTSR_TR30_Msk         (0x1UL << EXTI_FTSR_TR30_Pos)                /*!< 0x40000000 */
7542 #define EXTI_FTSR_TR30             EXTI_FTSR_TR30_Msk                          /*!< Falling trigger event configuration bit of line 30 */
7543 #define EXTI_FTSR_TR31_Pos         (31U)
7544 #define EXTI_FTSR_TR31_Msk         (0x1UL << EXTI_FTSR_TR31_Pos)                /*!< 0x80000000 */
7545 #define EXTI_FTSR_TR31             EXTI_FTSR_TR31_Msk                          /*!< Falling trigger event configuration bit of line 31 */
7546 
7547 /* References Defines */
7548 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
7549 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
7550 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
7551 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
7552 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
7553 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
7554 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
7555 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
7556 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
7557 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
7558 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
7559 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
7560 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
7561 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
7562 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
7563 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
7564 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
7565 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
7566 #if defined(EXTI_FTSR_TR18)
7567 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
7568 #endif
7569 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
7570 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
7571 #if defined(EXTI_FTSR_TR21)
7572 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
7573 #endif
7574 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
7575 #if defined(EXTI_FTSR_TR23)
7576 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
7577 #endif
7578 #if defined(EXTI_FTSR_TR24)
7579 #define EXTI_FTSR_FT24 EXTI_FTSR_TR24
7580 #endif
7581 #if defined(EXTI_FTSR_TR25)
7582 #define EXTI_FTSR_FT25 EXTI_FTSR_TR25
7583 #endif
7584 #if defined(EXTI_FTSR_TR26)
7585 #define EXTI_FTSR_FT26 EXTI_FTSR_TR26
7586 #endif
7587 #if defined(EXTI_FTSR_TR27)
7588 #define EXTI_FTSR_FT27 EXTI_FTSR_TR27
7589 #endif
7590 #if defined(EXTI_FTSR_TR28)
7591 #define EXTI_FTSR_FT28 EXTI_FTSR_TR28
7592 #endif
7593 #if defined(EXTI_FTSR_TR29)
7594 #define EXTI_FTSR_FT29 EXTI_FTSR_TR29
7595 #endif
7596 #if defined(EXTI_FTSR_TR30)
7597 #define EXTI_FTSR_FT30 EXTI_FTSR_TR30
7598 #endif
7599 #if defined(EXTI_FTSR_TR31)
7600 #define EXTI_FTSR_FT31 EXTI_FTSR_TR31
7601 #endif
7602 
7603 /******************  Bit definition for EXTI_SWIER register  ******************/
7604 #define EXTI_SWIER_SWIER0_Pos      (0U)
7605 #define EXTI_SWIER_SWIER0_Msk      (0x1UL << EXTI_SWIER_SWIER0_Pos)             /*!< 0x00000001 */
7606 #define EXTI_SWIER_SWIER0          EXTI_SWIER_SWIER0_Msk                       /*!< Software Interrupt on line 0 */
7607 #define EXTI_SWIER_SWIER1_Pos      (1U)
7608 #define EXTI_SWIER_SWIER1_Msk      (0x1UL << EXTI_SWIER_SWIER1_Pos)             /*!< 0x00000002 */
7609 #define EXTI_SWIER_SWIER1          EXTI_SWIER_SWIER1_Msk                       /*!< Software Interrupt on line 1 */
7610 #define EXTI_SWIER_SWIER2_Pos      (2U)
7611 #define EXTI_SWIER_SWIER2_Msk      (0x1UL << EXTI_SWIER_SWIER2_Pos)             /*!< 0x00000004 */
7612 #define EXTI_SWIER_SWIER2          EXTI_SWIER_SWIER2_Msk                       /*!< Software Interrupt on line 2 */
7613 #define EXTI_SWIER_SWIER3_Pos      (3U)
7614 #define EXTI_SWIER_SWIER3_Msk      (0x1UL << EXTI_SWIER_SWIER3_Pos)             /*!< 0x00000008 */
7615 #define EXTI_SWIER_SWIER3          EXTI_SWIER_SWIER3_Msk                       /*!< Software Interrupt on line 3 */
7616 #define EXTI_SWIER_SWIER4_Pos      (4U)
7617 #define EXTI_SWIER_SWIER4_Msk      (0x1UL << EXTI_SWIER_SWIER4_Pos)             /*!< 0x00000010 */
7618 #define EXTI_SWIER_SWIER4          EXTI_SWIER_SWIER4_Msk                       /*!< Software Interrupt on line 4 */
7619 #define EXTI_SWIER_SWIER5_Pos      (5U)
7620 #define EXTI_SWIER_SWIER5_Msk      (0x1UL << EXTI_SWIER_SWIER5_Pos)             /*!< 0x00000020 */
7621 #define EXTI_SWIER_SWIER5          EXTI_SWIER_SWIER5_Msk                       /*!< Software Interrupt on line 5 */
7622 #define EXTI_SWIER_SWIER6_Pos      (6U)
7623 #define EXTI_SWIER_SWIER6_Msk      (0x1UL << EXTI_SWIER_SWIER6_Pos)             /*!< 0x00000040 */
7624 #define EXTI_SWIER_SWIER6          EXTI_SWIER_SWIER6_Msk                       /*!< Software Interrupt on line 6 */
7625 #define EXTI_SWIER_SWIER7_Pos      (7U)
7626 #define EXTI_SWIER_SWIER7_Msk      (0x1UL << EXTI_SWIER_SWIER7_Pos)             /*!< 0x00000080 */
7627 #define EXTI_SWIER_SWIER7          EXTI_SWIER_SWIER7_Msk                       /*!< Software Interrupt on line 7 */
7628 #define EXTI_SWIER_SWIER8_Pos      (8U)
7629 #define EXTI_SWIER_SWIER8_Msk      (0x1UL << EXTI_SWIER_SWIER8_Pos)             /*!< 0x00000100 */
7630 #define EXTI_SWIER_SWIER8          EXTI_SWIER_SWIER8_Msk                       /*!< Software Interrupt on line 8 */
7631 #define EXTI_SWIER_SWIER9_Pos      (9U)
7632 #define EXTI_SWIER_SWIER9_Msk      (0x1UL << EXTI_SWIER_SWIER9_Pos)             /*!< 0x00000200 */
7633 #define EXTI_SWIER_SWIER9          EXTI_SWIER_SWIER9_Msk                       /*!< Software Interrupt on line 9 */
7634 #define EXTI_SWIER_SWIER10_Pos     (10U)
7635 #define EXTI_SWIER_SWIER10_Msk     (0x1UL << EXTI_SWIER_SWIER10_Pos)            /*!< 0x00000400 */
7636 #define EXTI_SWIER_SWIER10         EXTI_SWIER_SWIER10_Msk                      /*!< Software Interrupt on line 10 */
7637 #define EXTI_SWIER_SWIER11_Pos     (11U)
7638 #define EXTI_SWIER_SWIER11_Msk     (0x1UL << EXTI_SWIER_SWIER11_Pos)            /*!< 0x00000800 */
7639 #define EXTI_SWIER_SWIER11         EXTI_SWIER_SWIER11_Msk                      /*!< Software Interrupt on line 11 */
7640 #define EXTI_SWIER_SWIER12_Pos     (12U)
7641 #define EXTI_SWIER_SWIER12_Msk     (0x1UL << EXTI_SWIER_SWIER12_Pos)            /*!< 0x00001000 */
7642 #define EXTI_SWIER_SWIER12         EXTI_SWIER_SWIER12_Msk                      /*!< Software Interrupt on line 12 */
7643 #define EXTI_SWIER_SWIER13_Pos     (13U)
7644 #define EXTI_SWIER_SWIER13_Msk     (0x1UL << EXTI_SWIER_SWIER13_Pos)            /*!< 0x00002000 */
7645 #define EXTI_SWIER_SWIER13         EXTI_SWIER_SWIER13_Msk                      /*!< Software Interrupt on line 13 */
7646 #define EXTI_SWIER_SWIER14_Pos     (14U)
7647 #define EXTI_SWIER_SWIER14_Msk     (0x1UL << EXTI_SWIER_SWIER14_Pos)            /*!< 0x00004000 */
7648 #define EXTI_SWIER_SWIER14         EXTI_SWIER_SWIER14_Msk                      /*!< Software Interrupt on line 14 */
7649 #define EXTI_SWIER_SWIER15_Pos     (15U)
7650 #define EXTI_SWIER_SWIER15_Msk     (0x1UL << EXTI_SWIER_SWIER15_Pos)            /*!< 0x00008000 */
7651 #define EXTI_SWIER_SWIER15         EXTI_SWIER_SWIER15_Msk                      /*!< Software Interrupt on line 15 */
7652 #define EXTI_SWIER_SWIER16_Pos     (16U)
7653 #define EXTI_SWIER_SWIER16_Msk     (0x1UL << EXTI_SWIER_SWIER16_Pos)            /*!< 0x00010000 */
7654 #define EXTI_SWIER_SWIER16         EXTI_SWIER_SWIER16_Msk                      /*!< Software Interrupt on line 16 */
7655 #define EXTI_SWIER_SWIER17_Pos     (17U)
7656 #define EXTI_SWIER_SWIER17_Msk     (0x1UL << EXTI_SWIER_SWIER17_Pos)            /*!< 0x00020000 */
7657 #define EXTI_SWIER_SWIER17         EXTI_SWIER_SWIER17_Msk                      /*!< Software Interrupt on line 17 */
7658 #define EXTI_SWIER_SWIER19_Pos     (19U)
7659 #define EXTI_SWIER_SWIER19_Msk     (0x1UL << EXTI_SWIER_SWIER19_Pos)            /*!< 0x00080000 */
7660 #define EXTI_SWIER_SWIER19         EXTI_SWIER_SWIER19_Msk                      /*!< Software Interrupt on line 19 */
7661 #define EXTI_SWIER_SWIER20_Pos     (20U)
7662 #define EXTI_SWIER_SWIER20_Msk     (0x1UL << EXTI_SWIER_SWIER20_Pos)            /*!< 0x00100000 */
7663 #define EXTI_SWIER_SWIER20         EXTI_SWIER_SWIER20_Msk                      /*!< Software Interrupt on line 20 */
7664 #define EXTI_SWIER_SWIER21_Pos     (21U)
7665 #define EXTI_SWIER_SWIER21_Msk     (0x1UL << EXTI_SWIER_SWIER21_Pos)            /*!< 0x00200000 */
7666 #define EXTI_SWIER_SWIER21         EXTI_SWIER_SWIER21_Msk                      /*!< Software Interrupt on line 21 */
7667 #define EXTI_SWIER_SWIER22_Pos     (22U)
7668 #define EXTI_SWIER_SWIER22_Msk     (0x1UL << EXTI_SWIER_SWIER22_Pos)            /*!< 0x00400000 */
7669 #define EXTI_SWIER_SWIER22         EXTI_SWIER_SWIER22_Msk                      /*!< Software Interrupt on line 22 */
7670 #define EXTI_SWIER_SWIER29_Pos     (29U)
7671 #define EXTI_SWIER_SWIER29_Msk     (0x1UL << EXTI_SWIER_SWIER29_Pos)            /*!< 0x20000000 */
7672 #define EXTI_SWIER_SWIER29         EXTI_SWIER_SWIER29_Msk                      /*!< Software Interrupt on line 29 */
7673 #define EXTI_SWIER_SWIER30_Pos     (30U)
7674 #define EXTI_SWIER_SWIER30_Msk     (0x1UL << EXTI_SWIER_SWIER30_Pos)            /*!< 0x40000000 */
7675 #define EXTI_SWIER_SWIER30         EXTI_SWIER_SWIER30_Msk                      /*!< Software Interrupt on line 30 */
7676 #define EXTI_SWIER_SWIER31_Pos     (31U)
7677 #define EXTI_SWIER_SWIER31_Msk     (0x1UL << EXTI_SWIER_SWIER31_Pos)            /*!< 0x80000000 */
7678 #define EXTI_SWIER_SWIER31         EXTI_SWIER_SWIER31_Msk                      /*!< Software Interrupt on line 31 */
7679 
7680 /* References Defines */
7681 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
7682 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
7683 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
7684 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
7685 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
7686 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
7687 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
7688 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
7689 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
7690 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
7691 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
7692 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
7693 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
7694 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
7695 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
7696 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
7697 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
7698 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
7699 #if defined(EXTI_SWIER_SWIER18)
7700 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
7701 #endif
7702 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
7703 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
7704 #if defined(EXTI_SWIER_SWIER21)
7705 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
7706 #endif
7707 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
7708 #if defined(EXTI_SWIER_SWIER23)
7709 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
7710 #endif
7711 #if defined(EXTI_SWIER_SWIER24)
7712 #define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
7713 #endif
7714 #if defined(EXTI_SWIER_SWIER25)
7715 #define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
7716 #endif
7717 #if defined(EXTI_SWIER_SWIER26)
7718 #define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
7719 #endif
7720 #if defined(EXTI_SWIER_SWIER27)
7721 #define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
7722 #endif
7723 #if defined(EXTI_SWIER_SWIER28)
7724 #define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
7725 #endif
7726 #if defined(EXTI_SWIER_SWIER29)
7727 #define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
7728 #endif
7729 #if defined(EXTI_SWIER_SWIER30)
7730 #define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
7731 #endif
7732 #if defined(EXTI_SWIER_SWIER31)
7733 #define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
7734 #endif
7735 
7736 /*******************  Bit definition for EXTI_PR register  ********************/
7737 #define EXTI_PR_PR0_Pos            (0U)
7738 #define EXTI_PR_PR0_Msk            (0x1UL << EXTI_PR_PR0_Pos)                   /*!< 0x00000001 */
7739 #define EXTI_PR_PR0                EXTI_PR_PR0_Msk                             /*!< Pending bit for line 0 */
7740 #define EXTI_PR_PR1_Pos            (1U)
7741 #define EXTI_PR_PR1_Msk            (0x1UL << EXTI_PR_PR1_Pos)                   /*!< 0x00000002 */
7742 #define EXTI_PR_PR1                EXTI_PR_PR1_Msk                             /*!< Pending bit for line 1 */
7743 #define EXTI_PR_PR2_Pos            (2U)
7744 #define EXTI_PR_PR2_Msk            (0x1UL << EXTI_PR_PR2_Pos)                   /*!< 0x00000004 */
7745 #define EXTI_PR_PR2                EXTI_PR_PR2_Msk                             /*!< Pending bit for line 2 */
7746 #define EXTI_PR_PR3_Pos            (3U)
7747 #define EXTI_PR_PR3_Msk            (0x1UL << EXTI_PR_PR3_Pos)                   /*!< 0x00000008 */
7748 #define EXTI_PR_PR3                EXTI_PR_PR3_Msk                             /*!< Pending bit for line 3 */
7749 #define EXTI_PR_PR4_Pos            (4U)
7750 #define EXTI_PR_PR4_Msk            (0x1UL << EXTI_PR_PR4_Pos)                   /*!< 0x00000010 */
7751 #define EXTI_PR_PR4                EXTI_PR_PR4_Msk                             /*!< Pending bit for line 4 */
7752 #define EXTI_PR_PR5_Pos            (5U)
7753 #define EXTI_PR_PR5_Msk            (0x1UL << EXTI_PR_PR5_Pos)                   /*!< 0x00000020 */
7754 #define EXTI_PR_PR5                EXTI_PR_PR5_Msk                             /*!< Pending bit for line 5 */
7755 #define EXTI_PR_PR6_Pos            (6U)
7756 #define EXTI_PR_PR6_Msk            (0x1UL << EXTI_PR_PR6_Pos)                   /*!< 0x00000040 */
7757 #define EXTI_PR_PR6                EXTI_PR_PR6_Msk                             /*!< Pending bit for line 6 */
7758 #define EXTI_PR_PR7_Pos            (7U)
7759 #define EXTI_PR_PR7_Msk            (0x1UL << EXTI_PR_PR7_Pos)                   /*!< 0x00000080 */
7760 #define EXTI_PR_PR7                EXTI_PR_PR7_Msk                             /*!< Pending bit for line 7 */
7761 #define EXTI_PR_PR8_Pos            (8U)
7762 #define EXTI_PR_PR8_Msk            (0x1UL << EXTI_PR_PR8_Pos)                   /*!< 0x00000100 */
7763 #define EXTI_PR_PR8                EXTI_PR_PR8_Msk                             /*!< Pending bit for line 8 */
7764 #define EXTI_PR_PR9_Pos            (9U)
7765 #define EXTI_PR_PR9_Msk            (0x1UL << EXTI_PR_PR9_Pos)                   /*!< 0x00000200 */
7766 #define EXTI_PR_PR9                EXTI_PR_PR9_Msk                             /*!< Pending bit for line 9 */
7767 #define EXTI_PR_PR10_Pos           (10U)
7768 #define EXTI_PR_PR10_Msk           (0x1UL << EXTI_PR_PR10_Pos)                  /*!< 0x00000400 */
7769 #define EXTI_PR_PR10               EXTI_PR_PR10_Msk                            /*!< Pending bit for line 10 */
7770 #define EXTI_PR_PR11_Pos           (11U)
7771 #define EXTI_PR_PR11_Msk           (0x1UL << EXTI_PR_PR11_Pos)                  /*!< 0x00000800 */
7772 #define EXTI_PR_PR11               EXTI_PR_PR11_Msk                            /*!< Pending bit for line 11 */
7773 #define EXTI_PR_PR12_Pos           (12U)
7774 #define EXTI_PR_PR12_Msk           (0x1UL << EXTI_PR_PR12_Pos)                  /*!< 0x00001000 */
7775 #define EXTI_PR_PR12               EXTI_PR_PR12_Msk                            /*!< Pending bit for line 12 */
7776 #define EXTI_PR_PR13_Pos           (13U)
7777 #define EXTI_PR_PR13_Msk           (0x1UL << EXTI_PR_PR13_Pos)                  /*!< 0x00002000 */
7778 #define EXTI_PR_PR13               EXTI_PR_PR13_Msk                            /*!< Pending bit for line 13 */
7779 #define EXTI_PR_PR14_Pos           (14U)
7780 #define EXTI_PR_PR14_Msk           (0x1UL << EXTI_PR_PR14_Pos)                  /*!< 0x00004000 */
7781 #define EXTI_PR_PR14               EXTI_PR_PR14_Msk                            /*!< Pending bit for line 14 */
7782 #define EXTI_PR_PR15_Pos           (15U)
7783 #define EXTI_PR_PR15_Msk           (0x1UL << EXTI_PR_PR15_Pos)                  /*!< 0x00008000 */
7784 #define EXTI_PR_PR15               EXTI_PR_PR15_Msk                            /*!< Pending bit for line 15 */
7785 #define EXTI_PR_PR16_Pos           (16U)
7786 #define EXTI_PR_PR16_Msk           (0x1UL << EXTI_PR_PR16_Pos)                  /*!< 0x00010000 */
7787 #define EXTI_PR_PR16               EXTI_PR_PR16_Msk                            /*!< Pending bit for line 16 */
7788 #define EXTI_PR_PR17_Pos           (17U)
7789 #define EXTI_PR_PR17_Msk           (0x1UL << EXTI_PR_PR17_Pos)                  /*!< 0x00020000 */
7790 #define EXTI_PR_PR17               EXTI_PR_PR17_Msk                            /*!< Pending bit for line 17 */
7791 #define EXTI_PR_PR19_Pos           (19U)
7792 #define EXTI_PR_PR19_Msk           (0x1UL << EXTI_PR_PR19_Pos)                  /*!< 0x00080000 */
7793 #define EXTI_PR_PR19               EXTI_PR_PR19_Msk                            /*!< Pending bit for line 19 */
7794 #define EXTI_PR_PR20_Pos           (20U)
7795 #define EXTI_PR_PR20_Msk           (0x1UL << EXTI_PR_PR20_Pos)                  /*!< 0x00100000 */
7796 #define EXTI_PR_PR20               EXTI_PR_PR20_Msk                            /*!< Pending bit for line 20 */
7797 #define EXTI_PR_PR21_Pos           (21U)
7798 #define EXTI_PR_PR21_Msk           (0x1UL << EXTI_PR_PR21_Pos)                  /*!< 0x00200000 */
7799 #define EXTI_PR_PR21               EXTI_PR_PR21_Msk                            /*!< Pending bit for line 21 */
7800 #define EXTI_PR_PR22_Pos           (22U)
7801 #define EXTI_PR_PR22_Msk           (0x1UL << EXTI_PR_PR22_Pos)                  /*!< 0x00400000 */
7802 #define EXTI_PR_PR22               EXTI_PR_PR22_Msk                            /*!< Pending bit for line 22 */
7803 #define EXTI_PR_PR29_Pos           (29U)
7804 #define EXTI_PR_PR29_Msk           (0x1UL << EXTI_PR_PR29_Pos)                  /*!< 0x20000000 */
7805 #define EXTI_PR_PR29               EXTI_PR_PR29_Msk                            /*!< Pending bit for line 29 */
7806 #define EXTI_PR_PR30_Pos           (30U)
7807 #define EXTI_PR_PR30_Msk           (0x1UL << EXTI_PR_PR30_Pos)                  /*!< 0x40000000 */
7808 #define EXTI_PR_PR30               EXTI_PR_PR30_Msk                            /*!< Pending bit for line 30 */
7809 #define EXTI_PR_PR31_Pos           (31U)
7810 #define EXTI_PR_PR31_Msk           (0x1UL << EXTI_PR_PR31_Pos)                  /*!< 0x80000000 */
7811 #define EXTI_PR_PR31               EXTI_PR_PR31_Msk                            /*!< Pending bit for line 31 */
7812 
7813 /* References Defines */
7814 #define EXTI_PR_PIF0 EXTI_PR_PR0
7815 #define EXTI_PR_PIF1 EXTI_PR_PR1
7816 #define EXTI_PR_PIF2 EXTI_PR_PR2
7817 #define EXTI_PR_PIF3 EXTI_PR_PR3
7818 #define EXTI_PR_PIF4 EXTI_PR_PR4
7819 #define EXTI_PR_PIF5 EXTI_PR_PR5
7820 #define EXTI_PR_PIF6 EXTI_PR_PR6
7821 #define EXTI_PR_PIF6 EXTI_PR_PR6
7822 #define EXTI_PR_PIF7 EXTI_PR_PR7
7823 #define EXTI_PR_PIF8 EXTI_PR_PR8
7824 #define EXTI_PR_PIF9 EXTI_PR_PR9
7825 #define EXTI_PR_PIF10 EXTI_PR_PR10
7826 #define EXTI_PR_PIF11 EXTI_PR_PR11
7827 #define EXTI_PR_PIF12 EXTI_PR_PR12
7828 #define EXTI_PR_PIF13 EXTI_PR_PR13
7829 #define EXTI_PR_PIF14 EXTI_PR_PR14
7830 #define EXTI_PR_PIF15 EXTI_PR_PR15
7831 #define EXTI_PR_PIF16 EXTI_PR_PR16
7832 #define EXTI_PR_PIF17 EXTI_PR_PR17
7833 #if defined(EXTI_PR_PR18)
7834 #define EXTI_PR_PIF18 EXTI_PR_PR18
7835 #endif
7836 #define EXTI_PR_PIF19 EXTI_PR_PR19
7837 #define EXTI_PR_PIF20 EXTI_PR_PR20
7838 #if defined(EXTI_PR_PR21)
7839 #define EXTI_PR_PIF21 EXTI_PR_PR21
7840 #endif
7841 #define EXTI_PR_PIF22 EXTI_PR_PR22
7842 #if defined(EXTI_PR_PR23)
7843 #define EXTI_PR_PIF23 EXTI_PR_PR23
7844 #endif
7845 #if defined(EXTI_PR_PR24)
7846 #define EXTI_PR_PIF24 EXTI_PR_PR24
7847 #endif
7848 #if defined(EXTI_PR_PR25)
7849 #define EXTI_PR_PIF25 EXTI_PR_PR25
7850 #endif
7851 #if defined(EXTI_PR_PR26)
7852 #define EXTI_PR_PIF26 EXTI_PR_PR26
7853 #endif
7854 #if defined(EXTI_PR_PR27)
7855 #define EXTI_PR_PIF27 EXTI_PR_PR27
7856 #endif
7857 #if defined(EXTI_PR_PR28)
7858 #define EXTI_PR_PIF28 EXTI_PR_PR28
7859 #endif
7860 #if defined(EXTI_PR_PR29)
7861 #define EXTI_PR_PIF29 EXTI_PR_PR29
7862 #endif
7863 #if defined(EXTI_PR_PR30)
7864 #define EXTI_PR_PIF30 EXTI_PR_PR30
7865 #endif
7866 #if defined(EXTI_PR_PR31)
7867 #define EXTI_PR_PIF31 EXTI_PR_PR31
7868 #endif
7869 
7870 #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
7871 
7872 /*******************  Bit definition for EXTI_IMR2 register  ******************/
7873 #define EXTI_IMR2_MR32_Pos         (0U)
7874 #define EXTI_IMR2_MR32_Msk         (0x1UL << EXTI_IMR2_MR32_Pos)                /*!< 0x00000001 */
7875 #define EXTI_IMR2_MR32             EXTI_IMR2_MR32_Msk                          /*!< Interrupt Mask on line 32 */
7876 #define EXTI_IMR2_MR33_Pos         (1U)
7877 #define EXTI_IMR2_MR33_Msk         (0x1UL << EXTI_IMR2_MR33_Pos)                /*!< 0x00000002 */
7878 #define EXTI_IMR2_MR33             EXTI_IMR2_MR33_Msk                          /*!< Interrupt Mask on line 33 */
7879 #define EXTI_IMR2_MR34_Pos         (2U)
7880 #define EXTI_IMR2_MR34_Msk         (0x1UL << EXTI_IMR2_MR34_Pos)                /*!< 0x00000004 */
7881 #define EXTI_IMR2_MR34             EXTI_IMR2_MR34_Msk                          /*!< Interrupt Mask on line 34 */
7882 #define EXTI_IMR2_MR35_Pos         (3U)
7883 #define EXTI_IMR2_MR35_Msk         (0x1UL << EXTI_IMR2_MR35_Pos)                /*!< 0x00000008 */
7884 #define EXTI_IMR2_MR35             EXTI_IMR2_MR35_Msk                          /*!< Interrupt Mask on line 35 */
7885 
7886 /* References Defines */
7887 
7888 #define EXTI_IMR2_IM32 EXTI_IMR2_MR32
7889 #if defined(EXTI_IMR2_MR33)
7890 #define EXTI_IMR2_IM33 EXTI_IMR2_MR33
7891 #endif
7892 #if defined(EXTI_IMR2_MR34)
7893 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34
7894 #endif
7895 #if defined(EXTI_IMR2_MR35)
7896 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
7897 #endif
7898 
7899 #if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7900 #define EXTI_IMR2_IM_Pos           (0U)
7901 #define EXTI_IMR2_IM_Msk           (0xFUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
7902 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7903 #elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7904 #define EXTI_IMR2_IM_Pos           (0U)
7905 #define EXTI_IMR2_IM_Msk           (0xDUL << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */
7906 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7907 #else
7908 #define EXTI_IMR2_IM_Pos           (0U)
7909 #define EXTI_IMR2_IM_Msk           (0x1UL << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */
7910 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk
7911 #endif
7912 
7913 /*******************  Bit definition for EXTI_EMR2 ****************************/
7914 #define EXTI_EMR2_MR32_Pos         (0U)
7915 #define EXTI_EMR2_MR32_Msk         (0x1UL << EXTI_EMR2_MR32_Pos)                /*!< 0x00000001 */
7916 #define EXTI_EMR2_MR32             EXTI_EMR2_MR32_Msk                          /*!< Event Mask on line 32 */
7917 #define EXTI_EMR2_MR33_Pos         (1U)
7918 #define EXTI_EMR2_MR33_Msk         (0x1UL << EXTI_EMR2_MR33_Pos)                /*!< 0x00000002 */
7919 #define EXTI_EMR2_MR33             EXTI_EMR2_MR33_Msk                          /*!< Event Mask on line 33 */
7920 #define EXTI_EMR2_MR34_Pos         (2U)
7921 #define EXTI_EMR2_MR34_Msk         (0x1UL << EXTI_EMR2_MR34_Pos)                /*!< 0x00000004 */
7922 #define EXTI_EMR2_MR34             EXTI_EMR2_MR34_Msk                          /*!< Event Mask on line 34 */
7923 #define EXTI_EMR2_MR35_Pos         (3U)
7924 #define EXTI_EMR2_MR35_Msk         (0x1UL << EXTI_EMR2_MR35_Pos)                /*!< 0x00000008 */
7925 #define EXTI_EMR2_MR35             EXTI_EMR2_MR35_Msk                          /*!< Event Mask on line 34 */
7926 
7927 /* References Defines */
7928 #define EXTI_EMR2_EM32 EXTI_EMR2_MR32
7929 #if defined(EXTI_EMR2_MR33)
7930 #define EXTI_EMR2_EM33 EXTI_EMR2_MR33
7931 #endif
7932 #if defined(EXTI_EMR2_MR34)
7933 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
7934 #endif
7935 #if defined(EXTI_EMR2_MR35)
7936 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
7937 #endif
7938 
7939 #if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7940 #define EXTI_EMR2_EM_Pos           (0U)
7941 #define EXTI_EMR2_EM_Msk           (0xFUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
7942 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7943 #elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
7944 #define EXTI_EMR2_EM_Pos           (0U)
7945 #define EXTI_EMR2_EM_Msk           (0xDUL << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */
7946 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7947 #else
7948 #define EXTI_EMR2_EM_Pos           (0U)
7949 #define EXTI_EMR2_EM_Msk           (0x1UL << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */
7950 #define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk
7951 #endif
7952 
7953 /******************  Bit definition for EXTI_RTSR2 register ********************/
7954 #define EXTI_RTSR2_TR32_Pos        (0U)
7955 #define EXTI_RTSR2_TR32_Msk        (0x1UL << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
7956 #define EXTI_RTSR2_TR32            EXTI_RTSR2_TR32_Msk                         /*!< Rising trigger event configuration bit of line 32 */
7957 #define EXTI_RTSR2_TR33_Pos        (1U)
7958 #define EXTI_RTSR2_TR33_Msk        (0x1UL << EXTI_RTSR2_TR33_Pos)               /*!< 0x00000002 */
7959 #define EXTI_RTSR2_TR33            EXTI_RTSR2_TR33_Msk                         /*!< Rising trigger event configuration bit of line 33 */
7960 
7961 /* References Defines */
7962 #define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
7963 #if defined(EXTI_RTSR2_TR33)
7964 #define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
7965 #endif
7966 #if defined(EXTI_RTSR2_TR34)
7967 #define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
7968 #endif
7969 #if defined(EXTI_RTSR2_TR35)
7970 #define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
7971 #endif
7972 
7973 /******************  Bit definition for EXTI_FTSR2 register  ******************/
7974 #define EXTI_FTSR2_TR32_Pos        (0U)
7975 #define EXTI_FTSR2_TR32_Msk        (0x1UL << EXTI_FTSR2_TR32_Pos)               /*!< 0x00000001 */
7976 #define EXTI_FTSR2_TR32            EXTI_FTSR2_TR32_Msk                         /*!< Falling trigger event configuration bit of line 32 */
7977 #define EXTI_FTSR2_TR33_Pos        (1U)
7978 #define EXTI_FTSR2_TR33_Msk        (0x1UL << EXTI_FTSR2_TR33_Pos)               /*!< 0x00000002 */
7979 #define EXTI_FTSR2_TR33            EXTI_FTSR2_TR33_Msk                         /*!< Falling trigger event configuration bit of line 33 */
7980 
7981 /* References Defines */
7982 #define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
7983 #if defined(EXTI_FTSR2_TR33)
7984 #define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
7985 #endif
7986 #if defined(EXTI_FTSR2_TR34)
7987 #define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
7988 #endif
7989 #if defined(EXTI_FTSR2_TR35)
7990 #define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
7991 #endif
7992 
7993 /******************  Bit definition for EXTI_SWIER2 register  *****************/
7994 #define EXTI_SWIER2_SWIER32_Pos    (0U)
7995 #define EXTI_SWIER2_SWIER32_Msk    (0x1UL << EXTI_SWIER2_SWIER32_Pos)           /*!< 0x00000001 */
7996 #define EXTI_SWIER2_SWIER32        EXTI_SWIER2_SWIER32_Msk                     /*!< Software Interrupt on line 32 */
7997 #define EXTI_SWIER2_SWIER33_Pos    (1U)
7998 #define EXTI_SWIER2_SWIER33_Msk    (0x1UL << EXTI_SWIER2_SWIER33_Pos)           /*!< 0x00000002 */
7999 #define EXTI_SWIER2_SWIER33        EXTI_SWIER2_SWIER33_Msk                     /*!< Software Interrupt on line 33 */
8000 
8001 /* References Defines */
8002 #define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
8003 #if defined(EXTI_SWIER2_SWIER33)
8004 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
8005 #endif
8006 #if defined(EXTI_SWIER2_SWIER34)
8007 #define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
8008 #endif
8009 #if defined(EXTI_SWIER2_SWIER35)
8010 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
8011 #endif
8012 
8013 /*******************  Bit definition for EXTI_PR2 register  *******************/
8014 #define EXTI_PR2_PR32_Pos          (0U)
8015 #define EXTI_PR2_PR32_Msk          (0x1UL << EXTI_PR2_PR32_Pos)                 /*!< 0x00000001 */
8016 #define EXTI_PR2_PR32              EXTI_PR2_PR32_Msk                           /*!< Pending bit for line 32 */
8017 #define EXTI_PR2_PR33_Pos          (1U)
8018 #define EXTI_PR2_PR33_Msk          (0x1UL << EXTI_PR2_PR33_Pos)                 /*!< 0x00000002 */
8019 #define EXTI_PR2_PR33              EXTI_PR2_PR33_Msk                           /*!< Pending bit for line 33 */
8020 
8021 /* References Defines */
8022 #define EXTI_PR2_PIF32 EXTI_PR2_PR32
8023 #if defined(EXTI_PR2_PR33)
8024 #define EXTI_PR2_PIF33 EXTI_PR2_PR33
8025 #endif
8026 #if defined(EXTI_PR2_PR34)
8027 #define EXTI_PR2_PIF34 EXTI_PR2_PR34
8028 #endif
8029 #if defined(EXTI_PR2_PR35)
8030 #define EXTI_PR2_PIF35 EXTI_PR2_PR35
8031 #endif
8032 
8033 
8034 /******************************************************************************/
8035 /*                                                                            */
8036 /*                                    FLASH                                   */
8037 /*                                                                            */
8038 /******************************************************************************/
8039 /*******************  Bit definition for FLASH_ACR register  ******************/
8040 #define FLASH_ACR_LATENCY_Pos                (0U)
8041 #define FLASH_ACR_LATENCY_Msk                (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
8042 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< LATENCY[2:0] bits (Latency) */
8043 #define FLASH_ACR_LATENCY_0                  (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
8044 #define FLASH_ACR_LATENCY_1                  (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
8045 #define FLASH_ACR_LATENCY_2                  (0x4UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000004 */
8046 
8047 #define FLASH_ACR_HLFCYA_Pos                 (3U)
8048 #define FLASH_ACR_HLFCYA_Msk                 (0x1UL << FLASH_ACR_HLFCYA_Pos)    /*!< 0x00000008 */
8049 #define FLASH_ACR_HLFCYA                     FLASH_ACR_HLFCYA_Msk              /*!< Flash Half Cycle Access Enable */
8050 #define FLASH_ACR_PRFTBE_Pos                 (4U)
8051 #define FLASH_ACR_PRFTBE_Msk                 (0x1UL << FLASH_ACR_PRFTBE_Pos)    /*!< 0x00000010 */
8052 #define FLASH_ACR_PRFTBE                     FLASH_ACR_PRFTBE_Msk              /*!< Prefetch Buffer Enable */
8053 #define FLASH_ACR_PRFTBS_Pos                 (5U)
8054 #define FLASH_ACR_PRFTBS_Msk                 (0x1UL << FLASH_ACR_PRFTBS_Pos)    /*!< 0x00000020 */
8055 #define FLASH_ACR_PRFTBS                     FLASH_ACR_PRFTBS_Msk              /*!< Prefetch Buffer Status */
8056 
8057 /******************  Bit definition for FLASH_KEYR register  ******************/
8058 #define FLASH_KEYR_FKEYR_Pos                 (0U)
8059 #define FLASH_KEYR_FKEYR_Msk                 (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
8060 #define FLASH_KEYR_FKEYR                     FLASH_KEYR_FKEYR_Msk              /*!< FPEC Key */
8061 
8062 #define RDP_KEY_Pos    (0U)
8063 #define RDP_KEY_Msk    (0xA5UL << RDP_KEY_Pos)                                  /*!< 0x000000A5 */
8064 #define RDP_KEY        RDP_KEY_Msk                                             /*!< RDP Key */
8065 #define FLASH_KEY1_Pos                       (0U)
8066 #define FLASH_KEY1_Msk                       (0x45670123UL << FLASH_KEY1_Pos)   /*!< 0x45670123 */
8067 #define FLASH_KEY1                           FLASH_KEY1_Msk                    /*!< FPEC Key1 */
8068 #define FLASH_KEY2_Pos                       (0U)
8069 #define FLASH_KEY2_Msk                       (0xCDEF89ABUL << FLASH_KEY2_Pos)   /*!< 0xCDEF89AB */
8070 #define FLASH_KEY2                           FLASH_KEY2_Msk                    /*!< FPEC Key2 */
8071 
8072 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
8073 #define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)
8074 #define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
8075 #define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option Byte Key */
8076 
8077 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
8078 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
8079 
8080 /******************  Bit definition for FLASH_SR register  *******************/
8081 #define FLASH_SR_BSY_Pos                     (0U)
8082 #define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
8083 #define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
8084 #define FLASH_SR_PGERR_Pos                   (2U)
8085 #define FLASH_SR_PGERR_Msk                   (0x1UL << FLASH_SR_PGERR_Pos)      /*!< 0x00000004 */
8086 #define FLASH_SR_PGERR                       FLASH_SR_PGERR_Msk                /*!< Programming Error */
8087 #define FLASH_SR_WRPERR_Pos                  (4U)
8088 #define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
8089 #define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write Protection Error */
8090 #define FLASH_SR_EOP_Pos                     (5U)
8091 #define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000020 */
8092 #define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End of operation */
8093 
8094 /*******************  Bit definition for FLASH_CR register  *******************/
8095 #define FLASH_CR_PG_Pos                      (0U)
8096 #define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
8097 #define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Programming */
8098 #define FLASH_CR_PER_Pos                     (1U)
8099 #define FLASH_CR_PER_Msk                     (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
8100 #define FLASH_CR_PER                         FLASH_CR_PER_Msk                  /*!< Page Erase */
8101 #define FLASH_CR_MER_Pos                     (2U)
8102 #define FLASH_CR_MER_Msk                     (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
8103 #define FLASH_CR_MER                         FLASH_CR_MER_Msk                  /*!< Mass Erase */
8104 #define FLASH_CR_OPTPG_Pos                   (4U)
8105 #define FLASH_CR_OPTPG_Msk                   (0x1UL << FLASH_CR_OPTPG_Pos)      /*!< 0x00000010 */
8106 #define FLASH_CR_OPTPG                       FLASH_CR_OPTPG_Msk                /*!< Option Byte Programming */
8107 #define FLASH_CR_OPTER_Pos                   (5U)
8108 #define FLASH_CR_OPTER_Msk                   (0x1UL << FLASH_CR_OPTER_Pos)      /*!< 0x00000020 */
8109 #define FLASH_CR_OPTER                       FLASH_CR_OPTER_Msk                /*!< Option Byte Erase */
8110 #define FLASH_CR_STRT_Pos                    (6U)
8111 #define FLASH_CR_STRT_Msk                    (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00000040 */
8112 #define FLASH_CR_STRT                        FLASH_CR_STRT_Msk                 /*!< Start */
8113 #define FLASH_CR_LOCK_Pos                    (7U)
8114 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x00000080 */
8115 #define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Lock */
8116 #define FLASH_CR_OPTWRE_Pos                  (9U)
8117 #define FLASH_CR_OPTWRE_Msk                  (0x1UL << FLASH_CR_OPTWRE_Pos)     /*!< 0x00000200 */
8118 #define FLASH_CR_OPTWRE                      FLASH_CR_OPTWRE_Msk               /*!< Option Bytes Write Enable */
8119 #define FLASH_CR_ERRIE_Pos                   (10U)
8120 #define FLASH_CR_ERRIE_Msk                   (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x00000400 */
8121 #define FLASH_CR_ERRIE                       FLASH_CR_ERRIE_Msk                /*!< Error Interrupt Enable */
8122 #define FLASH_CR_EOPIE_Pos                   (12U)
8123 #define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x00001000 */
8124 #define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End of operation interrupt enable */
8125 #define FLASH_CR_OBL_LAUNCH_Pos              (13U)
8126 #define FLASH_CR_OBL_LAUNCH_Msk              (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
8127 #define FLASH_CR_OBL_LAUNCH                  FLASH_CR_OBL_LAUNCH_Msk           /*!< OptionBytes Loader Launch */
8128 
8129 /*******************  Bit definition for FLASH_AR register  *******************/
8130 #define FLASH_AR_FAR_Pos                     (0U)
8131 #define FLASH_AR_FAR_Msk                     (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
8132 #define FLASH_AR_FAR                         FLASH_AR_FAR_Msk                  /*!< Flash Address */
8133 
8134 /******************  Bit definition for FLASH_OBR register  *******************/
8135 #define FLASH_OBR_OPTERR_Pos                 (0U)
8136 #define FLASH_OBR_OPTERR_Msk                 (0x1UL << FLASH_OBR_OPTERR_Pos)    /*!< 0x00000001 */
8137 #define FLASH_OBR_OPTERR                     FLASH_OBR_OPTERR_Msk              /*!< Option Byte Error */
8138 #define FLASH_OBR_RDPRT_Pos                  (1U)
8139 #define FLASH_OBR_RDPRT_Msk                  (0x3UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
8140 #define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read protection */
8141 #define FLASH_OBR_RDPRT_1                    (0x1UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000002 */
8142 #define FLASH_OBR_RDPRT_2                    (0x3UL << FLASH_OBR_RDPRT_Pos)     /*!< 0x00000006 */
8143 
8144 #define FLASH_OBR_USER_Pos                   (8U)
8145 #define FLASH_OBR_USER_Msk                   (0x77UL << FLASH_OBR_USER_Pos)     /*!< 0x00007700 */
8146 #define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
8147 #define FLASH_OBR_IWDG_SW_Pos                (8U)
8148 #define FLASH_OBR_IWDG_SW_Msk                (0x1UL << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00000100 */
8149 #define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG SW */
8150 #define FLASH_OBR_nRST_STOP_Pos              (9U)
8151 #define FLASH_OBR_nRST_STOP_Msk              (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
8152 #define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
8153 #define FLASH_OBR_nRST_STDBY_Pos             (10U)
8154 #define FLASH_OBR_nRST_STDBY_Msk             (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
8155 #define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
8156 #define FLASH_OBR_nBOOT1_Pos                 (12U)
8157 #define FLASH_OBR_nBOOT1_Msk                 (0x1UL << FLASH_OBR_nBOOT1_Pos)    /*!< 0x00001000 */
8158 #define FLASH_OBR_nBOOT1                     FLASH_OBR_nBOOT1_Msk              /*!< nBOOT1 */
8159 #define FLASH_OBR_VDDA_MONITOR_Pos           (13U)
8160 #define FLASH_OBR_VDDA_MONITOR_Msk           (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
8161 #define FLASH_OBR_VDDA_MONITOR               FLASH_OBR_VDDA_MONITOR_Msk        /*!< VDDA_MONITOR */
8162 #define FLASH_OBR_SRAM_PE_Pos                (14U)
8163 #define FLASH_OBR_SRAM_PE_Msk                (0x1UL << FLASH_OBR_SRAM_PE_Pos)   /*!< 0x00004000 */
8164 #define FLASH_OBR_SRAM_PE                    FLASH_OBR_SRAM_PE_Msk             /*!< SRAM_PE */
8165 #define FLASH_OBR_DATA0_Pos                  (16U)
8166 #define FLASH_OBR_DATA0_Msk                  (0xFFUL << FLASH_OBR_DATA0_Pos)    /*!< 0x00FF0000 */
8167 #define FLASH_OBR_DATA0                      FLASH_OBR_DATA0_Msk               /*!< Data0 */
8168 #define FLASH_OBR_DATA1_Pos                  (24U)
8169 #define FLASH_OBR_DATA1_Msk                  (0xFFUL << FLASH_OBR_DATA1_Pos)    /*!< 0xFF000000 */
8170 #define FLASH_OBR_DATA1                      FLASH_OBR_DATA1_Msk               /*!< Data1 */
8171 
8172 /* Legacy defines */
8173 #define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
8174 
8175 /******************  Bit definition for FLASH_WRPR register  ******************/
8176 #define FLASH_WRPR_WRP_Pos                   (0U)
8177 #define FLASH_WRPR_WRP_Msk                   (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
8178 #define FLASH_WRPR_WRP                       FLASH_WRPR_WRP_Msk                /*!< Write Protect */
8179 
8180 /*----------------------------------------------------------------------------*/
8181 
8182 /******************  Bit definition for OB_RDP register  **********************/
8183 #define OB_RDP_RDP_Pos       (0U)
8184 #define OB_RDP_RDP_Msk       (0xFFUL << OB_RDP_RDP_Pos)                         /*!< 0x000000FF */
8185 #define OB_RDP_RDP           OB_RDP_RDP_Msk                                    /*!< Read protection option byte */
8186 #define OB_RDP_nRDP_Pos      (8U)
8187 #define OB_RDP_nRDP_Msk      (0xFFUL << OB_RDP_nRDP_Pos)                        /*!< 0x0000FF00 */
8188 #define OB_RDP_nRDP          OB_RDP_nRDP_Msk                                   /*!< Read protection complemented option byte */
8189 
8190 /******************  Bit definition for OB_USER register  *********************/
8191 #define OB_USER_USER_Pos     (16U)
8192 #define OB_USER_USER_Msk     (0xFFUL << OB_USER_USER_Pos)                       /*!< 0x00FF0000 */
8193 #define OB_USER_USER         OB_USER_USER_Msk                                  /*!< User option byte */
8194 #define OB_USER_nUSER_Pos    (24U)
8195 #define OB_USER_nUSER_Msk    (0xFFUL << OB_USER_nUSER_Pos)                      /*!< 0xFF000000 */
8196 #define OB_USER_nUSER        OB_USER_nUSER_Msk                                 /*!< User complemented option byte */
8197 
8198 /******************  Bit definition for FLASH_WRP0 register  ******************/
8199 #define OB_WRP0_WRP0_Pos     (0U)
8200 #define OB_WRP0_WRP0_Msk     (0xFFUL << OB_WRP0_WRP0_Pos)                       /*!< 0x000000FF */
8201 #define OB_WRP0_WRP0         OB_WRP0_WRP0_Msk                                  /*!< Flash memory write protection option bytes */
8202 #define OB_WRP0_nWRP0_Pos    (8U)
8203 #define OB_WRP0_nWRP0_Msk    (0xFFUL << OB_WRP0_nWRP0_Pos)                      /*!< 0x0000FF00 */
8204 #define OB_WRP0_nWRP0        OB_WRP0_nWRP0_Msk                                 /*!< Flash memory write protection complemented option bytes */
8205 
8206 /******************  Bit definition for FLASH_WRP1 register  ******************/
8207 #define OB_WRP1_WRP1_Pos     (16U)
8208 #define OB_WRP1_WRP1_Msk     (0xFFUL << OB_WRP1_WRP1_Pos)                       /*!< 0x00FF0000 */
8209 #define OB_WRP1_WRP1         OB_WRP1_WRP1_Msk                                  /*!< Flash memory write protection option bytes */
8210 #define OB_WRP1_nWRP1_Pos    (24U)
8211 #define OB_WRP1_nWRP1_Msk    (0xFFUL << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
8212 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
8213 
8214 /******************  Bit definition for FLASH_WRP2 register  ******************/
8215 #define OB_WRP2_WRP2_Pos     (0U)
8216 #define OB_WRP2_WRP2_Msk     (0xFFUL << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
8217 #define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
8218 #define OB_WRP2_nWRP2_Pos    (8U)
8219 #define OB_WRP2_nWRP2_Msk    (0xFFUL << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
8220 #define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
8221 
8222 /******************  Bit definition for FLASH_WRP3 register  ******************/
8223 #define OB_WRP3_WRP3_Pos     (16U)
8224 #define OB_WRP3_WRP3_Msk     (0xFFUL << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
8225 #define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
8226 #define OB_WRP3_nWRP3_Pos    (24U)
8227 #define OB_WRP3_nWRP3_Msk    (0xFFUL << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
8228 #define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
8229 
8230 /******************************************************************************/
8231 /*                                                                            */
8232 /*                            General Purpose I/O (GPIO)                      */
8233 /*                                                                            */
8234 /******************************************************************************/
8235 /*******************  Bit definition for GPIO_MODER register  *****************/
8236 #define GPIO_MODER_MODER0_Pos            (0U)
8237 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
8238 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
8239 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
8240 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
8241 #define GPIO_MODER_MODER1_Pos            (2U)
8242 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
8243 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
8244 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
8245 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
8246 #define GPIO_MODER_MODER2_Pos            (4U)
8247 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
8248 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
8249 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
8250 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
8251 #define GPIO_MODER_MODER3_Pos            (6U)
8252 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
8253 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
8254 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
8255 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
8256 #define GPIO_MODER_MODER4_Pos            (8U)
8257 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
8258 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
8259 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
8260 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
8261 #define GPIO_MODER_MODER5_Pos            (10U)
8262 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
8263 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
8264 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
8265 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
8266 #define GPIO_MODER_MODER6_Pos            (12U)
8267 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
8268 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
8269 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
8270 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
8271 #define GPIO_MODER_MODER7_Pos            (14U)
8272 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
8273 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
8274 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
8275 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
8276 #define GPIO_MODER_MODER8_Pos            (16U)
8277 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
8278 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
8279 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
8280 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
8281 #define GPIO_MODER_MODER9_Pos            (18U)
8282 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
8283 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
8284 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
8285 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
8286 #define GPIO_MODER_MODER10_Pos           (20U)
8287 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
8288 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
8289 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
8290 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
8291 #define GPIO_MODER_MODER11_Pos           (22U)
8292 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
8293 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
8294 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
8295 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
8296 #define GPIO_MODER_MODER12_Pos           (24U)
8297 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
8298 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
8299 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
8300 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
8301 #define GPIO_MODER_MODER13_Pos           (26U)
8302 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
8303 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
8304 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
8305 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
8306 #define GPIO_MODER_MODER14_Pos           (28U)
8307 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
8308 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
8309 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
8310 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
8311 #define GPIO_MODER_MODER15_Pos           (30U)
8312 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
8313 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
8314 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
8315 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
8316 
8317 /******************  Bit definition for GPIO_OTYPER register  *****************/
8318 #define GPIO_OTYPER_OT_0                 (0x00000001U)
8319 #define GPIO_OTYPER_OT_1                 (0x00000002U)
8320 #define GPIO_OTYPER_OT_2                 (0x00000004U)
8321 #define GPIO_OTYPER_OT_3                 (0x00000008U)
8322 #define GPIO_OTYPER_OT_4                 (0x00000010U)
8323 #define GPIO_OTYPER_OT_5                 (0x00000020U)
8324 #define GPIO_OTYPER_OT_6                 (0x00000040U)
8325 #define GPIO_OTYPER_OT_7                 (0x00000080U)
8326 #define GPIO_OTYPER_OT_8                 (0x00000100U)
8327 #define GPIO_OTYPER_OT_9                 (0x00000200U)
8328 #define GPIO_OTYPER_OT_10                (0x00000400U)
8329 #define GPIO_OTYPER_OT_11                (0x00000800U)
8330 #define GPIO_OTYPER_OT_12                (0x00001000U)
8331 #define GPIO_OTYPER_OT_13                (0x00002000U)
8332 #define GPIO_OTYPER_OT_14                (0x00004000U)
8333 #define GPIO_OTYPER_OT_15                (0x00008000U)
8334 
8335 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
8336 #define GPIO_OSPEEDER_OSPEEDR0_Pos       (0U)
8337 #define GPIO_OSPEEDER_OSPEEDR0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000003 */
8338 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDER_OSPEEDR0_Msk
8339 #define GPIO_OSPEEDER_OSPEEDR0_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000001 */
8340 #define GPIO_OSPEEDER_OSPEEDR0_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000002 */
8341 #define GPIO_OSPEEDER_OSPEEDR1_Pos       (2U)
8342 #define GPIO_OSPEEDER_OSPEEDR1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x0000000C */
8343 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDER_OSPEEDR1_Msk
8344 #define GPIO_OSPEEDER_OSPEEDR1_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000004 */
8345 #define GPIO_OSPEEDER_OSPEEDR1_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000008 */
8346 #define GPIO_OSPEEDER_OSPEEDR2_Pos       (4U)
8347 #define GPIO_OSPEEDER_OSPEEDR2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000030 */
8348 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDER_OSPEEDR2_Msk
8349 #define GPIO_OSPEEDER_OSPEEDR2_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000010 */
8350 #define GPIO_OSPEEDER_OSPEEDR2_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000020 */
8351 #define GPIO_OSPEEDER_OSPEEDR3_Pos       (6U)
8352 #define GPIO_OSPEEDER_OSPEEDR3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x000000C0 */
8353 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDER_OSPEEDR3_Msk
8354 #define GPIO_OSPEEDER_OSPEEDR3_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000040 */
8355 #define GPIO_OSPEEDER_OSPEEDR3_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000080 */
8356 #define GPIO_OSPEEDER_OSPEEDR4_Pos       (8U)
8357 #define GPIO_OSPEEDER_OSPEEDR4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000300 */
8358 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDER_OSPEEDR4_Msk
8359 #define GPIO_OSPEEDER_OSPEEDR4_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000100 */
8360 #define GPIO_OSPEEDER_OSPEEDR4_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000200 */
8361 #define GPIO_OSPEEDER_OSPEEDR5_Pos       (10U)
8362 #define GPIO_OSPEEDER_OSPEEDR5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000C00 */
8363 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDER_OSPEEDR5_Msk
8364 #define GPIO_OSPEEDER_OSPEEDR5_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000400 */
8365 #define GPIO_OSPEEDER_OSPEEDR5_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000800 */
8366 #define GPIO_OSPEEDER_OSPEEDR6_Pos       (12U)
8367 #define GPIO_OSPEEDER_OSPEEDR6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00003000 */
8368 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDER_OSPEEDR6_Msk
8369 #define GPIO_OSPEEDER_OSPEEDR6_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00001000 */
8370 #define GPIO_OSPEEDER_OSPEEDR6_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00002000 */
8371 #define GPIO_OSPEEDER_OSPEEDR7_Pos       (14U)
8372 #define GPIO_OSPEEDER_OSPEEDR7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x0000C000 */
8373 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDER_OSPEEDR7_Msk
8374 #define GPIO_OSPEEDER_OSPEEDR7_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00004000 */
8375 #define GPIO_OSPEEDER_OSPEEDR7_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00008000 */
8376 #define GPIO_OSPEEDER_OSPEEDR8_Pos       (16U)
8377 #define GPIO_OSPEEDER_OSPEEDR8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00030000 */
8378 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDER_OSPEEDR8_Msk
8379 #define GPIO_OSPEEDER_OSPEEDR8_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00010000 */
8380 #define GPIO_OSPEEDER_OSPEEDR8_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00020000 */
8381 #define GPIO_OSPEEDER_OSPEEDR9_Pos       (18U)
8382 #define GPIO_OSPEEDER_OSPEEDR9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x000C0000 */
8383 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDER_OSPEEDR9_Msk
8384 #define GPIO_OSPEEDER_OSPEEDR9_0         (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00040000 */
8385 #define GPIO_OSPEEDER_OSPEEDR9_1         (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00080000 */
8386 #define GPIO_OSPEEDER_OSPEEDR10_Pos      (20U)
8387 #define GPIO_OSPEEDER_OSPEEDR10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
8388 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDER_OSPEEDR10_Msk
8389 #define GPIO_OSPEEDER_OSPEEDR10_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
8390 #define GPIO_OSPEEDER_OSPEEDR10_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
8391 #define GPIO_OSPEEDER_OSPEEDR11_Pos      (22U)
8392 #define GPIO_OSPEEDER_OSPEEDR11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
8393 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDER_OSPEEDR11_Msk
8394 #define GPIO_OSPEEDER_OSPEEDR11_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
8395 #define GPIO_OSPEEDER_OSPEEDR11_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
8396 #define GPIO_OSPEEDER_OSPEEDR12_Pos      (24U)
8397 #define GPIO_OSPEEDER_OSPEEDR12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
8398 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDER_OSPEEDR12_Msk
8399 #define GPIO_OSPEEDER_OSPEEDR12_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
8400 #define GPIO_OSPEEDER_OSPEEDR12_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
8401 #define GPIO_OSPEEDER_OSPEEDR13_Pos      (26U)
8402 #define GPIO_OSPEEDER_OSPEEDR13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
8403 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDER_OSPEEDR13_Msk
8404 #define GPIO_OSPEEDER_OSPEEDR13_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
8405 #define GPIO_OSPEEDER_OSPEEDR13_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
8406 #define GPIO_OSPEEDER_OSPEEDR14_Pos      (28U)
8407 #define GPIO_OSPEEDER_OSPEEDR14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
8408 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDER_OSPEEDR14_Msk
8409 #define GPIO_OSPEEDER_OSPEEDR14_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
8410 #define GPIO_OSPEEDER_OSPEEDR14_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
8411 #define GPIO_OSPEEDER_OSPEEDR15_Pos      (30U)
8412 #define GPIO_OSPEEDER_OSPEEDR15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
8413 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDER_OSPEEDR15_Msk
8414 #define GPIO_OSPEEDER_OSPEEDR15_0        (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
8415 #define GPIO_OSPEEDER_OSPEEDR15_1        (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
8416 
8417 /*******************  Bit definition for GPIO_PUPDR register ******************/
8418 #define GPIO_PUPDR_PUPDR0_Pos            (0U)
8419 #define GPIO_PUPDR_PUPDR0_Msk            (0x3UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */
8420 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk
8421 #define GPIO_PUPDR_PUPDR0_0              (0x1UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */
8422 #define GPIO_PUPDR_PUPDR0_1              (0x2UL << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */
8423 #define GPIO_PUPDR_PUPDR1_Pos            (2U)
8424 #define GPIO_PUPDR_PUPDR1_Msk            (0x3UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */
8425 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk
8426 #define GPIO_PUPDR_PUPDR1_0              (0x1UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */
8427 #define GPIO_PUPDR_PUPDR1_1              (0x2UL << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */
8428 #define GPIO_PUPDR_PUPDR2_Pos            (4U)
8429 #define GPIO_PUPDR_PUPDR2_Msk            (0x3UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */
8430 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk
8431 #define GPIO_PUPDR_PUPDR2_0              (0x1UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */
8432 #define GPIO_PUPDR_PUPDR2_1              (0x2UL << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */
8433 #define GPIO_PUPDR_PUPDR3_Pos            (6U)
8434 #define GPIO_PUPDR_PUPDR3_Msk            (0x3UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */
8435 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk
8436 #define GPIO_PUPDR_PUPDR3_0              (0x1UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */
8437 #define GPIO_PUPDR_PUPDR3_1              (0x2UL << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */
8438 #define GPIO_PUPDR_PUPDR4_Pos            (8U)
8439 #define GPIO_PUPDR_PUPDR4_Msk            (0x3UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */
8440 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk
8441 #define GPIO_PUPDR_PUPDR4_0              (0x1UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */
8442 #define GPIO_PUPDR_PUPDR4_1              (0x2UL << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */
8443 #define GPIO_PUPDR_PUPDR5_Pos            (10U)
8444 #define GPIO_PUPDR_PUPDR5_Msk            (0x3UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */
8445 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk
8446 #define GPIO_PUPDR_PUPDR5_0              (0x1UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */
8447 #define GPIO_PUPDR_PUPDR5_1              (0x2UL << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */
8448 #define GPIO_PUPDR_PUPDR6_Pos            (12U)
8449 #define GPIO_PUPDR_PUPDR6_Msk            (0x3UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */
8450 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk
8451 #define GPIO_PUPDR_PUPDR6_0              (0x1UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */
8452 #define GPIO_PUPDR_PUPDR6_1              (0x2UL << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */
8453 #define GPIO_PUPDR_PUPDR7_Pos            (14U)
8454 #define GPIO_PUPDR_PUPDR7_Msk            (0x3UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */
8455 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk
8456 #define GPIO_PUPDR_PUPDR7_0              (0x1UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */
8457 #define GPIO_PUPDR_PUPDR7_1              (0x2UL << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */
8458 #define GPIO_PUPDR_PUPDR8_Pos            (16U)
8459 #define GPIO_PUPDR_PUPDR8_Msk            (0x3UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */
8460 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk
8461 #define GPIO_PUPDR_PUPDR8_0              (0x1UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */
8462 #define GPIO_PUPDR_PUPDR8_1              (0x2UL << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */
8463 #define GPIO_PUPDR_PUPDR9_Pos            (18U)
8464 #define GPIO_PUPDR_PUPDR9_Msk            (0x3UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */
8465 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk
8466 #define GPIO_PUPDR_PUPDR9_0              (0x1UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */
8467 #define GPIO_PUPDR_PUPDR9_1              (0x2UL << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */
8468 #define GPIO_PUPDR_PUPDR10_Pos           (20U)
8469 #define GPIO_PUPDR_PUPDR10_Msk           (0x3UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */
8470 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk
8471 #define GPIO_PUPDR_PUPDR10_0             (0x1UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */
8472 #define GPIO_PUPDR_PUPDR10_1             (0x2UL << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */
8473 #define GPIO_PUPDR_PUPDR11_Pos           (22U)
8474 #define GPIO_PUPDR_PUPDR11_Msk           (0x3UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */
8475 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk
8476 #define GPIO_PUPDR_PUPDR11_0             (0x1UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */
8477 #define GPIO_PUPDR_PUPDR11_1             (0x2UL << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */
8478 #define GPIO_PUPDR_PUPDR12_Pos           (24U)
8479 #define GPIO_PUPDR_PUPDR12_Msk           (0x3UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */
8480 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk
8481 #define GPIO_PUPDR_PUPDR12_0             (0x1UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */
8482 #define GPIO_PUPDR_PUPDR12_1             (0x2UL << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */
8483 #define GPIO_PUPDR_PUPDR13_Pos           (26U)
8484 #define GPIO_PUPDR_PUPDR13_Msk           (0x3UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */
8485 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk
8486 #define GPIO_PUPDR_PUPDR13_0             (0x1UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */
8487 #define GPIO_PUPDR_PUPDR13_1             (0x2UL << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */
8488 #define GPIO_PUPDR_PUPDR14_Pos           (28U)
8489 #define GPIO_PUPDR_PUPDR14_Msk           (0x3UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */
8490 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk
8491 #define GPIO_PUPDR_PUPDR14_0             (0x1UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */
8492 #define GPIO_PUPDR_PUPDR14_1             (0x2UL << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */
8493 #define GPIO_PUPDR_PUPDR15_Pos           (30U)
8494 #define GPIO_PUPDR_PUPDR15_Msk           (0x3UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */
8495 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk
8496 #define GPIO_PUPDR_PUPDR15_0             (0x1UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */
8497 #define GPIO_PUPDR_PUPDR15_1             (0x2UL << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */
8498 
8499 /*******************  Bit definition for GPIO_IDR register  *******************/
8500 #define GPIO_IDR_0                       (0x00000001U)
8501 #define GPIO_IDR_1                       (0x00000002U)
8502 #define GPIO_IDR_2                       (0x00000004U)
8503 #define GPIO_IDR_3                       (0x00000008U)
8504 #define GPIO_IDR_4                       (0x00000010U)
8505 #define GPIO_IDR_5                       (0x00000020U)
8506 #define GPIO_IDR_6                       (0x00000040U)
8507 #define GPIO_IDR_7                       (0x00000080U)
8508 #define GPIO_IDR_8                       (0x00000100U)
8509 #define GPIO_IDR_9                       (0x00000200U)
8510 #define GPIO_IDR_10                      (0x00000400U)
8511 #define GPIO_IDR_11                      (0x00000800U)
8512 #define GPIO_IDR_12                      (0x00001000U)
8513 #define GPIO_IDR_13                      (0x00002000U)
8514 #define GPIO_IDR_14                      (0x00004000U)
8515 #define GPIO_IDR_15                      (0x00008000U)
8516 
8517 /******************  Bit definition for GPIO_ODR register  ********************/
8518 #define GPIO_ODR_0                       (0x00000001U)
8519 #define GPIO_ODR_1                       (0x00000002U)
8520 #define GPIO_ODR_2                       (0x00000004U)
8521 #define GPIO_ODR_3                       (0x00000008U)
8522 #define GPIO_ODR_4                       (0x00000010U)
8523 #define GPIO_ODR_5                       (0x00000020U)
8524 #define GPIO_ODR_6                       (0x00000040U)
8525 #define GPIO_ODR_7                       (0x00000080U)
8526 #define GPIO_ODR_8                       (0x00000100U)
8527 #define GPIO_ODR_9                       (0x00000200U)
8528 #define GPIO_ODR_10                      (0x00000400U)
8529 #define GPIO_ODR_11                      (0x00000800U)
8530 #define GPIO_ODR_12                      (0x00001000U)
8531 #define GPIO_ODR_13                      (0x00002000U)
8532 #define GPIO_ODR_14                      (0x00004000U)
8533 #define GPIO_ODR_15                      (0x00008000U)
8534 
8535 /****************** Bit definition for GPIO_BSRR register  ********************/
8536 #define GPIO_BSRR_BS_0                   (0x00000001U)
8537 #define GPIO_BSRR_BS_1                   (0x00000002U)
8538 #define GPIO_BSRR_BS_2                   (0x00000004U)
8539 #define GPIO_BSRR_BS_3                   (0x00000008U)
8540 #define GPIO_BSRR_BS_4                   (0x00000010U)
8541 #define GPIO_BSRR_BS_5                   (0x00000020U)
8542 #define GPIO_BSRR_BS_6                   (0x00000040U)
8543 #define GPIO_BSRR_BS_7                   (0x00000080U)
8544 #define GPIO_BSRR_BS_8                   (0x00000100U)
8545 #define GPIO_BSRR_BS_9                   (0x00000200U)
8546 #define GPIO_BSRR_BS_10                  (0x00000400U)
8547 #define GPIO_BSRR_BS_11                  (0x00000800U)
8548 #define GPIO_BSRR_BS_12                  (0x00001000U)
8549 #define GPIO_BSRR_BS_13                  (0x00002000U)
8550 #define GPIO_BSRR_BS_14                  (0x00004000U)
8551 #define GPIO_BSRR_BS_15                  (0x00008000U)
8552 #define GPIO_BSRR_BR_0                   (0x00010000U)
8553 #define GPIO_BSRR_BR_1                   (0x00020000U)
8554 #define GPIO_BSRR_BR_2                   (0x00040000U)
8555 #define GPIO_BSRR_BR_3                   (0x00080000U)
8556 #define GPIO_BSRR_BR_4                   (0x00100000U)
8557 #define GPIO_BSRR_BR_5                   (0x00200000U)
8558 #define GPIO_BSRR_BR_6                   (0x00400000U)
8559 #define GPIO_BSRR_BR_7                   (0x00800000U)
8560 #define GPIO_BSRR_BR_8                   (0x01000000U)
8561 #define GPIO_BSRR_BR_9                   (0x02000000U)
8562 #define GPIO_BSRR_BR_10                  (0x04000000U)
8563 #define GPIO_BSRR_BR_11                  (0x08000000U)
8564 #define GPIO_BSRR_BR_12                  (0x10000000U)
8565 #define GPIO_BSRR_BR_13                  (0x20000000U)
8566 #define GPIO_BSRR_BR_14                  (0x40000000U)
8567 #define GPIO_BSRR_BR_15                  (0x80000000U)
8568 
8569 /****************** Bit definition for GPIO_LCKR register  ********************/
8570 #define GPIO_LCKR_LCK0_Pos               (0U)
8571 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
8572 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
8573 #define GPIO_LCKR_LCK1_Pos               (1U)
8574 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
8575 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
8576 #define GPIO_LCKR_LCK2_Pos               (2U)
8577 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
8578 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
8579 #define GPIO_LCKR_LCK3_Pos               (3U)
8580 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
8581 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
8582 #define GPIO_LCKR_LCK4_Pos               (4U)
8583 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
8584 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
8585 #define GPIO_LCKR_LCK5_Pos               (5U)
8586 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
8587 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
8588 #define GPIO_LCKR_LCK6_Pos               (6U)
8589 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
8590 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
8591 #define GPIO_LCKR_LCK7_Pos               (7U)
8592 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
8593 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
8594 #define GPIO_LCKR_LCK8_Pos               (8U)
8595 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
8596 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
8597 #define GPIO_LCKR_LCK9_Pos               (9U)
8598 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
8599 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
8600 #define GPIO_LCKR_LCK10_Pos              (10U)
8601 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
8602 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
8603 #define GPIO_LCKR_LCK11_Pos              (11U)
8604 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
8605 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
8606 #define GPIO_LCKR_LCK12_Pos              (12U)
8607 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
8608 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
8609 #define GPIO_LCKR_LCK13_Pos              (13U)
8610 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
8611 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
8612 #define GPIO_LCKR_LCK14_Pos              (14U)
8613 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
8614 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
8615 #define GPIO_LCKR_LCK15_Pos              (15U)
8616 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
8617 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
8618 #define GPIO_LCKR_LCKK_Pos               (16U)
8619 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
8620 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
8621 
8622 /****************** Bit definition for GPIO_AFRL register  ********************/
8623 #define GPIO_AFRL_AFRL0_Pos              (0U)
8624 #define GPIO_AFRL_AFRL0_Msk              (0xFUL << GPIO_AFRL_AFRL0_Pos)         /*!< 0x0000000F */
8625 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFRL0_Msk
8626 #define GPIO_AFRL_AFRL1_Pos              (4U)
8627 #define GPIO_AFRL_AFRL1_Msk              (0xFUL << GPIO_AFRL_AFRL1_Pos)         /*!< 0x000000F0 */
8628 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFRL1_Msk
8629 #define GPIO_AFRL_AFRL2_Pos              (8U)
8630 #define GPIO_AFRL_AFRL2_Msk              (0xFUL << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000F00 */
8631 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFRL2_Msk
8632 #define GPIO_AFRL_AFRL3_Pos              (12U)
8633 #define GPIO_AFRL_AFRL3_Msk              (0xFUL << GPIO_AFRL_AFRL3_Pos)         /*!< 0x0000F000 */
8634 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFRL3_Msk
8635 #define GPIO_AFRL_AFRL4_Pos              (16U)
8636 #define GPIO_AFRL_AFRL4_Msk              (0xFUL << GPIO_AFRL_AFRL4_Pos)         /*!< 0x000F0000 */
8637 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFRL4_Msk
8638 #define GPIO_AFRL_AFRL5_Pos              (20U)
8639 #define GPIO_AFRL_AFRL5_Msk              (0xFUL << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00F00000 */
8640 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFRL5_Msk
8641 #define GPIO_AFRL_AFRL6_Pos              (24U)
8642 #define GPIO_AFRL_AFRL6_Msk              (0xFUL << GPIO_AFRL_AFRL6_Pos)         /*!< 0x0F000000 */
8643 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFRL6_Msk
8644 #define GPIO_AFRL_AFRL7_Pos              (28U)
8645 #define GPIO_AFRL_AFRL7_Msk              (0xFUL << GPIO_AFRL_AFRL7_Pos)         /*!< 0xF0000000 */
8646 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFRL7_Msk
8647 
8648 /****************** Bit definition for GPIO_AFRH register  ********************/
8649 #define GPIO_AFRH_AFRH0_Pos              (0U)
8650 #define GPIO_AFRH_AFRH0_Msk              (0xFUL << GPIO_AFRH_AFRH0_Pos)         /*!< 0x0000000F */
8651 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFRH0_Msk
8652 #define GPIO_AFRH_AFRH1_Pos              (4U)
8653 #define GPIO_AFRH_AFRH1_Msk              (0xFUL << GPIO_AFRH_AFRH1_Pos)         /*!< 0x000000F0 */
8654 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFRH1_Msk
8655 #define GPIO_AFRH_AFRH2_Pos              (8U)
8656 #define GPIO_AFRH_AFRH2_Msk              (0xFUL << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000F00 */
8657 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFRH2_Msk
8658 #define GPIO_AFRH_AFRH3_Pos              (12U)
8659 #define GPIO_AFRH_AFRH3_Msk              (0xFUL << GPIO_AFRH_AFRH3_Pos)         /*!< 0x0000F000 */
8660 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFRH3_Msk
8661 #define GPIO_AFRH_AFRH4_Pos              (16U)
8662 #define GPIO_AFRH_AFRH4_Msk              (0xFUL << GPIO_AFRH_AFRH4_Pos)         /*!< 0x000F0000 */
8663 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFRH4_Msk
8664 #define GPIO_AFRH_AFRH5_Pos              (20U)
8665 #define GPIO_AFRH_AFRH5_Msk              (0xFUL << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00F00000 */
8666 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFRH5_Msk
8667 #define GPIO_AFRH_AFRH6_Pos              (24U)
8668 #define GPIO_AFRH_AFRH6_Msk              (0xFUL << GPIO_AFRH_AFRH6_Pos)         /*!< 0x0F000000 */
8669 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFRH6_Msk
8670 #define GPIO_AFRH_AFRH7_Pos              (28U)
8671 #define GPIO_AFRH_AFRH7_Msk              (0xFUL << GPIO_AFRH_AFRH7_Pos)         /*!< 0xF0000000 */
8672 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFRH7_Msk
8673 
8674 /****************** Bit definition for GPIO_BRR register  *********************/
8675 #define GPIO_BRR_BR_0                    (0x00000001U)
8676 #define GPIO_BRR_BR_1                    (0x00000002U)
8677 #define GPIO_BRR_BR_2                    (0x00000004U)
8678 #define GPIO_BRR_BR_3                    (0x00000008U)
8679 #define GPIO_BRR_BR_4                    (0x00000010U)
8680 #define GPIO_BRR_BR_5                    (0x00000020U)
8681 #define GPIO_BRR_BR_6                    (0x00000040U)
8682 #define GPIO_BRR_BR_7                    (0x00000080U)
8683 #define GPIO_BRR_BR_8                    (0x00000100U)
8684 #define GPIO_BRR_BR_9                    (0x00000200U)
8685 #define GPIO_BRR_BR_10                   (0x00000400U)
8686 #define GPIO_BRR_BR_11                   (0x00000800U)
8687 #define GPIO_BRR_BR_12                   (0x00001000U)
8688 #define GPIO_BRR_BR_13                   (0x00002000U)
8689 #define GPIO_BRR_BR_14                   (0x00004000U)
8690 #define GPIO_BRR_BR_15                   (0x00008000U)
8691 
8692 /******************************************************************************/
8693 /*                                                                            */
8694 /*                      Inter-integrated Circuit Interface (I2C)              */
8695 /*                                                                            */
8696 /******************************************************************************/
8697 /*******************  Bit definition for I2C_CR1 register  *******************/
8698 #define I2C_CR1_PE_Pos               (0U)
8699 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
8700 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
8701 #define I2C_CR1_TXIE_Pos             (1U)
8702 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
8703 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
8704 #define I2C_CR1_RXIE_Pos             (2U)
8705 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
8706 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
8707 #define I2C_CR1_ADDRIE_Pos           (3U)
8708 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
8709 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
8710 #define I2C_CR1_NACKIE_Pos           (4U)
8711 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
8712 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
8713 #define I2C_CR1_STOPIE_Pos           (5U)
8714 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
8715 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
8716 #define I2C_CR1_TCIE_Pos             (6U)
8717 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
8718 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
8719 #define I2C_CR1_ERRIE_Pos            (7U)
8720 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
8721 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
8722 #define I2C_CR1_DNF_Pos              (8U)
8723 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
8724 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
8725 #define I2C_CR1_ANFOFF_Pos           (12U)
8726 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
8727 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
8728 #define I2C_CR1_SWRST_Pos            (13U)
8729 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
8730 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
8731 #define I2C_CR1_TXDMAEN_Pos          (14U)
8732 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
8733 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
8734 #define I2C_CR1_RXDMAEN_Pos          (15U)
8735 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
8736 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
8737 #define I2C_CR1_SBC_Pos              (16U)
8738 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
8739 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
8740 #define I2C_CR1_NOSTRETCH_Pos        (17U)
8741 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
8742 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
8743 #define I2C_CR1_WUPEN_Pos            (18U)
8744 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
8745 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
8746 #define I2C_CR1_GCEN_Pos             (19U)
8747 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
8748 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
8749 #define I2C_CR1_SMBHEN_Pos           (20U)
8750 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
8751 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
8752 #define I2C_CR1_SMBDEN_Pos           (21U)
8753 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
8754 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
8755 #define I2C_CR1_ALERTEN_Pos          (22U)
8756 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
8757 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
8758 #define I2C_CR1_PECEN_Pos            (23U)
8759 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
8760 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
8761 
8762 /* Legacy defines */
8763 #define I2C_CR1_DFN I2C_CR1_DNF
8764 
8765 /******************  Bit definition for I2C_CR2 register  ********************/
8766 #define I2C_CR2_SADD_Pos             (0U)
8767 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
8768 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
8769 #define I2C_CR2_RD_WRN_Pos           (10U)
8770 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
8771 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
8772 #define I2C_CR2_ADD10_Pos            (11U)
8773 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
8774 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
8775 #define I2C_CR2_HEAD10R_Pos          (12U)
8776 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
8777 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
8778 #define I2C_CR2_START_Pos            (13U)
8779 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
8780 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
8781 #define I2C_CR2_STOP_Pos             (14U)
8782 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
8783 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
8784 #define I2C_CR2_NACK_Pos             (15U)
8785 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
8786 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
8787 #define I2C_CR2_NBYTES_Pos           (16U)
8788 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
8789 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
8790 #define I2C_CR2_RELOAD_Pos           (24U)
8791 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
8792 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
8793 #define I2C_CR2_AUTOEND_Pos          (25U)
8794 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
8795 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
8796 #define I2C_CR2_PECBYTE_Pos          (26U)
8797 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
8798 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
8799 
8800 /*******************  Bit definition for I2C_OAR1 register  ******************/
8801 #define I2C_OAR1_OA1_Pos             (0U)
8802 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
8803 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
8804 #define I2C_OAR1_OA1MODE_Pos         (10U)
8805 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
8806 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
8807 #define I2C_OAR1_OA1EN_Pos           (15U)
8808 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
8809 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
8810 
8811 /*******************  Bit definition for I2C_OAR2 register  *******************/
8812 #define I2C_OAR2_OA2_Pos             (1U)
8813 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
8814 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
8815 #define I2C_OAR2_OA2MSK_Pos          (8U)
8816 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
8817 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
8818 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
8819 #define I2C_OAR2_OA2MASK01_Pos       (8U)
8820 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
8821 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
8822 #define I2C_OAR2_OA2MASK02_Pos       (9U)
8823 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
8824 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
8825 #define I2C_OAR2_OA2MASK03_Pos       (8U)
8826 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
8827 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
8828 #define I2C_OAR2_OA2MASK04_Pos       (10U)
8829 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
8830 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
8831 #define I2C_OAR2_OA2MASK05_Pos       (8U)
8832 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
8833 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
8834 #define I2C_OAR2_OA2MASK06_Pos       (9U)
8835 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
8836 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
8837 #define I2C_OAR2_OA2MASK07_Pos       (8U)
8838 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
8839 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
8840 #define I2C_OAR2_OA2EN_Pos           (15U)
8841 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
8842 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
8843 
8844 /*******************  Bit definition for I2C_TIMINGR register *****************/
8845 #define I2C_TIMINGR_SCLL_Pos         (0U)
8846 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
8847 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
8848 #define I2C_TIMINGR_SCLH_Pos         (8U)
8849 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
8850 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
8851 #define I2C_TIMINGR_SDADEL_Pos       (16U)
8852 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
8853 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
8854 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
8855 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
8856 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
8857 #define I2C_TIMINGR_PRESC_Pos        (28U)
8858 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
8859 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
8860 
8861 /******************* Bit definition for I2C_TIMEOUTR register *****************/
8862 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
8863 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
8864 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
8865 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
8866 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
8867 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
8868 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
8869 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
8870 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
8871 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
8872 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
8873 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
8874 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
8875 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
8876 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
8877 
8878 /******************  Bit definition for I2C_ISR register  *********************/
8879 #define I2C_ISR_TXE_Pos              (0U)
8880 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
8881 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
8882 #define I2C_ISR_TXIS_Pos             (1U)
8883 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
8884 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
8885 #define I2C_ISR_RXNE_Pos             (2U)
8886 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
8887 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
8888 #define I2C_ISR_ADDR_Pos             (3U)
8889 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
8890 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
8891 #define I2C_ISR_NACKF_Pos            (4U)
8892 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
8893 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
8894 #define I2C_ISR_STOPF_Pos            (5U)
8895 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
8896 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
8897 #define I2C_ISR_TC_Pos               (6U)
8898 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
8899 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
8900 #define I2C_ISR_TCR_Pos              (7U)
8901 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
8902 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
8903 #define I2C_ISR_BERR_Pos             (8U)
8904 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
8905 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
8906 #define I2C_ISR_ARLO_Pos             (9U)
8907 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
8908 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
8909 #define I2C_ISR_OVR_Pos              (10U)
8910 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
8911 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
8912 #define I2C_ISR_PECERR_Pos           (11U)
8913 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
8914 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
8915 #define I2C_ISR_TIMEOUT_Pos          (12U)
8916 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
8917 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
8918 #define I2C_ISR_ALERT_Pos            (13U)
8919 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
8920 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
8921 #define I2C_ISR_BUSY_Pos             (15U)
8922 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
8923 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
8924 #define I2C_ISR_DIR_Pos              (16U)
8925 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
8926 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
8927 #define I2C_ISR_ADDCODE_Pos          (17U)
8928 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
8929 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
8930 
8931 /******************  Bit definition for I2C_ICR register  *********************/
8932 #define I2C_ICR_ADDRCF_Pos           (3U)
8933 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
8934 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
8935 #define I2C_ICR_NACKCF_Pos           (4U)
8936 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
8937 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
8938 #define I2C_ICR_STOPCF_Pos           (5U)
8939 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
8940 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
8941 #define I2C_ICR_BERRCF_Pos           (8U)
8942 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
8943 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
8944 #define I2C_ICR_ARLOCF_Pos           (9U)
8945 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
8946 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
8947 #define I2C_ICR_OVRCF_Pos            (10U)
8948 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
8949 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
8950 #define I2C_ICR_PECCF_Pos            (11U)
8951 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
8952 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
8953 #define I2C_ICR_TIMOUTCF_Pos         (12U)
8954 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
8955 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
8956 #define I2C_ICR_ALERTCF_Pos          (13U)
8957 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
8958 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
8959 
8960 /******************  Bit definition for I2C_PECR register  ********************/
8961 #define I2C_PECR_PEC_Pos             (0U)
8962 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
8963 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
8964 
8965 /******************  Bit definition for I2C_RXDR register  *********************/
8966 #define I2C_RXDR_RXDATA_Pos          (0U)
8967 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
8968 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
8969 
8970 /******************  Bit definition for I2C_TXDR register  *********************/
8971 #define I2C_TXDR_TXDATA_Pos          (0U)
8972 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
8973 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
8974 
8975 
8976 /******************************************************************************/
8977 /*                                                                            */
8978 /*                           Independent WATCHDOG (IWDG)                      */
8979 /*                                                                            */
8980 /******************************************************************************/
8981 /*******************  Bit definition for IWDG_KR register  ********************/
8982 #define IWDG_KR_KEY_Pos      (0U)
8983 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
8984 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
8985 
8986 /*******************  Bit definition for IWDG_PR register  ********************/
8987 #define IWDG_PR_PR_Pos       (0U)
8988 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
8989 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
8990 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
8991 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
8992 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
8993 
8994 /*******************  Bit definition for IWDG_RLR register  *******************/
8995 #define IWDG_RLR_RL_Pos      (0U)
8996 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
8997 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
8998 
8999 /*******************  Bit definition for IWDG_SR register  ********************/
9000 #define IWDG_SR_PVU_Pos      (0U)
9001 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
9002 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
9003 #define IWDG_SR_RVU_Pos      (1U)
9004 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
9005 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
9006 #define IWDG_SR_WVU_Pos      (2U)
9007 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
9008 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
9009 
9010 /*******************  Bit definition for IWDG_KR register  ********************/
9011 #define IWDG_WINR_WIN_Pos    (0U)
9012 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
9013 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
9014 
9015 /******************************************************************************/
9016 /*                                                                            */
9017 /*                             Power Control                                  */
9018 /*                                                                            */
9019 /******************************************************************************/
9020 /* Note: No specific macro feature on this device */
9021 /********************  Bit definition for PWR_CR register  ********************/
9022 #define PWR_CR_LPDS_Pos            (0U)
9023 #define PWR_CR_LPDS_Msk            (0x1UL << PWR_CR_LPDS_Pos)                   /*!< 0x00000001 */
9024 #define PWR_CR_LPDS                PWR_CR_LPDS_Msk                             /*!< Low-power Deepsleep */
9025 #define PWR_CR_PDDS_Pos            (1U)
9026 #define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
9027 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
9028 #define PWR_CR_CWUF_Pos            (2U)
9029 #define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
9030 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
9031 #define PWR_CR_CSBF_Pos            (3U)
9032 #define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
9033 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
9034 
9035 #define PWR_CR_DBP_Pos             (8U)
9036 #define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
9037 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
9038 
9039 /*******************  Bit definition for PWR_CSR register  ********************/
9040 #define PWR_CSR_WUF_Pos            (0U)
9041 #define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
9042 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
9043 #define PWR_CSR_SBF_Pos            (1U)
9044 #define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
9045 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
9046 #define PWR_CSR_VREFINTRDYF_Pos    (3U)
9047 #define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
9048 #define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
9049 
9050 #define PWR_CSR_EWUP1_Pos          (8U)
9051 #define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
9052 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
9053 #define PWR_CSR_EWUP2_Pos          (9U)
9054 #define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
9055 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
9056 #define PWR_CSR_EWUP3_Pos          (10U)
9057 #define PWR_CSR_EWUP3_Msk          (0x1UL << PWR_CSR_EWUP3_Pos)                 /*!< 0x00000400 */
9058 #define PWR_CSR_EWUP3              PWR_CSR_EWUP3_Msk                           /*!< Enable WKUP pin 3 */
9059 
9060 /******************************************************************************/
9061 /*                                                                            */
9062 /*                         Reset and Clock Control                            */
9063 /*                                                                            */
9064 /******************************************************************************/
9065 /********************  Bit definition for RCC_CR register  ********************/
9066 #define RCC_CR_HSION_Pos                         (0U)
9067 #define RCC_CR_HSION_Msk                         (0x1UL << RCC_CR_HSION_Pos)    /*!< 0x00000001 */
9068 #define RCC_CR_HSION                             RCC_CR_HSION_Msk
9069 #define RCC_CR_HSIRDY_Pos                        (1U)
9070 #define RCC_CR_HSIRDY_Msk                        (0x1UL << RCC_CR_HSIRDY_Pos)   /*!< 0x00000002 */
9071 #define RCC_CR_HSIRDY                            RCC_CR_HSIRDY_Msk
9072 
9073 #define RCC_CR_HSITRIM_Pos                       (3U)
9074 #define RCC_CR_HSITRIM_Msk                       (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
9075 #define RCC_CR_HSITRIM                           RCC_CR_HSITRIM_Msk
9076 #define RCC_CR_HSITRIM_0                         (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
9077 #define RCC_CR_HSITRIM_1                         (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
9078 #define RCC_CR_HSITRIM_2                         (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
9079 #define RCC_CR_HSITRIM_3                         (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
9080 #define RCC_CR_HSITRIM_4                         (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
9081 
9082 #define RCC_CR_HSICAL_Pos                        (8U)
9083 #define RCC_CR_HSICAL_Msk                        (0xFFUL << RCC_CR_HSICAL_Pos)  /*!< 0x0000FF00 */
9084 #define RCC_CR_HSICAL                            RCC_CR_HSICAL_Msk
9085 #define RCC_CR_HSICAL_0                          (0x01UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000100 */
9086 #define RCC_CR_HSICAL_1                          (0x02UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000200 */
9087 #define RCC_CR_HSICAL_2                          (0x04UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000400 */
9088 #define RCC_CR_HSICAL_3                          (0x08UL << RCC_CR_HSICAL_Pos)  /*!< 0x00000800 */
9089 #define RCC_CR_HSICAL_4                          (0x10UL << RCC_CR_HSICAL_Pos)  /*!< 0x00001000 */
9090 #define RCC_CR_HSICAL_5                          (0x20UL << RCC_CR_HSICAL_Pos)  /*!< 0x00002000 */
9091 #define RCC_CR_HSICAL_6                          (0x40UL << RCC_CR_HSICAL_Pos)  /*!< 0x00004000 */
9092 #define RCC_CR_HSICAL_7                          (0x80UL << RCC_CR_HSICAL_Pos)  /*!< 0x00008000 */
9093 
9094 #define RCC_CR_HSEON_Pos                         (16U)
9095 #define RCC_CR_HSEON_Msk                         (0x1UL << RCC_CR_HSEON_Pos)    /*!< 0x00010000 */
9096 #define RCC_CR_HSEON                             RCC_CR_HSEON_Msk
9097 #define RCC_CR_HSERDY_Pos                        (17U)
9098 #define RCC_CR_HSERDY_Msk                        (0x1UL << RCC_CR_HSERDY_Pos)   /*!< 0x00020000 */
9099 #define RCC_CR_HSERDY                            RCC_CR_HSERDY_Msk
9100 #define RCC_CR_HSEBYP_Pos                        (18U)
9101 #define RCC_CR_HSEBYP_Msk                        (0x1UL << RCC_CR_HSEBYP_Pos)   /*!< 0x00040000 */
9102 #define RCC_CR_HSEBYP                            RCC_CR_HSEBYP_Msk
9103 #define RCC_CR_CSSON_Pos                         (19U)
9104 #define RCC_CR_CSSON_Msk                         (0x1UL << RCC_CR_CSSON_Pos)    /*!< 0x00080000 */
9105 #define RCC_CR_CSSON                             RCC_CR_CSSON_Msk
9106 #define RCC_CR_PLLON_Pos                         (24U)
9107 #define RCC_CR_PLLON_Msk                         (0x1UL << RCC_CR_PLLON_Pos)    /*!< 0x01000000 */
9108 #define RCC_CR_PLLON                             RCC_CR_PLLON_Msk
9109 #define RCC_CR_PLLRDY_Pos                        (25U)
9110 #define RCC_CR_PLLRDY_Msk                        (0x1UL << RCC_CR_PLLRDY_Pos)   /*!< 0x02000000 */
9111 #define RCC_CR_PLLRDY                            RCC_CR_PLLRDY_Msk
9112 
9113 /********************  Bit definition for RCC_CFGR register  ******************/
9114 /*!< SW configuration */
9115 #define RCC_CFGR_SW_Pos                          (0U)
9116 #define RCC_CFGR_SW_Msk                          (0x3UL << RCC_CFGR_SW_Pos)     /*!< 0x00000003 */
9117 #define RCC_CFGR_SW                              RCC_CFGR_SW_Msk               /*!< SW[1:0] bits (System clock Switch) */
9118 #define RCC_CFGR_SW_0                            (0x1UL << RCC_CFGR_SW_Pos)     /*!< 0x00000001 */
9119 #define RCC_CFGR_SW_1                            (0x2UL << RCC_CFGR_SW_Pos)     /*!< 0x00000002 */
9120 
9121 #define RCC_CFGR_SW_HSI                          (0x00000000U)                 /*!< HSI selected as system clock */
9122 #define RCC_CFGR_SW_HSE                          (0x00000001U)                 /*!< HSE selected as system clock */
9123 #define RCC_CFGR_SW_PLL                          (0x00000002U)                 /*!< PLL selected as system clock */
9124 
9125 /*!< SWS configuration */
9126 #define RCC_CFGR_SWS_Pos                         (2U)
9127 #define RCC_CFGR_SWS_Msk                         (0x3UL << RCC_CFGR_SWS_Pos)    /*!< 0x0000000C */
9128 #define RCC_CFGR_SWS                             RCC_CFGR_SWS_Msk              /*!< SWS[1:0] bits (System Clock Switch Status) */
9129 #define RCC_CFGR_SWS_0                           (0x1UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000004 */
9130 #define RCC_CFGR_SWS_1                           (0x2UL << RCC_CFGR_SWS_Pos)    /*!< 0x00000008 */
9131 
9132 #define RCC_CFGR_SWS_HSI                         (0x00000000U)                 /*!< HSI oscillator used as system clock */
9133 #define RCC_CFGR_SWS_HSE                         (0x00000004U)                 /*!< HSE oscillator used as system clock */
9134 #define RCC_CFGR_SWS_PLL                         (0x00000008U)                 /*!< PLL used as system clock */
9135 
9136 /*!< HPRE configuration */
9137 #define RCC_CFGR_HPRE_Pos                        (4U)
9138 #define RCC_CFGR_HPRE_Msk                        (0xFUL << RCC_CFGR_HPRE_Pos)   /*!< 0x000000F0 */
9139 #define RCC_CFGR_HPRE                            RCC_CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB prescaler) */
9140 #define RCC_CFGR_HPRE_0                          (0x1UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000010 */
9141 #define RCC_CFGR_HPRE_1                          (0x2UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000020 */
9142 #define RCC_CFGR_HPRE_2                          (0x4UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000040 */
9143 #define RCC_CFGR_HPRE_3                          (0x8UL << RCC_CFGR_HPRE_Pos)   /*!< 0x00000080 */
9144 
9145 #define RCC_CFGR_HPRE_DIV1                       (0x00000000U)                 /*!< SYSCLK not divided */
9146 #define RCC_CFGR_HPRE_DIV2                       (0x00000080U)                 /*!< SYSCLK divided by 2 */
9147 #define RCC_CFGR_HPRE_DIV4                       (0x00000090U)                 /*!< SYSCLK divided by 4 */
9148 #define RCC_CFGR_HPRE_DIV8                       (0x000000A0U)                 /*!< SYSCLK divided by 8 */
9149 #define RCC_CFGR_HPRE_DIV16                      (0x000000B0U)                 /*!< SYSCLK divided by 16 */
9150 #define RCC_CFGR_HPRE_DIV64                      (0x000000C0U)                 /*!< SYSCLK divided by 64 */
9151 #define RCC_CFGR_HPRE_DIV128                     (0x000000D0U)                 /*!< SYSCLK divided by 128 */
9152 #define RCC_CFGR_HPRE_DIV256                     (0x000000E0U)                 /*!< SYSCLK divided by 256 */
9153 #define RCC_CFGR_HPRE_DIV512                     (0x000000F0U)                 /*!< SYSCLK divided by 512 */
9154 
9155 /*!< PPRE1 configuration */
9156 #define RCC_CFGR_PPRE1_Pos                       (8U)
9157 #define RCC_CFGR_PPRE1_Msk                       (0x7UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000700 */
9158 #define RCC_CFGR_PPRE1                           RCC_CFGR_PPRE1_Msk            /*!< PRE1[2:0] bits (APB1 prescaler) */
9159 #define RCC_CFGR_PPRE1_0                         (0x1UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000100 */
9160 #define RCC_CFGR_PPRE1_1                         (0x2UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000200 */
9161 #define RCC_CFGR_PPRE1_2                         (0x4UL << RCC_CFGR_PPRE1_Pos)  /*!< 0x00000400 */
9162 
9163 #define RCC_CFGR_PPRE1_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
9164 #define RCC_CFGR_PPRE1_DIV2                      (0x00000400U)                 /*!< HCLK divided by 2 */
9165 #define RCC_CFGR_PPRE1_DIV4                      (0x00000500U)                 /*!< HCLK divided by 4 */
9166 #define RCC_CFGR_PPRE1_DIV8                      (0x00000600U)                 /*!< HCLK divided by 8 */
9167 #define RCC_CFGR_PPRE1_DIV16                     (0x00000700U)                 /*!< HCLK divided by 16 */
9168 
9169 /*!< PPRE2 configuration */
9170 #define RCC_CFGR_PPRE2_Pos                       (11U)
9171 #define RCC_CFGR_PPRE2_Msk                       (0x7UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00003800 */
9172 #define RCC_CFGR_PPRE2                           RCC_CFGR_PPRE2_Msk            /*!< PRE2[2:0] bits (APB2 prescaler) */
9173 #define RCC_CFGR_PPRE2_0                         (0x1UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00000800 */
9174 #define RCC_CFGR_PPRE2_1                         (0x2UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00001000 */
9175 #define RCC_CFGR_PPRE2_2                         (0x4UL << RCC_CFGR_PPRE2_Pos)  /*!< 0x00002000 */
9176 
9177 #define RCC_CFGR_PPRE2_DIV1                      (0x00000000U)                 /*!< HCLK not divided */
9178 #define RCC_CFGR_PPRE2_DIV2                      (0x00002000U)                 /*!< HCLK divided by 2 */
9179 #define RCC_CFGR_PPRE2_DIV4                      (0x00002800U)                 /*!< HCLK divided by 4 */
9180 #define RCC_CFGR_PPRE2_DIV8                      (0x00003000U)                 /*!< HCLK divided by 8 */
9181 #define RCC_CFGR_PPRE2_DIV16                     (0x00003800U)                 /*!< HCLK divided by 16 */
9182 
9183 #define RCC_CFGR_PLLSRC_Pos                      (16U)
9184 #define RCC_CFGR_PLLSRC_Msk                      (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
9185 #define RCC_CFGR_PLLSRC                          RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */
9186 #define RCC_CFGR_PLLSRC_HSI_DIV2                 (0x00000000U)                 /*!< HSI clock divided by 2 selected as PLL entry clock source */
9187 #define RCC_CFGR_PLLSRC_HSE_PREDIV               (0x00010000U)                 /*!< HSE/PREDIV clock selected as PLL entry clock source */
9188 
9189 #define RCC_CFGR_PLLXTPRE_Pos                    (17U)
9190 #define RCC_CFGR_PLLXTPRE_Msk                    (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
9191 #define RCC_CFGR_PLLXTPRE                        RCC_CFGR_PLLXTPRE_Msk         /*!< HSE divider for PLL entry */
9192 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1        (0x00000000U)                 /*!< HSE/PREDIV clock not divided for PLL entry */
9193 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2        (0x00020000U)                 /*!< HSE/PREDIV clock divided by 2 for PLL entry */
9194 
9195 /*!< PLLMUL configuration */
9196 #define RCC_CFGR_PLLMUL_Pos                      (18U)
9197 #define RCC_CFGR_PLLMUL_Msk                      (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
9198 #define RCC_CFGR_PLLMUL                          RCC_CFGR_PLLMUL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
9199 #define RCC_CFGR_PLLMUL_0                        (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
9200 #define RCC_CFGR_PLLMUL_1                        (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
9201 #define RCC_CFGR_PLLMUL_2                        (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
9202 #define RCC_CFGR_PLLMUL_3                        (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
9203 
9204 #define RCC_CFGR_PLLMUL2                         (0x00000000U)                 /*!< PLL input clock*2 */
9205 #define RCC_CFGR_PLLMUL3                         (0x00040000U)                 /*!< PLL input clock*3 */
9206 #define RCC_CFGR_PLLMUL4                         (0x00080000U)                 /*!< PLL input clock*4 */
9207 #define RCC_CFGR_PLLMUL5                         (0x000C0000U)                 /*!< PLL input clock*5 */
9208 #define RCC_CFGR_PLLMUL6                         (0x00100000U)                 /*!< PLL input clock*6 */
9209 #define RCC_CFGR_PLLMUL7                         (0x00140000U)                 /*!< PLL input clock*7 */
9210 #define RCC_CFGR_PLLMUL8                         (0x00180000U)                 /*!< PLL input clock*8 */
9211 #define RCC_CFGR_PLLMUL9                         (0x001C0000U)                 /*!< PLL input clock*9 */
9212 #define RCC_CFGR_PLLMUL10                        (0x00200000U)                 /*!< PLL input clock10 */
9213 #define RCC_CFGR_PLLMUL11                        (0x00240000U)                 /*!< PLL input clock*11 */
9214 #define RCC_CFGR_PLLMUL12                        (0x00280000U)                 /*!< PLL input clock*12 */
9215 #define RCC_CFGR_PLLMUL13                        (0x002C0000U)                 /*!< PLL input clock*13 */
9216 #define RCC_CFGR_PLLMUL14                        (0x00300000U)                 /*!< PLL input clock*14 */
9217 #define RCC_CFGR_PLLMUL15                        (0x00340000U)                 /*!< PLL input clock*15 */
9218 #define RCC_CFGR_PLLMUL16                        (0x00380000U)                 /*!< PLL input clock*16 */
9219 
9220 /*!< I2S configuration */
9221 #define RCC_CFGR_I2SSRC_Pos                      (23U)
9222 #define RCC_CFGR_I2SSRC_Msk                      (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
9223 #define RCC_CFGR_I2SSRC                          RCC_CFGR_I2SSRC_Msk           /*!< I2S external clock source selection */
9224 
9225 #define RCC_CFGR_I2SSRC_SYSCLK                   (0x00000000U)                 /*!< System clock selected as I2S clock source */
9226 #define RCC_CFGR_I2SSRC_EXT                      (0x00800000U)                 /*!< External clock selected as I2S clock source */
9227 
9228 /*!< MCO configuration */
9229 #define RCC_CFGR_MCO_Pos                         (24U)
9230 #define RCC_CFGR_MCO_Msk                         (0x7UL << RCC_CFGR_MCO_Pos)    /*!< 0x07000000 */
9231 #define RCC_CFGR_MCO                             RCC_CFGR_MCO_Msk              /*!< MCO[2:0] bits (Microcontroller Clock Output) */
9232 #define RCC_CFGR_MCO_0                           (0x1UL << RCC_CFGR_MCO_Pos)    /*!< 0x01000000 */
9233 #define RCC_CFGR_MCO_1                           (0x2UL << RCC_CFGR_MCO_Pos)    /*!< 0x02000000 */
9234 #define RCC_CFGR_MCO_2                           (0x4UL << RCC_CFGR_MCO_Pos)    /*!< 0x04000000 */
9235 
9236 #define RCC_CFGR_MCO_NOCLOCK                     (0x00000000U)                 /*!< No clock */
9237 #define RCC_CFGR_MCO_LSI                         (0x02000000U)                 /*!< LSI clock selected as MCO source */
9238 #define RCC_CFGR_MCO_LSE                         (0x03000000U)                 /*!< LSE clock selected as MCO source */
9239 #define RCC_CFGR_MCO_SYSCLK                      (0x04000000U)                 /*!< System clock selected as MCO source */
9240 #define RCC_CFGR_MCO_HSI                         (0x05000000U)                 /*!< HSI clock selected as MCO source */
9241 #define RCC_CFGR_MCO_HSE                         (0x06000000U)                 /*!< HSE clock selected as MCO source  */
9242 #define RCC_CFGR_MCO_PLL                         (0x07000000U)                 /*!< PLL clock divided by 2 selected as MCO source */
9243 
9244 #define RCC_CFGR_MCOF_Pos                        (28U)
9245 #define RCC_CFGR_MCOF_Msk                        (0x1UL << RCC_CFGR_MCOF_Pos)   /*!< 0x10000000 */
9246 #define RCC_CFGR_MCOF                            RCC_CFGR_MCOF_Msk             /*!< Microcontroller Clock Output Flag */
9247 /* Reference defines */
9248 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
9249 #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
9250 #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
9251 #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
9252 #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
9253 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCO_LSI
9254 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCO_LSE
9255 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
9256 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
9257 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
9258 #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLL
9259 
9260 /*********************  Bit definition for RCC_CIR register  ********************/
9261 #define RCC_CIR_LSIRDYF_Pos                      (0U)
9262 #define RCC_CIR_LSIRDYF_Msk                      (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
9263 #define RCC_CIR_LSIRDYF                          RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
9264 #define RCC_CIR_LSERDYF_Pos                      (1U)
9265 #define RCC_CIR_LSERDYF_Msk                      (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
9266 #define RCC_CIR_LSERDYF                          RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
9267 #define RCC_CIR_HSIRDYF_Pos                      (2U)
9268 #define RCC_CIR_HSIRDYF_Msk                      (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
9269 #define RCC_CIR_HSIRDYF                          RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
9270 #define RCC_CIR_HSERDYF_Pos                      (3U)
9271 #define RCC_CIR_HSERDYF_Msk                      (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
9272 #define RCC_CIR_HSERDYF                          RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
9273 #define RCC_CIR_PLLRDYF_Pos                      (4U)
9274 #define RCC_CIR_PLLRDYF_Msk                      (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
9275 #define RCC_CIR_PLLRDYF                          RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
9276 #define RCC_CIR_CSSF_Pos                         (7U)
9277 #define RCC_CIR_CSSF_Msk                         (0x1UL << RCC_CIR_CSSF_Pos)    /*!< 0x00000080 */
9278 #define RCC_CIR_CSSF                             RCC_CIR_CSSF_Msk              /*!< Clock Security System Interrupt flag */
9279 #define RCC_CIR_LSIRDYIE_Pos                     (8U)
9280 #define RCC_CIR_LSIRDYIE_Msk                     (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
9281 #define RCC_CIR_LSIRDYIE                         RCC_CIR_LSIRDYIE_Msk          /*!< LSI Ready Interrupt Enable */
9282 #define RCC_CIR_LSERDYIE_Pos                     (9U)
9283 #define RCC_CIR_LSERDYIE_Msk                     (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
9284 #define RCC_CIR_LSERDYIE                         RCC_CIR_LSERDYIE_Msk          /*!< LSE Ready Interrupt Enable */
9285 #define RCC_CIR_HSIRDYIE_Pos                     (10U)
9286 #define RCC_CIR_HSIRDYIE_Msk                     (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
9287 #define RCC_CIR_HSIRDYIE                         RCC_CIR_HSIRDYIE_Msk          /*!< HSI Ready Interrupt Enable */
9288 #define RCC_CIR_HSERDYIE_Pos                     (11U)
9289 #define RCC_CIR_HSERDYIE_Msk                     (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
9290 #define RCC_CIR_HSERDYIE                         RCC_CIR_HSERDYIE_Msk          /*!< HSE Ready Interrupt Enable */
9291 #define RCC_CIR_PLLRDYIE_Pos                     (12U)
9292 #define RCC_CIR_PLLRDYIE_Msk                     (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
9293 #define RCC_CIR_PLLRDYIE                         RCC_CIR_PLLRDYIE_Msk          /*!< PLL Ready Interrupt Enable */
9294 #define RCC_CIR_LSIRDYC_Pos                      (16U)
9295 #define RCC_CIR_LSIRDYC_Msk                      (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
9296 #define RCC_CIR_LSIRDYC                          RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
9297 #define RCC_CIR_LSERDYC_Pos                      (17U)
9298 #define RCC_CIR_LSERDYC_Msk                      (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
9299 #define RCC_CIR_LSERDYC                          RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
9300 #define RCC_CIR_HSIRDYC_Pos                      (18U)
9301 #define RCC_CIR_HSIRDYC_Msk                      (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
9302 #define RCC_CIR_HSIRDYC                          RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
9303 #define RCC_CIR_HSERDYC_Pos                      (19U)
9304 #define RCC_CIR_HSERDYC_Msk                      (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
9305 #define RCC_CIR_HSERDYC                          RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
9306 #define RCC_CIR_PLLRDYC_Pos                      (20U)
9307 #define RCC_CIR_PLLRDYC_Msk                      (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
9308 #define RCC_CIR_PLLRDYC                          RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
9309 #define RCC_CIR_CSSC_Pos                         (23U)
9310 #define RCC_CIR_CSSC_Msk                         (0x1UL << RCC_CIR_CSSC_Pos)    /*!< 0x00800000 */
9311 #define RCC_CIR_CSSC                             RCC_CIR_CSSC_Msk              /*!< Clock Security System Interrupt Clear */
9312 
9313 /******************  Bit definition for RCC_APB2RSTR register  *****************/
9314 #define RCC_APB2RSTR_SYSCFGRST_Pos               (0U)
9315 #define RCC_APB2RSTR_SYSCFGRST_Msk               (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
9316 #define RCC_APB2RSTR_SYSCFGRST                   RCC_APB2RSTR_SYSCFGRST_Msk    /*!< SYSCFG reset */
9317 #define RCC_APB2RSTR_TIM1RST_Pos                 (11U)
9318 #define RCC_APB2RSTR_TIM1RST_Msk                 (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
9319 #define RCC_APB2RSTR_TIM1RST                     RCC_APB2RSTR_TIM1RST_Msk      /*!< TIM1 reset */
9320 #define RCC_APB2RSTR_SPI1RST_Pos                 (12U)
9321 #define RCC_APB2RSTR_SPI1RST_Msk                 (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9322 #define RCC_APB2RSTR_SPI1RST                     RCC_APB2RSTR_SPI1RST_Msk      /*!< SPI1 reset */
9323 #define RCC_APB2RSTR_TIM8RST_Pos                 (13U)
9324 #define RCC_APB2RSTR_TIM8RST_Msk                 (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
9325 #define RCC_APB2RSTR_TIM8RST                     RCC_APB2RSTR_TIM8RST_Msk      /*!< TIM8 reset */
9326 #define RCC_APB2RSTR_USART1RST_Pos               (14U)
9327 #define RCC_APB2RSTR_USART1RST_Msk               (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
9328 #define RCC_APB2RSTR_USART1RST                   RCC_APB2RSTR_USART1RST_Msk    /*!< USART1 reset */
9329 #define RCC_APB2RSTR_TIM15RST_Pos                (16U)
9330 #define RCC_APB2RSTR_TIM15RST_Msk                (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
9331 #define RCC_APB2RSTR_TIM15RST                    RCC_APB2RSTR_TIM15RST_Msk     /*!< TIM15 reset */
9332 #define RCC_APB2RSTR_TIM16RST_Pos                (17U)
9333 #define RCC_APB2RSTR_TIM16RST_Msk                (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
9334 #define RCC_APB2RSTR_TIM16RST                    RCC_APB2RSTR_TIM16RST_Msk     /*!< TIM16 reset */
9335 #define RCC_APB2RSTR_TIM17RST_Pos                (18U)
9336 #define RCC_APB2RSTR_TIM17RST_Msk                (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
9337 #define RCC_APB2RSTR_TIM17RST                    RCC_APB2RSTR_TIM17RST_Msk     /*!< TIM17 reset */
9338 
9339 /******************  Bit definition for RCC_APB1RSTR register  ******************/
9340 #define RCC_APB1RSTR_TIM2RST_Pos                 (0U)
9341 #define RCC_APB1RSTR_TIM2RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
9342 #define RCC_APB1RSTR_TIM2RST                     RCC_APB1RSTR_TIM2RST_Msk      /*!< Timer 2 reset */
9343 #define RCC_APB1RSTR_TIM3RST_Pos                 (1U)
9344 #define RCC_APB1RSTR_TIM3RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
9345 #define RCC_APB1RSTR_TIM3RST                     RCC_APB1RSTR_TIM3RST_Msk      /*!< Timer 3 reset */
9346 #define RCC_APB1RSTR_TIM4RST_Pos                 (2U)
9347 #define RCC_APB1RSTR_TIM4RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
9348 #define RCC_APB1RSTR_TIM4RST                     RCC_APB1RSTR_TIM4RST_Msk      /*!< Timer 4 reset */
9349 #define RCC_APB1RSTR_TIM6RST_Pos                 (4U)
9350 #define RCC_APB1RSTR_TIM6RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
9351 #define RCC_APB1RSTR_TIM6RST                     RCC_APB1RSTR_TIM6RST_Msk      /*!< Timer 6 reset */
9352 #define RCC_APB1RSTR_TIM7RST_Pos                 (5U)
9353 #define RCC_APB1RSTR_TIM7RST_Msk                 (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
9354 #define RCC_APB1RSTR_TIM7RST                     RCC_APB1RSTR_TIM7RST_Msk      /*!< Timer 7 reset */
9355 #define RCC_APB1RSTR_WWDGRST_Pos                 (11U)
9356 #define RCC_APB1RSTR_WWDGRST_Msk                 (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
9357 #define RCC_APB1RSTR_WWDGRST                     RCC_APB1RSTR_WWDGRST_Msk      /*!< Window Watchdog reset */
9358 #define RCC_APB1RSTR_SPI2RST_Pos                 (14U)
9359 #define RCC_APB1RSTR_SPI2RST_Msk                 (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
9360 #define RCC_APB1RSTR_SPI2RST                     RCC_APB1RSTR_SPI2RST_Msk      /*!< SPI2 reset */
9361 #define RCC_APB1RSTR_SPI3RST_Pos                 (15U)
9362 #define RCC_APB1RSTR_SPI3RST_Msk                 (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
9363 #define RCC_APB1RSTR_SPI3RST                     RCC_APB1RSTR_SPI3RST_Msk      /*!< SPI3 reset */
9364 #define RCC_APB1RSTR_USART2RST_Pos               (17U)
9365 #define RCC_APB1RSTR_USART2RST_Msk               (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9366 #define RCC_APB1RSTR_USART2RST                   RCC_APB1RSTR_USART2RST_Msk    /*!< USART 2 reset */
9367 #define RCC_APB1RSTR_USART3RST_Pos               (18U)
9368 #define RCC_APB1RSTR_USART3RST_Msk               (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9369 #define RCC_APB1RSTR_USART3RST                   RCC_APB1RSTR_USART3RST_Msk    /*!< USART 3 reset */
9370 #define RCC_APB1RSTR_UART4RST_Pos                (19U)
9371 #define RCC_APB1RSTR_UART4RST_Msk                (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9372 #define RCC_APB1RSTR_UART4RST                    RCC_APB1RSTR_UART4RST_Msk     /*!< UART 4 reset */
9373 #define RCC_APB1RSTR_UART5RST_Pos                (20U)
9374 #define RCC_APB1RSTR_UART5RST_Msk                (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9375 #define RCC_APB1RSTR_UART5RST                    RCC_APB1RSTR_UART5RST_Msk     /*!< UART 5 reset */
9376 #define RCC_APB1RSTR_I2C1RST_Pos                 (21U)
9377 #define RCC_APB1RSTR_I2C1RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
9378 #define RCC_APB1RSTR_I2C1RST                     RCC_APB1RSTR_I2C1RST_Msk      /*!< I2C 1 reset */
9379 #define RCC_APB1RSTR_I2C2RST_Pos                 (22U)
9380 #define RCC_APB1RSTR_I2C2RST_Msk                 (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
9381 #define RCC_APB1RSTR_I2C2RST                     RCC_APB1RSTR_I2C2RST_Msk      /*!< I2C 2 reset */
9382 #define RCC_APB1RSTR_CANRST_Pos                  (25U)
9383 #define RCC_APB1RSTR_CANRST_Msk                  (0x1UL << RCC_APB1RSTR_CANRST_Pos) /*!< 0x02000000 */
9384 #define RCC_APB1RSTR_CANRST                      RCC_APB1RSTR_CANRST_Msk       /*!< CAN reset */
9385 #define RCC_APB1RSTR_PWRRST_Pos                  (28U)
9386 #define RCC_APB1RSTR_PWRRST_Msk                  (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
9387 #define RCC_APB1RSTR_PWRRST                      RCC_APB1RSTR_PWRRST_Msk       /*!< PWR reset */
9388 #define RCC_APB1RSTR_DAC1RST_Pos                 (29U)
9389 #define RCC_APB1RSTR_DAC1RST_Msk                 (0x1UL << RCC_APB1RSTR_DAC1RST_Pos) /*!< 0x20000000 */
9390 #define RCC_APB1RSTR_DAC1RST                     RCC_APB1RSTR_DAC1RST_Msk      /*!< DAC 1 reset */
9391 
9392 /******************  Bit definition for RCC_AHBENR register  ******************/
9393 #define RCC_AHBENR_DMA1EN_Pos                    (0U)
9394 #define RCC_AHBENR_DMA1EN_Msk                    (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
9395 #define RCC_AHBENR_DMA1EN                        RCC_AHBENR_DMA1EN_Msk         /*!< DMA1 clock enable */
9396 #define RCC_AHBENR_DMA2EN_Pos                    (1U)
9397 #define RCC_AHBENR_DMA2EN_Msk                    (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
9398 #define RCC_AHBENR_DMA2EN                        RCC_AHBENR_DMA2EN_Msk         /*!< DMA2 clock enable */
9399 #define RCC_AHBENR_SRAMEN_Pos                    (2U)
9400 #define RCC_AHBENR_SRAMEN_Msk                    (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
9401 #define RCC_AHBENR_SRAMEN                        RCC_AHBENR_SRAMEN_Msk         /*!< SRAM interface clock enable */
9402 #define RCC_AHBENR_FLITFEN_Pos                   (4U)
9403 #define RCC_AHBENR_FLITFEN_Msk                   (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
9404 #define RCC_AHBENR_FLITFEN                       RCC_AHBENR_FLITFEN_Msk        /*!< FLITF clock enable */
9405 #define RCC_AHBENR_CRCEN_Pos                     (6U)
9406 #define RCC_AHBENR_CRCEN_Msk                     (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
9407 #define RCC_AHBENR_CRCEN                         RCC_AHBENR_CRCEN_Msk          /*!< CRC clock enable */
9408 #define RCC_AHBENR_GPIOAEN_Pos                   (17U)
9409 #define RCC_AHBENR_GPIOAEN_Msk                   (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
9410 #define RCC_AHBENR_GPIOAEN                       RCC_AHBENR_GPIOAEN_Msk        /*!< GPIOA clock enable */
9411 #define RCC_AHBENR_GPIOBEN_Pos                   (18U)
9412 #define RCC_AHBENR_GPIOBEN_Msk                   (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
9413 #define RCC_AHBENR_GPIOBEN                       RCC_AHBENR_GPIOBEN_Msk        /*!< GPIOB clock enable */
9414 #define RCC_AHBENR_GPIOCEN_Pos                   (19U)
9415 #define RCC_AHBENR_GPIOCEN_Msk                   (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
9416 #define RCC_AHBENR_GPIOCEN                       RCC_AHBENR_GPIOCEN_Msk        /*!< GPIOC clock enable */
9417 #define RCC_AHBENR_GPIODEN_Pos                   (20U)
9418 #define RCC_AHBENR_GPIODEN_Msk                   (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
9419 #define RCC_AHBENR_GPIODEN                       RCC_AHBENR_GPIODEN_Msk        /*!< GPIOD clock enable */
9420 #define RCC_AHBENR_GPIOEEN_Pos                   (21U)
9421 #define RCC_AHBENR_GPIOEEN_Msk                   (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00200000 */
9422 #define RCC_AHBENR_GPIOEEN                       RCC_AHBENR_GPIOEEN_Msk        /*!< GPIOE clock enable */
9423 #define RCC_AHBENR_GPIOFEN_Pos                   (22U)
9424 #define RCC_AHBENR_GPIOFEN_Msk                   (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
9425 #define RCC_AHBENR_GPIOFEN                       RCC_AHBENR_GPIOFEN_Msk        /*!< GPIOF clock enable */
9426 #define RCC_AHBENR_TSCEN_Pos                     (24U)
9427 #define RCC_AHBENR_TSCEN_Msk                     (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x01000000 */
9428 #define RCC_AHBENR_TSCEN                         RCC_AHBENR_TSCEN_Msk          /*!< TS clock enable */
9429 #define RCC_AHBENR_ADC12EN_Pos                   (28U)
9430 #define RCC_AHBENR_ADC12EN_Msk                   (0x1UL << RCC_AHBENR_ADC12EN_Pos) /*!< 0x10000000 */
9431 #define RCC_AHBENR_ADC12EN                       RCC_AHBENR_ADC12EN_Msk        /*!< ADC1/ ADC2 clock enable */
9432 #define RCC_AHBENR_ADC34EN_Pos                   (29U)
9433 #define RCC_AHBENR_ADC34EN_Msk                   (0x1UL << RCC_AHBENR_ADC34EN_Pos) /*!< 0x20000000 */
9434 #define RCC_AHBENR_ADC34EN                       RCC_AHBENR_ADC34EN_Msk        /*!< ADC3/ ADC4 clock enable */
9435 
9436 /*****************  Bit definition for RCC_APB2ENR register  ******************/
9437 #define RCC_APB2ENR_SYSCFGEN_Pos                 (0U)
9438 #define RCC_APB2ENR_SYSCFGEN_Msk                 (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
9439 #define RCC_APB2ENR_SYSCFGEN                     RCC_APB2ENR_SYSCFGEN_Msk      /*!< SYSCFG clock enable */
9440 #define RCC_APB2ENR_TIM1EN_Pos                   (11U)
9441 #define RCC_APB2ENR_TIM1EN_Msk                   (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
9442 #define RCC_APB2ENR_TIM1EN                       RCC_APB2ENR_TIM1EN_Msk        /*!< TIM1 clock enable */
9443 #define RCC_APB2ENR_SPI1EN_Pos                   (12U)
9444 #define RCC_APB2ENR_SPI1EN_Msk                   (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
9445 #define RCC_APB2ENR_SPI1EN                       RCC_APB2ENR_SPI1EN_Msk        /*!< SPI1 clock enable */
9446 #define RCC_APB2ENR_TIM8EN_Pos                   (13U)
9447 #define RCC_APB2ENR_TIM8EN_Msk                   (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
9448 #define RCC_APB2ENR_TIM8EN                       RCC_APB2ENR_TIM8EN_Msk        /*!< TIM8 clock enable */
9449 #define RCC_APB2ENR_USART1EN_Pos                 (14U)
9450 #define RCC_APB2ENR_USART1EN_Msk                 (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
9451 #define RCC_APB2ENR_USART1EN                     RCC_APB2ENR_USART1EN_Msk      /*!< USART1 clock enable */
9452 #define RCC_APB2ENR_TIM15EN_Pos                  (16U)
9453 #define RCC_APB2ENR_TIM15EN_Msk                  (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
9454 #define RCC_APB2ENR_TIM15EN                      RCC_APB2ENR_TIM15EN_Msk       /*!< TIM15 clock enable */
9455 #define RCC_APB2ENR_TIM16EN_Pos                  (17U)
9456 #define RCC_APB2ENR_TIM16EN_Msk                  (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
9457 #define RCC_APB2ENR_TIM16EN                      RCC_APB2ENR_TIM16EN_Msk       /*!< TIM16 clock enable */
9458 #define RCC_APB2ENR_TIM17EN_Pos                  (18U)
9459 #define RCC_APB2ENR_TIM17EN_Msk                  (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
9460 #define RCC_APB2ENR_TIM17EN                      RCC_APB2ENR_TIM17EN_Msk       /*!< TIM17 clock enable */
9461 
9462 /******************  Bit definition for RCC_APB1ENR register  ******************/
9463 #define RCC_APB1ENR_TIM2EN_Pos                   (0U)
9464 #define RCC_APB1ENR_TIM2EN_Msk                   (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
9465 #define RCC_APB1ENR_TIM2EN                       RCC_APB1ENR_TIM2EN_Msk        /*!< Timer 2 clock enable */
9466 #define RCC_APB1ENR_TIM3EN_Pos                   (1U)
9467 #define RCC_APB1ENR_TIM3EN_Msk                   (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
9468 #define RCC_APB1ENR_TIM3EN                       RCC_APB1ENR_TIM3EN_Msk        /*!< Timer 3 clock enable */
9469 #define RCC_APB1ENR_TIM4EN_Pos                   (2U)
9470 #define RCC_APB1ENR_TIM4EN_Msk                   (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
9471 #define RCC_APB1ENR_TIM4EN                       RCC_APB1ENR_TIM4EN_Msk        /*!< Timer 4 clock enable */
9472 #define RCC_APB1ENR_TIM6EN_Pos                   (4U)
9473 #define RCC_APB1ENR_TIM6EN_Msk                   (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
9474 #define RCC_APB1ENR_TIM6EN                       RCC_APB1ENR_TIM6EN_Msk        /*!< Timer 6 clock enable */
9475 #define RCC_APB1ENR_TIM7EN_Pos                   (5U)
9476 #define RCC_APB1ENR_TIM7EN_Msk                   (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
9477 #define RCC_APB1ENR_TIM7EN                       RCC_APB1ENR_TIM7EN_Msk        /*!< Timer 7 clock enable */
9478 #define RCC_APB1ENR_WWDGEN_Pos                   (11U)
9479 #define RCC_APB1ENR_WWDGEN_Msk                   (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
9480 #define RCC_APB1ENR_WWDGEN                       RCC_APB1ENR_WWDGEN_Msk        /*!< Window Watchdog clock enable */
9481 #define RCC_APB1ENR_SPI2EN_Pos                   (14U)
9482 #define RCC_APB1ENR_SPI2EN_Msk                   (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
9483 #define RCC_APB1ENR_SPI2EN                       RCC_APB1ENR_SPI2EN_Msk        /*!< SPI2 clock enable */
9484 #define RCC_APB1ENR_SPI3EN_Pos                   (15U)
9485 #define RCC_APB1ENR_SPI3EN_Msk                   (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
9486 #define RCC_APB1ENR_SPI3EN                       RCC_APB1ENR_SPI3EN_Msk        /*!< SPI3 clock enable */
9487 #define RCC_APB1ENR_USART2EN_Pos                 (17U)
9488 #define RCC_APB1ENR_USART2EN_Msk                 (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
9489 #define RCC_APB1ENR_USART2EN                     RCC_APB1ENR_USART2EN_Msk      /*!< USART 2 clock enable */
9490 #define RCC_APB1ENR_USART3EN_Pos                 (18U)
9491 #define RCC_APB1ENR_USART3EN_Msk                 (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
9492 #define RCC_APB1ENR_USART3EN                     RCC_APB1ENR_USART3EN_Msk      /*!< USART 3 clock enable */
9493 #define RCC_APB1ENR_UART4EN_Pos                  (19U)
9494 #define RCC_APB1ENR_UART4EN_Msk                  (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
9495 #define RCC_APB1ENR_UART4EN                      RCC_APB1ENR_UART4EN_Msk       /*!< UART 4 clock enable */
9496 #define RCC_APB1ENR_UART5EN_Pos                  (20U)
9497 #define RCC_APB1ENR_UART5EN_Msk                  (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
9498 #define RCC_APB1ENR_UART5EN                      RCC_APB1ENR_UART5EN_Msk       /*!< UART 5 clock enable */
9499 #define RCC_APB1ENR_I2C1EN_Pos                   (21U)
9500 #define RCC_APB1ENR_I2C1EN_Msk                   (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
9501 #define RCC_APB1ENR_I2C1EN                       RCC_APB1ENR_I2C1EN_Msk        /*!< I2C 1 clock enable */
9502 #define RCC_APB1ENR_I2C2EN_Pos                   (22U)
9503 #define RCC_APB1ENR_I2C2EN_Msk                   (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
9504 #define RCC_APB1ENR_I2C2EN                       RCC_APB1ENR_I2C2EN_Msk        /*!< I2C 2 clock enable */
9505 #define RCC_APB1ENR_CANEN_Pos                    (25U)
9506 #define RCC_APB1ENR_CANEN_Msk                    (0x1UL << RCC_APB1ENR_CANEN_Pos) /*!< 0x02000000 */
9507 #define RCC_APB1ENR_CANEN                        RCC_APB1ENR_CANEN_Msk         /*!< CAN clock enable */
9508 #define RCC_APB1ENR_PWREN_Pos                    (28U)
9509 #define RCC_APB1ENR_PWREN_Msk                    (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
9510 #define RCC_APB1ENR_PWREN                        RCC_APB1ENR_PWREN_Msk         /*!< PWR clock enable */
9511 #define RCC_APB1ENR_DAC1EN_Pos                   (29U)
9512 #define RCC_APB1ENR_DAC1EN_Msk                   (0x1UL << RCC_APB1ENR_DAC1EN_Pos) /*!< 0x20000000 */
9513 #define RCC_APB1ENR_DAC1EN                       RCC_APB1ENR_DAC1EN_Msk        /*!< DAC 1 clock enable */
9514 
9515 /********************  Bit definition for RCC_BDCR register  ******************/
9516 #define RCC_BDCR_LSE_Pos                         (0U)
9517 #define RCC_BDCR_LSE_Msk                         (0x7UL << RCC_BDCR_LSE_Pos)    /*!< 0x00000007 */
9518 #define RCC_BDCR_LSE                             RCC_BDCR_LSE_Msk              /*!< External Low Speed oscillator [2:0] bits */
9519 #define RCC_BDCR_LSEON_Pos                       (0U)
9520 #define RCC_BDCR_LSEON_Msk                       (0x1UL << RCC_BDCR_LSEON_Pos)  /*!< 0x00000001 */
9521 #define RCC_BDCR_LSEON                           RCC_BDCR_LSEON_Msk            /*!< External Low Speed oscillator enable */
9522 #define RCC_BDCR_LSERDY_Pos                      (1U)
9523 #define RCC_BDCR_LSERDY_Msk                      (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
9524 #define RCC_BDCR_LSERDY                          RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
9525 #define RCC_BDCR_LSEBYP_Pos                      (2U)
9526 #define RCC_BDCR_LSEBYP_Msk                      (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
9527 #define RCC_BDCR_LSEBYP                          RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */
9528 
9529 #define RCC_BDCR_LSEDRV_Pos                      (3U)
9530 #define RCC_BDCR_LSEDRV_Msk                      (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
9531 #define RCC_BDCR_LSEDRV                          RCC_BDCR_LSEDRV_Msk           /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
9532 #define RCC_BDCR_LSEDRV_0                        (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
9533 #define RCC_BDCR_LSEDRV_1                        (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
9534 
9535 #define RCC_BDCR_RTCSEL_Pos                      (8U)
9536 #define RCC_BDCR_RTCSEL_Msk                      (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
9537 #define RCC_BDCR_RTCSEL                          RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
9538 #define RCC_BDCR_RTCSEL_0                        (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
9539 #define RCC_BDCR_RTCSEL_1                        (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
9540 
9541 /*!< RTC configuration */
9542 #define RCC_BDCR_RTCSEL_NOCLOCK                  (0x00000000U)                 /*!< No clock */
9543 #define RCC_BDCR_RTCSEL_LSE                      (0x00000100U)                 /*!< LSE oscillator clock used as RTC clock */
9544 #define RCC_BDCR_RTCSEL_LSI                      (0x00000200U)                 /*!< LSI oscillator clock used as RTC clock */
9545 #define RCC_BDCR_RTCSEL_HSE                      (0x00000300U)                 /*!< HSE oscillator clock divided by 32 used as RTC clock */
9546 
9547 #define RCC_BDCR_RTCEN_Pos                       (15U)
9548 #define RCC_BDCR_RTCEN_Msk                       (0x1UL << RCC_BDCR_RTCEN_Pos)  /*!< 0x00008000 */
9549 #define RCC_BDCR_RTCEN                           RCC_BDCR_RTCEN_Msk            /*!< RTC clock enable */
9550 #define RCC_BDCR_BDRST_Pos                       (16U)
9551 #define RCC_BDCR_BDRST_Msk                       (0x1UL << RCC_BDCR_BDRST_Pos)  /*!< 0x00010000 */
9552 #define RCC_BDCR_BDRST                           RCC_BDCR_BDRST_Msk            /*!< Backup domain software reset  */
9553 
9554 /********************  Bit definition for RCC_CSR register  *******************/
9555 #define RCC_CSR_LSION_Pos                        (0U)
9556 #define RCC_CSR_LSION_Msk                        (0x1UL << RCC_CSR_LSION_Pos)   /*!< 0x00000001 */
9557 #define RCC_CSR_LSION                            RCC_CSR_LSION_Msk             /*!< Internal Low Speed oscillator enable */
9558 #define RCC_CSR_LSIRDY_Pos                       (1U)
9559 #define RCC_CSR_LSIRDY_Msk                       (0x1UL << RCC_CSR_LSIRDY_Pos)  /*!< 0x00000002 */
9560 #define RCC_CSR_LSIRDY                           RCC_CSR_LSIRDY_Msk            /*!< Internal Low Speed oscillator Ready */
9561 #define RCC_CSR_RMVF_Pos                         (24U)
9562 #define RCC_CSR_RMVF_Msk                         (0x1UL << RCC_CSR_RMVF_Pos)    /*!< 0x01000000 */
9563 #define RCC_CSR_RMVF                             RCC_CSR_RMVF_Msk              /*!< Remove reset flag */
9564 #define RCC_CSR_OBLRSTF_Pos                      (25U)
9565 #define RCC_CSR_OBLRSTF_Msk                      (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
9566 #define RCC_CSR_OBLRSTF                          RCC_CSR_OBLRSTF_Msk           /*!< OBL reset flag */
9567 #define RCC_CSR_PINRSTF_Pos                      (26U)
9568 #define RCC_CSR_PINRSTF_Msk                      (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
9569 #define RCC_CSR_PINRSTF                          RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
9570 #define RCC_CSR_PORRSTF_Pos                      (27U)
9571 #define RCC_CSR_PORRSTF_Msk                      (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
9572 #define RCC_CSR_PORRSTF                          RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
9573 #define RCC_CSR_SFTRSTF_Pos                      (28U)
9574 #define RCC_CSR_SFTRSTF_Msk                      (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
9575 #define RCC_CSR_SFTRSTF                          RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
9576 #define RCC_CSR_IWDGRSTF_Pos                     (29U)
9577 #define RCC_CSR_IWDGRSTF_Msk                     (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
9578 #define RCC_CSR_IWDGRSTF                         RCC_CSR_IWDGRSTF_Msk          /*!< Independent Watchdog reset flag */
9579 #define RCC_CSR_WWDGRSTF_Pos                     (30U)
9580 #define RCC_CSR_WWDGRSTF_Msk                     (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
9581 #define RCC_CSR_WWDGRSTF                         RCC_CSR_WWDGRSTF_Msk          /*!< Window watchdog reset flag */
9582 #define RCC_CSR_LPWRRSTF_Pos                     (31U)
9583 #define RCC_CSR_LPWRRSTF_Msk                     (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
9584 #define RCC_CSR_LPWRRSTF                         RCC_CSR_LPWRRSTF_Msk          /*!< Low-Power reset flag */
9585 
9586 /*******************  Bit definition for RCC_AHBRSTR register  ****************/
9587 #define RCC_AHBRSTR_GPIOARST_Pos                 (17U)
9588 #define RCC_AHBRSTR_GPIOARST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
9589 #define RCC_AHBRSTR_GPIOARST                     RCC_AHBRSTR_GPIOARST_Msk      /*!< GPIOA reset */
9590 #define RCC_AHBRSTR_GPIOBRST_Pos                 (18U)
9591 #define RCC_AHBRSTR_GPIOBRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
9592 #define RCC_AHBRSTR_GPIOBRST                     RCC_AHBRSTR_GPIOBRST_Msk      /*!< GPIOB reset */
9593 #define RCC_AHBRSTR_GPIOCRST_Pos                 (19U)
9594 #define RCC_AHBRSTR_GPIOCRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
9595 #define RCC_AHBRSTR_GPIOCRST                     RCC_AHBRSTR_GPIOCRST_Msk      /*!< GPIOC reset */
9596 #define RCC_AHBRSTR_GPIODRST_Pos                 (20U)
9597 #define RCC_AHBRSTR_GPIODRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
9598 #define RCC_AHBRSTR_GPIODRST                     RCC_AHBRSTR_GPIODRST_Msk      /*!< GPIOD reset */
9599 #define RCC_AHBRSTR_GPIOERST_Pos                 (21U)
9600 #define RCC_AHBRSTR_GPIOERST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00200000 */
9601 #define RCC_AHBRSTR_GPIOERST                     RCC_AHBRSTR_GPIOERST_Msk      /*!< GPIOE reset */
9602 #define RCC_AHBRSTR_GPIOFRST_Pos                 (22U)
9603 #define RCC_AHBRSTR_GPIOFRST_Msk                 (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
9604 #define RCC_AHBRSTR_GPIOFRST                     RCC_AHBRSTR_GPIOFRST_Msk      /*!< GPIOF reset */
9605 #define RCC_AHBRSTR_TSCRST_Pos                   (24U)
9606 #define RCC_AHBRSTR_TSCRST_Msk                   (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x01000000 */
9607 #define RCC_AHBRSTR_TSCRST                       RCC_AHBRSTR_TSCRST_Msk        /*!< TSC reset */
9608 #define RCC_AHBRSTR_ADC12RST_Pos                 (28U)
9609 #define RCC_AHBRSTR_ADC12RST_Msk                 (0x1UL << RCC_AHBRSTR_ADC12RST_Pos) /*!< 0x10000000 */
9610 #define RCC_AHBRSTR_ADC12RST                     RCC_AHBRSTR_ADC12RST_Msk      /*!< ADC1 & ADC2 reset */
9611 #define RCC_AHBRSTR_ADC34RST_Pos                 (29U)
9612 #define RCC_AHBRSTR_ADC34RST_Msk                 (0x1UL << RCC_AHBRSTR_ADC34RST_Pos) /*!< 0x20000000 */
9613 #define RCC_AHBRSTR_ADC34RST                     RCC_AHBRSTR_ADC34RST_Msk      /*!< ADC3 & ADC4 reset */
9614 
9615 /*******************  Bit definition for RCC_CFGR2 register  ******************/
9616 /*!< PREDIV configuration */
9617 #define RCC_CFGR2_PREDIV_Pos                     (0U)
9618 #define RCC_CFGR2_PREDIV_Msk                     (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
9619 #define RCC_CFGR2_PREDIV                         RCC_CFGR2_PREDIV_Msk          /*!< PREDIV[3:0] bits */
9620 #define RCC_CFGR2_PREDIV_0                       (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
9621 #define RCC_CFGR2_PREDIV_1                       (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
9622 #define RCC_CFGR2_PREDIV_2                       (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
9623 #define RCC_CFGR2_PREDIV_3                       (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
9624 
9625 #define RCC_CFGR2_PREDIV_DIV1                    (0x00000000U)                 /*!< PREDIV input clock not divided */
9626 #define RCC_CFGR2_PREDIV_DIV2                    (0x00000001U)                 /*!< PREDIV input clock divided by 2 */
9627 #define RCC_CFGR2_PREDIV_DIV3                    (0x00000002U)                 /*!< PREDIV input clock divided by 3 */
9628 #define RCC_CFGR2_PREDIV_DIV4                    (0x00000003U)                 /*!< PREDIV input clock divided by 4 */
9629 #define RCC_CFGR2_PREDIV_DIV5                    (0x00000004U)                 /*!< PREDIV input clock divided by 5 */
9630 #define RCC_CFGR2_PREDIV_DIV6                    (0x00000005U)                 /*!< PREDIV input clock divided by 6 */
9631 #define RCC_CFGR2_PREDIV_DIV7                    (0x00000006U)                 /*!< PREDIV input clock divided by 7 */
9632 #define RCC_CFGR2_PREDIV_DIV8                    (0x00000007U)                 /*!< PREDIV input clock divided by 8 */
9633 #define RCC_CFGR2_PREDIV_DIV9                    (0x00000008U)                 /*!< PREDIV input clock divided by 9 */
9634 #define RCC_CFGR2_PREDIV_DIV10                   (0x00000009U)                 /*!< PREDIV input clock divided by 10 */
9635 #define RCC_CFGR2_PREDIV_DIV11                   (0x0000000AU)                 /*!< PREDIV input clock divided by 11 */
9636 #define RCC_CFGR2_PREDIV_DIV12                   (0x0000000BU)                 /*!< PREDIV input clock divided by 12 */
9637 #define RCC_CFGR2_PREDIV_DIV13                   (0x0000000CU)                 /*!< PREDIV input clock divided by 13 */
9638 #define RCC_CFGR2_PREDIV_DIV14                   (0x0000000DU)                 /*!< PREDIV input clock divided by 14 */
9639 #define RCC_CFGR2_PREDIV_DIV15                   (0x0000000EU)                 /*!< PREDIV input clock divided by 15 */
9640 #define RCC_CFGR2_PREDIV_DIV16                   (0x0000000FU)                 /*!< PREDIV input clock divided by 16 */
9641 
9642 /*!< ADCPRE12 configuration */
9643 #define RCC_CFGR2_ADCPRE12_Pos                   (4U)
9644 #define RCC_CFGR2_ADCPRE12_Msk                   (0x1FUL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x000001F0 */
9645 #define RCC_CFGR2_ADCPRE12                       RCC_CFGR2_ADCPRE12_Msk        /*!< ADCPRE12[8:4] bits */
9646 #define RCC_CFGR2_ADCPRE12_0                     (0x01UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000010 */
9647 #define RCC_CFGR2_ADCPRE12_1                     (0x02UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000020 */
9648 #define RCC_CFGR2_ADCPRE12_2                     (0x04UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000040 */
9649 #define RCC_CFGR2_ADCPRE12_3                     (0x08UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000080 */
9650 #define RCC_CFGR2_ADCPRE12_4                     (0x10UL << RCC_CFGR2_ADCPRE12_Pos) /*!< 0x00000100 */
9651 
9652 #define RCC_CFGR2_ADCPRE12_NO                    (0x00000000U)                 /*!< ADC12 clock disabled, ADC12 can use AHB clock */
9653 #define RCC_CFGR2_ADCPRE12_DIV1                  (0x00000100U)                 /*!< ADC12 PLL clock divided by 1 */
9654 #define RCC_CFGR2_ADCPRE12_DIV2                  (0x00000110U)                 /*!< ADC12 PLL clock divided by 2 */
9655 #define RCC_CFGR2_ADCPRE12_DIV4                  (0x00000120U)                 /*!< ADC12 PLL clock divided by 4 */
9656 #define RCC_CFGR2_ADCPRE12_DIV6                  (0x00000130U)                 /*!< ADC12 PLL clock divided by 6 */
9657 #define RCC_CFGR2_ADCPRE12_DIV8                  (0x00000140U)                 /*!< ADC12 PLL clock divided by 8 */
9658 #define RCC_CFGR2_ADCPRE12_DIV10                 (0x00000150U)                 /*!< ADC12 PLL clock divided by 10 */
9659 #define RCC_CFGR2_ADCPRE12_DIV12                 (0x00000160U)                 /*!< ADC12 PLL clock divided by 12 */
9660 #define RCC_CFGR2_ADCPRE12_DIV16                 (0x00000170U)                 /*!< ADC12 PLL clock divided by 16 */
9661 #define RCC_CFGR2_ADCPRE12_DIV32                 (0x00000180U)                 /*!< ADC12 PLL clock divided by 32 */
9662 #define RCC_CFGR2_ADCPRE12_DIV64                 (0x00000190U)                 /*!< ADC12 PLL clock divided by 64 */
9663 #define RCC_CFGR2_ADCPRE12_DIV128                (0x000001A0U)                 /*!< ADC12 PLL clock divided by 128 */
9664 #define RCC_CFGR2_ADCPRE12_DIV256                (0x000001B0U)                 /*!< ADC12 PLL clock divided by 256 */
9665 
9666 /*!< ADCPRE34 configuration */
9667 #define RCC_CFGR2_ADCPRE34_Pos                   (9U)
9668 #define RCC_CFGR2_ADCPRE34_Msk                   (0x1FUL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00003E00 */
9669 #define RCC_CFGR2_ADCPRE34                       RCC_CFGR2_ADCPRE34_Msk        /*!< ADCPRE34[13:5] bits */
9670 #define RCC_CFGR2_ADCPRE34_0                     (0x01UL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000200 */
9671 #define RCC_CFGR2_ADCPRE34_1                     (0x02UL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000400 */
9672 #define RCC_CFGR2_ADCPRE34_2                     (0x04UL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00000800 */
9673 #define RCC_CFGR2_ADCPRE34_3                     (0x08UL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00001000 */
9674 #define RCC_CFGR2_ADCPRE34_4                     (0x10UL << RCC_CFGR2_ADCPRE34_Pos) /*!< 0x00002000 */
9675 
9676 #define RCC_CFGR2_ADCPRE34_NO                    (0x00000000U)                 /*!< ADC34 clock disabled, ADC34 can use AHB clock */
9677 #define RCC_CFGR2_ADCPRE34_DIV1                  (0x00002000U)                 /*!< ADC34 PLL clock divided by 1 */
9678 #define RCC_CFGR2_ADCPRE34_DIV2                  (0x00002200U)                 /*!< ADC34 PLL clock divided by 2 */
9679 #define RCC_CFGR2_ADCPRE34_DIV4                  (0x00002400U)                 /*!< ADC34 PLL clock divided by 4 */
9680 #define RCC_CFGR2_ADCPRE34_DIV6                  (0x00002600U)                 /*!< ADC34 PLL clock divided by 6 */
9681 #define RCC_CFGR2_ADCPRE34_DIV8                  (0x00002800U)                 /*!< ADC34 PLL clock divided by 8 */
9682 #define RCC_CFGR2_ADCPRE34_DIV10                 (0x00002A00U)                 /*!< ADC34 PLL clock divided by 10 */
9683 #define RCC_CFGR2_ADCPRE34_DIV12                 (0x00002C00U)                 /*!< ADC34 PLL clock divided by 12 */
9684 #define RCC_CFGR2_ADCPRE34_DIV16                 (0x00002E00U)                 /*!< ADC34 PLL clock divided by 16 */
9685 #define RCC_CFGR2_ADCPRE34_DIV32                 (0x00003000U)                 /*!< ADC34 PLL clock divided by 32 */
9686 #define RCC_CFGR2_ADCPRE34_DIV64                 (0x00003200U)                 /*!< ADC34 PLL clock divided by 64 */
9687 #define RCC_CFGR2_ADCPRE34_DIV128                (0x00003400U)                 /*!< ADC34 PLL clock divided by 128 */
9688 #define RCC_CFGR2_ADCPRE34_DIV256                (0x00003600U)                 /*!< ADC34 PLL clock divided by 256 */
9689 
9690 /*******************  Bit definition for RCC_CFGR3 register  ******************/
9691 #define RCC_CFGR3_USART1SW_Pos                   (0U)
9692 #define RCC_CFGR3_USART1SW_Msk                   (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
9693 #define RCC_CFGR3_USART1SW                       RCC_CFGR3_USART1SW_Msk        /*!< USART1SW[1:0] bits */
9694 #define RCC_CFGR3_USART1SW_0                     (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
9695 #define RCC_CFGR3_USART1SW_1                     (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
9696 
9697 #define RCC_CFGR3_USART1SW_PCLK2                 (0x00000000U)                 /*!< PCLK2 clock used as USART1 clock source */
9698 #define RCC_CFGR3_USART1SW_SYSCLK                (0x00000001U)                 /*!< System clock selected as USART1 clock source */
9699 #define RCC_CFGR3_USART1SW_LSE                   (0x00000002U)                 /*!< LSE oscillator clock used as USART1 clock source */
9700 #define RCC_CFGR3_USART1SW_HSI                   (0x00000003U)                 /*!< HSI oscillator clock used as USART1 clock source */
9701 /* Legacy defines */
9702 #define  RCC_CFGR3_USART1SW_PCLK             RCC_CFGR3_USART1SW_PCLK2
9703 
9704 #define RCC_CFGR3_I2CSW_Pos                      (4U)
9705 #define RCC_CFGR3_I2CSW_Msk                      (0x3UL << RCC_CFGR3_I2CSW_Pos) /*!< 0x00000030 */
9706 #define RCC_CFGR3_I2CSW                          RCC_CFGR3_I2CSW_Msk           /*!< I2CSW bits */
9707 #define RCC_CFGR3_I2C1SW_Pos                     (4U)
9708 #define RCC_CFGR3_I2C1SW_Msk                     (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
9709 #define RCC_CFGR3_I2C1SW                         RCC_CFGR3_I2C1SW_Msk          /*!< I2C1SW bits */
9710 #define RCC_CFGR3_I2C2SW_Pos                     (5U)
9711 #define RCC_CFGR3_I2C2SW_Msk                     (0x1UL << RCC_CFGR3_I2C2SW_Pos) /*!< 0x00000020 */
9712 #define RCC_CFGR3_I2C2SW                         RCC_CFGR3_I2C2SW_Msk          /*!< I2C2SW bits */
9713 
9714 #define RCC_CFGR3_I2C1SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C1 clock source */
9715 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos              (4U)
9716 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk              (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
9717 #define RCC_CFGR3_I2C1SW_SYSCLK                  RCC_CFGR3_I2C1SW_SYSCLK_Msk   /*!< System clock selected as I2C1 clock source */
9718 #define RCC_CFGR3_I2C2SW_HSI                     (0x00000000U)                 /*!< HSI oscillator clock used as I2C2 clock source */
9719 #define RCC_CFGR3_I2C2SW_SYSCLK_Pos              (5U)
9720 #define RCC_CFGR3_I2C2SW_SYSCLK_Msk              (0x1UL << RCC_CFGR3_I2C2SW_SYSCLK_Pos) /*!< 0x00000020 */
9721 #define RCC_CFGR3_I2C2SW_SYSCLK                  RCC_CFGR3_I2C2SW_SYSCLK_Msk   /*!< System clock selected as I2C2 clock source */
9722 #define RCC_CFGR3_TIMSW_Pos                      (8U)
9723 #define RCC_CFGR3_TIMSW_Msk                      (0x3UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000300 */
9724 #define RCC_CFGR3_TIMSW                          RCC_CFGR3_TIMSW_Msk           /*!< TIMSW bits */
9725 #define RCC_CFGR3_TIM1SW_Pos                     (8U)
9726 #define RCC_CFGR3_TIM1SW_Msk                     (0x1UL << RCC_CFGR3_TIM1SW_Pos) /*!< 0x00000100 */
9727 #define RCC_CFGR3_TIM1SW                         RCC_CFGR3_TIM1SW_Msk          /*!< TIM1SW bits */
9728 #define RCC_CFGR3_TIM8SW_Pos                     (9U)
9729 #define RCC_CFGR3_TIM8SW_Msk                     (0x1UL << RCC_CFGR3_TIM8SW_Pos) /*!< 0x00000200 */
9730 #define RCC_CFGR3_TIM8SW                         RCC_CFGR3_TIM8SW_Msk          /*!< TIM8SW bits */
9731 #define RCC_CFGR3_TIM1SW_PCLK2                   (0x00000000U)                 /*!< PCLK2 used as TIM1 clock source */
9732 #define RCC_CFGR3_TIM1SW_PLL_Pos                 (8U)
9733 #define RCC_CFGR3_TIM1SW_PLL_Msk                 (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos) /*!< 0x00000100 */
9734 #define RCC_CFGR3_TIM1SW_PLL                     RCC_CFGR3_TIM1SW_PLL_Msk      /*!< PLL clock used as TIM1 clock source */
9735 #define RCC_CFGR3_TIM8SW_PCLK2                   (0x00000000U)                 /*!< PCLK2 used as TIM8 clock source */
9736 #define RCC_CFGR3_TIM8SW_PLL_Pos                 (9U)
9737 #define RCC_CFGR3_TIM8SW_PLL_Msk                 (0x1UL << RCC_CFGR3_TIM8SW_PLL_Pos) /*!< 0x00000200 */
9738 #define RCC_CFGR3_TIM8SW_PLL                     RCC_CFGR3_TIM8SW_PLL_Msk      /*!< PLL clock used as TIM8 clock source */
9739 
9740 #define RCC_CFGR3_USART2SW_Pos                   (16U)
9741 #define RCC_CFGR3_USART2SW_Msk                   (0x3UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00030000 */
9742 #define RCC_CFGR3_USART2SW                       RCC_CFGR3_USART2SW_Msk        /*!< USART2SW[1:0] bits */
9743 #define RCC_CFGR3_USART2SW_0                     (0x1UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00010000 */
9744 #define RCC_CFGR3_USART2SW_1                     (0x2UL << RCC_CFGR3_USART2SW_Pos) /*!< 0x00020000 */
9745 
9746 #define RCC_CFGR3_USART2SW_PCLK                  (0x00000000U)                 /*!< PCLK1 clock used as USART2 clock source */
9747 #define RCC_CFGR3_USART2SW_SYSCLK                (0x00010000U)                 /*!< System clock selected as USART2 clock source */
9748 #define RCC_CFGR3_USART2SW_LSE                   (0x00020000U)                 /*!< LSE oscillator clock used as USART2 clock source */
9749 #define RCC_CFGR3_USART2SW_HSI                   (0x00030000U)                 /*!< HSI oscillator clock used as USART2 clock source */
9750 
9751 #define RCC_CFGR3_USART3SW_Pos                   (18U)
9752 #define RCC_CFGR3_USART3SW_Msk                   (0x3UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x000C0000 */
9753 #define RCC_CFGR3_USART3SW                       RCC_CFGR3_USART3SW_Msk        /*!< USART3SW[1:0] bits */
9754 #define RCC_CFGR3_USART3SW_0                     (0x1UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x00040000 */
9755 #define RCC_CFGR3_USART3SW_1                     (0x2UL << RCC_CFGR3_USART3SW_Pos) /*!< 0x00080000 */
9756 
9757 #define RCC_CFGR3_USART3SW_PCLK                  (0x00000000U)                 /*!< PCLK1 clock used as USART3 clock source */
9758 #define RCC_CFGR3_USART3SW_SYSCLK                (0x00040000U)                 /*!< System clock selected as USART3 clock source */
9759 #define RCC_CFGR3_USART3SW_LSE                   (0x00080000U)                 /*!< LSE oscillator clock used as USART3 clock source */
9760 #define RCC_CFGR3_USART3SW_HSI                   (0x000C0000U)                 /*!< HSI oscillator clock used as USART3 clock source */
9761 
9762 #define RCC_CFGR3_UART4SW_Pos                    (20U)
9763 #define RCC_CFGR3_UART4SW_Msk                    (0x3UL << RCC_CFGR3_UART4SW_Pos) /*!< 0x00300000 */
9764 #define RCC_CFGR3_UART4SW                        RCC_CFGR3_UART4SW_Msk         /*!< UART4SW[1:0] bits */
9765 #define RCC_CFGR3_UART4SW_0                      (0x1UL << RCC_CFGR3_UART4SW_Pos) /*!< 0x00100000 */
9766 #define RCC_CFGR3_UART4SW_1                      (0x2UL << RCC_CFGR3_UART4SW_Pos) /*!< 0x00200000 */
9767 
9768 #define RCC_CFGR3_UART4SW_PCLK                   (0x00000000U)                 /*!< PCLK1 clock used as UART4 clock source */
9769 #define RCC_CFGR3_UART4SW_SYSCLK                 (0x00100000U)                 /*!< System clock selected as UART4 clock source */
9770 #define RCC_CFGR3_UART4SW_LSE                    (0x00200000U)                 /*!< LSE oscillator clock used as UART4 clock source */
9771 #define RCC_CFGR3_UART4SW_HSI                    (0x00300000U)                 /*!< HSI oscillator clock used as UART4 clock source */
9772 
9773 #define RCC_CFGR3_UART5SW_Pos                    (22U)
9774 #define RCC_CFGR3_UART5SW_Msk                    (0x3UL << RCC_CFGR3_UART5SW_Pos) /*!< 0x00C00000 */
9775 #define RCC_CFGR3_UART5SW                        RCC_CFGR3_UART5SW_Msk         /*!< UART5SW[1:0] bits */
9776 #define RCC_CFGR3_UART5SW_0                      (0x1UL << RCC_CFGR3_UART5SW_Pos) /*!< 0x00400000 */
9777 #define RCC_CFGR3_UART5SW_1                      (0x2UL << RCC_CFGR3_UART5SW_Pos) /*!< 0x00800000 */
9778 
9779 #define RCC_CFGR3_UART5SW_PCLK                   (0x00000000U)                 /*!< PCLK1 clock used as UART5 clock source */
9780 #define RCC_CFGR3_UART5SW_SYSCLK                 (0x00400000U)                 /*!< System clock selected as UART5 clock source */
9781 #define RCC_CFGR3_UART5SW_LSE                    (0x00800000U)                 /*!< LSE oscillator clock used as UART5 clock source */
9782 #define RCC_CFGR3_UART5SW_HSI                    (0x00C00000U)                 /*!< HSI oscillator clock used as UART5 clock source */
9783 
9784 /* Legacy defines */
9785 #define  RCC_CFGR3_TIM1SW_HCLK                RCC_CFGR3_TIM1SW_PCLK2
9786 #define  RCC_CFGR3_TIM8SW_HCLK                RCC_CFGR3_TIM8SW_PCLK2
9787 
9788 /******************************************************************************/
9789 /*                                                                            */
9790 /*                           Real-Time Clock (RTC)                            */
9791 /*                                                                            */
9792 /******************************************************************************/
9793 /*
9794 * @brief Specific device feature definitions  (not present on all devices in the STM32F3 series)
9795 */
9796 #define RTC_TAMPER1_SUPPORT  /*!< TAMPER 1 feature support */
9797 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
9798 #define RTC_TAMPER3_SUPPORT  /*!< TAMPER 3 feature support */
9799 #define RTC_BACKUP_SUPPORT   /*!< BACKUP register feature support */
9800 #define RTC_WAKEUP_SUPPORT   /*!< WAKEUP feature support */
9801 
9802 /********************  Bits definition for RTC_TR register  *******************/
9803 #define RTC_TR_PM_Pos                (22U)
9804 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
9805 #define RTC_TR_PM                    RTC_TR_PM_Msk
9806 #define RTC_TR_HT_Pos                (20U)
9807 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
9808 #define RTC_TR_HT                    RTC_TR_HT_Msk
9809 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
9810 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
9811 #define RTC_TR_HU_Pos                (16U)
9812 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
9813 #define RTC_TR_HU                    RTC_TR_HU_Msk
9814 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
9815 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
9816 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
9817 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
9818 #define RTC_TR_MNT_Pos               (12U)
9819 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
9820 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
9821 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
9822 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
9823 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
9824 #define RTC_TR_MNU_Pos               (8U)
9825 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
9826 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
9827 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
9828 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
9829 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
9830 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
9831 #define RTC_TR_ST_Pos                (4U)
9832 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
9833 #define RTC_TR_ST                    RTC_TR_ST_Msk
9834 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
9835 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
9836 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
9837 #define RTC_TR_SU_Pos                (0U)
9838 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
9839 #define RTC_TR_SU                    RTC_TR_SU_Msk
9840 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
9841 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
9842 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
9843 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
9844 
9845 /********************  Bits definition for RTC_DR register  *******************/
9846 #define RTC_DR_YT_Pos                (20U)
9847 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
9848 #define RTC_DR_YT                    RTC_DR_YT_Msk
9849 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
9850 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
9851 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
9852 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
9853 #define RTC_DR_YU_Pos                (16U)
9854 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
9855 #define RTC_DR_YU                    RTC_DR_YU_Msk
9856 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
9857 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
9858 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
9859 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
9860 #define RTC_DR_WDU_Pos               (13U)
9861 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
9862 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
9863 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
9864 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
9865 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
9866 #define RTC_DR_MT_Pos                (12U)
9867 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
9868 #define RTC_DR_MT                    RTC_DR_MT_Msk
9869 #define RTC_DR_MU_Pos                (8U)
9870 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
9871 #define RTC_DR_MU                    RTC_DR_MU_Msk
9872 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
9873 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
9874 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
9875 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
9876 #define RTC_DR_DT_Pos                (4U)
9877 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
9878 #define RTC_DR_DT                    RTC_DR_DT_Msk
9879 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
9880 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
9881 #define RTC_DR_DU_Pos                (0U)
9882 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
9883 #define RTC_DR_DU                    RTC_DR_DU_Msk
9884 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
9885 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
9886 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
9887 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
9888 
9889 /********************  Bits definition for RTC_CR register  *******************/
9890 #define RTC_CR_COE_Pos               (23U)
9891 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                  /*!< 0x00800000 */
9892 #define RTC_CR_COE                   RTC_CR_COE_Msk
9893 #define RTC_CR_OSEL_Pos              (21U)
9894 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
9895 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
9896 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
9897 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
9898 #define RTC_CR_POL_Pos               (20U)
9899 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
9900 #define RTC_CR_POL                   RTC_CR_POL_Msk
9901 #define RTC_CR_COSEL_Pos             (19U)
9902 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
9903 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
9904 #define RTC_CR_BKP_Pos               (18U)
9905 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
9906 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
9907 #define RTC_CR_SUB1H_Pos             (17U)
9908 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
9909 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
9910 #define RTC_CR_ADD1H_Pos             (16U)
9911 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
9912 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
9913 #define RTC_CR_TSIE_Pos              (15U)
9914 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                 /*!< 0x00008000 */
9915 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
9916 #define RTC_CR_WUTIE_Pos             (14U)
9917 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)                /*!< 0x00004000 */
9918 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
9919 #define RTC_CR_ALRBIE_Pos            (13U)
9920 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)               /*!< 0x00002000 */
9921 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
9922 #define RTC_CR_ALRAIE_Pos            (12U)
9923 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)               /*!< 0x00001000 */
9924 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
9925 #define RTC_CR_TSE_Pos               (11U)
9926 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                  /*!< 0x00000800 */
9927 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
9928 #define RTC_CR_WUTE_Pos              (10U)
9929 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                 /*!< 0x00000400 */
9930 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
9931 #define RTC_CR_ALRBE_Pos             (9U)
9932 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)                /*!< 0x00000200 */
9933 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
9934 #define RTC_CR_ALRAE_Pos             (8U)
9935 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
9936 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
9937 #define RTC_CR_FMT_Pos               (6U)
9938 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
9939 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
9940 #define RTC_CR_BYPSHAD_Pos           (5U)
9941 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
9942 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
9943 #define RTC_CR_REFCKON_Pos           (4U)
9944 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
9945 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
9946 #define RTC_CR_TSEDGE_Pos            (3U)
9947 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)               /*!< 0x00000008 */
9948 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
9949 #define RTC_CR_WUCKSEL_Pos           (0U)
9950 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000007 */
9951 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
9952 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000001 */
9953 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
9954 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
9955 
9956 /* Legacy defines */
9957 #define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
9958 #define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
9959 #define RTC_CR_BCK                   RTC_CR_BKP
9960 
9961 /********************  Bits definition for RTC_ISR register  ******************/
9962 #define RTC_ISR_RECALPF_Pos          (16U)
9963 #define RTC_ISR_RECALPF_Msk          (0x1UL << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
9964 #define RTC_ISR_RECALPF              RTC_ISR_RECALPF_Msk
9965 #define RTC_ISR_TAMP3F_Pos           (15U)
9966 #define RTC_ISR_TAMP3F_Msk           (0x1UL << RTC_ISR_TAMP3F_Pos)              /*!< 0x00008000 */
9967 #define RTC_ISR_TAMP3F               RTC_ISR_TAMP3F_Msk
9968 #define RTC_ISR_TAMP2F_Pos           (14U)
9969 #define RTC_ISR_TAMP2F_Msk           (0x1UL << RTC_ISR_TAMP2F_Pos)              /*!< 0x00004000 */
9970 #define RTC_ISR_TAMP2F               RTC_ISR_TAMP2F_Msk
9971 #define RTC_ISR_TAMP1F_Pos           (13U)
9972 #define RTC_ISR_TAMP1F_Msk           (0x1UL << RTC_ISR_TAMP1F_Pos)              /*!< 0x00002000 */
9973 #define RTC_ISR_TAMP1F               RTC_ISR_TAMP1F_Msk
9974 #define RTC_ISR_TSOVF_Pos            (12U)
9975 #define RTC_ISR_TSOVF_Msk            (0x1UL << RTC_ISR_TSOVF_Pos)               /*!< 0x00001000 */
9976 #define RTC_ISR_TSOVF                RTC_ISR_TSOVF_Msk
9977 #define RTC_ISR_TSF_Pos              (11U)
9978 #define RTC_ISR_TSF_Msk              (0x1UL << RTC_ISR_TSF_Pos)                 /*!< 0x00000800 */
9979 #define RTC_ISR_TSF                  RTC_ISR_TSF_Msk
9980 #define RTC_ISR_WUTF_Pos             (10U)
9981 #define RTC_ISR_WUTF_Msk             (0x1UL << RTC_ISR_WUTF_Pos)                /*!< 0x00000400 */
9982 #define RTC_ISR_WUTF                 RTC_ISR_WUTF_Msk
9983 #define RTC_ISR_ALRBF_Pos            (9U)
9984 #define RTC_ISR_ALRBF_Msk            (0x1UL << RTC_ISR_ALRBF_Pos)               /*!< 0x00000200 */
9985 #define RTC_ISR_ALRBF                RTC_ISR_ALRBF_Msk
9986 #define RTC_ISR_ALRAF_Pos            (8U)
9987 #define RTC_ISR_ALRAF_Msk            (0x1UL << RTC_ISR_ALRAF_Pos)               /*!< 0x00000100 */
9988 #define RTC_ISR_ALRAF                RTC_ISR_ALRAF_Msk
9989 #define RTC_ISR_INIT_Pos             (7U)
9990 #define RTC_ISR_INIT_Msk             (0x1UL << RTC_ISR_INIT_Pos)                /*!< 0x00000080 */
9991 #define RTC_ISR_INIT                 RTC_ISR_INIT_Msk
9992 #define RTC_ISR_INITF_Pos            (6U)
9993 #define RTC_ISR_INITF_Msk            (0x1UL << RTC_ISR_INITF_Pos)               /*!< 0x00000040 */
9994 #define RTC_ISR_INITF                RTC_ISR_INITF_Msk
9995 #define RTC_ISR_RSF_Pos              (5U)
9996 #define RTC_ISR_RSF_Msk              (0x1UL << RTC_ISR_RSF_Pos)                 /*!< 0x00000020 */
9997 #define RTC_ISR_RSF                  RTC_ISR_RSF_Msk
9998 #define RTC_ISR_INITS_Pos            (4U)
9999 #define RTC_ISR_INITS_Msk            (0x1UL << RTC_ISR_INITS_Pos)               /*!< 0x00000010 */
10000 #define RTC_ISR_INITS                RTC_ISR_INITS_Msk
10001 #define RTC_ISR_SHPF_Pos             (3U)
10002 #define RTC_ISR_SHPF_Msk             (0x1UL << RTC_ISR_SHPF_Pos)                /*!< 0x00000008 */
10003 #define RTC_ISR_SHPF                 RTC_ISR_SHPF_Msk
10004 #define RTC_ISR_WUTWF_Pos            (2U)
10005 #define RTC_ISR_WUTWF_Msk            (0x1UL << RTC_ISR_WUTWF_Pos)               /*!< 0x00000004 */
10006 #define RTC_ISR_WUTWF                RTC_ISR_WUTWF_Msk
10007 #define RTC_ISR_ALRBWF_Pos           (1U)
10008 #define RTC_ISR_ALRBWF_Msk           (0x1UL << RTC_ISR_ALRBWF_Pos)              /*!< 0x00000002 */
10009 #define RTC_ISR_ALRBWF               RTC_ISR_ALRBWF_Msk
10010 #define RTC_ISR_ALRAWF_Pos           (0U)
10011 #define RTC_ISR_ALRAWF_Msk           (0x1UL << RTC_ISR_ALRAWF_Pos)              /*!< 0x00000001 */
10012 #define RTC_ISR_ALRAWF               RTC_ISR_ALRAWF_Msk
10013 
10014 /********************  Bits definition for RTC_PRER register  *****************/
10015 #define RTC_PRER_PREDIV_A_Pos        (16U)
10016 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
10017 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
10018 #define RTC_PRER_PREDIV_S_Pos        (0U)
10019 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
10020 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
10021 
10022 /********************  Bits definition for RTC_WUTR register  *****************/
10023 #define RTC_WUTR_WUT_Pos             (0U)
10024 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)             /*!< 0x0000FFFF */
10025 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
10026 
10027 /********************  Bits definition for RTC_ALRMAR register  ***************/
10028 #define RTC_ALRMAR_MSK4_Pos          (31U)
10029 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)             /*!< 0x80000000 */
10030 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
10031 #define RTC_ALRMAR_WDSEL_Pos         (30U)
10032 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)            /*!< 0x40000000 */
10033 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
10034 #define RTC_ALRMAR_DT_Pos            (28U)
10035 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)               /*!< 0x30000000 */
10036 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
10037 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)               /*!< 0x10000000 */
10038 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)               /*!< 0x20000000 */
10039 #define RTC_ALRMAR_DU_Pos            (24U)
10040 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)               /*!< 0x0F000000 */
10041 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
10042 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)               /*!< 0x01000000 */
10043 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)               /*!< 0x02000000 */
10044 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)               /*!< 0x04000000 */
10045 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)               /*!< 0x08000000 */
10046 #define RTC_ALRMAR_MSK3_Pos          (23U)
10047 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)             /*!< 0x00800000 */
10048 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
10049 #define RTC_ALRMAR_PM_Pos            (22U)
10050 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)               /*!< 0x00400000 */
10051 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
10052 #define RTC_ALRMAR_HT_Pos            (20U)
10053 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00300000 */
10054 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
10055 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00100000 */
10056 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)               /*!< 0x00200000 */
10057 #define RTC_ALRMAR_HU_Pos            (16U)
10058 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)               /*!< 0x000F0000 */
10059 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
10060 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00010000 */
10061 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00020000 */
10062 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00040000 */
10063 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)               /*!< 0x00080000 */
10064 #define RTC_ALRMAR_MSK2_Pos          (15U)
10065 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)             /*!< 0x00008000 */
10066 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
10067 #define RTC_ALRMAR_MNT_Pos           (12U)
10068 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00007000 */
10069 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
10070 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00001000 */
10071 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00002000 */
10072 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)              /*!< 0x00004000 */
10073 #define RTC_ALRMAR_MNU_Pos           (8U)
10074 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000F00 */
10075 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
10076 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000100 */
10077 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000200 */
10078 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000400 */
10079 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)              /*!< 0x00000800 */
10080 #define RTC_ALRMAR_MSK1_Pos          (7U)
10081 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)             /*!< 0x00000080 */
10082 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
10083 #define RTC_ALRMAR_ST_Pos            (4U)
10084 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000070 */
10085 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
10086 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000010 */
10087 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000020 */
10088 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)               /*!< 0x00000040 */
10089 #define RTC_ALRMAR_SU_Pos            (0U)
10090 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)               /*!< 0x0000000F */
10091 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
10092 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000001 */
10093 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000002 */
10094 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000004 */
10095 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)               /*!< 0x00000008 */
10096 
10097 /********************  Bits definition for RTC_ALRMBR register  ***************/
10098 #define RTC_ALRMBR_MSK4_Pos          (31U)
10099 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)             /*!< 0x80000000 */
10100 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
10101 #define RTC_ALRMBR_WDSEL_Pos         (30U)
10102 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)            /*!< 0x40000000 */
10103 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
10104 #define RTC_ALRMBR_DT_Pos            (28U)
10105 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)               /*!< 0x30000000 */
10106 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
10107 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)               /*!< 0x10000000 */
10108 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)               /*!< 0x20000000 */
10109 #define RTC_ALRMBR_DU_Pos            (24U)
10110 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)               /*!< 0x0F000000 */
10111 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
10112 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)               /*!< 0x01000000 */
10113 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)               /*!< 0x02000000 */
10114 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)               /*!< 0x04000000 */
10115 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)               /*!< 0x08000000 */
10116 #define RTC_ALRMBR_MSK3_Pos          (23U)
10117 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)             /*!< 0x00800000 */
10118 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
10119 #define RTC_ALRMBR_PM_Pos            (22U)
10120 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)               /*!< 0x00400000 */
10121 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
10122 #define RTC_ALRMBR_HT_Pos            (20U)
10123 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00300000 */
10124 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
10125 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00100000 */
10126 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)               /*!< 0x00200000 */
10127 #define RTC_ALRMBR_HU_Pos            (16U)
10128 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)               /*!< 0x000F0000 */
10129 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
10130 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00010000 */
10131 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00020000 */
10132 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00040000 */
10133 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)               /*!< 0x00080000 */
10134 #define RTC_ALRMBR_MSK2_Pos          (15U)
10135 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)             /*!< 0x00008000 */
10136 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
10137 #define RTC_ALRMBR_MNT_Pos           (12U)
10138 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00007000 */
10139 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
10140 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00001000 */
10141 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00002000 */
10142 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)              /*!< 0x00004000 */
10143 #define RTC_ALRMBR_MNU_Pos           (8U)
10144 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000F00 */
10145 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
10146 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000100 */
10147 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000200 */
10148 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000400 */
10149 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)              /*!< 0x00000800 */
10150 #define RTC_ALRMBR_MSK1_Pos          (7U)
10151 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)             /*!< 0x00000080 */
10152 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
10153 #define RTC_ALRMBR_ST_Pos            (4U)
10154 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000070 */
10155 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
10156 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000010 */
10157 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000020 */
10158 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)               /*!< 0x00000040 */
10159 #define RTC_ALRMBR_SU_Pos            (0U)
10160 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)               /*!< 0x0000000F */
10161 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
10162 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000001 */
10163 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000002 */
10164 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000004 */
10165 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)               /*!< 0x00000008 */
10166 
10167 /********************  Bits definition for RTC_WPR register  ******************/
10168 #define RTC_WPR_KEY_Pos              (0U)
10169 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
10170 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
10171 
10172 /********************  Bits definition for RTC_SSR register  ******************/
10173 #define RTC_SSR_SS_Pos               (0U)
10174 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
10175 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
10176 
10177 /********************  Bits definition for RTC_SHIFTR register  ***************/
10178 #define RTC_SHIFTR_SUBFS_Pos         (0U)
10179 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
10180 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
10181 #define RTC_SHIFTR_ADD1S_Pos         (31U)
10182 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
10183 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
10184 
10185 /********************  Bits definition for RTC_TSTR register  *****************/
10186 #define RTC_TSTR_PM_Pos              (22U)
10187 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                 /*!< 0x00400000 */
10188 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
10189 #define RTC_TSTR_HT_Pos              (20U)
10190 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                 /*!< 0x00300000 */
10191 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
10192 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                 /*!< 0x00100000 */
10193 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                 /*!< 0x00200000 */
10194 #define RTC_TSTR_HU_Pos              (16U)
10195 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                 /*!< 0x000F0000 */
10196 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
10197 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                 /*!< 0x00010000 */
10198 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                 /*!< 0x00020000 */
10199 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                 /*!< 0x00040000 */
10200 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                 /*!< 0x00080000 */
10201 #define RTC_TSTR_MNT_Pos             (12U)
10202 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)                /*!< 0x00007000 */
10203 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
10204 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)                /*!< 0x00001000 */
10205 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)                /*!< 0x00002000 */
10206 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
10207 #define RTC_TSTR_MNU_Pos             (8U)
10208 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
10209 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
10210 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
10211 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
10212 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
10213 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
10214 #define RTC_TSTR_ST_Pos              (4U)
10215 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
10216 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
10217 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
10218 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
10219 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
10220 #define RTC_TSTR_SU_Pos              (0U)
10221 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
10222 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
10223 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
10224 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
10225 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
10226 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
10227 
10228 /********************  Bits definition for RTC_TSDR register  *****************/
10229 #define RTC_TSDR_WDU_Pos             (13U)
10230 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)                /*!< 0x0000E000 */
10231 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
10232 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)                /*!< 0x00002000 */
10233 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)                /*!< 0x00004000 */
10234 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)                /*!< 0x00008000 */
10235 #define RTC_TSDR_MT_Pos              (12U)
10236 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                 /*!< 0x00001000 */
10237 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
10238 #define RTC_TSDR_MU_Pos              (8U)
10239 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                 /*!< 0x00000F00 */
10240 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
10241 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000100 */
10242 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000200 */
10243 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000400 */
10244 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                 /*!< 0x00000800 */
10245 #define RTC_TSDR_DT_Pos              (4U)
10246 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000030 */
10247 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
10248 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000010 */
10249 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                 /*!< 0x00000020 */
10250 #define RTC_TSDR_DU_Pos              (0U)
10251 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                 /*!< 0x0000000F */
10252 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
10253 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000001 */
10254 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000002 */
10255 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000004 */
10256 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                 /*!< 0x00000008 */
10257 
10258 /********************  Bits definition for RTC_TSSSR register  ****************/
10259 #define RTC_TSSSR_SS_Pos             (0U)
10260 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
10261 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
10262 
10263 /********************  Bits definition for RTC_CAL register  *****************/
10264 #define RTC_CALR_CALP_Pos            (15U)
10265 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
10266 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
10267 #define RTC_CALR_CALW8_Pos           (14U)
10268 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
10269 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
10270 #define RTC_CALR_CALW16_Pos          (13U)
10271 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
10272 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
10273 #define RTC_CALR_CALM_Pos            (0U)
10274 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
10275 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
10276 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
10277 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
10278 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
10279 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
10280 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
10281 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
10282 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
10283 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
10284 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
10285 
10286 /********************  Bits definition for RTC_TAFCR register  ****************/
10287 #define RTC_TAFCR_PC15MODE_Pos       (23U)
10288 #define RTC_TAFCR_PC15MODE_Msk       (0x1UL << RTC_TAFCR_PC15MODE_Pos)          /*!< 0x00800000 */
10289 #define RTC_TAFCR_PC15MODE           RTC_TAFCR_PC15MODE_Msk
10290 #define RTC_TAFCR_PC15VALUE_Pos      (22U)
10291 #define RTC_TAFCR_PC15VALUE_Msk      (0x1UL << RTC_TAFCR_PC15VALUE_Pos)         /*!< 0x00400000 */
10292 #define RTC_TAFCR_PC15VALUE          RTC_TAFCR_PC15VALUE_Msk
10293 #define RTC_TAFCR_PC14MODE_Pos       (21U)
10294 #define RTC_TAFCR_PC14MODE_Msk       (0x1UL << RTC_TAFCR_PC14MODE_Pos)          /*!< 0x00200000 */
10295 #define RTC_TAFCR_PC14MODE           RTC_TAFCR_PC14MODE_Msk
10296 #define RTC_TAFCR_PC14VALUE_Pos      (20U)
10297 #define RTC_TAFCR_PC14VALUE_Msk      (0x1UL << RTC_TAFCR_PC14VALUE_Pos)         /*!< 0x00100000 */
10298 #define RTC_TAFCR_PC14VALUE          RTC_TAFCR_PC14VALUE_Msk
10299 #define RTC_TAFCR_PC13MODE_Pos       (19U)
10300 #define RTC_TAFCR_PC13MODE_Msk       (0x1UL << RTC_TAFCR_PC13MODE_Pos)          /*!< 0x00080000 */
10301 #define RTC_TAFCR_PC13MODE           RTC_TAFCR_PC13MODE_Msk
10302 #define RTC_TAFCR_PC13VALUE_Pos      (18U)
10303 #define RTC_TAFCR_PC13VALUE_Msk      (0x1UL << RTC_TAFCR_PC13VALUE_Pos)         /*!< 0x00040000 */
10304 #define RTC_TAFCR_PC13VALUE          RTC_TAFCR_PC13VALUE_Msk
10305 #define RTC_TAFCR_TAMPPUDIS_Pos      (15U)
10306 #define RTC_TAFCR_TAMPPUDIS_Msk      (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)         /*!< 0x00008000 */
10307 #define RTC_TAFCR_TAMPPUDIS          RTC_TAFCR_TAMPPUDIS_Msk
10308 #define RTC_TAFCR_TAMPPRCH_Pos       (13U)
10309 #define RTC_TAFCR_TAMPPRCH_Msk       (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00006000 */
10310 #define RTC_TAFCR_TAMPPRCH           RTC_TAFCR_TAMPPRCH_Msk
10311 #define RTC_TAFCR_TAMPPRCH_0         (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00002000 */
10312 #define RTC_TAFCR_TAMPPRCH_1         (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)          /*!< 0x00004000 */
10313 #define RTC_TAFCR_TAMPFLT_Pos        (11U)
10314 #define RTC_TAFCR_TAMPFLT_Msk        (0x3UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001800 */
10315 #define RTC_TAFCR_TAMPFLT            RTC_TAFCR_TAMPFLT_Msk
10316 #define RTC_TAFCR_TAMPFLT_0          (0x1UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00000800 */
10317 #define RTC_TAFCR_TAMPFLT_1          (0x2UL << RTC_TAFCR_TAMPFLT_Pos)           /*!< 0x00001000 */
10318 #define RTC_TAFCR_TAMPFREQ_Pos       (8U)
10319 #define RTC_TAFCR_TAMPFREQ_Msk       (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000700 */
10320 #define RTC_TAFCR_TAMPFREQ           RTC_TAFCR_TAMPFREQ_Msk
10321 #define RTC_TAFCR_TAMPFREQ_0         (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000100 */
10322 #define RTC_TAFCR_TAMPFREQ_1         (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000200 */
10323 #define RTC_TAFCR_TAMPFREQ_2         (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)          /*!< 0x00000400 */
10324 #define RTC_TAFCR_TAMPTS_Pos         (7U)
10325 #define RTC_TAFCR_TAMPTS_Msk         (0x1UL << RTC_TAFCR_TAMPTS_Pos)            /*!< 0x00000080 */
10326 #define RTC_TAFCR_TAMPTS             RTC_TAFCR_TAMPTS_Msk
10327 #define RTC_TAFCR_TAMP3TRG_Pos       (6U)
10328 #define RTC_TAFCR_TAMP3TRG_Msk       (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)          /*!< 0x00000040 */
10329 #define RTC_TAFCR_TAMP3TRG           RTC_TAFCR_TAMP3TRG_Msk
10330 #define RTC_TAFCR_TAMP3E_Pos         (5U)
10331 #define RTC_TAFCR_TAMP3E_Msk         (0x1UL << RTC_TAFCR_TAMP3E_Pos)            /*!< 0x00000020 */
10332 #define RTC_TAFCR_TAMP3E             RTC_TAFCR_TAMP3E_Msk
10333 #define RTC_TAFCR_TAMP2TRG_Pos       (4U)
10334 #define RTC_TAFCR_TAMP2TRG_Msk       (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)          /*!< 0x00000010 */
10335 #define RTC_TAFCR_TAMP2TRG           RTC_TAFCR_TAMP2TRG_Msk
10336 #define RTC_TAFCR_TAMP2E_Pos         (3U)
10337 #define RTC_TAFCR_TAMP2E_Msk         (0x1UL << RTC_TAFCR_TAMP2E_Pos)            /*!< 0x00000008 */
10338 #define RTC_TAFCR_TAMP2E             RTC_TAFCR_TAMP2E_Msk
10339 #define RTC_TAFCR_TAMPIE_Pos         (2U)
10340 #define RTC_TAFCR_TAMPIE_Msk         (0x1UL << RTC_TAFCR_TAMPIE_Pos)            /*!< 0x00000004 */
10341 #define RTC_TAFCR_TAMPIE             RTC_TAFCR_TAMPIE_Msk
10342 #define RTC_TAFCR_TAMP1TRG_Pos       (1U)
10343 #define RTC_TAFCR_TAMP1TRG_Msk       (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)          /*!< 0x00000002 */
10344 #define RTC_TAFCR_TAMP1TRG           RTC_TAFCR_TAMP1TRG_Msk
10345 #define RTC_TAFCR_TAMP1E_Pos         (0U)
10346 #define RTC_TAFCR_TAMP1E_Msk         (0x1UL << RTC_TAFCR_TAMP1E_Pos)            /*!< 0x00000001 */
10347 #define RTC_TAFCR_TAMP1E             RTC_TAFCR_TAMP1E_Msk
10348 
10349 /* Reference defines */
10350 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_PC13VALUE
10351 
10352 /********************  Bits definition for RTC_ALRMASSR register  *************/
10353 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
10354 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
10355 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
10356 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x01000000 */
10357 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x02000000 */
10358 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x04000000 */
10359 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x08000000 */
10360 #define RTC_ALRMASSR_SS_Pos          (0U)
10361 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)          /*!< 0x00007FFF */
10362 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
10363 
10364 /********************  Bits definition for RTC_ALRMBSSR register  *************/
10365 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
10366 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x0F000000 */
10367 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
10368 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x01000000 */
10369 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x02000000 */
10370 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x04000000 */
10371 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x08000000 */
10372 #define RTC_ALRMBSSR_SS_Pos          (0U)
10373 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)          /*!< 0x00007FFF */
10374 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
10375 
10376 /********************  Bits definition for RTC_BKP0R register  ****************/
10377 #define RTC_BKP0R_Pos                (0U)
10378 #define RTC_BKP0R_Msk                (0xFFFFFFFFUL << RTC_BKP0R_Pos)            /*!< 0xFFFFFFFF */
10379 #define RTC_BKP0R                    RTC_BKP0R_Msk
10380 
10381 /********************  Bits definition for RTC_BKP1R register  ****************/
10382 #define RTC_BKP1R_Pos                (0U)
10383 #define RTC_BKP1R_Msk                (0xFFFFFFFFUL << RTC_BKP1R_Pos)            /*!< 0xFFFFFFFF */
10384 #define RTC_BKP1R                    RTC_BKP1R_Msk
10385 
10386 /********************  Bits definition for RTC_BKP2R register  ****************/
10387 #define RTC_BKP2R_Pos                (0U)
10388 #define RTC_BKP2R_Msk                (0xFFFFFFFFUL << RTC_BKP2R_Pos)            /*!< 0xFFFFFFFF */
10389 #define RTC_BKP2R                    RTC_BKP2R_Msk
10390 
10391 /********************  Bits definition for RTC_BKP3R register  ****************/
10392 #define RTC_BKP3R_Pos                (0U)
10393 #define RTC_BKP3R_Msk                (0xFFFFFFFFUL << RTC_BKP3R_Pos)            /*!< 0xFFFFFFFF */
10394 #define RTC_BKP3R                    RTC_BKP3R_Msk
10395 
10396 /********************  Bits definition for RTC_BKP4R register  ****************/
10397 #define RTC_BKP4R_Pos                (0U)
10398 #define RTC_BKP4R_Msk                (0xFFFFFFFFUL << RTC_BKP4R_Pos)            /*!< 0xFFFFFFFF */
10399 #define RTC_BKP4R                    RTC_BKP4R_Msk
10400 
10401 /********************  Bits definition for RTC_BKP5R register  ****************/
10402 #define RTC_BKP5R_Pos                (0U)
10403 #define RTC_BKP5R_Msk                (0xFFFFFFFFUL << RTC_BKP5R_Pos)            /*!< 0xFFFFFFFF */
10404 #define RTC_BKP5R                    RTC_BKP5R_Msk
10405 
10406 /********************  Bits definition for RTC_BKP6R register  ****************/
10407 #define RTC_BKP6R_Pos                (0U)
10408 #define RTC_BKP6R_Msk                (0xFFFFFFFFUL << RTC_BKP6R_Pos)            /*!< 0xFFFFFFFF */
10409 #define RTC_BKP6R                    RTC_BKP6R_Msk
10410 
10411 /********************  Bits definition for RTC_BKP7R register  ****************/
10412 #define RTC_BKP7R_Pos                (0U)
10413 #define RTC_BKP7R_Msk                (0xFFFFFFFFUL << RTC_BKP7R_Pos)            /*!< 0xFFFFFFFF */
10414 #define RTC_BKP7R                    RTC_BKP7R_Msk
10415 
10416 /********************  Bits definition for RTC_BKP8R register  ****************/
10417 #define RTC_BKP8R_Pos                (0U)
10418 #define RTC_BKP8R_Msk                (0xFFFFFFFFUL << RTC_BKP8R_Pos)            /*!< 0xFFFFFFFF */
10419 #define RTC_BKP8R                    RTC_BKP8R_Msk
10420 
10421 /********************  Bits definition for RTC_BKP9R register  ****************/
10422 #define RTC_BKP9R_Pos                (0U)
10423 #define RTC_BKP9R_Msk                (0xFFFFFFFFUL << RTC_BKP9R_Pos)            /*!< 0xFFFFFFFF */
10424 #define RTC_BKP9R                    RTC_BKP9R_Msk
10425 
10426 /********************  Bits definition for RTC_BKP10R register  ***************/
10427 #define RTC_BKP10R_Pos               (0U)
10428 #define RTC_BKP10R_Msk               (0xFFFFFFFFUL << RTC_BKP10R_Pos)           /*!< 0xFFFFFFFF */
10429 #define RTC_BKP10R                   RTC_BKP10R_Msk
10430 
10431 /********************  Bits definition for RTC_BKP11R register  ***************/
10432 #define RTC_BKP11R_Pos               (0U)
10433 #define RTC_BKP11R_Msk               (0xFFFFFFFFUL << RTC_BKP11R_Pos)           /*!< 0xFFFFFFFF */
10434 #define RTC_BKP11R                   RTC_BKP11R_Msk
10435 
10436 /********************  Bits definition for RTC_BKP12R register  ***************/
10437 #define RTC_BKP12R_Pos               (0U)
10438 #define RTC_BKP12R_Msk               (0xFFFFFFFFUL << RTC_BKP12R_Pos)           /*!< 0xFFFFFFFF */
10439 #define RTC_BKP12R                   RTC_BKP12R_Msk
10440 
10441 /********************  Bits definition for RTC_BKP13R register  ***************/
10442 #define RTC_BKP13R_Pos               (0U)
10443 #define RTC_BKP13R_Msk               (0xFFFFFFFFUL << RTC_BKP13R_Pos)           /*!< 0xFFFFFFFF */
10444 #define RTC_BKP13R                   RTC_BKP13R_Msk
10445 
10446 /********************  Bits definition for RTC_BKP14R register  ***************/
10447 #define RTC_BKP14R_Pos               (0U)
10448 #define RTC_BKP14R_Msk               (0xFFFFFFFFUL << RTC_BKP14R_Pos)           /*!< 0xFFFFFFFF */
10449 #define RTC_BKP14R                   RTC_BKP14R_Msk
10450 
10451 /********************  Bits definition for RTC_BKP15R register  ***************/
10452 #define RTC_BKP15R_Pos               (0U)
10453 #define RTC_BKP15R_Msk               (0xFFFFFFFFUL << RTC_BKP15R_Pos)           /*!< 0xFFFFFFFF */
10454 #define RTC_BKP15R                   RTC_BKP15R_Msk
10455 
10456 /******************** Number of backup registers ******************************/
10457 #define RTC_BKP_NUMBER                       16
10458 
10459 /******************************************************************************/
10460 /*                                                                            */
10461 /*                        Serial Peripheral Interface (SPI)                   */
10462 /*                                                                            */
10463 /******************************************************************************/
10464 
10465 /*
10466  * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
10467  */
10468 #define SPI_I2S_SUPPORT                       /*!< I2S support */
10469 #define SPI_I2S_FULLDUPLEX_SUPPORT            /*!< I2S Full-Duplex support */
10470 
10471 /*******************  Bit definition for SPI_CR1 register  ********************/
10472 #define SPI_CR1_CPHA_Pos            (0U)
10473 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
10474 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
10475 #define SPI_CR1_CPOL_Pos            (1U)
10476 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
10477 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
10478 #define SPI_CR1_MSTR_Pos            (2U)
10479 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
10480 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
10481 #define SPI_CR1_BR_Pos              (3U)
10482 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
10483 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
10484 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
10485 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
10486 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
10487 #define SPI_CR1_SPE_Pos             (6U)
10488 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
10489 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
10490 #define SPI_CR1_LSBFIRST_Pos        (7U)
10491 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
10492 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
10493 #define SPI_CR1_SSI_Pos             (8U)
10494 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
10495 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
10496 #define SPI_CR1_SSM_Pos             (9U)
10497 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
10498 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
10499 #define SPI_CR1_RXONLY_Pos          (10U)
10500 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
10501 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
10502 #define SPI_CR1_CRCL_Pos            (11U)
10503 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */
10504 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
10505 #define SPI_CR1_CRCNEXT_Pos         (12U)
10506 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
10507 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
10508 #define SPI_CR1_CRCEN_Pos           (13U)
10509 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
10510 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
10511 #define SPI_CR1_BIDIOE_Pos          (14U)
10512 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
10513 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
10514 #define SPI_CR1_BIDIMODE_Pos        (15U)
10515 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
10516 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
10517 
10518 /*******************  Bit definition for SPI_CR2 register  ********************/
10519 #define SPI_CR2_RXDMAEN_Pos         (0U)
10520 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
10521 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
10522 #define SPI_CR2_TXDMAEN_Pos         (1U)
10523 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
10524 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
10525 #define SPI_CR2_SSOE_Pos            (2U)
10526 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
10527 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
10528 #define SPI_CR2_NSSP_Pos            (3U)
10529 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */
10530 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
10531 #define SPI_CR2_FRF_Pos             (4U)
10532 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
10533 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
10534 #define SPI_CR2_ERRIE_Pos           (5U)
10535 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
10536 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
10537 #define SPI_CR2_RXNEIE_Pos          (6U)
10538 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
10539 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
10540 #define SPI_CR2_TXEIE_Pos           (7U)
10541 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
10542 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
10543 #define SPI_CR2_DS_Pos              (8U)
10544 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */
10545 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
10546 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */
10547 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */
10548 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */
10549 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */
10550 #define SPI_CR2_FRXTH_Pos           (12U)
10551 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */
10552 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
10553 #define SPI_CR2_LDMARX_Pos          (13U)
10554 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */
10555 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
10556 #define SPI_CR2_LDMATX_Pos          (14U)
10557 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */
10558 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
10559 
10560 /********************  Bit definition for SPI_SR register  ********************/
10561 #define SPI_SR_RXNE_Pos             (0U)
10562 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
10563 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
10564 #define SPI_SR_TXE_Pos              (1U)
10565 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
10566 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
10567 #define SPI_SR_CHSIDE_Pos           (2U)
10568 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
10569 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
10570 #define SPI_SR_UDR_Pos              (3U)
10571 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
10572 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
10573 #define SPI_SR_CRCERR_Pos           (4U)
10574 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
10575 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
10576 #define SPI_SR_MODF_Pos             (5U)
10577 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
10578 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
10579 #define SPI_SR_OVR_Pos              (6U)
10580 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
10581 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
10582 #define SPI_SR_BSY_Pos              (7U)
10583 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
10584 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
10585 #define SPI_SR_FRE_Pos              (8U)
10586 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
10587 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
10588 #define SPI_SR_FRLVL_Pos            (9U)
10589 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */
10590 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
10591 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */
10592 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */
10593 #define SPI_SR_FTLVL_Pos            (11U)
10594 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */
10595 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
10596 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */
10597 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */
10598 
10599 /********************  Bit definition for SPI_DR register  ********************/
10600 #define SPI_DR_DR_Pos               (0U)
10601 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
10602 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
10603 
10604 /*******************  Bit definition for SPI_CRCPR register  ******************/
10605 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
10606 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
10607 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
10608 
10609 /******************  Bit definition for SPI_RXCRCR register  ******************/
10610 #define SPI_RXCRCR_RXCRC_Pos        (0U)
10611 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
10612 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
10613 
10614 /******************  Bit definition for SPI_TXCRCR register  ******************/
10615 #define SPI_TXCRCR_TXCRC_Pos        (0U)
10616 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
10617 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
10618 
10619 /******************  Bit definition for SPI_I2SCFGR register  *****************/
10620 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
10621 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
10622 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
10623 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
10624 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
10625 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
10626 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
10627 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
10628 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
10629 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
10630 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
10631 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
10632 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
10633 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
10634 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
10635 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
10636 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
10637 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
10638 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
10639 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
10640 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
10641 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
10642 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
10643 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
10644 #define SPI_I2SCFGR_I2SE_Pos        (10U)
10645 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
10646 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
10647 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
10648 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
10649 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
10650 
10651 /******************  Bit definition for SPI_I2SPR register  *******************/
10652 #define SPI_I2SPR_I2SDIV_Pos        (0U)
10653 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
10654 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
10655 #define SPI_I2SPR_ODD_Pos           (8U)
10656 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
10657 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
10658 #define SPI_I2SPR_MCKOE_Pos         (9U)
10659 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
10660 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
10661 
10662 /******************************************************************************/
10663 /*                                                                            */
10664 /*                        System Configuration(SYSCFG)                        */
10665 /*                                                                            */
10666 /******************************************************************************/
10667 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
10668 #define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)
10669 #define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
10670 #define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
10671 #define SYSCFG_CFGR1_MEM_MODE_0                  (0x00000001U)                 /*!< Bit 0 */
10672 #define SYSCFG_CFGR1_MEM_MODE_1                  (0x00000002U)                 /*!< Bit 1 */
10673 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos           (6U)
10674 #define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos) /*!< 0x00000040 */
10675 #define SYSCFG_CFGR1_TIM1_ITR3_RMP               SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk /*!< Timer 1 ITR3 selection */
10676 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos          (7U)
10677 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk          (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos) /*!< 0x00000080 */
10678 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP              SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk /*!< DAC1 Trigger1 remap */
10679 #define SYSCFG_CFGR1_DMA_RMP_Pos                 (8U)
10680 #define SYSCFG_CFGR1_DMA_RMP_Msk                 (0x79UL << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00007900 */
10681 #define SYSCFG_CFGR1_DMA_RMP                     SYSCFG_CFGR1_DMA_RMP_Msk      /*!< DMA remap mask */
10682 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos           (8U)
10683 #define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk           (0x1UL << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos) /*!< 0x00000100 */
10684 #define SYSCFG_CFGR1_ADC24_DMA_RMP               SYSCFG_CFGR1_ADC24_DMA_RMP_Msk /*!< ADC2 and ADC4 DMA remap */
10685 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos           (11U)
10686 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
10687 #define SYSCFG_CFGR1_TIM16_DMA_RMP               SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
10688 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos           (12U)
10689 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk           (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
10690 #define SYSCFG_CFGR1_TIM17_DMA_RMP               SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
10691 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos     (13U)
10692 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk     (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos) /*!< 0x00002000 */
10693 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP         SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk /*!< Timer 6 / DAC1 Ch1 DMA remap */
10694 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos     (14U)
10695 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk     (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos) /*!< 0x00004000 */
10696 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP         SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk /*!< Timer 7 / DAC1 Ch2 DMA remap */
10697 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos             (16U)
10698 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
10699 #define SYSCFG_CFGR1_I2C_PB6_FMP                 SYSCFG_CFGR1_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
10700 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos             (17U)
10701 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
10702 #define SYSCFG_CFGR1_I2C_PB7_FMP                 SYSCFG_CFGR1_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
10703 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos             (18U)
10704 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
10705 #define SYSCFG_CFGR1_I2C_PB8_FMP                 SYSCFG_CFGR1_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
10706 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos             (19U)
10707 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
10708 #define SYSCFG_CFGR1_I2C_PB9_FMP                 SYSCFG_CFGR1_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
10709 #define SYSCFG_CFGR1_I2C1_FMP_Pos                (20U)
10710 #define SYSCFG_CFGR1_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
10711 #define SYSCFG_CFGR1_I2C1_FMP                    SYSCFG_CFGR1_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
10712 #define SYSCFG_CFGR1_I2C2_FMP_Pos                (21U)
10713 #define SYSCFG_CFGR1_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
10714 #define SYSCFG_CFGR1_I2C2_FMP                    SYSCFG_CFGR1_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
10715 #define SYSCFG_CFGR1_ENCODER_MODE_Pos            (22U)
10716 #define SYSCFG_CFGR1_ENCODER_MODE_Msk            (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00C00000 */
10717 #define SYSCFG_CFGR1_ENCODER_MODE                SYSCFG_CFGR1_ENCODER_MODE_Msk /*!< Encoder Mode */
10718 #define SYSCFG_CFGR1_ENCODER_MODE_0              (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00400000 */
10719 #define SYSCFG_CFGR1_ENCODER_MODE_1              (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos) /*!< 0x00800000 */
10720 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos       (22U)
10721 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk       (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos) /*!< 0x00400000 */
10722 #define SYSCFG_CFGR1_ENCODER_MODE_TIM2           SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
10723 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos       (23U)
10724 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk       (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos) /*!< 0x00800000 */
10725 #define SYSCFG_CFGR1_ENCODER_MODE_TIM3           SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
10726 #define SYSCFG_CFGR1_ENCODER_MODE_TIM4_Pos       (22U)
10727 #define SYSCFG_CFGR1_ENCODER_MODE_TIM4_Msk       (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_TIM4_Pos) /*!< 0x00C00000 */
10728 #define SYSCFG_CFGR1_ENCODER_MODE_TIM4           SYSCFG_CFGR1_ENCODER_MODE_TIM4_Msk /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
10729 #define SYSCFG_CFGR1_FPU_IE_Pos                  (26U)
10730 #define SYSCFG_CFGR1_FPU_IE_Msk                  (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */
10731 #define SYSCFG_CFGR1_FPU_IE                      SYSCFG_CFGR1_FPU_IE_Msk       /*!< Floating Point Unit Interrupt Enable */
10732 #define SYSCFG_CFGR1_FPU_IE_0                    (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */
10733 #define SYSCFG_CFGR1_FPU_IE_1                    (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */
10734 #define SYSCFG_CFGR1_FPU_IE_2                    (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */
10735 #define SYSCFG_CFGR1_FPU_IE_3                    (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */
10736 #define SYSCFG_CFGR1_FPU_IE_4                    (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */
10737 #define SYSCFG_CFGR1_FPU_IE_5                    (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */
10738 
10739 /*****************  Bit definition for SYSCFG_RCR register  *******************/
10740 #define SYSCFG_RCR_PAGE0_Pos                     (0U)
10741 #define SYSCFG_RCR_PAGE0_Msk                     (0x1UL << SYSCFG_RCR_PAGE0_Pos) /*!< 0x00000001 */
10742 #define SYSCFG_RCR_PAGE0                         SYSCFG_RCR_PAGE0_Msk          /*!< ICODE SRAM Write protection page 0 */
10743 #define SYSCFG_RCR_PAGE1_Pos                     (1U)
10744 #define SYSCFG_RCR_PAGE1_Msk                     (0x1UL << SYSCFG_RCR_PAGE1_Pos) /*!< 0x00000002 */
10745 #define SYSCFG_RCR_PAGE1                         SYSCFG_RCR_PAGE1_Msk          /*!< ICODE SRAM Write protection page 1 */
10746 #define SYSCFG_RCR_PAGE2_Pos                     (2U)
10747 #define SYSCFG_RCR_PAGE2_Msk                     (0x1UL << SYSCFG_RCR_PAGE2_Pos) /*!< 0x00000004 */
10748 #define SYSCFG_RCR_PAGE2                         SYSCFG_RCR_PAGE2_Msk          /*!< ICODE SRAM Write protection page 2 */
10749 #define SYSCFG_RCR_PAGE3_Pos                     (3U)
10750 #define SYSCFG_RCR_PAGE3_Msk                     (0x1UL << SYSCFG_RCR_PAGE3_Pos) /*!< 0x00000008 */
10751 #define SYSCFG_RCR_PAGE3                         SYSCFG_RCR_PAGE3_Msk          /*!< ICODE SRAM Write protection page 3 */
10752 #define SYSCFG_RCR_PAGE4_Pos                     (4U)
10753 #define SYSCFG_RCR_PAGE4_Msk                     (0x1UL << SYSCFG_RCR_PAGE4_Pos) /*!< 0x00000010 */
10754 #define SYSCFG_RCR_PAGE4                         SYSCFG_RCR_PAGE4_Msk          /*!< ICODE SRAM Write protection page 4 */
10755 #define SYSCFG_RCR_PAGE5_Pos                     (5U)
10756 #define SYSCFG_RCR_PAGE5_Msk                     (0x1UL << SYSCFG_RCR_PAGE5_Pos) /*!< 0x00000020 */
10757 #define SYSCFG_RCR_PAGE5                         SYSCFG_RCR_PAGE5_Msk          /*!< ICODE SRAM Write protection page 5 */
10758 #define SYSCFG_RCR_PAGE6_Pos                     (6U)
10759 #define SYSCFG_RCR_PAGE6_Msk                     (0x1UL << SYSCFG_RCR_PAGE6_Pos) /*!< 0x00000040 */
10760 #define SYSCFG_RCR_PAGE6                         SYSCFG_RCR_PAGE6_Msk          /*!< ICODE SRAM Write protection page 6 */
10761 #define SYSCFG_RCR_PAGE7_Pos                     (7U)
10762 #define SYSCFG_RCR_PAGE7_Msk                     (0x1UL << SYSCFG_RCR_PAGE7_Pos) /*!< 0x00000080 */
10763 #define SYSCFG_RCR_PAGE7                         SYSCFG_RCR_PAGE7_Msk          /*!< ICODE SRAM Write protection page 7 */
10764 
10765 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
10766 #define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)
10767 #define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
10768 #define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
10769 #define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)
10770 #define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
10771 #define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
10772 #define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)
10773 #define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
10774 #define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
10775 #define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)
10776 #define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
10777 #define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
10778 
10779 /*!<*
10780   * @brief  EXTI0 configuration
10781   */
10782 #define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
10783 #define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
10784 #define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
10785 #define SYSCFG_EXTICR1_EXTI0_PD                  (0x00000003U)                 /*!< PD[0] pin */
10786 #define SYSCFG_EXTICR1_EXTI0_PE                  (0x00000004U)                 /*!< PE[0] pin */
10787 #define SYSCFG_EXTICR1_EXTI0_PF                  (0x00000005U)                 /*!< PF[0] pin */
10788 
10789 /*!<*
10790   * @brief  EXTI1 configuration
10791   */
10792 #define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
10793 #define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
10794 #define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
10795 #define SYSCFG_EXTICR1_EXTI1_PD                  (0x00000030U)                 /*!< PD[1] pin */
10796 #define SYSCFG_EXTICR1_EXTI1_PE                  (0x00000040U)                 /*!< PE[1] pin */
10797 #define SYSCFG_EXTICR1_EXTI1_PF                  (0x00000050U)                 /*!< PF[1] pin */
10798 
10799 /*!<*
10800   * @brief  EXTI2 configuration
10801   */
10802 #define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
10803 #define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
10804 #define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
10805 #define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
10806 #define SYSCFG_EXTICR1_EXTI2_PE                  (0x00000400U)                 /*!< PE[2] pin */
10807 #define SYSCFG_EXTICR1_EXTI2_PF                  (0x00000500U)                 /*!< PF[2] pin */
10808 
10809 /*!<*
10810   * @brief  EXTI3 configuration
10811   */
10812 #define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
10813 #define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
10814 #define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
10815 #define SYSCFG_EXTICR1_EXTI3_PD                  (0x00003000U)                 /*!< PD[3] pin */
10816 #define SYSCFG_EXTICR1_EXTI3_PE                  (0x00004000U)                 /*!< PE[3] pin */
10817 
10818 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
10819 #define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)
10820 #define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
10821 #define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
10822 #define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)
10823 #define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
10824 #define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
10825 #define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)
10826 #define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
10827 #define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
10828 #define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)
10829 #define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
10830 #define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
10831 
10832 /*!<*
10833   * @brief  EXTI4 configuration
10834   */
10835 #define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
10836 #define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
10837 #define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
10838 #define SYSCFG_EXTICR2_EXTI4_PD                  (0x00000003U)                 /*!< PD[4] pin */
10839 #define SYSCFG_EXTICR2_EXTI4_PE                  (0x00000004U)                 /*!< PE[4] pin */
10840 #define SYSCFG_EXTICR2_EXTI4_PF                  (0x00000005U)                 /*!< PF[4] pin */
10841 
10842 /*!<*
10843   * @brief  EXTI5 configuration
10844   */
10845 #define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
10846 #define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
10847 #define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
10848 #define SYSCFG_EXTICR2_EXTI5_PD                  (0x00000030U)                 /*!< PD[5] pin */
10849 #define SYSCFG_EXTICR2_EXTI5_PE                  (0x00000040U)                 /*!< PE[5] pin */
10850 #define SYSCFG_EXTICR2_EXTI5_PF                  (0x00000050U)                 /*!< PF[5] pin */
10851 
10852 /*!<*
10853   * @brief  EXTI6 configuration
10854   */
10855 #define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
10856 #define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
10857 #define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
10858 #define SYSCFG_EXTICR2_EXTI6_PD                  (0x00000300U)                 /*!< PD[6] pin */
10859 #define SYSCFG_EXTICR2_EXTI6_PE                  (0x00000400U)                 /*!< PE[6] pin */
10860 #define SYSCFG_EXTICR2_EXTI6_PF                  (0x00000500U)                 /*!< PF[6] pin */
10861 
10862 /*!<*
10863   * @brief  EXTI7 configuration
10864   */
10865 #define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
10866 #define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
10867 #define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
10868 #define SYSCFG_EXTICR2_EXTI7_PD                  (0x00003000U)                 /*!< PD[7] pin */
10869 #define SYSCFG_EXTICR2_EXTI7_PE                  (0x00004000U)                 /*!< PE[7] pin */
10870 
10871 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
10872 #define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)
10873 #define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
10874 #define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
10875 #define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)
10876 #define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
10877 #define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
10878 #define SYSCFG_EXTICR3_EXTI10_Pos                (8U)
10879 #define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
10880 #define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
10881 #define SYSCFG_EXTICR3_EXTI11_Pos                (12U)
10882 #define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
10883 #define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
10884 
10885 /*!<*
10886   * @brief  EXTI8 configuration
10887   */
10888 #define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
10889 #define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
10890 #define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
10891 #define SYSCFG_EXTICR3_EXTI8_PD                  (0x00000003U)                 /*!< PD[8] pin */
10892 #define SYSCFG_EXTICR3_EXTI8_PE                  (0x00000004U)                 /*!< PE[8] pin */
10893 
10894 /*!<*
10895   * @brief  EXTI9 configuration
10896   */
10897 #define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
10898 #define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
10899 #define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
10900 #define SYSCFG_EXTICR3_EXTI9_PD                  (0x00000030U)                 /*!< PD[9] pin */
10901 #define SYSCFG_EXTICR3_EXTI9_PE                  (0x00000040U)                 /*!< PE[9] pin */
10902 #define SYSCFG_EXTICR3_EXTI9_PF                  (0x00000050U)                 /*!< PF[9] pin */
10903 
10904 /*!<*
10905   * @brief  EXTI10 configuration
10906   */
10907 #define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
10908 #define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
10909 #define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
10910 #define SYSCFG_EXTICR3_EXTI10_PD                 (0x00000300U)                 /*!< PD[10] pin */
10911 #define SYSCFG_EXTICR3_EXTI10_PE                 (0x00000400U)                 /*!< PE[10] pin */
10912 #define SYSCFG_EXTICR3_EXTI10_PF                 (0x00000500U)                 /*!< PF[10] pin */
10913 
10914 /*!<*
10915   * @brief  EXTI11 configuration
10916   */
10917 #define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
10918 #define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
10919 #define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
10920 #define SYSCFG_EXTICR3_EXTI11_PD                 (0x00003000U)                 /*!< PD[11] pin */
10921 #define SYSCFG_EXTICR3_EXTI11_PE                 (0x00004000U)                 /*!< PE[11] pin */
10922 
10923 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
10924 #define SYSCFG_EXTICR4_EXTI12_Pos                (0U)
10925 #define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
10926 #define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
10927 #define SYSCFG_EXTICR4_EXTI13_Pos                (4U)
10928 #define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
10929 #define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
10930 #define SYSCFG_EXTICR4_EXTI14_Pos                (8U)
10931 #define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
10932 #define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
10933 #define SYSCFG_EXTICR4_EXTI15_Pos                (12U)
10934 #define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
10935 #define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
10936 
10937 /*!<*
10938   * @brief  EXTI12 configuration
10939   */
10940 #define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
10941 #define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
10942 #define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
10943 #define SYSCFG_EXTICR4_EXTI12_PD                 (0x00000003U)                 /*!< PD[12] pin */
10944 #define SYSCFG_EXTICR4_EXTI12_PE                 (0x00000004U)                 /*!< PE[12] pin */
10945 
10946 /*!<*
10947   * @brief  EXTI13 configuration
10948   */
10949 #define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
10950 #define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
10951 #define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
10952 #define SYSCFG_EXTICR4_EXTI13_PD                 (0x00000030U)                 /*!< PD[13] pin */
10953 #define SYSCFG_EXTICR4_EXTI13_PE                 (0x00000040U)                 /*!< PE[13] pin */
10954 
10955 /*!<*
10956   * @brief  EXTI14 configuration
10957   */
10958 #define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
10959 #define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
10960 #define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
10961 #define SYSCFG_EXTICR4_EXTI14_PD                 (0x00000300U)                 /*!< PD[14] pin */
10962 #define SYSCFG_EXTICR4_EXTI14_PE                 (0x00000400U)                 /*!< PE[14] pin */
10963 
10964 /*!<*
10965   * @brief  EXTI15 configuration
10966   */
10967 #define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
10968 #define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
10969 #define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
10970 #define SYSCFG_EXTICR4_EXTI15_PD                 (0x00003000U)                 /*!< PD[15] pin */
10971 #define SYSCFG_EXTICR4_EXTI15_PE                 (0x00004000U)                 /*!< PE[15] pin */
10972 
10973 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
10974 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos             (0U)
10975 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk             (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
10976 #define SYSCFG_CFGR2_LOCKUP_LOCK                 SYSCFG_CFGR2_LOCKUP_LOCK_Msk  /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
10977 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos        (1U)
10978 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk        (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
10979 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK            SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
10980 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos            (4U)
10981 #define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk            (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos) /*!< 0x00000010 */
10982 #define SYSCFG_CFGR2_BYP_ADDR_PAR                SYSCFG_CFGR2_BYP_ADDR_PAR_Msk /*!< Disables the address parity check on RAM */
10983 #define SYSCFG_CFGR2_SRAM_PE_Pos                 (8U)
10984 #define SYSCFG_CFGR2_SRAM_PE_Msk                 (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos) /*!< 0x00000100 */
10985 #define SYSCFG_CFGR2_SRAM_PE                     SYSCFG_CFGR2_SRAM_PE_Msk      /*!< SRAM Parity error flag */
10986 
10987 /******************************************************************************/
10988 /*                                                                            */
10989 /*                                    TIM                                     */
10990 /*                                                                            */
10991 /******************************************************************************/
10992 /*******************  Bit definition for TIM_CR1 register  ********************/
10993 #define TIM_CR1_CEN_Pos           (0U)
10994 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
10995 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
10996 #define TIM_CR1_UDIS_Pos          (1U)
10997 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
10998 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
10999 #define TIM_CR1_URS_Pos           (2U)
11000 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
11001 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
11002 #define TIM_CR1_OPM_Pos           (3U)
11003 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
11004 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
11005 #define TIM_CR1_DIR_Pos           (4U)
11006 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
11007 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
11008 
11009 #define TIM_CR1_CMS_Pos           (5U)
11010 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
11011 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
11012 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
11013 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
11014 
11015 #define TIM_CR1_ARPE_Pos          (7U)
11016 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
11017 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
11018 
11019 #define TIM_CR1_CKD_Pos           (8U)
11020 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
11021 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
11022 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
11023 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
11024 
11025 #define TIM_CR1_UIFREMAP_Pos      (11U)
11026 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
11027 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
11028 
11029 /*******************  Bit definition for TIM_CR2 register  ********************/
11030 #define TIM_CR2_CCPC_Pos          (0U)
11031 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
11032 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
11033 #define TIM_CR2_CCUS_Pos          (2U)
11034 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
11035 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
11036 #define TIM_CR2_CCDS_Pos          (3U)
11037 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
11038 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
11039 
11040 #define TIM_CR2_MMS_Pos           (4U)
11041 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
11042 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
11043 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
11044 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
11045 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
11046 
11047 #define TIM_CR2_TI1S_Pos          (7U)
11048 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
11049 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
11050 #define TIM_CR2_OIS1_Pos          (8U)
11051 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
11052 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
11053 #define TIM_CR2_OIS1N_Pos         (9U)
11054 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
11055 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
11056 #define TIM_CR2_OIS2_Pos          (10U)
11057 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
11058 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
11059 #define TIM_CR2_OIS2N_Pos         (11U)
11060 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
11061 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
11062 #define TIM_CR2_OIS3_Pos          (12U)
11063 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
11064 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
11065 #define TIM_CR2_OIS3N_Pos         (13U)
11066 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
11067 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
11068 #define TIM_CR2_OIS4_Pos          (14U)
11069 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
11070 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
11071 
11072 #define TIM_CR2_OIS5_Pos          (16U)
11073 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
11074 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
11075 #define TIM_CR2_OIS6_Pos          (18U)
11076 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
11077 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
11078 
11079 #define TIM_CR2_MMS2_Pos          (20U)
11080 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
11081 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
11082 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
11083 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
11084 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
11085 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
11086 
11087 /*******************  Bit definition for TIM_SMCR register  *******************/
11088 #define TIM_SMCR_SMS_Pos          (0U)
11089 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
11090 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
11091 #define TIM_SMCR_SMS_0            (0x00000001U)                                /*!<Bit 0 */
11092 #define TIM_SMCR_SMS_1            (0x00000002U)                                /*!<Bit 1 */
11093 #define TIM_SMCR_SMS_2            (0x00000004U)                                /*!<Bit 2 */
11094 #define TIM_SMCR_SMS_3            (0x00010000U)                                /*!<Bit 3 */
11095 
11096 #define TIM_SMCR_OCCS_Pos         (3U)
11097 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
11098 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
11099 
11100 #define TIM_SMCR_TS_Pos           (4U)
11101 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
11102 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
11103 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
11104 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
11105 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
11106 
11107 #define TIM_SMCR_MSM_Pos          (7U)
11108 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
11109 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
11110 
11111 #define TIM_SMCR_ETF_Pos          (8U)
11112 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
11113 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
11114 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
11115 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
11116 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
11117 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
11118 
11119 #define TIM_SMCR_ETPS_Pos         (12U)
11120 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
11121 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
11122 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
11123 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
11124 
11125 #define TIM_SMCR_ECE_Pos          (14U)
11126 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
11127 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
11128 #define TIM_SMCR_ETP_Pos          (15U)
11129 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
11130 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
11131 
11132 /*******************  Bit definition for TIM_DIER register  *******************/
11133 #define TIM_DIER_UIE_Pos          (0U)
11134 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
11135 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
11136 #define TIM_DIER_CC1IE_Pos        (1U)
11137 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
11138 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
11139 #define TIM_DIER_CC2IE_Pos        (2U)
11140 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
11141 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
11142 #define TIM_DIER_CC3IE_Pos        (3U)
11143 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
11144 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
11145 #define TIM_DIER_CC4IE_Pos        (4U)
11146 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
11147 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
11148 #define TIM_DIER_COMIE_Pos        (5U)
11149 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
11150 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
11151 #define TIM_DIER_TIE_Pos          (6U)
11152 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
11153 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
11154 #define TIM_DIER_BIE_Pos          (7U)
11155 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
11156 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
11157 #define TIM_DIER_UDE_Pos          (8U)
11158 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
11159 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
11160 #define TIM_DIER_CC1DE_Pos        (9U)
11161 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
11162 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
11163 #define TIM_DIER_CC2DE_Pos        (10U)
11164 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
11165 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
11166 #define TIM_DIER_CC3DE_Pos        (11U)
11167 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
11168 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
11169 #define TIM_DIER_CC4DE_Pos        (12U)
11170 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
11171 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
11172 #define TIM_DIER_COMDE_Pos        (13U)
11173 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
11174 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
11175 #define TIM_DIER_TDE_Pos          (14U)
11176 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
11177 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
11178 
11179 /********************  Bit definition for TIM_SR register  ********************/
11180 #define TIM_SR_UIF_Pos            (0U)
11181 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
11182 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
11183 #define TIM_SR_CC1IF_Pos          (1U)
11184 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
11185 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
11186 #define TIM_SR_CC2IF_Pos          (2U)
11187 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
11188 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
11189 #define TIM_SR_CC3IF_Pos          (3U)
11190 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
11191 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
11192 #define TIM_SR_CC4IF_Pos          (4U)
11193 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
11194 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
11195 #define TIM_SR_COMIF_Pos          (5U)
11196 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
11197 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
11198 #define TIM_SR_TIF_Pos            (6U)
11199 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
11200 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
11201 #define TIM_SR_BIF_Pos            (7U)
11202 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
11203 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
11204 #define TIM_SR_B2IF_Pos           (8U)
11205 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
11206 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
11207 #define TIM_SR_CC1OF_Pos          (9U)
11208 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
11209 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
11210 #define TIM_SR_CC2OF_Pos          (10U)
11211 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
11212 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
11213 #define TIM_SR_CC3OF_Pos          (11U)
11214 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
11215 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
11216 #define TIM_SR_CC4OF_Pos          (12U)
11217 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
11218 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
11219 #define TIM_SR_CC5IF_Pos          (16U)
11220 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
11221 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
11222 #define TIM_SR_CC6IF_Pos          (17U)
11223 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
11224 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
11225 
11226 /*******************  Bit definition for TIM_EGR register  ********************/
11227 #define TIM_EGR_UG_Pos            (0U)
11228 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
11229 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
11230 #define TIM_EGR_CC1G_Pos          (1U)
11231 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
11232 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
11233 #define TIM_EGR_CC2G_Pos          (2U)
11234 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
11235 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
11236 #define TIM_EGR_CC3G_Pos          (3U)
11237 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
11238 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
11239 #define TIM_EGR_CC4G_Pos          (4U)
11240 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
11241 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
11242 #define TIM_EGR_COMG_Pos          (5U)
11243 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
11244 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
11245 #define TIM_EGR_TG_Pos            (6U)
11246 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
11247 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
11248 #define TIM_EGR_BG_Pos            (7U)
11249 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
11250 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
11251 #define TIM_EGR_B2G_Pos           (8U)
11252 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
11253 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
11254 
11255 /******************  Bit definition for TIM_CCMR1 register  *******************/
11256 #define TIM_CCMR1_CC1S_Pos        (0U)
11257 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
11258 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
11259 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
11260 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
11261 
11262 #define TIM_CCMR1_OC1FE_Pos       (2U)
11263 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
11264 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
11265 #define TIM_CCMR1_OC1PE_Pos       (3U)
11266 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
11267 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
11268 
11269 #define TIM_CCMR1_OC1M_Pos        (4U)
11270 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
11271 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
11272 #define TIM_CCMR1_OC1M_0          (0x00000010U)                                /*!<Bit 0 */
11273 #define TIM_CCMR1_OC1M_1          (0x00000020U)                                /*!<Bit 1 */
11274 #define TIM_CCMR1_OC1M_2          (0x00000040U)                                /*!<Bit 2 */
11275 #define TIM_CCMR1_OC1M_3          (0x00010000U)                                /*!<Bit 3 */
11276 
11277 #define TIM_CCMR1_OC1CE_Pos       (7U)
11278 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
11279 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
11280 
11281 #define TIM_CCMR1_CC2S_Pos        (8U)
11282 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
11283 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
11284 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
11285 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
11286 
11287 #define TIM_CCMR1_OC2FE_Pos       (10U)
11288 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
11289 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
11290 #define TIM_CCMR1_OC2PE_Pos       (11U)
11291 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
11292 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
11293 
11294 #define TIM_CCMR1_OC2M_Pos        (12U)
11295 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
11296 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
11297 #define TIM_CCMR1_OC2M_0          (0x00001000U)                                /*!<Bit 0 */
11298 #define TIM_CCMR1_OC2M_1          (0x00002000U)                                /*!<Bit 1 */
11299 #define TIM_CCMR1_OC2M_2          (0x00004000U)                                /*!<Bit 2 */
11300 #define TIM_CCMR1_OC2M_3          (0x01000000U)                                /*!<Bit 3 */
11301 
11302 #define TIM_CCMR1_OC2CE_Pos       (15U)
11303 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
11304 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
11305 
11306 /*----------------------------------------------------------------------------*/
11307 
11308 #define TIM_CCMR1_IC1PSC_Pos      (2U)
11309 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
11310 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
11311 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
11312 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
11313 
11314 #define TIM_CCMR1_IC1F_Pos        (4U)
11315 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
11316 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
11317 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
11318 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
11319 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
11320 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
11321 
11322 #define TIM_CCMR1_IC2PSC_Pos      (10U)
11323 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
11324 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
11325 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
11326 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
11327 
11328 #define TIM_CCMR1_IC2F_Pos        (12U)
11329 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
11330 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
11331 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
11332 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
11333 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
11334 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
11335 
11336 /******************  Bit definition for TIM_CCMR2 register  *******************/
11337 #define TIM_CCMR2_CC3S_Pos        (0U)
11338 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
11339 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
11340 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
11341 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
11342 
11343 #define TIM_CCMR2_OC3FE_Pos       (2U)
11344 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
11345 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
11346 #define TIM_CCMR2_OC3PE_Pos       (3U)
11347 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
11348 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
11349 
11350 #define TIM_CCMR2_OC3M_Pos        (4U)
11351 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
11352 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
11353 #define TIM_CCMR2_OC3M_0          (0x00000010U)                                /*!<Bit 0 */
11354 #define TIM_CCMR2_OC3M_1          (0x00000020U)                                /*!<Bit 1 */
11355 #define TIM_CCMR2_OC3M_2          (0x00000040U)                                /*!<Bit 2 */
11356 #define TIM_CCMR2_OC3M_3          (0x00010000U)                                /*!<Bit 3 */
11357 
11358 #define TIM_CCMR2_OC3CE_Pos       (7U)
11359 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
11360 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
11361 
11362 #define TIM_CCMR2_CC4S_Pos        (8U)
11363 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
11364 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
11365 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
11366 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
11367 
11368 #define TIM_CCMR2_OC4FE_Pos       (10U)
11369 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
11370 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
11371 #define TIM_CCMR2_OC4PE_Pos       (11U)
11372 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
11373 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
11374 
11375 #define TIM_CCMR2_OC4M_Pos        (12U)
11376 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
11377 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
11378 #define TIM_CCMR2_OC4M_0          (0x00001000U)                                /*!<Bit 0 */
11379 #define TIM_CCMR2_OC4M_1          (0x00002000U)                                /*!<Bit 1 */
11380 #define TIM_CCMR2_OC4M_2          (0x00004000U)                                /*!<Bit 2 */
11381 #define TIM_CCMR2_OC4M_3          (0x01000000U)                                /*!<Bit 3 */
11382 
11383 #define TIM_CCMR2_OC4CE_Pos       (15U)
11384 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
11385 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
11386 
11387 /*----------------------------------------------------------------------------*/
11388 
11389 #define TIM_CCMR2_IC3PSC_Pos      (2U)
11390 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
11391 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
11392 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
11393 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
11394 
11395 #define TIM_CCMR2_IC3F_Pos        (4U)
11396 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
11397 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
11398 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
11399 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
11400 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
11401 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
11402 
11403 #define TIM_CCMR2_IC4PSC_Pos      (10U)
11404 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
11405 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
11406 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
11407 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
11408 
11409 #define TIM_CCMR2_IC4F_Pos        (12U)
11410 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
11411 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
11412 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
11413 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
11414 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
11415 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
11416 
11417 /*******************  Bit definition for TIM_CCER register  *******************/
11418 #define TIM_CCER_CC1E_Pos         (0U)
11419 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
11420 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
11421 #define TIM_CCER_CC1P_Pos         (1U)
11422 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
11423 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
11424 #define TIM_CCER_CC1NE_Pos        (2U)
11425 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
11426 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
11427 #define TIM_CCER_CC1NP_Pos        (3U)
11428 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
11429 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
11430 #define TIM_CCER_CC2E_Pos         (4U)
11431 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
11432 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
11433 #define TIM_CCER_CC2P_Pos         (5U)
11434 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
11435 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
11436 #define TIM_CCER_CC2NE_Pos        (6U)
11437 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
11438 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
11439 #define TIM_CCER_CC2NP_Pos        (7U)
11440 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
11441 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
11442 #define TIM_CCER_CC3E_Pos         (8U)
11443 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
11444 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
11445 #define TIM_CCER_CC3P_Pos         (9U)
11446 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
11447 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
11448 #define TIM_CCER_CC3NE_Pos        (10U)
11449 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
11450 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
11451 #define TIM_CCER_CC3NP_Pos        (11U)
11452 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
11453 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
11454 #define TIM_CCER_CC4E_Pos         (12U)
11455 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
11456 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
11457 #define TIM_CCER_CC4P_Pos         (13U)
11458 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
11459 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
11460 #define TIM_CCER_CC4NP_Pos        (15U)
11461 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
11462 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
11463 #define TIM_CCER_CC5E_Pos         (16U)
11464 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
11465 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
11466 #define TIM_CCER_CC5P_Pos         (17U)
11467 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
11468 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
11469 #define TIM_CCER_CC6E_Pos         (20U)
11470 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
11471 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
11472 #define TIM_CCER_CC6P_Pos         (21U)
11473 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
11474 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
11475 
11476 /*******************  Bit definition for TIM_CNT register  ********************/
11477 #define TIM_CNT_CNT_Pos           (0U)
11478 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
11479 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
11480 #define TIM_CNT_UIFCPY_Pos        (31U)
11481 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
11482 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
11483 
11484 /*******************  Bit definition for TIM_PSC register  ********************/
11485 #define TIM_PSC_PSC_Pos           (0U)
11486 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
11487 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
11488 
11489 /*******************  Bit definition for TIM_ARR register  ********************/
11490 #define TIM_ARR_ARR_Pos           (0U)
11491 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
11492 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
11493 
11494 /*******************  Bit definition for TIM_RCR register  ********************/
11495 #define TIM_RCR_REP_Pos           (0U)
11496 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
11497 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
11498 
11499 /*******************  Bit definition for TIM_CCR1 register  *******************/
11500 #define TIM_CCR1_CCR1_Pos         (0U)
11501 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
11502 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
11503 
11504 /*******************  Bit definition for TIM_CCR2 register  *******************/
11505 #define TIM_CCR2_CCR2_Pos         (0U)
11506 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
11507 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
11508 
11509 /*******************  Bit definition for TIM_CCR3 register  *******************/
11510 #define TIM_CCR3_CCR3_Pos         (0U)
11511 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
11512 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
11513 
11514 /*******************  Bit definition for TIM_CCR4 register  *******************/
11515 #define TIM_CCR4_CCR4_Pos         (0U)
11516 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
11517 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
11518 
11519 /*******************  Bit definition for TIM_CCR5 register  *******************/
11520 #define TIM_CCR5_CCR5_Pos         (0U)
11521 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
11522 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
11523 #define TIM_CCR5_GC5C1_Pos        (29U)
11524 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
11525 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
11526 #define TIM_CCR5_GC5C2_Pos        (30U)
11527 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
11528 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
11529 #define TIM_CCR5_GC5C3_Pos        (31U)
11530 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
11531 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
11532 
11533 /*******************  Bit definition for TIM_CCR6 register  *******************/
11534 #define TIM_CCR6_CCR6_Pos         (0U)
11535 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
11536 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
11537 
11538 /*******************  Bit definition for TIM_BDTR register  *******************/
11539 #define TIM_BDTR_DTG_Pos          (0U)
11540 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
11541 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
11542 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
11543 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
11544 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
11545 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
11546 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
11547 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
11548 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
11549 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
11550 
11551 #define TIM_BDTR_LOCK_Pos         (8U)
11552 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
11553 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
11554 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
11555 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
11556 
11557 #define TIM_BDTR_OSSI_Pos         (10U)
11558 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
11559 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
11560 #define TIM_BDTR_OSSR_Pos         (11U)
11561 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
11562 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
11563 #define TIM_BDTR_BKE_Pos          (12U)
11564 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
11565 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
11566 #define TIM_BDTR_BKP_Pos          (13U)
11567 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
11568 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
11569 #define TIM_BDTR_AOE_Pos          (14U)
11570 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
11571 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
11572 #define TIM_BDTR_MOE_Pos          (15U)
11573 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
11574 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
11575 
11576 #define TIM_BDTR_BKF_Pos          (16U)
11577 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
11578 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
11579 #define TIM_BDTR_BK2F_Pos         (20U)
11580 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
11581 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
11582 
11583 #define TIM_BDTR_BK2E_Pos         (24U)
11584 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
11585 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
11586 #define TIM_BDTR_BK2P_Pos         (25U)
11587 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
11588 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
11589 
11590 /*******************  Bit definition for TIM_DCR register  ********************/
11591 #define TIM_DCR_DBA_Pos           (0U)
11592 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
11593 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
11594 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
11595 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
11596 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
11597 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
11598 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
11599 
11600 #define TIM_DCR_DBL_Pos           (8U)
11601 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
11602 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
11603 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
11604 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
11605 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
11606 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
11607 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
11608 
11609 /*******************  Bit definition for TIM_DMAR register  *******************/
11610 #define TIM_DMAR_DMAB_Pos         (0U)
11611 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
11612 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
11613 
11614 /*******************  Bit definition for TIM16_OR register  *********************/
11615 #define TIM16_OR_TI1_RMP_Pos      (0U)
11616 #define TIM16_OR_TI1_RMP_Msk      (0x3UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000003 */
11617 #define TIM16_OR_TI1_RMP          TIM16_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
11618 #define TIM16_OR_TI1_RMP_0        (0x1UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000001 */
11619 #define TIM16_OR_TI1_RMP_1        (0x2UL << TIM16_OR_TI1_RMP_Pos)               /*!< 0x00000002 */
11620 
11621 /*******************  Bit definition for TIM1_OR register  *********************/
11622 #define TIM1_OR_ETR_RMP_Pos      (0U)
11623 #define TIM1_OR_ETR_RMP_Msk      (0xFUL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x0000000F */
11624 #define TIM1_OR_ETR_RMP          TIM1_OR_ETR_RMP_Msk                           /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
11625 #define TIM1_OR_ETR_RMP_0        (0x1UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
11626 #define TIM1_OR_ETR_RMP_1        (0x2UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
11627 #define TIM1_OR_ETR_RMP_2        (0x4UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
11628 #define TIM1_OR_ETR_RMP_3        (0x8UL << TIM1_OR_ETR_RMP_Pos)                 /*!< 0x00000008 */
11629 
11630 /*******************  Bit definition for TIM8_OR register  *********************/
11631 #define TIM8_OR_ETR_RMP_Pos      (0U)
11632 #define TIM8_OR_ETR_RMP_Msk      (0xFUL << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x0000000F */
11633 #define TIM8_OR_ETR_RMP          TIM8_OR_ETR_RMP_Msk                           /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
11634 #define TIM8_OR_ETR_RMP_0        (0x1UL << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
11635 #define TIM8_OR_ETR_RMP_1        (0x2UL << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
11636 #define TIM8_OR_ETR_RMP_2        (0x4UL << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
11637 #define TIM8_OR_ETR_RMP_3        (0x8UL << TIM8_OR_ETR_RMP_Pos)                 /*!< 0x00000008 */
11638 
11639 /******************  Bit definition for TIM_CCMR3 register  *******************/
11640 #define TIM_CCMR3_OC5FE_Pos       (2U)
11641 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
11642 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
11643 #define TIM_CCMR3_OC5PE_Pos       (3U)
11644 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
11645 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
11646 
11647 #define TIM_CCMR3_OC5M_Pos        (4U)
11648 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
11649 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
11650 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
11651 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
11652 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
11653 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
11654 
11655 #define TIM_CCMR3_OC5CE_Pos       (7U)
11656 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
11657 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
11658 
11659 #define TIM_CCMR3_OC6FE_Pos       (10U)
11660 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
11661 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
11662 #define TIM_CCMR3_OC6PE_Pos       (11U)
11663 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
11664 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
11665 
11666 #define TIM_CCMR3_OC6M_Pos        (12U)
11667 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
11668 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
11669 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
11670 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
11671 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
11672 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
11673 
11674 #define TIM_CCMR3_OC6CE_Pos       (15U)
11675 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
11676 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
11677 
11678 /******************************************************************************/
11679 /*                                                                            */
11680 /*                          Touch Sensing Controller (TSC)                    */
11681 /*                                                                            */
11682 /******************************************************************************/
11683 /*******************  Bit definition for TSC_CR register  *********************/
11684 #define TSC_CR_TSCE_Pos          (0U)
11685 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
11686 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
11687 #define TSC_CR_START_Pos         (1U)
11688 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
11689 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
11690 #define TSC_CR_AM_Pos            (2U)
11691 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
11692 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
11693 #define TSC_CR_SYNCPOL_Pos       (3U)
11694 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
11695 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
11696 #define TSC_CR_IODEF_Pos         (4U)
11697 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
11698 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
11699 
11700 #define TSC_CR_MCV_Pos           (5U)
11701 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
11702 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
11703 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
11704 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
11705 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
11706 
11707 #define TSC_CR_PGPSC_Pos         (12U)
11708 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
11709 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
11710 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
11711 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
11712 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
11713 
11714 #define TSC_CR_SSPSC_Pos         (15U)
11715 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
11716 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
11717 #define TSC_CR_SSE_Pos           (16U)
11718 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
11719 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
11720 
11721 #define TSC_CR_SSD_Pos           (17U)
11722 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
11723 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
11724 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
11725 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
11726 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
11727 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
11728 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
11729 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
11730 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
11731 
11732 #define TSC_CR_CTPL_Pos          (24U)
11733 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
11734 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
11735 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
11736 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
11737 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
11738 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
11739 
11740 #define TSC_CR_CTPH_Pos          (28U)
11741 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
11742 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
11743 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
11744 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
11745 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
11746 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
11747 
11748 /*******************  Bit definition for TSC_IER register  ********************/
11749 #define TSC_IER_EOAIE_Pos        (0U)
11750 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
11751 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
11752 #define TSC_IER_MCEIE_Pos        (1U)
11753 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
11754 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
11755 
11756 /*******************  Bit definition for TSC_ICR register  ********************/
11757 #define TSC_ICR_EOAIC_Pos        (0U)
11758 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
11759 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
11760 #define TSC_ICR_MCEIC_Pos        (1U)
11761 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
11762 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
11763 
11764 /*******************  Bit definition for TSC_ISR register  ********************/
11765 #define TSC_ISR_EOAF_Pos         (0U)
11766 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
11767 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
11768 #define TSC_ISR_MCEF_Pos         (1U)
11769 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
11770 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
11771 
11772 /*******************  Bit definition for TSC_IOHCR register  ******************/
11773 #define TSC_IOHCR_G1_IO1_Pos     (0U)
11774 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
11775 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
11776 #define TSC_IOHCR_G1_IO2_Pos     (1U)
11777 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
11778 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
11779 #define TSC_IOHCR_G1_IO3_Pos     (2U)
11780 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
11781 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
11782 #define TSC_IOHCR_G1_IO4_Pos     (3U)
11783 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
11784 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
11785 #define TSC_IOHCR_G2_IO1_Pos     (4U)
11786 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
11787 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
11788 #define TSC_IOHCR_G2_IO2_Pos     (5U)
11789 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
11790 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
11791 #define TSC_IOHCR_G2_IO3_Pos     (6U)
11792 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
11793 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
11794 #define TSC_IOHCR_G2_IO4_Pos     (7U)
11795 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
11796 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
11797 #define TSC_IOHCR_G3_IO1_Pos     (8U)
11798 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
11799 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
11800 #define TSC_IOHCR_G3_IO2_Pos     (9U)
11801 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
11802 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
11803 #define TSC_IOHCR_G3_IO3_Pos     (10U)
11804 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
11805 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
11806 #define TSC_IOHCR_G3_IO4_Pos     (11U)
11807 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
11808 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
11809 #define TSC_IOHCR_G4_IO1_Pos     (12U)
11810 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
11811 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
11812 #define TSC_IOHCR_G4_IO2_Pos     (13U)
11813 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
11814 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
11815 #define TSC_IOHCR_G4_IO3_Pos     (14U)
11816 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
11817 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
11818 #define TSC_IOHCR_G4_IO4_Pos     (15U)
11819 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
11820 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
11821 #define TSC_IOHCR_G5_IO1_Pos     (16U)
11822 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
11823 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
11824 #define TSC_IOHCR_G5_IO2_Pos     (17U)
11825 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
11826 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
11827 #define TSC_IOHCR_G5_IO3_Pos     (18U)
11828 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
11829 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
11830 #define TSC_IOHCR_G5_IO4_Pos     (19U)
11831 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
11832 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
11833 #define TSC_IOHCR_G6_IO1_Pos     (20U)
11834 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
11835 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
11836 #define TSC_IOHCR_G6_IO2_Pos     (21U)
11837 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
11838 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
11839 #define TSC_IOHCR_G6_IO3_Pos     (22U)
11840 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
11841 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
11842 #define TSC_IOHCR_G6_IO4_Pos     (23U)
11843 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
11844 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
11845 #define TSC_IOHCR_G7_IO1_Pos     (24U)
11846 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
11847 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
11848 #define TSC_IOHCR_G7_IO2_Pos     (25U)
11849 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
11850 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
11851 #define TSC_IOHCR_G7_IO3_Pos     (26U)
11852 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
11853 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
11854 #define TSC_IOHCR_G7_IO4_Pos     (27U)
11855 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
11856 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
11857 #define TSC_IOHCR_G8_IO1_Pos     (28U)
11858 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
11859 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
11860 #define TSC_IOHCR_G8_IO2_Pos     (29U)
11861 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
11862 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
11863 #define TSC_IOHCR_G8_IO3_Pos     (30U)
11864 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
11865 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
11866 #define TSC_IOHCR_G8_IO4_Pos     (31U)
11867 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
11868 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
11869 
11870 /*******************  Bit definition for TSC_IOASCR register  *****************/
11871 #define TSC_IOASCR_G1_IO1_Pos    (0U)
11872 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
11873 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
11874 #define TSC_IOASCR_G1_IO2_Pos    (1U)
11875 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
11876 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
11877 #define TSC_IOASCR_G1_IO3_Pos    (2U)
11878 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
11879 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
11880 #define TSC_IOASCR_G1_IO4_Pos    (3U)
11881 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
11882 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
11883 #define TSC_IOASCR_G2_IO1_Pos    (4U)
11884 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
11885 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
11886 #define TSC_IOASCR_G2_IO2_Pos    (5U)
11887 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
11888 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
11889 #define TSC_IOASCR_G2_IO3_Pos    (6U)
11890 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
11891 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
11892 #define TSC_IOASCR_G2_IO4_Pos    (7U)
11893 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
11894 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
11895 #define TSC_IOASCR_G3_IO1_Pos    (8U)
11896 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
11897 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
11898 #define TSC_IOASCR_G3_IO2_Pos    (9U)
11899 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
11900 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
11901 #define TSC_IOASCR_G3_IO3_Pos    (10U)
11902 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
11903 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
11904 #define TSC_IOASCR_G3_IO4_Pos    (11U)
11905 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
11906 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
11907 #define TSC_IOASCR_G4_IO1_Pos    (12U)
11908 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
11909 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
11910 #define TSC_IOASCR_G4_IO2_Pos    (13U)
11911 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
11912 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
11913 #define TSC_IOASCR_G4_IO3_Pos    (14U)
11914 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
11915 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
11916 #define TSC_IOASCR_G4_IO4_Pos    (15U)
11917 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
11918 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
11919 #define TSC_IOASCR_G5_IO1_Pos    (16U)
11920 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
11921 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
11922 #define TSC_IOASCR_G5_IO2_Pos    (17U)
11923 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
11924 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
11925 #define TSC_IOASCR_G5_IO3_Pos    (18U)
11926 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
11927 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
11928 #define TSC_IOASCR_G5_IO4_Pos    (19U)
11929 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
11930 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
11931 #define TSC_IOASCR_G6_IO1_Pos    (20U)
11932 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
11933 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
11934 #define TSC_IOASCR_G6_IO2_Pos    (21U)
11935 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
11936 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
11937 #define TSC_IOASCR_G6_IO3_Pos    (22U)
11938 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
11939 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
11940 #define TSC_IOASCR_G6_IO4_Pos    (23U)
11941 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
11942 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
11943 #define TSC_IOASCR_G7_IO1_Pos    (24U)
11944 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
11945 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
11946 #define TSC_IOASCR_G7_IO2_Pos    (25U)
11947 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
11948 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
11949 #define TSC_IOASCR_G7_IO3_Pos    (26U)
11950 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
11951 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
11952 #define TSC_IOASCR_G7_IO4_Pos    (27U)
11953 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
11954 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
11955 #define TSC_IOASCR_G8_IO1_Pos    (28U)
11956 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
11957 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
11958 #define TSC_IOASCR_G8_IO2_Pos    (29U)
11959 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
11960 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
11961 #define TSC_IOASCR_G8_IO3_Pos    (30U)
11962 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
11963 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
11964 #define TSC_IOASCR_G8_IO4_Pos    (31U)
11965 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
11966 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
11967 
11968 /*******************  Bit definition for TSC_IOSCR register  ******************/
11969 #define TSC_IOSCR_G1_IO1_Pos     (0U)
11970 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
11971 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
11972 #define TSC_IOSCR_G1_IO2_Pos     (1U)
11973 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
11974 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
11975 #define TSC_IOSCR_G1_IO3_Pos     (2U)
11976 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
11977 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
11978 #define TSC_IOSCR_G1_IO4_Pos     (3U)
11979 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
11980 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
11981 #define TSC_IOSCR_G2_IO1_Pos     (4U)
11982 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
11983 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
11984 #define TSC_IOSCR_G2_IO2_Pos     (5U)
11985 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
11986 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
11987 #define TSC_IOSCR_G2_IO3_Pos     (6U)
11988 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
11989 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
11990 #define TSC_IOSCR_G2_IO4_Pos     (7U)
11991 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
11992 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
11993 #define TSC_IOSCR_G3_IO1_Pos     (8U)
11994 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
11995 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
11996 #define TSC_IOSCR_G3_IO2_Pos     (9U)
11997 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
11998 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
11999 #define TSC_IOSCR_G3_IO3_Pos     (10U)
12000 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
12001 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
12002 #define TSC_IOSCR_G3_IO4_Pos     (11U)
12003 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
12004 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
12005 #define TSC_IOSCR_G4_IO1_Pos     (12U)
12006 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
12007 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
12008 #define TSC_IOSCR_G4_IO2_Pos     (13U)
12009 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
12010 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
12011 #define TSC_IOSCR_G4_IO3_Pos     (14U)
12012 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
12013 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
12014 #define TSC_IOSCR_G4_IO4_Pos     (15U)
12015 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
12016 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
12017 #define TSC_IOSCR_G5_IO1_Pos     (16U)
12018 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
12019 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
12020 #define TSC_IOSCR_G5_IO2_Pos     (17U)
12021 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
12022 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
12023 #define TSC_IOSCR_G5_IO3_Pos     (18U)
12024 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
12025 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
12026 #define TSC_IOSCR_G5_IO4_Pos     (19U)
12027 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
12028 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
12029 #define TSC_IOSCR_G6_IO1_Pos     (20U)
12030 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
12031 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
12032 #define TSC_IOSCR_G6_IO2_Pos     (21U)
12033 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
12034 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
12035 #define TSC_IOSCR_G6_IO3_Pos     (22U)
12036 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
12037 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
12038 #define TSC_IOSCR_G6_IO4_Pos     (23U)
12039 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
12040 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
12041 #define TSC_IOSCR_G7_IO1_Pos     (24U)
12042 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
12043 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
12044 #define TSC_IOSCR_G7_IO2_Pos     (25U)
12045 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
12046 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
12047 #define TSC_IOSCR_G7_IO3_Pos     (26U)
12048 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
12049 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
12050 #define TSC_IOSCR_G7_IO4_Pos     (27U)
12051 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
12052 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
12053 #define TSC_IOSCR_G8_IO1_Pos     (28U)
12054 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
12055 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
12056 #define TSC_IOSCR_G8_IO2_Pos     (29U)
12057 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
12058 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
12059 #define TSC_IOSCR_G8_IO3_Pos     (30U)
12060 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
12061 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
12062 #define TSC_IOSCR_G8_IO4_Pos     (31U)
12063 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
12064 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
12065 
12066 /*******************  Bit definition for TSC_IOCCR register  ******************/
12067 #define TSC_IOCCR_G1_IO1_Pos     (0U)
12068 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
12069 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
12070 #define TSC_IOCCR_G1_IO2_Pos     (1U)
12071 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
12072 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
12073 #define TSC_IOCCR_G1_IO3_Pos     (2U)
12074 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
12075 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
12076 #define TSC_IOCCR_G1_IO4_Pos     (3U)
12077 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
12078 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
12079 #define TSC_IOCCR_G2_IO1_Pos     (4U)
12080 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
12081 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
12082 #define TSC_IOCCR_G2_IO2_Pos     (5U)
12083 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
12084 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
12085 #define TSC_IOCCR_G2_IO3_Pos     (6U)
12086 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
12087 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
12088 #define TSC_IOCCR_G2_IO4_Pos     (7U)
12089 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
12090 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
12091 #define TSC_IOCCR_G3_IO1_Pos     (8U)
12092 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
12093 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
12094 #define TSC_IOCCR_G3_IO2_Pos     (9U)
12095 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
12096 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
12097 #define TSC_IOCCR_G3_IO3_Pos     (10U)
12098 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
12099 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
12100 #define TSC_IOCCR_G3_IO4_Pos     (11U)
12101 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
12102 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
12103 #define TSC_IOCCR_G4_IO1_Pos     (12U)
12104 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
12105 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
12106 #define TSC_IOCCR_G4_IO2_Pos     (13U)
12107 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
12108 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
12109 #define TSC_IOCCR_G4_IO3_Pos     (14U)
12110 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
12111 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
12112 #define TSC_IOCCR_G4_IO4_Pos     (15U)
12113 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
12114 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
12115 #define TSC_IOCCR_G5_IO1_Pos     (16U)
12116 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
12117 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
12118 #define TSC_IOCCR_G5_IO2_Pos     (17U)
12119 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
12120 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
12121 #define TSC_IOCCR_G5_IO3_Pos     (18U)
12122 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
12123 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
12124 #define TSC_IOCCR_G5_IO4_Pos     (19U)
12125 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
12126 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
12127 #define TSC_IOCCR_G6_IO1_Pos     (20U)
12128 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
12129 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
12130 #define TSC_IOCCR_G6_IO2_Pos     (21U)
12131 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
12132 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
12133 #define TSC_IOCCR_G6_IO3_Pos     (22U)
12134 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
12135 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
12136 #define TSC_IOCCR_G6_IO4_Pos     (23U)
12137 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
12138 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
12139 #define TSC_IOCCR_G7_IO1_Pos     (24U)
12140 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
12141 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
12142 #define TSC_IOCCR_G7_IO2_Pos     (25U)
12143 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
12144 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
12145 #define TSC_IOCCR_G7_IO3_Pos     (26U)
12146 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
12147 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
12148 #define TSC_IOCCR_G7_IO4_Pos     (27U)
12149 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
12150 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
12151 #define TSC_IOCCR_G8_IO1_Pos     (28U)
12152 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
12153 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
12154 #define TSC_IOCCR_G8_IO2_Pos     (29U)
12155 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
12156 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
12157 #define TSC_IOCCR_G8_IO3_Pos     (30U)
12158 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
12159 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
12160 #define TSC_IOCCR_G8_IO4_Pos     (31U)
12161 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
12162 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
12163 
12164 /*******************  Bit definition for TSC_IOGCSR register  *****************/
12165 #define TSC_IOGCSR_G1E_Pos       (0U)
12166 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
12167 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
12168 #define TSC_IOGCSR_G2E_Pos       (1U)
12169 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
12170 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
12171 #define TSC_IOGCSR_G3E_Pos       (2U)
12172 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
12173 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
12174 #define TSC_IOGCSR_G4E_Pos       (3U)
12175 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
12176 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
12177 #define TSC_IOGCSR_G5E_Pos       (4U)
12178 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
12179 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
12180 #define TSC_IOGCSR_G6E_Pos       (5U)
12181 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
12182 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
12183 #define TSC_IOGCSR_G7E_Pos       (6U)
12184 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
12185 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
12186 #define TSC_IOGCSR_G8E_Pos       (7U)
12187 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
12188 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
12189 #define TSC_IOGCSR_G1S_Pos       (16U)
12190 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
12191 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
12192 #define TSC_IOGCSR_G2S_Pos       (17U)
12193 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
12194 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
12195 #define TSC_IOGCSR_G3S_Pos       (18U)
12196 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
12197 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
12198 #define TSC_IOGCSR_G4S_Pos       (19U)
12199 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
12200 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
12201 #define TSC_IOGCSR_G5S_Pos       (20U)
12202 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
12203 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
12204 #define TSC_IOGCSR_G6S_Pos       (21U)
12205 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
12206 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
12207 #define TSC_IOGCSR_G7S_Pos       (22U)
12208 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
12209 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
12210 #define TSC_IOGCSR_G8S_Pos       (23U)
12211 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
12212 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
12213 
12214 /*******************  Bit definition for TSC_IOGXCR register  *****************/
12215 #define TSC_IOGXCR_CNT_Pos       (0U)
12216 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
12217 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
12218 
12219 /******************************************************************************/
12220 /*                                                                            */
12221 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
12222 /*                                                                            */
12223 /******************************************************************************/
12224 /******************  Bit definition for USART_CR1 register  *******************/
12225 #define USART_CR1_UE_Pos              (0U)
12226 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
12227 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
12228 #define USART_CR1_UESM_Pos            (1U)
12229 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
12230 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
12231 #define USART_CR1_RE_Pos              (2U)
12232 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
12233 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
12234 #define USART_CR1_TE_Pos              (3U)
12235 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
12236 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
12237 #define USART_CR1_IDLEIE_Pos          (4U)
12238 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
12239 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
12240 #define USART_CR1_RXNEIE_Pos          (5U)
12241 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
12242 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
12243 #define USART_CR1_TCIE_Pos            (6U)
12244 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
12245 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
12246 #define USART_CR1_TXEIE_Pos           (7U)
12247 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
12248 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
12249 #define USART_CR1_PEIE_Pos            (8U)
12250 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
12251 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
12252 #define USART_CR1_PS_Pos              (9U)
12253 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
12254 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
12255 #define USART_CR1_PCE_Pos             (10U)
12256 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
12257 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
12258 #define USART_CR1_WAKE_Pos            (11U)
12259 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
12260 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
12261 #define USART_CR1_M_Pos               (12U)
12262 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
12263 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
12264 #define USART_CR1_M0_Pos              (12U)
12265 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
12266 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< SmartCard Word length */
12267 #define USART_CR1_MME_Pos             (13U)
12268 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
12269 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
12270 #define USART_CR1_CMIE_Pos            (14U)
12271 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
12272 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
12273 #define USART_CR1_OVER8_Pos           (15U)
12274 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
12275 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
12276 #define USART_CR1_DEDT_Pos            (16U)
12277 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
12278 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
12279 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
12280 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
12281 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
12282 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
12283 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
12284 #define USART_CR1_DEAT_Pos            (21U)
12285 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
12286 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
12287 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
12288 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
12289 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
12290 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
12291 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
12292 #define USART_CR1_RTOIE_Pos           (26U)
12293 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
12294 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
12295 #define USART_CR1_EOBIE_Pos           (27U)
12296 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
12297 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
12298 
12299 /******************  Bit definition for USART_CR2 register  *******************/
12300 #define USART_CR2_ADDM7_Pos           (4U)
12301 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
12302 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
12303 #define USART_CR2_LBDL_Pos            (5U)
12304 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
12305 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
12306 #define USART_CR2_LBDIE_Pos           (6U)
12307 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
12308 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
12309 #define USART_CR2_LBCL_Pos            (8U)
12310 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
12311 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
12312 #define USART_CR2_CPHA_Pos            (9U)
12313 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
12314 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
12315 #define USART_CR2_CPOL_Pos            (10U)
12316 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
12317 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
12318 #define USART_CR2_CLKEN_Pos           (11U)
12319 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
12320 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
12321 #define USART_CR2_STOP_Pos            (12U)
12322 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
12323 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
12324 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
12325 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
12326 #define USART_CR2_LINEN_Pos           (14U)
12327 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
12328 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
12329 #define USART_CR2_SWAP_Pos            (15U)
12330 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
12331 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
12332 #define USART_CR2_RXINV_Pos           (16U)
12333 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
12334 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
12335 #define USART_CR2_TXINV_Pos           (17U)
12336 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
12337 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
12338 #define USART_CR2_DATAINV_Pos         (18U)
12339 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
12340 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
12341 #define USART_CR2_MSBFIRST_Pos        (19U)
12342 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
12343 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
12344 #define USART_CR2_ABREN_Pos           (20U)
12345 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
12346 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
12347 #define USART_CR2_ABRMODE_Pos         (21U)
12348 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
12349 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
12350 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
12351 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
12352 #define USART_CR2_RTOEN_Pos           (23U)
12353 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
12354 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
12355 #define USART_CR2_ADD_Pos             (24U)
12356 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
12357 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
12358 
12359 /******************  Bit definition for USART_CR3 register  *******************/
12360 #define USART_CR3_EIE_Pos             (0U)
12361 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
12362 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
12363 #define USART_CR3_IREN_Pos            (1U)
12364 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
12365 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
12366 #define USART_CR3_IRLP_Pos            (2U)
12367 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
12368 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
12369 #define USART_CR3_HDSEL_Pos           (3U)
12370 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
12371 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
12372 #define USART_CR3_NACK_Pos            (4U)
12373 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
12374 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
12375 #define USART_CR3_SCEN_Pos            (5U)
12376 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
12377 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
12378 #define USART_CR3_DMAR_Pos            (6U)
12379 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
12380 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
12381 #define USART_CR3_DMAT_Pos            (7U)
12382 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
12383 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
12384 #define USART_CR3_RTSE_Pos            (8U)
12385 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
12386 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
12387 #define USART_CR3_CTSE_Pos            (9U)
12388 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
12389 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
12390 #define USART_CR3_CTSIE_Pos           (10U)
12391 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
12392 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
12393 #define USART_CR3_ONEBIT_Pos          (11U)
12394 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
12395 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
12396 #define USART_CR3_OVRDIS_Pos          (12U)
12397 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
12398 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
12399 #define USART_CR3_DDRE_Pos            (13U)
12400 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
12401 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
12402 #define USART_CR3_DEM_Pos             (14U)
12403 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
12404 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
12405 #define USART_CR3_DEP_Pos             (15U)
12406 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
12407 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
12408 #define USART_CR3_SCARCNT_Pos         (17U)
12409 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
12410 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
12411 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
12412 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
12413 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
12414 #define USART_CR3_WUS_Pos             (20U)
12415 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
12416 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
12417 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
12418 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
12419 #define USART_CR3_WUFIE_Pos           (22U)
12420 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
12421 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
12422 
12423 /******************  Bit definition for USART_BRR register  *******************/
12424 #define USART_BRR_DIV_FRACTION_Pos    (0U)
12425 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
12426 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
12427 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
12428 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
12429 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
12430 
12431 /******************  Bit definition for USART_GTPR register  ******************/
12432 #define USART_GTPR_PSC_Pos            (0U)
12433 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
12434 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
12435 #define USART_GTPR_GT_Pos             (8U)
12436 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
12437 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
12438 
12439 
12440 /*******************  Bit definition for USART_RTOR register  *****************/
12441 #define USART_RTOR_RTO_Pos            (0U)
12442 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
12443 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
12444 #define USART_RTOR_BLEN_Pos           (24U)
12445 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
12446 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
12447 
12448 /*******************  Bit definition for USART_RQR register  ******************/
12449 #define USART_RQR_ABRRQ_Pos           (0U)
12450 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
12451 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
12452 #define USART_RQR_SBKRQ_Pos           (1U)
12453 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
12454 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
12455 #define USART_RQR_MMRQ_Pos            (2U)
12456 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
12457 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
12458 #define USART_RQR_RXFRQ_Pos           (3U)
12459 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
12460 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
12461 #define USART_RQR_TXFRQ_Pos           (4U)
12462 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
12463 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
12464 
12465 /*******************  Bit definition for USART_ISR register  ******************/
12466 #define USART_ISR_PE_Pos              (0U)
12467 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
12468 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
12469 #define USART_ISR_FE_Pos              (1U)
12470 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
12471 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
12472 #define USART_ISR_NE_Pos              (2U)
12473 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
12474 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
12475 #define USART_ISR_ORE_Pos             (3U)
12476 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
12477 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
12478 #define USART_ISR_IDLE_Pos            (4U)
12479 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
12480 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
12481 #define USART_ISR_RXNE_Pos            (5U)
12482 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
12483 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
12484 #define USART_ISR_TC_Pos              (6U)
12485 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
12486 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
12487 #define USART_ISR_TXE_Pos             (7U)
12488 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
12489 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
12490 #define USART_ISR_LBDF_Pos            (8U)
12491 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
12492 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
12493 #define USART_ISR_CTSIF_Pos           (9U)
12494 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
12495 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
12496 #define USART_ISR_CTS_Pos             (10U)
12497 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
12498 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
12499 #define USART_ISR_RTOF_Pos            (11U)
12500 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
12501 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
12502 #define USART_ISR_EOBF_Pos            (12U)
12503 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
12504 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
12505 #define USART_ISR_ABRE_Pos            (14U)
12506 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
12507 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
12508 #define USART_ISR_ABRF_Pos            (15U)
12509 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
12510 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
12511 #define USART_ISR_BUSY_Pos            (16U)
12512 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
12513 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
12514 #define USART_ISR_CMF_Pos             (17U)
12515 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
12516 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
12517 #define USART_ISR_SBKF_Pos            (18U)
12518 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
12519 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
12520 #define USART_ISR_RWU_Pos             (19U)
12521 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
12522 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
12523 #define USART_ISR_WUF_Pos             (20U)
12524 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
12525 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
12526 #define USART_ISR_TEACK_Pos           (21U)
12527 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
12528 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
12529 #define USART_ISR_REACK_Pos           (22U)
12530 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
12531 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
12532 
12533 /*******************  Bit definition for USART_ICR register  ******************/
12534 #define USART_ICR_PECF_Pos            (0U)
12535 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
12536 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
12537 #define USART_ICR_FECF_Pos            (1U)
12538 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
12539 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
12540 #define USART_ICR_NCF_Pos             (2U)
12541 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
12542 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
12543 #define USART_ICR_ORECF_Pos           (3U)
12544 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
12545 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
12546 #define USART_ICR_IDLECF_Pos          (4U)
12547 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
12548 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
12549 #define USART_ICR_TCCF_Pos            (6U)
12550 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
12551 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
12552 #define USART_ICR_LBDCF_Pos           (8U)
12553 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
12554 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
12555 #define USART_ICR_CTSCF_Pos           (9U)
12556 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
12557 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
12558 #define USART_ICR_RTOCF_Pos           (11U)
12559 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
12560 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
12561 #define USART_ICR_EOBCF_Pos           (12U)
12562 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
12563 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
12564 #define USART_ICR_CMCF_Pos            (17U)
12565 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
12566 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
12567 #define USART_ICR_WUCF_Pos            (20U)
12568 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
12569 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
12570 
12571 /*******************  Bit definition for USART_RDR register  ******************/
12572 #define USART_RDR_RDR_Pos             (0U)
12573 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
12574 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
12575 
12576 /*******************  Bit definition for USART_TDR register  ******************/
12577 #define USART_TDR_TDR_Pos             (0U)
12578 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
12579 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
12580 
12581 /******************************************************************************/
12582 /*                                                                            */
12583 /*                            Window WATCHDOG                                 */
12584 /*                                                                            */
12585 /******************************************************************************/
12586 /*******************  Bit definition for WWDG_CR register  ********************/
12587 #define WWDG_CR_T_Pos           (0U)
12588 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
12589 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
12590 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
12591 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
12592 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
12593 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
12594 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
12595 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
12596 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
12597 
12598 /* Legacy defines */
12599 #define  WWDG_CR_T0 WWDG_CR_T_0
12600 #define  WWDG_CR_T1 WWDG_CR_T_1
12601 #define  WWDG_CR_T2 WWDG_CR_T_2
12602 #define  WWDG_CR_T3 WWDG_CR_T_3
12603 #define  WWDG_CR_T4 WWDG_CR_T_4
12604 #define  WWDG_CR_T5 WWDG_CR_T_5
12605 #define  WWDG_CR_T6 WWDG_CR_T_6
12606 
12607 #define WWDG_CR_WDGA_Pos        (7U)
12608 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
12609 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
12610 
12611 /*******************  Bit definition for WWDG_CFR register  *******************/
12612 #define WWDG_CFR_W_Pos          (0U)
12613 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
12614 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
12615 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
12616 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
12617 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
12618 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
12619 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
12620 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
12621 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
12622 
12623 /* Legacy defines */
12624 #define  WWDG_CFR_W0 WWDG_CFR_W_0
12625 #define  WWDG_CFR_W1 WWDG_CFR_W_1
12626 #define  WWDG_CFR_W2 WWDG_CFR_W_2
12627 #define  WWDG_CFR_W3 WWDG_CFR_W_3
12628 #define  WWDG_CFR_W4 WWDG_CFR_W_4
12629 #define  WWDG_CFR_W5 WWDG_CFR_W_5
12630 #define  WWDG_CFR_W6 WWDG_CFR_W_6
12631 
12632 #define WWDG_CFR_WDGTB_Pos      (7U)
12633 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
12634 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
12635 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
12636 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
12637 
12638 /* Legacy defines */
12639 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12640 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12641 
12642 #define WWDG_CFR_EWI_Pos        (9U)
12643 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
12644 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
12645 
12646 /*******************  Bit definition for WWDG_SR register  ********************/
12647 #define WWDG_SR_EWIF_Pos        (0U)
12648 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
12649 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
12650 
12651 /**
12652   * @}
12653   */
12654 
12655  /**
12656   * @}
12657   */
12658 
12659 /** @addtogroup Exported_macros
12660   * @{
12661   */
12662 
12663 /****************************** ADC Instances *********************************/
12664 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
12665                                        ((INSTANCE) == ADC2) || \
12666                                        ((INSTANCE) == ADC3) || \
12667                                        ((INSTANCE) == ADC4))
12668 
12669 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
12670                                                     ((INSTANCE) == ADC3))
12671 
12672 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
12673                                           ((INSTANCE) == ADC34_COMMON))
12674 
12675 /****************************** CAN Instances *********************************/
12676 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
12677 
12678 /****************************** COMP Instances ********************************/
12679 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
12680                                         ((INSTANCE) == COMP2) || \
12681                                         ((INSTANCE) == COMP3) || \
12682                                         ((INSTANCE) == COMP4) || \
12683                                         ((INSTANCE) == COMP5) || \
12684                                         ((INSTANCE) == COMP6) || \
12685                                         ((INSTANCE) == COMP7))
12686 
12687 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \
12688                                                   ((COMMON_INSTANCE) == COMP34_COMMON) || \
12689                                                   ((COMMON_INSTANCE) == COMP56_COMMON))
12690 
12691 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
12692 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
12693 
12694 /******************** COMP Instances with window mode capability **************/
12695 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
12696                                                ((INSTANCE) == COMP4) || \
12697                                                ((INSTANCE) == COMP6))
12698 
12699 /****************************** CRC Instances *********************************/
12700 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
12701 
12702 /****************************** DAC Instances *********************************/
12703 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
12704 
12705 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
12706     ((((INSTANCE) == DAC1) &&                   \
12707      (((CHANNEL) == DAC_CHANNEL_1) ||          \
12708       ((CHANNEL) == DAC_CHANNEL_2))))
12709 
12710 /****************************** DMA Instances *********************************/
12711 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
12712                                        ((INSTANCE) == DMA1_Channel2) || \
12713                                        ((INSTANCE) == DMA1_Channel3) || \
12714                                        ((INSTANCE) == DMA1_Channel4) || \
12715                                        ((INSTANCE) == DMA1_Channel5) || \
12716                                        ((INSTANCE) == DMA1_Channel6) || \
12717                                        ((INSTANCE) == DMA1_Channel7) || \
12718                                        ((INSTANCE) == DMA2_Channel1) || \
12719                                        ((INSTANCE) == DMA2_Channel2) || \
12720                                        ((INSTANCE) == DMA2_Channel3) || \
12721                                        ((INSTANCE) == DMA2_Channel4) || \
12722                                        ((INSTANCE) == DMA2_Channel5))
12723 
12724 /****************************** GPIO Instances ********************************/
12725 #define IS_GPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
12726                                          ((INSTANCE) == GPIOB) || \
12727                                          ((INSTANCE) == GPIOC) || \
12728                                          ((INSTANCE) == GPIOD) || \
12729                                          ((INSTANCE) == GPIOE) || \
12730                                          ((INSTANCE) == GPIOF))
12731 
12732 #define IS_GPIO_AF_INSTANCE(INSTANCE)   (((INSTANCE) == GPIOA) || \
12733                                          ((INSTANCE) == GPIOB) || \
12734                                          ((INSTANCE) == GPIOC) || \
12735                                          ((INSTANCE) == GPIOD) || \
12736                                          ((INSTANCE) == GPIOE) || \
12737                                          ((INSTANCE) == GPIOF))
12738 
12739 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
12740                                          ((INSTANCE) == GPIOB) || \
12741                                          ((INSTANCE) == GPIOD))
12742 
12743 /****************************** I2C Instances *********************************/
12744 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
12745                                        ((INSTANCE) == I2C2))
12746 
12747 /****************** I2C Instances : wakeup capability from stop modes *********/
12748 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
12749 
12750 /****************************** I2S Instances *********************************/
12751 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
12752                                        ((INSTANCE) == SPI3))
12753 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \
12754                                            ((INSTANCE) == I2S3ext))
12755 
12756 /****************************** OPAMP Instances *******************************/
12757 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
12758                                          ((INSTANCE) == OPAMP2) || \
12759                                          ((INSTANCE) == OPAMP3) || \
12760                                          ((INSTANCE) == OPAMP4))
12761 
12762 /****************************** IWDG Instances ********************************/
12763 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
12764 
12765 /****************************** RTC Instances *********************************/
12766 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
12767 
12768 /****************************** SMBUS Instances *******************************/
12769 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
12770                                          ((INSTANCE) == I2C2))
12771 
12772 /****************************** SPI Instances *********************************/
12773 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
12774                                        ((INSTANCE) == SPI2) || \
12775                                        ((INSTANCE) == SPI3))
12776 
12777 /******************* TIM Instances : All supported instances ******************/
12778 #define IS_TIM_INSTANCE(INSTANCE)\
12779   (((INSTANCE) == TIM1)    || \
12780    ((INSTANCE) == TIM2)    || \
12781    ((INSTANCE) == TIM3)    || \
12782    ((INSTANCE) == TIM4)    || \
12783    ((INSTANCE) == TIM6)    || \
12784    ((INSTANCE) == TIM7)    || \
12785    ((INSTANCE) == TIM8)    || \
12786    ((INSTANCE) == TIM15)   || \
12787    ((INSTANCE) == TIM16)   || \
12788    ((INSTANCE) == TIM17))
12789 
12790 /******************* TIM Instances : at least 1 capture/compare channel *******/
12791 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
12792   (((INSTANCE) == TIM1)    || \
12793    ((INSTANCE) == TIM2)    || \
12794    ((INSTANCE) == TIM3)    || \
12795    ((INSTANCE) == TIM4)    || \
12796    ((INSTANCE) == TIM8)    || \
12797    ((INSTANCE) == TIM15)   || \
12798    ((INSTANCE) == TIM16)   || \
12799    ((INSTANCE) == TIM17))
12800 
12801 /****************** TIM Instances : at least 2 capture/compare channels *******/
12802 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
12803   (((INSTANCE) == TIM1)    || \
12804    ((INSTANCE) == TIM2)    || \
12805    ((INSTANCE) == TIM3)    || \
12806    ((INSTANCE) == TIM4)    || \
12807    ((INSTANCE) == TIM8)    || \
12808    ((INSTANCE) == TIM15))
12809 
12810 /****************** TIM Instances : at least 3 capture/compare channels *******/
12811 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
12812   (((INSTANCE) == TIM1)    || \
12813    ((INSTANCE) == TIM2)    || \
12814    ((INSTANCE) == TIM3)    || \
12815    ((INSTANCE) == TIM4)    || \
12816    ((INSTANCE) == TIM8))
12817 
12818 /****************** TIM Instances : at least 4 capture/compare channels *******/
12819 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
12820   (((INSTANCE) == TIM1)    || \
12821    ((INSTANCE) == TIM2)    || \
12822    ((INSTANCE) == TIM3)    || \
12823    ((INSTANCE) == TIM4)    || \
12824    ((INSTANCE) == TIM8))
12825 
12826 /****************** TIM Instances : at least 5 capture/compare channels *******/
12827 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
12828   (((INSTANCE) == TIM1)    || \
12829    ((INSTANCE) == TIM8))
12830 
12831 /****************** TIM Instances : at least 6 capture/compare channels *******/
12832 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
12833   (((INSTANCE) == TIM1)    || \
12834    ((INSTANCE) == TIM8))
12835 
12836 /************************** TIM Instances : Advanced-control timers ***********/
12837 
12838 /****************** TIM Instances : Advanced timer instances *******************/
12839 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
12840   (((INSTANCE) == TIM1)    || \
12841    ((INSTANCE) == TIM8))
12842 
12843 /****************** TIM Instances : supporting clock selection ****************/
12844 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
12845   (((INSTANCE) == TIM1)    || \
12846    ((INSTANCE) == TIM2)    || \
12847    ((INSTANCE) == TIM3)    || \
12848    ((INSTANCE) == TIM4)    || \
12849    ((INSTANCE) == TIM8)    || \
12850    ((INSTANCE) == TIM15))
12851 
12852 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
12853 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
12854   (((INSTANCE) == TIM1)    || \
12855    ((INSTANCE) == TIM2)    || \
12856    ((INSTANCE) == TIM3)    || \
12857    ((INSTANCE) == TIM4)    || \
12858    ((INSTANCE) == TIM8))
12859 
12860 /****************** TIM Instances : supporting external clock mode 2 **********/
12861 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
12862   (((INSTANCE) == TIM1)    || \
12863    ((INSTANCE) == TIM2)    || \
12864    ((INSTANCE) == TIM3)    || \
12865    ((INSTANCE) == TIM4)    || \
12866    ((INSTANCE) == TIM8))
12867 
12868 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
12869 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
12870   (((INSTANCE) == TIM1)    || \
12871    ((INSTANCE) == TIM2)    || \
12872    ((INSTANCE) == TIM3)    || \
12873    ((INSTANCE) == TIM4)    || \
12874    ((INSTANCE) == TIM8)    || \
12875    ((INSTANCE) == TIM15))
12876 
12877 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
12878 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
12879   (((INSTANCE) == TIM1)    || \
12880    ((INSTANCE) == TIM2)    || \
12881    ((INSTANCE) == TIM3)    || \
12882    ((INSTANCE) == TIM4)    || \
12883    ((INSTANCE) == TIM8)    || \
12884    ((INSTANCE) == TIM15))
12885 
12886 /****************** TIM Instances : supporting OCxREF clear *******************/
12887 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
12888   (((INSTANCE) == TIM1)    || \
12889    ((INSTANCE) == TIM2)    || \
12890    ((INSTANCE) == TIM3)    || \
12891    ((INSTANCE) == TIM4)    || \
12892    ((INSTANCE) == TIM8))
12893 
12894 /****************** TIM Instances : supporting encoder interface **************/
12895 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
12896   (((INSTANCE) == TIM1)    || \
12897    ((INSTANCE) == TIM2)    || \
12898    ((INSTANCE) == TIM3)    || \
12899    ((INSTANCE) == TIM4)    || \
12900    ((INSTANCE) == TIM8))
12901 
12902 /****************** TIM Instances : supporting Hall interface *****************/
12903 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
12904   (((INSTANCE) == TIM1)    || \
12905    ((INSTANCE) == TIM8))
12906 
12907 /**************** TIM Instances : external trigger input available ************/
12908 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
12909                                             ((INSTANCE) == TIM2)  || \
12910                                             ((INSTANCE) == TIM3)  || \
12911                                             ((INSTANCE) == TIM4)  || \
12912                                             ((INSTANCE) == TIM8))
12913 
12914 /****************** TIM Instances : supporting input XOR function *************/
12915 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
12916   (((INSTANCE) == TIM1)    || \
12917    ((INSTANCE) == TIM2)    || \
12918    ((INSTANCE) == TIM3)    || \
12919    ((INSTANCE) == TIM4)    || \
12920    ((INSTANCE) == TIM8)    || \
12921    ((INSTANCE) == TIM15))
12922 
12923 /****************** TIM Instances : supporting master mode ********************/
12924 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
12925   (((INSTANCE) == TIM1)    || \
12926    ((INSTANCE) == TIM2)    || \
12927    ((INSTANCE) == TIM3)    || \
12928    ((INSTANCE) == TIM4)    || \
12929    ((INSTANCE) == TIM6)    || \
12930    ((INSTANCE) == TIM7)    || \
12931    ((INSTANCE) == TIM8)   || \
12932    ((INSTANCE) == TIM15))
12933 
12934 /****************** TIM Instances : supporting slave mode *********************/
12935 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
12936   (((INSTANCE) == TIM1)    || \
12937    ((INSTANCE) == TIM2)    || \
12938    ((INSTANCE) == TIM3)    || \
12939    ((INSTANCE) == TIM4)    || \
12940    ((INSTANCE) == TIM8)   || \
12941    ((INSTANCE) == TIM15))
12942 
12943 /****************** TIM Instances : supporting 32 bits counter ****************/
12944 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
12945     ((INSTANCE) == TIM2)
12946 
12947 /****************** TIM Instances : supporting DMA burst **********************/
12948 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
12949     (((INSTANCE) == TIM1)    || \
12950      ((INSTANCE) == TIM2)    || \
12951    ((INSTANCE) == TIM3)    || \
12952    ((INSTANCE) == TIM4)    || \
12953      ((INSTANCE) == TIM8)    || \
12954    ((INSTANCE) == TIM15)   || \
12955    ((INSTANCE) == TIM16)   || \
12956      ((INSTANCE) == TIM17))
12957 
12958 /****************** TIM Instances : supporting the break function *************/
12959 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
12960       (((INSTANCE) == TIM1)    || \
12961        ((INSTANCE) == TIM8)    || \
12962        ((INSTANCE) == TIM15)   || \
12963        ((INSTANCE) == TIM16)   || \
12964        ((INSTANCE) == TIM17))
12965 
12966 /****************** TIM Instances : supporting input/output channel(s) ********/
12967 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
12968     ((((INSTANCE) == TIM1) &&                   \
12969      (((CHANNEL) == TIM_CHANNEL_1) ||          \
12970       ((CHANNEL) == TIM_CHANNEL_2) ||          \
12971       ((CHANNEL) == TIM_CHANNEL_3) ||          \
12972       ((CHANNEL) == TIM_CHANNEL_4) ||          \
12973       ((CHANNEL) == TIM_CHANNEL_5) ||          \
12974       ((CHANNEL) == TIM_CHANNEL_6)))           \
12975     ||                                         \
12976     (((INSTANCE) == TIM2) &&                   \
12977      (((CHANNEL) == TIM_CHANNEL_1) ||          \
12978       ((CHANNEL) == TIM_CHANNEL_2) ||          \
12979       ((CHANNEL) == TIM_CHANNEL_3) ||          \
12980       ((CHANNEL) == TIM_CHANNEL_4)))           \
12981     ||                                         \
12982     (((INSTANCE) == TIM3) &&                   \
12983      (((CHANNEL) == TIM_CHANNEL_1) ||          \
12984       ((CHANNEL) == TIM_CHANNEL_2) ||          \
12985       ((CHANNEL) == TIM_CHANNEL_3) ||          \
12986       ((CHANNEL) == TIM_CHANNEL_4)))           \
12987     ||                                         \
12988     (((INSTANCE) == TIM4) &&                   \
12989      (((CHANNEL) == TIM_CHANNEL_1) ||          \
12990       ((CHANNEL) == TIM_CHANNEL_2) ||          \
12991       ((CHANNEL) == TIM_CHANNEL_3) ||          \
12992       ((CHANNEL) == TIM_CHANNEL_4)))           \
12993     ||                                         \
12994     (((INSTANCE) == TIM8) &&                   \
12995      (((CHANNEL) == TIM_CHANNEL_1) ||          \
12996       ((CHANNEL) == TIM_CHANNEL_2) ||          \
12997       ((CHANNEL) == TIM_CHANNEL_3) ||          \
12998       ((CHANNEL) == TIM_CHANNEL_4) ||          \
12999       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13000       ((CHANNEL) == TIM_CHANNEL_6)))           \
13001     ||                                         \
13002     (((INSTANCE) == TIM15) &&                  \
13003      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13004       ((CHANNEL) == TIM_CHANNEL_2)))           \
13005     ||                                         \
13006     (((INSTANCE) == TIM16) &&                  \
13007      (((CHANNEL) == TIM_CHANNEL_1)))           \
13008     ||                                         \
13009     (((INSTANCE) == TIM17) &&                  \
13010      (((CHANNEL) == TIM_CHANNEL_1))))
13011 
13012 /****************** TIM Instances : supporting complementary output(s) ********/
13013 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
13014    ((((INSTANCE) == TIM1) &&                    \
13015      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13016       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13017       ((CHANNEL) == TIM_CHANNEL_3)))            \
13018     ||                                         \
13019     (((INSTANCE) == TIM8) &&                    \
13020      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13021       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13022       ((CHANNEL) == TIM_CHANNEL_3)))            \
13023     ||                                          \
13024     (((INSTANCE) == TIM15) &&                   \
13025       ((CHANNEL) == TIM_CHANNEL_1))             \
13026     ||                                          \
13027     (((INSTANCE) == TIM16) &&                   \
13028      ((CHANNEL) == TIM_CHANNEL_1))              \
13029     ||                                          \
13030     (((INSTANCE) == TIM17) &&                   \
13031      ((CHANNEL) == TIM_CHANNEL_1)))
13032 
13033 /****************** TIM Instances : supporting counting mode selection ********/
13034 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
13035   (((INSTANCE) == TIM1)    || \
13036    ((INSTANCE) == TIM2)    || \
13037    ((INSTANCE) == TIM3)    || \
13038    ((INSTANCE) == TIM4)    || \
13039    ((INSTANCE) == TIM8))
13040 
13041 /****************** TIM Instances : supporting repetition counter *************/
13042 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
13043   (((INSTANCE) == TIM1)    || \
13044    ((INSTANCE) == TIM8)    || \
13045    ((INSTANCE) == TIM15)   || \
13046    ((INSTANCE) == TIM16)   || \
13047    ((INSTANCE) == TIM17))
13048 
13049 /****************** TIM Instances : supporting clock division *****************/
13050 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
13051   (((INSTANCE) == TIM1)    || \
13052    ((INSTANCE) == TIM2)    || \
13053    ((INSTANCE) == TIM3)    || \
13054    ((INSTANCE) == TIM4)    || \
13055    ((INSTANCE) == TIM8)    || \
13056    ((INSTANCE) == TIM15)   || \
13057    ((INSTANCE) == TIM16)   || \
13058    ((INSTANCE) == TIM17))
13059 
13060 /****************** TIM Instances : supporting 2 break inputs *****************/
13061 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
13062   (((INSTANCE) == TIM1)    || \
13063    ((INSTANCE) == TIM8))
13064 
13065 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
13066 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
13067   (((INSTANCE) == TIM1)    || \
13068    ((INSTANCE) == TIM8))
13069 
13070 /****************** TIM Instances : supporting DMA generation on Update events*/
13071 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
13072   (((INSTANCE) == TIM1)    || \
13073    ((INSTANCE) == TIM2)    || \
13074    ((INSTANCE) == TIM3)    || \
13075    ((INSTANCE) == TIM4)    || \
13076    ((INSTANCE) == TIM6)    || \
13077    ((INSTANCE) == TIM7)    || \
13078    ((INSTANCE) == TIM8)    || \
13079    ((INSTANCE) == TIM15)   || \
13080    ((INSTANCE) == TIM16)   || \
13081    ((INSTANCE) == TIM17))
13082 
13083 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
13084 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
13085   (((INSTANCE) == TIM1)    || \
13086    ((INSTANCE) == TIM2)    || \
13087    ((INSTANCE) == TIM3)    || \
13088    ((INSTANCE) == TIM4)    || \
13089    ((INSTANCE) == TIM8)    || \
13090    ((INSTANCE) == TIM15)   || \
13091    ((INSTANCE) == TIM16)   || \
13092    ((INSTANCE) == TIM17))
13093 
13094 /****************** TIM Instances : supporting commutation event generation ***/
13095 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
13096   (((INSTANCE) == TIM1)    || \
13097    ((INSTANCE) == TIM8)    || \
13098    ((INSTANCE) == TIM15)   || \
13099    ((INSTANCE) == TIM16)   || \
13100    ((INSTANCE) == TIM17))
13101 
13102 /****************** TIM Instances : supporting remapping capability ***********/
13103 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
13104   (((INSTANCE) == TIM1)    || \
13105    ((INSTANCE) == TIM8)   || \
13106    ((INSTANCE) == TIM16))
13107 
13108 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
13109 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
13110   (((INSTANCE) == TIM1)    || \
13111    ((INSTANCE) == TIM8))
13112 
13113 /****************************** TSC Instances *********************************/
13114 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
13115 
13116 /******************** USART Instances : Synchronous mode **********************/
13117 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13118                                      ((INSTANCE) == USART2) || \
13119                                      ((INSTANCE) == USART3))
13120 
13121 /****************** USART Instances : Auto Baud Rate detection ****************/
13122 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13123                                                             ((INSTANCE) == USART2) || \
13124                                                             ((INSTANCE) == USART3))
13125 
13126 /******************** UART Instances : Asynchronous mode **********************/
13127 #define IS_UART_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13128                                       ((INSTANCE) == USART2) || \
13129                                       ((INSTANCE) == USART3) || \
13130                                       ((INSTANCE) == UART4)  || \
13131                                       ((INSTANCE) == UART5))
13132 
13133 /******************** UART Instances : Half-Duplex mode **********************/
13134 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13135                                                  ((INSTANCE) == USART2) || \
13136                                                  ((INSTANCE) == USART3) || \
13137                                                  ((INSTANCE) == UART4)  || \
13138                                                  ((INSTANCE) == UART5))
13139 
13140 /******************** UART Instances : LIN mode **********************/
13141 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13142                                           ((INSTANCE) == USART2) || \
13143                                           ((INSTANCE) == USART3) || \
13144                                           ((INSTANCE) == UART4)  || \
13145                                           ((INSTANCE) == UART5))
13146 
13147 /******************** UART Instances : Wake-up from Stop mode **********************/
13148 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
13149                                                       ((INSTANCE) == USART2) || \
13150                                                       ((INSTANCE) == USART3) || \
13151                                                       ((INSTANCE) == UART4)  || \
13152                                                       ((INSTANCE) == UART5))
13153 
13154 /****************** UART Instances : Hardware Flow control ********************/
13155 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13156                                            ((INSTANCE) == USART2) || \
13157                                            ((INSTANCE) == USART3))
13158 
13159 /****************** UART Instances : Auto Baud Rate detection *****************/
13160 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13161                                                            ((INSTANCE) == USART2) || \
13162                                                            ((INSTANCE) == USART3))
13163 
13164 /****************** UART Instances : Driver Enable ****************************/
13165 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13166                                                   ((INSTANCE) == USART2) || \
13167                                                   ((INSTANCE) == USART3))
13168 
13169 /********************* UART Instances : Smard card mode ***********************/
13170 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13171                                          ((INSTANCE) == USART2) || \
13172                                          ((INSTANCE) == USART3))
13173 
13174 /*********************** UART Instances : IRDA mode ***************************/
13175 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13176                                     ((INSTANCE) == USART2) || \
13177                                     ((INSTANCE) == USART3) || \
13178                                     ((INSTANCE) == UART4)  || \
13179                                     ((INSTANCE) == UART5))
13180 
13181 /******************** UART Instances : Support of continuous communication using DMA ****/
13182 #define IS_UART_DMA_INSTANCE(INSTANCE) (1)
13183 
13184 /****************************** WWDG Instances ********************************/
13185 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
13186 
13187 /**
13188   * @}
13189   */
13190 
13191 
13192 /******************************************************************************/
13193 /*  For a painless codes migration between the STM32F3xx device product       */
13194 /*  lines, the aliases defined below are put in place to overcome the         */
13195 /*  differences in the interrupt handlers and IRQn definitions.               */
13196 /*  No need to update developed interrupt code when moving across             */
13197 /*  product lines within the same STM32F3 Family                              */
13198 /******************************************************************************/
13199 
13200 /* Aliases for __IRQn */
13201 #define ADC1_IRQn           ADC1_2_IRQn
13202 #define SDADC1_IRQn         ADC4_IRQn
13203 #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
13204 #define USB_HP_CAN_TX_IRQn  CAN_TX_IRQn
13205 #define COMP1_2_IRQn        COMP1_2_3_IRQn
13206 #define COMP2_IRQn          COMP1_2_3_IRQn
13207 #define COMP_IRQn           COMP1_2_3_IRQn
13208 #define COMP4_6_IRQn        COMP4_5_6_IRQn
13209 #define TIM15_IRQn          TIM1_BRK_TIM15_IRQn
13210 #define TIM18_DAC2_IRQn     TIM1_CC_IRQn
13211 #define TIM17_IRQn          TIM1_TRG_COM_TIM17_IRQn
13212 #define TIM16_IRQn          TIM1_UP_TIM16_IRQn
13213 #define TIM6_DAC1_IRQn      TIM6_DAC_IRQn
13214 #define TIM7_DAC2_IRQn      TIM7_IRQn
13215 #define TIM12_IRQn          TIM8_BRK_IRQn
13216 #define TIM14_IRQn          TIM8_TRG_COM_IRQn
13217 #define TIM13_IRQn          TIM8_UP_IRQn
13218 
13219 
13220 /* Aliases for __IRQHandler */
13221 #define ADC1_IRQHandler           ADC1_2_IRQHandler
13222 #define SDADC1_IRQHandler         ADC4_IRQHandler
13223 #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
13224 #define USB_HP_CAN_TX_IRQHandler  CAN_TX_IRQHandler
13225 #define COMP1_2_IRQHandler        COMP1_2_3_IRQHandler
13226 #define COMP2_IRQHandler          COMP1_2_3_IRQHandler
13227 #define COMP_IRQHandler           COMP1_2_3_IRQHandler
13228 #define COMP4_6_IRQHandler        COMP4_5_6_IRQHandler
13229 #define TIM15_IRQHandler          TIM1_BRK_TIM15_IRQHandler
13230 #define TIM18_DAC2_IRQHandler     TIM1_CC_IRQHandler
13231 #define TIM17_IRQHandler          TIM1_TRG_COM_TIM17_IRQHandler
13232 #define TIM16_IRQHandler          TIM1_UP_TIM16_IRQHandler
13233 #define TIM6_DAC1_IRQHandler      TIM6_DAC_IRQHandler
13234 #define TIM7_DAC2_IRQHandler      TIM7_IRQHandler
13235 #define TIM12_IRQHandler          TIM8_BRK_IRQHandler
13236 #define TIM14_IRQHandler          TIM8_TRG_COM_IRQHandler
13237 #define TIM13_IRQHandler          TIM8_UP_IRQHandler
13238 
13239 
13240 #ifdef __cplusplus
13241 }
13242 #endif /* __cplusplus */
13243 
13244 #endif /* __STM32F358xx_H */
13245 
13246 /**
13247   * @}
13248   */
13249 
13250 /**
13251   * @}
13252   */
13253