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Searched refs:TIM_DCR_DBSS_1 (Results 1 – 25 of 26) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim.c4857 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart()
4877 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5311 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart()
5331 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim.c4853 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart()
4873 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4933 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4953 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5305 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart()
5325 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5385 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5405 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim.c4855 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart()
4875 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4935 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4955 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5309 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart()
5329 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5389 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5409 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h1332 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1
1333 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
1336 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1337 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h1262 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1
1263 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
1266 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1267 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h1403 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1
1404 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
1407 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1408 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8908 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32wba52xx.h13071 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32wba54xx.h13778 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32wba55xx.h13796 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
/hal_stm32-3.5.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7790 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32h562xx.h10476 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32h563xx.h12560 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
Dstm32h573xx.h12995 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
/hal_stm32-3.5.0/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h10921 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u535xx.h10521 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u575xx.h11544 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u5a5xx.h12301 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u585xx.h11993 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u5f7xx.h13350 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u595xx.h11852 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u599xx.h15571 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u5g7xx.h13799 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u5a9xx.h16020 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
Dstm32u5g9xx.h16925 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro

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