/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/ |
D | stm32u5xx_hal_tim.c | 4857 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4877 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5311 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5331 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
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/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/src/ |
D | stm32h5xx_hal_tim.c | 4853 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4873 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4933 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4953 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5305 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5325 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5385 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5405 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/ |
D | stm32wbaxx_hal_tim.c | 4855 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiWriteStart() 4875 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 4935 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart() 4955 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart() 5309 tmpDBSS = TIM_DCR_DBSS_1; in HAL_TIM_DMABurst_MultiReadStart() 5329 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart() 5389 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart() 5409 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
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/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/ |
D | stm32h5xx_ll_tim.h | 1332 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1333 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) … 1336 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) … 1337 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/ |
D | stm32wbaxx_ll_tim.h | 1262 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1263 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) … 1266 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) … 1267 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
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/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/ |
D | stm32u5xx_ll_tim.h | 1403 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 … 1404 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) … 1407 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) … 1408 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
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/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 8908 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32wba52xx.h | 13071 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32wba54xx.h | 13778 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32wba55xx.h | 13796 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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/hal_stm32-3.5.0/stm32cube/stm32h5xx/soc/ |
D | stm32h503xx.h | 7790 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32h562xx.h | 10476 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32h563xx.h | 12560 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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D | stm32h573xx.h | 12995 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00000200… macro
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/hal_stm32-3.5.0/stm32cube/stm32u5xx/soc/ |
D | stm32u545xx.h | 10921 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u535xx.h | 10521 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u575xx.h | 11544 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u5a5xx.h | 12301 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u585xx.h | 11993 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u5f7xx.h | 13350 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u595xx.h | 11852 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u599xx.h | 15571 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u5g7xx.h | 13799 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u5a9xx.h | 16020 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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D | stm32u5g9xx.h | 16925 #define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000… macro
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