1 /**
2   ******************************************************************************
3   * @file    stm32wbaxx_hal_tim.c
4   * @author  MCD Application Team
5   * @brief   TIM HAL module driver.
6   *          This file provides firmware functions to manage the following
7   *          functionalities of the Timer (TIM) peripheral:
8   *           + TIM Time Base Initialization
9   *           + TIM Time Base Start
10   *           + TIM Time Base Start Interruption
11   *           + TIM Time Base Start DMA
12   *           + TIM Output Compare/PWM Initialization
13   *           + TIM Output Compare/PWM Channel Configuration
14   *           + TIM Output Compare/PWM  Start
15   *           + TIM Output Compare/PWM  Start Interruption
16   *           + TIM Output Compare/PWM Start DMA
17   *           + TIM Input Capture Initialization
18   *           + TIM Input Capture Channel Configuration
19   *           + TIM Input Capture Start
20   *           + TIM Input Capture Start Interruption
21   *           + TIM Input Capture Start DMA
22   *           + TIM One Pulse Initialization
23   *           + TIM One Pulse Channel Configuration
24   *           + TIM One Pulse Start
25   *           + TIM Encoder Interface Initialization
26   *           + TIM Encoder Interface Start
27   *           + TIM Encoder Interface Start Interruption
28   *           + TIM Encoder Interface Start DMA
29   *           + Commutation Event configuration with Interruption and DMA
30   *           + TIM OCRef clear configuration
31   *           + TIM External Clock configuration
32   ******************************************************************************
33   * @attention
34   *
35   * Copyright (c) 2022 STMicroelectronics.
36   * All rights reserved.
37   *
38   * This software is licensed under terms that can be found in the LICENSE file
39   * in the root directory of this software component.
40   * If no LICENSE file comes with this software, it is provided AS-IS.
41   *
42   ******************************************************************************
43   @verbatim
44   ==============================================================================
45                       ##### TIMER Generic features #####
46   ==============================================================================
47   [..] The Timer features include:
48        (#) 16-bit up, down, up/down auto-reload counter.
49        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50            counter clock frequency either by any factor between 1 and 65536.
51        (#) Up to 4 independent channels for:
52            (++) Input Capture
53            (++) Output Compare
54            (++) PWM generation (Edge and Center-aligned Mode)
55            (++) One-pulse mode output
56        (#) Synchronization circuit to control the timer with external signals and to interconnect
57             several timers together.
58        (#) Supports incremental encoder for positioning purposes
59 
60             ##### How to use this driver #####
61   ==============================================================================
62     [..]
63      (#) Initialize the TIM low level resources by implementing the following functions
64          depending on the selected feature:
65            (++) Time Base : HAL_TIM_Base_MspInit()
66            (++) Input Capture : HAL_TIM_IC_MspInit()
67            (++) Output Compare : HAL_TIM_OC_MspInit()
68            (++) PWM generation : HAL_TIM_PWM_MspInit()
69            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71 
72      (#) Initialize the TIM low level resources :
73         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74         (##) TIM pins configuration
75             (+++) Enable the clock for the TIM GPIOs using the following function:
76              __HAL_RCC_GPIOx_CLK_ENABLE();
77             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78 
79      (#) The external Clock can be configured, if needed (the default clock is the
80          internal clock from the APBx), using the following function:
81          HAL_TIM_ConfigClockSource, the clock configuration should be done before
82          any start function.
83 
84      (#) Configure the TIM in the desired functioning mode using one of the
85        Initialization function of this driver:
86        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87        (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
88             to use the Timer to generate an Output Compare signal.
89        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90             PWM signal.
91        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92             external signal.
93        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94             in One Pulse Mode.
95        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96 
97      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104 
105      (#) The DMA Burst is managed with the two following functions:
106          HAL_TIM_DMABurst_WriteStart()
107          HAL_TIM_DMABurst_ReadStart()
108 
109     *** Callback registration ***
110   =============================================
111 
112   [..]
113   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114   allows the user to configure dynamically the driver callbacks.
115 
116   [..]
117   Use Function HAL_TIM_RegisterCallback() to register a callback.
118   HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119   the Callback ID and a pointer to the user callback function.
120 
121   [..]
122   Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123   weak function.
124   HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125   and the Callback ID.
126 
127   [..]
128   These functions allow to register/unregister following callbacks:
129     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
130     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
131     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
132     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
133     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
134     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
135     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
136     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
137     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
138     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
139     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
140     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
141     (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
142     (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
143     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
144     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
145     (+) TriggerCallback                   : TIM Trigger Callback.
146     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
147     (+) IC_CaptureCallback                : TIM Input Capture Callback.
148     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
149     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
150     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
151     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152     (+) ErrorCallback                     : TIM Error Callback.
153     (+) CommutationCallback               : TIM Commutation Callback.
154     (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
155     (+) BreakCallback                     : TIM Break Callback.
156     (+) Break2Callback                    : TIM Break2 Callback.
157     (+) EncoderIndexCallback              : TIM Encoder Index Callback.
158     (+) DirectionChangeCallback           : TIM Direction Change Callback
159     (+) IndexErrorCallback                : TIM Index Error Callback.
160     (+) TransitionErrorCallback           : TIM Transition Error Callback
161 
162   [..]
163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
164 all interrupt callbacks are set to the corresponding weak functions:
165   examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
166 
167   [..]
168   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
169   functionalities in the Init / DeInit only when these callbacks are null
170   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
171     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
172 
173   [..]
174     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
175     Exception done MspInit / MspDeInit that can be registered / unregistered
176     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
177     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
178   In that case first register the MspInit/MspDeInit user callbacks
179       using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
180 
181   [..]
182       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
183       not defined, the callback registration feature is not available and all callbacks
184       are set to the corresponding weak functions.
185 
186   @endverbatim
187   ******************************************************************************
188   */
189 
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32wbaxx_hal.h"
192 
193 /** @addtogroup STM32WBAxx_HAL_Driver
194   * @{
195   */
196 
197 /** @defgroup TIM TIM
198   * @brief TIM HAL module driver
199   * @{
200   */
201 
202 #ifdef HAL_TIM_MODULE_ENABLED
203 
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 /** @addtogroup TIM_Private_Constants
207   * @{
208   */
209 #define TIMx_AF2_OCRSEL TIM_AF2_OCRSEL
210 
211 /**
212   * @}
213   */
214 /* Private macros ------------------------------------------------------------*/
215 /* Private variables ---------------------------------------------------------*/
216 /* Private function prototypes -----------------------------------------------*/
217 /** @addtogroup TIM_Private_Functions
218   * @{
219   */
220 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
222 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
223 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
224 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
225 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
226 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
227                               uint32_t TIM_ICFilter);
228 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
229 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
230                               uint32_t TIM_ICFilter);
231 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
232                               uint32_t TIM_ICFilter);
233 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
234 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
235 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
236 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
237 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
238 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
240                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig);
241 /**
242   * @}
243   */
244 /* Exported functions --------------------------------------------------------*/
245 
246 /** @defgroup TIM_Exported_Functions TIM Exported Functions
247   * @{
248   */
249 
250 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
251   *  @brief    Time Base functions
252   *
253 @verbatim
254   ==============================================================================
255               ##### Time Base functions #####
256   ==============================================================================
257   [..]
258     This section provides functions allowing to:
259     (+) Initialize and configure the TIM base.
260     (+) De-initialize the TIM base.
261     (+) Start the Time Base.
262     (+) Stop the Time Base.
263     (+) Start the Time Base and enable interrupt.
264     (+) Stop the Time Base and disable interrupt.
265     (+) Start the Time Base and enable DMA transfer.
266     (+) Stop the Time Base and disable DMA transfer.
267 
268 @endverbatim
269   * @{
270   */
271 /**
272   * @brief  Initializes the TIM Time base Unit according to the specified
273   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
274   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
275   *         requires a timer reset to avoid unexpected direction
276   *         due to DIR bit readonly in center aligned mode.
277   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
278   * @param  htim TIM Base handle
279   * @retval HAL status
280   */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
282 {
283   /* Check the TIM handle allocation */
284   if (htim == NULL)
285   {
286     return HAL_ERROR;
287   }
288 
289   /* Check the parameters */
290   assert_param(IS_TIM_INSTANCE(htim->Instance));
291   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
292   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
293   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
294   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
295 
296   if (htim->State == HAL_TIM_STATE_RESET)
297   {
298     /* Allocate lock resource and initialize it */
299     htim->Lock = HAL_UNLOCKED;
300 
301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
302     /* Reset interrupt callbacks to legacy weak callbacks */
303     TIM_ResetCallback(htim);
304 
305     if (htim->Base_MspInitCallback == NULL)
306     {
307       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
308     }
309     /* Init the low level hardware : GPIO, CLOCK, NVIC */
310     htim->Base_MspInitCallback(htim);
311 #else
312     /* Init the low level hardware : GPIO, CLOCK, NVIC */
313     HAL_TIM_Base_MspInit(htim);
314 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
315   }
316 
317   /* Set the TIM state */
318   htim->State = HAL_TIM_STATE_BUSY;
319 
320   /* Set the Time Base configuration */
321   TIM_Base_SetConfig(htim->Instance, &htim->Init);
322 
323   /* Initialize the DMA burst operation state */
324   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
325 
326   /* Initialize the TIM channels state */
327   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
328   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
329 
330   /* Initialize the TIM state*/
331   htim->State = HAL_TIM_STATE_READY;
332 
333   return HAL_OK;
334 }
335 
336 /**
337   * @brief  DeInitializes the TIM Base peripheral
338   * @param  htim TIM Base handle
339   * @retval HAL status
340   */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)341 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
342 {
343   /* Check the parameters */
344   assert_param(IS_TIM_INSTANCE(htim->Instance));
345 
346   htim->State = HAL_TIM_STATE_BUSY;
347 
348   /* Disable the TIM Peripheral Clock */
349   __HAL_TIM_DISABLE(htim);
350 
351 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
352   if (htim->Base_MspDeInitCallback == NULL)
353   {
354     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
355   }
356   /* DeInit the low level hardware */
357   htim->Base_MspDeInitCallback(htim);
358 #else
359   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
360   HAL_TIM_Base_MspDeInit(htim);
361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
362 
363   /* Change the DMA burst operation state */
364   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
365 
366   /* Change the TIM channels state */
367   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
368   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
369 
370   /* Change TIM state */
371   htim->State = HAL_TIM_STATE_RESET;
372 
373   /* Release Lock */
374   __HAL_UNLOCK(htim);
375 
376   return HAL_OK;
377 }
378 
379 /**
380   * @brief  Initializes the TIM Base MSP.
381   * @param  htim TIM Base handle
382   * @retval None
383   */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
385 {
386   /* Prevent unused argument(s) compilation warning */
387   UNUSED(htim);
388 
389   /* NOTE : This function should not be modified, when the callback is needed,
390             the HAL_TIM_Base_MspInit could be implemented in the user file
391    */
392 }
393 
394 /**
395   * @brief  DeInitializes TIM Base MSP.
396   * @param  htim TIM Base handle
397   * @retval None
398   */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)399 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
400 {
401   /* Prevent unused argument(s) compilation warning */
402   UNUSED(htim);
403 
404   /* NOTE : This function should not be modified, when the callback is needed,
405             the HAL_TIM_Base_MspDeInit could be implemented in the user file
406    */
407 }
408 
409 
410 /**
411   * @brief  Starts the TIM Base generation.
412   * @param  htim TIM Base handle
413   * @retval HAL status
414   */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)415 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
416 {
417   uint32_t tmpsmcr;
418 
419   /* Check the parameters */
420   assert_param(IS_TIM_INSTANCE(htim->Instance));
421 
422   /* Check the TIM state */
423   if (htim->State != HAL_TIM_STATE_READY)
424   {
425     return HAL_ERROR;
426   }
427 
428   /* Set the TIM state */
429   htim->State = HAL_TIM_STATE_BUSY;
430 
431   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
432   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
433   {
434     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
435     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
436     {
437       __HAL_TIM_ENABLE(htim);
438     }
439   }
440   else
441   {
442     __HAL_TIM_ENABLE(htim);
443   }
444 
445   /* Return function status */
446   return HAL_OK;
447 }
448 
449 /**
450   * @brief  Stops the TIM Base generation.
451   * @param  htim TIM Base handle
452   * @retval HAL status
453   */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)454 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
455 {
456   /* Check the parameters */
457   assert_param(IS_TIM_INSTANCE(htim->Instance));
458 
459   /* Disable the Peripheral */
460   __HAL_TIM_DISABLE(htim);
461 
462   /* Set the TIM state */
463   htim->State = HAL_TIM_STATE_READY;
464 
465   /* Return function status */
466   return HAL_OK;
467 }
468 
469 /**
470   * @brief  Starts the TIM Base generation in interrupt mode.
471   * @param  htim TIM Base handle
472   * @retval HAL status
473   */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
475 {
476   uint32_t tmpsmcr;
477 
478   /* Check the parameters */
479   assert_param(IS_TIM_INSTANCE(htim->Instance));
480 
481   /* Check the TIM state */
482   if (htim->State != HAL_TIM_STATE_READY)
483   {
484     return HAL_ERROR;
485   }
486 
487   /* Set the TIM state */
488   htim->State = HAL_TIM_STATE_BUSY;
489 
490   /* Enable the TIM Update interrupt */
491   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
492 
493   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
494   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
495   {
496     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
497     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
498     {
499       __HAL_TIM_ENABLE(htim);
500     }
501   }
502   else
503   {
504     __HAL_TIM_ENABLE(htim);
505   }
506 
507   /* Return function status */
508   return HAL_OK;
509 }
510 
511 /**
512   * @brief  Stops the TIM Base generation in interrupt mode.
513   * @param  htim TIM Base handle
514   * @retval HAL status
515   */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)516 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
517 {
518   /* Check the parameters */
519   assert_param(IS_TIM_INSTANCE(htim->Instance));
520 
521   /* Disable the TIM Update interrupt */
522   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
523 
524   /* Disable the Peripheral */
525   __HAL_TIM_DISABLE(htim);
526 
527   /* Set the TIM state */
528   htim->State = HAL_TIM_STATE_READY;
529 
530   /* Return function status */
531   return HAL_OK;
532 }
533 
534 /**
535   * @brief  Starts the TIM Base generation in DMA mode.
536   * @param  htim TIM Base handle
537   * @param  pData The source Buffer address.
538   * @param  Length The length of data to be transferred from memory to peripheral.
539   * @retval HAL status
540   */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
542 {
543   uint32_t tmpsmcr;
544 
545   /* Check the parameters */
546   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
547 
548   /* Set the TIM state */
549   if (htim->State == HAL_TIM_STATE_BUSY)
550   {
551     return HAL_BUSY;
552   }
553   else if (htim->State == HAL_TIM_STATE_READY)
554   {
555     if ((pData == NULL) || (Length == 0U))
556     {
557       return HAL_ERROR;
558     }
559     else
560     {
561       htim->State = HAL_TIM_STATE_BUSY;
562     }
563   }
564   else
565   {
566     return HAL_ERROR;
567   }
568 
569   /* Set the DMA Period elapsed callbacks */
570   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
571   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
572 
573   /* Set the DMA error callback */
574   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
575 
576   /* Enable the DMA channel */
577   if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
578                        Length) != HAL_OK)
579   {
580     /* Return error status */
581     return HAL_ERROR;
582   }
583 
584   /* Enable the TIM Update DMA request */
585   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
586 
587   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
588   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
589   {
590     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
591     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
592     {
593       __HAL_TIM_ENABLE(htim);
594     }
595   }
596   else
597   {
598     __HAL_TIM_ENABLE(htim);
599   }
600 
601   /* Return function status */
602   return HAL_OK;
603 }
604 
605 /**
606   * @brief  Stops the TIM Base generation in DMA mode.
607   * @param  htim TIM Base handle
608   * @retval HAL status
609   */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
611 {
612   /* Check the parameters */
613   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
614 
615   /* Disable the TIM Update DMA request */
616   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
617 
618   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
619 
620   /* Disable the Peripheral */
621   __HAL_TIM_DISABLE(htim);
622 
623   /* Set the TIM state */
624   htim->State = HAL_TIM_STATE_READY;
625 
626   /* Return function status */
627   return HAL_OK;
628 }
629 
630 /**
631   * @}
632   */
633 
634 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
635   *  @brief    TIM Output Compare functions
636   *
637 @verbatim
638   ==============================================================================
639                   ##### TIM Output Compare functions #####
640   ==============================================================================
641   [..]
642     This section provides functions allowing to:
643     (+) Initialize and configure the TIM Output Compare.
644     (+) De-initialize the TIM Output Compare.
645     (+) Start the TIM Output Compare.
646     (+) Stop the TIM Output Compare.
647     (+) Start the TIM Output Compare and enable interrupt.
648     (+) Stop the TIM Output Compare and disable interrupt.
649     (+) Start the TIM Output Compare and enable DMA transfer.
650     (+) Stop the TIM Output Compare and disable DMA transfer.
651 
652 @endverbatim
653   * @{
654   */
655 /**
656   * @brief  Initializes the TIM Output Compare according to the specified
657   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
658   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
659   *         requires a timer reset to avoid unexpected direction
660   *         due to DIR bit readonly in center aligned mode.
661   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
662   * @param  htim TIM Output Compare handle
663   * @retval HAL status
664   */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)665 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
666 {
667   /* Check the TIM handle allocation */
668   if (htim == NULL)
669   {
670     return HAL_ERROR;
671   }
672 
673   /* Check the parameters */
674   assert_param(IS_TIM_INSTANCE(htim->Instance));
675   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
676   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
677   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
678   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
679 
680   if (htim->State == HAL_TIM_STATE_RESET)
681   {
682     /* Allocate lock resource and initialize it */
683     htim->Lock = HAL_UNLOCKED;
684 
685 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
686     /* Reset interrupt callbacks to legacy weak callbacks */
687     TIM_ResetCallback(htim);
688 
689     if (htim->OC_MspInitCallback == NULL)
690     {
691       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
692     }
693     /* Init the low level hardware : GPIO, CLOCK, NVIC */
694     htim->OC_MspInitCallback(htim);
695 #else
696     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
697     HAL_TIM_OC_MspInit(htim);
698 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
699   }
700 
701   /* Set the TIM state */
702   htim->State = HAL_TIM_STATE_BUSY;
703 
704   /* Init the base time for the Output Compare */
705   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
706 
707   /* Initialize the DMA burst operation state */
708   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
709 
710   /* Initialize the TIM channels state */
711   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
712   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
713 
714   /* Initialize the TIM state*/
715   htim->State = HAL_TIM_STATE_READY;
716 
717   return HAL_OK;
718 }
719 
720 /**
721   * @brief  DeInitializes the TIM peripheral
722   * @param  htim TIM Output Compare handle
723   * @retval HAL status
724   */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)725 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
726 {
727   /* Check the parameters */
728   assert_param(IS_TIM_INSTANCE(htim->Instance));
729 
730   htim->State = HAL_TIM_STATE_BUSY;
731 
732   /* Disable the TIM Peripheral Clock */
733   __HAL_TIM_DISABLE(htim);
734 
735 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
736   if (htim->OC_MspDeInitCallback == NULL)
737   {
738     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
739   }
740   /* DeInit the low level hardware */
741   htim->OC_MspDeInitCallback(htim);
742 #else
743   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
744   HAL_TIM_OC_MspDeInit(htim);
745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
746 
747   /* Change the DMA burst operation state */
748   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
749 
750   /* Change the TIM channels state */
751   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
752   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
753 
754   /* Change TIM state */
755   htim->State = HAL_TIM_STATE_RESET;
756 
757   /* Release Lock */
758   __HAL_UNLOCK(htim);
759 
760   return HAL_OK;
761 }
762 
763 /**
764   * @brief  Initializes the TIM Output Compare MSP.
765   * @param  htim TIM Output Compare handle
766   * @retval None
767   */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
769 {
770   /* Prevent unused argument(s) compilation warning */
771   UNUSED(htim);
772 
773   /* NOTE : This function should not be modified, when the callback is needed,
774             the HAL_TIM_OC_MspInit could be implemented in the user file
775    */
776 }
777 
778 /**
779   * @brief  DeInitializes TIM Output Compare MSP.
780   * @param  htim TIM Output Compare handle
781   * @retval None
782   */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)783 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
784 {
785   /* Prevent unused argument(s) compilation warning */
786   UNUSED(htim);
787 
788   /* NOTE : This function should not be modified, when the callback is needed,
789             the HAL_TIM_OC_MspDeInit could be implemented in the user file
790    */
791 }
792 
793 /**
794   * @brief  Starts the TIM Output Compare signal generation.
795   * @param  htim TIM Output Compare handle
796   * @param  Channel TIM Channel to be enabled
797   *          This parameter can be one of the following values:
798   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
799   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
800   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
801   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
802   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
803   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
804   * @retval HAL status
805   */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)806 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
807 {
808   uint32_t tmpsmcr;
809 
810   /* Check the parameters */
811   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
812 
813   /* Check the TIM channel state */
814   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
815   {
816     return HAL_ERROR;
817   }
818 
819   /* Set the TIM channel state */
820   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
821 
822   /* Enable the Output compare channel */
823   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
824 
825   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
826   {
827     /* Enable the main output */
828     __HAL_TIM_MOE_ENABLE(htim);
829   }
830 
831   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
832   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
833   {
834     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
835     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
836     {
837       __HAL_TIM_ENABLE(htim);
838     }
839   }
840   else
841   {
842     __HAL_TIM_ENABLE(htim);
843   }
844 
845   /* Return function status */
846   return HAL_OK;
847 }
848 
849 /**
850   * @brief  Stops the TIM Output Compare signal generation.
851   * @param  htim TIM Output Compare handle
852   * @param  Channel TIM Channel to be disabled
853   *          This parameter can be one of the following values:
854   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
855   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
856   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
857   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
858   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
859   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
860   * @retval HAL status
861   */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)862 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
863 {
864   /* Check the parameters */
865   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
866 
867   /* Disable the Output compare channel */
868   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
869 
870   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
871   {
872     /* Disable the Main Output */
873     __HAL_TIM_MOE_DISABLE(htim);
874   }
875 
876   /* Disable the Peripheral */
877   __HAL_TIM_DISABLE(htim);
878 
879   /* Set the TIM channel state */
880   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
881 
882   /* Return function status */
883   return HAL_OK;
884 }
885 
886 /**
887   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
888   * @param  htim TIM Output Compare handle
889   * @param  Channel TIM Channel to be enabled
890   *          This parameter can be one of the following values:
891   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
892   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
893   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
894   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
895   * @retval HAL status
896   */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)897 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
898 {
899   HAL_StatusTypeDef status = HAL_OK;
900   uint32_t tmpsmcr;
901 
902   /* Check the parameters */
903   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
904 
905   /* Check the TIM channel state */
906   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
907   {
908     return HAL_ERROR;
909   }
910 
911   /* Set the TIM channel state */
912   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
913 
914   switch (Channel)
915   {
916     case TIM_CHANNEL_1:
917     {
918       /* Enable the TIM Capture/Compare 1 interrupt */
919       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
920       break;
921     }
922 
923     case TIM_CHANNEL_2:
924     {
925       /* Enable the TIM Capture/Compare 2 interrupt */
926       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
927       break;
928     }
929 
930     case TIM_CHANNEL_3:
931     {
932       /* Enable the TIM Capture/Compare 3 interrupt */
933       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
934       break;
935     }
936 
937     case TIM_CHANNEL_4:
938     {
939       /* Enable the TIM Capture/Compare 4 interrupt */
940       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
941       break;
942     }
943 
944     default:
945       status = HAL_ERROR;
946       break;
947   }
948 
949   if (status == HAL_OK)
950   {
951     /* Enable the Output compare channel */
952     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
953 
954     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
955     {
956       /* Enable the main output */
957       __HAL_TIM_MOE_ENABLE(htim);
958     }
959 
960     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
961     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
962     {
963       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
964       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
965       {
966         __HAL_TIM_ENABLE(htim);
967       }
968     }
969     else
970     {
971       __HAL_TIM_ENABLE(htim);
972     }
973   }
974 
975   /* Return function status */
976   return status;
977 }
978 
979 /**
980   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
981   * @param  htim TIM Output Compare handle
982   * @param  Channel TIM Channel to be disabled
983   *          This parameter can be one of the following values:
984   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
985   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
986   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
987   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
988   * @retval HAL status
989   */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)990 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
991 {
992   HAL_StatusTypeDef status = HAL_OK;
993 
994   /* Check the parameters */
995   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
996 
997   switch (Channel)
998   {
999     case TIM_CHANNEL_1:
1000     {
1001       /* Disable the TIM Capture/Compare 1 interrupt */
1002       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1003       break;
1004     }
1005 
1006     case TIM_CHANNEL_2:
1007     {
1008       /* Disable the TIM Capture/Compare 2 interrupt */
1009       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1010       break;
1011     }
1012 
1013     case TIM_CHANNEL_3:
1014     {
1015       /* Disable the TIM Capture/Compare 3 interrupt */
1016       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1017       break;
1018     }
1019 
1020     case TIM_CHANNEL_4:
1021     {
1022       /* Disable the TIM Capture/Compare 4 interrupt */
1023       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1024       break;
1025     }
1026 
1027     default:
1028       status = HAL_ERROR;
1029       break;
1030   }
1031 
1032   if (status == HAL_OK)
1033   {
1034     /* Disable the Output compare channel */
1035     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1036 
1037     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1038     {
1039       /* Disable the Main Output */
1040       __HAL_TIM_MOE_DISABLE(htim);
1041     }
1042 
1043     /* Disable the Peripheral */
1044     __HAL_TIM_DISABLE(htim);
1045 
1046     /* Set the TIM channel state */
1047     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1048   }
1049 
1050   /* Return function status */
1051   return status;
1052 }
1053 
1054 /**
1055   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
1056   * @param  htim TIM Output Compare handle
1057   * @param  Channel TIM Channel to be enabled
1058   *          This parameter can be one of the following values:
1059   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1060   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1061   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1062   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1063   * @param  pData The source Buffer address.
1064   * @param  Length The length of data to be transferred from memory to TIM peripheral
1065   * @retval HAL status
1066   */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1067 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1068                                        uint16_t Length)
1069 {
1070   HAL_StatusTypeDef status = HAL_OK;
1071   uint32_t tmpsmcr;
1072 
1073   /* Check the parameters */
1074   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1075 
1076   /* Set the TIM channel state */
1077   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1078   {
1079     return HAL_BUSY;
1080   }
1081   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1082   {
1083     if ((pData == NULL) || (Length == 0U))
1084     {
1085       return HAL_ERROR;
1086     }
1087     else
1088     {
1089       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1090     }
1091   }
1092   else
1093   {
1094     return HAL_ERROR;
1095   }
1096 
1097   switch (Channel)
1098   {
1099     case TIM_CHANNEL_1:
1100     {
1101       /* Set the DMA compare callbacks */
1102       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1103       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1104 
1105       /* Set the DMA error callback */
1106       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1107 
1108       /* Enable the DMA channel */
1109       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1110                            Length) != HAL_OK)
1111       {
1112         /* Return error status */
1113         return HAL_ERROR;
1114       }
1115 
1116       /* Enable the TIM Capture/Compare 1 DMA request */
1117       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1118       break;
1119     }
1120 
1121     case TIM_CHANNEL_2:
1122     {
1123       /* Set the DMA compare callbacks */
1124       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1125       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1126 
1127       /* Set the DMA error callback */
1128       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1129 
1130       /* Enable the DMA channel */
1131       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1132                            Length) != HAL_OK)
1133       {
1134         /* Return error status */
1135         return HAL_ERROR;
1136       }
1137 
1138       /* Enable the TIM Capture/Compare 2 DMA request */
1139       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1140       break;
1141     }
1142 
1143     case TIM_CHANNEL_3:
1144     {
1145       /* Set the DMA compare callbacks */
1146       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1147       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1148 
1149       /* Set the DMA error callback */
1150       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1151 
1152       /* Enable the DMA channel */
1153       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1154                            Length) != HAL_OK)
1155       {
1156         /* Return error status */
1157         return HAL_ERROR;
1158       }
1159       /* Enable the TIM Capture/Compare 3 DMA request */
1160       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1161       break;
1162     }
1163 
1164     case TIM_CHANNEL_4:
1165     {
1166       /* Set the DMA compare callbacks */
1167       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1168       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1169 
1170       /* Set the DMA error callback */
1171       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1172 
1173       /* Enable the DMA channel */
1174       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1175                            Length) != HAL_OK)
1176       {
1177         /* Return error status */
1178         return HAL_ERROR;
1179       }
1180       /* Enable the TIM Capture/Compare 4 DMA request */
1181       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1182       break;
1183     }
1184 
1185     default:
1186       status = HAL_ERROR;
1187       break;
1188   }
1189 
1190   if (status == HAL_OK)
1191   {
1192     /* Enable the Output compare channel */
1193     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1194 
1195     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1196     {
1197       /* Enable the main output */
1198       __HAL_TIM_MOE_ENABLE(htim);
1199     }
1200 
1201     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1202     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1203     {
1204       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1205       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1206       {
1207         __HAL_TIM_ENABLE(htim);
1208       }
1209     }
1210     else
1211     {
1212       __HAL_TIM_ENABLE(htim);
1213     }
1214   }
1215 
1216   /* Return function status */
1217   return status;
1218 }
1219 
1220 /**
1221   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
1222   * @param  htim TIM Output Compare handle
1223   * @param  Channel TIM Channel to be disabled
1224   *          This parameter can be one of the following values:
1225   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1226   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1227   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1228   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1229   * @retval HAL status
1230   */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1231 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1232 {
1233   HAL_StatusTypeDef status = HAL_OK;
1234 
1235   /* Check the parameters */
1236   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1237 
1238   switch (Channel)
1239   {
1240     case TIM_CHANNEL_1:
1241     {
1242       /* Disable the TIM Capture/Compare 1 DMA request */
1243       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1244       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1245       break;
1246     }
1247 
1248     case TIM_CHANNEL_2:
1249     {
1250       /* Disable the TIM Capture/Compare 2 DMA request */
1251       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1252       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1253       break;
1254     }
1255 
1256     case TIM_CHANNEL_3:
1257     {
1258       /* Disable the TIM Capture/Compare 3 DMA request */
1259       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1260       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1261       break;
1262     }
1263 
1264     case TIM_CHANNEL_4:
1265     {
1266       /* Disable the TIM Capture/Compare 4 interrupt */
1267       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1268       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1269       break;
1270     }
1271 
1272     default:
1273       status = HAL_ERROR;
1274       break;
1275   }
1276 
1277   if (status == HAL_OK)
1278   {
1279     /* Disable the Output compare channel */
1280     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1281 
1282     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1283     {
1284       /* Disable the Main Output */
1285       __HAL_TIM_MOE_DISABLE(htim);
1286     }
1287 
1288     /* Disable the Peripheral */
1289     __HAL_TIM_DISABLE(htim);
1290 
1291     /* Set the TIM channel state */
1292     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1293   }
1294 
1295   /* Return function status */
1296   return status;
1297 }
1298 
1299 /**
1300   * @}
1301   */
1302 
1303 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1304   *  @brief    TIM PWM functions
1305   *
1306 @verbatim
1307   ==============================================================================
1308                           ##### TIM PWM functions #####
1309   ==============================================================================
1310   [..]
1311     This section provides functions allowing to:
1312     (+) Initialize and configure the TIM PWM.
1313     (+) De-initialize the TIM PWM.
1314     (+) Start the TIM PWM.
1315     (+) Stop the TIM PWM.
1316     (+) Start the TIM PWM and enable interrupt.
1317     (+) Stop the TIM PWM and disable interrupt.
1318     (+) Start the TIM PWM and enable DMA transfer.
1319     (+) Stop the TIM PWM and disable DMA transfer.
1320 
1321 @endverbatim
1322   * @{
1323   */
1324 /**
1325   * @brief  Initializes the TIM PWM Time Base according to the specified
1326   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
1327   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1328   *         requires a timer reset to avoid unexpected direction
1329   *         due to DIR bit readonly in center aligned mode.
1330   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1331   * @param  htim TIM PWM handle
1332   * @retval HAL status
1333   */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1334 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1335 {
1336   /* Check the TIM handle allocation */
1337   if (htim == NULL)
1338   {
1339     return HAL_ERROR;
1340   }
1341 
1342   /* Check the parameters */
1343   assert_param(IS_TIM_INSTANCE(htim->Instance));
1344   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1345   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1346   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1347   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1348 
1349   if (htim->State == HAL_TIM_STATE_RESET)
1350   {
1351     /* Allocate lock resource and initialize it */
1352     htim->Lock = HAL_UNLOCKED;
1353 
1354 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1355     /* Reset interrupt callbacks to legacy weak callbacks */
1356     TIM_ResetCallback(htim);
1357 
1358     if (htim->PWM_MspInitCallback == NULL)
1359     {
1360       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1361     }
1362     /* Init the low level hardware : GPIO, CLOCK, NVIC */
1363     htim->PWM_MspInitCallback(htim);
1364 #else
1365     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1366     HAL_TIM_PWM_MspInit(htim);
1367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1368   }
1369 
1370   /* Set the TIM state */
1371   htim->State = HAL_TIM_STATE_BUSY;
1372 
1373   /* Init the base time for the PWM */
1374   TIM_Base_SetConfig(htim->Instance, &htim->Init);
1375 
1376   /* Initialize the DMA burst operation state */
1377   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1378 
1379   /* Initialize the TIM channels state */
1380   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1381   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1382 
1383   /* Initialize the TIM state*/
1384   htim->State = HAL_TIM_STATE_READY;
1385 
1386   return HAL_OK;
1387 }
1388 
1389 /**
1390   * @brief  DeInitializes the TIM peripheral
1391   * @param  htim TIM PWM handle
1392   * @retval HAL status
1393   */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1394 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1395 {
1396   /* Check the parameters */
1397   assert_param(IS_TIM_INSTANCE(htim->Instance));
1398 
1399   htim->State = HAL_TIM_STATE_BUSY;
1400 
1401   /* Disable the TIM Peripheral Clock */
1402   __HAL_TIM_DISABLE(htim);
1403 
1404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1405   if (htim->PWM_MspDeInitCallback == NULL)
1406   {
1407     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1408   }
1409   /* DeInit the low level hardware */
1410   htim->PWM_MspDeInitCallback(htim);
1411 #else
1412   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1413   HAL_TIM_PWM_MspDeInit(htim);
1414 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1415 
1416   /* Change the DMA burst operation state */
1417   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1418 
1419   /* Change the TIM channels state */
1420   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1421   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1422 
1423   /* Change TIM state */
1424   htim->State = HAL_TIM_STATE_RESET;
1425 
1426   /* Release Lock */
1427   __HAL_UNLOCK(htim);
1428 
1429   return HAL_OK;
1430 }
1431 
1432 /**
1433   * @brief  Initializes the TIM PWM MSP.
1434   * @param  htim TIM PWM handle
1435   * @retval None
1436   */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1437 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1438 {
1439   /* Prevent unused argument(s) compilation warning */
1440   UNUSED(htim);
1441 
1442   /* NOTE : This function should not be modified, when the callback is needed,
1443             the HAL_TIM_PWM_MspInit could be implemented in the user file
1444    */
1445 }
1446 
1447 /**
1448   * @brief  DeInitializes TIM PWM MSP.
1449   * @param  htim TIM PWM handle
1450   * @retval None
1451   */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1452 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1453 {
1454   /* Prevent unused argument(s) compilation warning */
1455   UNUSED(htim);
1456 
1457   /* NOTE : This function should not be modified, when the callback is needed,
1458             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1459    */
1460 }
1461 
1462 /**
1463   * @brief  Starts the PWM signal generation.
1464   * @param  htim TIM handle
1465   * @param  Channel TIM Channels to be enabled
1466   *          This parameter can be one of the following values:
1467   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1468   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1469   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1470   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1471   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1472   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1473   * @retval HAL status
1474   */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1475 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1476 {
1477   uint32_t tmpsmcr;
1478 
1479   /* Check the parameters */
1480   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1481 
1482   /* Check the TIM channel state */
1483   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1484   {
1485     return HAL_ERROR;
1486   }
1487 
1488   /* Set the TIM channel state */
1489   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1490 
1491   /* Enable the Capture compare channel */
1492   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1493 
1494   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1495   {
1496     /* Enable the main output */
1497     __HAL_TIM_MOE_ENABLE(htim);
1498   }
1499 
1500   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1501   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1502   {
1503     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1504     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1505     {
1506       __HAL_TIM_ENABLE(htim);
1507     }
1508   }
1509   else
1510   {
1511     __HAL_TIM_ENABLE(htim);
1512   }
1513 
1514   /* Return function status */
1515   return HAL_OK;
1516 }
1517 
1518 /**
1519   * @brief  Stops the PWM signal generation.
1520   * @param  htim TIM PWM handle
1521   * @param  Channel TIM Channels to be disabled
1522   *          This parameter can be one of the following values:
1523   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1524   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1525   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1526   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1527   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1528   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1529   * @retval HAL status
1530   */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1531 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1532 {
1533   /* Check the parameters */
1534   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1535 
1536   /* Disable the Capture compare channel */
1537   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1538 
1539   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1540   {
1541     /* Disable the Main Output */
1542     __HAL_TIM_MOE_DISABLE(htim);
1543   }
1544 
1545   /* Disable the Peripheral */
1546   __HAL_TIM_DISABLE(htim);
1547 
1548   /* Set the TIM channel state */
1549   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1550 
1551   /* Return function status */
1552   return HAL_OK;
1553 }
1554 
1555 /**
1556   * @brief  Starts the PWM signal generation in interrupt mode.
1557   * @param  htim TIM PWM handle
1558   * @param  Channel TIM Channel to be enabled
1559   *          This parameter can be one of the following values:
1560   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1561   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1562   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1563   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1564   * @retval HAL status
1565   */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1566 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1567 {
1568   HAL_StatusTypeDef status = HAL_OK;
1569   uint32_t tmpsmcr;
1570 
1571   /* Check the parameters */
1572   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1573 
1574   /* Check the TIM channel state */
1575   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1576   {
1577     return HAL_ERROR;
1578   }
1579 
1580   /* Set the TIM channel state */
1581   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1582 
1583   switch (Channel)
1584   {
1585     case TIM_CHANNEL_1:
1586     {
1587       /* Enable the TIM Capture/Compare 1 interrupt */
1588       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1589       break;
1590     }
1591 
1592     case TIM_CHANNEL_2:
1593     {
1594       /* Enable the TIM Capture/Compare 2 interrupt */
1595       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1596       break;
1597     }
1598 
1599     case TIM_CHANNEL_3:
1600     {
1601       /* Enable the TIM Capture/Compare 3 interrupt */
1602       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1603       break;
1604     }
1605 
1606     case TIM_CHANNEL_4:
1607     {
1608       /* Enable the TIM Capture/Compare 4 interrupt */
1609       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1610       break;
1611     }
1612 
1613     default:
1614       status = HAL_ERROR;
1615       break;
1616   }
1617 
1618   if (status == HAL_OK)
1619   {
1620     /* Enable the Capture compare channel */
1621     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1622 
1623     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1624     {
1625       /* Enable the main output */
1626       __HAL_TIM_MOE_ENABLE(htim);
1627     }
1628 
1629     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1630     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1631     {
1632       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1633       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1634       {
1635         __HAL_TIM_ENABLE(htim);
1636       }
1637     }
1638     else
1639     {
1640       __HAL_TIM_ENABLE(htim);
1641     }
1642   }
1643 
1644   /* Return function status */
1645   return status;
1646 }
1647 
1648 /**
1649   * @brief  Stops the PWM signal generation in interrupt mode.
1650   * @param  htim TIM PWM handle
1651   * @param  Channel TIM Channels to be disabled
1652   *          This parameter can be one of the following values:
1653   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1654   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1655   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1656   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1657   * @retval HAL status
1658   */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1659 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1660 {
1661   HAL_StatusTypeDef status = HAL_OK;
1662 
1663   /* Check the parameters */
1664   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1665 
1666   switch (Channel)
1667   {
1668     case TIM_CHANNEL_1:
1669     {
1670       /* Disable the TIM Capture/Compare 1 interrupt */
1671       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1672       break;
1673     }
1674 
1675     case TIM_CHANNEL_2:
1676     {
1677       /* Disable the TIM Capture/Compare 2 interrupt */
1678       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1679       break;
1680     }
1681 
1682     case TIM_CHANNEL_3:
1683     {
1684       /* Disable the TIM Capture/Compare 3 interrupt */
1685       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1686       break;
1687     }
1688 
1689     case TIM_CHANNEL_4:
1690     {
1691       /* Disable the TIM Capture/Compare 4 interrupt */
1692       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1693       break;
1694     }
1695 
1696     default:
1697       status = HAL_ERROR;
1698       break;
1699   }
1700 
1701   if (status == HAL_OK)
1702   {
1703     /* Disable the Capture compare channel */
1704     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1705 
1706     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1707     {
1708       /* Disable the Main Output */
1709       __HAL_TIM_MOE_DISABLE(htim);
1710     }
1711 
1712     /* Disable the Peripheral */
1713     __HAL_TIM_DISABLE(htim);
1714 
1715     /* Set the TIM channel state */
1716     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1717   }
1718 
1719   /* Return function status */
1720   return status;
1721 }
1722 
1723 /**
1724   * @brief  Starts the TIM PWM signal generation in DMA mode.
1725   * @param  htim TIM PWM handle
1726   * @param  Channel TIM Channels to be enabled
1727   *          This parameter can be one of the following values:
1728   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1729   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1730   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1731   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1732   * @param  pData The source Buffer address.
1733   * @param  Length The length of data to be transferred from memory to TIM peripheral
1734   * @retval HAL status
1735   */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1736 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1737                                         uint16_t Length)
1738 {
1739   HAL_StatusTypeDef status = HAL_OK;
1740   uint32_t tmpsmcr;
1741 
1742   /* Check the parameters */
1743   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1744 
1745   /* Set the TIM channel state */
1746   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1747   {
1748     return HAL_BUSY;
1749   }
1750   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1751   {
1752     if ((pData == NULL) || (Length == 0U))
1753     {
1754       return HAL_ERROR;
1755     }
1756     else
1757     {
1758       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1759     }
1760   }
1761   else
1762   {
1763     return HAL_ERROR;
1764   }
1765 
1766   switch (Channel)
1767   {
1768     case TIM_CHANNEL_1:
1769     {
1770       /* Set the DMA compare callbacks */
1771       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1772       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1773 
1774       /* Set the DMA error callback */
1775       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1776 
1777       /* Enable the DMA channel */
1778       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1779                            Length) != HAL_OK)
1780       {
1781         /* Return error status */
1782         return HAL_ERROR;
1783       }
1784 
1785       /* Enable the TIM Capture/Compare 1 DMA request */
1786       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1787       break;
1788     }
1789 
1790     case TIM_CHANNEL_2:
1791     {
1792       /* Set the DMA compare callbacks */
1793       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1794       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1795 
1796       /* Set the DMA error callback */
1797       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1798 
1799       /* Enable the DMA channel */
1800       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1801                            Length) != HAL_OK)
1802       {
1803         /* Return error status */
1804         return HAL_ERROR;
1805       }
1806       /* Enable the TIM Capture/Compare 2 DMA request */
1807       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1808       break;
1809     }
1810 
1811     case TIM_CHANNEL_3:
1812     {
1813       /* Set the DMA compare callbacks */
1814       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1815       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1816 
1817       /* Set the DMA error callback */
1818       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1819 
1820       /* Enable the DMA channel */
1821       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1822                            Length) != HAL_OK)
1823       {
1824         /* Return error status */
1825         return HAL_ERROR;
1826       }
1827       /* Enable the TIM Output Capture/Compare 3 request */
1828       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1829       break;
1830     }
1831 
1832     case TIM_CHANNEL_4:
1833     {
1834       /* Set the DMA compare callbacks */
1835       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1836       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1837 
1838       /* Set the DMA error callback */
1839       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1840 
1841       /* Enable the DMA channel */
1842       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1843                            Length) != HAL_OK)
1844       {
1845         /* Return error status */
1846         return HAL_ERROR;
1847       }
1848       /* Enable the TIM Capture/Compare 4 DMA request */
1849       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1850       break;
1851     }
1852 
1853     default:
1854       status = HAL_ERROR;
1855       break;
1856   }
1857 
1858   if (status == HAL_OK)
1859   {
1860     /* Enable the Capture compare channel */
1861     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1862 
1863     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1864     {
1865       /* Enable the main output */
1866       __HAL_TIM_MOE_ENABLE(htim);
1867     }
1868 
1869     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1870     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1871     {
1872       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1873       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1874       {
1875         __HAL_TIM_ENABLE(htim);
1876       }
1877     }
1878     else
1879     {
1880       __HAL_TIM_ENABLE(htim);
1881     }
1882   }
1883 
1884   /* Return function status */
1885   return status;
1886 }
1887 
1888 /**
1889   * @brief  Stops the TIM PWM signal generation in DMA mode.
1890   * @param  htim TIM PWM handle
1891   * @param  Channel TIM Channels to be disabled
1892   *          This parameter can be one of the following values:
1893   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1894   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1895   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1896   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1897   * @retval HAL status
1898   */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1899 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1900 {
1901   HAL_StatusTypeDef status = HAL_OK;
1902 
1903   /* Check the parameters */
1904   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1905 
1906   switch (Channel)
1907   {
1908     case TIM_CHANNEL_1:
1909     {
1910       /* Disable the TIM Capture/Compare 1 DMA request */
1911       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1912       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1913       break;
1914     }
1915 
1916     case TIM_CHANNEL_2:
1917     {
1918       /* Disable the TIM Capture/Compare 2 DMA request */
1919       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1920       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1921       break;
1922     }
1923 
1924     case TIM_CHANNEL_3:
1925     {
1926       /* Disable the TIM Capture/Compare 3 DMA request */
1927       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1928       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1929       break;
1930     }
1931 
1932     case TIM_CHANNEL_4:
1933     {
1934       /* Disable the TIM Capture/Compare 4 interrupt */
1935       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1936       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1937       break;
1938     }
1939 
1940     default:
1941       status = HAL_ERROR;
1942       break;
1943   }
1944 
1945   if (status == HAL_OK)
1946   {
1947     /* Disable the Capture compare channel */
1948     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1949 
1950     if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1951     {
1952       /* Disable the Main Output */
1953       __HAL_TIM_MOE_DISABLE(htim);
1954     }
1955 
1956     /* Disable the Peripheral */
1957     __HAL_TIM_DISABLE(htim);
1958 
1959     /* Set the TIM channel state */
1960     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1961   }
1962 
1963   /* Return function status */
1964   return status;
1965 }
1966 
1967 /**
1968   * @}
1969   */
1970 
1971 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1972   *  @brief    TIM Input Capture functions
1973   *
1974 @verbatim
1975   ==============================================================================
1976               ##### TIM Input Capture functions #####
1977   ==============================================================================
1978  [..]
1979    This section provides functions allowing to:
1980    (+) Initialize and configure the TIM Input Capture.
1981    (+) De-initialize the TIM Input Capture.
1982    (+) Start the TIM Input Capture.
1983    (+) Stop the TIM Input Capture.
1984    (+) Start the TIM Input Capture and enable interrupt.
1985    (+) Stop the TIM Input Capture and disable interrupt.
1986    (+) Start the TIM Input Capture and enable DMA transfer.
1987    (+) Stop the TIM Input Capture and disable DMA transfer.
1988 
1989 @endverbatim
1990   * @{
1991   */
1992 /**
1993   * @brief  Initializes the TIM Input Capture Time base according to the specified
1994   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
1995   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1996   *         requires a timer reset to avoid unexpected direction
1997   *         due to DIR bit readonly in center aligned mode.
1998   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1999   * @param  htim TIM Input Capture handle
2000   * @retval HAL status
2001   */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)2002 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
2003 {
2004   /* Check the TIM handle allocation */
2005   if (htim == NULL)
2006   {
2007     return HAL_ERROR;
2008   }
2009 
2010   /* Check the parameters */
2011   assert_param(IS_TIM_INSTANCE(htim->Instance));
2012   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2013   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2014   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2015   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2016 
2017   if (htim->State == HAL_TIM_STATE_RESET)
2018   {
2019     /* Allocate lock resource and initialize it */
2020     htim->Lock = HAL_UNLOCKED;
2021 
2022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2023     /* Reset interrupt callbacks to legacy weak callbacks */
2024     TIM_ResetCallback(htim);
2025 
2026     if (htim->IC_MspInitCallback == NULL)
2027     {
2028       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2029     }
2030     /* Init the low level hardware : GPIO, CLOCK, NVIC */
2031     htim->IC_MspInitCallback(htim);
2032 #else
2033     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2034     HAL_TIM_IC_MspInit(htim);
2035 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2036   }
2037 
2038   /* Set the TIM state */
2039   htim->State = HAL_TIM_STATE_BUSY;
2040 
2041   /* Init the base time for the input capture */
2042   TIM_Base_SetConfig(htim->Instance, &htim->Init);
2043 
2044   /* Initialize the DMA burst operation state */
2045   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2046 
2047   /* Initialize the TIM channels state */
2048   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2049   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2050 
2051   /* Initialize the TIM state*/
2052   htim->State = HAL_TIM_STATE_READY;
2053 
2054   return HAL_OK;
2055 }
2056 
2057 /**
2058   * @brief  DeInitializes the TIM peripheral
2059   * @param  htim TIM Input Capture handle
2060   * @retval HAL status
2061   */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2062 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2063 {
2064   /* Check the parameters */
2065   assert_param(IS_TIM_INSTANCE(htim->Instance));
2066 
2067   htim->State = HAL_TIM_STATE_BUSY;
2068 
2069   /* Disable the TIM Peripheral Clock */
2070   __HAL_TIM_DISABLE(htim);
2071 
2072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2073   if (htim->IC_MspDeInitCallback == NULL)
2074   {
2075     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2076   }
2077   /* DeInit the low level hardware */
2078   htim->IC_MspDeInitCallback(htim);
2079 #else
2080   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2081   HAL_TIM_IC_MspDeInit(htim);
2082 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2083 
2084   /* Change the DMA burst operation state */
2085   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2086 
2087   /* Change the TIM channels state */
2088   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2089   TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2090 
2091   /* Change TIM state */
2092   htim->State = HAL_TIM_STATE_RESET;
2093 
2094   /* Release Lock */
2095   __HAL_UNLOCK(htim);
2096 
2097   return HAL_OK;
2098 }
2099 
2100 /**
2101   * @brief  Initializes the TIM Input Capture MSP.
2102   * @param  htim TIM Input Capture handle
2103   * @retval None
2104   */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2105 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2106 {
2107   /* Prevent unused argument(s) compilation warning */
2108   UNUSED(htim);
2109 
2110   /* NOTE : This function should not be modified, when the callback is needed,
2111             the HAL_TIM_IC_MspInit could be implemented in the user file
2112    */
2113 }
2114 
2115 /**
2116   * @brief  DeInitializes TIM Input Capture MSP.
2117   * @param  htim TIM handle
2118   * @retval None
2119   */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2120 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2121 {
2122   /* Prevent unused argument(s) compilation warning */
2123   UNUSED(htim);
2124 
2125   /* NOTE : This function should not be modified, when the callback is needed,
2126             the HAL_TIM_IC_MspDeInit could be implemented in the user file
2127    */
2128 }
2129 
2130 /**
2131   * @brief  Starts the TIM Input Capture measurement.
2132   * @param  htim TIM Input Capture handle
2133   * @param  Channel TIM Channels to be enabled
2134   *          This parameter can be one of the following values:
2135   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2136   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2137   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2138   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2139   * @retval HAL status
2140   */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2141 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2142 {
2143   uint32_t tmpsmcr;
2144   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2145   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2146 
2147   /* Check the parameters */
2148   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2149 
2150   /* Check the TIM channel state */
2151   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2152       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2153   {
2154     return HAL_ERROR;
2155   }
2156 
2157   /* Set the TIM channel state */
2158   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2159   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2160 
2161   /* Enable the Input Capture channel */
2162   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2163 
2164   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2165   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2166   {
2167     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2168     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2169     {
2170       __HAL_TIM_ENABLE(htim);
2171     }
2172   }
2173   else
2174   {
2175     __HAL_TIM_ENABLE(htim);
2176   }
2177 
2178   /* Return function status */
2179   return HAL_OK;
2180 }
2181 
2182 /**
2183   * @brief  Stops the TIM Input Capture measurement.
2184   * @param  htim TIM Input Capture handle
2185   * @param  Channel TIM Channels to be disabled
2186   *          This parameter can be one of the following values:
2187   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2188   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2189   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2190   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2191   * @retval HAL status
2192   */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2193 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2194 {
2195   /* Check the parameters */
2196   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2197 
2198   /* Disable the Input Capture channel */
2199   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2200 
2201   /* Disable the Peripheral */
2202   __HAL_TIM_DISABLE(htim);
2203 
2204   /* Set the TIM channel state */
2205   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2206   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2207 
2208   /* Return function status */
2209   return HAL_OK;
2210 }
2211 
2212 /**
2213   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
2214   * @param  htim TIM Input Capture handle
2215   * @param  Channel TIM Channels to be enabled
2216   *          This parameter can be one of the following values:
2217   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2218   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2219   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2220   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2221   * @retval HAL status
2222   */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2223 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2224 {
2225   HAL_StatusTypeDef status = HAL_OK;
2226   uint32_t tmpsmcr;
2227 
2228   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2229   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2230 
2231   /* Check the parameters */
2232   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2233 
2234   /* Check the TIM channel state */
2235   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2236       || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2237   {
2238     return HAL_ERROR;
2239   }
2240 
2241   /* Set the TIM channel state */
2242   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2243   TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2244 
2245   switch (Channel)
2246   {
2247     case TIM_CHANNEL_1:
2248     {
2249       /* Enable the TIM Capture/Compare 1 interrupt */
2250       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2251       break;
2252     }
2253 
2254     case TIM_CHANNEL_2:
2255     {
2256       /* Enable the TIM Capture/Compare 2 interrupt */
2257       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2258       break;
2259     }
2260 
2261     case TIM_CHANNEL_3:
2262     {
2263       /* Enable the TIM Capture/Compare 3 interrupt */
2264       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2265       break;
2266     }
2267 
2268     case TIM_CHANNEL_4:
2269     {
2270       /* Enable the TIM Capture/Compare 4 interrupt */
2271       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2272       break;
2273     }
2274 
2275     default:
2276       status = HAL_ERROR;
2277       break;
2278   }
2279 
2280   if (status == HAL_OK)
2281   {
2282     /* Enable the Input Capture channel */
2283     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2284 
2285     /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2286     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2287     {
2288       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2289       if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2290       {
2291         __HAL_TIM_ENABLE(htim);
2292       }
2293     }
2294     else
2295     {
2296       __HAL_TIM_ENABLE(htim);
2297     }
2298   }
2299 
2300   /* Return function status */
2301   return status;
2302 }
2303 
2304 /**
2305   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
2306   * @param  htim TIM Input Capture handle
2307   * @param  Channel TIM Channels to be disabled
2308   *          This parameter can be one of the following values:
2309   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2310   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2311   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2312   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2313   * @retval HAL status
2314   */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2315 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2316 {
2317   HAL_StatusTypeDef status = HAL_OK;
2318 
2319   /* Check the parameters */
2320   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2321 
2322   switch (Channel)
2323   {
2324     case TIM_CHANNEL_1:
2325     {
2326       /* Disable the TIM Capture/Compare 1 interrupt */
2327       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2328       break;
2329     }
2330 
2331     case TIM_CHANNEL_2:
2332     {
2333       /* Disable the TIM Capture/Compare 2 interrupt */
2334       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2335       break;
2336     }
2337 
2338     case TIM_CHANNEL_3:
2339     {
2340       /* Disable the TIM Capture/Compare 3 interrupt */
2341       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2342       break;
2343     }
2344 
2345     case TIM_CHANNEL_4:
2346     {
2347       /* Disable the TIM Capture/Compare 4 interrupt */
2348       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2349       break;
2350     }
2351 
2352     default:
2353       status = HAL_ERROR;
2354       break;
2355   }
2356 
2357   if (status == HAL_OK)
2358   {
2359     /* Disable the Input Capture channel */
2360     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2361 
2362     /* Disable the Peripheral */
2363     __HAL_TIM_DISABLE(htim);
2364 
2365     /* Set the TIM channel state */
2366     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2367     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2368   }
2369 
2370   /* Return function status */
2371   return status;
2372 }
2373 
2374 /**
2375   * @brief  Starts the TIM Input Capture measurement in DMA mode.
2376   * @param  htim TIM Input Capture handle
2377   * @param  Channel TIM Channels to be enabled
2378   *          This parameter can be one of the following values:
2379   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2380   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2381   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2382   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2383   * @param  pData The destination Buffer address.
2384   * @param  Length The length of data to be transferred from TIM peripheral to memory.
2385   * @retval HAL status
2386   */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2387 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2388 {
2389   HAL_StatusTypeDef status = HAL_OK;
2390   uint32_t tmpsmcr;
2391 
2392   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2393   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2394 
2395   /* Check the parameters */
2396   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2397   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2398 
2399   /* Set the TIM channel state */
2400   if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2401       || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2402   {
2403     return HAL_BUSY;
2404   }
2405   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2406            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2407   {
2408     if ((pData == NULL) || (Length == 0U))
2409     {
2410       return HAL_ERROR;
2411     }
2412     else
2413     {
2414       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2415       TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2416     }
2417   }
2418   else
2419   {
2420     return HAL_ERROR;
2421   }
2422 
2423   /* Enable the Input Capture channel */
2424   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2425 
2426   switch (Channel)
2427   {
2428     case TIM_CHANNEL_1:
2429     {
2430       /* Set the DMA capture callbacks */
2431       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2432       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2433 
2434       /* Set the DMA error callback */
2435       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2436 
2437       /* Enable the DMA channel */
2438       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2439                            Length) != HAL_OK)
2440       {
2441         /* Return error status */
2442         return HAL_ERROR;
2443       }
2444       /* Enable the TIM Capture/Compare 1 DMA request */
2445       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2446       break;
2447     }
2448 
2449     case TIM_CHANNEL_2:
2450     {
2451       /* Set the DMA capture callbacks */
2452       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2453       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2454 
2455       /* Set the DMA error callback */
2456       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2457 
2458       /* Enable the DMA channel */
2459       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2460                            Length) != HAL_OK)
2461       {
2462         /* Return error status */
2463         return HAL_ERROR;
2464       }
2465       /* Enable the TIM Capture/Compare 2  DMA request */
2466       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2467       break;
2468     }
2469 
2470     case TIM_CHANNEL_3:
2471     {
2472       /* Set the DMA capture callbacks */
2473       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2474       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2475 
2476       /* Set the DMA error callback */
2477       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2478 
2479       /* Enable the DMA channel */
2480       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2481                            Length) != HAL_OK)
2482       {
2483         /* Return error status */
2484         return HAL_ERROR;
2485       }
2486       /* Enable the TIM Capture/Compare 3  DMA request */
2487       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2488       break;
2489     }
2490 
2491     case TIM_CHANNEL_4:
2492     {
2493       /* Set the DMA capture callbacks */
2494       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2495       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2496 
2497       /* Set the DMA error callback */
2498       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2499 
2500       /* Enable the DMA channel */
2501       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2502                            Length) != HAL_OK)
2503       {
2504         /* Return error status */
2505         return HAL_ERROR;
2506       }
2507       /* Enable the TIM Capture/Compare 4  DMA request */
2508       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2509       break;
2510     }
2511 
2512     default:
2513       status = HAL_ERROR;
2514       break;
2515   }
2516 
2517   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2518   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2519   {
2520     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2521     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2522     {
2523       __HAL_TIM_ENABLE(htim);
2524     }
2525   }
2526   else
2527   {
2528     __HAL_TIM_ENABLE(htim);
2529   }
2530 
2531   /* Return function status */
2532   return status;
2533 }
2534 
2535 /**
2536   * @brief  Stops the TIM Input Capture measurement in DMA mode.
2537   * @param  htim TIM Input Capture handle
2538   * @param  Channel TIM Channels to be disabled
2539   *          This parameter can be one of the following values:
2540   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
2541   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
2542   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
2543   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
2544   * @retval HAL status
2545   */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2546 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2547 {
2548   HAL_StatusTypeDef status = HAL_OK;
2549 
2550   /* Check the parameters */
2551   assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2552   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2553 
2554   /* Disable the Input Capture channel */
2555   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2556 
2557   switch (Channel)
2558   {
2559     case TIM_CHANNEL_1:
2560     {
2561       /* Disable the TIM Capture/Compare 1 DMA request */
2562       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2563       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2564       break;
2565     }
2566 
2567     case TIM_CHANNEL_2:
2568     {
2569       /* Disable the TIM Capture/Compare 2 DMA request */
2570       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2571       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2572       break;
2573     }
2574 
2575     case TIM_CHANNEL_3:
2576     {
2577       /* Disable the TIM Capture/Compare 3  DMA request */
2578       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2579       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2580       break;
2581     }
2582 
2583     case TIM_CHANNEL_4:
2584     {
2585       /* Disable the TIM Capture/Compare 4  DMA request */
2586       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2587       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2588       break;
2589     }
2590 
2591     default:
2592       status = HAL_ERROR;
2593       break;
2594   }
2595 
2596   if (status == HAL_OK)
2597   {
2598     /* Disable the Peripheral */
2599     __HAL_TIM_DISABLE(htim);
2600 
2601     /* Set the TIM channel state */
2602     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2603     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2604   }
2605 
2606   /* Return function status */
2607   return status;
2608 }
2609 /**
2610   * @}
2611   */
2612 
2613 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2614   *  @brief    TIM One Pulse functions
2615   *
2616 @verbatim
2617   ==============================================================================
2618                         ##### TIM One Pulse functions #####
2619   ==============================================================================
2620   [..]
2621     This section provides functions allowing to:
2622     (+) Initialize and configure the TIM One Pulse.
2623     (+) De-initialize the TIM One Pulse.
2624     (+) Start the TIM One Pulse.
2625     (+) Stop the TIM One Pulse.
2626     (+) Start the TIM One Pulse and enable interrupt.
2627     (+) Stop the TIM One Pulse and disable interrupt.
2628     (+) Start the TIM One Pulse and enable DMA transfer.
2629     (+) Stop the TIM One Pulse and disable DMA transfer.
2630 
2631 @endverbatim
2632   * @{
2633   */
2634 /**
2635   * @brief  Initializes the TIM One Pulse Time Base according to the specified
2636   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
2637   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2638   *         requires a timer reset to avoid unexpected direction
2639   *         due to DIR bit readonly in center aligned mode.
2640   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2641   * @note   When the timer instance is initialized in One Pulse mode, timer
2642   *         channels 1 and channel 2 are reserved and cannot be used for other
2643   *         purpose.
2644   * @param  htim TIM One Pulse handle
2645   * @param  OnePulseMode Select the One pulse mode.
2646   *         This parameter can be one of the following values:
2647   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2648   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2649   * @retval HAL status
2650   */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2651 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2652 {
2653   /* Check the TIM handle allocation */
2654   if (htim == NULL)
2655   {
2656     return HAL_ERROR;
2657   }
2658 
2659   /* Check the parameters */
2660   assert_param(IS_TIM_INSTANCE(htim->Instance));
2661   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2662   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2663   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2664   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2665   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2666 
2667   if (htim->State == HAL_TIM_STATE_RESET)
2668   {
2669     /* Allocate lock resource and initialize it */
2670     htim->Lock = HAL_UNLOCKED;
2671 
2672 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2673     /* Reset interrupt callbacks to legacy weak callbacks */
2674     TIM_ResetCallback(htim);
2675 
2676     if (htim->OnePulse_MspInitCallback == NULL)
2677     {
2678       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2679     }
2680     /* Init the low level hardware : GPIO, CLOCK, NVIC */
2681     htim->OnePulse_MspInitCallback(htim);
2682 #else
2683     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2684     HAL_TIM_OnePulse_MspInit(htim);
2685 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2686   }
2687 
2688   /* Set the TIM state */
2689   htim->State = HAL_TIM_STATE_BUSY;
2690 
2691   /* Configure the Time base in the One Pulse Mode */
2692   TIM_Base_SetConfig(htim->Instance, &htim->Init);
2693 
2694   /* Reset the OPM Bit */
2695   htim->Instance->CR1 &= ~TIM_CR1_OPM;
2696 
2697   /* Configure the OPM Mode */
2698   htim->Instance->CR1 |= OnePulseMode;
2699 
2700   /* Initialize the DMA burst operation state */
2701   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2702 
2703   /* Initialize the TIM channels state */
2704   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2705   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2706   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2707   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2708 
2709   /* Initialize the TIM state*/
2710   htim->State = HAL_TIM_STATE_READY;
2711 
2712   return HAL_OK;
2713 }
2714 
2715 /**
2716   * @brief  DeInitializes the TIM One Pulse
2717   * @param  htim TIM One Pulse handle
2718   * @retval HAL status
2719   */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2720 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2721 {
2722   /* Check the parameters */
2723   assert_param(IS_TIM_INSTANCE(htim->Instance));
2724 
2725   htim->State = HAL_TIM_STATE_BUSY;
2726 
2727   /* Disable the TIM Peripheral Clock */
2728   __HAL_TIM_DISABLE(htim);
2729 
2730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2731   if (htim->OnePulse_MspDeInitCallback == NULL)
2732   {
2733     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2734   }
2735   /* DeInit the low level hardware */
2736   htim->OnePulse_MspDeInitCallback(htim);
2737 #else
2738   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2739   HAL_TIM_OnePulse_MspDeInit(htim);
2740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2741 
2742   /* Change the DMA burst operation state */
2743   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2744 
2745   /* Set the TIM channel state */
2746   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2747   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2748   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2749   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2750 
2751   /* Change TIM state */
2752   htim->State = HAL_TIM_STATE_RESET;
2753 
2754   /* Release Lock */
2755   __HAL_UNLOCK(htim);
2756 
2757   return HAL_OK;
2758 }
2759 
2760 /**
2761   * @brief  Initializes the TIM One Pulse MSP.
2762   * @param  htim TIM One Pulse handle
2763   * @retval None
2764   */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2765 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2766 {
2767   /* Prevent unused argument(s) compilation warning */
2768   UNUSED(htim);
2769 
2770   /* NOTE : This function should not be modified, when the callback is needed,
2771             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2772    */
2773 }
2774 
2775 /**
2776   * @brief  DeInitializes TIM One Pulse MSP.
2777   * @param  htim TIM One Pulse handle
2778   * @retval None
2779   */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2780 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2781 {
2782   /* Prevent unused argument(s) compilation warning */
2783   UNUSED(htim);
2784 
2785   /* NOTE : This function should not be modified, when the callback is needed,
2786             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2787    */
2788 }
2789 
2790 /**
2791   * @brief  Starts the TIM One Pulse signal generation.
2792   * @note Though OutputChannel parameter is deprecated and ignored by the function
2793   *        it has been kept to avoid HAL_TIM API compatibility break.
2794   * @note The pulse output channel is determined when calling
2795   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2796   * @param  htim TIM One Pulse handle
2797   * @param  OutputChannel See note above
2798   * @retval HAL status
2799   */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2800 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2801 {
2802   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2803   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2804   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2805   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2806 
2807   /* Prevent unused argument(s) compilation warning */
2808   UNUSED(OutputChannel);
2809 
2810   /* Check the TIM channels state */
2811   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2812       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2813       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2814       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2815   {
2816     return HAL_ERROR;
2817   }
2818 
2819   /* Set the TIM channels state */
2820   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2821   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2822   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2823   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2824 
2825   /* Enable the Capture compare and the Input Capture channels
2826     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2827     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2828     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2829     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2830 
2831     No need to enable the counter, it's enabled automatically by hardware
2832     (the counter starts in response to a stimulus and generate a pulse */
2833 
2834   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2835   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2836 
2837   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2838   {
2839     /* Enable the main output */
2840     __HAL_TIM_MOE_ENABLE(htim);
2841   }
2842 
2843   /* Return function status */
2844   return HAL_OK;
2845 }
2846 
2847 /**
2848   * @brief  Stops the TIM One Pulse signal generation.
2849   * @note Though OutputChannel parameter is deprecated and ignored by the function
2850   *        it has been kept to avoid HAL_TIM API compatibility break.
2851   * @note The pulse output channel is determined when calling
2852   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2853   * @param  htim TIM One Pulse handle
2854   * @param  OutputChannel See note above
2855   * @retval HAL status
2856   */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2857 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2858 {
2859   /* Prevent unused argument(s) compilation warning */
2860   UNUSED(OutputChannel);
2861 
2862   /* Disable the Capture compare and the Input Capture channels
2863   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2864   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2865   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2866   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2867 
2868   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2869   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2870 
2871   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2872   {
2873     /* Disable the Main Output */
2874     __HAL_TIM_MOE_DISABLE(htim);
2875   }
2876 
2877   /* Disable the Peripheral */
2878   __HAL_TIM_DISABLE(htim);
2879 
2880   /* Set the TIM channels state */
2881   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2882   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2883   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2884   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2885 
2886   /* Return function status */
2887   return HAL_OK;
2888 }
2889 
2890 /**
2891   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
2892   * @note Though OutputChannel parameter is deprecated and ignored by the function
2893   *        it has been kept to avoid HAL_TIM API compatibility break.
2894   * @note The pulse output channel is determined when calling
2895   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2896   * @param  htim TIM One Pulse handle
2897   * @param  OutputChannel See note above
2898   * @retval HAL status
2899   */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2900 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2901 {
2902   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2903   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2904   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2905   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2906 
2907   /* Prevent unused argument(s) compilation warning */
2908   UNUSED(OutputChannel);
2909 
2910   /* Check the TIM channels state */
2911   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2912       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2913       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2914       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2915   {
2916     return HAL_ERROR;
2917   }
2918 
2919   /* Set the TIM channels state */
2920   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2921   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2922   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2923   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2924 
2925   /* Enable the Capture compare and the Input Capture channels
2926     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2927     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2928     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2929     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2930 
2931     No need to enable the counter, it's enabled automatically by hardware
2932     (the counter starts in response to a stimulus and generate a pulse */
2933 
2934   /* Enable the TIM Capture/Compare 1 interrupt */
2935   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2936 
2937   /* Enable the TIM Capture/Compare 2 interrupt */
2938   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2939 
2940   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2941   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2942 
2943   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2944   {
2945     /* Enable the main output */
2946     __HAL_TIM_MOE_ENABLE(htim);
2947   }
2948 
2949   /* Return function status */
2950   return HAL_OK;
2951 }
2952 
2953 /**
2954   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
2955   * @note Though OutputChannel parameter is deprecated and ignored by the function
2956   *        it has been kept to avoid HAL_TIM API compatibility break.
2957   * @note The pulse output channel is determined when calling
2958   *       @ref HAL_TIM_OnePulse_ConfigChannel().
2959   * @param  htim TIM One Pulse handle
2960   * @param  OutputChannel See note above
2961   * @retval HAL status
2962   */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2964 {
2965   /* Prevent unused argument(s) compilation warning */
2966   UNUSED(OutputChannel);
2967 
2968   /* Disable the TIM Capture/Compare 1 interrupt */
2969   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2970 
2971   /* Disable the TIM Capture/Compare 2 interrupt */
2972   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2973 
2974   /* Disable the Capture compare and the Input Capture channels
2975   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2976   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2977   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2978   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2979   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2980   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2981 
2982   if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2983   {
2984     /* Disable the Main Output */
2985     __HAL_TIM_MOE_DISABLE(htim);
2986   }
2987 
2988   /* Disable the Peripheral */
2989   __HAL_TIM_DISABLE(htim);
2990 
2991   /* Set the TIM channels state */
2992   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2993   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2994   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2995   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2996 
2997   /* Return function status */
2998   return HAL_OK;
2999 }
3000 
3001 /**
3002   * @}
3003   */
3004 
3005 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3006   *  @brief    TIM Encoder functions
3007   *
3008 @verbatim
3009   ==============================================================================
3010                           ##### TIM Encoder functions #####
3011   ==============================================================================
3012   [..]
3013     This section provides functions allowing to:
3014     (+) Initialize and configure the TIM Encoder.
3015     (+) De-initialize the TIM Encoder.
3016     (+) Start the TIM Encoder.
3017     (+) Stop the TIM Encoder.
3018     (+) Start the TIM Encoder and enable interrupt.
3019     (+) Stop the TIM Encoder and disable interrupt.
3020     (+) Start the TIM Encoder and enable DMA transfer.
3021     (+) Stop the TIM Encoder and disable DMA transfer.
3022 
3023 @endverbatim
3024   * @{
3025   */
3026 /**
3027   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
3028   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3029   *         requires a timer reset to avoid unexpected direction
3030   *         due to DIR bit readonly in center aligned mode.
3031   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3032   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
3033   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3034   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3035   * @note   When the timer instance is initialized in Encoder mode, timer
3036   *         channels 1 and channel 2 are reserved and cannot be used for other
3037   *         purpose.
3038   * @param  htim TIM Encoder Interface handle
3039   * @param  sConfig TIM Encoder Interface configuration structure
3040   * @retval HAL status
3041   */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3042 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3043 {
3044   uint32_t tmpsmcr;
3045   uint32_t tmpccmr1;
3046   uint32_t tmpccer;
3047 
3048   /* Check the TIM handle allocation */
3049   if (htim == NULL)
3050   {
3051     return HAL_ERROR;
3052   }
3053 
3054   /* Check the parameters */
3055   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3056   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3057   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3058   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3059   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3060   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3061   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3062   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3063   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3064   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3065   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3066   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3067   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3068   assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3069 
3070   if (htim->State == HAL_TIM_STATE_RESET)
3071   {
3072     /* Allocate lock resource and initialize it */
3073     htim->Lock = HAL_UNLOCKED;
3074 
3075 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3076     /* Reset interrupt callbacks to legacy weak callbacks */
3077     TIM_ResetCallback(htim);
3078 
3079     if (htim->Encoder_MspInitCallback == NULL)
3080     {
3081       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3082     }
3083     /* Init the low level hardware : GPIO, CLOCK, NVIC */
3084     htim->Encoder_MspInitCallback(htim);
3085 #else
3086     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3087     HAL_TIM_Encoder_MspInit(htim);
3088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3089   }
3090 
3091   /* Set the TIM state */
3092   htim->State = HAL_TIM_STATE_BUSY;
3093 
3094   /* Reset the SMS and ECE bits */
3095   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3096 
3097   /* Configure the Time base in the Encoder Mode */
3098   TIM_Base_SetConfig(htim->Instance, &htim->Init);
3099 
3100   /* Get the TIMx SMCR register value */
3101   tmpsmcr = htim->Instance->SMCR;
3102 
3103   /* Get the TIMx CCMR1 register value */
3104   tmpccmr1 = htim->Instance->CCMR1;
3105 
3106   /* Get the TIMx CCER register value */
3107   tmpccer = htim->Instance->CCER;
3108 
3109   /* Set the encoder Mode */
3110   tmpsmcr |= sConfig->EncoderMode;
3111 
3112   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3113   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3114   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3115 
3116   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3117   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3118   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3119   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3120   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3121 
3122   /* Set the TI1 and the TI2 Polarities */
3123   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3124   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3125   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3126 
3127   /* Write to TIMx SMCR */
3128   htim->Instance->SMCR = tmpsmcr;
3129 
3130   /* Write to TIMx CCMR1 */
3131   htim->Instance->CCMR1 = tmpccmr1;
3132 
3133   /* Write to TIMx CCER */
3134   htim->Instance->CCER = tmpccer;
3135 
3136   /* Initialize the DMA burst operation state */
3137   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3138 
3139   /* Set the TIM channels state */
3140   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3141   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3142   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3143   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3144 
3145   /* Initialize the TIM state*/
3146   htim->State = HAL_TIM_STATE_READY;
3147 
3148   return HAL_OK;
3149 }
3150 
3151 
3152 /**
3153   * @brief  DeInitializes the TIM Encoder interface
3154   * @param  htim TIM Encoder Interface handle
3155   * @retval HAL status
3156   */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3157 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3158 {
3159   /* Check the parameters */
3160   assert_param(IS_TIM_INSTANCE(htim->Instance));
3161 
3162   htim->State = HAL_TIM_STATE_BUSY;
3163 
3164   /* Disable the TIM Peripheral Clock */
3165   __HAL_TIM_DISABLE(htim);
3166 
3167 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3168   if (htim->Encoder_MspDeInitCallback == NULL)
3169   {
3170     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3171   }
3172   /* DeInit the low level hardware */
3173   htim->Encoder_MspDeInitCallback(htim);
3174 #else
3175   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3176   HAL_TIM_Encoder_MspDeInit(htim);
3177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3178 
3179   /* Change the DMA burst operation state */
3180   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3181 
3182   /* Set the TIM channels state */
3183   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3184   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3185   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3186   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3187 
3188   /* Change TIM state */
3189   htim->State = HAL_TIM_STATE_RESET;
3190 
3191   /* Release Lock */
3192   __HAL_UNLOCK(htim);
3193 
3194   return HAL_OK;
3195 }
3196 
3197 /**
3198   * @brief  Initializes the TIM Encoder Interface MSP.
3199   * @param  htim TIM Encoder Interface handle
3200   * @retval None
3201   */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3202 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3203 {
3204   /* Prevent unused argument(s) compilation warning */
3205   UNUSED(htim);
3206 
3207   /* NOTE : This function should not be modified, when the callback is needed,
3208             the HAL_TIM_Encoder_MspInit could be implemented in the user file
3209    */
3210 }
3211 
3212 /**
3213   * @brief  DeInitializes TIM Encoder Interface MSP.
3214   * @param  htim TIM Encoder Interface handle
3215   * @retval None
3216   */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3217 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3218 {
3219   /* Prevent unused argument(s) compilation warning */
3220   UNUSED(htim);
3221 
3222   /* NOTE : This function should not be modified, when the callback is needed,
3223             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3224    */
3225 }
3226 
3227 /**
3228   * @brief  Starts the TIM Encoder Interface.
3229   * @param  htim TIM Encoder Interface handle
3230   * @param  Channel TIM Channels to be enabled
3231   *          This parameter can be one of the following values:
3232   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3233   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3234   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3235   * @retval HAL status
3236   */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3237 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3238 {
3239   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3240   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3241   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3242   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3243 
3244   /* Check the parameters */
3245   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3246 
3247   /* Set the TIM channel(s) state */
3248   if (Channel == TIM_CHANNEL_1)
3249   {
3250     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3251         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3252     {
3253       return HAL_ERROR;
3254     }
3255     else
3256     {
3257       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3258       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3259     }
3260   }
3261   else if (Channel == TIM_CHANNEL_2)
3262   {
3263     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3264         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3265     {
3266       return HAL_ERROR;
3267     }
3268     else
3269     {
3270       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3271       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3272     }
3273   }
3274   else
3275   {
3276     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3277         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3278         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3279         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3280     {
3281       return HAL_ERROR;
3282     }
3283     else
3284     {
3285       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3286       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3287       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3288       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3289     }
3290   }
3291 
3292   /* Enable the encoder interface channels */
3293   switch (Channel)
3294   {
3295     case TIM_CHANNEL_1:
3296     {
3297       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3298       break;
3299     }
3300 
3301     case TIM_CHANNEL_2:
3302     {
3303       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3304       break;
3305     }
3306 
3307     default :
3308     {
3309       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3310       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3311       break;
3312     }
3313   }
3314   /* Enable the Peripheral */
3315   __HAL_TIM_ENABLE(htim);
3316 
3317   /* Return function status */
3318   return HAL_OK;
3319 }
3320 
3321 /**
3322   * @brief  Stops the TIM Encoder Interface.
3323   * @param  htim TIM Encoder Interface handle
3324   * @param  Channel TIM Channels to be disabled
3325   *          This parameter can be one of the following values:
3326   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3327   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3328   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3329   * @retval HAL status
3330   */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3331 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3332 {
3333   /* Check the parameters */
3334   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3335 
3336   /* Disable the Input Capture channels 1 and 2
3337     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3338   switch (Channel)
3339   {
3340     case TIM_CHANNEL_1:
3341     {
3342       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3343       break;
3344     }
3345 
3346     case TIM_CHANNEL_2:
3347     {
3348       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3349       break;
3350     }
3351 
3352     default :
3353     {
3354       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3355       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3356       break;
3357     }
3358   }
3359 
3360   /* Disable the Peripheral */
3361   __HAL_TIM_DISABLE(htim);
3362 
3363   /* Set the TIM channel(s) state */
3364   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3365   {
3366     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3367     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3368   }
3369   else
3370   {
3371     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3372     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3373     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3374     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3375   }
3376 
3377   /* Return function status */
3378   return HAL_OK;
3379 }
3380 
3381 /**
3382   * @brief  Starts the TIM Encoder Interface in interrupt mode.
3383   * @param  htim TIM Encoder Interface handle
3384   * @param  Channel TIM Channels to be enabled
3385   *          This parameter can be one of the following values:
3386   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3387   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3388   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3389   * @retval HAL status
3390   */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3391 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3392 {
3393   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3394   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3395   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3396   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3397 
3398   /* Check the parameters */
3399   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3400 
3401   /* Set the TIM channel(s) state */
3402   if (Channel == TIM_CHANNEL_1)
3403   {
3404     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3405         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3406     {
3407       return HAL_ERROR;
3408     }
3409     else
3410     {
3411       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3412       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3413     }
3414   }
3415   else if (Channel == TIM_CHANNEL_2)
3416   {
3417     if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3418         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3419     {
3420       return HAL_ERROR;
3421     }
3422     else
3423     {
3424       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3425       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3426     }
3427   }
3428   else
3429   {
3430     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3431         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3432         || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3433         || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3434     {
3435       return HAL_ERROR;
3436     }
3437     else
3438     {
3439       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3440       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3441       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3442       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3443     }
3444   }
3445 
3446   /* Enable the encoder interface channels */
3447   /* Enable the capture compare Interrupts 1 and/or 2 */
3448   switch (Channel)
3449   {
3450     case TIM_CHANNEL_1:
3451     {
3452       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3453       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3454       break;
3455     }
3456 
3457     case TIM_CHANNEL_2:
3458     {
3459       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3460       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3461       break;
3462     }
3463 
3464     default :
3465     {
3466       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3467       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3468       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3469       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3470       break;
3471     }
3472   }
3473 
3474   /* Enable the Peripheral */
3475   __HAL_TIM_ENABLE(htim);
3476 
3477   /* Return function status */
3478   return HAL_OK;
3479 }
3480 
3481 /**
3482   * @brief  Stops the TIM Encoder Interface in interrupt mode.
3483   * @param  htim TIM Encoder Interface handle
3484   * @param  Channel TIM Channels to be disabled
3485   *          This parameter can be one of the following values:
3486   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3487   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3488   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3489   * @retval HAL status
3490   */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3492 {
3493   /* Check the parameters */
3494   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3495 
3496   /* Disable the Input Capture channels 1 and 2
3497     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3498   if (Channel == TIM_CHANNEL_1)
3499   {
3500     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3501 
3502     /* Disable the capture compare Interrupts 1 */
3503     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3504   }
3505   else if (Channel == TIM_CHANNEL_2)
3506   {
3507     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3508 
3509     /* Disable the capture compare Interrupts 2 */
3510     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3511   }
3512   else
3513   {
3514     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3515     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3516 
3517     /* Disable the capture compare Interrupts 1 and 2 */
3518     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3519     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3520   }
3521 
3522   /* Disable the Peripheral */
3523   __HAL_TIM_DISABLE(htim);
3524 
3525   /* Set the TIM channel(s) state */
3526   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3527   {
3528     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3529     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3530   }
3531   else
3532   {
3533     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3534     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3535     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3536     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3537   }
3538 
3539   /* Return function status */
3540   return HAL_OK;
3541 }
3542 
3543 /**
3544   * @brief  Starts the TIM Encoder Interface in DMA mode.
3545   * @param  htim TIM Encoder Interface handle
3546   * @param  Channel TIM Channels to be enabled
3547   *          This parameter can be one of the following values:
3548   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3549   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3550   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3551   * @param  pData1 The destination Buffer address for IC1.
3552   * @param  pData2 The destination Buffer address for IC2.
3553   * @param  Length The length of data to be transferred from TIM peripheral to memory.
3554   * @retval HAL status
3555   */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3556 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3557                                             uint32_t *pData2, uint16_t Length)
3558 {
3559   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3560   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3561   HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3562   HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3563 
3564   /* Check the parameters */
3565   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3566 
3567   /* Set the TIM channel(s) state */
3568   if (Channel == TIM_CHANNEL_1)
3569   {
3570     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3571         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3572     {
3573       return HAL_BUSY;
3574     }
3575     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3576              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3577     {
3578       if ((pData1 == NULL) || (Length == 0U))
3579       {
3580         return HAL_ERROR;
3581       }
3582       else
3583       {
3584         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3585         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3586       }
3587     }
3588     else
3589     {
3590       return HAL_ERROR;
3591     }
3592   }
3593   else if (Channel == TIM_CHANNEL_2)
3594   {
3595     if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3596         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3597     {
3598       return HAL_BUSY;
3599     }
3600     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3601              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3602     {
3603       if ((pData2 == NULL) || (Length == 0U))
3604       {
3605         return HAL_ERROR;
3606       }
3607       else
3608       {
3609         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3610         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3611       }
3612     }
3613     else
3614     {
3615       return HAL_ERROR;
3616     }
3617   }
3618   else
3619   {
3620     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3621         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3622         || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3623         || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3624     {
3625       return HAL_BUSY;
3626     }
3627     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3628              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3629              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3630              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3631     {
3632       if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3633       {
3634         return HAL_ERROR;
3635       }
3636       else
3637       {
3638         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3639         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3640         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3641         TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3642       }
3643     }
3644     else
3645     {
3646       return HAL_ERROR;
3647     }
3648   }
3649 
3650   switch (Channel)
3651   {
3652     case TIM_CHANNEL_1:
3653     {
3654       /* Set the DMA capture callbacks */
3655       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3656       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3657 
3658       /* Set the DMA error callback */
3659       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3660 
3661       /* Enable the DMA channel */
3662       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3663                            Length) != HAL_OK)
3664       {
3665         /* Return error status */
3666         return HAL_ERROR;
3667       }
3668       /* Enable the TIM Input Capture DMA request */
3669       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3670 
3671       /* Enable the Capture compare channel */
3672       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3673 
3674       /* Enable the Peripheral */
3675       __HAL_TIM_ENABLE(htim);
3676 
3677       break;
3678     }
3679 
3680     case TIM_CHANNEL_2:
3681     {
3682       /* Set the DMA capture callbacks */
3683       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3684       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3685 
3686       /* Set the DMA error callback */
3687       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3688       /* Enable the DMA channel */
3689       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3690                            Length) != HAL_OK)
3691       {
3692         /* Return error status */
3693         return HAL_ERROR;
3694       }
3695       /* Enable the TIM Input Capture  DMA request */
3696       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3697 
3698       /* Enable the Capture compare channel */
3699       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3700 
3701       /* Enable the Peripheral */
3702       __HAL_TIM_ENABLE(htim);
3703 
3704       break;
3705     }
3706 
3707     default:
3708     {
3709       /* Set the DMA capture callbacks */
3710       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3711       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3712 
3713       /* Set the DMA error callback */
3714       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3715 
3716       /* Enable the DMA channel */
3717       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3718                            Length) != HAL_OK)
3719       {
3720         /* Return error status */
3721         return HAL_ERROR;
3722       }
3723 
3724       /* Set the DMA capture callbacks */
3725       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3726       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3727 
3728       /* Set the DMA error callback */
3729       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3730 
3731       /* Enable the DMA channel */
3732       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3733                            Length) != HAL_OK)
3734       {
3735         /* Return error status */
3736         return HAL_ERROR;
3737       }
3738 
3739       /* Enable the TIM Input Capture  DMA request */
3740       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3741       /* Enable the TIM Input Capture  DMA request */
3742       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3743 
3744       /* Enable the Capture compare channel */
3745       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3746       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3747 
3748       /* Enable the Peripheral */
3749       __HAL_TIM_ENABLE(htim);
3750 
3751       break;
3752     }
3753   }
3754 
3755   /* Return function status */
3756   return HAL_OK;
3757 }
3758 
3759 /**
3760   * @brief  Stops the TIM Encoder Interface in DMA mode.
3761   * @param  htim TIM Encoder Interface handle
3762   * @param  Channel TIM Channels to be enabled
3763   *          This parameter can be one of the following values:
3764   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
3765   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
3766   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3767   * @retval HAL status
3768   */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3769 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3770 {
3771   /* Check the parameters */
3772   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3773 
3774   /* Disable the Input Capture channels 1 and 2
3775     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3776   if (Channel == TIM_CHANNEL_1)
3777   {
3778     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3779 
3780     /* Disable the capture compare DMA Request 1 */
3781     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3782     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3783   }
3784   else if (Channel == TIM_CHANNEL_2)
3785   {
3786     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3787 
3788     /* Disable the capture compare DMA Request 2 */
3789     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3790     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3791   }
3792   else
3793   {
3794     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3795     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3796 
3797     /* Disable the capture compare DMA Request 1 and 2 */
3798     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3799     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3800     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3801     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3802   }
3803 
3804   /* Disable the Peripheral */
3805   __HAL_TIM_DISABLE(htim);
3806 
3807   /* Set the TIM channel(s) state */
3808   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3809   {
3810     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3811     TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3812   }
3813   else
3814   {
3815     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3816     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3817     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3818     TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3819   }
3820 
3821   /* Return function status */
3822   return HAL_OK;
3823 }
3824 
3825 /**
3826   * @}
3827   */
3828 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3829   *  @brief    TIM IRQ handler management
3830   *
3831 @verbatim
3832   ==============================================================================
3833                         ##### IRQ handler management #####
3834   ==============================================================================
3835   [..]
3836     This section provides Timer IRQ handler function.
3837 
3838 @endverbatim
3839   * @{
3840   */
3841 /**
3842   * @brief  This function handles TIM interrupts requests.
3843   * @param  htim TIM  handle
3844   * @retval None
3845   */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3846 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3847 {
3848   uint32_t itsource = htim->Instance->DIER;
3849   uint32_t itflag   = htim->Instance->SR;
3850 
3851   /* Capture compare 1 event */
3852   if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3853   {
3854     if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3855     {
3856       {
3857         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3858         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3859 
3860         /* Input capture event */
3861         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3862         {
3863 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3864           htim->IC_CaptureCallback(htim);
3865 #else
3866           HAL_TIM_IC_CaptureCallback(htim);
3867 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3868         }
3869         /* Output compare event */
3870         else
3871         {
3872 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3873           htim->OC_DelayElapsedCallback(htim);
3874           htim->PWM_PulseFinishedCallback(htim);
3875 #else
3876           HAL_TIM_OC_DelayElapsedCallback(htim);
3877           HAL_TIM_PWM_PulseFinishedCallback(htim);
3878 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3879         }
3880         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3881       }
3882     }
3883   }
3884   /* Capture compare 2 event */
3885   if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3886   {
3887     if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3888     {
3889       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3890       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3891       /* Input capture event */
3892       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3893       {
3894 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3895         htim->IC_CaptureCallback(htim);
3896 #else
3897         HAL_TIM_IC_CaptureCallback(htim);
3898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3899       }
3900       /* Output compare event */
3901       else
3902       {
3903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3904         htim->OC_DelayElapsedCallback(htim);
3905         htim->PWM_PulseFinishedCallback(htim);
3906 #else
3907         HAL_TIM_OC_DelayElapsedCallback(htim);
3908         HAL_TIM_PWM_PulseFinishedCallback(htim);
3909 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3910       }
3911       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3912     }
3913   }
3914   /* Capture compare 3 event */
3915   if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3916   {
3917     if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3918     {
3919       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3920       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3921       /* Input capture event */
3922       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3923       {
3924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3925         htim->IC_CaptureCallback(htim);
3926 #else
3927         HAL_TIM_IC_CaptureCallback(htim);
3928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3929       }
3930       /* Output compare event */
3931       else
3932       {
3933 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3934         htim->OC_DelayElapsedCallback(htim);
3935         htim->PWM_PulseFinishedCallback(htim);
3936 #else
3937         HAL_TIM_OC_DelayElapsedCallback(htim);
3938         HAL_TIM_PWM_PulseFinishedCallback(htim);
3939 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3940       }
3941       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3942     }
3943   }
3944   /* Capture compare 4 event */
3945   if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3946   {
3947     if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3948     {
3949       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3950       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3951       /* Input capture event */
3952       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3953       {
3954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3955         htim->IC_CaptureCallback(htim);
3956 #else
3957         HAL_TIM_IC_CaptureCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959       }
3960       /* Output compare event */
3961       else
3962       {
3963 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3964         htim->OC_DelayElapsedCallback(htim);
3965         htim->PWM_PulseFinishedCallback(htim);
3966 #else
3967         HAL_TIM_OC_DelayElapsedCallback(htim);
3968         HAL_TIM_PWM_PulseFinishedCallback(htim);
3969 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3970       }
3971       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3972     }
3973   }
3974   /* TIM Update event */
3975   if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3976   {
3977     if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3978     {
3979       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3981       htim->PeriodElapsedCallback(htim);
3982 #else
3983       HAL_TIM_PeriodElapsedCallback(htim);
3984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3985     }
3986   }
3987   /* TIM Break input event */
3988   if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
3989   {
3990     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3991     {
3992       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3993 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3994       htim->BreakCallback(htim);
3995 #else
3996       HAL_TIMEx_BreakCallback(htim);
3997 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3998     }
3999   }
4000   /* TIM Break2 input event */
4001   if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
4002   {
4003     if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4004     {
4005       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4006 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4007       htim->Break2Callback(htim);
4008 #else
4009       HAL_TIMEx_Break2Callback(htim);
4010 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4011     }
4012   }
4013   /* TIM Trigger detection event */
4014   if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4015   {
4016     if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4017     {
4018       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4019 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4020       htim->TriggerCallback(htim);
4021 #else
4022       HAL_TIM_TriggerCallback(htim);
4023 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4024     }
4025   }
4026   /* TIM commutation event */
4027   if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4028   {
4029     if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4030     {
4031       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4032 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4033       htim->CommutationCallback(htim);
4034 #else
4035       HAL_TIMEx_CommutCallback(htim);
4036 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4037     }
4038   }
4039   /* TIM Encoder index event */
4040   if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
4041   {
4042     if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
4043     {
4044       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
4045 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4046       htim->EncoderIndexCallback(htim);
4047 #else
4048       HAL_TIMEx_EncoderIndexCallback(htim);
4049 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4050     }
4051   }
4052   /* TIM Direction change event */
4053   if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
4054   {
4055     if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
4056     {
4057       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
4058 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4059       htim->DirectionChangeCallback(htim);
4060 #else
4061       HAL_TIMEx_DirectionChangeCallback(htim);
4062 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4063     }
4064   }
4065   /* TIM Index error event */
4066   if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
4067   {
4068     if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
4069     {
4070       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
4071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4072       htim->IndexErrorCallback(htim);
4073 #else
4074       HAL_TIMEx_IndexErrorCallback(htim);
4075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4076     }
4077   }
4078   /* TIM Transition error event */
4079   if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
4080   {
4081     if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
4082     {
4083       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
4084 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4085       htim->TransitionErrorCallback(htim);
4086 #else
4087       HAL_TIMEx_TransitionErrorCallback(htim);
4088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4089     }
4090   }
4091 }
4092 
4093 /**
4094   * @}
4095   */
4096 
4097 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4098   *  @brief    TIM Peripheral Control functions
4099   *
4100 @verbatim
4101   ==============================================================================
4102                    ##### Peripheral Control functions #####
4103   ==============================================================================
4104  [..]
4105    This section provides functions allowing to:
4106       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4107       (+) Configure External Clock source.
4108       (+) Configure Complementary channels, break features and dead time.
4109       (+) Configure Master and the Slave synchronization.
4110       (+) Configure the DMA Burst Mode.
4111 
4112 @endverbatim
4113   * @{
4114   */
4115 
4116 /**
4117   * @brief  Initializes the TIM Output Compare Channels according to the specified
4118   *         parameters in the TIM_OC_InitTypeDef.
4119   * @param  htim TIM Output Compare handle
4120   * @param  sConfig TIM Output Compare configuration structure
4121   * @param  Channel TIM Channels to configure
4122   *          This parameter can be one of the following values:
4123   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4124   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4125   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4126   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4127   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
4128   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
4129   * @retval HAL status
4130   */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4131 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4132                                            const TIM_OC_InitTypeDef *sConfig,
4133                                            uint32_t Channel)
4134 {
4135   HAL_StatusTypeDef status = HAL_OK;
4136 
4137   /* Check the parameters */
4138   assert_param(IS_TIM_CHANNELS(Channel));
4139   assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
4140   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4141 
4142   /* Process Locked */
4143   __HAL_LOCK(htim);
4144 
4145   switch (Channel)
4146   {
4147     case TIM_CHANNEL_1:
4148     {
4149       /* Check the parameters */
4150       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4151 
4152       /* Configure the TIM Channel 1 in Output Compare */
4153       TIM_OC1_SetConfig(htim->Instance, sConfig);
4154       break;
4155     }
4156 
4157     case TIM_CHANNEL_2:
4158     {
4159       /* Check the parameters */
4160       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4161 
4162       /* Configure the TIM Channel 2 in Output Compare */
4163       TIM_OC2_SetConfig(htim->Instance, sConfig);
4164       break;
4165     }
4166 
4167     case TIM_CHANNEL_3:
4168     {
4169       /* Check the parameters */
4170       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4171 
4172       /* Configure the TIM Channel 3 in Output Compare */
4173       TIM_OC3_SetConfig(htim->Instance, sConfig);
4174       break;
4175     }
4176 
4177     case TIM_CHANNEL_4:
4178     {
4179       /* Check the parameters */
4180       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4181 
4182       /* Configure the TIM Channel 4 in Output Compare */
4183       TIM_OC4_SetConfig(htim->Instance, sConfig);
4184       break;
4185     }
4186 
4187     case TIM_CHANNEL_5:
4188     {
4189       /* Check the parameters */
4190       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4191 
4192       /* Configure the TIM Channel 5 in Output Compare */
4193       TIM_OC5_SetConfig(htim->Instance, sConfig);
4194       break;
4195     }
4196 
4197     case TIM_CHANNEL_6:
4198     {
4199       /* Check the parameters */
4200       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4201 
4202       /* Configure the TIM Channel 6 in Output Compare */
4203       TIM_OC6_SetConfig(htim->Instance, sConfig);
4204       break;
4205     }
4206 
4207     default:
4208       status = HAL_ERROR;
4209       break;
4210   }
4211 
4212   __HAL_UNLOCK(htim);
4213 
4214   return status;
4215 }
4216 
4217 /**
4218   * @brief  Initializes the TIM Input Capture Channels according to the specified
4219   *         parameters in the TIM_IC_InitTypeDef.
4220   * @param  htim TIM IC handle
4221   * @param  sConfig TIM Input Capture configuration structure
4222   * @param  Channel TIM Channel to configure
4223   *          This parameter can be one of the following values:
4224   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4225   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4226   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4227   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4228   * @retval HAL status
4229   */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4230 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4231 {
4232   HAL_StatusTypeDef status = HAL_OK;
4233 
4234   /* Check the parameters */
4235   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4236   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4237   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4238   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4239   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4240 
4241   /* Process Locked */
4242   __HAL_LOCK(htim);
4243 
4244   if (Channel == TIM_CHANNEL_1)
4245   {
4246     /* TI1 Configuration */
4247     TIM_TI1_SetConfig(htim->Instance,
4248                       sConfig->ICPolarity,
4249                       sConfig->ICSelection,
4250                       sConfig->ICFilter);
4251 
4252     /* Reset the IC1PSC Bits */
4253     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4254 
4255     /* Set the IC1PSC value */
4256     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4257   }
4258   else if (Channel == TIM_CHANNEL_2)
4259   {
4260     /* TI2 Configuration */
4261     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4262 
4263     TIM_TI2_SetConfig(htim->Instance,
4264                       sConfig->ICPolarity,
4265                       sConfig->ICSelection,
4266                       sConfig->ICFilter);
4267 
4268     /* Reset the IC2PSC Bits */
4269     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4270 
4271     /* Set the IC2PSC value */
4272     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4273   }
4274   else if (Channel == TIM_CHANNEL_3)
4275   {
4276     /* TI3 Configuration */
4277     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4278 
4279     TIM_TI3_SetConfig(htim->Instance,
4280                       sConfig->ICPolarity,
4281                       sConfig->ICSelection,
4282                       sConfig->ICFilter);
4283 
4284     /* Reset the IC3PSC Bits */
4285     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4286 
4287     /* Set the IC3PSC value */
4288     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4289   }
4290   else if (Channel == TIM_CHANNEL_4)
4291   {
4292     /* TI4 Configuration */
4293     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4294 
4295     TIM_TI4_SetConfig(htim->Instance,
4296                       sConfig->ICPolarity,
4297                       sConfig->ICSelection,
4298                       sConfig->ICFilter);
4299 
4300     /* Reset the IC4PSC Bits */
4301     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4302 
4303     /* Set the IC4PSC value */
4304     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4305   }
4306   else
4307   {
4308     status = HAL_ERROR;
4309   }
4310 
4311   __HAL_UNLOCK(htim);
4312 
4313   return status;
4314 }
4315 
4316 /**
4317   * @brief  Initializes the TIM PWM  channels according to the specified
4318   *         parameters in the TIM_OC_InitTypeDef.
4319   * @param  htim TIM PWM handle
4320   * @param  sConfig TIM PWM configuration structure
4321   * @param  Channel TIM Channels to be configured
4322   *          This parameter can be one of the following values:
4323   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4324   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4325   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
4326   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
4327   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
4328   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
4329   * @retval HAL status
4330   */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4331 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4332                                             const TIM_OC_InitTypeDef *sConfig,
4333                                             uint32_t Channel)
4334 {
4335   HAL_StatusTypeDef status = HAL_OK;
4336 
4337   /* Check the parameters */
4338   assert_param(IS_TIM_CHANNELS(Channel));
4339   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4340   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4341   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4342 
4343   /* Process Locked */
4344   __HAL_LOCK(htim);
4345 
4346   switch (Channel)
4347   {
4348     case TIM_CHANNEL_1:
4349     {
4350       /* Check the parameters */
4351       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4352 
4353       /* Configure the Channel 1 in PWM mode */
4354       TIM_OC1_SetConfig(htim->Instance, sConfig);
4355 
4356       /* Set the Preload enable bit for channel1 */
4357       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4358 
4359       /* Configure the Output Fast mode */
4360       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4361       htim->Instance->CCMR1 |= sConfig->OCFastMode;
4362       break;
4363     }
4364 
4365     case TIM_CHANNEL_2:
4366     {
4367       /* Check the parameters */
4368       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4369 
4370       /* Configure the Channel 2 in PWM mode */
4371       TIM_OC2_SetConfig(htim->Instance, sConfig);
4372 
4373       /* Set the Preload enable bit for channel2 */
4374       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4375 
4376       /* Configure the Output Fast mode */
4377       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4378       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4379       break;
4380     }
4381 
4382     case TIM_CHANNEL_3:
4383     {
4384       /* Check the parameters */
4385       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4386 
4387       /* Configure the Channel 3 in PWM mode */
4388       TIM_OC3_SetConfig(htim->Instance, sConfig);
4389 
4390       /* Set the Preload enable bit for channel3 */
4391       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4392 
4393       /* Configure the Output Fast mode */
4394       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4395       htim->Instance->CCMR2 |= sConfig->OCFastMode;
4396       break;
4397     }
4398 
4399     case TIM_CHANNEL_4:
4400     {
4401       /* Check the parameters */
4402       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4403 
4404       /* Configure the Channel 4 in PWM mode */
4405       TIM_OC4_SetConfig(htim->Instance, sConfig);
4406 
4407       /* Set the Preload enable bit for channel4 */
4408       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4409 
4410       /* Configure the Output Fast mode */
4411       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4412       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4413       break;
4414     }
4415 
4416     case TIM_CHANNEL_5:
4417     {
4418       /* Check the parameters */
4419       assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4420 
4421       /* Configure the Channel 5 in PWM mode */
4422       TIM_OC5_SetConfig(htim->Instance, sConfig);
4423 
4424       /* Set the Preload enable bit for channel5*/
4425       htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4426 
4427       /* Configure the Output Fast mode */
4428       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4429       htim->Instance->CCMR3 |= sConfig->OCFastMode;
4430       break;
4431     }
4432 
4433     case TIM_CHANNEL_6:
4434     {
4435       /* Check the parameters */
4436       assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4437 
4438       /* Configure the Channel 6 in PWM mode */
4439       TIM_OC6_SetConfig(htim->Instance, sConfig);
4440 
4441       /* Set the Preload enable bit for channel6 */
4442       htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4443 
4444       /* Configure the Output Fast mode */
4445       htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4446       htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4447       break;
4448     }
4449 
4450     default:
4451       status = HAL_ERROR;
4452       break;
4453   }
4454 
4455   __HAL_UNLOCK(htim);
4456 
4457   return status;
4458 }
4459 
4460 /**
4461   * @brief  Initializes the TIM One Pulse Channels according to the specified
4462   *         parameters in the TIM_OnePulse_InitTypeDef.
4463   * @param  htim TIM One Pulse handle
4464   * @param  sConfig TIM One Pulse configuration structure
4465   * @param  OutputChannel TIM output channel to configure
4466   *          This parameter can be one of the following values:
4467   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4468   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4469   * @param  InputChannel TIM input Channel to configure
4470   *          This parameter can be one of the following values:
4471   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
4472   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
4473   * @note  To output a waveform with a minimum delay user can enable the fast
4474   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4475   *        output is forced in response to the edge detection on TIx input,
4476   *        without taking in account the comparison.
4477   * @retval HAL status
4478   */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4479 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
4480                                                  uint32_t OutputChannel,  uint32_t InputChannel)
4481 {
4482   HAL_StatusTypeDef status = HAL_OK;
4483   TIM_OC_InitTypeDef temp1;
4484 
4485   /* Check the parameters */
4486   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4487   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4488 
4489   if (OutputChannel != InputChannel)
4490   {
4491     /* Process Locked */
4492     __HAL_LOCK(htim);
4493 
4494     htim->State = HAL_TIM_STATE_BUSY;
4495 
4496     /* Extract the Output compare configuration from sConfig structure */
4497     temp1.OCMode = sConfig->OCMode;
4498     temp1.Pulse = sConfig->Pulse;
4499     temp1.OCPolarity = sConfig->OCPolarity;
4500     temp1.OCNPolarity = sConfig->OCNPolarity;
4501     temp1.OCIdleState = sConfig->OCIdleState;
4502     temp1.OCNIdleState = sConfig->OCNIdleState;
4503 
4504     switch (OutputChannel)
4505     {
4506       case TIM_CHANNEL_1:
4507       {
4508         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4509 
4510         TIM_OC1_SetConfig(htim->Instance, &temp1);
4511         break;
4512       }
4513 
4514       case TIM_CHANNEL_2:
4515       {
4516         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4517 
4518         TIM_OC2_SetConfig(htim->Instance, &temp1);
4519         break;
4520       }
4521 
4522       default:
4523         status = HAL_ERROR;
4524         break;
4525     }
4526 
4527     if (status == HAL_OK)
4528     {
4529       switch (InputChannel)
4530       {
4531         case TIM_CHANNEL_1:
4532         {
4533           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4534 
4535           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4536                             sConfig->ICSelection, sConfig->ICFilter);
4537 
4538           /* Reset the IC1PSC Bits */
4539           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4540 
4541           /* Select the Trigger source */
4542           htim->Instance->SMCR &= ~TIM_SMCR_TS;
4543           htim->Instance->SMCR |= TIM_TS_TI1FP1;
4544 
4545           /* Select the Slave Mode */
4546           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4547           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4548           break;
4549         }
4550 
4551         case TIM_CHANNEL_2:
4552         {
4553           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4554 
4555           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4556                             sConfig->ICSelection, sConfig->ICFilter);
4557 
4558           /* Reset the IC2PSC Bits */
4559           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4560 
4561           /* Select the Trigger source */
4562           htim->Instance->SMCR &= ~TIM_SMCR_TS;
4563           htim->Instance->SMCR |= TIM_TS_TI2FP2;
4564 
4565           /* Select the Slave Mode */
4566           htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4567           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4568           break;
4569         }
4570 
4571         default:
4572           status = HAL_ERROR;
4573           break;
4574       }
4575     }
4576 
4577     htim->State = HAL_TIM_STATE_READY;
4578 
4579     __HAL_UNLOCK(htim);
4580 
4581     return status;
4582   }
4583   else
4584   {
4585     return HAL_ERROR;
4586   }
4587 }
4588 
4589 /**
4590   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4591   * @param  htim TIM handle
4592   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
4593   *         This parameter can be one of the following values:
4594   *            @arg TIM_DMABASE_CR1
4595   *            @arg TIM_DMABASE_CR2
4596   *            @arg TIM_DMABASE_SMCR
4597   *            @arg TIM_DMABASE_DIER
4598   *            @arg TIM_DMABASE_SR
4599   *            @arg TIM_DMABASE_EGR
4600   *            @arg TIM_DMABASE_CCMR1
4601   *            @arg TIM_DMABASE_CCMR2
4602   *            @arg TIM_DMABASE_CCER
4603   *            @arg TIM_DMABASE_CNT
4604   *            @arg TIM_DMABASE_PSC
4605   *            @arg TIM_DMABASE_ARR
4606   *            @arg TIM_DMABASE_RCR
4607   *            @arg TIM_DMABASE_CCR1
4608   *            @arg TIM_DMABASE_CCR2
4609   *            @arg TIM_DMABASE_CCR3
4610   *            @arg TIM_DMABASE_CCR4
4611   *            @arg TIM_DMABASE_BDTR
4612   *            @arg TIM_DMABASE_CCMR3
4613   *            @arg TIM_DMABASE_CCR5
4614   *            @arg TIM_DMABASE_CCR6
4615   *            @arg TIM_DMABASE_DTR2
4616   *            @arg TIM_DMABASE_ECR
4617   *            @arg TIM_DMABASE_TISEL
4618   *            @arg TIM_DMABASE_AF1
4619   *            @arg TIM_DMABASE_AF2
4620   *            @arg TIM_DMABASE_OR
4621   * @param  BurstRequestSrc TIM DMA Request sources
4622   *         This parameter can be one of the following values:
4623   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4624   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4625   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4626   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4627   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4628   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4629   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4630   * @param  BurstBuffer The Buffer address.
4631   * @param  BurstLength DMA Burst length. This parameter can be one value
4632   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4633   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
4634   * @retval HAL status
4635   */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4636 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4637                                               uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t  BurstLength)
4638 {
4639   HAL_StatusTypeDef status = HAL_OK;
4640   uint32_t BlockDataLength = 0;
4641   uint32_t data_width;
4642   const DMA_HandleTypeDef *hdma = NULL;
4643 
4644   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4645 
4646   switch (BurstRequestSrc)
4647   {
4648     case TIM_DMA_UPDATE:
4649     {
4650       hdma = htim->hdma[TIM_DMA_ID_UPDATE];
4651       break;
4652     }
4653     case TIM_DMA_CC1:
4654     {
4655       hdma = htim->hdma[TIM_DMA_ID_CC1];
4656       break;
4657     }
4658     case TIM_DMA_CC2:
4659     {
4660       hdma = htim->hdma[TIM_DMA_ID_CC2];
4661       break;
4662     }
4663     case TIM_DMA_CC3:
4664     {
4665       hdma = htim->hdma[TIM_DMA_ID_CC3];
4666       break;
4667     }
4668     case TIM_DMA_CC4:
4669     {
4670       hdma = htim->hdma[TIM_DMA_ID_CC4];
4671       break;
4672     }
4673     case TIM_DMA_COM:
4674     {
4675       hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
4676       break;
4677     }
4678     case TIM_DMA_TRIGGER:
4679     {
4680       hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
4681       break;
4682     }
4683     default:
4684       status = HAL_ERROR;
4685       break;
4686   }
4687 
4688   if (hdma != NULL)
4689   {
4690 
4691     if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
4692         && (hdma->LinkedListQueue->Head != 0U))
4693     {
4694       data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
4695     }
4696     else
4697     {
4698       data_width = hdma->Init.SrcDataWidth;
4699     }
4700 
4701     switch (data_width)
4702     {
4703       case DMA_SRC_DATAWIDTH_BYTE:
4704       {
4705         BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
4706         break;
4707       }
4708       case DMA_SRC_DATAWIDTH_HALFWORD:
4709       {
4710         BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
4711         break;
4712       }
4713       case DMA_SRC_DATAWIDTH_WORD:
4714       {
4715         BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
4716         break;
4717       }
4718       default:
4719         status = HAL_ERROR;
4720         break;
4721     }
4722 
4723     if (status == HAL_OK)
4724     {
4725       status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4726                                                 BlockDataLength);
4727     }
4728   }
4729 
4730 
4731   return status;
4732 }
4733 
4734 /**
4735   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4736   * @param  htim TIM handle
4737   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
4738   *         This parameter can be one of the following values:
4739   *            @arg TIM_DMABASE_CR1
4740   *            @arg TIM_DMABASE_CR2
4741   *            @arg TIM_DMABASE_SMCR
4742   *            @arg TIM_DMABASE_DIER
4743   *            @arg TIM_DMABASE_SR
4744   *            @arg TIM_DMABASE_EGR
4745   *            @arg TIM_DMABASE_CCMR1
4746   *            @arg TIM_DMABASE_CCMR2
4747   *            @arg TIM_DMABASE_CCER
4748   *            @arg TIM_DMABASE_CNT
4749   *            @arg TIM_DMABASE_PSC
4750   *            @arg TIM_DMABASE_ARR
4751   *            @arg TIM_DMABASE_RCR
4752   *            @arg TIM_DMABASE_CCR1
4753   *            @arg TIM_DMABASE_CCR2
4754   *            @arg TIM_DMABASE_CCR3
4755   *            @arg TIM_DMABASE_CCR4
4756   *            @arg TIM_DMABASE_BDTR
4757   *            @arg TIM_DMABASE_CCMR3
4758   *            @arg TIM_DMABASE_CCR5
4759   *            @arg TIM_DMABASE_CCR6
4760   *            @arg TIM_DMABASE_DTR2
4761   *            @arg TIM_DMABASE_ECR
4762   *            @arg TIM_DMABASE_TISEL
4763   *            @arg TIM_DMABASE_AF1
4764   *            @arg TIM_DMABASE_AF2
4765   *            @arg TIM_DMABASE_OR
4766   * @param  BurstRequestSrc TIM DMA Request sources
4767   *         This parameter can be one of the following values:
4768   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
4769   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4770   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4771   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4772   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4773   *            @arg TIM_DMA_COM: TIM Commutation DMA source
4774   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4775   * @param  BurstBuffer The Buffer address.
4776   * @param  BurstLength DMA Burst length. This parameter can be one value
4777   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4778   * @param  DataLength Data length. This parameter can be one value
4779   *         between 1 and 0xFFFF.
4780   * @retval HAL status
4781   */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4782 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4783                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4784                                                    uint32_t  BurstLength,  uint32_t  DataLength)
4785 {
4786   HAL_StatusTypeDef status = HAL_OK;
4787   uint32_t tmpDBSS = 0;
4788 
4789   /* Check the parameters */
4790   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4791   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4792   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4793   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4794   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4795 
4796   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4797   {
4798     return HAL_BUSY;
4799   }
4800   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4801   {
4802     if ((BurstBuffer == NULL) && (BurstLength > 0U))
4803     {
4804       return HAL_ERROR;
4805     }
4806     else
4807     {
4808       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4809     }
4810   }
4811   else
4812   {
4813     /* nothing to do */
4814   }
4815 
4816   switch (BurstRequestSrc)
4817   {
4818     case TIM_DMA_UPDATE:
4819     {
4820       /* Set the DMA Period elapsed callbacks */
4821       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4822       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4823 
4824       /* Set the DMA error callback */
4825       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4826 
4827       /* Enable the DMA channel */
4828       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4829                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4830       {
4831         /* Return error status */
4832         return HAL_ERROR;
4833       }
4834       /* Configure the DMA Burst Source Selection */
4835       tmpDBSS = TIM_DCR_DBSS_0;
4836       break;
4837     }
4838     case TIM_DMA_CC1:
4839     {
4840       /* Set the DMA compare callbacks */
4841       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4842       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4843 
4844       /* Set the DMA error callback */
4845       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4846 
4847       /* Enable the DMA channel */
4848       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4849                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4850       {
4851         /* Return error status */
4852         return HAL_ERROR;
4853       }
4854       /* Configure the DMA Burst Source Selection */
4855       tmpDBSS = TIM_DCR_DBSS_1;
4856       break;
4857     }
4858     case TIM_DMA_CC2:
4859     {
4860       /* Set the DMA compare callbacks */
4861       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4862       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4863 
4864       /* Set the DMA error callback */
4865       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4866 
4867       /* Enable the DMA channel */
4868       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4869                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4870       {
4871         /* Return error status */
4872         return HAL_ERROR;
4873       }
4874       /* Configure the DMA Burst Source Selection */
4875       tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4876       break;
4877     }
4878     case TIM_DMA_CC3:
4879     {
4880       /* Set the DMA compare callbacks */
4881       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4882       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4883 
4884       /* Set the DMA error callback */
4885       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4886 
4887       /* Enable the DMA channel */
4888       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4889                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4890       {
4891         /* Return error status */
4892         return HAL_ERROR;
4893       }
4894       /* Configure the DMA Burst Source Selection */
4895       tmpDBSS = TIM_DCR_DBSS_2;
4896       break;
4897     }
4898     case TIM_DMA_CC4:
4899     {
4900       /* Set the DMA compare callbacks */
4901       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4902       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4903 
4904       /* Set the DMA error callback */
4905       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4906 
4907       /* Enable the DMA channel */
4908       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4909                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4910       {
4911         /* Return error status */
4912         return HAL_ERROR;
4913       }
4914       /* Configure the DMA Burst Source Selection */
4915       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
4916       break;
4917     }
4918     case TIM_DMA_COM:
4919     {
4920       /* Set the DMA commutation callbacks */
4921       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
4922       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
4923 
4924       /* Set the DMA error callback */
4925       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4926 
4927       /* Enable the DMA channel */
4928       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4929                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4930       {
4931         /* Return error status */
4932         return HAL_ERROR;
4933       }
4934       /* Configure the DMA Burst Source Selection */
4935       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
4936       break;
4937     }
4938     case TIM_DMA_TRIGGER:
4939     {
4940       /* Set the DMA trigger callbacks */
4941       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4942       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4943 
4944       /* Set the DMA error callback */
4945       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4946 
4947       /* Enable the DMA channel */
4948       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4949                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4950       {
4951         /* Return error status */
4952         return HAL_ERROR;
4953       }
4954       /* Configure the DMA Burst Source Selection */
4955       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4956       break;
4957     }
4958     default:
4959       status = HAL_ERROR;
4960       break;
4961   }
4962 
4963   if (status == HAL_OK)
4964   {
4965     /* Configure the DMA Burst Mode */
4966     htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
4967     /* Enable the TIM DMA Request */
4968     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4969   }
4970 
4971   /* Return function status */
4972   return status;
4973 }
4974 
4975 /**
4976   * @brief  Stops the TIM DMA Burst mode
4977   * @param  htim TIM handle
4978   * @param  BurstRequestSrc TIM DMA Request sources to disable
4979   * @retval HAL status
4980   */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4981 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4982 {
4983   HAL_StatusTypeDef status = HAL_OK;
4984 
4985   /* Check the parameters */
4986   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4987 
4988   /* Abort the DMA transfer (at least disable the DMA channel) */
4989   switch (BurstRequestSrc)
4990   {
4991     case TIM_DMA_UPDATE:
4992     {
4993       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4994       break;
4995     }
4996     case TIM_DMA_CC1:
4997     {
4998       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4999       break;
5000     }
5001     case TIM_DMA_CC2:
5002     {
5003       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5004       break;
5005     }
5006     case TIM_DMA_CC3:
5007     {
5008       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5009       break;
5010     }
5011     case TIM_DMA_CC4:
5012     {
5013       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5014       break;
5015     }
5016     case TIM_DMA_COM:
5017     {
5018       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5019       break;
5020     }
5021     case TIM_DMA_TRIGGER:
5022     {
5023       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5024       break;
5025     }
5026     default:
5027       status = HAL_ERROR;
5028       break;
5029   }
5030 
5031   if (status == HAL_OK)
5032   {
5033     /* Disable the TIM Update DMA request */
5034     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5035 
5036     /* Change the DMA burst operation state */
5037     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5038   }
5039 
5040   /* Return function status */
5041   return status;
5042 }
5043 
5044 /**
5045   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5046   * @param  htim TIM handle
5047   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
5048   *         This parameter can be one of the following values:
5049   *            @arg TIM_DMABASE_CR1
5050   *            @arg TIM_DMABASE_CR2
5051   *            @arg TIM_DMABASE_SMCR
5052   *            @arg TIM_DMABASE_DIER
5053   *            @arg TIM_DMABASE_SR
5054   *            @arg TIM_DMABASE_EGR
5055   *            @arg TIM_DMABASE_CCMR1
5056   *            @arg TIM_DMABASE_CCMR2
5057   *            @arg TIM_DMABASE_CCER
5058   *            @arg TIM_DMABASE_CNT
5059   *            @arg TIM_DMABASE_PSC
5060   *            @arg TIM_DMABASE_ARR
5061   *            @arg TIM_DMABASE_RCR
5062   *            @arg TIM_DMABASE_CCR1
5063   *            @arg TIM_DMABASE_CCR2
5064   *            @arg TIM_DMABASE_CCR3
5065   *            @arg TIM_DMABASE_CCR4
5066   *            @arg TIM_DMABASE_BDTR
5067   *            @arg TIM_DMABASE_CCMR3
5068   *            @arg TIM_DMABASE_CCR5
5069   *            @arg TIM_DMABASE_CCR6
5070   *            @arg TIM_DMABASE_DTR2
5071   *            @arg TIM_DMABASE_ECR
5072   *            @arg TIM_DMABASE_TISEL
5073   *            @arg TIM_DMABASE_AF1
5074   *            @arg TIM_DMABASE_AF2
5075   *            @arg TIM_DMABASE_OR
5076   * @param  BurstRequestSrc TIM DMA Request sources
5077   *         This parameter can be one of the following values:
5078   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
5079   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5080   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5081   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5082   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5083   *            @arg TIM_DMA_COM: TIM Commutation DMA source
5084   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5085   * @param  BurstBuffer The Buffer address.
5086   * @param  BurstLength DMA Burst length. This parameter can be one value
5087   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5088   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
5089   * @retval HAL status
5090   */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)5091 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5092                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
5093 {
5094   HAL_StatusTypeDef status = HAL_OK;
5095   uint32_t BlockDataLength = 0;
5096   uint32_t data_width;
5097   const DMA_HandleTypeDef *hdma = NULL;
5098 
5099   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5100 
5101   switch (BurstRequestSrc)
5102   {
5103     case TIM_DMA_UPDATE:
5104     {
5105       hdma = htim->hdma[TIM_DMA_ID_UPDATE];
5106       break;
5107     }
5108     case TIM_DMA_CC1:
5109     {
5110       hdma = htim->hdma[TIM_DMA_ID_CC1];
5111       break;
5112     }
5113     case TIM_DMA_CC2:
5114     {
5115       hdma = htim->hdma[TIM_DMA_ID_CC2];
5116       break;
5117     }
5118     case TIM_DMA_CC3:
5119     {
5120       hdma = htim->hdma[TIM_DMA_ID_CC3];
5121       break;
5122     }
5123     case TIM_DMA_CC4:
5124     {
5125       hdma = htim->hdma[TIM_DMA_ID_CC4];
5126       break;
5127     }
5128     case TIM_DMA_COM:
5129     {
5130       hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
5131       break;
5132     }
5133     case TIM_DMA_TRIGGER:
5134     {
5135       hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
5136       break;
5137     }
5138     default:
5139       status = HAL_ERROR;
5140       break;
5141   }
5142 
5143   if (hdma != NULL)
5144   {
5145 
5146     if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
5147         && (hdma->LinkedListQueue->Head != 0U))
5148     {
5149       data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
5150     }
5151     else
5152     {
5153       data_width = hdma->Init.SrcDataWidth;
5154     }
5155 
5156     switch (data_width)
5157 
5158     {
5159       case DMA_SRC_DATAWIDTH_BYTE:
5160       {
5161         BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
5162         break;
5163       }
5164       case DMA_SRC_DATAWIDTH_HALFWORD:
5165       {
5166         BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
5167         break;
5168       }
5169       case DMA_SRC_DATAWIDTH_WORD:
5170       {
5171         BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
5172         break;
5173       }
5174       default:
5175         status = HAL_ERROR;
5176         break;
5177     }
5178 
5179     if (status == HAL_OK)
5180     {
5181       status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
5182                                                BlockDataLength);
5183     }
5184   }
5185 
5186   return status;
5187 }
5188 
5189 /**
5190   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5191   * @param  htim TIM handle
5192   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
5193   *         This parameter can be one of the following values:
5194   *            @arg TIM_DMABASE_CR1
5195   *            @arg TIM_DMABASE_CR2
5196   *            @arg TIM_DMABASE_SMCR
5197   *            @arg TIM_DMABASE_DIER
5198   *            @arg TIM_DMABASE_SR
5199   *            @arg TIM_DMABASE_EGR
5200   *            @arg TIM_DMABASE_CCMR1
5201   *            @arg TIM_DMABASE_CCMR2
5202   *            @arg TIM_DMABASE_CCER
5203   *            @arg TIM_DMABASE_CNT
5204   *            @arg TIM_DMABASE_PSC
5205   *            @arg TIM_DMABASE_ARR
5206   *            @arg TIM_DMABASE_RCR
5207   *            @arg TIM_DMABASE_CCR1
5208   *            @arg TIM_DMABASE_CCR2
5209   *            @arg TIM_DMABASE_CCR3
5210   *            @arg TIM_DMABASE_CCR4
5211   *            @arg TIM_DMABASE_BDTR
5212   *            @arg TIM_DMABASE_CCMR3
5213   *            @arg TIM_DMABASE_CCR5
5214   *            @arg TIM_DMABASE_CCR6
5215   *            @arg TIM_DMABASE_DTR2
5216   *            @arg TIM_DMABASE_ECR
5217   *            @arg TIM_DMABASE_TISEL
5218   *            @arg TIM_DMABASE_AF1
5219   *            @arg TIM_DMABASE_AF2
5220   *            @arg TIM_DMABASE_OR
5221   * @param  BurstRequestSrc TIM DMA Request sources
5222   *         This parameter can be one of the following values:
5223   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
5224   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5225   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5226   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5227   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5228   *            @arg TIM_DMA_COM: TIM Commutation DMA source
5229   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5230   * @param  BurstBuffer The Buffer address.
5231   * @param  BurstLength DMA Burst length. This parameter can be one value
5232   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5233   * @param  DataLength Data length. This parameter can be one value
5234   *         between 1 and 0xFFFF.
5235   * @retval HAL status
5236   */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)5237 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5238                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
5239                                                   uint32_t  BurstLength, uint32_t  DataLength)
5240 {
5241   HAL_StatusTypeDef status = HAL_OK;
5242   uint32_t tmpDBSS = 0;
5243 
5244   /* Check the parameters */
5245   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5246   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5247   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5248   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5249   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5250 
5251   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5252   {
5253     return HAL_BUSY;
5254   }
5255   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5256   {
5257     if ((BurstBuffer == NULL) && (BurstLength > 0U))
5258     {
5259       return HAL_ERROR;
5260     }
5261     else
5262     {
5263       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5264     }
5265   }
5266   else
5267   {
5268     /* nothing to do */
5269   }
5270   switch (BurstRequestSrc)
5271   {
5272     case TIM_DMA_UPDATE:
5273     {
5274       /* Set the DMA Period elapsed callbacks */
5275       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5276       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5277 
5278       /* Set the DMA error callback */
5279       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5280 
5281       /* Enable the DMA channel */
5282       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5283                            DataLength) != HAL_OK)
5284       {
5285         /* Return error status */
5286         return HAL_ERROR;
5287       }
5288       /* Configure the DMA Burst Source Selection */
5289       tmpDBSS = TIM_DCR_DBSS_0;
5290       break;
5291     }
5292     case TIM_DMA_CC1:
5293     {
5294       /* Set the DMA capture callbacks */
5295       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5296       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5297 
5298       /* Set the DMA error callback */
5299       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5300 
5301       /* Enable the DMA channel */
5302       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5303                            DataLength) != HAL_OK)
5304       {
5305         /* Return error status */
5306         return HAL_ERROR;
5307       }
5308       /* Configure the DMA Burst Source Selection */
5309       tmpDBSS =  TIM_DCR_DBSS_1;
5310       break;
5311     }
5312     case TIM_DMA_CC2:
5313     {
5314       /* Set the DMA capture callbacks */
5315       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5316       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5317 
5318       /* Set the DMA error callback */
5319       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5320 
5321       /* Enable the DMA channel */
5322       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5323                            DataLength) != HAL_OK)
5324       {
5325         /* Return error status */
5326         return HAL_ERROR;
5327       }
5328       /* Configure the DMA Burst Source Selection */
5329       tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5330       break;
5331     }
5332     case TIM_DMA_CC3:
5333     {
5334       /* Set the DMA capture callbacks */
5335       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5336       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5337 
5338       /* Set the DMA error callback */
5339       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5340 
5341       /* Enable the DMA channel */
5342       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5343                            DataLength) != HAL_OK)
5344       {
5345         /* Return error status */
5346         return HAL_ERROR;
5347       }
5348       /* Configure the DMA Burst Source Selection */
5349       tmpDBSS = TIM_DCR_DBSS_2;
5350       break;
5351     }
5352     case TIM_DMA_CC4:
5353     {
5354       /* Set the DMA capture callbacks */
5355       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5356       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5357 
5358       /* Set the DMA error callback */
5359       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5360 
5361       /* Enable the DMA channel */
5362       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5363                            DataLength) != HAL_OK)
5364       {
5365         /* Return error status */
5366         return HAL_ERROR;
5367       }
5368       /* Configure the DMA Burst Source Selection */
5369       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
5370       break;
5371     }
5372     case TIM_DMA_COM:
5373     {
5374       /* Set the DMA commutation callbacks */
5375       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
5376       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
5377 
5378       /* Set the DMA error callback */
5379       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5380 
5381       /* Enable the DMA channel */
5382       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5383                            DataLength) != HAL_OK)
5384       {
5385         /* Return error status */
5386         return HAL_ERROR;
5387       }
5388       /* Configure the DMA Burst Source Selection */
5389       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
5390       break;
5391     }
5392     case TIM_DMA_TRIGGER:
5393     {
5394       /* Set the DMA trigger callbacks */
5395       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5396       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5397 
5398       /* Set the DMA error callback */
5399       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5400 
5401       /* Enable the DMA channel */
5402       if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5403                            DataLength) != HAL_OK)
5404       {
5405         /* Return error status */
5406         return HAL_ERROR;
5407       }
5408       /* Configure the DMA Burst Source Selection */
5409       tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5410       break;
5411     }
5412     default:
5413       status = HAL_ERROR;
5414       break;
5415   }
5416 
5417   if (status == HAL_OK)
5418   {
5419     /* Configure the DMA Burst Mode */
5420     htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
5421 
5422     /* Enable the TIM DMA Request */
5423     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5424   }
5425 
5426   /* Return function status */
5427   return status;
5428 }
5429 
5430 /**
5431   * @brief  Stop the DMA burst reading
5432   * @param  htim TIM handle
5433   * @param  BurstRequestSrc TIM DMA Request sources to disable.
5434   * @retval HAL status
5435   */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5436 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5437 {
5438   HAL_StatusTypeDef status = HAL_OK;
5439 
5440   /* Check the parameters */
5441   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5442 
5443   /* Abort the DMA transfer (at least disable the DMA channel) */
5444   switch (BurstRequestSrc)
5445   {
5446     case TIM_DMA_UPDATE:
5447     {
5448       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5449       break;
5450     }
5451     case TIM_DMA_CC1:
5452     {
5453       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5454       break;
5455     }
5456     case TIM_DMA_CC2:
5457     {
5458       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5459       break;
5460     }
5461     case TIM_DMA_CC3:
5462     {
5463       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5464       break;
5465     }
5466     case TIM_DMA_CC4:
5467     {
5468       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5469       break;
5470     }
5471     case TIM_DMA_COM:
5472     {
5473       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5474       break;
5475     }
5476     case TIM_DMA_TRIGGER:
5477     {
5478       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5479       break;
5480     }
5481     default:
5482       status = HAL_ERROR;
5483       break;
5484   }
5485 
5486   if (status == HAL_OK)
5487   {
5488     /* Disable the TIM Update DMA request */
5489     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5490 
5491     /* Change the DMA burst operation state */
5492     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5493   }
5494 
5495   /* Return function status */
5496   return status;
5497 }
5498 
5499 /**
5500   * @brief  Generate a software event
5501   * @param  htim TIM handle
5502   * @param  EventSource specifies the event source.
5503   *          This parameter can be one of the following values:
5504   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5505   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5506   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5507   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5508   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5509   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
5510   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5511   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5512   *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5513   * @note   Basic timers can only generate an update event.
5514   * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5515   * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5516   *         only for timer instances supporting break input(s).
5517   * @retval HAL status
5518   */
5519 
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5520 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5521 {
5522   /* Check the parameters */
5523   assert_param(IS_TIM_INSTANCE(htim->Instance));
5524   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5525 
5526   /* Process Locked */
5527   __HAL_LOCK(htim);
5528 
5529   /* Change the TIM state */
5530   htim->State = HAL_TIM_STATE_BUSY;
5531 
5532   /* Set the event sources */
5533   htim->Instance->EGR = EventSource;
5534 
5535   /* Change the TIM state */
5536   htim->State = HAL_TIM_STATE_READY;
5537 
5538   __HAL_UNLOCK(htim);
5539 
5540   /* Return function status */
5541   return HAL_OK;
5542 }
5543 
5544 /**
5545   * @brief  Configures the OCRef clear feature
5546   * @param  htim TIM handle
5547   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5548   *         contains the OCREF clear feature and parameters for the TIM peripheral.
5549   * @param  Channel specifies the TIM Channel
5550   *          This parameter can be one of the following values:
5551   *            @arg TIM_CHANNEL_1: TIM Channel 1
5552   *            @arg TIM_CHANNEL_2: TIM Channel 2
5553   *            @arg TIM_CHANNEL_3: TIM Channel 3
5554   *            @arg TIM_CHANNEL_4: TIM Channel 4
5555   *            @arg TIM_CHANNEL_5: TIM Channel 5
5556   *            @arg TIM_CHANNEL_6: TIM Channel 6
5557   * @retval HAL status
5558   */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5559 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5560                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5561                                            uint32_t Channel)
5562 {
5563   HAL_StatusTypeDef status = HAL_OK;
5564 
5565   /* Check the parameters */
5566   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5567   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5568 
5569   /* Process Locked */
5570   __HAL_LOCK(htim);
5571 
5572   htim->State = HAL_TIM_STATE_BUSY;
5573 
5574   switch (sClearInputConfig->ClearInputSource)
5575   {
5576     case TIM_CLEARINPUTSOURCE_NONE:
5577     {
5578       /* Clear the OCREF clear selection bit and the the ETR Bits */
5579       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5580       break;
5581     }
5582 
5583     case TIM_CLEARINPUTSOURCE_COMP1:
5584     case TIM_CLEARINPUTSOURCE_COMP2:
5585     {
5586       /* Clear the OCREF clear selection bit */
5587       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5588 
5589       /* Clear TIMx_AF2_OCRSEL (reset value) */
5590       MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
5591       break;
5592     }
5593 
5594     case TIM_CLEARINPUTSOURCE_ETR:
5595     {
5596       /* Check the parameters */
5597       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5598       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5599       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5600 
5601       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5602       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5603       {
5604         htim->State = HAL_TIM_STATE_READY;
5605         __HAL_UNLOCK(htim);
5606         return HAL_ERROR;
5607       }
5608 
5609       TIM_ETR_SetConfig(htim->Instance,
5610                         sClearInputConfig->ClearInputPrescaler,
5611                         sClearInputConfig->ClearInputPolarity,
5612                         sClearInputConfig->ClearInputFilter);
5613 
5614       /* Set the OCREF clear selection bit */
5615       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5616       break;
5617     }
5618 
5619     default:
5620       status = HAL_ERROR;
5621       break;
5622   }
5623 
5624   if (status == HAL_OK)
5625   {
5626     switch (Channel)
5627     {
5628       case TIM_CHANNEL_1:
5629       {
5630         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5631         {
5632           /* Enable the OCREF clear feature for Channel 1 */
5633           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5634         }
5635         else
5636         {
5637           /* Disable the OCREF clear feature for Channel 1 */
5638           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5639         }
5640         break;
5641       }
5642       case TIM_CHANNEL_2:
5643       {
5644         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5645         {
5646           /* Enable the OCREF clear feature for Channel 2 */
5647           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5648         }
5649         else
5650         {
5651           /* Disable the OCREF clear feature for Channel 2 */
5652           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5653         }
5654         break;
5655       }
5656       case TIM_CHANNEL_3:
5657       {
5658         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5659         {
5660           /* Enable the OCREF clear feature for Channel 3 */
5661           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5662         }
5663         else
5664         {
5665           /* Disable the OCREF clear feature for Channel 3 */
5666           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5667         }
5668         break;
5669       }
5670       case TIM_CHANNEL_4:
5671       {
5672         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5673         {
5674           /* Enable the OCREF clear feature for Channel 4 */
5675           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5676         }
5677         else
5678         {
5679           /* Disable the OCREF clear feature for Channel 4 */
5680           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5681         }
5682         break;
5683       }
5684       case TIM_CHANNEL_5:
5685       {
5686         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5687         {
5688           /* Enable the OCREF clear feature for Channel 5 */
5689           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5690         }
5691         else
5692         {
5693           /* Disable the OCREF clear feature for Channel 5 */
5694           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5695         }
5696         break;
5697       }
5698       case TIM_CHANNEL_6:
5699       {
5700         if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5701         {
5702           /* Enable the OCREF clear feature for Channel 6 */
5703           SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5704         }
5705         else
5706         {
5707           /* Disable the OCREF clear feature for Channel 6 */
5708           CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5709         }
5710         break;
5711       }
5712       default:
5713         break;
5714     }
5715   }
5716 
5717   htim->State = HAL_TIM_STATE_READY;
5718 
5719   __HAL_UNLOCK(htim);
5720 
5721   return status;
5722 }
5723 
5724 /**
5725   * @brief   Configures the clock source to be used
5726   * @param  htim TIM handle
5727   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5728   *         contains the clock source information for the TIM peripheral.
5729   * @retval HAL status
5730   */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5731 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5732 {
5733   HAL_StatusTypeDef status = HAL_OK;
5734   uint32_t tmpsmcr;
5735 
5736   /* Process Locked */
5737   __HAL_LOCK(htim);
5738 
5739   htim->State = HAL_TIM_STATE_BUSY;
5740 
5741   /* Check the parameters */
5742   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5743 
5744   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5745   tmpsmcr = htim->Instance->SMCR;
5746   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5747   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5748   htim->Instance->SMCR = tmpsmcr;
5749 
5750   switch (sClockSourceConfig->ClockSource)
5751   {
5752     case TIM_CLOCKSOURCE_INTERNAL:
5753     {
5754       assert_param(IS_TIM_INSTANCE(htim->Instance));
5755       break;
5756     }
5757 
5758     case TIM_CLOCKSOURCE_ETRMODE1:
5759     {
5760       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5761       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5762 
5763       /* Check ETR input conditioning related parameters */
5764       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5765       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5766       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5767 
5768       /* Configure the ETR Clock source */
5769       TIM_ETR_SetConfig(htim->Instance,
5770                         sClockSourceConfig->ClockPrescaler,
5771                         sClockSourceConfig->ClockPolarity,
5772                         sClockSourceConfig->ClockFilter);
5773 
5774       /* Select the External clock mode1 and the ETRF trigger */
5775       tmpsmcr = htim->Instance->SMCR;
5776       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5777       /* Write to TIMx SMCR */
5778       htim->Instance->SMCR = tmpsmcr;
5779       break;
5780     }
5781 
5782     case TIM_CLOCKSOURCE_ETRMODE2:
5783     {
5784       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5785       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5786 
5787       /* Check ETR input conditioning related parameters */
5788       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5789       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5790       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5791 
5792       /* Configure the ETR Clock source */
5793       TIM_ETR_SetConfig(htim->Instance,
5794                         sClockSourceConfig->ClockPrescaler,
5795                         sClockSourceConfig->ClockPolarity,
5796                         sClockSourceConfig->ClockFilter);
5797       /* Enable the External clock mode2 */
5798       htim->Instance->SMCR |= TIM_SMCR_ECE;
5799       break;
5800     }
5801 
5802     case TIM_CLOCKSOURCE_TI1:
5803     {
5804       /* Check whether or not the timer instance supports external clock mode 1 */
5805       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5806 
5807       /* Check TI1 input conditioning related parameters */
5808       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5809       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5810 
5811       TIM_TI1_ConfigInputStage(htim->Instance,
5812                                sClockSourceConfig->ClockPolarity,
5813                                sClockSourceConfig->ClockFilter);
5814       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5815       break;
5816     }
5817 
5818     case TIM_CLOCKSOURCE_TI2:
5819     {
5820       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5821       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5822 
5823       /* Check TI2 input conditioning related parameters */
5824       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5825       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5826 
5827       TIM_TI2_ConfigInputStage(htim->Instance,
5828                                sClockSourceConfig->ClockPolarity,
5829                                sClockSourceConfig->ClockFilter);
5830       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5831       break;
5832     }
5833 
5834     case TIM_CLOCKSOURCE_TI1ED:
5835     {
5836       /* Check whether or not the timer instance supports external clock mode 1 */
5837       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5838 
5839       /* Check TI1 input conditioning related parameters */
5840       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5841       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5842 
5843       TIM_TI1_ConfigInputStage(htim->Instance,
5844                                sClockSourceConfig->ClockPolarity,
5845                                sClockSourceConfig->ClockFilter);
5846       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5847       break;
5848     }
5849 
5850     case TIM_CLOCKSOURCE_ITR0:
5851     case TIM_CLOCKSOURCE_ITR1:
5852     case TIM_CLOCKSOURCE_ITR2:
5853     case TIM_CLOCKSOURCE_ITR7:
5854     case TIM_CLOCKSOURCE_ITR8:
5855     {
5856       /* Check whether or not the timer instance supports internal trigger input */
5857       assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5858 
5859       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5860       break;
5861     }
5862 
5863     default:
5864       status = HAL_ERROR;
5865       break;
5866   }
5867   htim->State = HAL_TIM_STATE_READY;
5868 
5869   __HAL_UNLOCK(htim);
5870 
5871   return status;
5872 }
5873 
5874 /**
5875   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
5876   *         or a XOR combination between CH1_input, CH2_input & CH3_input
5877   * @param  htim TIM handle.
5878   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
5879   *         output of a XOR gate.
5880   *          This parameter can be one of the following values:
5881   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5882   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5883   *            pins are connected to the TI1 input (XOR combination)
5884   * @retval HAL status
5885   */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5886 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5887 {
5888   uint32_t tmpcr2;
5889 
5890   /* Check the parameters */
5891   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5892   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5893 
5894   /* Get the TIMx CR2 register value */
5895   tmpcr2 = htim->Instance->CR2;
5896 
5897   /* Reset the TI1 selection */
5898   tmpcr2 &= ~TIM_CR2_TI1S;
5899 
5900   /* Set the TI1 selection */
5901   tmpcr2 |= TI1_Selection;
5902 
5903   /* Write to TIMxCR2 */
5904   htim->Instance->CR2 = tmpcr2;
5905 
5906   return HAL_OK;
5907 }
5908 
5909 /**
5910   * @brief  Configures the TIM in Slave mode
5911   * @param  htim TIM handle.
5912   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5913   *         contains the selected trigger (internal trigger input, filtered
5914   *         timer input or external trigger input) and the Slave mode
5915   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5916   * @retval HAL status
5917   */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5918 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5919 {
5920   /* Check the parameters */
5921   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5922   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5923   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5924 
5925   __HAL_LOCK(htim);
5926 
5927   htim->State = HAL_TIM_STATE_BUSY;
5928 
5929   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5930   {
5931     htim->State = HAL_TIM_STATE_READY;
5932     __HAL_UNLOCK(htim);
5933     return HAL_ERROR;
5934   }
5935 
5936   /* Disable Trigger Interrupt */
5937   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5938 
5939   /* Disable Trigger DMA request */
5940   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5941 
5942   htim->State = HAL_TIM_STATE_READY;
5943 
5944   __HAL_UNLOCK(htim);
5945 
5946   return HAL_OK;
5947 }
5948 
5949 /**
5950   * @brief  Configures the TIM in Slave mode in interrupt mode
5951   * @param  htim TIM handle.
5952   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5953   *         contains the selected trigger (internal trigger input, filtered
5954   *         timer input or external trigger input) and the Slave mode
5955   *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5956   * @retval HAL status
5957   */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5958 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5959                                                 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5960 {
5961   /* Check the parameters */
5962   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5963   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5964   assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5965 
5966   __HAL_LOCK(htim);
5967 
5968   htim->State = HAL_TIM_STATE_BUSY;
5969 
5970   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5971   {
5972     htim->State = HAL_TIM_STATE_READY;
5973     __HAL_UNLOCK(htim);
5974     return HAL_ERROR;
5975   }
5976 
5977   /* Enable Trigger Interrupt */
5978   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5979 
5980   /* Disable Trigger DMA request */
5981   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5982 
5983   htim->State = HAL_TIM_STATE_READY;
5984 
5985   __HAL_UNLOCK(htim);
5986 
5987   return HAL_OK;
5988 }
5989 
5990 /**
5991   * @brief  Read the captured value from Capture Compare unit
5992   * @param  htim TIM handle.
5993   * @param  Channel TIM Channels to be enabled
5994   *          This parameter can be one of the following values:
5995   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
5996   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
5997   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
5998   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
5999   * @retval Captured value
6000   */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)6001 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
6002 {
6003   uint32_t tmpreg = 0U;
6004 
6005   switch (Channel)
6006   {
6007     case TIM_CHANNEL_1:
6008     {
6009       /* Check the parameters */
6010       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6011 
6012       /* Return the capture 1 value */
6013       tmpreg =  htim->Instance->CCR1;
6014 
6015       break;
6016     }
6017     case TIM_CHANNEL_2:
6018     {
6019       /* Check the parameters */
6020       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6021 
6022       /* Return the capture 2 value */
6023       tmpreg =   htim->Instance->CCR2;
6024 
6025       break;
6026     }
6027 
6028     case TIM_CHANNEL_3:
6029     {
6030       /* Check the parameters */
6031       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
6032 
6033       /* Return the capture 3 value */
6034       tmpreg =   htim->Instance->CCR3;
6035 
6036       break;
6037     }
6038 
6039     case TIM_CHANNEL_4:
6040     {
6041       /* Check the parameters */
6042       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
6043 
6044       /* Return the capture 4 value */
6045       tmpreg =   htim->Instance->CCR4;
6046 
6047       break;
6048     }
6049 
6050     default:
6051       break;
6052   }
6053 
6054   return tmpreg;
6055 }
6056 
6057 /**
6058   * @brief  Start the DMA data transfer.
6059   * @param  hdma DMA handle
6060   * @param  src      : The source memory Buffer address.
6061   * @param  dst      : The destination memory Buffer address.
6062   * @param  length   : The size of a source block transfer in byte.
6063   * @retval HAL status
6064   */
TIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)6065 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
6066                                    uint32_t length)
6067 {
6068   HAL_StatusTypeDef status ;
6069 
6070   /* Enable the DMA channel */
6071   if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6072   {
6073     if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
6074     {
6075       /* Enable the DMA channel */
6076       hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
6077       hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
6078       hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
6079 
6080       status = HAL_DMAEx_List_Start_IT(hdma);
6081     }
6082     else
6083     {
6084       status = HAL_ERROR;
6085     }
6086   }
6087   else
6088   {
6089     status = HAL_DMA_Start_IT(hdma, src, dst, length);
6090   }
6091 
6092   return status;
6093 }
6094 
6095 /**
6096   * @}
6097   */
6098 
6099 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
6100   *  @brief    TIM Callbacks functions
6101   *
6102 @verbatim
6103   ==============================================================================
6104                         ##### TIM Callbacks functions #####
6105   ==============================================================================
6106  [..]
6107    This section provides TIM callback functions:
6108    (+) TIM Period elapsed callback
6109    (+) TIM Output Compare callback
6110    (+) TIM Input capture callback
6111    (+) TIM Trigger callback
6112    (+) TIM Error callback
6113    (+) TIM Index callback
6114    (+) TIM Direction change callback
6115    (+) TIM Index error callback
6116    (+) TIM Transition error callback
6117 
6118 @endverbatim
6119   * @{
6120   */
6121 
6122 /**
6123   * @brief  Period elapsed callback in non-blocking mode
6124   * @param  htim TIM handle
6125   * @retval None
6126   */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)6127 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
6128 {
6129   /* Prevent unused argument(s) compilation warning */
6130   UNUSED(htim);
6131 
6132   /* NOTE : This function should not be modified, when the callback is needed,
6133             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
6134    */
6135 }
6136 
6137 /**
6138   * @brief  Period elapsed half complete callback in non-blocking mode
6139   * @param  htim TIM handle
6140   * @retval None
6141   */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)6142 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
6143 {
6144   /* Prevent unused argument(s) compilation warning */
6145   UNUSED(htim);
6146 
6147   /* NOTE : This function should not be modified, when the callback is needed,
6148             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
6149    */
6150 }
6151 
6152 /**
6153   * @brief  Output Compare callback in non-blocking mode
6154   * @param  htim TIM OC handle
6155   * @retval None
6156   */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)6157 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
6158 {
6159   /* Prevent unused argument(s) compilation warning */
6160   UNUSED(htim);
6161 
6162   /* NOTE : This function should not be modified, when the callback is needed,
6163             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
6164    */
6165 }
6166 
6167 /**
6168   * @brief  Input Capture callback in non-blocking mode
6169   * @param  htim TIM IC handle
6170   * @retval None
6171   */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)6172 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
6173 {
6174   /* Prevent unused argument(s) compilation warning */
6175   UNUSED(htim);
6176 
6177   /* NOTE : This function should not be modified, when the callback is needed,
6178             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
6179    */
6180 }
6181 
6182 /**
6183   * @brief  Input Capture half complete callback in non-blocking mode
6184   * @param  htim TIM IC handle
6185   * @retval None
6186   */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)6187 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
6188 {
6189   /* Prevent unused argument(s) compilation warning */
6190   UNUSED(htim);
6191 
6192   /* NOTE : This function should not be modified, when the callback is needed,
6193             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
6194    */
6195 }
6196 
6197 /**
6198   * @brief  PWM Pulse finished callback in non-blocking mode
6199   * @param  htim TIM handle
6200   * @retval None
6201   */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)6202 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
6203 {
6204   /* Prevent unused argument(s) compilation warning */
6205   UNUSED(htim);
6206 
6207   /* NOTE : This function should not be modified, when the callback is needed,
6208             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
6209    */
6210 }
6211 
6212 /**
6213   * @brief  PWM Pulse finished half complete callback in non-blocking mode
6214   * @param  htim TIM handle
6215   * @retval None
6216   */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)6217 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
6218 {
6219   /* Prevent unused argument(s) compilation warning */
6220   UNUSED(htim);
6221 
6222   /* NOTE : This function should not be modified, when the callback is needed,
6223             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
6224    */
6225 }
6226 
6227 /**
6228   * @brief  Hall Trigger detection callback in non-blocking mode
6229   * @param  htim TIM handle
6230   * @retval None
6231   */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)6232 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
6233 {
6234   /* Prevent unused argument(s) compilation warning */
6235   UNUSED(htim);
6236 
6237   /* NOTE : This function should not be modified, when the callback is needed,
6238             the HAL_TIM_TriggerCallback could be implemented in the user file
6239    */
6240 }
6241 
6242 /**
6243   * @brief  Hall Trigger detection half complete callback in non-blocking mode
6244   * @param  htim TIM handle
6245   * @retval None
6246   */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)6247 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
6248 {
6249   /* Prevent unused argument(s) compilation warning */
6250   UNUSED(htim);
6251 
6252   /* NOTE : This function should not be modified, when the callback is needed,
6253             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
6254    */
6255 }
6256 
6257 /**
6258   * @brief  Timer error callback in non-blocking mode
6259   * @param  htim TIM handle
6260   * @retval None
6261   */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)6262 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
6263 {
6264   /* Prevent unused argument(s) compilation warning */
6265   UNUSED(htim);
6266 
6267   /* NOTE : This function should not be modified, when the callback is needed,
6268             the HAL_TIM_ErrorCallback could be implemented in the user file
6269    */
6270 }
6271 
6272 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6273 /**
6274   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
6275   * @param htim tim handle
6276   * @param CallbackID ID of the callback to be registered
6277   *        This parameter can be one of the following values:
6278   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6279   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6280   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6281   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6282   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6283   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6284   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6285   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6286   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6287   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6288   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6289   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6290   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6291   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6292   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6293   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6294   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6295   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6296   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6297   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6298   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6299   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6300   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6301   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6302   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6303   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6304   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6305   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6306   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6307   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6308   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6309   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6310   *          @param pCallback pointer to the callback function
6311   *          @retval status
6312   */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6313 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6314                                            pTIM_CallbackTypeDef pCallback)
6315 {
6316   HAL_StatusTypeDef status = HAL_OK;
6317 
6318   if (pCallback == NULL)
6319   {
6320     return HAL_ERROR;
6321   }
6322 
6323   if (htim->State == HAL_TIM_STATE_READY)
6324   {
6325     switch (CallbackID)
6326     {
6327       case HAL_TIM_BASE_MSPINIT_CB_ID :
6328         htim->Base_MspInitCallback                 = pCallback;
6329         break;
6330 
6331       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6332         htim->Base_MspDeInitCallback               = pCallback;
6333         break;
6334 
6335       case HAL_TIM_IC_MSPINIT_CB_ID :
6336         htim->IC_MspInitCallback                   = pCallback;
6337         break;
6338 
6339       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6340         htim->IC_MspDeInitCallback                 = pCallback;
6341         break;
6342 
6343       case HAL_TIM_OC_MSPINIT_CB_ID :
6344         htim->OC_MspInitCallback                   = pCallback;
6345         break;
6346 
6347       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6348         htim->OC_MspDeInitCallback                 = pCallback;
6349         break;
6350 
6351       case HAL_TIM_PWM_MSPINIT_CB_ID :
6352         htim->PWM_MspInitCallback                  = pCallback;
6353         break;
6354 
6355       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6356         htim->PWM_MspDeInitCallback                = pCallback;
6357         break;
6358 
6359       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6360         htim->OnePulse_MspInitCallback             = pCallback;
6361         break;
6362 
6363       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6364         htim->OnePulse_MspDeInitCallback           = pCallback;
6365         break;
6366 
6367       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6368         htim->Encoder_MspInitCallback              = pCallback;
6369         break;
6370 
6371       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6372         htim->Encoder_MspDeInitCallback            = pCallback;
6373         break;
6374 
6375       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6376         htim->HallSensor_MspInitCallback           = pCallback;
6377         break;
6378 
6379       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6380         htim->HallSensor_MspDeInitCallback         = pCallback;
6381         break;
6382 
6383       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6384         htim->PeriodElapsedCallback                = pCallback;
6385         break;
6386 
6387       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6388         htim->PeriodElapsedHalfCpltCallback        = pCallback;
6389         break;
6390 
6391       case HAL_TIM_TRIGGER_CB_ID :
6392         htim->TriggerCallback                      = pCallback;
6393         break;
6394 
6395       case HAL_TIM_TRIGGER_HALF_CB_ID :
6396         htim->TriggerHalfCpltCallback              = pCallback;
6397         break;
6398 
6399       case HAL_TIM_IC_CAPTURE_CB_ID :
6400         htim->IC_CaptureCallback                   = pCallback;
6401         break;
6402 
6403       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6404         htim->IC_CaptureHalfCpltCallback           = pCallback;
6405         break;
6406 
6407       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6408         htim->OC_DelayElapsedCallback              = pCallback;
6409         break;
6410 
6411       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6412         htim->PWM_PulseFinishedCallback            = pCallback;
6413         break;
6414 
6415       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6416         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
6417         break;
6418 
6419       case HAL_TIM_ERROR_CB_ID :
6420         htim->ErrorCallback                        = pCallback;
6421         break;
6422 
6423       case HAL_TIM_COMMUTATION_CB_ID :
6424         htim->CommutationCallback                  = pCallback;
6425         break;
6426 
6427       case HAL_TIM_COMMUTATION_HALF_CB_ID :
6428         htim->CommutationHalfCpltCallback          = pCallback;
6429         break;
6430 
6431       case HAL_TIM_BREAK_CB_ID :
6432         htim->BreakCallback                        = pCallback;
6433         break;
6434 
6435       case HAL_TIM_BREAK2_CB_ID :
6436         htim->Break2Callback                       = pCallback;
6437         break;
6438 
6439       case HAL_TIM_ENCODER_INDEX_CB_ID :
6440         htim->EncoderIndexCallback                 = pCallback;
6441         break;
6442 
6443       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6444         htim->DirectionChangeCallback              = pCallback;
6445         break;
6446 
6447       case HAL_TIM_INDEX_ERROR_CB_ID :
6448         htim->IndexErrorCallback                   = pCallback;
6449         break;
6450 
6451       case HAL_TIM_TRANSITION_ERROR_CB_ID :
6452         htim->TransitionErrorCallback              = pCallback;
6453         break;
6454 
6455       default :
6456         /* Return error status */
6457         status = HAL_ERROR;
6458         break;
6459     }
6460   }
6461   else if (htim->State == HAL_TIM_STATE_RESET)
6462   {
6463     switch (CallbackID)
6464     {
6465       case HAL_TIM_BASE_MSPINIT_CB_ID :
6466         htim->Base_MspInitCallback         = pCallback;
6467         break;
6468 
6469       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6470         htim->Base_MspDeInitCallback       = pCallback;
6471         break;
6472 
6473       case HAL_TIM_IC_MSPINIT_CB_ID :
6474         htim->IC_MspInitCallback           = pCallback;
6475         break;
6476 
6477       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6478         htim->IC_MspDeInitCallback         = pCallback;
6479         break;
6480 
6481       case HAL_TIM_OC_MSPINIT_CB_ID :
6482         htim->OC_MspInitCallback           = pCallback;
6483         break;
6484 
6485       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6486         htim->OC_MspDeInitCallback         = pCallback;
6487         break;
6488 
6489       case HAL_TIM_PWM_MSPINIT_CB_ID :
6490         htim->PWM_MspInitCallback          = pCallback;
6491         break;
6492 
6493       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6494         htim->PWM_MspDeInitCallback        = pCallback;
6495         break;
6496 
6497       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6498         htim->OnePulse_MspInitCallback     = pCallback;
6499         break;
6500 
6501       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6502         htim->OnePulse_MspDeInitCallback   = pCallback;
6503         break;
6504 
6505       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6506         htim->Encoder_MspInitCallback      = pCallback;
6507         break;
6508 
6509       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6510         htim->Encoder_MspDeInitCallback    = pCallback;
6511         break;
6512 
6513       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6514         htim->HallSensor_MspInitCallback   = pCallback;
6515         break;
6516 
6517       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6518         htim->HallSensor_MspDeInitCallback = pCallback;
6519         break;
6520 
6521       default :
6522         /* Return error status */
6523         status = HAL_ERROR;
6524         break;
6525     }
6526   }
6527   else
6528   {
6529     /* Return error status */
6530     status = HAL_ERROR;
6531   }
6532 
6533   return status;
6534 }
6535 
6536 /**
6537   * @brief  Unregister a TIM callback
6538   *         TIM callback is redirected to the weak predefined callback
6539   * @param htim tim handle
6540   * @param CallbackID ID of the callback to be unregistered
6541   *        This parameter can be one of the following values:
6542   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6543   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6544   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6545   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6546   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6547   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6548   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6549   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6550   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6551   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6552   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6553   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6554   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6555   *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6556   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6557   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6558   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6559   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6560   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6561   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6562   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6563   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6564   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6565   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6566   *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6567   *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6568   *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6569   *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6570   *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6571   *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6572   *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6573   *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6574   *          @retval status
6575   */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6576 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6577 {
6578   HAL_StatusTypeDef status = HAL_OK;
6579 
6580   if (htim->State == HAL_TIM_STATE_READY)
6581   {
6582     switch (CallbackID)
6583     {
6584       case HAL_TIM_BASE_MSPINIT_CB_ID :
6585         /* Legacy weak Base MspInit Callback */
6586         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
6587         break;
6588 
6589       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6590         /* Legacy weak Base Msp DeInit Callback */
6591         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
6592         break;
6593 
6594       case HAL_TIM_IC_MSPINIT_CB_ID :
6595         /* Legacy weak IC Msp Init Callback */
6596         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
6597         break;
6598 
6599       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6600         /* Legacy weak IC Msp DeInit Callback */
6601         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
6602         break;
6603 
6604       case HAL_TIM_OC_MSPINIT_CB_ID :
6605         /* Legacy weak OC Msp Init Callback */
6606         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
6607         break;
6608 
6609       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6610         /* Legacy weak OC Msp DeInit Callback */
6611         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
6612         break;
6613 
6614       case HAL_TIM_PWM_MSPINIT_CB_ID :
6615         /* Legacy weak PWM Msp Init Callback */
6616         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
6617         break;
6618 
6619       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6620         /* Legacy weak PWM Msp DeInit Callback */
6621         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
6622         break;
6623 
6624       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6625         /* Legacy weak One Pulse Msp Init Callback */
6626         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
6627         break;
6628 
6629       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6630         /* Legacy weak One Pulse Msp DeInit Callback */
6631         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
6632         break;
6633 
6634       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6635         /* Legacy weak Encoder Msp Init Callback */
6636         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
6637         break;
6638 
6639       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6640         /* Legacy weak Encoder Msp DeInit Callback */
6641         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
6642         break;
6643 
6644       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6645         /* Legacy weak Hall Sensor Msp Init Callback */
6646         htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
6647         break;
6648 
6649       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6650         /* Legacy weak Hall Sensor Msp DeInit Callback */
6651         htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
6652         break;
6653 
6654       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6655         /* Legacy weak Period Elapsed Callback */
6656         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
6657         break;
6658 
6659       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6660         /* Legacy weak Period Elapsed half complete Callback */
6661         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
6662         break;
6663 
6664       case HAL_TIM_TRIGGER_CB_ID :
6665         /* Legacy weak Trigger Callback */
6666         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
6667         break;
6668 
6669       case HAL_TIM_TRIGGER_HALF_CB_ID :
6670         /* Legacy weak Trigger half complete Callback */
6671         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
6672         break;
6673 
6674       case HAL_TIM_IC_CAPTURE_CB_ID :
6675         /* Legacy weak IC Capture Callback */
6676         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
6677         break;
6678 
6679       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6680         /* Legacy weak IC Capture half complete Callback */
6681         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
6682         break;
6683 
6684       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6685         /* Legacy weak OC Delay Elapsed Callback */
6686         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
6687         break;
6688 
6689       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6690         /* Legacy weak PWM Pulse Finished Callback */
6691         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
6692         break;
6693 
6694       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6695         /* Legacy weak PWM Pulse Finished half complete Callback */
6696         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6697         break;
6698 
6699       case HAL_TIM_ERROR_CB_ID :
6700         /* Legacy weak Error Callback */
6701         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
6702         break;
6703 
6704       case HAL_TIM_COMMUTATION_CB_ID :
6705         /* Legacy weak Commutation Callback */
6706         htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
6707         break;
6708 
6709       case HAL_TIM_COMMUTATION_HALF_CB_ID :
6710         /* Legacy weak Commutation half complete Callback */
6711         htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
6712         break;
6713 
6714       case HAL_TIM_BREAK_CB_ID :
6715         /* Legacy weak Break Callback */
6716         htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
6717         break;
6718 
6719       case HAL_TIM_BREAK2_CB_ID :
6720         /* Legacy weak Break2 Callback */
6721         htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
6722         break;
6723 
6724       case HAL_TIM_ENCODER_INDEX_CB_ID :
6725         /* Legacy weak Encoder Index Callback */
6726         htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
6727         break;
6728 
6729       case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6730         /* Legacy weak Direction Change Callback */
6731         htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
6732         break;
6733 
6734       case HAL_TIM_INDEX_ERROR_CB_ID :
6735         /* Legacy weak Index Error Callback */
6736         htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
6737         break;
6738 
6739       case HAL_TIM_TRANSITION_ERROR_CB_ID :
6740         /* Legacy weak Transition Error Callback */
6741         htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
6742         break;
6743 
6744       default :
6745         /* Return error status */
6746         status = HAL_ERROR;
6747         break;
6748     }
6749   }
6750   else if (htim->State == HAL_TIM_STATE_RESET)
6751   {
6752     switch (CallbackID)
6753     {
6754       case HAL_TIM_BASE_MSPINIT_CB_ID :
6755         /* Legacy weak Base MspInit Callback */
6756         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
6757         break;
6758 
6759       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6760         /* Legacy weak Base Msp DeInit Callback */
6761         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
6762         break;
6763 
6764       case HAL_TIM_IC_MSPINIT_CB_ID :
6765         /* Legacy weak IC Msp Init Callback */
6766         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
6767         break;
6768 
6769       case HAL_TIM_IC_MSPDEINIT_CB_ID :
6770         /* Legacy weak IC Msp DeInit Callback */
6771         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
6772         break;
6773 
6774       case HAL_TIM_OC_MSPINIT_CB_ID :
6775         /* Legacy weak OC Msp Init Callback */
6776         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
6777         break;
6778 
6779       case HAL_TIM_OC_MSPDEINIT_CB_ID :
6780         /* Legacy weak OC Msp DeInit Callback */
6781         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
6782         break;
6783 
6784       case HAL_TIM_PWM_MSPINIT_CB_ID :
6785         /* Legacy weak PWM Msp Init Callback */
6786         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
6787         break;
6788 
6789       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6790         /* Legacy weak PWM Msp DeInit Callback */
6791         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
6792         break;
6793 
6794       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6795         /* Legacy weak One Pulse Msp Init Callback */
6796         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
6797         break;
6798 
6799       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6800         /* Legacy weak One Pulse Msp DeInit Callback */
6801         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
6802         break;
6803 
6804       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6805         /* Legacy weak Encoder Msp Init Callback */
6806         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
6807         break;
6808 
6809       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6810         /* Legacy weak Encoder Msp DeInit Callback */
6811         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
6812         break;
6813 
6814       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6815         /* Legacy weak Hall Sensor Msp Init Callback */
6816         htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
6817         break;
6818 
6819       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6820         /* Legacy weak Hall Sensor Msp DeInit Callback */
6821         htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6822         break;
6823 
6824       default :
6825         /* Return error status */
6826         status = HAL_ERROR;
6827         break;
6828     }
6829   }
6830   else
6831   {
6832     /* Return error status */
6833     status = HAL_ERROR;
6834   }
6835 
6836   return status;
6837 }
6838 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6839 
6840 /**
6841   * @}
6842   */
6843 
6844 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6845   *  @brief   TIM Peripheral State functions
6846   *
6847 @verbatim
6848   ==============================================================================
6849                         ##### Peripheral State functions #####
6850   ==============================================================================
6851     [..]
6852     This subsection permits to get in run-time the status of the peripheral
6853     and the data flow.
6854 
6855 @endverbatim
6856   * @{
6857   */
6858 
6859 /**
6860   * @brief  Return the TIM Base handle state.
6861   * @param  htim TIM Base handle
6862   * @retval HAL state
6863   */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6864 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6865 {
6866   return htim->State;
6867 }
6868 
6869 /**
6870   * @brief  Return the TIM OC handle state.
6871   * @param  htim TIM Output Compare handle
6872   * @retval HAL state
6873   */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6874 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6875 {
6876   return htim->State;
6877 }
6878 
6879 /**
6880   * @brief  Return the TIM PWM handle state.
6881   * @param  htim TIM handle
6882   * @retval HAL state
6883   */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6884 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6885 {
6886   return htim->State;
6887 }
6888 
6889 /**
6890   * @brief  Return the TIM Input Capture handle state.
6891   * @param  htim TIM IC handle
6892   * @retval HAL state
6893   */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6894 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6895 {
6896   return htim->State;
6897 }
6898 
6899 /**
6900   * @brief  Return the TIM One Pulse Mode handle state.
6901   * @param  htim TIM OPM handle
6902   * @retval HAL state
6903   */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6904 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6905 {
6906   return htim->State;
6907 }
6908 
6909 /**
6910   * @brief  Return the TIM Encoder Mode handle state.
6911   * @param  htim TIM Encoder Interface handle
6912   * @retval HAL state
6913   */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6914 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6915 {
6916   return htim->State;
6917 }
6918 
6919 /**
6920   * @brief  Return the TIM Encoder Mode handle state.
6921   * @param  htim TIM handle
6922   * @retval Active channel
6923   */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6924 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6925 {
6926   return htim->Channel;
6927 }
6928 
6929 /**
6930   * @brief  Return actual state of the TIM channel.
6931   * @param  htim TIM handle
6932   * @param  Channel TIM Channel
6933   *          This parameter can be one of the following values:
6934   *            @arg TIM_CHANNEL_1: TIM Channel 1
6935   *            @arg TIM_CHANNEL_2: TIM Channel 2
6936   *            @arg TIM_CHANNEL_3: TIM Channel 3
6937   *            @arg TIM_CHANNEL_4: TIM Channel 4
6938   *            @arg TIM_CHANNEL_5: TIM Channel 5
6939   *            @arg TIM_CHANNEL_6: TIM Channel 6
6940   * @retval TIM Channel state
6941   */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6942 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
6943 {
6944   HAL_TIM_ChannelStateTypeDef channel_state;
6945 
6946   /* Check the parameters */
6947   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6948 
6949   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6950 
6951   return channel_state;
6952 }
6953 
6954 /**
6955   * @brief  Return actual state of a DMA burst operation.
6956   * @param  htim TIM handle
6957   * @retval DMA burst state
6958   */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6959 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6960 {
6961   /* Check the parameters */
6962   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6963 
6964   return htim->DMABurstState;
6965 }
6966 
6967 /**
6968   * @}
6969   */
6970 
6971 /**
6972   * @}
6973   */
6974 
6975 /** @defgroup TIM_Private_Functions TIM Private Functions
6976   * @{
6977   */
6978 
6979 /**
6980   * @brief  TIM DMA error callback
6981   * @param  hdma pointer to DMA handle.
6982   * @retval None
6983   */
TIM_DMAError(DMA_HandleTypeDef * hdma)6984 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6985 {
6986   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6987 
6988   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6989   {
6990     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6991     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6992   }
6993   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6994   {
6995     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6996     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6997   }
6998   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6999   {
7000     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7001     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7002   }
7003   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7004   {
7005     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7006     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7007   }
7008   else
7009   {
7010     htim->State = HAL_TIM_STATE_READY;
7011   }
7012 
7013 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7014   htim->ErrorCallback(htim);
7015 #else
7016   HAL_TIM_ErrorCallback(htim);
7017 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7018 
7019   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7020 }
7021 
7022 /**
7023   * @brief  TIM DMA Delay Pulse complete callback.
7024   * @param  hdma pointer to DMA handle.
7025   * @retval None
7026   */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)7027 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
7028 {
7029   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7030 
7031   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7032   {
7033     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7034   }
7035   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7036   {
7037     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7038   }
7039   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7040   {
7041     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7042   }
7043   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7044   {
7045     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7046   }
7047   else
7048   {
7049     /* nothing to do */
7050   }
7051 
7052 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7053   htim->PWM_PulseFinishedCallback(htim);
7054 #else
7055   HAL_TIM_PWM_PulseFinishedCallback(htim);
7056 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7057 
7058   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7059 }
7060 
7061 /**
7062   * @brief  TIM DMA Delay Pulse half complete callback.
7063   * @param  hdma pointer to DMA handle.
7064   * @retval None
7065   */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)7066 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
7067 {
7068   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7069 
7070   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7071   {
7072     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7073   }
7074   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7075   {
7076     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7077   }
7078   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7079   {
7080     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7081   }
7082   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7083   {
7084     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7085   }
7086   else
7087   {
7088     /* nothing to do */
7089   }
7090 
7091 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7092   htim->PWM_PulseFinishedHalfCpltCallback(htim);
7093 #else
7094   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
7095 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7096 
7097   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7098 }
7099 
7100 /**
7101   * @brief  TIM DMA Capture complete callback.
7102   * @param  hdma pointer to DMA handle.
7103   * @retval None
7104   */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)7105 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
7106 {
7107   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7108 
7109   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7110   {
7111     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7112   }
7113   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7114   {
7115     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7116   }
7117   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7118   {
7119     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7120   }
7121   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7122   {
7123     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7124   }
7125   else
7126   {
7127     /* nothing to do */
7128   }
7129 
7130 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7131   htim->IC_CaptureCallback(htim);
7132 #else
7133   HAL_TIM_IC_CaptureCallback(htim);
7134 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7135 
7136   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7137 }
7138 
7139 /**
7140   * @brief  TIM DMA Capture half complete callback.
7141   * @param  hdma pointer to DMA handle.
7142   * @retval None
7143   */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)7144 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
7145 {
7146   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7147 
7148   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7149   {
7150     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7151   }
7152   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7153   {
7154     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7155   }
7156   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7157   {
7158     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7159   }
7160   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7161   {
7162     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7163   }
7164   else
7165   {
7166     /* nothing to do */
7167   }
7168 
7169 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7170   htim->IC_CaptureHalfCpltCallback(htim);
7171 #else
7172   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
7173 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7174 
7175   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7176 }
7177 
7178 /**
7179   * @brief  TIM DMA Period Elapse complete callback.
7180   * @param  hdma pointer to DMA handle.
7181   * @retval None
7182   */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)7183 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
7184 {
7185   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7186 
7187 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7188   htim->PeriodElapsedCallback(htim);
7189 #else
7190   HAL_TIM_PeriodElapsedCallback(htim);
7191 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7192 }
7193 
7194 /**
7195   * @brief  TIM DMA Period Elapse half complete callback.
7196   * @param  hdma pointer to DMA handle.
7197   * @retval None
7198   */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)7199 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
7200 {
7201   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7202 
7203 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7204   htim->PeriodElapsedHalfCpltCallback(htim);
7205 #else
7206   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
7207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7208 }
7209 
7210 /**
7211   * @brief  TIM DMA Trigger callback.
7212   * @param  hdma pointer to DMA handle.
7213   * @retval None
7214   */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)7215 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
7216 {
7217   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7218 
7219 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7220   htim->TriggerCallback(htim);
7221 #else
7222   HAL_TIM_TriggerCallback(htim);
7223 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7224 }
7225 
7226 /**
7227   * @brief  TIM DMA Trigger half complete callback.
7228   * @param  hdma pointer to DMA handle.
7229   * @retval None
7230   */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)7231 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
7232 {
7233   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7234 
7235 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7236   htim->TriggerHalfCpltCallback(htim);
7237 #else
7238   HAL_TIM_TriggerHalfCpltCallback(htim);
7239 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7240 }
7241 
7242 /**
7243   * @brief  Time Base configuration
7244   * @param  TIMx TIM peripheral
7245   * @param  Structure TIM Base configuration structure
7246   * @retval None
7247   */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)7248 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
7249 {
7250   uint32_t tmpcr1;
7251   tmpcr1 = TIMx->CR1;
7252 
7253   /* Set TIM Time Base Unit parameters ---------------------------------------*/
7254   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
7255   {
7256     /* Select the Counter Mode */
7257     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
7258     tmpcr1 |= Structure->CounterMode;
7259   }
7260 
7261   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
7262   {
7263     /* Set the clock division */
7264     tmpcr1 &= ~TIM_CR1_CKD;
7265     tmpcr1 |= (uint32_t)Structure->ClockDivision;
7266   }
7267 
7268   /* Set the auto-reload preload */
7269   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
7270 
7271   TIMx->CR1 = tmpcr1;
7272 
7273   /* Set the Autoreload value */
7274   TIMx->ARR = (uint32_t)Structure->Period ;
7275 
7276   /* Set the Prescaler value */
7277   TIMx->PSC = Structure->Prescaler;
7278 
7279   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7280   {
7281     /* Set the Repetition Counter value */
7282     TIMx->RCR = Structure->RepetitionCounter;
7283   }
7284 
7285   /* Generate an update event to reload the Prescaler
7286      and the repetition counter (only for advanced timer) value immediately */
7287   TIMx->EGR = TIM_EGR_UG;
7288 }
7289 
7290 /**
7291   * @brief  Timer Output Compare 1 configuration
7292   * @param  TIMx to select the TIM peripheral
7293   * @param  OC_Config The output configuration structure
7294   * @retval None
7295   */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7296 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7297 {
7298   uint32_t tmpccmrx;
7299   uint32_t tmpccer;
7300   uint32_t tmpcr2;
7301 
7302   /* Get the TIMx CCER register value */
7303   tmpccer = TIMx->CCER;
7304 
7305   /* Disable the Channel 1: Reset the CC1E Bit */
7306   TIMx->CCER &= ~TIM_CCER_CC1E;
7307 
7308   /* Get the TIMx CR2 register value */
7309   tmpcr2 =  TIMx->CR2;
7310 
7311   /* Get the TIMx CCMR1 register value */
7312   tmpccmrx = TIMx->CCMR1;
7313 
7314   /* Reset the Output Compare Mode Bits */
7315   tmpccmrx &= ~TIM_CCMR1_OC1M;
7316   tmpccmrx &= ~TIM_CCMR1_CC1S;
7317   /* Select the Output Compare Mode */
7318   tmpccmrx |= OC_Config->OCMode;
7319 
7320   /* Reset the Output Polarity level */
7321   tmpccer &= ~TIM_CCER_CC1P;
7322   /* Set the Output Compare Polarity */
7323   tmpccer |= OC_Config->OCPolarity;
7324 
7325   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7326   {
7327     /* Check parameters */
7328     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7329 
7330     /* Reset the Output N Polarity level */
7331     tmpccer &= ~TIM_CCER_CC1NP;
7332     /* Set the Output N Polarity */
7333     tmpccer |= OC_Config->OCNPolarity;
7334     /* Reset the Output N State */
7335     tmpccer &= ~TIM_CCER_CC1NE;
7336   }
7337 
7338   if (IS_TIM_BREAK_INSTANCE(TIMx))
7339   {
7340     /* Check parameters */
7341     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7342     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7343 
7344     /* Reset the Output Compare and Output Compare N IDLE State */
7345     tmpcr2 &= ~TIM_CR2_OIS1;
7346     tmpcr2 &= ~TIM_CR2_OIS1N;
7347     /* Set the Output Idle state */
7348     tmpcr2 |= OC_Config->OCIdleState;
7349     /* Set the Output N Idle state */
7350     tmpcr2 |= OC_Config->OCNIdleState;
7351   }
7352 
7353   /* Write to TIMx CR2 */
7354   TIMx->CR2 = tmpcr2;
7355 
7356   /* Write to TIMx CCMR1 */
7357   TIMx->CCMR1 = tmpccmrx;
7358 
7359   /* Set the Capture Compare Register value */
7360   TIMx->CCR1 = OC_Config->Pulse;
7361 
7362   /* Write to TIMx CCER */
7363   TIMx->CCER = tmpccer;
7364 }
7365 
7366 /**
7367   * @brief  Timer Output Compare 2 configuration
7368   * @param  TIMx to select the TIM peripheral
7369   * @param  OC_Config The output configuration structure
7370   * @retval None
7371   */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7372 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7373 {
7374   uint32_t tmpccmrx;
7375   uint32_t tmpccer;
7376   uint32_t tmpcr2;
7377 
7378   /* Get the TIMx CCER register value */
7379   tmpccer = TIMx->CCER;
7380 
7381   /* Disable the Channel 2: Reset the CC2E Bit */
7382   TIMx->CCER &= ~TIM_CCER_CC2E;
7383 
7384   /* Get the TIMx CR2 register value */
7385   tmpcr2 =  TIMx->CR2;
7386 
7387   /* Get the TIMx CCMR1 register value */
7388   tmpccmrx = TIMx->CCMR1;
7389 
7390   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7391   tmpccmrx &= ~TIM_CCMR1_OC2M;
7392   tmpccmrx &= ~TIM_CCMR1_CC2S;
7393 
7394   /* Select the Output Compare Mode */
7395   tmpccmrx |= (OC_Config->OCMode << 8U);
7396 
7397   /* Reset the Output Polarity level */
7398   tmpccer &= ~TIM_CCER_CC2P;
7399   /* Set the Output Compare Polarity */
7400   tmpccer |= (OC_Config->OCPolarity << 4U);
7401 
7402   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7403   {
7404     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7405 
7406     /* Reset the Output N Polarity level */
7407     tmpccer &= ~TIM_CCER_CC2NP;
7408     /* Set the Output N Polarity */
7409     tmpccer |= (OC_Config->OCNPolarity << 4U);
7410     /* Reset the Output N State */
7411     tmpccer &= ~TIM_CCER_CC2NE;
7412 
7413   }
7414 
7415   if (IS_TIM_BREAK_INSTANCE(TIMx))
7416   {
7417     /* Check parameters */
7418     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7419     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7420 
7421     /* Reset the Output Compare and Output Compare N IDLE State */
7422     tmpcr2 &= ~TIM_CR2_OIS2;
7423     tmpcr2 &= ~TIM_CR2_OIS2N;
7424     /* Set the Output Idle state */
7425     tmpcr2 |= (OC_Config->OCIdleState << 2U);
7426     /* Set the Output N Idle state */
7427     tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7428   }
7429 
7430   /* Write to TIMx CR2 */
7431   TIMx->CR2 = tmpcr2;
7432 
7433   /* Write to TIMx CCMR1 */
7434   TIMx->CCMR1 = tmpccmrx;
7435 
7436   /* Set the Capture Compare Register value */
7437   TIMx->CCR2 = OC_Config->Pulse;
7438 
7439   /* Write to TIMx CCER */
7440   TIMx->CCER = tmpccer;
7441 }
7442 
7443 /**
7444   * @brief  Timer Output Compare 3 configuration
7445   * @param  TIMx to select the TIM peripheral
7446   * @param  OC_Config The output configuration structure
7447   * @retval None
7448   */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7449 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7450 {
7451   uint32_t tmpccmrx;
7452   uint32_t tmpccer;
7453   uint32_t tmpcr2;
7454 
7455   /* Get the TIMx CCER register value */
7456   tmpccer = TIMx->CCER;
7457 
7458   /* Disable the Channel 3: Reset the CC2E Bit */
7459   TIMx->CCER &= ~TIM_CCER_CC3E;
7460 
7461   /* Get the TIMx CR2 register value */
7462   tmpcr2 =  TIMx->CR2;
7463 
7464   /* Get the TIMx CCMR2 register value */
7465   tmpccmrx = TIMx->CCMR2;
7466 
7467   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7468   tmpccmrx &= ~TIM_CCMR2_OC3M;
7469   tmpccmrx &= ~TIM_CCMR2_CC3S;
7470   /* Select the Output Compare Mode */
7471   tmpccmrx |= OC_Config->OCMode;
7472 
7473   /* Reset the Output Polarity level */
7474   tmpccer &= ~TIM_CCER_CC3P;
7475   /* Set the Output Compare Polarity */
7476   tmpccer |= (OC_Config->OCPolarity << 8U);
7477 
7478   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7479   {
7480     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7481 
7482     /* Reset the Output N Polarity level */
7483     tmpccer &= ~TIM_CCER_CC3NP;
7484     /* Set the Output N Polarity */
7485     tmpccer |= (OC_Config->OCNPolarity << 8U);
7486     /* Reset the Output N State */
7487     tmpccer &= ~TIM_CCER_CC3NE;
7488   }
7489 
7490   if (IS_TIM_BREAK_INSTANCE(TIMx))
7491   {
7492     /* Check parameters */
7493     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7494     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7495 
7496     /* Reset the Output Compare and Output Compare N IDLE State */
7497     tmpcr2 &= ~TIM_CR2_OIS3;
7498     tmpcr2 &= ~TIM_CR2_OIS3N;
7499     /* Set the Output Idle state */
7500     tmpcr2 |= (OC_Config->OCIdleState << 4U);
7501     /* Set the Output N Idle state */
7502     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7503   }
7504 
7505   /* Write to TIMx CR2 */
7506   TIMx->CR2 = tmpcr2;
7507 
7508   /* Write to TIMx CCMR2 */
7509   TIMx->CCMR2 = tmpccmrx;
7510 
7511   /* Set the Capture Compare Register value */
7512   TIMx->CCR3 = OC_Config->Pulse;
7513 
7514   /* Write to TIMx CCER */
7515   TIMx->CCER = tmpccer;
7516 }
7517 
7518 /**
7519   * @brief  Timer Output Compare 4 configuration
7520   * @param  TIMx to select the TIM peripheral
7521   * @param  OC_Config The output configuration structure
7522   * @retval None
7523   */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7524 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7525 {
7526   uint32_t tmpccmrx;
7527   uint32_t tmpccer;
7528   uint32_t tmpcr2;
7529 
7530   /* Get the TIMx CCER register value */
7531   tmpccer = TIMx->CCER;
7532 
7533   /* Disable the Channel 4: Reset the CC4E Bit */
7534   TIMx->CCER &= ~TIM_CCER_CC4E;
7535 
7536   /* Get the TIMx CR2 register value */
7537   tmpcr2 =  TIMx->CR2;
7538 
7539   /* Get the TIMx CCMR2 register value */
7540   tmpccmrx = TIMx->CCMR2;
7541 
7542   /* Reset the Output Compare mode and Capture/Compare selection Bits */
7543   tmpccmrx &= ~TIM_CCMR2_OC4M;
7544   tmpccmrx &= ~TIM_CCMR2_CC4S;
7545 
7546   /* Select the Output Compare Mode */
7547   tmpccmrx |= (OC_Config->OCMode << 8U);
7548 
7549   /* Reset the Output Polarity level */
7550   tmpccer &= ~TIM_CCER_CC4P;
7551   /* Set the Output Compare Polarity */
7552   tmpccer |= (OC_Config->OCPolarity << 12U);
7553 
7554   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7555   {
7556     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7557 
7558     /* Reset the Output N Polarity level */
7559     tmpccer &= ~TIM_CCER_CC4NP;
7560     /* Set the Output N Polarity */
7561     tmpccer |= (OC_Config->OCNPolarity << 12U);
7562     /* Reset the Output N State */
7563     tmpccer &= ~TIM_CCER_CC4NE;
7564   }
7565 
7566   if (IS_TIM_BREAK_INSTANCE(TIMx))
7567   {
7568     /* Check parameters */
7569     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7570     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7571 
7572     /* Reset the Output Compare IDLE State */
7573     tmpcr2 &= ~TIM_CR2_OIS4;
7574     /* Reset the Output Compare N IDLE State */
7575     tmpcr2 &= ~TIM_CR2_OIS4N;
7576 
7577     /* Set the Output Idle state */
7578     tmpcr2 |= (OC_Config->OCIdleState << 6U);
7579     /* Set the Output N Idle state */
7580     tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7581   }
7582 
7583   /* Write to TIMx CR2 */
7584   TIMx->CR2 = tmpcr2;
7585 
7586   /* Write to TIMx CCMR2 */
7587   TIMx->CCMR2 = tmpccmrx;
7588 
7589   /* Set the Capture Compare Register value */
7590   TIMx->CCR4 = OC_Config->Pulse;
7591 
7592   /* Write to TIMx CCER */
7593   TIMx->CCER = tmpccer;
7594 }
7595 
7596 /**
7597   * @brief  Timer Output Compare 5 configuration
7598   * @param  TIMx to select the TIM peripheral
7599   * @param  OC_Config The output configuration structure
7600   * @retval None
7601   */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7602 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7603                               const TIM_OC_InitTypeDef *OC_Config)
7604 {
7605   uint32_t tmpccmrx;
7606   uint32_t tmpccer;
7607   uint32_t tmpcr2;
7608 
7609   /* Get the TIMx CCER register value */
7610   tmpccer = TIMx->CCER;
7611 
7612   /* Disable the output: Reset the CCxE Bit */
7613   TIMx->CCER &= ~TIM_CCER_CC5E;
7614 
7615   /* Get the TIMx CR2 register value */
7616   tmpcr2 =  TIMx->CR2;
7617   /* Get the TIMx CCMR1 register value */
7618   tmpccmrx = TIMx->CCMR3;
7619 
7620   /* Reset the Output Compare Mode Bits */
7621   tmpccmrx &= ~(TIM_CCMR3_OC5M);
7622   /* Select the Output Compare Mode */
7623   tmpccmrx |= OC_Config->OCMode;
7624 
7625   /* Reset the Output Polarity level */
7626   tmpccer &= ~TIM_CCER_CC5P;
7627   /* Set the Output Compare Polarity */
7628   tmpccer |= (OC_Config->OCPolarity << 16U);
7629 
7630   if (IS_TIM_BREAK_INSTANCE(TIMx))
7631   {
7632     /* Reset the Output Compare IDLE State */
7633     tmpcr2 &= ~TIM_CR2_OIS5;
7634     /* Set the Output Idle state */
7635     tmpcr2 |= (OC_Config->OCIdleState << 8U);
7636   }
7637   /* Write to TIMx CR2 */
7638   TIMx->CR2 = tmpcr2;
7639 
7640   /* Write to TIMx CCMR3 */
7641   TIMx->CCMR3 = tmpccmrx;
7642 
7643   /* Set the Capture Compare Register value */
7644   TIMx->CCR5 = OC_Config->Pulse;
7645 
7646   /* Write to TIMx CCER */
7647   TIMx->CCER = tmpccer;
7648 }
7649 
7650 /**
7651   * @brief  Timer Output Compare 6 configuration
7652   * @param  TIMx to select the TIM peripheral
7653   * @param  OC_Config The output configuration structure
7654   * @retval None
7655   */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7656 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7657                               const TIM_OC_InitTypeDef *OC_Config)
7658 {
7659   uint32_t tmpccmrx;
7660   uint32_t tmpccer;
7661   uint32_t tmpcr2;
7662 
7663   /* Get the TIMx CCER register value */
7664   tmpccer = TIMx->CCER;
7665 
7666   /* Disable the output: Reset the CCxE Bit */
7667   TIMx->CCER &= ~TIM_CCER_CC6E;
7668 
7669   /* Get the TIMx CR2 register value */
7670   tmpcr2 =  TIMx->CR2;
7671   /* Get the TIMx CCMR1 register value */
7672   tmpccmrx = TIMx->CCMR3;
7673 
7674   /* Reset the Output Compare Mode Bits */
7675   tmpccmrx &= ~(TIM_CCMR3_OC6M);
7676   /* Select the Output Compare Mode */
7677   tmpccmrx |= (OC_Config->OCMode << 8U);
7678 
7679   /* Reset the Output Polarity level */
7680   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7681   /* Set the Output Compare Polarity */
7682   tmpccer |= (OC_Config->OCPolarity << 20U);
7683 
7684   if (IS_TIM_BREAK_INSTANCE(TIMx))
7685   {
7686     /* Reset the Output Compare IDLE State */
7687     tmpcr2 &= ~TIM_CR2_OIS6;
7688     /* Set the Output Idle state */
7689     tmpcr2 |= (OC_Config->OCIdleState << 10U);
7690   }
7691 
7692   /* Write to TIMx CR2 */
7693   TIMx->CR2 = tmpcr2;
7694 
7695   /* Write to TIMx CCMR3 */
7696   TIMx->CCMR3 = tmpccmrx;
7697 
7698   /* Set the Capture Compare Register value */
7699   TIMx->CCR6 = OC_Config->Pulse;
7700 
7701   /* Write to TIMx CCER */
7702   TIMx->CCER = tmpccer;
7703 }
7704 
7705 /**
7706   * @brief  Slave Timer configuration function
7707   * @param  htim TIM handle
7708   * @param  sSlaveConfig Slave timer configuration
7709   * @retval None
7710   */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7711 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7712                                                   const TIM_SlaveConfigTypeDef *sSlaveConfig)
7713 {
7714   HAL_StatusTypeDef status = HAL_OK;
7715   uint32_t tmpsmcr;
7716   uint32_t tmpccmr1;
7717   uint32_t tmpccer;
7718 
7719   /* Get the TIMx SMCR register value */
7720   tmpsmcr = htim->Instance->SMCR;
7721 
7722   /* Reset the Trigger Selection Bits */
7723   tmpsmcr &= ~TIM_SMCR_TS;
7724   /* Set the Input Trigger source */
7725   tmpsmcr |= sSlaveConfig->InputTrigger;
7726 
7727   /* Reset the slave mode Bits */
7728   tmpsmcr &= ~TIM_SMCR_SMS;
7729   /* Set the slave mode */
7730   tmpsmcr |= sSlaveConfig->SlaveMode;
7731 
7732   /* Write to TIMx SMCR */
7733   htim->Instance->SMCR = tmpsmcr;
7734 
7735   /* Configure the trigger prescaler, filter, and polarity */
7736   switch (sSlaveConfig->InputTrigger)
7737   {
7738     case TIM_TS_ETRF:
7739     {
7740       /* Check the parameters */
7741       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7742       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7743       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7744       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7745       /* Configure the ETR Trigger source */
7746       TIM_ETR_SetConfig(htim->Instance,
7747                         sSlaveConfig->TriggerPrescaler,
7748                         sSlaveConfig->TriggerPolarity,
7749                         sSlaveConfig->TriggerFilter);
7750       break;
7751     }
7752 
7753     case TIM_TS_TI1F_ED:
7754     {
7755       /* Check the parameters */
7756       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7757       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7758 
7759       if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
7760           (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7761       {
7762         return HAL_ERROR;
7763       }
7764 
7765       /* Disable the Channel 1: Reset the CC1E Bit */
7766       tmpccer = htim->Instance->CCER;
7767       htim->Instance->CCER &= ~TIM_CCER_CC1E;
7768       tmpccmr1 = htim->Instance->CCMR1;
7769 
7770       /* Set the filter */
7771       tmpccmr1 &= ~TIM_CCMR1_IC1F;
7772       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7773 
7774       /* Write to TIMx CCMR1 and CCER registers */
7775       htim->Instance->CCMR1 = tmpccmr1;
7776       htim->Instance->CCER = tmpccer;
7777       break;
7778     }
7779 
7780     case TIM_TS_TI1FP1:
7781     {
7782       /* Check the parameters */
7783       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7784       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7785       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7786 
7787       /* Configure TI1 Filter and Polarity */
7788       TIM_TI1_ConfigInputStage(htim->Instance,
7789                                sSlaveConfig->TriggerPolarity,
7790                                sSlaveConfig->TriggerFilter);
7791       break;
7792     }
7793 
7794     case TIM_TS_TI2FP2:
7795     {
7796       /* Check the parameters */
7797       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7798       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7799       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7800 
7801       /* Configure TI2 Filter and Polarity */
7802       TIM_TI2_ConfigInputStage(htim->Instance,
7803                                sSlaveConfig->TriggerPolarity,
7804                                sSlaveConfig->TriggerFilter);
7805       break;
7806     }
7807 
7808     case TIM_TS_ITR0:
7809     case TIM_TS_ITR1:
7810     case TIM_TS_ITR2:
7811     case TIM_TS_ITR7:
7812     case TIM_TS_ITR8:
7813     {
7814       /* Check the parameter */
7815       assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7816       break;
7817     }
7818 
7819     default:
7820       status = HAL_ERROR;
7821       break;
7822   }
7823 
7824   return status;
7825 }
7826 
7827 /**
7828   * @brief  Configure the TI1 as Input.
7829   * @param  TIMx to select the TIM peripheral.
7830   * @param  TIM_ICPolarity The Input Polarity.
7831   *          This parameter can be one of the following values:
7832   *            @arg TIM_ICPOLARITY_RISING
7833   *            @arg TIM_ICPOLARITY_FALLING
7834   *            @arg TIM_ICPOLARITY_BOTHEDGE
7835   * @param  TIM_ICSelection specifies the input to be used.
7836   *          This parameter can be one of the following values:
7837   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7838   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7839   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7840   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7841   *          This parameter must be a value between 0x00 and 0x0F.
7842   * @retval None
7843   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7844   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7845   *        protected against un-initialized filter and polarity values.
7846   */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7847 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7848                        uint32_t TIM_ICFilter)
7849 {
7850   uint32_t tmpccmr1;
7851   uint32_t tmpccer;
7852 
7853   /* Disable the Channel 1: Reset the CC1E Bit */
7854   tmpccer = TIMx->CCER;
7855   TIMx->CCER &= ~TIM_CCER_CC1E;
7856   tmpccmr1 = TIMx->CCMR1;
7857 
7858   /* Select the Input */
7859   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7860   {
7861     tmpccmr1 &= ~TIM_CCMR1_CC1S;
7862     tmpccmr1 |= TIM_ICSelection;
7863   }
7864   else
7865   {
7866     tmpccmr1 |= TIM_CCMR1_CC1S_0;
7867   }
7868 
7869   /* Set the filter */
7870   tmpccmr1 &= ~TIM_CCMR1_IC1F;
7871   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7872 
7873   /* Select the Polarity and set the CC1E Bit */
7874   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7875   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7876 
7877   /* Write to TIMx CCMR1 and CCER registers */
7878   TIMx->CCMR1 = tmpccmr1;
7879   TIMx->CCER = tmpccer;
7880 }
7881 
7882 /**
7883   * @brief  Configure the Polarity and Filter for TI1.
7884   * @param  TIMx to select the TIM peripheral.
7885   * @param  TIM_ICPolarity The Input Polarity.
7886   *          This parameter can be one of the following values:
7887   *            @arg TIM_ICPOLARITY_RISING
7888   *            @arg TIM_ICPOLARITY_FALLING
7889   *            @arg TIM_ICPOLARITY_BOTHEDGE
7890   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7891   *          This parameter must be a value between 0x00 and 0x0F.
7892   * @retval None
7893   */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7894 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7895 {
7896   uint32_t tmpccmr1;
7897   uint32_t tmpccer;
7898 
7899   /* Disable the Channel 1: Reset the CC1E Bit */
7900   tmpccer = TIMx->CCER;
7901   TIMx->CCER &= ~TIM_CCER_CC1E;
7902   tmpccmr1 = TIMx->CCMR1;
7903 
7904   /* Set the filter */
7905   tmpccmr1 &= ~TIM_CCMR1_IC1F;
7906   tmpccmr1 |= (TIM_ICFilter << 4U);
7907 
7908   /* Select the Polarity and set the CC1E Bit */
7909   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7910   tmpccer |= TIM_ICPolarity;
7911 
7912   /* Write to TIMx CCMR1 and CCER registers */
7913   TIMx->CCMR1 = tmpccmr1;
7914   TIMx->CCER = tmpccer;
7915 }
7916 
7917 /**
7918   * @brief  Configure the TI2 as Input.
7919   * @param  TIMx to select the TIM peripheral
7920   * @param  TIM_ICPolarity The Input Polarity.
7921   *          This parameter can be one of the following values:
7922   *            @arg TIM_ICPOLARITY_RISING
7923   *            @arg TIM_ICPOLARITY_FALLING
7924   *            @arg TIM_ICPOLARITY_BOTHEDGE
7925   * @param  TIM_ICSelection specifies the input to be used.
7926   *          This parameter can be one of the following values:
7927   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7928   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7929   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7930   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7931   *          This parameter must be a value between 0x00 and 0x0F.
7932   * @retval None
7933   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7934   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7935   *        protected against un-initialized filter and polarity values.
7936   */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7937 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7938                               uint32_t TIM_ICFilter)
7939 {
7940   uint32_t tmpccmr1;
7941   uint32_t tmpccer;
7942 
7943   /* Disable the Channel 2: Reset the CC2E Bit */
7944   tmpccer = TIMx->CCER;
7945   TIMx->CCER &= ~TIM_CCER_CC2E;
7946   tmpccmr1 = TIMx->CCMR1;
7947 
7948   /* Select the Input */
7949   tmpccmr1 &= ~TIM_CCMR1_CC2S;
7950   tmpccmr1 |= (TIM_ICSelection << 8U);
7951 
7952   /* Set the filter */
7953   tmpccmr1 &= ~TIM_CCMR1_IC2F;
7954   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7955 
7956   /* Select the Polarity and set the CC2E Bit */
7957   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7958   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7959 
7960   /* Write to TIMx CCMR1 and CCER registers */
7961   TIMx->CCMR1 = tmpccmr1 ;
7962   TIMx->CCER = tmpccer;
7963 }
7964 
7965 /**
7966   * @brief  Configure the Polarity and Filter for TI2.
7967   * @param  TIMx to select the TIM peripheral.
7968   * @param  TIM_ICPolarity The Input Polarity.
7969   *          This parameter can be one of the following values:
7970   *            @arg TIM_ICPOLARITY_RISING
7971   *            @arg TIM_ICPOLARITY_FALLING
7972   *            @arg TIM_ICPOLARITY_BOTHEDGE
7973   * @param  TIM_ICFilter Specifies the Input Capture Filter.
7974   *          This parameter must be a value between 0x00 and 0x0F.
7975   * @retval None
7976   */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7977 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7978 {
7979   uint32_t tmpccmr1;
7980   uint32_t tmpccer;
7981 
7982   /* Disable the Channel 2: Reset the CC2E Bit */
7983   tmpccer = TIMx->CCER;
7984   TIMx->CCER &= ~TIM_CCER_CC2E;
7985   tmpccmr1 = TIMx->CCMR1;
7986 
7987   /* Set the filter */
7988   tmpccmr1 &= ~TIM_CCMR1_IC2F;
7989   tmpccmr1 |= (TIM_ICFilter << 12U);
7990 
7991   /* Select the Polarity and set the CC2E Bit */
7992   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7993   tmpccer |= (TIM_ICPolarity << 4U);
7994 
7995   /* Write to TIMx CCMR1 and CCER registers */
7996   TIMx->CCMR1 = tmpccmr1 ;
7997   TIMx->CCER = tmpccer;
7998 }
7999 
8000 /**
8001   * @brief  Configure the TI3 as Input.
8002   * @param  TIMx to select the TIM peripheral
8003   * @param  TIM_ICPolarity The Input Polarity.
8004   *          This parameter can be one of the following values:
8005   *            @arg TIM_ICPOLARITY_RISING
8006   *            @arg TIM_ICPOLARITY_FALLING
8007   *            @arg TIM_ICPOLARITY_BOTHEDGE
8008   * @param  TIM_ICSelection specifies the input to be used.
8009   *          This parameter can be one of the following values:
8010   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
8011   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
8012   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
8013   * @param  TIM_ICFilter Specifies the Input Capture Filter.
8014   *          This parameter must be a value between 0x00 and 0x0F.
8015   * @retval None
8016   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
8017   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8018   *        protected against un-initialized filter and polarity values.
8019   */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8020 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8021                               uint32_t TIM_ICFilter)
8022 {
8023   uint32_t tmpccmr2;
8024   uint32_t tmpccer;
8025 
8026   /* Disable the Channel 3: Reset the CC3E Bit */
8027   tmpccer = TIMx->CCER;
8028   TIMx->CCER &= ~TIM_CCER_CC3E;
8029   tmpccmr2 = TIMx->CCMR2;
8030 
8031   /* Select the Input */
8032   tmpccmr2 &= ~TIM_CCMR2_CC3S;
8033   tmpccmr2 |= TIM_ICSelection;
8034 
8035   /* Set the filter */
8036   tmpccmr2 &= ~TIM_CCMR2_IC3F;
8037   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
8038 
8039   /* Select the Polarity and set the CC3E Bit */
8040   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
8041   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
8042 
8043   /* Write to TIMx CCMR2 and CCER registers */
8044   TIMx->CCMR2 = tmpccmr2;
8045   TIMx->CCER = tmpccer;
8046 }
8047 
8048 /**
8049   * @brief  Configure the TI4 as Input.
8050   * @param  TIMx to select the TIM peripheral
8051   * @param  TIM_ICPolarity The Input Polarity.
8052   *          This parameter can be one of the following values:
8053   *            @arg TIM_ICPOLARITY_RISING
8054   *            @arg TIM_ICPOLARITY_FALLING
8055   *            @arg TIM_ICPOLARITY_BOTHEDGE
8056   * @param  TIM_ICSelection specifies the input to be used.
8057   *          This parameter can be one of the following values:
8058   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
8059   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
8060   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
8061   * @param  TIM_ICFilter Specifies the Input Capture Filter.
8062   *          This parameter must be a value between 0x00 and 0x0F.
8063   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
8064   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8065   *        protected against un-initialized filter and polarity values.
8066   * @retval None
8067   */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8068 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8069                               uint32_t TIM_ICFilter)
8070 {
8071   uint32_t tmpccmr2;
8072   uint32_t tmpccer;
8073 
8074   /* Disable the Channel 4: Reset the CC4E Bit */
8075   tmpccer = TIMx->CCER;
8076   TIMx->CCER &= ~TIM_CCER_CC4E;
8077   tmpccmr2 = TIMx->CCMR2;
8078 
8079   /* Select the Input */
8080   tmpccmr2 &= ~TIM_CCMR2_CC4S;
8081   tmpccmr2 |= (TIM_ICSelection << 8U);
8082 
8083   /* Set the filter */
8084   tmpccmr2 &= ~TIM_CCMR2_IC4F;
8085   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
8086 
8087   /* Select the Polarity and set the CC4E Bit */
8088   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
8089   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
8090 
8091   /* Write to TIMx CCMR2 and CCER registers */
8092   TIMx->CCMR2 = tmpccmr2;
8093   TIMx->CCER = tmpccer ;
8094 }
8095 
8096 /**
8097   * @brief  Selects the Input Trigger source
8098   * @param  TIMx to select the TIM peripheral
8099   * @param  InputTriggerSource The Input Trigger source.
8100   *          This parameter can be one of the following values:
8101   *            @arg TIM_TS_ITR0: Internal Trigger 0
8102   *            @arg TIM_TS_ITR1: Internal Trigger 1
8103   *            @arg TIM_TS_ITR2: Internal Trigger 2
8104   *            @arg TIM_TS_ITR7: Internal Trigger 7
8105   *            @arg TIM_TS_ITR8: Internal Trigger 8
8106   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
8107   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
8108   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
8109   *            @arg TIM_TS_ETRF: External Trigger input
8110   * @retval None
8111   */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)8112 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
8113 {
8114   uint32_t tmpsmcr;
8115 
8116   /* Get the TIMx SMCR register value */
8117   tmpsmcr = TIMx->SMCR;
8118   /* Reset the TS Bits */
8119   tmpsmcr &= ~TIM_SMCR_TS;
8120   /* Set the Input Trigger source and the slave mode*/
8121   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8122   /* Write to TIMx SMCR */
8123   TIMx->SMCR = tmpsmcr;
8124 }
8125 /**
8126   * @brief  Configures the TIMx External Trigger (ETR).
8127   * @param  TIMx to select the TIM peripheral
8128   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
8129   *          This parameter can be one of the following values:
8130   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
8131   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
8132   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
8133   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
8134   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
8135   *          This parameter can be one of the following values:
8136   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
8137   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
8138   * @param  ExtTRGFilter External Trigger Filter.
8139   *          This parameter must be a value between 0x00 and 0x0F
8140   * @retval None
8141   */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)8142 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
8143                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
8144 {
8145   uint32_t tmpsmcr;
8146 
8147   tmpsmcr = TIMx->SMCR;
8148 
8149   /* Reset the ETR Bits */
8150   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8151 
8152   /* Set the Prescaler, the Filter value and the Polarity */
8153   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8154 
8155   /* Write to TIMx SMCR */
8156   TIMx->SMCR = tmpsmcr;
8157 }
8158 
8159 /**
8160   * @brief  Enables or disables the TIM Capture Compare Channel x.
8161   * @param  TIMx to select the TIM peripheral
8162   * @param  Channel specifies the TIM Channel
8163   *          This parameter can be one of the following values:
8164   *            @arg TIM_CHANNEL_1: TIM Channel 1
8165   *            @arg TIM_CHANNEL_2: TIM Channel 2
8166   *            @arg TIM_CHANNEL_3: TIM Channel 3
8167   *            @arg TIM_CHANNEL_4: TIM Channel 4
8168   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
8169   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
8170   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
8171   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
8172   * @retval None
8173   */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)8174 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
8175 {
8176   uint32_t tmp;
8177 
8178   /* Check the parameters */
8179   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
8180   assert_param(IS_TIM_CHANNELS(Channel));
8181 
8182   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8183 
8184   /* Reset the CCxE Bit */
8185   TIMx->CCER &= ~tmp;
8186 
8187   /* Set or reset the CCxE Bit */
8188   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8189 }
8190 
8191 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
8192 /**
8193   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
8194   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
8195   *                the configuration information for TIM module.
8196   * @retval None
8197   */
TIM_ResetCallback(TIM_HandleTypeDef * htim)8198 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
8199 {
8200   /* Reset the TIM callback to the legacy weak callbacks */
8201   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
8202   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
8203   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
8204   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
8205   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
8206   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
8207   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
8208   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
8209   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
8210   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
8211   htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
8212   htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
8213   htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
8214   htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
8215   htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
8216   htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
8217   htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
8218   htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
8219 }
8220 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
8221 
8222 /**
8223   * @}
8224   */
8225 
8226 #endif /* HAL_TIM_MODULE_ENABLED */
8227 /**
8228   * @}
8229   */
8230 
8231 /**
8232   * @}
8233   */
8234