1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2022 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
88 to use the Timer to generate an Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157 (+) EncoderIndexCallback : TIM Encoder Index Callback.
158 (+) DirectionChangeCallback : TIM Direction Change Callback
159 (+) IndexErrorCallback : TIM Index Error Callback.
160 (+) TransitionErrorCallback : TIM Transition Error Callback
161
162 [..]
163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
164 all interrupt callbacks are set to the corresponding weak functions:
165 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
166
167 [..]
168 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
169 functionalities in the Init / DeInit only when these callbacks are null
170 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
171 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
172
173 [..]
174 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
175 Exception done MspInit / MspDeInit that can be registered / unregistered
176 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
177 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
178 In that case first register the MspInit/MspDeInit user callbacks
179 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
180
181 [..]
182 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
183 not defined, the callback registration feature is not available and all callbacks
184 are set to the corresponding weak functions.
185
186 @endverbatim
187 ******************************************************************************
188 */
189
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32h5xx_hal.h"
192
193 /** @addtogroup STM32H5xx_HAL_Driver
194 * @{
195 */
196
197 /** @defgroup TIM TIM
198 * @brief TIM HAL module driver
199 * @{
200 */
201
202 #ifdef HAL_TIM_MODULE_ENABLED
203
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 /** @addtogroup TIM_Private_Constants
207 * @{
208 */
209 #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
210
211 /**
212 * @}
213 */
214 /* Private macros ------------------------------------------------------------*/
215 /* Private variables ---------------------------------------------------------*/
216 /* Private function prototypes -----------------------------------------------*/
217 /** @addtogroup TIM_Private_Functions
218 * @{
219 */
220 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
222 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
223 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
224 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
225 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
226 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
227 uint32_t TIM_ICFilter);
228 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
229 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
230 uint32_t TIM_ICFilter);
231 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
232 uint32_t TIM_ICFilter);
233 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
234 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
235 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
236 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
237 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
238 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
240 const TIM_SlaveConfigTypeDef *sSlaveConfig);
241 /**
242 * @}
243 */
244 /* Exported functions --------------------------------------------------------*/
245
246 /** @defgroup TIM_Exported_Functions TIM Exported Functions
247 * @{
248 */
249
250 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
251 * @brief Time Base functions
252 *
253 @verbatim
254 ==============================================================================
255 ##### Time Base functions #####
256 ==============================================================================
257 [..]
258 This section provides functions allowing to:
259 (+) Initialize and configure the TIM base.
260 (+) De-initialize the TIM base.
261 (+) Start the Time Base.
262 (+) Stop the Time Base.
263 (+) Start the Time Base and enable interrupt.
264 (+) Stop the Time Base and disable interrupt.
265 (+) Start the Time Base and enable DMA transfer.
266 (+) Stop the Time Base and disable DMA transfer.
267
268 @endverbatim
269 * @{
270 */
271 /**
272 * @brief Initializes the TIM Time base Unit according to the specified
273 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
274 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
275 * requires a timer reset to avoid unexpected direction
276 * due to DIR bit readonly in center aligned mode.
277 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
278 * @param htim TIM Base handle
279 * @retval HAL status
280 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
282 {
283 /* Check the TIM handle allocation */
284 if (htim == NULL)
285 {
286 return HAL_ERROR;
287 }
288
289 /* Check the parameters */
290 assert_param(IS_TIM_INSTANCE(htim->Instance));
291 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
292 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
293 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
294 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
295
296 if (htim->State == HAL_TIM_STATE_RESET)
297 {
298 /* Allocate lock resource and initialize it */
299 htim->Lock = HAL_UNLOCKED;
300
301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
302 /* Reset interrupt callbacks to legacy weak callbacks */
303 TIM_ResetCallback(htim);
304
305 if (htim->Base_MspInitCallback == NULL)
306 {
307 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
308 }
309 /* Init the low level hardware : GPIO, CLOCK, NVIC */
310 htim->Base_MspInitCallback(htim);
311 #else
312 /* Init the low level hardware : GPIO, CLOCK, NVIC */
313 HAL_TIM_Base_MspInit(htim);
314 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
315 }
316
317 /* Set the TIM state */
318 htim->State = HAL_TIM_STATE_BUSY;
319
320 /* Set the Time Base configuration */
321 TIM_Base_SetConfig(htim->Instance, &htim->Init);
322
323 /* Initialize the DMA burst operation state */
324 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
325
326 /* Initialize the TIM channels state */
327 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
328 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
329
330 /* Initialize the TIM state*/
331 htim->State = HAL_TIM_STATE_READY;
332
333 return HAL_OK;
334 }
335
336 /**
337 * @brief DeInitializes the TIM Base peripheral
338 * @param htim TIM Base handle
339 * @retval HAL status
340 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)341 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
342 {
343 /* Check the parameters */
344 assert_param(IS_TIM_INSTANCE(htim->Instance));
345
346 htim->State = HAL_TIM_STATE_BUSY;
347
348 /* Disable the TIM Peripheral Clock */
349 __HAL_TIM_DISABLE(htim);
350
351 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
352 if (htim->Base_MspDeInitCallback == NULL)
353 {
354 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
355 }
356 /* DeInit the low level hardware */
357 htim->Base_MspDeInitCallback(htim);
358 #else
359 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
360 HAL_TIM_Base_MspDeInit(htim);
361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
362
363 /* Change the DMA burst operation state */
364 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
365
366 /* Change the TIM channels state */
367 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
368 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
369
370 /* Change TIM state */
371 htim->State = HAL_TIM_STATE_RESET;
372
373 /* Release Lock */
374 __HAL_UNLOCK(htim);
375
376 return HAL_OK;
377 }
378
379 /**
380 * @brief Initializes the TIM Base MSP.
381 * @param htim TIM Base handle
382 * @retval None
383 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
385 {
386 /* Prevent unused argument(s) compilation warning */
387 UNUSED(htim);
388
389 /* NOTE : This function should not be modified, when the callback is needed,
390 the HAL_TIM_Base_MspInit could be implemented in the user file
391 */
392 }
393
394 /**
395 * @brief DeInitializes TIM Base MSP.
396 * @param htim TIM Base handle
397 * @retval None
398 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)399 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
400 {
401 /* Prevent unused argument(s) compilation warning */
402 UNUSED(htim);
403
404 /* NOTE : This function should not be modified, when the callback is needed,
405 the HAL_TIM_Base_MspDeInit could be implemented in the user file
406 */
407 }
408
409
410 /**
411 * @brief Starts the TIM Base generation.
412 * @param htim TIM Base handle
413 * @retval HAL status
414 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)415 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
416 {
417 uint32_t tmpsmcr;
418
419 /* Check the parameters */
420 assert_param(IS_TIM_INSTANCE(htim->Instance));
421
422 /* Check the TIM state */
423 if (htim->State != HAL_TIM_STATE_READY)
424 {
425 return HAL_ERROR;
426 }
427
428 /* Set the TIM state */
429 htim->State = HAL_TIM_STATE_BUSY;
430
431 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
432 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
433 {
434 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
435 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
436 {
437 __HAL_TIM_ENABLE(htim);
438 }
439 }
440 else
441 {
442 __HAL_TIM_ENABLE(htim);
443 }
444
445 /* Return function status */
446 return HAL_OK;
447 }
448
449 /**
450 * @brief Stops the TIM Base generation.
451 * @param htim TIM Base handle
452 * @retval HAL status
453 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)454 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
455 {
456 /* Check the parameters */
457 assert_param(IS_TIM_INSTANCE(htim->Instance));
458
459 /* Disable the Peripheral */
460 __HAL_TIM_DISABLE(htim);
461
462 /* Set the TIM state */
463 htim->State = HAL_TIM_STATE_READY;
464
465 /* Return function status */
466 return HAL_OK;
467 }
468
469 /**
470 * @brief Starts the TIM Base generation in interrupt mode.
471 * @param htim TIM Base handle
472 * @retval HAL status
473 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
475 {
476 uint32_t tmpsmcr;
477
478 /* Check the parameters */
479 assert_param(IS_TIM_INSTANCE(htim->Instance));
480
481 /* Check the TIM state */
482 if (htim->State != HAL_TIM_STATE_READY)
483 {
484 return HAL_ERROR;
485 }
486
487 /* Set the TIM state */
488 htim->State = HAL_TIM_STATE_BUSY;
489
490 /* Enable the TIM Update interrupt */
491 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
492
493 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
494 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
495 {
496 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
497 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
498 {
499 __HAL_TIM_ENABLE(htim);
500 }
501 }
502 else
503 {
504 __HAL_TIM_ENABLE(htim);
505 }
506
507 /* Return function status */
508 return HAL_OK;
509 }
510
511 /**
512 * @brief Stops the TIM Base generation in interrupt mode.
513 * @param htim TIM Base handle
514 * @retval HAL status
515 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)516 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
517 {
518 /* Check the parameters */
519 assert_param(IS_TIM_INSTANCE(htim->Instance));
520
521 /* Disable the TIM Update interrupt */
522 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
523
524 /* Disable the Peripheral */
525 __HAL_TIM_DISABLE(htim);
526
527 /* Set the TIM state */
528 htim->State = HAL_TIM_STATE_READY;
529
530 /* Return function status */
531 return HAL_OK;
532 }
533
534 /**
535 * @brief Starts the TIM Base generation in DMA mode.
536 * @param htim TIM Base handle
537 * @param pData The source Buffer address.
538 * @param Length The length of data to be transferred from memory to peripheral.
539 * @retval HAL status
540 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
542 {
543 uint32_t tmpsmcr;
544
545 /* Check the parameters */
546 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
547
548 /* Set the TIM state */
549 if (htim->State == HAL_TIM_STATE_BUSY)
550 {
551 return HAL_BUSY;
552 }
553 else if (htim->State == HAL_TIM_STATE_READY)
554 {
555 if ((pData == NULL) || (Length == 0U))
556 {
557 return HAL_ERROR;
558 }
559 else
560 {
561 htim->State = HAL_TIM_STATE_BUSY;
562 }
563 }
564 else
565 {
566 return HAL_ERROR;
567 }
568
569 /* Set the DMA Period elapsed callbacks */
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
571 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
572
573 /* Set the DMA error callback */
574 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
575
576 /* Enable the DMA channel */
577 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
578 Length) != HAL_OK)
579 {
580 /* Return error status */
581 return HAL_ERROR;
582 }
583
584 /* Enable the TIM Update DMA request */
585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
586
587 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
588 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
589 {
590 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
591 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
592 {
593 __HAL_TIM_ENABLE(htim);
594 }
595 }
596 else
597 {
598 __HAL_TIM_ENABLE(htim);
599 }
600
601 /* Return function status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Stops the TIM Base generation in DMA mode.
607 * @param htim TIM Base handle
608 * @retval HAL status
609 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
611 {
612 /* Check the parameters */
613 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
614
615 /* Disable the TIM Update DMA request */
616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
617
618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
619
620 /* Disable the Peripheral */
621 __HAL_TIM_DISABLE(htim);
622
623 /* Set the TIM state */
624 htim->State = HAL_TIM_STATE_READY;
625
626 /* Return function status */
627 return HAL_OK;
628 }
629
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
635 * @brief TIM Output Compare functions
636 *
637 @verbatim
638 ==============================================================================
639 ##### TIM Output Compare functions #####
640 ==============================================================================
641 [..]
642 This section provides functions allowing to:
643 (+) Initialize and configure the TIM Output Compare.
644 (+) De-initialize the TIM Output Compare.
645 (+) Start the TIM Output Compare.
646 (+) Stop the TIM Output Compare.
647 (+) Start the TIM Output Compare and enable interrupt.
648 (+) Stop the TIM Output Compare and disable interrupt.
649 (+) Start the TIM Output Compare and enable DMA transfer.
650 (+) Stop the TIM Output Compare and disable DMA transfer.
651
652 @endverbatim
653 * @{
654 */
655 /**
656 * @brief Initializes the TIM Output Compare according to the specified
657 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
658 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
659 * requires a timer reset to avoid unexpected direction
660 * due to DIR bit readonly in center aligned mode.
661 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
662 * @param htim TIM Output Compare handle
663 * @retval HAL status
664 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)665 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
666 {
667 /* Check the TIM handle allocation */
668 if (htim == NULL)
669 {
670 return HAL_ERROR;
671 }
672
673 /* Check the parameters */
674 assert_param(IS_TIM_INSTANCE(htim->Instance));
675 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
676 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
677 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
678 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
679
680 if (htim->State == HAL_TIM_STATE_RESET)
681 {
682 /* Allocate lock resource and initialize it */
683 htim->Lock = HAL_UNLOCKED;
684
685 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
686 /* Reset interrupt callbacks to legacy weak callbacks */
687 TIM_ResetCallback(htim);
688
689 if (htim->OC_MspInitCallback == NULL)
690 {
691 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
692 }
693 /* Init the low level hardware : GPIO, CLOCK, NVIC */
694 htim->OC_MspInitCallback(htim);
695 #else
696 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
697 HAL_TIM_OC_MspInit(htim);
698 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
699 }
700
701 /* Set the TIM state */
702 htim->State = HAL_TIM_STATE_BUSY;
703
704 /* Init the base time for the Output Compare */
705 TIM_Base_SetConfig(htim->Instance, &htim->Init);
706
707 /* Initialize the DMA burst operation state */
708 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
709
710 /* Initialize the TIM channels state */
711 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
712 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Initialize the TIM state*/
715 htim->State = HAL_TIM_STATE_READY;
716
717 return HAL_OK;
718 }
719
720 /**
721 * @brief DeInitializes the TIM peripheral
722 * @param htim TIM Output Compare handle
723 * @retval HAL status
724 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)725 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
726 {
727 /* Check the parameters */
728 assert_param(IS_TIM_INSTANCE(htim->Instance));
729
730 htim->State = HAL_TIM_STATE_BUSY;
731
732 /* Disable the TIM Peripheral Clock */
733 __HAL_TIM_DISABLE(htim);
734
735 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
736 if (htim->OC_MspDeInitCallback == NULL)
737 {
738 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
739 }
740 /* DeInit the low level hardware */
741 htim->OC_MspDeInitCallback(htim);
742 #else
743 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
744 HAL_TIM_OC_MspDeInit(htim);
745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
746
747 /* Change the DMA burst operation state */
748 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
749
750 /* Change the TIM channels state */
751 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
752 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
753
754 /* Change TIM state */
755 htim->State = HAL_TIM_STATE_RESET;
756
757 /* Release Lock */
758 __HAL_UNLOCK(htim);
759
760 return HAL_OK;
761 }
762
763 /**
764 * @brief Initializes the TIM Output Compare MSP.
765 * @param htim TIM Output Compare handle
766 * @retval None
767 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
769 {
770 /* Prevent unused argument(s) compilation warning */
771 UNUSED(htim);
772
773 /* NOTE : This function should not be modified, when the callback is needed,
774 the HAL_TIM_OC_MspInit could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief DeInitializes TIM Output Compare MSP.
780 * @param htim TIM Output Compare handle
781 * @retval None
782 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)783 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
784 {
785 /* Prevent unused argument(s) compilation warning */
786 UNUSED(htim);
787
788 /* NOTE : This function should not be modified, when the callback is needed,
789 the HAL_TIM_OC_MspDeInit could be implemented in the user file
790 */
791 }
792
793 /**
794 * @brief Starts the TIM Output Compare signal generation.
795 * @param htim TIM Output Compare handle
796 * @param Channel TIM Channel to be enabled
797 * This parameter can be one of the following values:
798 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
799 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
800 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
801 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
802 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
803 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
804 * @retval HAL status
805 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)806 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
807 {
808 uint32_t tmpsmcr;
809
810 /* Check the parameters */
811 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
812
813 /* Check the TIM channel state */
814 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
815 {
816 return HAL_ERROR;
817 }
818
819 /* Set the TIM channel state */
820 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
821
822 /* Enable the Output compare channel */
823 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
824
825 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
826 {
827 /* Enable the main output */
828 __HAL_TIM_MOE_ENABLE(htim);
829 }
830
831 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
832 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
833 {
834 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
835 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
836 {
837 __HAL_TIM_ENABLE(htim);
838 }
839 }
840 else
841 {
842 __HAL_TIM_ENABLE(htim);
843 }
844
845 /* Return function status */
846 return HAL_OK;
847 }
848
849 /**
850 * @brief Stops the TIM Output Compare signal generation.
851 * @param htim TIM Output Compare handle
852 * @param Channel TIM Channel to be disabled
853 * This parameter can be one of the following values:
854 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
855 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
856 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
857 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
858 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
859 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
860 * @retval HAL status
861 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)862 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
863 {
864 /* Check the parameters */
865 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
866
867 /* Disable the Output compare channel */
868 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
869
870 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
871 {
872 /* Disable the Main Output */
873 __HAL_TIM_MOE_DISABLE(htim);
874 }
875
876 /* Disable the Peripheral */
877 __HAL_TIM_DISABLE(htim);
878
879 /* Set the TIM channel state */
880 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
881
882 /* Return function status */
883 return HAL_OK;
884 }
885
886 /**
887 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
888 * @param htim TIM Output Compare handle
889 * @param Channel TIM Channel to be enabled
890 * This parameter can be one of the following values:
891 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
892 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
893 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
894 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
895 * @retval HAL status
896 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)897 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
898 {
899 HAL_StatusTypeDef status = HAL_OK;
900 uint32_t tmpsmcr;
901
902 /* Check the parameters */
903 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
904
905 /* Check the TIM channel state */
906 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
907 {
908 return HAL_ERROR;
909 }
910
911 /* Set the TIM channel state */
912 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
913
914 switch (Channel)
915 {
916 case TIM_CHANNEL_1:
917 {
918 /* Enable the TIM Capture/Compare 1 interrupt */
919 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
920 break;
921 }
922
923 case TIM_CHANNEL_2:
924 {
925 /* Enable the TIM Capture/Compare 2 interrupt */
926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
927 break;
928 }
929
930 case TIM_CHANNEL_3:
931 {
932 /* Enable the TIM Capture/Compare 3 interrupt */
933 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
934 break;
935 }
936
937 case TIM_CHANNEL_4:
938 {
939 /* Enable the TIM Capture/Compare 4 interrupt */
940 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
941 break;
942 }
943
944 default:
945 status = HAL_ERROR;
946 break;
947 }
948
949 if (status == HAL_OK)
950 {
951 /* Enable the Output compare channel */
952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
953
954 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
955 {
956 /* Enable the main output */
957 __HAL_TIM_MOE_ENABLE(htim);
958 }
959
960 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
961 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
962 {
963 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
964 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
965 {
966 __HAL_TIM_ENABLE(htim);
967 }
968 }
969 else
970 {
971 __HAL_TIM_ENABLE(htim);
972 }
973 }
974
975 /* Return function status */
976 return status;
977 }
978
979 /**
980 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
981 * @param htim TIM Output Compare handle
982 * @param Channel TIM Channel to be disabled
983 * This parameter can be one of the following values:
984 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
985 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
986 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
987 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
988 * @retval HAL status
989 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)990 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
991 {
992 HAL_StatusTypeDef status = HAL_OK;
993
994 /* Check the parameters */
995 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
996
997 switch (Channel)
998 {
999 case TIM_CHANNEL_1:
1000 {
1001 /* Disable the TIM Capture/Compare 1 interrupt */
1002 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1003 break;
1004 }
1005
1006 case TIM_CHANNEL_2:
1007 {
1008 /* Disable the TIM Capture/Compare 2 interrupt */
1009 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1010 break;
1011 }
1012
1013 case TIM_CHANNEL_3:
1014 {
1015 /* Disable the TIM Capture/Compare 3 interrupt */
1016 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1017 break;
1018 }
1019
1020 case TIM_CHANNEL_4:
1021 {
1022 /* Disable the TIM Capture/Compare 4 interrupt */
1023 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1024 break;
1025 }
1026
1027 default:
1028 status = HAL_ERROR;
1029 break;
1030 }
1031
1032 if (status == HAL_OK)
1033 {
1034 /* Disable the Output compare channel */
1035 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1036
1037 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1038 {
1039 /* Disable the Main Output */
1040 __HAL_TIM_MOE_DISABLE(htim);
1041 }
1042
1043 /* Disable the Peripheral */
1044 __HAL_TIM_DISABLE(htim);
1045
1046 /* Set the TIM channel state */
1047 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1048 }
1049
1050 /* Return function status */
1051 return status;
1052 }
1053
1054 /**
1055 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1056 * @param htim TIM Output Compare handle
1057 * @param Channel TIM Channel to be enabled
1058 * This parameter can be one of the following values:
1059 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1060 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1061 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1062 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1063 * @param pData The source Buffer address.
1064 * @param Length The length of data to be transferred from memory to TIM peripheral
1065 * @retval HAL status
1066 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1067 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1068 uint16_t Length)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071 uint32_t tmpsmcr;
1072
1073 /* Check the parameters */
1074 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1075
1076 /* Set the TIM channel state */
1077 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1078 {
1079 return HAL_BUSY;
1080 }
1081 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1082 {
1083 if ((pData == NULL) || (Length == 0U))
1084 {
1085 return HAL_ERROR;
1086 }
1087 else
1088 {
1089 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1090 }
1091 }
1092 else
1093 {
1094 return HAL_ERROR;
1095 }
1096
1097 switch (Channel)
1098 {
1099 case TIM_CHANNEL_1:
1100 {
1101 /* Set the DMA compare callbacks */
1102 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1103 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1104
1105 /* Set the DMA error callback */
1106 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1107
1108 /* Enable the DMA channel */
1109 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1110 Length) != HAL_OK)
1111 {
1112 /* Return error status */
1113 return HAL_ERROR;
1114 }
1115
1116 /* Enable the TIM Capture/Compare 1 DMA request */
1117 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1118 break;
1119 }
1120
1121 case TIM_CHANNEL_2:
1122 {
1123 /* Set the DMA compare callbacks */
1124 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1125 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1126
1127 /* Set the DMA error callback */
1128 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1129
1130 /* Enable the DMA channel */
1131 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1132 Length) != HAL_OK)
1133 {
1134 /* Return error status */
1135 return HAL_ERROR;
1136 }
1137
1138 /* Enable the TIM Capture/Compare 2 DMA request */
1139 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1140 break;
1141 }
1142
1143 case TIM_CHANNEL_3:
1144 {
1145 /* Set the DMA compare callbacks */
1146 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1147 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1148
1149 /* Set the DMA error callback */
1150 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1151
1152 /* Enable the DMA channel */
1153 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1154 Length) != HAL_OK)
1155 {
1156 /* Return error status */
1157 return HAL_ERROR;
1158 }
1159 /* Enable the TIM Capture/Compare 3 DMA request */
1160 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1161 break;
1162 }
1163
1164 case TIM_CHANNEL_4:
1165 {
1166 /* Set the DMA compare callbacks */
1167 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1168 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1169
1170 /* Set the DMA error callback */
1171 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1172
1173 /* Enable the DMA channel */
1174 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1175 Length) != HAL_OK)
1176 {
1177 /* Return error status */
1178 return HAL_ERROR;
1179 }
1180 /* Enable the TIM Capture/Compare 4 DMA request */
1181 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1182 break;
1183 }
1184
1185 default:
1186 status = HAL_ERROR;
1187 break;
1188 }
1189
1190 if (status == HAL_OK)
1191 {
1192 /* Enable the Output compare channel */
1193 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1194
1195 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1196 {
1197 /* Enable the main output */
1198 __HAL_TIM_MOE_ENABLE(htim);
1199 }
1200
1201 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1202 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1203 {
1204 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1205 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1206 {
1207 __HAL_TIM_ENABLE(htim);
1208 }
1209 }
1210 else
1211 {
1212 __HAL_TIM_ENABLE(htim);
1213 }
1214 }
1215
1216 /* Return function status */
1217 return status;
1218 }
1219
1220 /**
1221 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1222 * @param htim TIM Output Compare handle
1223 * @param Channel TIM Channel to be disabled
1224 * This parameter can be one of the following values:
1225 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1226 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1227 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1228 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1229 * @retval HAL status
1230 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1231 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1232 {
1233 HAL_StatusTypeDef status = HAL_OK;
1234
1235 /* Check the parameters */
1236 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1237
1238 switch (Channel)
1239 {
1240 case TIM_CHANNEL_1:
1241 {
1242 /* Disable the TIM Capture/Compare 1 DMA request */
1243 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1244 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1245 break;
1246 }
1247
1248 case TIM_CHANNEL_2:
1249 {
1250 /* Disable the TIM Capture/Compare 2 DMA request */
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1253 break;
1254 }
1255
1256 case TIM_CHANNEL_3:
1257 {
1258 /* Disable the TIM Capture/Compare 3 DMA request */
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1261 break;
1262 }
1263
1264 case TIM_CHANNEL_4:
1265 {
1266 /* Disable the TIM Capture/Compare 4 interrupt */
1267 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1268 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1269 break;
1270 }
1271
1272 default:
1273 status = HAL_ERROR;
1274 break;
1275 }
1276
1277 if (status == HAL_OK)
1278 {
1279 /* Disable the Output compare channel */
1280 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1281
1282 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1283 {
1284 /* Disable the Main Output */
1285 __HAL_TIM_MOE_DISABLE(htim);
1286 }
1287
1288 /* Disable the Peripheral */
1289 __HAL_TIM_DISABLE(htim);
1290
1291 /* Set the TIM channel state */
1292 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1293 }
1294
1295 /* Return function status */
1296 return status;
1297 }
1298
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1304 * @brief TIM PWM functions
1305 *
1306 @verbatim
1307 ==============================================================================
1308 ##### TIM PWM functions #####
1309 ==============================================================================
1310 [..]
1311 This section provides functions allowing to:
1312 (+) Initialize and configure the TIM PWM.
1313 (+) De-initialize the TIM PWM.
1314 (+) Start the TIM PWM.
1315 (+) Stop the TIM PWM.
1316 (+) Start the TIM PWM and enable interrupt.
1317 (+) Stop the TIM PWM and disable interrupt.
1318 (+) Start the TIM PWM and enable DMA transfer.
1319 (+) Stop the TIM PWM and disable DMA transfer.
1320
1321 @endverbatim
1322 * @{
1323 */
1324 /**
1325 * @brief Initializes the TIM PWM Time Base according to the specified
1326 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1327 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1328 * requires a timer reset to avoid unexpected direction
1329 * due to DIR bit readonly in center aligned mode.
1330 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1331 * @param htim TIM PWM handle
1332 * @retval HAL status
1333 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1334 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1335 {
1336 /* Check the TIM handle allocation */
1337 if (htim == NULL)
1338 {
1339 return HAL_ERROR;
1340 }
1341
1342 /* Check the parameters */
1343 assert_param(IS_TIM_INSTANCE(htim->Instance));
1344 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1345 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1346 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1347 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1348
1349 if (htim->State == HAL_TIM_STATE_RESET)
1350 {
1351 /* Allocate lock resource and initialize it */
1352 htim->Lock = HAL_UNLOCKED;
1353
1354 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1355 /* Reset interrupt callbacks to legacy weak callbacks */
1356 TIM_ResetCallback(htim);
1357
1358 if (htim->PWM_MspInitCallback == NULL)
1359 {
1360 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1361 }
1362 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1363 htim->PWM_MspInitCallback(htim);
1364 #else
1365 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1366 HAL_TIM_PWM_MspInit(htim);
1367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1368 }
1369
1370 /* Set the TIM state */
1371 htim->State = HAL_TIM_STATE_BUSY;
1372
1373 /* Init the base time for the PWM */
1374 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1375
1376 /* Initialize the DMA burst operation state */
1377 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1378
1379 /* Initialize the TIM channels state */
1380 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1381 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1382
1383 /* Initialize the TIM state*/
1384 htim->State = HAL_TIM_STATE_READY;
1385
1386 return HAL_OK;
1387 }
1388
1389 /**
1390 * @brief DeInitializes the TIM peripheral
1391 * @param htim TIM PWM handle
1392 * @retval HAL status
1393 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1394 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1395 {
1396 /* Check the parameters */
1397 assert_param(IS_TIM_INSTANCE(htim->Instance));
1398
1399 htim->State = HAL_TIM_STATE_BUSY;
1400
1401 /* Disable the TIM Peripheral Clock */
1402 __HAL_TIM_DISABLE(htim);
1403
1404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1405 if (htim->PWM_MspDeInitCallback == NULL)
1406 {
1407 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1408 }
1409 /* DeInit the low level hardware */
1410 htim->PWM_MspDeInitCallback(htim);
1411 #else
1412 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1413 HAL_TIM_PWM_MspDeInit(htim);
1414 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1415
1416 /* Change the DMA burst operation state */
1417 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1418
1419 /* Change the TIM channels state */
1420 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1421 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1422
1423 /* Change TIM state */
1424 htim->State = HAL_TIM_STATE_RESET;
1425
1426 /* Release Lock */
1427 __HAL_UNLOCK(htim);
1428
1429 return HAL_OK;
1430 }
1431
1432 /**
1433 * @brief Initializes the TIM PWM MSP.
1434 * @param htim TIM PWM handle
1435 * @retval None
1436 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1437 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1438 {
1439 /* Prevent unused argument(s) compilation warning */
1440 UNUSED(htim);
1441
1442 /* NOTE : This function should not be modified, when the callback is needed,
1443 the HAL_TIM_PWM_MspInit could be implemented in the user file
1444 */
1445 }
1446
1447 /**
1448 * @brief DeInitializes TIM PWM MSP.
1449 * @param htim TIM PWM handle
1450 * @retval None
1451 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1452 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1453 {
1454 /* Prevent unused argument(s) compilation warning */
1455 UNUSED(htim);
1456
1457 /* NOTE : This function should not be modified, when the callback is needed,
1458 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1459 */
1460 }
1461
1462 /**
1463 * @brief Starts the PWM signal generation.
1464 * @param htim TIM handle
1465 * @param Channel TIM Channels to be enabled
1466 * This parameter can be one of the following values:
1467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1469 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1470 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1471 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1472 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1473 * @retval HAL status
1474 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1475 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1476 {
1477 uint32_t tmpsmcr;
1478
1479 /* Check the parameters */
1480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1481
1482 /* Check the TIM channel state */
1483 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1484 {
1485 return HAL_ERROR;
1486 }
1487
1488 /* Set the TIM channel state */
1489 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1490
1491 /* Enable the Capture compare channel */
1492 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1493
1494 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1495 {
1496 /* Enable the main output */
1497 __HAL_TIM_MOE_ENABLE(htim);
1498 }
1499
1500 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1501 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1502 {
1503 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1504 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1505 {
1506 __HAL_TIM_ENABLE(htim);
1507 }
1508 }
1509 else
1510 {
1511 __HAL_TIM_ENABLE(htim);
1512 }
1513
1514 /* Return function status */
1515 return HAL_OK;
1516 }
1517
1518 /**
1519 * @brief Stops the PWM signal generation.
1520 * @param htim TIM PWM handle
1521 * @param Channel TIM Channels to be disabled
1522 * This parameter can be one of the following values:
1523 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1524 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1525 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1526 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1527 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1528 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1529 * @retval HAL status
1530 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1531 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1532 {
1533 /* Check the parameters */
1534 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1535
1536 /* Disable the Capture compare channel */
1537 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1538
1539 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1540 {
1541 /* Disable the Main Output */
1542 __HAL_TIM_MOE_DISABLE(htim);
1543 }
1544
1545 /* Disable the Peripheral */
1546 __HAL_TIM_DISABLE(htim);
1547
1548 /* Set the TIM channel state */
1549 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1550
1551 /* Return function status */
1552 return HAL_OK;
1553 }
1554
1555 /**
1556 * @brief Starts the PWM signal generation in interrupt mode.
1557 * @param htim TIM PWM handle
1558 * @param Channel TIM Channel to be enabled
1559 * This parameter can be one of the following values:
1560 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1561 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1562 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1563 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1564 * @retval HAL status
1565 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1566 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1567 {
1568 HAL_StatusTypeDef status = HAL_OK;
1569 uint32_t tmpsmcr;
1570
1571 /* Check the parameters */
1572 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1573
1574 /* Check the TIM channel state */
1575 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1576 {
1577 return HAL_ERROR;
1578 }
1579
1580 /* Set the TIM channel state */
1581 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1582
1583 switch (Channel)
1584 {
1585 case TIM_CHANNEL_1:
1586 {
1587 /* Enable the TIM Capture/Compare 1 interrupt */
1588 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1589 break;
1590 }
1591
1592 case TIM_CHANNEL_2:
1593 {
1594 /* Enable the TIM Capture/Compare 2 interrupt */
1595 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1596 break;
1597 }
1598
1599 case TIM_CHANNEL_3:
1600 {
1601 /* Enable the TIM Capture/Compare 3 interrupt */
1602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1603 break;
1604 }
1605
1606 case TIM_CHANNEL_4:
1607 {
1608 /* Enable the TIM Capture/Compare 4 interrupt */
1609 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1610 break;
1611 }
1612
1613 default:
1614 status = HAL_ERROR;
1615 break;
1616 }
1617
1618 if (status == HAL_OK)
1619 {
1620 /* Enable the Capture compare channel */
1621 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1622
1623 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1624 {
1625 /* Enable the main output */
1626 __HAL_TIM_MOE_ENABLE(htim);
1627 }
1628
1629 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1630 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1631 {
1632 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1633 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1634 {
1635 __HAL_TIM_ENABLE(htim);
1636 }
1637 }
1638 else
1639 {
1640 __HAL_TIM_ENABLE(htim);
1641 }
1642 }
1643
1644 /* Return function status */
1645 return status;
1646 }
1647
1648 /**
1649 * @brief Stops the PWM signal generation in interrupt mode.
1650 * @param htim TIM PWM handle
1651 * @param Channel TIM Channels to be disabled
1652 * This parameter can be one of the following values:
1653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1655 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1656 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1657 * @retval HAL status
1658 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1659 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1660 {
1661 HAL_StatusTypeDef status = HAL_OK;
1662
1663 /* Check the parameters */
1664 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1665
1666 switch (Channel)
1667 {
1668 case TIM_CHANNEL_1:
1669 {
1670 /* Disable the TIM Capture/Compare 1 interrupt */
1671 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1672 break;
1673 }
1674
1675 case TIM_CHANNEL_2:
1676 {
1677 /* Disable the TIM Capture/Compare 2 interrupt */
1678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1679 break;
1680 }
1681
1682 case TIM_CHANNEL_3:
1683 {
1684 /* Disable the TIM Capture/Compare 3 interrupt */
1685 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1686 break;
1687 }
1688
1689 case TIM_CHANNEL_4:
1690 {
1691 /* Disable the TIM Capture/Compare 4 interrupt */
1692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1693 break;
1694 }
1695
1696 default:
1697 status = HAL_ERROR;
1698 break;
1699 }
1700
1701 if (status == HAL_OK)
1702 {
1703 /* Disable the Capture compare channel */
1704 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1705
1706 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1707 {
1708 /* Disable the Main Output */
1709 __HAL_TIM_MOE_DISABLE(htim);
1710 }
1711
1712 /* Disable the Peripheral */
1713 __HAL_TIM_DISABLE(htim);
1714
1715 /* Set the TIM channel state */
1716 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1717 }
1718
1719 /* Return function status */
1720 return status;
1721 }
1722
1723 /**
1724 * @brief Starts the TIM PWM signal generation in DMA mode.
1725 * @param htim TIM PWM handle
1726 * @param Channel TIM Channels to be enabled
1727 * This parameter can be one of the following values:
1728 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1729 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1730 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1731 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1732 * @param pData The source Buffer address.
1733 * @param Length The length of data to be transferred from memory to TIM peripheral
1734 * @retval HAL status
1735 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1736 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1737 uint16_t Length)
1738 {
1739 HAL_StatusTypeDef status = HAL_OK;
1740 uint32_t tmpsmcr;
1741
1742 /* Check the parameters */
1743 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1744
1745 /* Set the TIM channel state */
1746 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1747 {
1748 return HAL_BUSY;
1749 }
1750 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1751 {
1752 if ((pData == NULL) || (Length == 0U))
1753 {
1754 return HAL_ERROR;
1755 }
1756 else
1757 {
1758 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1759 }
1760 }
1761 else
1762 {
1763 return HAL_ERROR;
1764 }
1765
1766 switch (Channel)
1767 {
1768 case TIM_CHANNEL_1:
1769 {
1770 /* Set the DMA compare callbacks */
1771 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1772 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1773
1774 /* Set the DMA error callback */
1775 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1776
1777 /* Enable the DMA channel */
1778 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1779 Length) != HAL_OK)
1780 {
1781 /* Return error status */
1782 return HAL_ERROR;
1783 }
1784
1785 /* Enable the TIM Capture/Compare 1 DMA request */
1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1787 break;
1788 }
1789
1790 case TIM_CHANNEL_2:
1791 {
1792 /* Set the DMA compare callbacks */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1794 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1795
1796 /* Set the DMA error callback */
1797 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1798
1799 /* Enable the DMA channel */
1800 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1801 Length) != HAL_OK)
1802 {
1803 /* Return error status */
1804 return HAL_ERROR;
1805 }
1806 /* Enable the TIM Capture/Compare 2 DMA request */
1807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1808 break;
1809 }
1810
1811 case TIM_CHANNEL_3:
1812 {
1813 /* Set the DMA compare callbacks */
1814 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1815 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1816
1817 /* Set the DMA error callback */
1818 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1819
1820 /* Enable the DMA channel */
1821 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1822 Length) != HAL_OK)
1823 {
1824 /* Return error status */
1825 return HAL_ERROR;
1826 }
1827 /* Enable the TIM Output Capture/Compare 3 request */
1828 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1829 break;
1830 }
1831
1832 case TIM_CHANNEL_4:
1833 {
1834 /* Set the DMA compare callbacks */
1835 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1836 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1837
1838 /* Set the DMA error callback */
1839 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1840
1841 /* Enable the DMA channel */
1842 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1843 Length) != HAL_OK)
1844 {
1845 /* Return error status */
1846 return HAL_ERROR;
1847 }
1848 /* Enable the TIM Capture/Compare 4 DMA request */
1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1850 break;
1851 }
1852
1853 default:
1854 status = HAL_ERROR;
1855 break;
1856 }
1857
1858 if (status == HAL_OK)
1859 {
1860 /* Enable the Capture compare channel */
1861 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1862
1863 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1864 {
1865 /* Enable the main output */
1866 __HAL_TIM_MOE_ENABLE(htim);
1867 }
1868
1869 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1870 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1871 {
1872 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1873 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1874 {
1875 __HAL_TIM_ENABLE(htim);
1876 }
1877 }
1878 else
1879 {
1880 __HAL_TIM_ENABLE(htim);
1881 }
1882 }
1883
1884 /* Return function status */
1885 return status;
1886 }
1887
1888 /**
1889 * @brief Stops the TIM PWM signal generation in DMA mode.
1890 * @param htim TIM PWM handle
1891 * @param Channel TIM Channels to be disabled
1892 * This parameter can be one of the following values:
1893 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1894 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1895 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1896 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1897 * @retval HAL status
1898 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1899 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1900 {
1901 HAL_StatusTypeDef status = HAL_OK;
1902
1903 /* Check the parameters */
1904 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1905
1906 switch (Channel)
1907 {
1908 case TIM_CHANNEL_1:
1909 {
1910 /* Disable the TIM Capture/Compare 1 DMA request */
1911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1912 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1913 break;
1914 }
1915
1916 case TIM_CHANNEL_2:
1917 {
1918 /* Disable the TIM Capture/Compare 2 DMA request */
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1920 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1921 break;
1922 }
1923
1924 case TIM_CHANNEL_3:
1925 {
1926 /* Disable the TIM Capture/Compare 3 DMA request */
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1929 break;
1930 }
1931
1932 case TIM_CHANNEL_4:
1933 {
1934 /* Disable the TIM Capture/Compare 4 interrupt */
1935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1937 break;
1938 }
1939
1940 default:
1941 status = HAL_ERROR;
1942 break;
1943 }
1944
1945 if (status == HAL_OK)
1946 {
1947 /* Disable the Capture compare channel */
1948 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1949
1950 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1951 {
1952 /* Disable the Main Output */
1953 __HAL_TIM_MOE_DISABLE(htim);
1954 }
1955
1956 /* Disable the Peripheral */
1957 __HAL_TIM_DISABLE(htim);
1958
1959 /* Set the TIM channel state */
1960 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1961 }
1962
1963 /* Return function status */
1964 return status;
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1972 * @brief TIM Input Capture functions
1973 *
1974 @verbatim
1975 ==============================================================================
1976 ##### TIM Input Capture functions #####
1977 ==============================================================================
1978 [..]
1979 This section provides functions allowing to:
1980 (+) Initialize and configure the TIM Input Capture.
1981 (+) De-initialize the TIM Input Capture.
1982 (+) Start the TIM Input Capture.
1983 (+) Stop the TIM Input Capture.
1984 (+) Start the TIM Input Capture and enable interrupt.
1985 (+) Stop the TIM Input Capture and disable interrupt.
1986 (+) Start the TIM Input Capture and enable DMA transfer.
1987 (+) Stop the TIM Input Capture and disable DMA transfer.
1988
1989 @endverbatim
1990 * @{
1991 */
1992 /**
1993 * @brief Initializes the TIM Input Capture Time base according to the specified
1994 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1995 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1996 * requires a timer reset to avoid unexpected direction
1997 * due to DIR bit readonly in center aligned mode.
1998 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1999 * @param htim TIM Input Capture handle
2000 * @retval HAL status
2001 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)2002 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
2003 {
2004 /* Check the TIM handle allocation */
2005 if (htim == NULL)
2006 {
2007 return HAL_ERROR;
2008 }
2009
2010 /* Check the parameters */
2011 assert_param(IS_TIM_INSTANCE(htim->Instance));
2012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2014 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2015 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2016
2017 if (htim->State == HAL_TIM_STATE_RESET)
2018 {
2019 /* Allocate lock resource and initialize it */
2020 htim->Lock = HAL_UNLOCKED;
2021
2022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2023 /* Reset interrupt callbacks to legacy weak callbacks */
2024 TIM_ResetCallback(htim);
2025
2026 if (htim->IC_MspInitCallback == NULL)
2027 {
2028 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2029 }
2030 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2031 htim->IC_MspInitCallback(htim);
2032 #else
2033 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2034 HAL_TIM_IC_MspInit(htim);
2035 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2036 }
2037
2038 /* Set the TIM state */
2039 htim->State = HAL_TIM_STATE_BUSY;
2040
2041 /* Init the base time for the input capture */
2042 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2043
2044 /* Initialize the DMA burst operation state */
2045 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2046
2047 /* Initialize the TIM channels state */
2048 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2049 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2050
2051 /* Initialize the TIM state*/
2052 htim->State = HAL_TIM_STATE_READY;
2053
2054 return HAL_OK;
2055 }
2056
2057 /**
2058 * @brief DeInitializes the TIM peripheral
2059 * @param htim TIM Input Capture handle
2060 * @retval HAL status
2061 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2062 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2063 {
2064 /* Check the parameters */
2065 assert_param(IS_TIM_INSTANCE(htim->Instance));
2066
2067 htim->State = HAL_TIM_STATE_BUSY;
2068
2069 /* Disable the TIM Peripheral Clock */
2070 __HAL_TIM_DISABLE(htim);
2071
2072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2073 if (htim->IC_MspDeInitCallback == NULL)
2074 {
2075 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2076 }
2077 /* DeInit the low level hardware */
2078 htim->IC_MspDeInitCallback(htim);
2079 #else
2080 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2081 HAL_TIM_IC_MspDeInit(htim);
2082 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2083
2084 /* Change the DMA burst operation state */
2085 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2086
2087 /* Change the TIM channels state */
2088 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2089 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2090
2091 /* Change TIM state */
2092 htim->State = HAL_TIM_STATE_RESET;
2093
2094 /* Release Lock */
2095 __HAL_UNLOCK(htim);
2096
2097 return HAL_OK;
2098 }
2099
2100 /**
2101 * @brief Initializes the TIM Input Capture MSP.
2102 * @param htim TIM Input Capture handle
2103 * @retval None
2104 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2105 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2106 {
2107 /* Prevent unused argument(s) compilation warning */
2108 UNUSED(htim);
2109
2110 /* NOTE : This function should not be modified, when the callback is needed,
2111 the HAL_TIM_IC_MspInit could be implemented in the user file
2112 */
2113 }
2114
2115 /**
2116 * @brief DeInitializes TIM Input Capture MSP.
2117 * @param htim TIM handle
2118 * @retval None
2119 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2120 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2121 {
2122 /* Prevent unused argument(s) compilation warning */
2123 UNUSED(htim);
2124
2125 /* NOTE : This function should not be modified, when the callback is needed,
2126 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2127 */
2128 }
2129
2130 /**
2131 * @brief Starts the TIM Input Capture measurement.
2132 * @param htim TIM Input Capture handle
2133 * @param Channel TIM Channels to be enabled
2134 * This parameter can be one of the following values:
2135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2139 * @retval HAL status
2140 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2141 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2142 {
2143 uint32_t tmpsmcr;
2144 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2145 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2146
2147 /* Check the parameters */
2148 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2149
2150 /* Check the TIM channel state */
2151 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2152 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2153 {
2154 return HAL_ERROR;
2155 }
2156
2157 /* Set the TIM channel state */
2158 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2159 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2160
2161 /* Enable the Input Capture channel */
2162 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2163
2164 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2165 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2166 {
2167 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2168 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2169 {
2170 __HAL_TIM_ENABLE(htim);
2171 }
2172 }
2173 else
2174 {
2175 __HAL_TIM_ENABLE(htim);
2176 }
2177
2178 /* Return function status */
2179 return HAL_OK;
2180 }
2181
2182 /**
2183 * @brief Stops the TIM Input Capture measurement.
2184 * @param htim TIM Input Capture handle
2185 * @param Channel TIM Channels to be disabled
2186 * This parameter can be one of the following values:
2187 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2188 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2189 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2190 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2191 * @retval HAL status
2192 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2193 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2194 {
2195 /* Check the parameters */
2196 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2197
2198 /* Disable the Input Capture channel */
2199 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2200
2201 /* Disable the Peripheral */
2202 __HAL_TIM_DISABLE(htim);
2203
2204 /* Set the TIM channel state */
2205 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2206 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2207
2208 /* Return function status */
2209 return HAL_OK;
2210 }
2211
2212 /**
2213 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2214 * @param htim TIM Input Capture handle
2215 * @param Channel TIM Channels to be enabled
2216 * This parameter can be one of the following values:
2217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2221 * @retval HAL status
2222 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2223 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2224 {
2225 HAL_StatusTypeDef status = HAL_OK;
2226 uint32_t tmpsmcr;
2227
2228 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2229 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2230
2231 /* Check the parameters */
2232 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2233
2234 /* Check the TIM channel state */
2235 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2236 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2237 {
2238 return HAL_ERROR;
2239 }
2240
2241 /* Set the TIM channel state */
2242 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2243 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2244
2245 switch (Channel)
2246 {
2247 case TIM_CHANNEL_1:
2248 {
2249 /* Enable the TIM Capture/Compare 1 interrupt */
2250 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2251 break;
2252 }
2253
2254 case TIM_CHANNEL_2:
2255 {
2256 /* Enable the TIM Capture/Compare 2 interrupt */
2257 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2258 break;
2259 }
2260
2261 case TIM_CHANNEL_3:
2262 {
2263 /* Enable the TIM Capture/Compare 3 interrupt */
2264 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2265 break;
2266 }
2267
2268 case TIM_CHANNEL_4:
2269 {
2270 /* Enable the TIM Capture/Compare 4 interrupt */
2271 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2272 break;
2273 }
2274
2275 default:
2276 status = HAL_ERROR;
2277 break;
2278 }
2279
2280 if (status == HAL_OK)
2281 {
2282 /* Enable the Input Capture channel */
2283 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2284
2285 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2286 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2287 {
2288 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2289 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2290 {
2291 __HAL_TIM_ENABLE(htim);
2292 }
2293 }
2294 else
2295 {
2296 __HAL_TIM_ENABLE(htim);
2297 }
2298 }
2299
2300 /* Return function status */
2301 return status;
2302 }
2303
2304 /**
2305 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2306 * @param htim TIM Input Capture handle
2307 * @param Channel TIM Channels to be disabled
2308 * This parameter can be one of the following values:
2309 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2310 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2311 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2312 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2313 * @retval HAL status
2314 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2315 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2316 {
2317 HAL_StatusTypeDef status = HAL_OK;
2318
2319 /* Check the parameters */
2320 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2321
2322 switch (Channel)
2323 {
2324 case TIM_CHANNEL_1:
2325 {
2326 /* Disable the TIM Capture/Compare 1 interrupt */
2327 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2328 break;
2329 }
2330
2331 case TIM_CHANNEL_2:
2332 {
2333 /* Disable the TIM Capture/Compare 2 interrupt */
2334 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2335 break;
2336 }
2337
2338 case TIM_CHANNEL_3:
2339 {
2340 /* Disable the TIM Capture/Compare 3 interrupt */
2341 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2342 break;
2343 }
2344
2345 case TIM_CHANNEL_4:
2346 {
2347 /* Disable the TIM Capture/Compare 4 interrupt */
2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2349 break;
2350 }
2351
2352 default:
2353 status = HAL_ERROR;
2354 break;
2355 }
2356
2357 if (status == HAL_OK)
2358 {
2359 /* Disable the Input Capture channel */
2360 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2361
2362 /* Disable the Peripheral */
2363 __HAL_TIM_DISABLE(htim);
2364
2365 /* Set the TIM channel state */
2366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2368 }
2369
2370 /* Return function status */
2371 return status;
2372 }
2373
2374 /**
2375 * @brief Starts the TIM Input Capture measurement in DMA mode.
2376 * @param htim TIM Input Capture handle
2377 * @param Channel TIM Channels to be enabled
2378 * This parameter can be one of the following values:
2379 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2380 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2381 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2382 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2383 * @param pData The destination Buffer address.
2384 * @param Length The length of data to be transferred from TIM peripheral to memory.
2385 * @retval HAL status
2386 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2387 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2388 {
2389 HAL_StatusTypeDef status = HAL_OK;
2390 uint32_t tmpsmcr;
2391
2392 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2393 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2394
2395 /* Check the parameters */
2396 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2397 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2398
2399 /* Set the TIM channel state */
2400 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2401 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2402 {
2403 return HAL_BUSY;
2404 }
2405 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2406 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2407 {
2408 if ((pData == NULL) || (Length == 0U))
2409 {
2410 return HAL_ERROR;
2411 }
2412 else
2413 {
2414 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2415 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2416 }
2417 }
2418 else
2419 {
2420 return HAL_ERROR;
2421 }
2422
2423 /* Enable the Input Capture channel */
2424 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2425
2426 switch (Channel)
2427 {
2428 case TIM_CHANNEL_1:
2429 {
2430 /* Set the DMA capture callbacks */
2431 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2432 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2433
2434 /* Set the DMA error callback */
2435 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2436
2437 /* Enable the DMA channel */
2438 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2439 Length) != HAL_OK)
2440 {
2441 /* Return error status */
2442 return HAL_ERROR;
2443 }
2444 /* Enable the TIM Capture/Compare 1 DMA request */
2445 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2446 break;
2447 }
2448
2449 case TIM_CHANNEL_2:
2450 {
2451 /* Set the DMA capture callbacks */
2452 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2453 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2454
2455 /* Set the DMA error callback */
2456 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2457
2458 /* Enable the DMA channel */
2459 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2460 Length) != HAL_OK)
2461 {
2462 /* Return error status */
2463 return HAL_ERROR;
2464 }
2465 /* Enable the TIM Capture/Compare 2 DMA request */
2466 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2467 break;
2468 }
2469
2470 case TIM_CHANNEL_3:
2471 {
2472 /* Set the DMA capture callbacks */
2473 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2474 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2475
2476 /* Set the DMA error callback */
2477 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2478
2479 /* Enable the DMA channel */
2480 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2481 Length) != HAL_OK)
2482 {
2483 /* Return error status */
2484 return HAL_ERROR;
2485 }
2486 /* Enable the TIM Capture/Compare 3 DMA request */
2487 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2488 break;
2489 }
2490
2491 case TIM_CHANNEL_4:
2492 {
2493 /* Set the DMA capture callbacks */
2494 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2495 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2496
2497 /* Set the DMA error callback */
2498 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2499
2500 /* Enable the DMA channel */
2501 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2502 Length) != HAL_OK)
2503 {
2504 /* Return error status */
2505 return HAL_ERROR;
2506 }
2507 /* Enable the TIM Capture/Compare 4 DMA request */
2508 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2509 break;
2510 }
2511
2512 default:
2513 status = HAL_ERROR;
2514 break;
2515 }
2516
2517 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2518 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2519 {
2520 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2521 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2522 {
2523 __HAL_TIM_ENABLE(htim);
2524 }
2525 }
2526 else
2527 {
2528 __HAL_TIM_ENABLE(htim);
2529 }
2530
2531 /* Return function status */
2532 return status;
2533 }
2534
2535 /**
2536 * @brief Stops the TIM Input Capture measurement in DMA mode.
2537 * @param htim TIM Input Capture handle
2538 * @param Channel TIM Channels to be disabled
2539 * This parameter can be one of the following values:
2540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2542 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2543 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2544 * @retval HAL status
2545 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2546 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2547 {
2548 HAL_StatusTypeDef status = HAL_OK;
2549
2550 /* Check the parameters */
2551 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2552 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2553
2554 /* Disable the Input Capture channel */
2555 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2556
2557 switch (Channel)
2558 {
2559 case TIM_CHANNEL_1:
2560 {
2561 /* Disable the TIM Capture/Compare 1 DMA request */
2562 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2563 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2564 break;
2565 }
2566
2567 case TIM_CHANNEL_2:
2568 {
2569 /* Disable the TIM Capture/Compare 2 DMA request */
2570 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2571 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2572 break;
2573 }
2574
2575 case TIM_CHANNEL_3:
2576 {
2577 /* Disable the TIM Capture/Compare 3 DMA request */
2578 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2579 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2580 break;
2581 }
2582
2583 case TIM_CHANNEL_4:
2584 {
2585 /* Disable the TIM Capture/Compare 4 DMA request */
2586 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2587 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2588 break;
2589 }
2590
2591 default:
2592 status = HAL_ERROR;
2593 break;
2594 }
2595
2596 if (status == HAL_OK)
2597 {
2598 /* Disable the Peripheral */
2599 __HAL_TIM_DISABLE(htim);
2600
2601 /* Set the TIM channel state */
2602 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2603 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2604 }
2605
2606 /* Return function status */
2607 return status;
2608 }
2609 /**
2610 * @}
2611 */
2612
2613 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2614 * @brief TIM One Pulse functions
2615 *
2616 @verbatim
2617 ==============================================================================
2618 ##### TIM One Pulse functions #####
2619 ==============================================================================
2620 [..]
2621 This section provides functions allowing to:
2622 (+) Initialize and configure the TIM One Pulse.
2623 (+) De-initialize the TIM One Pulse.
2624 (+) Start the TIM One Pulse.
2625 (+) Stop the TIM One Pulse.
2626 (+) Start the TIM One Pulse and enable interrupt.
2627 (+) Stop the TIM One Pulse and disable interrupt.
2628 (+) Start the TIM One Pulse and enable DMA transfer.
2629 (+) Stop the TIM One Pulse and disable DMA transfer.
2630
2631 @endverbatim
2632 * @{
2633 */
2634 /**
2635 * @brief Initializes the TIM One Pulse Time Base according to the specified
2636 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2637 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2638 * requires a timer reset to avoid unexpected direction
2639 * due to DIR bit readonly in center aligned mode.
2640 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2641 * @note When the timer instance is initialized in One Pulse mode, timer
2642 * channels 1 and channel 2 are reserved and cannot be used for other
2643 * purpose.
2644 * @param htim TIM One Pulse handle
2645 * @param OnePulseMode Select the One pulse mode.
2646 * This parameter can be one of the following values:
2647 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2648 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2649 * @retval HAL status
2650 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2651 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2652 {
2653 /* Check the TIM handle allocation */
2654 if (htim == NULL)
2655 {
2656 return HAL_ERROR;
2657 }
2658
2659 /* Check the parameters */
2660 assert_param(IS_TIM_INSTANCE(htim->Instance));
2661 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2662 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2663 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2664 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2665 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2666
2667 if (htim->State == HAL_TIM_STATE_RESET)
2668 {
2669 /* Allocate lock resource and initialize it */
2670 htim->Lock = HAL_UNLOCKED;
2671
2672 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2673 /* Reset interrupt callbacks to legacy weak callbacks */
2674 TIM_ResetCallback(htim);
2675
2676 if (htim->OnePulse_MspInitCallback == NULL)
2677 {
2678 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2679 }
2680 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2681 htim->OnePulse_MspInitCallback(htim);
2682 #else
2683 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2684 HAL_TIM_OnePulse_MspInit(htim);
2685 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2686 }
2687
2688 /* Set the TIM state */
2689 htim->State = HAL_TIM_STATE_BUSY;
2690
2691 /* Configure the Time base in the One Pulse Mode */
2692 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2693
2694 /* Reset the OPM Bit */
2695 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2696
2697 /* Configure the OPM Mode */
2698 htim->Instance->CR1 |= OnePulseMode;
2699
2700 /* Initialize the DMA burst operation state */
2701 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2702
2703 /* Initialize the TIM channels state */
2704 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2705 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2706 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2707 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2708
2709 /* Initialize the TIM state*/
2710 htim->State = HAL_TIM_STATE_READY;
2711
2712 return HAL_OK;
2713 }
2714
2715 /**
2716 * @brief DeInitializes the TIM One Pulse
2717 * @param htim TIM One Pulse handle
2718 * @retval HAL status
2719 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2720 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2721 {
2722 /* Check the parameters */
2723 assert_param(IS_TIM_INSTANCE(htim->Instance));
2724
2725 htim->State = HAL_TIM_STATE_BUSY;
2726
2727 /* Disable the TIM Peripheral Clock */
2728 __HAL_TIM_DISABLE(htim);
2729
2730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2731 if (htim->OnePulse_MspDeInitCallback == NULL)
2732 {
2733 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2734 }
2735 /* DeInit the low level hardware */
2736 htim->OnePulse_MspDeInitCallback(htim);
2737 #else
2738 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2739 HAL_TIM_OnePulse_MspDeInit(htim);
2740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2741
2742 /* Change the DMA burst operation state */
2743 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2744
2745 /* Set the TIM channel state */
2746 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2747 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2748 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2749 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2750
2751 /* Change TIM state */
2752 htim->State = HAL_TIM_STATE_RESET;
2753
2754 /* Release Lock */
2755 __HAL_UNLOCK(htim);
2756
2757 return HAL_OK;
2758 }
2759
2760 /**
2761 * @brief Initializes the TIM One Pulse MSP.
2762 * @param htim TIM One Pulse handle
2763 * @retval None
2764 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2765 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2766 {
2767 /* Prevent unused argument(s) compilation warning */
2768 UNUSED(htim);
2769
2770 /* NOTE : This function should not be modified, when the callback is needed,
2771 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2772 */
2773 }
2774
2775 /**
2776 * @brief DeInitializes TIM One Pulse MSP.
2777 * @param htim TIM One Pulse handle
2778 * @retval None
2779 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2780 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2781 {
2782 /* Prevent unused argument(s) compilation warning */
2783 UNUSED(htim);
2784
2785 /* NOTE : This function should not be modified, when the callback is needed,
2786 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2787 */
2788 }
2789
2790 /**
2791 * @brief Starts the TIM One Pulse signal generation.
2792 * @note Though OutputChannel parameter is deprecated and ignored by the function
2793 * it has been kept to avoid HAL_TIM API compatibility break.
2794 * @note The pulse output channel is determined when calling
2795 * @ref HAL_TIM_OnePulse_ConfigChannel().
2796 * @param htim TIM One Pulse handle
2797 * @param OutputChannel See note above
2798 * @retval HAL status
2799 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2800 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2801 {
2802 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2803 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2804 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2805 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2806
2807 /* Prevent unused argument(s) compilation warning */
2808 UNUSED(OutputChannel);
2809
2810 /* Check the TIM channels state */
2811 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2812 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2813 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2814 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2815 {
2816 return HAL_ERROR;
2817 }
2818
2819 /* Set the TIM channels state */
2820 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2821 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2822 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2823 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2824
2825 /* Enable the Capture compare and the Input Capture channels
2826 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2827 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2828 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2829 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2830
2831 No need to enable the counter, it's enabled automatically by hardware
2832 (the counter starts in response to a stimulus and generate a pulse */
2833
2834 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2835 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2836
2837 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2838 {
2839 /* Enable the main output */
2840 __HAL_TIM_MOE_ENABLE(htim);
2841 }
2842
2843 /* Return function status */
2844 return HAL_OK;
2845 }
2846
2847 /**
2848 * @brief Stops the TIM One Pulse signal generation.
2849 * @note Though OutputChannel parameter is deprecated and ignored by the function
2850 * it has been kept to avoid HAL_TIM API compatibility break.
2851 * @note The pulse output channel is determined when calling
2852 * @ref HAL_TIM_OnePulse_ConfigChannel().
2853 * @param htim TIM One Pulse handle
2854 * @param OutputChannel See note above
2855 * @retval HAL status
2856 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2857 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2858 {
2859 /* Prevent unused argument(s) compilation warning */
2860 UNUSED(OutputChannel);
2861
2862 /* Disable the Capture compare and the Input Capture channels
2863 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2864 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2865 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2866 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2867
2868 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2869 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2870
2871 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2872 {
2873 /* Disable the Main Output */
2874 __HAL_TIM_MOE_DISABLE(htim);
2875 }
2876
2877 /* Disable the Peripheral */
2878 __HAL_TIM_DISABLE(htim);
2879
2880 /* Set the TIM channels state */
2881 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2882 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2883 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2884 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2885
2886 /* Return function status */
2887 return HAL_OK;
2888 }
2889
2890 /**
2891 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2892 * @note Though OutputChannel parameter is deprecated and ignored by the function
2893 * it has been kept to avoid HAL_TIM API compatibility break.
2894 * @note The pulse output channel is determined when calling
2895 * @ref HAL_TIM_OnePulse_ConfigChannel().
2896 * @param htim TIM One Pulse handle
2897 * @param OutputChannel See note above
2898 * @retval HAL status
2899 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2900 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2901 {
2902 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2903 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2904 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2905 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2906
2907 /* Prevent unused argument(s) compilation warning */
2908 UNUSED(OutputChannel);
2909
2910 /* Check the TIM channels state */
2911 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2912 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2913 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2914 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2915 {
2916 return HAL_ERROR;
2917 }
2918
2919 /* Set the TIM channels state */
2920 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2921 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2922 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2923 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2924
2925 /* Enable the Capture compare and the Input Capture channels
2926 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2927 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2928 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2929 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2930
2931 No need to enable the counter, it's enabled automatically by hardware
2932 (the counter starts in response to a stimulus and generate a pulse */
2933
2934 /* Enable the TIM Capture/Compare 1 interrupt */
2935 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2936
2937 /* Enable the TIM Capture/Compare 2 interrupt */
2938 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2939
2940 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2941 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2942
2943 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2944 {
2945 /* Enable the main output */
2946 __HAL_TIM_MOE_ENABLE(htim);
2947 }
2948
2949 /* Return function status */
2950 return HAL_OK;
2951 }
2952
2953 /**
2954 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2955 * @note Though OutputChannel parameter is deprecated and ignored by the function
2956 * it has been kept to avoid HAL_TIM API compatibility break.
2957 * @note The pulse output channel is determined when calling
2958 * @ref HAL_TIM_OnePulse_ConfigChannel().
2959 * @param htim TIM One Pulse handle
2960 * @param OutputChannel See note above
2961 * @retval HAL status
2962 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2964 {
2965 /* Prevent unused argument(s) compilation warning */
2966 UNUSED(OutputChannel);
2967
2968 /* Disable the TIM Capture/Compare 1 interrupt */
2969 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2970
2971 /* Disable the TIM Capture/Compare 2 interrupt */
2972 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2973
2974 /* Disable the Capture compare and the Input Capture channels
2975 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2976 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2977 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2978 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2979 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2980 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2981
2982 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2983 {
2984 /* Disable the Main Output */
2985 __HAL_TIM_MOE_DISABLE(htim);
2986 }
2987
2988 /* Disable the Peripheral */
2989 __HAL_TIM_DISABLE(htim);
2990
2991 /* Set the TIM channels state */
2992 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2993 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2994 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2995 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2996
2997 /* Return function status */
2998 return HAL_OK;
2999 }
3000
3001 /**
3002 * @}
3003 */
3004
3005 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3006 * @brief TIM Encoder functions
3007 *
3008 @verbatim
3009 ==============================================================================
3010 ##### TIM Encoder functions #####
3011 ==============================================================================
3012 [..]
3013 This section provides functions allowing to:
3014 (+) Initialize and configure the TIM Encoder.
3015 (+) De-initialize the TIM Encoder.
3016 (+) Start the TIM Encoder.
3017 (+) Stop the TIM Encoder.
3018 (+) Start the TIM Encoder and enable interrupt.
3019 (+) Stop the TIM Encoder and disable interrupt.
3020 (+) Start the TIM Encoder and enable DMA transfer.
3021 (+) Stop the TIM Encoder and disable DMA transfer.
3022
3023 @endverbatim
3024 * @{
3025 */
3026 /**
3027 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3028 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3029 * requires a timer reset to avoid unexpected direction
3030 * due to DIR bit readonly in center aligned mode.
3031 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3032 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3033 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3034 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3035 * @note When the timer instance is initialized in Encoder mode, timer
3036 * channels 1 and channel 2 are reserved and cannot be used for other
3037 * purpose.
3038 * @param htim TIM Encoder Interface handle
3039 * @param sConfig TIM Encoder Interface configuration structure
3040 * @retval HAL status
3041 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)3042 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
3043 {
3044 uint32_t tmpsmcr;
3045 uint32_t tmpccmr1;
3046 uint32_t tmpccer;
3047
3048 /* Check the TIM handle allocation */
3049 if (htim == NULL)
3050 {
3051 return HAL_ERROR;
3052 }
3053
3054 /* Check the parameters */
3055 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3056 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3057 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3058 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3059 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3060 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3061 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3062 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3063 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3064 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3065 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3066 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3067 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3068 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3069
3070 if (htim->State == HAL_TIM_STATE_RESET)
3071 {
3072 /* Allocate lock resource and initialize it */
3073 htim->Lock = HAL_UNLOCKED;
3074
3075 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3076 /* Reset interrupt callbacks to legacy weak callbacks */
3077 TIM_ResetCallback(htim);
3078
3079 if (htim->Encoder_MspInitCallback == NULL)
3080 {
3081 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3082 }
3083 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3084 htim->Encoder_MspInitCallback(htim);
3085 #else
3086 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3087 HAL_TIM_Encoder_MspInit(htim);
3088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3089 }
3090
3091 /* Set the TIM state */
3092 htim->State = HAL_TIM_STATE_BUSY;
3093
3094 /* Reset the SMS and ECE bits */
3095 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3096
3097 /* Configure the Time base in the Encoder Mode */
3098 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3099
3100 /* Get the TIMx SMCR register value */
3101 tmpsmcr = htim->Instance->SMCR;
3102
3103 /* Get the TIMx CCMR1 register value */
3104 tmpccmr1 = htim->Instance->CCMR1;
3105
3106 /* Get the TIMx CCER register value */
3107 tmpccer = htim->Instance->CCER;
3108
3109 /* Set the encoder Mode */
3110 tmpsmcr |= sConfig->EncoderMode;
3111
3112 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3113 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3114 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3115
3116 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3117 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3118 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3119 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3120 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3121
3122 /* Set the TI1 and the TI2 Polarities */
3123 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3124 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3125 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3126
3127 /* Write to TIMx SMCR */
3128 htim->Instance->SMCR = tmpsmcr;
3129
3130 /* Write to TIMx CCMR1 */
3131 htim->Instance->CCMR1 = tmpccmr1;
3132
3133 /* Write to TIMx CCER */
3134 htim->Instance->CCER = tmpccer;
3135
3136 /* Initialize the DMA burst operation state */
3137 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3138
3139 /* Set the TIM channels state */
3140 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3141 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3142 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3143 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3144
3145 /* Initialize the TIM state*/
3146 htim->State = HAL_TIM_STATE_READY;
3147
3148 return HAL_OK;
3149 }
3150
3151
3152 /**
3153 * @brief DeInitializes the TIM Encoder interface
3154 * @param htim TIM Encoder Interface handle
3155 * @retval HAL status
3156 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3157 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3158 {
3159 /* Check the parameters */
3160 assert_param(IS_TIM_INSTANCE(htim->Instance));
3161
3162 htim->State = HAL_TIM_STATE_BUSY;
3163
3164 /* Disable the TIM Peripheral Clock */
3165 __HAL_TIM_DISABLE(htim);
3166
3167 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3168 if (htim->Encoder_MspDeInitCallback == NULL)
3169 {
3170 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3171 }
3172 /* DeInit the low level hardware */
3173 htim->Encoder_MspDeInitCallback(htim);
3174 #else
3175 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3176 HAL_TIM_Encoder_MspDeInit(htim);
3177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3178
3179 /* Change the DMA burst operation state */
3180 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3181
3182 /* Set the TIM channels state */
3183 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3184 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3185 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3186 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3187
3188 /* Change TIM state */
3189 htim->State = HAL_TIM_STATE_RESET;
3190
3191 /* Release Lock */
3192 __HAL_UNLOCK(htim);
3193
3194 return HAL_OK;
3195 }
3196
3197 /**
3198 * @brief Initializes the TIM Encoder Interface MSP.
3199 * @param htim TIM Encoder Interface handle
3200 * @retval None
3201 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3202 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3203 {
3204 /* Prevent unused argument(s) compilation warning */
3205 UNUSED(htim);
3206
3207 /* NOTE : This function should not be modified, when the callback is needed,
3208 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3209 */
3210 }
3211
3212 /**
3213 * @brief DeInitializes TIM Encoder Interface MSP.
3214 * @param htim TIM Encoder Interface handle
3215 * @retval None
3216 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3217 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3218 {
3219 /* Prevent unused argument(s) compilation warning */
3220 UNUSED(htim);
3221
3222 /* NOTE : This function should not be modified, when the callback is needed,
3223 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3224 */
3225 }
3226
3227 /**
3228 * @brief Starts the TIM Encoder Interface.
3229 * @param htim TIM Encoder Interface handle
3230 * @param Channel TIM Channels to be enabled
3231 * This parameter can be one of the following values:
3232 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3233 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3234 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3235 * @retval HAL status
3236 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3237 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3238 {
3239 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3240 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3241 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3242 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3243
3244 /* Check the parameters */
3245 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3246
3247 /* Set the TIM channel(s) state */
3248 if (Channel == TIM_CHANNEL_1)
3249 {
3250 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3251 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3252 {
3253 return HAL_ERROR;
3254 }
3255 else
3256 {
3257 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3258 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3259 }
3260 }
3261 else if (Channel == TIM_CHANNEL_2)
3262 {
3263 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3264 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3265 {
3266 return HAL_ERROR;
3267 }
3268 else
3269 {
3270 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3271 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3272 }
3273 }
3274 else
3275 {
3276 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3277 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3278 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3279 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3280 {
3281 return HAL_ERROR;
3282 }
3283 else
3284 {
3285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3289 }
3290 }
3291
3292 /* Enable the encoder interface channels */
3293 switch (Channel)
3294 {
3295 case TIM_CHANNEL_1:
3296 {
3297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3298 break;
3299 }
3300
3301 case TIM_CHANNEL_2:
3302 {
3303 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3304 break;
3305 }
3306
3307 default :
3308 {
3309 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3310 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3311 break;
3312 }
3313 }
3314 /* Enable the Peripheral */
3315 __HAL_TIM_ENABLE(htim);
3316
3317 /* Return function status */
3318 return HAL_OK;
3319 }
3320
3321 /**
3322 * @brief Stops the TIM Encoder Interface.
3323 * @param htim TIM Encoder Interface handle
3324 * @param Channel TIM Channels to be disabled
3325 * This parameter can be one of the following values:
3326 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3327 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3328 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3329 * @retval HAL status
3330 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3331 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3332 {
3333 /* Check the parameters */
3334 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3335
3336 /* Disable the Input Capture channels 1 and 2
3337 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3338 switch (Channel)
3339 {
3340 case TIM_CHANNEL_1:
3341 {
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3343 break;
3344 }
3345
3346 case TIM_CHANNEL_2:
3347 {
3348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3349 break;
3350 }
3351
3352 default :
3353 {
3354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3355 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3356 break;
3357 }
3358 }
3359
3360 /* Disable the Peripheral */
3361 __HAL_TIM_DISABLE(htim);
3362
3363 /* Set the TIM channel(s) state */
3364 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3365 {
3366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3368 }
3369 else
3370 {
3371 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3372 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3373 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3374 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3375 }
3376
3377 /* Return function status */
3378 return HAL_OK;
3379 }
3380
3381 /**
3382 * @brief Starts the TIM Encoder Interface in interrupt mode.
3383 * @param htim TIM Encoder Interface handle
3384 * @param Channel TIM Channels to be enabled
3385 * This parameter can be one of the following values:
3386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3389 * @retval HAL status
3390 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3391 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3392 {
3393 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3394 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3395 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3396 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3397
3398 /* Check the parameters */
3399 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3400
3401 /* Set the TIM channel(s) state */
3402 if (Channel == TIM_CHANNEL_1)
3403 {
3404 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3405 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3406 {
3407 return HAL_ERROR;
3408 }
3409 else
3410 {
3411 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3412 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3413 }
3414 }
3415 else if (Channel == TIM_CHANNEL_2)
3416 {
3417 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3418 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3419 {
3420 return HAL_ERROR;
3421 }
3422 else
3423 {
3424 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3425 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3426 }
3427 }
3428 else
3429 {
3430 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3431 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3432 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3433 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3434 {
3435 return HAL_ERROR;
3436 }
3437 else
3438 {
3439 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3440 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3441 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3442 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3443 }
3444 }
3445
3446 /* Enable the encoder interface channels */
3447 /* Enable the capture compare Interrupts 1 and/or 2 */
3448 switch (Channel)
3449 {
3450 case TIM_CHANNEL_1:
3451 {
3452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3453 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3454 break;
3455 }
3456
3457 case TIM_CHANNEL_2:
3458 {
3459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3461 break;
3462 }
3463
3464 default :
3465 {
3466 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3468 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3469 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3470 break;
3471 }
3472 }
3473
3474 /* Enable the Peripheral */
3475 __HAL_TIM_ENABLE(htim);
3476
3477 /* Return function status */
3478 return HAL_OK;
3479 }
3480
3481 /**
3482 * @brief Stops the TIM Encoder Interface in interrupt mode.
3483 * @param htim TIM Encoder Interface handle
3484 * @param Channel TIM Channels to be disabled
3485 * This parameter can be one of the following values:
3486 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3487 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3488 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3489 * @retval HAL status
3490 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3492 {
3493 /* Check the parameters */
3494 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3495
3496 /* Disable the Input Capture channels 1 and 2
3497 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3498 if (Channel == TIM_CHANNEL_1)
3499 {
3500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3501
3502 /* Disable the capture compare Interrupts 1 */
3503 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3504 }
3505 else if (Channel == TIM_CHANNEL_2)
3506 {
3507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3508
3509 /* Disable the capture compare Interrupts 2 */
3510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3511 }
3512 else
3513 {
3514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3516
3517 /* Disable the capture compare Interrupts 1 and 2 */
3518 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3519 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3520 }
3521
3522 /* Disable the Peripheral */
3523 __HAL_TIM_DISABLE(htim);
3524
3525 /* Set the TIM channel(s) state */
3526 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3527 {
3528 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3529 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3530 }
3531 else
3532 {
3533 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3534 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3535 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3536 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3537 }
3538
3539 /* Return function status */
3540 return HAL_OK;
3541 }
3542
3543 /**
3544 * @brief Starts the TIM Encoder Interface in DMA mode.
3545 * @param htim TIM Encoder Interface handle
3546 * @param Channel TIM Channels to be enabled
3547 * This parameter can be one of the following values:
3548 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3549 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3550 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3551 * @param pData1 The destination Buffer address for IC1.
3552 * @param pData2 The destination Buffer address for IC2.
3553 * @param Length The length of data to be transferred from TIM peripheral to memory.
3554 * @retval HAL status
3555 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3556 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3557 uint32_t *pData2, uint16_t Length)
3558 {
3559 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3560 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3561 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3562 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3563
3564 /* Check the parameters */
3565 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3566
3567 /* Set the TIM channel(s) state */
3568 if (Channel == TIM_CHANNEL_1)
3569 {
3570 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3571 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3572 {
3573 return HAL_BUSY;
3574 }
3575 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3576 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3577 {
3578 if ((pData1 == NULL) || (Length == 0U))
3579 {
3580 return HAL_ERROR;
3581 }
3582 else
3583 {
3584 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3585 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3586 }
3587 }
3588 else
3589 {
3590 return HAL_ERROR;
3591 }
3592 }
3593 else if (Channel == TIM_CHANNEL_2)
3594 {
3595 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3596 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3597 {
3598 return HAL_BUSY;
3599 }
3600 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3601 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3602 {
3603 if ((pData2 == NULL) || (Length == 0U))
3604 {
3605 return HAL_ERROR;
3606 }
3607 else
3608 {
3609 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3611 }
3612 }
3613 else
3614 {
3615 return HAL_ERROR;
3616 }
3617 }
3618 else
3619 {
3620 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3621 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3622 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3623 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3624 {
3625 return HAL_BUSY;
3626 }
3627 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3628 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3629 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3630 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3631 {
3632 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3633 {
3634 return HAL_ERROR;
3635 }
3636 else
3637 {
3638 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3640 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3641 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3642 }
3643 }
3644 else
3645 {
3646 return HAL_ERROR;
3647 }
3648 }
3649
3650 switch (Channel)
3651 {
3652 case TIM_CHANNEL_1:
3653 {
3654 /* Set the DMA capture callbacks */
3655 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3656 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3657
3658 /* Set the DMA error callback */
3659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3660
3661 /* Enable the DMA channel */
3662 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3663 Length) != HAL_OK)
3664 {
3665 /* Return error status */
3666 return HAL_ERROR;
3667 }
3668 /* Enable the TIM Input Capture DMA request */
3669 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3670
3671 /* Enable the Capture compare channel */
3672 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3673
3674 /* Enable the Peripheral */
3675 __HAL_TIM_ENABLE(htim);
3676
3677 break;
3678 }
3679
3680 case TIM_CHANNEL_2:
3681 {
3682 /* Set the DMA capture callbacks */
3683 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3684 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3685
3686 /* Set the DMA error callback */
3687 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3688 /* Enable the DMA channel */
3689 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3690 Length) != HAL_OK)
3691 {
3692 /* Return error status */
3693 return HAL_ERROR;
3694 }
3695 /* Enable the TIM Input Capture DMA request */
3696 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3697
3698 /* Enable the Capture compare channel */
3699 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3700
3701 /* Enable the Peripheral */
3702 __HAL_TIM_ENABLE(htim);
3703
3704 break;
3705 }
3706
3707 default:
3708 {
3709 /* Set the DMA capture callbacks */
3710 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3711 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3712
3713 /* Set the DMA error callback */
3714 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3715
3716 /* Enable the DMA channel */
3717 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3718 Length) != HAL_OK)
3719 {
3720 /* Return error status */
3721 return HAL_ERROR;
3722 }
3723
3724 /* Set the DMA capture callbacks */
3725 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3726 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3727
3728 /* Set the DMA error callback */
3729 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3730
3731 /* Enable the DMA channel */
3732 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3733 Length) != HAL_OK)
3734 {
3735 /* Return error status */
3736 return HAL_ERROR;
3737 }
3738
3739 /* Enable the TIM Input Capture DMA request */
3740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3741 /* Enable the TIM Input Capture DMA request */
3742 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3743
3744 /* Enable the Capture compare channel */
3745 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3746 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3747
3748 /* Enable the Peripheral */
3749 __HAL_TIM_ENABLE(htim);
3750
3751 break;
3752 }
3753 }
3754
3755 /* Return function status */
3756 return HAL_OK;
3757 }
3758
3759 /**
3760 * @brief Stops the TIM Encoder Interface in DMA mode.
3761 * @param htim TIM Encoder Interface handle
3762 * @param Channel TIM Channels to be enabled
3763 * This parameter can be one of the following values:
3764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3766 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3767 * @retval HAL status
3768 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3769 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3770 {
3771 /* Check the parameters */
3772 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3773
3774 /* Disable the Input Capture channels 1 and 2
3775 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3776 if (Channel == TIM_CHANNEL_1)
3777 {
3778 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3779
3780 /* Disable the capture compare DMA Request 1 */
3781 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3782 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3783 }
3784 else if (Channel == TIM_CHANNEL_2)
3785 {
3786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3787
3788 /* Disable the capture compare DMA Request 2 */
3789 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3790 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3791 }
3792 else
3793 {
3794 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3795 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3796
3797 /* Disable the capture compare DMA Request 1 and 2 */
3798 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3799 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3800 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3801 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3802 }
3803
3804 /* Disable the Peripheral */
3805 __HAL_TIM_DISABLE(htim);
3806
3807 /* Set the TIM channel(s) state */
3808 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3809 {
3810 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3811 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3812 }
3813 else
3814 {
3815 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3817 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3819 }
3820
3821 /* Return function status */
3822 return HAL_OK;
3823 }
3824
3825 /**
3826 * @}
3827 */
3828 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3829 * @brief TIM IRQ handler management
3830 *
3831 @verbatim
3832 ==============================================================================
3833 ##### IRQ handler management #####
3834 ==============================================================================
3835 [..]
3836 This section provides Timer IRQ handler function.
3837
3838 @endverbatim
3839 * @{
3840 */
3841 /**
3842 * @brief This function handles TIM interrupts requests.
3843 * @param htim TIM handle
3844 * @retval None
3845 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3846 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3847 {
3848 uint32_t itsource = htim->Instance->DIER;
3849 uint32_t itflag = htim->Instance->SR;
3850
3851 /* Capture compare 1 event */
3852 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3853 {
3854 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3855 {
3856 {
3857 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3858 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3859
3860 /* Input capture event */
3861 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3862 {
3863 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3864 htim->IC_CaptureCallback(htim);
3865 #else
3866 HAL_TIM_IC_CaptureCallback(htim);
3867 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3868 }
3869 /* Output compare event */
3870 else
3871 {
3872 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3873 htim->OC_DelayElapsedCallback(htim);
3874 htim->PWM_PulseFinishedCallback(htim);
3875 #else
3876 HAL_TIM_OC_DelayElapsedCallback(htim);
3877 HAL_TIM_PWM_PulseFinishedCallback(htim);
3878 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3879 }
3880 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3881 }
3882 }
3883 }
3884 /* Capture compare 2 event */
3885 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3886 {
3887 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3888 {
3889 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3890 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3891 /* Input capture event */
3892 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3893 {
3894 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3895 htim->IC_CaptureCallback(htim);
3896 #else
3897 HAL_TIM_IC_CaptureCallback(htim);
3898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3899 }
3900 /* Output compare event */
3901 else
3902 {
3903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3904 htim->OC_DelayElapsedCallback(htim);
3905 htim->PWM_PulseFinishedCallback(htim);
3906 #else
3907 HAL_TIM_OC_DelayElapsedCallback(htim);
3908 HAL_TIM_PWM_PulseFinishedCallback(htim);
3909 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3910 }
3911 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3912 }
3913 }
3914 /* Capture compare 3 event */
3915 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3916 {
3917 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3918 {
3919 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3920 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3921 /* Input capture event */
3922 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3923 {
3924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3925 htim->IC_CaptureCallback(htim);
3926 #else
3927 HAL_TIM_IC_CaptureCallback(htim);
3928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3929 }
3930 /* Output compare event */
3931 else
3932 {
3933 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3934 htim->OC_DelayElapsedCallback(htim);
3935 htim->PWM_PulseFinishedCallback(htim);
3936 #else
3937 HAL_TIM_OC_DelayElapsedCallback(htim);
3938 HAL_TIM_PWM_PulseFinishedCallback(htim);
3939 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3940 }
3941 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3942 }
3943 }
3944 /* Capture compare 4 event */
3945 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3946 {
3947 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3948 {
3949 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3950 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3951 /* Input capture event */
3952 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3953 {
3954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3955 htim->IC_CaptureCallback(htim);
3956 #else
3957 HAL_TIM_IC_CaptureCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959 }
3960 /* Output compare event */
3961 else
3962 {
3963 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3964 htim->OC_DelayElapsedCallback(htim);
3965 htim->PWM_PulseFinishedCallback(htim);
3966 #else
3967 HAL_TIM_OC_DelayElapsedCallback(htim);
3968 HAL_TIM_PWM_PulseFinishedCallback(htim);
3969 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3970 }
3971 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3972 }
3973 }
3974 /* TIM Update event */
3975 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3976 {
3977 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3978 {
3979 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3981 htim->PeriodElapsedCallback(htim);
3982 #else
3983 HAL_TIM_PeriodElapsedCallback(htim);
3984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3985 }
3986 }
3987 /* TIM Break input event */
3988 if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
3989 {
3990 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3991 {
3992 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3993 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3994 htim->BreakCallback(htim);
3995 #else
3996 HAL_TIMEx_BreakCallback(htim);
3997 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3998 }
3999 }
4000 /* TIM Break2 input event */
4001 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
4002 {
4003 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4004 {
4005 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4006 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4007 htim->Break2Callback(htim);
4008 #else
4009 HAL_TIMEx_Break2Callback(htim);
4010 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4011 }
4012 }
4013 /* TIM Trigger detection event */
4014 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4015 {
4016 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4017 {
4018 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
4019 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4020 htim->TriggerCallback(htim);
4021 #else
4022 HAL_TIM_TriggerCallback(htim);
4023 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4024 }
4025 }
4026 /* TIM commutation event */
4027 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4028 {
4029 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4030 {
4031 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
4032 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4033 htim->CommutationCallback(htim);
4034 #else
4035 HAL_TIMEx_CommutCallback(htim);
4036 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4037 }
4038 }
4039 /* TIM Encoder index event */
4040 if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
4041 {
4042 if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
4043 {
4044 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
4045 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4046 htim->EncoderIndexCallback(htim);
4047 #else
4048 HAL_TIMEx_EncoderIndexCallback(htim);
4049 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4050 }
4051 }
4052 /* TIM Direction change event */
4053 if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
4054 {
4055 if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
4056 {
4057 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
4058 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4059 htim->DirectionChangeCallback(htim);
4060 #else
4061 HAL_TIMEx_DirectionChangeCallback(htim);
4062 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4063 }
4064 }
4065 /* TIM Index error event */
4066 if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
4067 {
4068 if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
4069 {
4070 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
4071 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4072 htim->IndexErrorCallback(htim);
4073 #else
4074 HAL_TIMEx_IndexErrorCallback(htim);
4075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4076 }
4077 }
4078 /* TIM Transition error event */
4079 if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
4080 {
4081 if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
4082 {
4083 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
4084 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4085 htim->TransitionErrorCallback(htim);
4086 #else
4087 HAL_TIMEx_TransitionErrorCallback(htim);
4088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4089 }
4090 }
4091 }
4092
4093 /**
4094 * @}
4095 */
4096
4097 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4098 * @brief TIM Peripheral Control functions
4099 *
4100 @verbatim
4101 ==============================================================================
4102 ##### Peripheral Control functions #####
4103 ==============================================================================
4104 [..]
4105 This section provides functions allowing to:
4106 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4107 (+) Configure External Clock source.
4108 (+) Configure Complementary channels, break features and dead time.
4109 (+) Configure Master and the Slave synchronization.
4110 (+) Configure the DMA Burst Mode.
4111
4112 @endverbatim
4113 * @{
4114 */
4115
4116 /**
4117 * @brief Initializes the TIM Output Compare Channels according to the specified
4118 * parameters in the TIM_OC_InitTypeDef.
4119 * @param htim TIM Output Compare handle
4120 * @param sConfig TIM Output Compare configuration structure
4121 * @param Channel TIM Channels to configure
4122 * This parameter can be one of the following values:
4123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4127 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4128 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4129 * @retval HAL status
4130 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4131 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4132 const TIM_OC_InitTypeDef *sConfig,
4133 uint32_t Channel)
4134 {
4135 HAL_StatusTypeDef status = HAL_OK;
4136
4137 /* Check the parameters */
4138 assert_param(IS_TIM_CHANNELS(Channel));
4139 assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
4140 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4141
4142 /* Process Locked */
4143 __HAL_LOCK(htim);
4144
4145 switch (Channel)
4146 {
4147 case TIM_CHANNEL_1:
4148 {
4149 /* Check the parameters */
4150 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4151
4152 /* Configure the TIM Channel 1 in Output Compare */
4153 TIM_OC1_SetConfig(htim->Instance, sConfig);
4154 break;
4155 }
4156
4157 case TIM_CHANNEL_2:
4158 {
4159 /* Check the parameters */
4160 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4161
4162 /* Configure the TIM Channel 2 in Output Compare */
4163 TIM_OC2_SetConfig(htim->Instance, sConfig);
4164 break;
4165 }
4166
4167 case TIM_CHANNEL_3:
4168 {
4169 /* Check the parameters */
4170 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4171
4172 /* Configure the TIM Channel 3 in Output Compare */
4173 TIM_OC3_SetConfig(htim->Instance, sConfig);
4174 break;
4175 }
4176
4177 case TIM_CHANNEL_4:
4178 {
4179 /* Check the parameters */
4180 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4181
4182 /* Configure the TIM Channel 4 in Output Compare */
4183 TIM_OC4_SetConfig(htim->Instance, sConfig);
4184 break;
4185 }
4186
4187 case TIM_CHANNEL_5:
4188 {
4189 /* Check the parameters */
4190 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4191
4192 /* Configure the TIM Channel 5 in Output Compare */
4193 TIM_OC5_SetConfig(htim->Instance, sConfig);
4194 break;
4195 }
4196
4197 case TIM_CHANNEL_6:
4198 {
4199 /* Check the parameters */
4200 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4201
4202 /* Configure the TIM Channel 6 in Output Compare */
4203 TIM_OC6_SetConfig(htim->Instance, sConfig);
4204 break;
4205 }
4206
4207 default:
4208 status = HAL_ERROR;
4209 break;
4210 }
4211
4212 __HAL_UNLOCK(htim);
4213
4214 return status;
4215 }
4216
4217 /**
4218 * @brief Initializes the TIM Input Capture Channels according to the specified
4219 * parameters in the TIM_IC_InitTypeDef.
4220 * @param htim TIM IC handle
4221 * @param sConfig TIM Input Capture configuration structure
4222 * @param Channel TIM Channel to configure
4223 * This parameter can be one of the following values:
4224 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4225 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4226 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4227 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4228 * @retval HAL status
4229 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4230 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4231 {
4232 HAL_StatusTypeDef status = HAL_OK;
4233
4234 /* Check the parameters */
4235 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4236 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4237 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4238 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4239 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4240
4241 /* Process Locked */
4242 __HAL_LOCK(htim);
4243
4244 if (Channel == TIM_CHANNEL_1)
4245 {
4246 /* TI1 Configuration */
4247 TIM_TI1_SetConfig(htim->Instance,
4248 sConfig->ICPolarity,
4249 sConfig->ICSelection,
4250 sConfig->ICFilter);
4251
4252 /* Reset the IC1PSC Bits */
4253 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4254
4255 /* Set the IC1PSC value */
4256 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4257 }
4258 else if (Channel == TIM_CHANNEL_2)
4259 {
4260 /* TI2 Configuration */
4261 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4262
4263 TIM_TI2_SetConfig(htim->Instance,
4264 sConfig->ICPolarity,
4265 sConfig->ICSelection,
4266 sConfig->ICFilter);
4267
4268 /* Reset the IC2PSC Bits */
4269 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4270
4271 /* Set the IC2PSC value */
4272 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4273 }
4274 else if (Channel == TIM_CHANNEL_3)
4275 {
4276 /* TI3 Configuration */
4277 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4278
4279 TIM_TI3_SetConfig(htim->Instance,
4280 sConfig->ICPolarity,
4281 sConfig->ICSelection,
4282 sConfig->ICFilter);
4283
4284 /* Reset the IC3PSC Bits */
4285 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4286
4287 /* Set the IC3PSC value */
4288 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4289 }
4290 else if (Channel == TIM_CHANNEL_4)
4291 {
4292 /* TI4 Configuration */
4293 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4294
4295 TIM_TI4_SetConfig(htim->Instance,
4296 sConfig->ICPolarity,
4297 sConfig->ICSelection,
4298 sConfig->ICFilter);
4299
4300 /* Reset the IC4PSC Bits */
4301 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4302
4303 /* Set the IC4PSC value */
4304 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4305 }
4306 else
4307 {
4308 status = HAL_ERROR;
4309 }
4310
4311 __HAL_UNLOCK(htim);
4312
4313 return status;
4314 }
4315
4316 /**
4317 * @brief Initializes the TIM PWM channels according to the specified
4318 * parameters in the TIM_OC_InitTypeDef.
4319 * @param htim TIM PWM handle
4320 * @param sConfig TIM PWM configuration structure
4321 * @param Channel TIM Channels to be configured
4322 * This parameter can be one of the following values:
4323 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4324 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4325 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4326 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4327 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4328 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4329 * @retval HAL status
4330 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4331 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4332 const TIM_OC_InitTypeDef *sConfig,
4333 uint32_t Channel)
4334 {
4335 HAL_StatusTypeDef status = HAL_OK;
4336
4337 /* Check the parameters */
4338 assert_param(IS_TIM_CHANNELS(Channel));
4339 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4340 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4341 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4342
4343 /* Process Locked */
4344 __HAL_LOCK(htim);
4345
4346 switch (Channel)
4347 {
4348 case TIM_CHANNEL_1:
4349 {
4350 /* Check the parameters */
4351 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4352
4353 /* Configure the Channel 1 in PWM mode */
4354 TIM_OC1_SetConfig(htim->Instance, sConfig);
4355
4356 /* Set the Preload enable bit for channel1 */
4357 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4358
4359 /* Configure the Output Fast mode */
4360 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4361 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4362 break;
4363 }
4364
4365 case TIM_CHANNEL_2:
4366 {
4367 /* Check the parameters */
4368 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4369
4370 /* Configure the Channel 2 in PWM mode */
4371 TIM_OC2_SetConfig(htim->Instance, sConfig);
4372
4373 /* Set the Preload enable bit for channel2 */
4374 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4375
4376 /* Configure the Output Fast mode */
4377 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4378 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4379 break;
4380 }
4381
4382 case TIM_CHANNEL_3:
4383 {
4384 /* Check the parameters */
4385 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4386
4387 /* Configure the Channel 3 in PWM mode */
4388 TIM_OC3_SetConfig(htim->Instance, sConfig);
4389
4390 /* Set the Preload enable bit for channel3 */
4391 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4392
4393 /* Configure the Output Fast mode */
4394 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4395 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4396 break;
4397 }
4398
4399 case TIM_CHANNEL_4:
4400 {
4401 /* Check the parameters */
4402 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4403
4404 /* Configure the Channel 4 in PWM mode */
4405 TIM_OC4_SetConfig(htim->Instance, sConfig);
4406
4407 /* Set the Preload enable bit for channel4 */
4408 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4409
4410 /* Configure the Output Fast mode */
4411 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4412 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4413 break;
4414 }
4415
4416 case TIM_CHANNEL_5:
4417 {
4418 /* Check the parameters */
4419 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4420
4421 /* Configure the Channel 5 in PWM mode */
4422 TIM_OC5_SetConfig(htim->Instance, sConfig);
4423
4424 /* Set the Preload enable bit for channel5*/
4425 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4426
4427 /* Configure the Output Fast mode */
4428 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4429 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4430 break;
4431 }
4432
4433 case TIM_CHANNEL_6:
4434 {
4435 /* Check the parameters */
4436 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4437
4438 /* Configure the Channel 6 in PWM mode */
4439 TIM_OC6_SetConfig(htim->Instance, sConfig);
4440
4441 /* Set the Preload enable bit for channel6 */
4442 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4443
4444 /* Configure the Output Fast mode */
4445 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4446 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4447 break;
4448 }
4449
4450 default:
4451 status = HAL_ERROR;
4452 break;
4453 }
4454
4455 __HAL_UNLOCK(htim);
4456
4457 return status;
4458 }
4459
4460 /**
4461 * @brief Initializes the TIM One Pulse Channels according to the specified
4462 * parameters in the TIM_OnePulse_InitTypeDef.
4463 * @param htim TIM One Pulse handle
4464 * @param sConfig TIM One Pulse configuration structure
4465 * @param OutputChannel TIM output channel to configure
4466 * This parameter can be one of the following values:
4467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4469 * @param InputChannel TIM input Channel to configure
4470 * This parameter can be one of the following values:
4471 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4472 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4473 * @note To output a waveform with a minimum delay user can enable the fast
4474 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4475 * output is forced in response to the edge detection on TIx input,
4476 * without taking in account the comparison.
4477 * @retval HAL status
4478 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4479 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4480 uint32_t OutputChannel, uint32_t InputChannel)
4481 {
4482 HAL_StatusTypeDef status = HAL_OK;
4483 TIM_OC_InitTypeDef temp1;
4484
4485 /* Check the parameters */
4486 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4487 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4488
4489 if (OutputChannel != InputChannel)
4490 {
4491 /* Process Locked */
4492 __HAL_LOCK(htim);
4493
4494 htim->State = HAL_TIM_STATE_BUSY;
4495
4496 /* Extract the Output compare configuration from sConfig structure */
4497 temp1.OCMode = sConfig->OCMode;
4498 temp1.Pulse = sConfig->Pulse;
4499 temp1.OCPolarity = sConfig->OCPolarity;
4500 temp1.OCNPolarity = sConfig->OCNPolarity;
4501 temp1.OCIdleState = sConfig->OCIdleState;
4502 temp1.OCNIdleState = sConfig->OCNIdleState;
4503
4504 switch (OutputChannel)
4505 {
4506 case TIM_CHANNEL_1:
4507 {
4508 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4509
4510 TIM_OC1_SetConfig(htim->Instance, &temp1);
4511 break;
4512 }
4513
4514 case TIM_CHANNEL_2:
4515 {
4516 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4517
4518 TIM_OC2_SetConfig(htim->Instance, &temp1);
4519 break;
4520 }
4521
4522 default:
4523 status = HAL_ERROR;
4524 break;
4525 }
4526
4527 if (status == HAL_OK)
4528 {
4529 switch (InputChannel)
4530 {
4531 case TIM_CHANNEL_1:
4532 {
4533 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4534
4535 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4536 sConfig->ICSelection, sConfig->ICFilter);
4537
4538 /* Reset the IC1PSC Bits */
4539 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4540
4541 /* Select the Trigger source */
4542 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4543 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4544
4545 /* Select the Slave Mode */
4546 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4547 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4548 break;
4549 }
4550
4551 case TIM_CHANNEL_2:
4552 {
4553 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4554
4555 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4556 sConfig->ICSelection, sConfig->ICFilter);
4557
4558 /* Reset the IC2PSC Bits */
4559 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4560
4561 /* Select the Trigger source */
4562 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4563 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4564
4565 /* Select the Slave Mode */
4566 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4567 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4568 break;
4569 }
4570
4571 default:
4572 status = HAL_ERROR;
4573 break;
4574 }
4575 }
4576
4577 htim->State = HAL_TIM_STATE_READY;
4578
4579 __HAL_UNLOCK(htim);
4580
4581 return status;
4582 }
4583 else
4584 {
4585 return HAL_ERROR;
4586 }
4587 }
4588
4589 /**
4590 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4591 * @param htim TIM handle
4592 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4593 * This parameter can be one of the following values:
4594 * @arg TIM_DMABASE_CR1
4595 * @arg TIM_DMABASE_CR2
4596 * @arg TIM_DMABASE_SMCR
4597 * @arg TIM_DMABASE_DIER
4598 * @arg TIM_DMABASE_SR
4599 * @arg TIM_DMABASE_EGR
4600 * @arg TIM_DMABASE_CCMR1
4601 * @arg TIM_DMABASE_CCMR2
4602 * @arg TIM_DMABASE_CCER
4603 * @arg TIM_DMABASE_CNT
4604 * @arg TIM_DMABASE_PSC
4605 * @arg TIM_DMABASE_ARR
4606 * @arg TIM_DMABASE_RCR
4607 * @arg TIM_DMABASE_CCR1
4608 * @arg TIM_DMABASE_CCR2
4609 * @arg TIM_DMABASE_CCR3
4610 * @arg TIM_DMABASE_CCR4
4611 * @arg TIM_DMABASE_BDTR
4612 * @arg TIM_DMABASE_CCMR3
4613 * @arg TIM_DMABASE_CCR5
4614 * @arg TIM_DMABASE_CCR6
4615 * @arg TIM_DMABASE_DTR2
4616 * @arg TIM_DMABASE_ECR
4617 * @arg TIM_DMABASE_TISEL
4618 * @arg TIM_DMABASE_AF1
4619 * @arg TIM_DMABASE_AF2
4620 * @param BurstRequestSrc TIM DMA Request sources
4621 * This parameter can be one of the following values:
4622 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4623 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4624 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4625 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4626 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4627 * @arg TIM_DMA_COM: TIM Commutation DMA source
4628 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4629 * @param BurstBuffer The Buffer address.
4630 * @param BurstLength DMA Burst length. This parameter can be one value
4631 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4632 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4633 * @retval HAL status
4634 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4635 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4636 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4637 {
4638 HAL_StatusTypeDef status = HAL_OK;
4639 uint32_t BlockDataLength = 0;
4640 uint32_t data_width;
4641 const DMA_HandleTypeDef *hdma = NULL;
4642
4643 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4644
4645 switch (BurstRequestSrc)
4646 {
4647 case TIM_DMA_UPDATE:
4648 {
4649 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
4650 break;
4651 }
4652 case TIM_DMA_CC1:
4653 {
4654 hdma = htim->hdma[TIM_DMA_ID_CC1];
4655 break;
4656 }
4657 case TIM_DMA_CC2:
4658 {
4659 hdma = htim->hdma[TIM_DMA_ID_CC2];
4660 break;
4661 }
4662 case TIM_DMA_CC3:
4663 {
4664 hdma = htim->hdma[TIM_DMA_ID_CC3];
4665 break;
4666 }
4667 case TIM_DMA_CC4:
4668 {
4669 hdma = htim->hdma[TIM_DMA_ID_CC4];
4670 break;
4671 }
4672 case TIM_DMA_COM:
4673 {
4674 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
4675 break;
4676 }
4677 case TIM_DMA_TRIGGER:
4678 {
4679 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
4680 break;
4681 }
4682 default:
4683 status = HAL_ERROR;
4684 break;
4685 }
4686
4687 if (hdma != NULL)
4688 {
4689
4690 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
4691 && (hdma->LinkedListQueue->Head != 0U))
4692 {
4693 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
4694 }
4695 else
4696 {
4697 data_width = hdma->Init.SrcDataWidth;
4698 }
4699
4700 switch (data_width)
4701 {
4702 case DMA_SRC_DATAWIDTH_BYTE:
4703 {
4704 BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
4705 break;
4706 }
4707 case DMA_SRC_DATAWIDTH_HALFWORD:
4708 {
4709 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
4710 break;
4711 }
4712 case DMA_SRC_DATAWIDTH_WORD:
4713 {
4714 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
4715 break;
4716 }
4717 default:
4718 status = HAL_ERROR;
4719 break;
4720 }
4721 }
4722
4723 if (status == HAL_OK)
4724 {
4725 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4726 BlockDataLength);
4727 }
4728
4729
4730 return status;
4731 }
4732
4733 /**
4734 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4735 * @param htim TIM handle
4736 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4737 * This parameter can be one of the following values:
4738 * @arg TIM_DMABASE_CR1
4739 * @arg TIM_DMABASE_CR2
4740 * @arg TIM_DMABASE_SMCR
4741 * @arg TIM_DMABASE_DIER
4742 * @arg TIM_DMABASE_SR
4743 * @arg TIM_DMABASE_EGR
4744 * @arg TIM_DMABASE_CCMR1
4745 * @arg TIM_DMABASE_CCMR2
4746 * @arg TIM_DMABASE_CCER
4747 * @arg TIM_DMABASE_CNT
4748 * @arg TIM_DMABASE_PSC
4749 * @arg TIM_DMABASE_ARR
4750 * @arg TIM_DMABASE_RCR
4751 * @arg TIM_DMABASE_CCR1
4752 * @arg TIM_DMABASE_CCR2
4753 * @arg TIM_DMABASE_CCR3
4754 * @arg TIM_DMABASE_CCR4
4755 * @arg TIM_DMABASE_BDTR
4756 * @arg TIM_DMABASE_CCMR3
4757 * @arg TIM_DMABASE_CCR5
4758 * @arg TIM_DMABASE_CCR6
4759 * @arg TIM_DMABASE_DTR2
4760 * @arg TIM_DMABASE_ECR
4761 * @arg TIM_DMABASE_TISEL
4762 * @arg TIM_DMABASE_AF1
4763 * @arg TIM_DMABASE_AF2
4764 * @param BurstRequestSrc TIM DMA Request sources
4765 * This parameter can be one of the following values:
4766 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4767 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4768 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4769 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4770 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4771 * @arg TIM_DMA_COM: TIM Commutation DMA source
4772 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4773 * @param BurstBuffer The Buffer address.
4774 * @param BurstLength DMA Burst length. This parameter can be one value
4775 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4776 * @param DataLength Data length. This parameter can be one value
4777 * between 1 and 0xFFFF.
4778 * @retval HAL status
4779 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4780 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4781 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4782 uint32_t BurstLength, uint32_t DataLength)
4783 {
4784 HAL_StatusTypeDef status = HAL_OK;
4785 uint32_t tmpDBSS = 0;
4786
4787 /* Check the parameters */
4788 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4789 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4790 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4791 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4792 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4793
4794 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4795 {
4796 return HAL_BUSY;
4797 }
4798 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4799 {
4800 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4801 {
4802 return HAL_ERROR;
4803 }
4804 else
4805 {
4806 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4807 }
4808 }
4809 else
4810 {
4811 /* nothing to do */
4812 }
4813
4814 switch (BurstRequestSrc)
4815 {
4816 case TIM_DMA_UPDATE:
4817 {
4818 /* Set the DMA Period elapsed callbacks */
4819 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4820 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4821
4822 /* Set the DMA error callback */
4823 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4824
4825 /* Enable the DMA channel */
4826 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4827 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4828 {
4829 /* Return error status */
4830 return HAL_ERROR;
4831 }
4832 /* Configure the DMA Burst Source Selection */
4833 tmpDBSS = TIM_DCR_DBSS_0;
4834 break;
4835 }
4836 case TIM_DMA_CC1:
4837 {
4838 /* Set the DMA compare callbacks */
4839 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4840 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4841
4842 /* Set the DMA error callback */
4843 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4844
4845 /* Enable the DMA channel */
4846 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4847 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4848 {
4849 /* Return error status */
4850 return HAL_ERROR;
4851 }
4852 /* Configure the DMA Burst Source Selection */
4853 tmpDBSS = TIM_DCR_DBSS_1;
4854 break;
4855 }
4856 case TIM_DMA_CC2:
4857 {
4858 /* Set the DMA compare callbacks */
4859 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4860 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4861
4862 /* Set the DMA error callback */
4863 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4864
4865 /* Enable the DMA channel */
4866 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4867 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4868 {
4869 /* Return error status */
4870 return HAL_ERROR;
4871 }
4872 /* Configure the DMA Burst Source Selection */
4873 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4874 break;
4875 }
4876 case TIM_DMA_CC3:
4877 {
4878 /* Set the DMA compare callbacks */
4879 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4880 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4881
4882 /* Set the DMA error callback */
4883 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4884
4885 /* Enable the DMA channel */
4886 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4887 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4888 {
4889 /* Return error status */
4890 return HAL_ERROR;
4891 }
4892 /* Configure the DMA Burst Source Selection */
4893 tmpDBSS = TIM_DCR_DBSS_2;
4894 break;
4895 }
4896 case TIM_DMA_CC4:
4897 {
4898 /* Set the DMA compare callbacks */
4899 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4900 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4901
4902 /* Set the DMA error callback */
4903 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4904
4905 /* Enable the DMA channel */
4906 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4907 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4908 {
4909 /* Return error status */
4910 return HAL_ERROR;
4911 }
4912 /* Configure the DMA Burst Source Selection */
4913 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
4914 break;
4915 }
4916 case TIM_DMA_COM:
4917 {
4918 /* Set the DMA commutation callbacks */
4919 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4920 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4921
4922 /* Set the DMA error callback */
4923 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4924
4925 /* Enable the DMA channel */
4926 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4927 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4928 {
4929 /* Return error status */
4930 return HAL_ERROR;
4931 }
4932 /* Configure the DMA Burst Source Selection */
4933 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
4934 break;
4935 }
4936 case TIM_DMA_TRIGGER:
4937 {
4938 /* Set the DMA trigger callbacks */
4939 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4940 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4941
4942 /* Set the DMA error callback */
4943 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4944
4945 /* Enable the DMA channel */
4946 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4947 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4948 {
4949 /* Return error status */
4950 return HAL_ERROR;
4951 }
4952 /* Configure the DMA Burst Source Selection */
4953 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4954 break;
4955 }
4956 default:
4957 status = HAL_ERROR;
4958 break;
4959 }
4960
4961 if (status == HAL_OK)
4962 {
4963 /* Configure the DMA Burst Mode */
4964 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
4965 /* Enable the TIM DMA Request */
4966 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4967 }
4968
4969 /* Return function status */
4970 return status;
4971 }
4972
4973 /**
4974 * @brief Stops the TIM DMA Burst mode
4975 * @param htim TIM handle
4976 * @param BurstRequestSrc TIM DMA Request sources to disable
4977 * @retval HAL status
4978 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4979 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4980 {
4981 HAL_StatusTypeDef status = HAL_OK;
4982
4983 /* Check the parameters */
4984 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4985
4986 /* Abort the DMA transfer (at least disable the DMA channel) */
4987 switch (BurstRequestSrc)
4988 {
4989 case TIM_DMA_UPDATE:
4990 {
4991 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4992 break;
4993 }
4994 case TIM_DMA_CC1:
4995 {
4996 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4997 break;
4998 }
4999 case TIM_DMA_CC2:
5000 {
5001 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5002 break;
5003 }
5004 case TIM_DMA_CC3:
5005 {
5006 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5007 break;
5008 }
5009 case TIM_DMA_CC4:
5010 {
5011 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5012 break;
5013 }
5014 case TIM_DMA_COM:
5015 {
5016 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5017 break;
5018 }
5019 case TIM_DMA_TRIGGER:
5020 {
5021 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5022 break;
5023 }
5024 default:
5025 status = HAL_ERROR;
5026 break;
5027 }
5028
5029 if (status == HAL_OK)
5030 {
5031 /* Disable the TIM Update DMA request */
5032 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5033
5034 /* Change the DMA burst operation state */
5035 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5036 }
5037
5038 /* Return function status */
5039 return status;
5040 }
5041
5042 /**
5043 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5044 * @param htim TIM handle
5045 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5046 * This parameter can be one of the following values:
5047 * @arg TIM_DMABASE_CR1
5048 * @arg TIM_DMABASE_CR2
5049 * @arg TIM_DMABASE_SMCR
5050 * @arg TIM_DMABASE_DIER
5051 * @arg TIM_DMABASE_SR
5052 * @arg TIM_DMABASE_EGR
5053 * @arg TIM_DMABASE_CCMR1
5054 * @arg TIM_DMABASE_CCMR2
5055 * @arg TIM_DMABASE_CCER
5056 * @arg TIM_DMABASE_CNT
5057 * @arg TIM_DMABASE_PSC
5058 * @arg TIM_DMABASE_ARR
5059 * @arg TIM_DMABASE_RCR
5060 * @arg TIM_DMABASE_CCR1
5061 * @arg TIM_DMABASE_CCR2
5062 * @arg TIM_DMABASE_CCR3
5063 * @arg TIM_DMABASE_CCR4
5064 * @arg TIM_DMABASE_BDTR
5065 * @arg TIM_DMABASE_CCMR3
5066 * @arg TIM_DMABASE_CCR5
5067 * @arg TIM_DMABASE_CCR6
5068 * @arg TIM_DMABASE_DTR2
5069 * @arg TIM_DMABASE_ECR
5070 * @arg TIM_DMABASE_TISEL
5071 * @arg TIM_DMABASE_AF1
5072 * @arg TIM_DMABASE_AF2
5073 * @param BurstRequestSrc TIM DMA Request sources
5074 * This parameter can be one of the following values:
5075 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5076 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5077 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5078 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5079 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5080 * @arg TIM_DMA_COM: TIM Commutation DMA source
5081 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5082 * @param BurstBuffer The Buffer address.
5083 * @param BurstLength DMA Burst length. This parameter can be one value
5084 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5085 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
5086 * @retval HAL status
5087 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)5088 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5089 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
5090 {
5091 HAL_StatusTypeDef status = HAL_OK;
5092 uint32_t BlockDataLength = 0;
5093 uint32_t data_width;
5094 const DMA_HandleTypeDef *hdma = NULL;
5095
5096 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5097
5098 switch (BurstRequestSrc)
5099 {
5100 case TIM_DMA_UPDATE:
5101 {
5102 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
5103 break;
5104 }
5105 case TIM_DMA_CC1:
5106 {
5107 hdma = htim->hdma[TIM_DMA_ID_CC1];
5108 break;
5109 }
5110 case TIM_DMA_CC2:
5111 {
5112 hdma = htim->hdma[TIM_DMA_ID_CC2];
5113 break;
5114 }
5115 case TIM_DMA_CC3:
5116 {
5117 hdma = htim->hdma[TIM_DMA_ID_CC3];
5118 break;
5119 }
5120 case TIM_DMA_CC4:
5121 {
5122 hdma = htim->hdma[TIM_DMA_ID_CC4];
5123 break;
5124 }
5125 case TIM_DMA_COM:
5126 {
5127 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
5128 break;
5129 }
5130 case TIM_DMA_TRIGGER:
5131 {
5132 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
5133 break;
5134 }
5135 default:
5136 status = HAL_ERROR;
5137 break;
5138 }
5139
5140 if (hdma != NULL)
5141 {
5142
5143 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
5144 && (hdma->LinkedListQueue->Head != 0U))
5145 {
5146 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
5147 }
5148 else
5149 {
5150 data_width = hdma->Init.SrcDataWidth;
5151 }
5152
5153 switch (data_width)
5154
5155 {
5156 case DMA_SRC_DATAWIDTH_BYTE:
5157 {
5158 BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
5159 break;
5160 }
5161 case DMA_SRC_DATAWIDTH_HALFWORD:
5162 {
5163 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
5164 break;
5165 }
5166 case DMA_SRC_DATAWIDTH_WORD:
5167 {
5168 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
5169 break;
5170 }
5171 default:
5172 status = HAL_ERROR;
5173 break;
5174 }
5175 }
5176
5177 if (status == HAL_OK)
5178 {
5179 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
5180 BlockDataLength);
5181 }
5182
5183 return status;
5184 }
5185
5186 /**
5187 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5188 * @param htim TIM handle
5189 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5190 * This parameter can be one of the following values:
5191 * @arg TIM_DMABASE_CR1
5192 * @arg TIM_DMABASE_CR2
5193 * @arg TIM_DMABASE_SMCR
5194 * @arg TIM_DMABASE_DIER
5195 * @arg TIM_DMABASE_SR
5196 * @arg TIM_DMABASE_EGR
5197 * @arg TIM_DMABASE_CCMR1
5198 * @arg TIM_DMABASE_CCMR2
5199 * @arg TIM_DMABASE_CCER
5200 * @arg TIM_DMABASE_CNT
5201 * @arg TIM_DMABASE_PSC
5202 * @arg TIM_DMABASE_ARR
5203 * @arg TIM_DMABASE_RCR
5204 * @arg TIM_DMABASE_CCR1
5205 * @arg TIM_DMABASE_CCR2
5206 * @arg TIM_DMABASE_CCR3
5207 * @arg TIM_DMABASE_CCR4
5208 * @arg TIM_DMABASE_BDTR
5209 * @arg TIM_DMABASE_CCMR3
5210 * @arg TIM_DMABASE_CCR5
5211 * @arg TIM_DMABASE_CCR6
5212 * @arg TIM_DMABASE_DTR2
5213 * @arg TIM_DMABASE_ECR
5214 * @arg TIM_DMABASE_TISEL
5215 * @arg TIM_DMABASE_AF1
5216 * @arg TIM_DMABASE_AF2
5217 * @param BurstRequestSrc TIM DMA Request sources
5218 * This parameter can be one of the following values:
5219 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5220 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5221 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5222 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5223 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5224 * @arg TIM_DMA_COM: TIM Commutation DMA source
5225 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5226 * @param BurstBuffer The Buffer address.
5227 * @param BurstLength DMA Burst length. This parameter can be one value
5228 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5229 * @param DataLength Data length. This parameter can be one value
5230 * between 1 and 0xFFFF.
5231 * @retval HAL status
5232 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)5233 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5234 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
5235 uint32_t BurstLength, uint32_t DataLength)
5236 {
5237 HAL_StatusTypeDef status = HAL_OK;
5238 uint32_t tmpDBSS = 0;
5239
5240 /* Check the parameters */
5241 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5242 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5243 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5244 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5245 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5246
5247 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5248 {
5249 return HAL_BUSY;
5250 }
5251 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5252 {
5253 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5254 {
5255 return HAL_ERROR;
5256 }
5257 else
5258 {
5259 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5260 }
5261 }
5262 else
5263 {
5264 /* nothing to do */
5265 }
5266 switch (BurstRequestSrc)
5267 {
5268 case TIM_DMA_UPDATE:
5269 {
5270 /* Set the DMA Period elapsed callbacks */
5271 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5272 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5273
5274 /* Set the DMA error callback */
5275 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5276
5277 /* Enable the DMA channel */
5278 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5279 DataLength) != HAL_OK)
5280 {
5281 /* Return error status */
5282 return HAL_ERROR;
5283 }
5284 /* Configure the DMA Burst Source Selection */
5285 tmpDBSS = TIM_DCR_DBSS_0;
5286 break;
5287 }
5288 case TIM_DMA_CC1:
5289 {
5290 /* Set the DMA capture callbacks */
5291 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5292 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5293
5294 /* Set the DMA error callback */
5295 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5296
5297 /* Enable the DMA channel */
5298 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5299 DataLength) != HAL_OK)
5300 {
5301 /* Return error status */
5302 return HAL_ERROR;
5303 }
5304 /* Configure the DMA Burst Source Selection */
5305 tmpDBSS = TIM_DCR_DBSS_1;
5306 break;
5307 }
5308 case TIM_DMA_CC2:
5309 {
5310 /* Set the DMA capture callbacks */
5311 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5312 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5313
5314 /* Set the DMA error callback */
5315 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5316
5317 /* Enable the DMA channel */
5318 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5319 DataLength) != HAL_OK)
5320 {
5321 /* Return error status */
5322 return HAL_ERROR;
5323 }
5324 /* Configure the DMA Burst Source Selection */
5325 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5326 break;
5327 }
5328 case TIM_DMA_CC3:
5329 {
5330 /* Set the DMA capture callbacks */
5331 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5332 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5333
5334 /* Set the DMA error callback */
5335 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5336
5337 /* Enable the DMA channel */
5338 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5339 DataLength) != HAL_OK)
5340 {
5341 /* Return error status */
5342 return HAL_ERROR;
5343 }
5344 /* Configure the DMA Burst Source Selection */
5345 tmpDBSS = TIM_DCR_DBSS_2;
5346 break;
5347 }
5348 case TIM_DMA_CC4:
5349 {
5350 /* Set the DMA capture callbacks */
5351 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5352 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5353
5354 /* Set the DMA error callback */
5355 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5356
5357 /* Enable the DMA channel */
5358 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5359 DataLength) != HAL_OK)
5360 {
5361 /* Return error status */
5362 return HAL_ERROR;
5363 }
5364 /* Configure the DMA Burst Source Selection */
5365 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
5366 break;
5367 }
5368 case TIM_DMA_COM:
5369 {
5370 /* Set the DMA commutation callbacks */
5371 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5372 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5373
5374 /* Set the DMA error callback */
5375 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5376
5377 /* Enable the DMA channel */
5378 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5379 DataLength) != HAL_OK)
5380 {
5381 /* Return error status */
5382 return HAL_ERROR;
5383 }
5384 /* Configure the DMA Burst Source Selection */
5385 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
5386 break;
5387 }
5388 case TIM_DMA_TRIGGER:
5389 {
5390 /* Set the DMA trigger callbacks */
5391 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5392 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5393
5394 /* Set the DMA error callback */
5395 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5396
5397 /* Enable the DMA channel */
5398 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5399 DataLength) != HAL_OK)
5400 {
5401 /* Return error status */
5402 return HAL_ERROR;
5403 }
5404 /* Configure the DMA Burst Source Selection */
5405 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5406 break;
5407 }
5408 default:
5409 status = HAL_ERROR;
5410 break;
5411 }
5412
5413 if (status == HAL_OK)
5414 {
5415 /* Configure the DMA Burst Mode */
5416 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
5417
5418 /* Enable the TIM DMA Request */
5419 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5420 }
5421
5422 /* Return function status */
5423 return status;
5424 }
5425
5426 /**
5427 * @brief Stop the DMA burst reading
5428 * @param htim TIM handle
5429 * @param BurstRequestSrc TIM DMA Request sources to disable.
5430 * @retval HAL status
5431 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5432 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5433 {
5434 HAL_StatusTypeDef status = HAL_OK;
5435
5436 /* Check the parameters */
5437 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5438
5439 /* Abort the DMA transfer (at least disable the DMA channel) */
5440 switch (BurstRequestSrc)
5441 {
5442 case TIM_DMA_UPDATE:
5443 {
5444 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5445 break;
5446 }
5447 case TIM_DMA_CC1:
5448 {
5449 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5450 break;
5451 }
5452 case TIM_DMA_CC2:
5453 {
5454 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5455 break;
5456 }
5457 case TIM_DMA_CC3:
5458 {
5459 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5460 break;
5461 }
5462 case TIM_DMA_CC4:
5463 {
5464 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5465 break;
5466 }
5467 case TIM_DMA_COM:
5468 {
5469 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5470 break;
5471 }
5472 case TIM_DMA_TRIGGER:
5473 {
5474 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5475 break;
5476 }
5477 default:
5478 status = HAL_ERROR;
5479 break;
5480 }
5481
5482 if (status == HAL_OK)
5483 {
5484 /* Disable the TIM Update DMA request */
5485 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5486
5487 /* Change the DMA burst operation state */
5488 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5489 }
5490
5491 /* Return function status */
5492 return status;
5493 }
5494
5495 /**
5496 * @brief Generate a software event
5497 * @param htim TIM handle
5498 * @param EventSource specifies the event source.
5499 * This parameter can be one of the following values:
5500 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5501 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5502 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5503 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5504 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5505 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5506 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5507 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5508 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5509 * @note Basic timers can only generate an update event.
5510 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5511 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5512 * only for timer instances supporting break input(s).
5513 * @retval HAL status
5514 */
5515
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5516 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5517 {
5518 /* Check the parameters */
5519 assert_param(IS_TIM_INSTANCE(htim->Instance));
5520 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5521
5522 /* Process Locked */
5523 __HAL_LOCK(htim);
5524
5525 /* Change the TIM state */
5526 htim->State = HAL_TIM_STATE_BUSY;
5527
5528 /* Set the event sources */
5529 htim->Instance->EGR = EventSource;
5530
5531 /* Change the TIM state */
5532 htim->State = HAL_TIM_STATE_READY;
5533
5534 __HAL_UNLOCK(htim);
5535
5536 /* Return function status */
5537 return HAL_OK;
5538 }
5539
5540 /**
5541 * @brief Configures the OCRef clear feature
5542 * @param htim TIM handle
5543 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5544 * contains the OCREF clear feature and parameters for the TIM peripheral.
5545 * @param Channel specifies the TIM Channel
5546 * This parameter can be one of the following values:
5547 * @arg TIM_CHANNEL_1: TIM Channel 1
5548 * @arg TIM_CHANNEL_2: TIM Channel 2
5549 * @arg TIM_CHANNEL_3: TIM Channel 3
5550 * @arg TIM_CHANNEL_4: TIM Channel 4
5551 * @arg TIM_CHANNEL_5: TIM Channel 5
5552 * @arg TIM_CHANNEL_6: TIM Channel 6
5553 * @retval HAL status
5554 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5555 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5556 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5557 uint32_t Channel)
5558 {
5559 HAL_StatusTypeDef status = HAL_OK;
5560
5561 /* Check the parameters */
5562 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5563 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5564
5565 /* Process Locked */
5566 __HAL_LOCK(htim);
5567
5568 htim->State = HAL_TIM_STATE_BUSY;
5569
5570 switch (sClearInputConfig->ClearInputSource)
5571 {
5572 case TIM_CLEARINPUTSOURCE_NONE:
5573 {
5574 /* Clear the OCREF clear selection bit and the the ETR Bits */
5575 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5576 break;
5577 }
5578 case TIM_CLEARINPUTSOURCE_OCREFCLR:
5579 {
5580 /* Clear the OCREF clear selection bit */
5581 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5582 break;
5583 }
5584
5585 case TIM_CLEARINPUTSOURCE_ETR:
5586 {
5587 /* Check the parameters */
5588 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5589 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5590 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5591
5592 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5593 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5594 {
5595 htim->State = HAL_TIM_STATE_READY;
5596 __HAL_UNLOCK(htim);
5597 return HAL_ERROR;
5598 }
5599
5600 TIM_ETR_SetConfig(htim->Instance,
5601 sClearInputConfig->ClearInputPrescaler,
5602 sClearInputConfig->ClearInputPolarity,
5603 sClearInputConfig->ClearInputFilter);
5604
5605 /* Set the OCREF clear selection bit */
5606 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5607
5608 /* Clear TIMx_AF2_OCRSEL (reset value) */
5609 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5610 break;
5611 }
5612
5613 default:
5614 status = HAL_ERROR;
5615 break;
5616 }
5617
5618 if (status == HAL_OK)
5619 {
5620 switch (Channel)
5621 {
5622 case TIM_CHANNEL_1:
5623 {
5624 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5625 {
5626 /* Enable the OCREF clear feature for Channel 1 */
5627 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5628 }
5629 else
5630 {
5631 /* Disable the OCREF clear feature for Channel 1 */
5632 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5633 }
5634 break;
5635 }
5636 case TIM_CHANNEL_2:
5637 {
5638 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5639 {
5640 /* Enable the OCREF clear feature for Channel 2 */
5641 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5642 }
5643 else
5644 {
5645 /* Disable the OCREF clear feature for Channel 2 */
5646 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5647 }
5648 break;
5649 }
5650 case TIM_CHANNEL_3:
5651 {
5652 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5653 {
5654 /* Enable the OCREF clear feature for Channel 3 */
5655 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5656 }
5657 else
5658 {
5659 /* Disable the OCREF clear feature for Channel 3 */
5660 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5661 }
5662 break;
5663 }
5664 case TIM_CHANNEL_4:
5665 {
5666 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5667 {
5668 /* Enable the OCREF clear feature for Channel 4 */
5669 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5670 }
5671 else
5672 {
5673 /* Disable the OCREF clear feature for Channel 4 */
5674 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5675 }
5676 break;
5677 }
5678 case TIM_CHANNEL_5:
5679 {
5680 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5681 {
5682 /* Enable the OCREF clear feature for Channel 5 */
5683 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5684 }
5685 else
5686 {
5687 /* Disable the OCREF clear feature for Channel 5 */
5688 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5689 }
5690 break;
5691 }
5692 case TIM_CHANNEL_6:
5693 {
5694 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5695 {
5696 /* Enable the OCREF clear feature for Channel 6 */
5697 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5698 }
5699 else
5700 {
5701 /* Disable the OCREF clear feature for Channel 6 */
5702 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5703 }
5704 break;
5705 }
5706 default:
5707 break;
5708 }
5709 }
5710
5711 htim->State = HAL_TIM_STATE_READY;
5712
5713 __HAL_UNLOCK(htim);
5714
5715 return status;
5716 }
5717
5718 /**
5719 * @brief Configures the clock source to be used
5720 * @param htim TIM handle
5721 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5722 * contains the clock source information for the TIM peripheral.
5723 * @retval HAL status
5724 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5725 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5726 {
5727 HAL_StatusTypeDef status = HAL_OK;
5728 uint32_t tmpsmcr;
5729
5730 /* Process Locked */
5731 __HAL_LOCK(htim);
5732
5733 htim->State = HAL_TIM_STATE_BUSY;
5734
5735 /* Check the parameters */
5736 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5737
5738 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5739 tmpsmcr = htim->Instance->SMCR;
5740 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5741 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5742 htim->Instance->SMCR = tmpsmcr;
5743
5744 switch (sClockSourceConfig->ClockSource)
5745 {
5746 case TIM_CLOCKSOURCE_INTERNAL:
5747 {
5748 assert_param(IS_TIM_INSTANCE(htim->Instance));
5749 break;
5750 }
5751
5752 case TIM_CLOCKSOURCE_ETRMODE1:
5753 {
5754 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5755 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5756
5757 /* Check ETR input conditioning related parameters */
5758 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5759 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5760 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5761
5762 /* Configure the ETR Clock source */
5763 TIM_ETR_SetConfig(htim->Instance,
5764 sClockSourceConfig->ClockPrescaler,
5765 sClockSourceConfig->ClockPolarity,
5766 sClockSourceConfig->ClockFilter);
5767
5768 /* Select the External clock mode1 and the ETRF trigger */
5769 tmpsmcr = htim->Instance->SMCR;
5770 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5771 /* Write to TIMx SMCR */
5772 htim->Instance->SMCR = tmpsmcr;
5773 break;
5774 }
5775
5776 case TIM_CLOCKSOURCE_ETRMODE2:
5777 {
5778 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5779 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5780
5781 /* Check ETR input conditioning related parameters */
5782 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5783 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5784 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5785
5786 /* Configure the ETR Clock source */
5787 TIM_ETR_SetConfig(htim->Instance,
5788 sClockSourceConfig->ClockPrescaler,
5789 sClockSourceConfig->ClockPolarity,
5790 sClockSourceConfig->ClockFilter);
5791 /* Enable the External clock mode2 */
5792 htim->Instance->SMCR |= TIM_SMCR_ECE;
5793 break;
5794 }
5795
5796 case TIM_CLOCKSOURCE_TI1:
5797 {
5798 /* Check whether or not the timer instance supports external clock mode 1 */
5799 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5800
5801 /* Check TI1 input conditioning related parameters */
5802 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5803 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5804
5805 TIM_TI1_ConfigInputStage(htim->Instance,
5806 sClockSourceConfig->ClockPolarity,
5807 sClockSourceConfig->ClockFilter);
5808 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5809 break;
5810 }
5811
5812 case TIM_CLOCKSOURCE_TI2:
5813 {
5814 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5815 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5816
5817 /* Check TI2 input conditioning related parameters */
5818 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5819 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5820
5821 TIM_TI2_ConfigInputStage(htim->Instance,
5822 sClockSourceConfig->ClockPolarity,
5823 sClockSourceConfig->ClockFilter);
5824 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5825 break;
5826 }
5827
5828 case TIM_CLOCKSOURCE_TI1ED:
5829 {
5830 /* Check whether or not the timer instance supports external clock mode 1 */
5831 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5832
5833 /* Check TI1 input conditioning related parameters */
5834 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5835 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5836
5837 TIM_TI1_ConfigInputStage(htim->Instance,
5838 sClockSourceConfig->ClockPolarity,
5839 sClockSourceConfig->ClockFilter);
5840 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5841 break;
5842 }
5843
5844 case TIM_CLOCKSOURCE_ITR0:
5845 case TIM_CLOCKSOURCE_ITR1:
5846 case TIM_CLOCKSOURCE_ITR2:
5847 case TIM_CLOCKSOURCE_ITR3:
5848 case TIM_CLOCKSOURCE_ITR4:
5849 case TIM_CLOCKSOURCE_ITR5:
5850 case TIM_CLOCKSOURCE_ITR6:
5851 case TIM_CLOCKSOURCE_ITR7:
5852 case TIM_CLOCKSOURCE_ITR8:
5853 case TIM_CLOCKSOURCE_ITR9:
5854 case TIM_CLOCKSOURCE_ITR10:
5855 case TIM_CLOCKSOURCE_ITR11:
5856 case TIM_CLOCKSOURCE_ITR12:
5857 {
5858 /* Check whether or not the timer instance supports internal trigger input */
5859 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5860
5861 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5862 break;
5863 }
5864
5865 default:
5866 status = HAL_ERROR;
5867 break;
5868 }
5869 htim->State = HAL_TIM_STATE_READY;
5870
5871 __HAL_UNLOCK(htim);
5872
5873 return status;
5874 }
5875
5876 /**
5877 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5878 * or a XOR combination between CH1_input, CH2_input & CH3_input
5879 * @param htim TIM handle.
5880 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5881 * output of a XOR gate.
5882 * This parameter can be one of the following values:
5883 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5884 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5885 * pins are connected to the TI1 input (XOR combination)
5886 * @retval HAL status
5887 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5888 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5889 {
5890 uint32_t tmpcr2;
5891
5892 /* Check the parameters */
5893 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5894 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5895
5896 /* Get the TIMx CR2 register value */
5897 tmpcr2 = htim->Instance->CR2;
5898
5899 /* Reset the TI1 selection */
5900 tmpcr2 &= ~TIM_CR2_TI1S;
5901
5902 /* Set the TI1 selection */
5903 tmpcr2 |= TI1_Selection;
5904
5905 /* Write to TIMxCR2 */
5906 htim->Instance->CR2 = tmpcr2;
5907
5908 return HAL_OK;
5909 }
5910
5911 /**
5912 * @brief Configures the TIM in Slave mode
5913 * @param htim TIM handle.
5914 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5915 * contains the selected trigger (internal trigger input, filtered
5916 * timer input or external trigger input) and the Slave mode
5917 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5918 * @retval HAL status
5919 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5920 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5921 {
5922 /* Check the parameters */
5923 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5924 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5925 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5926
5927 __HAL_LOCK(htim);
5928
5929 htim->State = HAL_TIM_STATE_BUSY;
5930
5931 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5932 {
5933 htim->State = HAL_TIM_STATE_READY;
5934 __HAL_UNLOCK(htim);
5935 return HAL_ERROR;
5936 }
5937
5938 /* Disable Trigger Interrupt */
5939 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5940
5941 /* Disable Trigger DMA request */
5942 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5943
5944 htim->State = HAL_TIM_STATE_READY;
5945
5946 __HAL_UNLOCK(htim);
5947
5948 return HAL_OK;
5949 }
5950
5951 /**
5952 * @brief Configures the TIM in Slave mode in interrupt mode
5953 * @param htim TIM handle.
5954 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5955 * contains the selected trigger (internal trigger input, filtered
5956 * timer input or external trigger input) and the Slave mode
5957 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5958 * @retval HAL status
5959 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5960 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5961 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5962 {
5963 /* Check the parameters */
5964 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5965 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5966 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5967
5968 __HAL_LOCK(htim);
5969
5970 htim->State = HAL_TIM_STATE_BUSY;
5971
5972 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5973 {
5974 htim->State = HAL_TIM_STATE_READY;
5975 __HAL_UNLOCK(htim);
5976 return HAL_ERROR;
5977 }
5978
5979 /* Enable Trigger Interrupt */
5980 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5981
5982 /* Disable Trigger DMA request */
5983 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5984
5985 htim->State = HAL_TIM_STATE_READY;
5986
5987 __HAL_UNLOCK(htim);
5988
5989 return HAL_OK;
5990 }
5991
5992 /**
5993 * @brief Read the captured value from Capture Compare unit
5994 * @param htim TIM handle.
5995 * @param Channel TIM Channels to be enabled
5996 * This parameter can be one of the following values:
5997 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5998 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5999 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
6000 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
6001 * @retval Captured value
6002 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)6003 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
6004 {
6005 uint32_t tmpreg = 0U;
6006
6007 switch (Channel)
6008 {
6009 case TIM_CHANNEL_1:
6010 {
6011 /* Check the parameters */
6012 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6013
6014 /* Return the capture 1 value */
6015 tmpreg = htim->Instance->CCR1;
6016
6017 break;
6018 }
6019 case TIM_CHANNEL_2:
6020 {
6021 /* Check the parameters */
6022 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6023
6024 /* Return the capture 2 value */
6025 tmpreg = htim->Instance->CCR2;
6026
6027 break;
6028 }
6029
6030 case TIM_CHANNEL_3:
6031 {
6032 /* Check the parameters */
6033 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
6034
6035 /* Return the capture 3 value */
6036 tmpreg = htim->Instance->CCR3;
6037
6038 break;
6039 }
6040
6041 case TIM_CHANNEL_4:
6042 {
6043 /* Check the parameters */
6044 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
6045
6046 /* Return the capture 4 value */
6047 tmpreg = htim->Instance->CCR4;
6048
6049 break;
6050 }
6051
6052 default:
6053 break;
6054 }
6055
6056 return tmpreg;
6057 }
6058
6059 /**
6060 * @brief Start the DMA data transfer.
6061 * @param hdma DMA handle
6062 * @param src : The source memory Buffer address.
6063 * @param dst : The destination memory Buffer address.
6064 * @param length : The size of a source block transfer in byte.
6065 * @retval HAL status
6066 */
TIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)6067 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
6068 uint32_t length)
6069 {
6070 HAL_StatusTypeDef status ;
6071
6072 /* Enable the DMA channel */
6073 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6074 {
6075 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
6076 {
6077 /* Enable the DMA channel */
6078 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
6079 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
6080 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
6081
6082 status = HAL_DMAEx_List_Start_IT(hdma);
6083 }
6084 else
6085 {
6086 status = HAL_ERROR;
6087 }
6088 }
6089 else
6090 {
6091 status = HAL_DMA_Start_IT(hdma, src, dst, length);
6092 }
6093
6094 return status;
6095 }
6096
6097 /**
6098 * @}
6099 */
6100
6101 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
6102 * @brief TIM Callbacks functions
6103 *
6104 @verbatim
6105 ==============================================================================
6106 ##### TIM Callbacks functions #####
6107 ==============================================================================
6108 [..]
6109 This section provides TIM callback functions:
6110 (+) TIM Period elapsed callback
6111 (+) TIM Output Compare callback
6112 (+) TIM Input capture callback
6113 (+) TIM Trigger callback
6114 (+) TIM Error callback
6115 (+) TIM Index callback
6116 (+) TIM Direction change callback
6117 (+) TIM Index error callback
6118 (+) TIM Transition error callback
6119
6120 @endverbatim
6121 * @{
6122 */
6123
6124 /**
6125 * @brief Period elapsed callback in non-blocking mode
6126 * @param htim TIM handle
6127 * @retval None
6128 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)6129 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
6130 {
6131 /* Prevent unused argument(s) compilation warning */
6132 UNUSED(htim);
6133
6134 /* NOTE : This function should not be modified, when the callback is needed,
6135 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
6136 */
6137 }
6138
6139 /**
6140 * @brief Period elapsed half complete callback in non-blocking mode
6141 * @param htim TIM handle
6142 * @retval None
6143 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)6144 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
6145 {
6146 /* Prevent unused argument(s) compilation warning */
6147 UNUSED(htim);
6148
6149 /* NOTE : This function should not be modified, when the callback is needed,
6150 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
6151 */
6152 }
6153
6154 /**
6155 * @brief Output Compare callback in non-blocking mode
6156 * @param htim TIM OC handle
6157 * @retval None
6158 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)6159 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
6160 {
6161 /* Prevent unused argument(s) compilation warning */
6162 UNUSED(htim);
6163
6164 /* NOTE : This function should not be modified, when the callback is needed,
6165 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
6166 */
6167 }
6168
6169 /**
6170 * @brief Input Capture callback in non-blocking mode
6171 * @param htim TIM IC handle
6172 * @retval None
6173 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)6174 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
6175 {
6176 /* Prevent unused argument(s) compilation warning */
6177 UNUSED(htim);
6178
6179 /* NOTE : This function should not be modified, when the callback is needed,
6180 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
6181 */
6182 }
6183
6184 /**
6185 * @brief Input Capture half complete callback in non-blocking mode
6186 * @param htim TIM IC handle
6187 * @retval None
6188 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)6189 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
6190 {
6191 /* Prevent unused argument(s) compilation warning */
6192 UNUSED(htim);
6193
6194 /* NOTE : This function should not be modified, when the callback is needed,
6195 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
6196 */
6197 }
6198
6199 /**
6200 * @brief PWM Pulse finished callback in non-blocking mode
6201 * @param htim TIM handle
6202 * @retval None
6203 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)6204 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
6205 {
6206 /* Prevent unused argument(s) compilation warning */
6207 UNUSED(htim);
6208
6209 /* NOTE : This function should not be modified, when the callback is needed,
6210 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
6211 */
6212 }
6213
6214 /**
6215 * @brief PWM Pulse finished half complete callback in non-blocking mode
6216 * @param htim TIM handle
6217 * @retval None
6218 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)6219 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
6220 {
6221 /* Prevent unused argument(s) compilation warning */
6222 UNUSED(htim);
6223
6224 /* NOTE : This function should not be modified, when the callback is needed,
6225 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
6226 */
6227 }
6228
6229 /**
6230 * @brief Hall Trigger detection callback in non-blocking mode
6231 * @param htim TIM handle
6232 * @retval None
6233 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)6234 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
6235 {
6236 /* Prevent unused argument(s) compilation warning */
6237 UNUSED(htim);
6238
6239 /* NOTE : This function should not be modified, when the callback is needed,
6240 the HAL_TIM_TriggerCallback could be implemented in the user file
6241 */
6242 }
6243
6244 /**
6245 * @brief Hall Trigger detection half complete callback in non-blocking mode
6246 * @param htim TIM handle
6247 * @retval None
6248 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)6249 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
6250 {
6251 /* Prevent unused argument(s) compilation warning */
6252 UNUSED(htim);
6253
6254 /* NOTE : This function should not be modified, when the callback is needed,
6255 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
6256 */
6257 }
6258
6259 /**
6260 * @brief Timer error callback in non-blocking mode
6261 * @param htim TIM handle
6262 * @retval None
6263 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)6264 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
6265 {
6266 /* Prevent unused argument(s) compilation warning */
6267 UNUSED(htim);
6268
6269 /* NOTE : This function should not be modified, when the callback is needed,
6270 the HAL_TIM_ErrorCallback could be implemented in the user file
6271 */
6272 }
6273
6274 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6275 /**
6276 * @brief Register a User TIM callback to be used instead of the weak predefined callback
6277 * @param htim tim handle
6278 * @param CallbackID ID of the callback to be registered
6279 * This parameter can be one of the following values:
6280 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6281 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6282 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6283 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6284 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6285 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6286 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6287 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6288 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6289 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6290 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6291 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6292 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6293 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6294 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6295 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6296 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6297 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6298 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6299 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6300 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6301 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6302 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6303 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6304 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6305 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6306 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6307 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6308 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6309 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6310 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6311 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6312 * @param pCallback pointer to the callback function
6313 * @retval status
6314 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6315 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6316 pTIM_CallbackTypeDef pCallback)
6317 {
6318 HAL_StatusTypeDef status = HAL_OK;
6319
6320 if (pCallback == NULL)
6321 {
6322 return HAL_ERROR;
6323 }
6324
6325 if (htim->State == HAL_TIM_STATE_READY)
6326 {
6327 switch (CallbackID)
6328 {
6329 case HAL_TIM_BASE_MSPINIT_CB_ID :
6330 htim->Base_MspInitCallback = pCallback;
6331 break;
6332
6333 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6334 htim->Base_MspDeInitCallback = pCallback;
6335 break;
6336
6337 case HAL_TIM_IC_MSPINIT_CB_ID :
6338 htim->IC_MspInitCallback = pCallback;
6339 break;
6340
6341 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6342 htim->IC_MspDeInitCallback = pCallback;
6343 break;
6344
6345 case HAL_TIM_OC_MSPINIT_CB_ID :
6346 htim->OC_MspInitCallback = pCallback;
6347 break;
6348
6349 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6350 htim->OC_MspDeInitCallback = pCallback;
6351 break;
6352
6353 case HAL_TIM_PWM_MSPINIT_CB_ID :
6354 htim->PWM_MspInitCallback = pCallback;
6355 break;
6356
6357 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6358 htim->PWM_MspDeInitCallback = pCallback;
6359 break;
6360
6361 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6362 htim->OnePulse_MspInitCallback = pCallback;
6363 break;
6364
6365 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6366 htim->OnePulse_MspDeInitCallback = pCallback;
6367 break;
6368
6369 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6370 htim->Encoder_MspInitCallback = pCallback;
6371 break;
6372
6373 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6374 htim->Encoder_MspDeInitCallback = pCallback;
6375 break;
6376
6377 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6378 htim->HallSensor_MspInitCallback = pCallback;
6379 break;
6380
6381 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6382 htim->HallSensor_MspDeInitCallback = pCallback;
6383 break;
6384
6385 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6386 htim->PeriodElapsedCallback = pCallback;
6387 break;
6388
6389 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6390 htim->PeriodElapsedHalfCpltCallback = pCallback;
6391 break;
6392
6393 case HAL_TIM_TRIGGER_CB_ID :
6394 htim->TriggerCallback = pCallback;
6395 break;
6396
6397 case HAL_TIM_TRIGGER_HALF_CB_ID :
6398 htim->TriggerHalfCpltCallback = pCallback;
6399 break;
6400
6401 case HAL_TIM_IC_CAPTURE_CB_ID :
6402 htim->IC_CaptureCallback = pCallback;
6403 break;
6404
6405 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6406 htim->IC_CaptureHalfCpltCallback = pCallback;
6407 break;
6408
6409 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6410 htim->OC_DelayElapsedCallback = pCallback;
6411 break;
6412
6413 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6414 htim->PWM_PulseFinishedCallback = pCallback;
6415 break;
6416
6417 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6418 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6419 break;
6420
6421 case HAL_TIM_ERROR_CB_ID :
6422 htim->ErrorCallback = pCallback;
6423 break;
6424
6425 case HAL_TIM_COMMUTATION_CB_ID :
6426 htim->CommutationCallback = pCallback;
6427 break;
6428
6429 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6430 htim->CommutationHalfCpltCallback = pCallback;
6431 break;
6432
6433 case HAL_TIM_BREAK_CB_ID :
6434 htim->BreakCallback = pCallback;
6435 break;
6436
6437 case HAL_TIM_BREAK2_CB_ID :
6438 htim->Break2Callback = pCallback;
6439 break;
6440
6441 case HAL_TIM_ENCODER_INDEX_CB_ID :
6442 htim->EncoderIndexCallback = pCallback;
6443 break;
6444
6445 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6446 htim->DirectionChangeCallback = pCallback;
6447 break;
6448
6449 case HAL_TIM_INDEX_ERROR_CB_ID :
6450 htim->IndexErrorCallback = pCallback;
6451 break;
6452
6453 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6454 htim->TransitionErrorCallback = pCallback;
6455 break;
6456
6457 default :
6458 /* Return error status */
6459 status = HAL_ERROR;
6460 break;
6461 }
6462 }
6463 else if (htim->State == HAL_TIM_STATE_RESET)
6464 {
6465 switch (CallbackID)
6466 {
6467 case HAL_TIM_BASE_MSPINIT_CB_ID :
6468 htim->Base_MspInitCallback = pCallback;
6469 break;
6470
6471 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6472 htim->Base_MspDeInitCallback = pCallback;
6473 break;
6474
6475 case HAL_TIM_IC_MSPINIT_CB_ID :
6476 htim->IC_MspInitCallback = pCallback;
6477 break;
6478
6479 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6480 htim->IC_MspDeInitCallback = pCallback;
6481 break;
6482
6483 case HAL_TIM_OC_MSPINIT_CB_ID :
6484 htim->OC_MspInitCallback = pCallback;
6485 break;
6486
6487 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6488 htim->OC_MspDeInitCallback = pCallback;
6489 break;
6490
6491 case HAL_TIM_PWM_MSPINIT_CB_ID :
6492 htim->PWM_MspInitCallback = pCallback;
6493 break;
6494
6495 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6496 htim->PWM_MspDeInitCallback = pCallback;
6497 break;
6498
6499 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6500 htim->OnePulse_MspInitCallback = pCallback;
6501 break;
6502
6503 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6504 htim->OnePulse_MspDeInitCallback = pCallback;
6505 break;
6506
6507 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6508 htim->Encoder_MspInitCallback = pCallback;
6509 break;
6510
6511 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6512 htim->Encoder_MspDeInitCallback = pCallback;
6513 break;
6514
6515 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6516 htim->HallSensor_MspInitCallback = pCallback;
6517 break;
6518
6519 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6520 htim->HallSensor_MspDeInitCallback = pCallback;
6521 break;
6522
6523 default :
6524 /* Return error status */
6525 status = HAL_ERROR;
6526 break;
6527 }
6528 }
6529 else
6530 {
6531 /* Return error status */
6532 status = HAL_ERROR;
6533 }
6534
6535 return status;
6536 }
6537
6538 /**
6539 * @brief Unregister a TIM callback
6540 * TIM callback is redirected to the weak predefined callback
6541 * @param htim tim handle
6542 * @param CallbackID ID of the callback to be unregistered
6543 * This parameter can be one of the following values:
6544 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6545 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6546 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6547 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6548 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6549 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6550 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6551 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6552 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6553 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6554 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6555 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6556 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6557 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6558 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6559 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6560 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6561 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6562 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6563 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6564 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6565 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6566 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6567 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6568 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6569 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6570 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6571 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6572 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6573 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6574 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6575 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6576 * @retval status
6577 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6578 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6579 {
6580 HAL_StatusTypeDef status = HAL_OK;
6581
6582 if (htim->State == HAL_TIM_STATE_READY)
6583 {
6584 switch (CallbackID)
6585 {
6586 case HAL_TIM_BASE_MSPINIT_CB_ID :
6587 /* Legacy weak Base MspInit Callback */
6588 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6589 break;
6590
6591 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6592 /* Legacy weak Base Msp DeInit Callback */
6593 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6594 break;
6595
6596 case HAL_TIM_IC_MSPINIT_CB_ID :
6597 /* Legacy weak IC Msp Init Callback */
6598 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6599 break;
6600
6601 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6602 /* Legacy weak IC Msp DeInit Callback */
6603 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6604 break;
6605
6606 case HAL_TIM_OC_MSPINIT_CB_ID :
6607 /* Legacy weak OC Msp Init Callback */
6608 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6609 break;
6610
6611 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6612 /* Legacy weak OC Msp DeInit Callback */
6613 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6614 break;
6615
6616 case HAL_TIM_PWM_MSPINIT_CB_ID :
6617 /* Legacy weak PWM Msp Init Callback */
6618 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6619 break;
6620
6621 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6622 /* Legacy weak PWM Msp DeInit Callback */
6623 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6624 break;
6625
6626 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6627 /* Legacy weak One Pulse Msp Init Callback */
6628 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6629 break;
6630
6631 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6632 /* Legacy weak One Pulse Msp DeInit Callback */
6633 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6634 break;
6635
6636 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6637 /* Legacy weak Encoder Msp Init Callback */
6638 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6639 break;
6640
6641 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6642 /* Legacy weak Encoder Msp DeInit Callback */
6643 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6644 break;
6645
6646 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6647 /* Legacy weak Hall Sensor Msp Init Callback */
6648 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6649 break;
6650
6651 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6652 /* Legacy weak Hall Sensor Msp DeInit Callback */
6653 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6654 break;
6655
6656 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6657 /* Legacy weak Period Elapsed Callback */
6658 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6659 break;
6660
6661 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6662 /* Legacy weak Period Elapsed half complete Callback */
6663 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6664 break;
6665
6666 case HAL_TIM_TRIGGER_CB_ID :
6667 /* Legacy weak Trigger Callback */
6668 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6669 break;
6670
6671 case HAL_TIM_TRIGGER_HALF_CB_ID :
6672 /* Legacy weak Trigger half complete Callback */
6673 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6674 break;
6675
6676 case HAL_TIM_IC_CAPTURE_CB_ID :
6677 /* Legacy weak IC Capture Callback */
6678 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6679 break;
6680
6681 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6682 /* Legacy weak IC Capture half complete Callback */
6683 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6684 break;
6685
6686 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6687 /* Legacy weak OC Delay Elapsed Callback */
6688 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6689 break;
6690
6691 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6692 /* Legacy weak PWM Pulse Finished Callback */
6693 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6694 break;
6695
6696 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6697 /* Legacy weak PWM Pulse Finished half complete Callback */
6698 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6699 break;
6700
6701 case HAL_TIM_ERROR_CB_ID :
6702 /* Legacy weak Error Callback */
6703 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6704 break;
6705
6706 case HAL_TIM_COMMUTATION_CB_ID :
6707 /* Legacy weak Commutation Callback */
6708 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6709 break;
6710
6711 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6712 /* Legacy weak Commutation half complete Callback */
6713 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6714 break;
6715
6716 case HAL_TIM_BREAK_CB_ID :
6717 /* Legacy weak Break Callback */
6718 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6719 break;
6720
6721 case HAL_TIM_BREAK2_CB_ID :
6722 /* Legacy weak Break2 Callback */
6723 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6724 break;
6725
6726 case HAL_TIM_ENCODER_INDEX_CB_ID :
6727 /* Legacy weak Encoder Index Callback */
6728 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
6729 break;
6730
6731 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6732 /* Legacy weak Direction Change Callback */
6733 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
6734 break;
6735
6736 case HAL_TIM_INDEX_ERROR_CB_ID :
6737 /* Legacy weak Index Error Callback */
6738 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
6739 break;
6740
6741 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6742 /* Legacy weak Transition Error Callback */
6743 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
6744 break;
6745
6746 default :
6747 /* Return error status */
6748 status = HAL_ERROR;
6749 break;
6750 }
6751 }
6752 else if (htim->State == HAL_TIM_STATE_RESET)
6753 {
6754 switch (CallbackID)
6755 {
6756 case HAL_TIM_BASE_MSPINIT_CB_ID :
6757 /* Legacy weak Base MspInit Callback */
6758 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6759 break;
6760
6761 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6762 /* Legacy weak Base Msp DeInit Callback */
6763 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6764 break;
6765
6766 case HAL_TIM_IC_MSPINIT_CB_ID :
6767 /* Legacy weak IC Msp Init Callback */
6768 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6769 break;
6770
6771 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6772 /* Legacy weak IC Msp DeInit Callback */
6773 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6774 break;
6775
6776 case HAL_TIM_OC_MSPINIT_CB_ID :
6777 /* Legacy weak OC Msp Init Callback */
6778 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6779 break;
6780
6781 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6782 /* Legacy weak OC Msp DeInit Callback */
6783 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6784 break;
6785
6786 case HAL_TIM_PWM_MSPINIT_CB_ID :
6787 /* Legacy weak PWM Msp Init Callback */
6788 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6789 break;
6790
6791 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6792 /* Legacy weak PWM Msp DeInit Callback */
6793 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6794 break;
6795
6796 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6797 /* Legacy weak One Pulse Msp Init Callback */
6798 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6799 break;
6800
6801 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6802 /* Legacy weak One Pulse Msp DeInit Callback */
6803 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6804 break;
6805
6806 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6807 /* Legacy weak Encoder Msp Init Callback */
6808 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6809 break;
6810
6811 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6812 /* Legacy weak Encoder Msp DeInit Callback */
6813 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6814 break;
6815
6816 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6817 /* Legacy weak Hall Sensor Msp Init Callback */
6818 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6819 break;
6820
6821 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6822 /* Legacy weak Hall Sensor Msp DeInit Callback */
6823 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6824 break;
6825
6826 default :
6827 /* Return error status */
6828 status = HAL_ERROR;
6829 break;
6830 }
6831 }
6832 else
6833 {
6834 /* Return error status */
6835 status = HAL_ERROR;
6836 }
6837
6838 return status;
6839 }
6840 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6841
6842 /**
6843 * @}
6844 */
6845
6846 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6847 * @brief TIM Peripheral State functions
6848 *
6849 @verbatim
6850 ==============================================================================
6851 ##### Peripheral State functions #####
6852 ==============================================================================
6853 [..]
6854 This subsection permits to get in run-time the status of the peripheral
6855 and the data flow.
6856
6857 @endverbatim
6858 * @{
6859 */
6860
6861 /**
6862 * @brief Return the TIM Base handle state.
6863 * @param htim TIM Base handle
6864 * @retval HAL state
6865 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6866 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6867 {
6868 return htim->State;
6869 }
6870
6871 /**
6872 * @brief Return the TIM OC handle state.
6873 * @param htim TIM Output Compare handle
6874 * @retval HAL state
6875 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6876 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6877 {
6878 return htim->State;
6879 }
6880
6881 /**
6882 * @brief Return the TIM PWM handle state.
6883 * @param htim TIM handle
6884 * @retval HAL state
6885 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6886 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6887 {
6888 return htim->State;
6889 }
6890
6891 /**
6892 * @brief Return the TIM Input Capture handle state.
6893 * @param htim TIM IC handle
6894 * @retval HAL state
6895 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6896 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6897 {
6898 return htim->State;
6899 }
6900
6901 /**
6902 * @brief Return the TIM One Pulse Mode handle state.
6903 * @param htim TIM OPM handle
6904 * @retval HAL state
6905 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6906 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6907 {
6908 return htim->State;
6909 }
6910
6911 /**
6912 * @brief Return the TIM Encoder Mode handle state.
6913 * @param htim TIM Encoder Interface handle
6914 * @retval HAL state
6915 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6916 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6917 {
6918 return htim->State;
6919 }
6920
6921 /**
6922 * @brief Return the TIM Encoder Mode handle state.
6923 * @param htim TIM handle
6924 * @retval Active channel
6925 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6926 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6927 {
6928 return htim->Channel;
6929 }
6930
6931 /**
6932 * @brief Return actual state of the TIM channel.
6933 * @param htim TIM handle
6934 * @param Channel TIM Channel
6935 * This parameter can be one of the following values:
6936 * @arg TIM_CHANNEL_1: TIM Channel 1
6937 * @arg TIM_CHANNEL_2: TIM Channel 2
6938 * @arg TIM_CHANNEL_3: TIM Channel 3
6939 * @arg TIM_CHANNEL_4: TIM Channel 4
6940 * @arg TIM_CHANNEL_5: TIM Channel 5
6941 * @arg TIM_CHANNEL_6: TIM Channel 6
6942 * @retval TIM Channel state
6943 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6944 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6945 {
6946 HAL_TIM_ChannelStateTypeDef channel_state;
6947
6948 /* Check the parameters */
6949 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6950
6951 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6952
6953 return channel_state;
6954 }
6955
6956 /**
6957 * @brief Return actual state of a DMA burst operation.
6958 * @param htim TIM handle
6959 * @retval DMA burst state
6960 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6961 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6962 {
6963 /* Check the parameters */
6964 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6965
6966 return htim->DMABurstState;
6967 }
6968
6969 /**
6970 * @}
6971 */
6972
6973 /**
6974 * @}
6975 */
6976
6977 /** @defgroup TIM_Private_Functions TIM Private Functions
6978 * @{
6979 */
6980
6981 /**
6982 * @brief TIM DMA error callback
6983 * @param hdma pointer to DMA handle.
6984 * @retval None
6985 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6986 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6987 {
6988 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6989
6990 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6991 {
6992 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6993 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6994 }
6995 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6996 {
6997 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6998 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6999 }
7000 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7001 {
7002 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7003 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7004 }
7005 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7006 {
7007 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7008 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7009 }
7010 else
7011 {
7012 htim->State = HAL_TIM_STATE_READY;
7013 }
7014
7015 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7016 htim->ErrorCallback(htim);
7017 #else
7018 HAL_TIM_ErrorCallback(htim);
7019 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7020
7021 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7022 }
7023
7024 /**
7025 * @brief TIM DMA Delay Pulse complete callback.
7026 * @param hdma pointer to DMA handle.
7027 * @retval None
7028 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)7029 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
7030 {
7031 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7032
7033 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7034 {
7035 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7036
7037 if (hdma->Init.Mode == DMA_NORMAL)
7038 {
7039 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
7040 }
7041 }
7042 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7043 {
7044 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7045
7046 if (hdma->Init.Mode == DMA_NORMAL)
7047 {
7048 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
7049 }
7050 }
7051 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7052 {
7053 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7054
7055 if (hdma->Init.Mode == DMA_NORMAL)
7056 {
7057 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7058 }
7059 }
7060 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7061 {
7062 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7063
7064 if (hdma->Init.Mode == DMA_NORMAL)
7065 {
7066 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7067 }
7068 }
7069 else
7070 {
7071 /* nothing to do */
7072 }
7073
7074 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7075 htim->PWM_PulseFinishedCallback(htim);
7076 #else
7077 HAL_TIM_PWM_PulseFinishedCallback(htim);
7078 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7079
7080 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7081 }
7082
7083 /**
7084 * @brief TIM DMA Delay Pulse half complete callback.
7085 * @param hdma pointer to DMA handle.
7086 * @retval None
7087 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)7088 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
7089 {
7090 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7091
7092 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7093 {
7094 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7095 }
7096 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7097 {
7098 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7099 }
7100 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7101 {
7102 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7103 }
7104 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7105 {
7106 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7107 }
7108 else
7109 {
7110 /* nothing to do */
7111 }
7112
7113 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7114 htim->PWM_PulseFinishedHalfCpltCallback(htim);
7115 #else
7116 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
7117 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7118
7119 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7120 }
7121
7122 /**
7123 * @brief TIM DMA Capture complete callback.
7124 * @param hdma pointer to DMA handle.
7125 * @retval None
7126 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)7127 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
7128 {
7129 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7130
7131 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7132 {
7133 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7134
7135 if (hdma->Init.Mode == DMA_NORMAL)
7136 {
7137 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
7138 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
7139 }
7140 }
7141 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7142 {
7143 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7144
7145 if (hdma->Init.Mode == DMA_NORMAL)
7146 {
7147 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
7148 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
7149 }
7150 }
7151 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7152 {
7153 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7154
7155 if (hdma->Init.Mode == DMA_NORMAL)
7156 {
7157 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7158 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7159 }
7160 }
7161 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7162 {
7163 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7164
7165 if (hdma->Init.Mode == DMA_NORMAL)
7166 {
7167 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7168 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7169 }
7170 }
7171 else
7172 {
7173 /* nothing to do */
7174 }
7175
7176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7177 htim->IC_CaptureCallback(htim);
7178 #else
7179 HAL_TIM_IC_CaptureCallback(htim);
7180 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7181
7182 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7183 }
7184
7185 /**
7186 * @brief TIM DMA Capture half complete callback.
7187 * @param hdma pointer to DMA handle.
7188 * @retval None
7189 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)7190 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
7191 {
7192 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7193
7194 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7195 {
7196 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7197 }
7198 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7199 {
7200 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7201 }
7202 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7203 {
7204 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7205 }
7206 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7207 {
7208 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7209 }
7210 else
7211 {
7212 /* nothing to do */
7213 }
7214
7215 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7216 htim->IC_CaptureHalfCpltCallback(htim);
7217 #else
7218 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
7219 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7220
7221 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7222 }
7223
7224 /**
7225 * @brief TIM DMA Period Elapse complete callback.
7226 * @param hdma pointer to DMA handle.
7227 * @retval None
7228 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)7229 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
7230 {
7231 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7232
7233 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
7234 {
7235 htim->State = HAL_TIM_STATE_READY;
7236 }
7237
7238 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7239 htim->PeriodElapsedCallback(htim);
7240 #else
7241 HAL_TIM_PeriodElapsedCallback(htim);
7242 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7243 }
7244
7245 /**
7246 * @brief TIM DMA Period Elapse half complete callback.
7247 * @param hdma pointer to DMA handle.
7248 * @retval None
7249 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)7250 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
7251 {
7252 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7253
7254 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7255 htim->PeriodElapsedHalfCpltCallback(htim);
7256 #else
7257 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
7258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7259 }
7260
7261 /**
7262 * @brief TIM DMA Trigger callback.
7263 * @param hdma pointer to DMA handle.
7264 * @retval None
7265 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)7266 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
7267 {
7268 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7269
7270 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
7271 {
7272 htim->State = HAL_TIM_STATE_READY;
7273 }
7274
7275 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7276 htim->TriggerCallback(htim);
7277 #else
7278 HAL_TIM_TriggerCallback(htim);
7279 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7280 }
7281
7282 /**
7283 * @brief TIM DMA Trigger half complete callback.
7284 * @param hdma pointer to DMA handle.
7285 * @retval None
7286 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)7287 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
7288 {
7289 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7290
7291 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7292 htim->TriggerHalfCpltCallback(htim);
7293 #else
7294 HAL_TIM_TriggerHalfCpltCallback(htim);
7295 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7296 }
7297
7298 /**
7299 * @brief Time Base configuration
7300 * @param TIMx TIM peripheral
7301 * @param Structure TIM Base configuration structure
7302 * @retval None
7303 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)7304 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
7305 {
7306 uint32_t tmpcr1;
7307 tmpcr1 = TIMx->CR1;
7308
7309 /* Set TIM Time Base Unit parameters ---------------------------------------*/
7310 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
7311 {
7312 /* Select the Counter Mode */
7313 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
7314 tmpcr1 |= Structure->CounterMode;
7315 }
7316
7317 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
7318 {
7319 /* Set the clock division */
7320 tmpcr1 &= ~TIM_CR1_CKD;
7321 tmpcr1 |= (uint32_t)Structure->ClockDivision;
7322 }
7323
7324 /* Set the auto-reload preload */
7325 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
7326
7327 TIMx->CR1 = tmpcr1;
7328
7329 /* Set the Autoreload value */
7330 TIMx->ARR = (uint32_t)Structure->Period ;
7331
7332 /* Set the Prescaler value */
7333 TIMx->PSC = Structure->Prescaler;
7334
7335 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7336 {
7337 /* Set the Repetition Counter value */
7338 TIMx->RCR = Structure->RepetitionCounter;
7339 }
7340
7341 /* Generate an update event to reload the Prescaler
7342 and the repetition counter (only for advanced timer) value immediately */
7343 TIMx->EGR = TIM_EGR_UG;
7344 }
7345
7346 /**
7347 * @brief Timer Output Compare 1 configuration
7348 * @param TIMx to select the TIM peripheral
7349 * @param OC_Config The output configuration structure
7350 * @retval None
7351 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7352 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7353 {
7354 uint32_t tmpccmrx;
7355 uint32_t tmpccer;
7356 uint32_t tmpcr2;
7357
7358 /* Get the TIMx CCER register value */
7359 tmpccer = TIMx->CCER;
7360
7361 /* Disable the Channel 1: Reset the CC1E Bit */
7362 TIMx->CCER &= ~TIM_CCER_CC1E;
7363
7364 /* Get the TIMx CR2 register value */
7365 tmpcr2 = TIMx->CR2;
7366
7367 /* Get the TIMx CCMR1 register value */
7368 tmpccmrx = TIMx->CCMR1;
7369
7370 /* Reset the Output Compare Mode Bits */
7371 tmpccmrx &= ~TIM_CCMR1_OC1M;
7372 tmpccmrx &= ~TIM_CCMR1_CC1S;
7373 /* Select the Output Compare Mode */
7374 tmpccmrx |= OC_Config->OCMode;
7375
7376 /* Reset the Output Polarity level */
7377 tmpccer &= ~TIM_CCER_CC1P;
7378 /* Set the Output Compare Polarity */
7379 tmpccer |= OC_Config->OCPolarity;
7380
7381 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7382 {
7383 /* Check parameters */
7384 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7385
7386 /* Reset the Output N Polarity level */
7387 tmpccer &= ~TIM_CCER_CC1NP;
7388 /* Set the Output N Polarity */
7389 tmpccer |= OC_Config->OCNPolarity;
7390 /* Reset the Output N State */
7391 tmpccer &= ~TIM_CCER_CC1NE;
7392 }
7393
7394 if (IS_TIM_BREAK_INSTANCE(TIMx))
7395 {
7396 /* Check parameters */
7397 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7398 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7399
7400 /* Reset the Output Compare and Output Compare N IDLE State */
7401 tmpcr2 &= ~TIM_CR2_OIS1;
7402 tmpcr2 &= ~TIM_CR2_OIS1N;
7403 /* Set the Output Idle state */
7404 tmpcr2 |= OC_Config->OCIdleState;
7405 /* Set the Output N Idle state */
7406 tmpcr2 |= OC_Config->OCNIdleState;
7407 }
7408
7409 /* Write to TIMx CR2 */
7410 TIMx->CR2 = tmpcr2;
7411
7412 /* Write to TIMx CCMR1 */
7413 TIMx->CCMR1 = tmpccmrx;
7414
7415 /* Set the Capture Compare Register value */
7416 TIMx->CCR1 = OC_Config->Pulse;
7417
7418 /* Write to TIMx CCER */
7419 TIMx->CCER = tmpccer;
7420 }
7421
7422 /**
7423 * @brief Timer Output Compare 2 configuration
7424 * @param TIMx to select the TIM peripheral
7425 * @param OC_Config The output configuration structure
7426 * @retval None
7427 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7428 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7429 {
7430 uint32_t tmpccmrx;
7431 uint32_t tmpccer;
7432 uint32_t tmpcr2;
7433
7434 /* Get the TIMx CCER register value */
7435 tmpccer = TIMx->CCER;
7436
7437 /* Disable the Channel 2: Reset the CC2E Bit */
7438 TIMx->CCER &= ~TIM_CCER_CC2E;
7439
7440 /* Get the TIMx CR2 register value */
7441 tmpcr2 = TIMx->CR2;
7442
7443 /* Get the TIMx CCMR1 register value */
7444 tmpccmrx = TIMx->CCMR1;
7445
7446 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7447 tmpccmrx &= ~TIM_CCMR1_OC2M;
7448 tmpccmrx &= ~TIM_CCMR1_CC2S;
7449
7450 /* Select the Output Compare Mode */
7451 tmpccmrx |= (OC_Config->OCMode << 8U);
7452
7453 /* Reset the Output Polarity level */
7454 tmpccer &= ~TIM_CCER_CC2P;
7455 /* Set the Output Compare Polarity */
7456 tmpccer |= (OC_Config->OCPolarity << 4U);
7457
7458 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7459 {
7460 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7461
7462 /* Reset the Output N Polarity level */
7463 tmpccer &= ~TIM_CCER_CC2NP;
7464 /* Set the Output N Polarity */
7465 tmpccer |= (OC_Config->OCNPolarity << 4U);
7466 /* Reset the Output N State */
7467 tmpccer &= ~TIM_CCER_CC2NE;
7468
7469 }
7470
7471 if (IS_TIM_BREAK_INSTANCE(TIMx))
7472 {
7473 /* Check parameters */
7474 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7475 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7476
7477 /* Reset the Output Compare and Output Compare N IDLE State */
7478 tmpcr2 &= ~TIM_CR2_OIS2;
7479 tmpcr2 &= ~TIM_CR2_OIS2N;
7480 /* Set the Output Idle state */
7481 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7482 /* Set the Output N Idle state */
7483 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7484 }
7485
7486 /* Write to TIMx CR2 */
7487 TIMx->CR2 = tmpcr2;
7488
7489 /* Write to TIMx CCMR1 */
7490 TIMx->CCMR1 = tmpccmrx;
7491
7492 /* Set the Capture Compare Register value */
7493 TIMx->CCR2 = OC_Config->Pulse;
7494
7495 /* Write to TIMx CCER */
7496 TIMx->CCER = tmpccer;
7497 }
7498
7499 /**
7500 * @brief Timer Output Compare 3 configuration
7501 * @param TIMx to select the TIM peripheral
7502 * @param OC_Config The output configuration structure
7503 * @retval None
7504 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7505 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7506 {
7507 uint32_t tmpccmrx;
7508 uint32_t tmpccer;
7509 uint32_t tmpcr2;
7510
7511 /* Get the TIMx CCER register value */
7512 tmpccer = TIMx->CCER;
7513
7514 /* Disable the Channel 3: Reset the CC2E Bit */
7515 TIMx->CCER &= ~TIM_CCER_CC3E;
7516
7517 /* Get the TIMx CR2 register value */
7518 tmpcr2 = TIMx->CR2;
7519
7520 /* Get the TIMx CCMR2 register value */
7521 tmpccmrx = TIMx->CCMR2;
7522
7523 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7524 tmpccmrx &= ~TIM_CCMR2_OC3M;
7525 tmpccmrx &= ~TIM_CCMR2_CC3S;
7526 /* Select the Output Compare Mode */
7527 tmpccmrx |= OC_Config->OCMode;
7528
7529 /* Reset the Output Polarity level */
7530 tmpccer &= ~TIM_CCER_CC3P;
7531 /* Set the Output Compare Polarity */
7532 tmpccer |= (OC_Config->OCPolarity << 8U);
7533
7534 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7535 {
7536 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7537
7538 /* Reset the Output N Polarity level */
7539 tmpccer &= ~TIM_CCER_CC3NP;
7540 /* Set the Output N Polarity */
7541 tmpccer |= (OC_Config->OCNPolarity << 8U);
7542 /* Reset the Output N State */
7543 tmpccer &= ~TIM_CCER_CC3NE;
7544 }
7545
7546 if (IS_TIM_BREAK_INSTANCE(TIMx))
7547 {
7548 /* Check parameters */
7549 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7550 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7551
7552 /* Reset the Output Compare and Output Compare N IDLE State */
7553 tmpcr2 &= ~TIM_CR2_OIS3;
7554 tmpcr2 &= ~TIM_CR2_OIS3N;
7555 /* Set the Output Idle state */
7556 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7557 /* Set the Output N Idle state */
7558 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7559 }
7560
7561 /* Write to TIMx CR2 */
7562 TIMx->CR2 = tmpcr2;
7563
7564 /* Write to TIMx CCMR2 */
7565 TIMx->CCMR2 = tmpccmrx;
7566
7567 /* Set the Capture Compare Register value */
7568 TIMx->CCR3 = OC_Config->Pulse;
7569
7570 /* Write to TIMx CCER */
7571 TIMx->CCER = tmpccer;
7572 }
7573
7574 /**
7575 * @brief Timer Output Compare 4 configuration
7576 * @param TIMx to select the TIM peripheral
7577 * @param OC_Config The output configuration structure
7578 * @retval None
7579 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7580 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7581 {
7582 uint32_t tmpccmrx;
7583 uint32_t tmpccer;
7584 uint32_t tmpcr2;
7585
7586 /* Get the TIMx CCER register value */
7587 tmpccer = TIMx->CCER;
7588
7589 /* Disable the Channel 4: Reset the CC4E Bit */
7590 TIMx->CCER &= ~TIM_CCER_CC4E;
7591
7592 /* Get the TIMx CR2 register value */
7593 tmpcr2 = TIMx->CR2;
7594
7595 /* Get the TIMx CCMR2 register value */
7596 tmpccmrx = TIMx->CCMR2;
7597
7598 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7599 tmpccmrx &= ~TIM_CCMR2_OC4M;
7600 tmpccmrx &= ~TIM_CCMR2_CC4S;
7601
7602 /* Select the Output Compare Mode */
7603 tmpccmrx |= (OC_Config->OCMode << 8U);
7604
7605 /* Reset the Output Polarity level */
7606 tmpccer &= ~TIM_CCER_CC4P;
7607 /* Set the Output Compare Polarity */
7608 tmpccer |= (OC_Config->OCPolarity << 12U);
7609
7610 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7611 {
7612 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7613
7614 /* Reset the Output N Polarity level */
7615 tmpccer &= ~TIM_CCER_CC4NP;
7616 /* Set the Output N Polarity */
7617 tmpccer |= (OC_Config->OCNPolarity << 12U);
7618 /* Reset the Output N State */
7619 tmpccer &= ~TIM_CCER_CC4NE;
7620 }
7621
7622 if (IS_TIM_BREAK_INSTANCE(TIMx))
7623 {
7624 /* Check parameters */
7625 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7626 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7627
7628 /* Reset the Output Compare IDLE State */
7629 tmpcr2 &= ~TIM_CR2_OIS4;
7630 /* Reset the Output Compare N IDLE State */
7631 tmpcr2 &= ~TIM_CR2_OIS4N;
7632
7633 /* Set the Output Idle state */
7634 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7635 /* Set the Output N Idle state */
7636 tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7637 }
7638
7639 /* Write to TIMx CR2 */
7640 TIMx->CR2 = tmpcr2;
7641
7642 /* Write to TIMx CCMR2 */
7643 TIMx->CCMR2 = tmpccmrx;
7644
7645 /* Set the Capture Compare Register value */
7646 TIMx->CCR4 = OC_Config->Pulse;
7647
7648 /* Write to TIMx CCER */
7649 TIMx->CCER = tmpccer;
7650 }
7651
7652 /**
7653 * @brief Timer Output Compare 5 configuration
7654 * @param TIMx to select the TIM peripheral
7655 * @param OC_Config The output configuration structure
7656 * @retval None
7657 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7658 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7659 const TIM_OC_InitTypeDef *OC_Config)
7660 {
7661 uint32_t tmpccmrx;
7662 uint32_t tmpccer;
7663 uint32_t tmpcr2;
7664
7665 /* Get the TIMx CCER register value */
7666 tmpccer = TIMx->CCER;
7667
7668 /* Disable the output: Reset the CCxE Bit */
7669 TIMx->CCER &= ~TIM_CCER_CC5E;
7670
7671 /* Get the TIMx CR2 register value */
7672 tmpcr2 = TIMx->CR2;
7673 /* Get the TIMx CCMR1 register value */
7674 tmpccmrx = TIMx->CCMR3;
7675
7676 /* Reset the Output Compare Mode Bits */
7677 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7678 /* Select the Output Compare Mode */
7679 tmpccmrx |= OC_Config->OCMode;
7680
7681 /* Reset the Output Polarity level */
7682 tmpccer &= ~TIM_CCER_CC5P;
7683 /* Set the Output Compare Polarity */
7684 tmpccer |= (OC_Config->OCPolarity << 16U);
7685
7686 if (IS_TIM_BREAK_INSTANCE(TIMx))
7687 {
7688 /* Reset the Output Compare IDLE State */
7689 tmpcr2 &= ~TIM_CR2_OIS5;
7690 /* Set the Output Idle state */
7691 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7692 }
7693 /* Write to TIMx CR2 */
7694 TIMx->CR2 = tmpcr2;
7695
7696 /* Write to TIMx CCMR3 */
7697 TIMx->CCMR3 = tmpccmrx;
7698
7699 /* Set the Capture Compare Register value */
7700 TIMx->CCR5 = OC_Config->Pulse;
7701
7702 /* Write to TIMx CCER */
7703 TIMx->CCER = tmpccer;
7704 }
7705
7706 /**
7707 * @brief Timer Output Compare 6 configuration
7708 * @param TIMx to select the TIM peripheral
7709 * @param OC_Config The output configuration structure
7710 * @retval None
7711 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7712 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7713 const TIM_OC_InitTypeDef *OC_Config)
7714 {
7715 uint32_t tmpccmrx;
7716 uint32_t tmpccer;
7717 uint32_t tmpcr2;
7718
7719 /* Get the TIMx CCER register value */
7720 tmpccer = TIMx->CCER;
7721
7722 /* Disable the output: Reset the CCxE Bit */
7723 TIMx->CCER &= ~TIM_CCER_CC6E;
7724
7725 /* Get the TIMx CR2 register value */
7726 tmpcr2 = TIMx->CR2;
7727 /* Get the TIMx CCMR1 register value */
7728 tmpccmrx = TIMx->CCMR3;
7729
7730 /* Reset the Output Compare Mode Bits */
7731 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7732 /* Select the Output Compare Mode */
7733 tmpccmrx |= (OC_Config->OCMode << 8U);
7734
7735 /* Reset the Output Polarity level */
7736 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7737 /* Set the Output Compare Polarity */
7738 tmpccer |= (OC_Config->OCPolarity << 20U);
7739
7740 if (IS_TIM_BREAK_INSTANCE(TIMx))
7741 {
7742 /* Reset the Output Compare IDLE State */
7743 tmpcr2 &= ~TIM_CR2_OIS6;
7744 /* Set the Output Idle state */
7745 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7746 }
7747
7748 /* Write to TIMx CR2 */
7749 TIMx->CR2 = tmpcr2;
7750
7751 /* Write to TIMx CCMR3 */
7752 TIMx->CCMR3 = tmpccmrx;
7753
7754 /* Set the Capture Compare Register value */
7755 TIMx->CCR6 = OC_Config->Pulse;
7756
7757 /* Write to TIMx CCER */
7758 TIMx->CCER = tmpccer;
7759 }
7760
7761 /**
7762 * @brief Slave Timer configuration function
7763 * @param htim TIM handle
7764 * @param sSlaveConfig Slave timer configuration
7765 * @retval None
7766 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7767 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7768 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7769 {
7770 HAL_StatusTypeDef status = HAL_OK;
7771 uint32_t tmpsmcr;
7772 uint32_t tmpccmr1;
7773 uint32_t tmpccer;
7774
7775 /* Get the TIMx SMCR register value */
7776 tmpsmcr = htim->Instance->SMCR;
7777
7778 /* Reset the Trigger Selection Bits */
7779 tmpsmcr &= ~TIM_SMCR_TS;
7780 /* Set the Input Trigger source */
7781 tmpsmcr |= sSlaveConfig->InputTrigger;
7782
7783 /* Reset the slave mode Bits */
7784 tmpsmcr &= ~TIM_SMCR_SMS;
7785 /* Set the slave mode */
7786 tmpsmcr |= sSlaveConfig->SlaveMode;
7787
7788 /* Write to TIMx SMCR */
7789 htim->Instance->SMCR = tmpsmcr;
7790
7791 /* Configure the trigger prescaler, filter, and polarity */
7792 switch (sSlaveConfig->InputTrigger)
7793 {
7794 case TIM_TS_ETRF:
7795 {
7796 /* Check the parameters */
7797 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7798 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7799 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7800 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7801 /* Configure the ETR Trigger source */
7802 TIM_ETR_SetConfig(htim->Instance,
7803 sSlaveConfig->TriggerPrescaler,
7804 sSlaveConfig->TriggerPolarity,
7805 sSlaveConfig->TriggerFilter);
7806 break;
7807 }
7808
7809 case TIM_TS_TI1F_ED:
7810 {
7811 /* Check the parameters */
7812 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7813 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7814
7815 if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
7816 (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7817 {
7818 return HAL_ERROR;
7819 }
7820
7821 /* Disable the Channel 1: Reset the CC1E Bit */
7822 tmpccer = htim->Instance->CCER;
7823 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7824 tmpccmr1 = htim->Instance->CCMR1;
7825
7826 /* Set the filter */
7827 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7828 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7829
7830 /* Write to TIMx CCMR1 and CCER registers */
7831 htim->Instance->CCMR1 = tmpccmr1;
7832 htim->Instance->CCER = tmpccer;
7833 break;
7834 }
7835
7836 case TIM_TS_TI1FP1:
7837 {
7838 /* Check the parameters */
7839 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7840 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7841 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7842
7843 /* Configure TI1 Filter and Polarity */
7844 TIM_TI1_ConfigInputStage(htim->Instance,
7845 sSlaveConfig->TriggerPolarity,
7846 sSlaveConfig->TriggerFilter);
7847 break;
7848 }
7849
7850 case TIM_TS_TI2FP2:
7851 {
7852 /* Check the parameters */
7853 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7854 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7855 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7856
7857 /* Configure TI2 Filter and Polarity */
7858 TIM_TI2_ConfigInputStage(htim->Instance,
7859 sSlaveConfig->TriggerPolarity,
7860 sSlaveConfig->TriggerFilter);
7861 break;
7862 }
7863
7864 case TIM_TS_ITR0:
7865 case TIM_TS_ITR1:
7866 case TIM_TS_ITR2:
7867 case TIM_TS_ITR3:
7868 case TIM_TS_ITR4:
7869 case TIM_TS_ITR5:
7870 case TIM_TS_ITR6:
7871 case TIM_TS_ITR7:
7872 case TIM_TS_ITR8:
7873 case TIM_TS_ITR9:
7874 case TIM_TS_ITR10:
7875 case TIM_TS_ITR11:
7876 case TIM_TS_ITR12:
7877 {
7878 /* Check the parameter */
7879 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7880 break;
7881 }
7882
7883 default:
7884 status = HAL_ERROR;
7885 break;
7886 }
7887
7888 return status;
7889 }
7890
7891 /**
7892 * @brief Configure the TI1 as Input.
7893 * @param TIMx to select the TIM peripheral.
7894 * @param TIM_ICPolarity The Input Polarity.
7895 * This parameter can be one of the following values:
7896 * @arg TIM_ICPOLARITY_RISING
7897 * @arg TIM_ICPOLARITY_FALLING
7898 * @arg TIM_ICPOLARITY_BOTHEDGE
7899 * @param TIM_ICSelection specifies the input to be used.
7900 * This parameter can be one of the following values:
7901 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7902 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7903 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7904 * @param TIM_ICFilter Specifies the Input Capture Filter.
7905 * This parameter must be a value between 0x00 and 0x0F.
7906 * @retval None
7907 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7908 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7909 * protected against un-initialized filter and polarity values.
7910 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7911 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7912 uint32_t TIM_ICFilter)
7913 {
7914 uint32_t tmpccmr1;
7915 uint32_t tmpccer;
7916
7917 /* Disable the Channel 1: Reset the CC1E Bit */
7918 tmpccer = TIMx->CCER;
7919 TIMx->CCER &= ~TIM_CCER_CC1E;
7920 tmpccmr1 = TIMx->CCMR1;
7921
7922 /* Select the Input */
7923 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7924 {
7925 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7926 tmpccmr1 |= TIM_ICSelection;
7927 }
7928 else
7929 {
7930 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7931 }
7932
7933 /* Set the filter */
7934 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7935 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7936
7937 /* Select the Polarity and set the CC1E Bit */
7938 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7939 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7940
7941 /* Write to TIMx CCMR1 and CCER registers */
7942 TIMx->CCMR1 = tmpccmr1;
7943 TIMx->CCER = tmpccer;
7944 }
7945
7946 /**
7947 * @brief Configure the Polarity and Filter for TI1.
7948 * @param TIMx to select the TIM peripheral.
7949 * @param TIM_ICPolarity The Input Polarity.
7950 * This parameter can be one of the following values:
7951 * @arg TIM_ICPOLARITY_RISING
7952 * @arg TIM_ICPOLARITY_FALLING
7953 * @arg TIM_ICPOLARITY_BOTHEDGE
7954 * @param TIM_ICFilter Specifies the Input Capture Filter.
7955 * This parameter must be a value between 0x00 and 0x0F.
7956 * @retval None
7957 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7958 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7959 {
7960 uint32_t tmpccmr1;
7961 uint32_t tmpccer;
7962
7963 /* Disable the Channel 1: Reset the CC1E Bit */
7964 tmpccer = TIMx->CCER;
7965 TIMx->CCER &= ~TIM_CCER_CC1E;
7966 tmpccmr1 = TIMx->CCMR1;
7967
7968 /* Set the filter */
7969 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7970 tmpccmr1 |= (TIM_ICFilter << 4U);
7971
7972 /* Select the Polarity and set the CC1E Bit */
7973 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7974 tmpccer |= TIM_ICPolarity;
7975
7976 /* Write to TIMx CCMR1 and CCER registers */
7977 TIMx->CCMR1 = tmpccmr1;
7978 TIMx->CCER = tmpccer;
7979 }
7980
7981 /**
7982 * @brief Configure the TI2 as Input.
7983 * @param TIMx to select the TIM peripheral
7984 * @param TIM_ICPolarity The Input Polarity.
7985 * This parameter can be one of the following values:
7986 * @arg TIM_ICPOLARITY_RISING
7987 * @arg TIM_ICPOLARITY_FALLING
7988 * @arg TIM_ICPOLARITY_BOTHEDGE
7989 * @param TIM_ICSelection specifies the input to be used.
7990 * This parameter can be one of the following values:
7991 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7992 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7993 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7994 * @param TIM_ICFilter Specifies the Input Capture Filter.
7995 * This parameter must be a value between 0x00 and 0x0F.
7996 * @retval None
7997 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7998 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7999 * protected against un-initialized filter and polarity values.
8000 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8001 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8002 uint32_t TIM_ICFilter)
8003 {
8004 uint32_t tmpccmr1;
8005 uint32_t tmpccer;
8006
8007 /* Disable the Channel 2: Reset the CC2E Bit */
8008 tmpccer = TIMx->CCER;
8009 TIMx->CCER &= ~TIM_CCER_CC2E;
8010 tmpccmr1 = TIMx->CCMR1;
8011
8012 /* Select the Input */
8013 tmpccmr1 &= ~TIM_CCMR1_CC2S;
8014 tmpccmr1 |= (TIM_ICSelection << 8U);
8015
8016 /* Set the filter */
8017 tmpccmr1 &= ~TIM_CCMR1_IC2F;
8018 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
8019
8020 /* Select the Polarity and set the CC2E Bit */
8021 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8022 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
8023
8024 /* Write to TIMx CCMR1 and CCER registers */
8025 TIMx->CCMR1 = tmpccmr1 ;
8026 TIMx->CCER = tmpccer;
8027 }
8028
8029 /**
8030 * @brief Configure the Polarity and Filter for TI2.
8031 * @param TIMx to select the TIM peripheral.
8032 * @param TIM_ICPolarity The Input Polarity.
8033 * This parameter can be one of the following values:
8034 * @arg TIM_ICPOLARITY_RISING
8035 * @arg TIM_ICPOLARITY_FALLING
8036 * @arg TIM_ICPOLARITY_BOTHEDGE
8037 * @param TIM_ICFilter Specifies the Input Capture Filter.
8038 * This parameter must be a value between 0x00 and 0x0F.
8039 * @retval None
8040 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)8041 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
8042 {
8043 uint32_t tmpccmr1;
8044 uint32_t tmpccer;
8045
8046 /* Disable the Channel 2: Reset the CC2E Bit */
8047 tmpccer = TIMx->CCER;
8048 TIMx->CCER &= ~TIM_CCER_CC2E;
8049 tmpccmr1 = TIMx->CCMR1;
8050
8051 /* Set the filter */
8052 tmpccmr1 &= ~TIM_CCMR1_IC2F;
8053 tmpccmr1 |= (TIM_ICFilter << 12U);
8054
8055 /* Select the Polarity and set the CC2E Bit */
8056 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8057 tmpccer |= (TIM_ICPolarity << 4U);
8058
8059 /* Write to TIMx CCMR1 and CCER registers */
8060 TIMx->CCMR1 = tmpccmr1 ;
8061 TIMx->CCER = tmpccer;
8062 }
8063
8064 /**
8065 * @brief Configure the TI3 as Input.
8066 * @param TIMx to select the TIM peripheral
8067 * @param TIM_ICPolarity The Input Polarity.
8068 * This parameter can be one of the following values:
8069 * @arg TIM_ICPOLARITY_RISING
8070 * @arg TIM_ICPOLARITY_FALLING
8071 * @arg TIM_ICPOLARITY_BOTHEDGE
8072 * @param TIM_ICSelection specifies the input to be used.
8073 * This parameter can be one of the following values:
8074 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
8075 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
8076 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
8077 * @param TIM_ICFilter Specifies the Input Capture Filter.
8078 * This parameter must be a value between 0x00 and 0x0F.
8079 * @retval None
8080 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
8081 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8082 * protected against un-initialized filter and polarity values.
8083 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8084 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8085 uint32_t TIM_ICFilter)
8086 {
8087 uint32_t tmpccmr2;
8088 uint32_t tmpccer;
8089
8090 /* Disable the Channel 3: Reset the CC3E Bit */
8091 tmpccer = TIMx->CCER;
8092 TIMx->CCER &= ~TIM_CCER_CC3E;
8093 tmpccmr2 = TIMx->CCMR2;
8094
8095 /* Select the Input */
8096 tmpccmr2 &= ~TIM_CCMR2_CC3S;
8097 tmpccmr2 |= TIM_ICSelection;
8098
8099 /* Set the filter */
8100 tmpccmr2 &= ~TIM_CCMR2_IC3F;
8101 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
8102
8103 /* Select the Polarity and set the CC3E Bit */
8104 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
8105 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
8106
8107 /* Write to TIMx CCMR2 and CCER registers */
8108 TIMx->CCMR2 = tmpccmr2;
8109 TIMx->CCER = tmpccer;
8110 }
8111
8112 /**
8113 * @brief Configure the TI4 as Input.
8114 * @param TIMx to select the TIM peripheral
8115 * @param TIM_ICPolarity The Input Polarity.
8116 * This parameter can be one of the following values:
8117 * @arg TIM_ICPOLARITY_RISING
8118 * @arg TIM_ICPOLARITY_FALLING
8119 * @arg TIM_ICPOLARITY_BOTHEDGE
8120 * @param TIM_ICSelection specifies the input to be used.
8121 * This parameter can be one of the following values:
8122 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
8123 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
8124 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
8125 * @param TIM_ICFilter Specifies the Input Capture Filter.
8126 * This parameter must be a value between 0x00 and 0x0F.
8127 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
8128 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8129 * protected against un-initialized filter and polarity values.
8130 * @retval None
8131 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8132 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8133 uint32_t TIM_ICFilter)
8134 {
8135 uint32_t tmpccmr2;
8136 uint32_t tmpccer;
8137
8138 /* Disable the Channel 4: Reset the CC4E Bit */
8139 tmpccer = TIMx->CCER;
8140 TIMx->CCER &= ~TIM_CCER_CC4E;
8141 tmpccmr2 = TIMx->CCMR2;
8142
8143 /* Select the Input */
8144 tmpccmr2 &= ~TIM_CCMR2_CC4S;
8145 tmpccmr2 |= (TIM_ICSelection << 8U);
8146
8147 /* Set the filter */
8148 tmpccmr2 &= ~TIM_CCMR2_IC4F;
8149 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
8150
8151 /* Select the Polarity and set the CC4E Bit */
8152 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
8153 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
8154
8155 /* Write to TIMx CCMR2 and CCER registers */
8156 TIMx->CCMR2 = tmpccmr2;
8157 TIMx->CCER = tmpccer ;
8158 }
8159
8160 /**
8161 * @brief Selects the Input Trigger source
8162 * @param TIMx to select the TIM peripheral
8163 * @param InputTriggerSource The Input Trigger source.
8164 * This parameter can be one of the following values:
8165 * @arg TIM_TS_ITR0: Internal Trigger 0
8166 * @arg TIM_TS_ITR1: Internal Trigger 1
8167 * @arg TIM_TS_ITR2: Internal Trigger 2
8168 * @arg TIM_TS_ITR3: Internal Trigger 3
8169 * @arg TIM_TS_ITR4: Internal Trigger 4
8170 * @arg TIM_TS_ITR5: Internal Trigger 5
8171 * @arg TIM_TS_ITR6: Internal Trigger 6
8172 * @arg TIM_TS_ITR7: Internal Trigger 7
8173 * @arg TIM_TS_ITR8: Internal Trigger 8
8174 * @arg TIM_TS_ITR9: Internal Trigger 9
8175 * @arg TIM_TS_ITR10: Internal Trigger 10
8176 * @arg TIM_TS_ITR11: Internal Trigger 11
8177 * @arg TIM_TS_ITR12: Internal Trigger 12
8178 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
8179 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
8180 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
8181 * @arg TIM_TS_ETRF: External Trigger input
8182 * @retval None
8183 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)8184 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
8185 {
8186 uint32_t tmpsmcr;
8187
8188 /* Get the TIMx SMCR register value */
8189 tmpsmcr = TIMx->SMCR;
8190 /* Reset the TS Bits */
8191 tmpsmcr &= ~TIM_SMCR_TS;
8192 /* Set the Input Trigger source and the slave mode*/
8193 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8194 /* Write to TIMx SMCR */
8195 TIMx->SMCR = tmpsmcr;
8196 }
8197 /**
8198 * @brief Configures the TIMx External Trigger (ETR).
8199 * @param TIMx to select the TIM peripheral
8200 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
8201 * This parameter can be one of the following values:
8202 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
8203 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
8204 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
8205 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
8206 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
8207 * This parameter can be one of the following values:
8208 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
8209 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
8210 * @param ExtTRGFilter External Trigger Filter.
8211 * This parameter must be a value between 0x00 and 0x0F
8212 * @retval None
8213 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)8214 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
8215 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
8216 {
8217 uint32_t tmpsmcr;
8218
8219 tmpsmcr = TIMx->SMCR;
8220
8221 /* Reset the ETR Bits */
8222 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8223
8224 /* Set the Prescaler, the Filter value and the Polarity */
8225 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8226
8227 /* Write to TIMx SMCR */
8228 TIMx->SMCR = tmpsmcr;
8229 }
8230
8231 /**
8232 * @brief Enables or disables the TIM Capture Compare Channel x.
8233 * @param TIMx to select the TIM peripheral
8234 * @param Channel specifies the TIM Channel
8235 * This parameter can be one of the following values:
8236 * @arg TIM_CHANNEL_1: TIM Channel 1
8237 * @arg TIM_CHANNEL_2: TIM Channel 2
8238 * @arg TIM_CHANNEL_3: TIM Channel 3
8239 * @arg TIM_CHANNEL_4: TIM Channel 4
8240 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
8241 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
8242 * @param ChannelState specifies the TIM Channel CCxE bit new state.
8243 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
8244 * @retval None
8245 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)8246 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
8247 {
8248 uint32_t tmp;
8249
8250 /* Check the parameters */
8251 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
8252 assert_param(IS_TIM_CHANNELS(Channel));
8253
8254 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8255
8256 /* Reset the CCxE Bit */
8257 TIMx->CCER &= ~tmp;
8258
8259 /* Set or reset the CCxE Bit */
8260 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8261 }
8262
8263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
8264 /**
8265 * @brief Reset interrupt callbacks to the legacy weak callbacks.
8266 * @param htim pointer to a TIM_HandleTypeDef structure that contains
8267 * the configuration information for TIM module.
8268 * @retval None
8269 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)8270 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
8271 {
8272 /* Reset the TIM callback to the legacy weak callbacks */
8273 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
8274 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
8275 htim->TriggerCallback = HAL_TIM_TriggerCallback;
8276 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
8277 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
8278 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
8279 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
8280 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
8281 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
8282 htim->ErrorCallback = HAL_TIM_ErrorCallback;
8283 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
8284 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
8285 htim->BreakCallback = HAL_TIMEx_BreakCallback;
8286 htim->Break2Callback = HAL_TIMEx_Break2Callback;
8287 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
8288 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
8289 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
8290 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
8291 }
8292 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
8293
8294 /**
8295 * @}
8296 */
8297
8298 #endif /* HAL_TIM_MODULE_ENABLED */
8299 /**
8300 * @}
8301 */
8302
8303 /**
8304 * @}
8305 */
8306
