1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2021 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
88 to use the Timer to generate an Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157 (+) EncoderIndexCallback : TIM Encoder Index Callback.
158 (+) DirectionChangeCallback : TIM Direction Change Callback
159 (+) IndexErrorCallback : TIM Index Error Callback.
160 (+) TransitionErrorCallback : TIM Transition Error Callback
161
162 [..]
163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
164 all interrupt callbacks are set to the corresponding weak functions:
165 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
166
167 [..]
168 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
169 functionalities in the Init / DeInit only when these callbacks are null
170 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
171 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
172
173 [..]
174 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
175 Exception done MspInit / MspDeInit that can be registered / unregistered
176 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
177 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
178 In that case first register the MspInit/MspDeInit user callbacks
179 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
180
181 [..]
182 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
183 not defined, the callback registration feature is not available and all callbacks
184 are set to the corresponding weak functions.
185
186 @endverbatim
187 ******************************************************************************
188 */
189
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32u5xx_hal.h"
192
193 /** @addtogroup STM32U5xx_HAL_Driver
194 * @{
195 */
196
197 /** @defgroup TIM TIM
198 * @brief TIM HAL module driver
199 * @{
200 */
201
202 #ifdef HAL_TIM_MODULE_ENABLED
203
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 /** @addtogroup TIM_Private_Constants
207 * @{
208 */
209 #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
210
211 /**
212 * @}
213 */
214 /* Private macros ------------------------------------------------------------*/
215 /* Private variables ---------------------------------------------------------*/
216 /* Private function prototypes -----------------------------------------------*/
217 /** @addtogroup TIM_Private_Functions
218 * @{
219 */
220 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
222 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
223 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
224 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
225 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
226 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
227 uint32_t TIM_ICFilter);
228 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
229 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
230 uint32_t TIM_ICFilter);
231 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
232 uint32_t TIM_ICFilter);
233 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
234 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
235 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
236 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
237 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
238 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
240 const TIM_SlaveConfigTypeDef *sSlaveConfig);
241 /**
242 * @}
243 */
244 /* Exported functions --------------------------------------------------------*/
245
246 /** @defgroup TIM_Exported_Functions TIM Exported Functions
247 * @{
248 */
249
250 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
251 * @brief Time Base functions
252 *
253 @verbatim
254 ==============================================================================
255 ##### Time Base functions #####
256 ==============================================================================
257 [..]
258 This section provides functions allowing to:
259 (+) Initialize and configure the TIM base.
260 (+) De-initialize the TIM base.
261 (+) Start the Time Base.
262 (+) Stop the Time Base.
263 (+) Start the Time Base and enable interrupt.
264 (+) Stop the Time Base and disable interrupt.
265 (+) Start the Time Base and enable DMA transfer.
266 (+) Stop the Time Base and disable DMA transfer.
267
268 @endverbatim
269 * @{
270 */
271 /**
272 * @brief Initializes the TIM Time base Unit according to the specified
273 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
274 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
275 * requires a timer reset to avoid unexpected direction
276 * due to DIR bit readonly in center aligned mode.
277 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
278 * @param htim TIM Base handle
279 * @retval HAL status
280 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
282 {
283 /* Check the TIM handle allocation */
284 if (htim == NULL)
285 {
286 return HAL_ERROR;
287 }
288
289 /* Check the parameters */
290 assert_param(IS_TIM_INSTANCE(htim->Instance));
291 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
292 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
293 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
294 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
295
296 if (htim->State == HAL_TIM_STATE_RESET)
297 {
298 /* Allocate lock resource and initialize it */
299 htim->Lock = HAL_UNLOCKED;
300
301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
302 /* Reset interrupt callbacks to legacy weak callbacks */
303 TIM_ResetCallback(htim);
304
305 if (htim->Base_MspInitCallback == NULL)
306 {
307 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
308 }
309 /* Init the low level hardware : GPIO, CLOCK, NVIC */
310 htim->Base_MspInitCallback(htim);
311 #else
312 /* Init the low level hardware : GPIO, CLOCK, NVIC */
313 HAL_TIM_Base_MspInit(htim);
314 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
315 }
316
317 /* Set the TIM state */
318 htim->State = HAL_TIM_STATE_BUSY;
319
320 /* Set the Time Base configuration */
321 TIM_Base_SetConfig(htim->Instance, &htim->Init);
322
323 /* Initialize the DMA burst operation state */
324 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
325
326 /* Initialize the TIM channels state */
327 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
328 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
329
330 /* Initialize the TIM state*/
331 htim->State = HAL_TIM_STATE_READY;
332
333 return HAL_OK;
334 }
335
336 /**
337 * @brief DeInitializes the TIM Base peripheral
338 * @param htim TIM Base handle
339 * @retval HAL status
340 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)341 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
342 {
343 /* Check the parameters */
344 assert_param(IS_TIM_INSTANCE(htim->Instance));
345
346 htim->State = HAL_TIM_STATE_BUSY;
347
348 /* Disable the TIM Peripheral Clock */
349 __HAL_TIM_DISABLE(htim);
350
351 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
352 if (htim->Base_MspDeInitCallback == NULL)
353 {
354 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
355 }
356 /* DeInit the low level hardware */
357 htim->Base_MspDeInitCallback(htim);
358 #else
359 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
360 HAL_TIM_Base_MspDeInit(htim);
361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
362
363 /* Change the DMA burst operation state */
364 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
365
366 /* Change the TIM channels state */
367 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
368 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
369
370 /* Change TIM state */
371 htim->State = HAL_TIM_STATE_RESET;
372
373 /* Release Lock */
374 __HAL_UNLOCK(htim);
375
376 return HAL_OK;
377 }
378
379 /**
380 * @brief Initializes the TIM Base MSP.
381 * @param htim TIM Base handle
382 * @retval None
383 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)384 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
385 {
386 /* Prevent unused argument(s) compilation warning */
387 UNUSED(htim);
388
389 /* NOTE : This function should not be modified, when the callback is needed,
390 the HAL_TIM_Base_MspInit could be implemented in the user file
391 */
392 }
393
394 /**
395 * @brief DeInitializes TIM Base MSP.
396 * @param htim TIM Base handle
397 * @retval None
398 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)399 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
400 {
401 /* Prevent unused argument(s) compilation warning */
402 UNUSED(htim);
403
404 /* NOTE : This function should not be modified, when the callback is needed,
405 the HAL_TIM_Base_MspDeInit could be implemented in the user file
406 */
407 }
408
409
410 /**
411 * @brief Starts the TIM Base generation.
412 * @param htim TIM Base handle
413 * @retval HAL status
414 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)415 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
416 {
417 uint32_t tmpsmcr;
418
419 /* Check the parameters */
420 assert_param(IS_TIM_INSTANCE(htim->Instance));
421
422 /* Check the TIM state */
423 if (htim->State != HAL_TIM_STATE_READY)
424 {
425 return HAL_ERROR;
426 }
427
428 /* Set the TIM state */
429 htim->State = HAL_TIM_STATE_BUSY;
430
431 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
432 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
433 {
434 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
435 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
436 {
437 __HAL_TIM_ENABLE(htim);
438 }
439 }
440 else
441 {
442 __HAL_TIM_ENABLE(htim);
443 }
444
445 /* Return function status */
446 return HAL_OK;
447 }
448
449 /**
450 * @brief Stops the TIM Base generation.
451 * @param htim TIM Base handle
452 * @retval HAL status
453 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)454 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
455 {
456 /* Check the parameters */
457 assert_param(IS_TIM_INSTANCE(htim->Instance));
458
459 /* Disable the Peripheral */
460 __HAL_TIM_DISABLE(htim);
461
462 /* Set the TIM state */
463 htim->State = HAL_TIM_STATE_READY;
464
465 /* Return function status */
466 return HAL_OK;
467 }
468
469 /**
470 * @brief Starts the TIM Base generation in interrupt mode.
471 * @param htim TIM Base handle
472 * @retval HAL status
473 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
475 {
476 uint32_t tmpsmcr;
477
478 /* Check the parameters */
479 assert_param(IS_TIM_INSTANCE(htim->Instance));
480
481 /* Check the TIM state */
482 if (htim->State != HAL_TIM_STATE_READY)
483 {
484 return HAL_ERROR;
485 }
486
487 /* Set the TIM state */
488 htim->State = HAL_TIM_STATE_BUSY;
489
490 /* Enable the TIM Update interrupt */
491 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
492
493 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
494 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
495 {
496 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
497 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
498 {
499 __HAL_TIM_ENABLE(htim);
500 }
501 }
502 else
503 {
504 __HAL_TIM_ENABLE(htim);
505 }
506
507 /* Return function status */
508 return HAL_OK;
509 }
510
511 /**
512 * @brief Stops the TIM Base generation in interrupt mode.
513 * @param htim TIM Base handle
514 * @retval HAL status
515 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)516 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
517 {
518 /* Check the parameters */
519 assert_param(IS_TIM_INSTANCE(htim->Instance));
520
521 /* Disable the TIM Update interrupt */
522 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
523
524 /* Disable the Peripheral */
525 __HAL_TIM_DISABLE(htim);
526
527 /* Set the TIM state */
528 htim->State = HAL_TIM_STATE_READY;
529
530 /* Return function status */
531 return HAL_OK;
532 }
533
534 /**
535 * @brief Starts the TIM Base generation in DMA mode.
536 * @param htim TIM Base handle
537 * @param pData The source Buffer address.
538 * @param Length The length of data to be transferred from memory to peripheral.
539 * @retval HAL status
540 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
542 {
543 uint32_t tmpsmcr;
544
545 /* Check the parameters */
546 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
547
548 /* Set the TIM state */
549 if (htim->State == HAL_TIM_STATE_BUSY)
550 {
551 return HAL_BUSY;
552 }
553 else if (htim->State == HAL_TIM_STATE_READY)
554 {
555 if ((pData == NULL) || (Length == 0U))
556 {
557 return HAL_ERROR;
558 }
559 else
560 {
561 htim->State = HAL_TIM_STATE_BUSY;
562 }
563 }
564 else
565 {
566 return HAL_ERROR;
567 }
568
569 /* Set the DMA Period elapsed callbacks */
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
571 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
572
573 /* Set the DMA error callback */
574 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
575
576 /* Enable the DMA channel */
577 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
578 Length) != HAL_OK)
579 {
580 /* Return error status */
581 return HAL_ERROR;
582 }
583
584 /* Enable the TIM Update DMA request */
585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
586
587 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
588 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
589 {
590 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
591 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
592 {
593 __HAL_TIM_ENABLE(htim);
594 }
595 }
596 else
597 {
598 __HAL_TIM_ENABLE(htim);
599 }
600
601 /* Return function status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Stops the TIM Base generation in DMA mode.
607 * @param htim TIM Base handle
608 * @retval HAL status
609 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
611 {
612 /* Check the parameters */
613 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
614
615 /* Disable the TIM Update DMA request */
616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
617
618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
619
620 /* Disable the Peripheral */
621 __HAL_TIM_DISABLE(htim);
622
623 /* Set the TIM state */
624 htim->State = HAL_TIM_STATE_READY;
625
626 /* Return function status */
627 return HAL_OK;
628 }
629
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
635 * @brief TIM Output Compare functions
636 *
637 @verbatim
638 ==============================================================================
639 ##### TIM Output Compare functions #####
640 ==============================================================================
641 [..]
642 This section provides functions allowing to:
643 (+) Initialize and configure the TIM Output Compare.
644 (+) De-initialize the TIM Output Compare.
645 (+) Start the TIM Output Compare.
646 (+) Stop the TIM Output Compare.
647 (+) Start the TIM Output Compare and enable interrupt.
648 (+) Stop the TIM Output Compare and disable interrupt.
649 (+) Start the TIM Output Compare and enable DMA transfer.
650 (+) Stop the TIM Output Compare and disable DMA transfer.
651
652 @endverbatim
653 * @{
654 */
655 /**
656 * @brief Initializes the TIM Output Compare according to the specified
657 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
658 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
659 * requires a timer reset to avoid unexpected direction
660 * due to DIR bit readonly in center aligned mode.
661 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
662 * @param htim TIM Output Compare handle
663 * @retval HAL status
664 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)665 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
666 {
667 /* Check the TIM handle allocation */
668 if (htim == NULL)
669 {
670 return HAL_ERROR;
671 }
672
673 /* Check the parameters */
674 assert_param(IS_TIM_INSTANCE(htim->Instance));
675 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
676 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
677 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
678 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
679
680 if (htim->State == HAL_TIM_STATE_RESET)
681 {
682 /* Allocate lock resource and initialize it */
683 htim->Lock = HAL_UNLOCKED;
684
685 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
686 /* Reset interrupt callbacks to legacy weak callbacks */
687 TIM_ResetCallback(htim);
688
689 if (htim->OC_MspInitCallback == NULL)
690 {
691 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
692 }
693 /* Init the low level hardware : GPIO, CLOCK, NVIC */
694 htim->OC_MspInitCallback(htim);
695 #else
696 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
697 HAL_TIM_OC_MspInit(htim);
698 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
699 }
700
701 /* Set the TIM state */
702 htim->State = HAL_TIM_STATE_BUSY;
703
704 /* Init the base time for the Output Compare */
705 TIM_Base_SetConfig(htim->Instance, &htim->Init);
706
707 /* Initialize the DMA burst operation state */
708 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
709
710 /* Initialize the TIM channels state */
711 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
712 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
713
714 /* Initialize the TIM state*/
715 htim->State = HAL_TIM_STATE_READY;
716
717 return HAL_OK;
718 }
719
720 /**
721 * @brief DeInitializes the TIM peripheral
722 * @param htim TIM Output Compare handle
723 * @retval HAL status
724 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)725 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
726 {
727 /* Check the parameters */
728 assert_param(IS_TIM_INSTANCE(htim->Instance));
729
730 htim->State = HAL_TIM_STATE_BUSY;
731
732 /* Disable the TIM Peripheral Clock */
733 __HAL_TIM_DISABLE(htim);
734
735 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
736 if (htim->OC_MspDeInitCallback == NULL)
737 {
738 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
739 }
740 /* DeInit the low level hardware */
741 htim->OC_MspDeInitCallback(htim);
742 #else
743 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
744 HAL_TIM_OC_MspDeInit(htim);
745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
746
747 /* Change the DMA burst operation state */
748 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
749
750 /* Change the TIM channels state */
751 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
752 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
753
754 /* Change TIM state */
755 htim->State = HAL_TIM_STATE_RESET;
756
757 /* Release Lock */
758 __HAL_UNLOCK(htim);
759
760 return HAL_OK;
761 }
762
763 /**
764 * @brief Initializes the TIM Output Compare MSP.
765 * @param htim TIM Output Compare handle
766 * @retval None
767 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)768 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
769 {
770 /* Prevent unused argument(s) compilation warning */
771 UNUSED(htim);
772
773 /* NOTE : This function should not be modified, when the callback is needed,
774 the HAL_TIM_OC_MspInit could be implemented in the user file
775 */
776 }
777
778 /**
779 * @brief DeInitializes TIM Output Compare MSP.
780 * @param htim TIM Output Compare handle
781 * @retval None
782 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)783 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
784 {
785 /* Prevent unused argument(s) compilation warning */
786 UNUSED(htim);
787
788 /* NOTE : This function should not be modified, when the callback is needed,
789 the HAL_TIM_OC_MspDeInit could be implemented in the user file
790 */
791 }
792
793 /**
794 * @brief Starts the TIM Output Compare signal generation.
795 * @param htim TIM Output Compare handle
796 * @param Channel TIM Channel to be enabled
797 * This parameter can be one of the following values:
798 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
799 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
800 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
801 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
802 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
803 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
804 * @retval HAL status
805 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)806 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
807 {
808 uint32_t tmpsmcr;
809
810 /* Check the parameters */
811 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
812
813 /* Check the TIM channel state */
814 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
815 {
816 return HAL_ERROR;
817 }
818
819 /* Set the TIM channel state */
820 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
821
822 /* Enable the Output compare channel */
823 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
824
825 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
826 {
827 /* Enable the main output */
828 __HAL_TIM_MOE_ENABLE(htim);
829 }
830
831 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
832 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
833 {
834 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
835 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
836 {
837 __HAL_TIM_ENABLE(htim);
838 }
839 }
840 else
841 {
842 __HAL_TIM_ENABLE(htim);
843 }
844
845 /* Return function status */
846 return HAL_OK;
847 }
848
849 /**
850 * @brief Stops the TIM Output Compare signal generation.
851 * @param htim TIM Output Compare handle
852 * @param Channel TIM Channel to be disabled
853 * This parameter can be one of the following values:
854 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
855 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
856 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
857 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
858 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
859 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
860 * @retval HAL status
861 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)862 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
863 {
864 /* Check the parameters */
865 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
866
867 /* Disable the Output compare channel */
868 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
869
870 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
871 {
872 /* Disable the Main Output */
873 __HAL_TIM_MOE_DISABLE(htim);
874 }
875
876 /* Disable the Peripheral */
877 __HAL_TIM_DISABLE(htim);
878
879 /* Set the TIM channel state */
880 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
881
882 /* Return function status */
883 return HAL_OK;
884 }
885
886 /**
887 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
888 * @param htim TIM Output Compare handle
889 * @param Channel TIM Channel to be enabled
890 * This parameter can be one of the following values:
891 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
892 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
893 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
894 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
895 * @retval HAL status
896 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)897 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
898 {
899 HAL_StatusTypeDef status = HAL_OK;
900 uint32_t tmpsmcr;
901
902 /* Check the parameters */
903 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
904
905 /* Check the TIM channel state */
906 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
907 {
908 return HAL_ERROR;
909 }
910
911 /* Set the TIM channel state */
912 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
913
914 switch (Channel)
915 {
916 case TIM_CHANNEL_1:
917 {
918 /* Enable the TIM Capture/Compare 1 interrupt */
919 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
920 break;
921 }
922
923 case TIM_CHANNEL_2:
924 {
925 /* Enable the TIM Capture/Compare 2 interrupt */
926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
927 break;
928 }
929
930 case TIM_CHANNEL_3:
931 {
932 /* Enable the TIM Capture/Compare 3 interrupt */
933 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
934 break;
935 }
936
937 case TIM_CHANNEL_4:
938 {
939 /* Enable the TIM Capture/Compare 4 interrupt */
940 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
941 break;
942 }
943
944 default:
945 status = HAL_ERROR;
946 break;
947 }
948
949 if (status == HAL_OK)
950 {
951 /* Enable the Output compare channel */
952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
953
954 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
955 {
956 /* Enable the main output */
957 __HAL_TIM_MOE_ENABLE(htim);
958 }
959
960 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
961 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
962 {
963 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
964 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
965 {
966 __HAL_TIM_ENABLE(htim);
967 }
968 }
969 else
970 {
971 __HAL_TIM_ENABLE(htim);
972 }
973 }
974
975 /* Return function status */
976 return status;
977 }
978
979 /**
980 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
981 * @param htim TIM Output Compare handle
982 * @param Channel TIM Channel to be disabled
983 * This parameter can be one of the following values:
984 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
985 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
986 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
987 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
988 * @retval HAL status
989 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)990 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
991 {
992 HAL_StatusTypeDef status = HAL_OK;
993
994 /* Check the parameters */
995 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
996
997 switch (Channel)
998 {
999 case TIM_CHANNEL_1:
1000 {
1001 /* Disable the TIM Capture/Compare 1 interrupt */
1002 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1003 break;
1004 }
1005
1006 case TIM_CHANNEL_2:
1007 {
1008 /* Disable the TIM Capture/Compare 2 interrupt */
1009 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1010 break;
1011 }
1012
1013 case TIM_CHANNEL_3:
1014 {
1015 /* Disable the TIM Capture/Compare 3 interrupt */
1016 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1017 break;
1018 }
1019
1020 case TIM_CHANNEL_4:
1021 {
1022 /* Disable the TIM Capture/Compare 4 interrupt */
1023 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1024 break;
1025 }
1026
1027 default:
1028 status = HAL_ERROR;
1029 break;
1030 }
1031
1032 if (status == HAL_OK)
1033 {
1034 /* Disable the Output compare channel */
1035 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1036
1037 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1038 {
1039 /* Disable the Main Output */
1040 __HAL_TIM_MOE_DISABLE(htim);
1041 }
1042
1043 /* Disable the Peripheral */
1044 __HAL_TIM_DISABLE(htim);
1045
1046 /* Set the TIM channel state */
1047 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1048 }
1049
1050 /* Return function status */
1051 return status;
1052 }
1053
1054 /**
1055 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1056 * @param htim TIM Output Compare handle
1057 * @param Channel TIM Channel to be enabled
1058 * This parameter can be one of the following values:
1059 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1060 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1061 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1062 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1063 * @param pData The source Buffer address.
1064 * @param Length The length of data to be transferred from memory to TIM peripheral
1065 * @retval HAL status
1066 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1067 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1068 uint16_t Length)
1069 {
1070 HAL_StatusTypeDef status = HAL_OK;
1071 uint32_t tmpsmcr;
1072
1073 /* Check the parameters */
1074 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1075
1076 /* Set the TIM channel state */
1077 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1078 {
1079 return HAL_BUSY;
1080 }
1081 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1082 {
1083 if ((pData == NULL) || (Length == 0U))
1084 {
1085 return HAL_ERROR;
1086 }
1087 else
1088 {
1089 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1090 }
1091 }
1092 else
1093 {
1094 return HAL_ERROR;
1095 }
1096
1097 switch (Channel)
1098 {
1099 case TIM_CHANNEL_1:
1100 {
1101 /* Set the DMA compare callbacks */
1102 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1103 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1104
1105 /* Set the DMA error callback */
1106 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1107
1108 /* Enable the DMA channel */
1109 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1110 Length) != HAL_OK)
1111 {
1112 /* Return error status */
1113 return HAL_ERROR;
1114 }
1115
1116 /* Enable the TIM Capture/Compare 1 DMA request */
1117 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1118 break;
1119 }
1120
1121 case TIM_CHANNEL_2:
1122 {
1123 /* Set the DMA compare callbacks */
1124 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1125 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1126
1127 /* Set the DMA error callback */
1128 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1129
1130 /* Enable the DMA channel */
1131 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1132 Length) != HAL_OK)
1133 {
1134 /* Return error status */
1135 return HAL_ERROR;
1136 }
1137
1138 /* Enable the TIM Capture/Compare 2 DMA request */
1139 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1140 break;
1141 }
1142
1143 case TIM_CHANNEL_3:
1144 {
1145 /* Set the DMA compare callbacks */
1146 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1147 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1148
1149 /* Set the DMA error callback */
1150 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1151
1152 /* Enable the DMA channel */
1153 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1154 Length) != HAL_OK)
1155 {
1156 /* Return error status */
1157 return HAL_ERROR;
1158 }
1159 /* Enable the TIM Capture/Compare 3 DMA request */
1160 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1161 break;
1162 }
1163
1164 case TIM_CHANNEL_4:
1165 {
1166 /* Set the DMA compare callbacks */
1167 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1168 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1169
1170 /* Set the DMA error callback */
1171 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1172
1173 /* Enable the DMA channel */
1174 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1175 Length) != HAL_OK)
1176 {
1177 /* Return error status */
1178 return HAL_ERROR;
1179 }
1180 /* Enable the TIM Capture/Compare 4 DMA request */
1181 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1182 break;
1183 }
1184
1185 default:
1186 status = HAL_ERROR;
1187 break;
1188 }
1189
1190 if (status == HAL_OK)
1191 {
1192 /* Enable the Output compare channel */
1193 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1194
1195 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1196 {
1197 /* Enable the main output */
1198 __HAL_TIM_MOE_ENABLE(htim);
1199 }
1200
1201 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1202 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1203 {
1204 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1205 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1206 {
1207 __HAL_TIM_ENABLE(htim);
1208 }
1209 }
1210 else
1211 {
1212 __HAL_TIM_ENABLE(htim);
1213 }
1214 }
1215
1216 /* Return function status */
1217 return status;
1218 }
1219
1220 /**
1221 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1222 * @param htim TIM Output Compare handle
1223 * @param Channel TIM Channel to be disabled
1224 * This parameter can be one of the following values:
1225 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1226 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1227 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1228 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1229 * @retval HAL status
1230 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1231 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1232 {
1233 HAL_StatusTypeDef status = HAL_OK;
1234
1235 /* Check the parameters */
1236 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1237
1238 switch (Channel)
1239 {
1240 case TIM_CHANNEL_1:
1241 {
1242 /* Disable the TIM Capture/Compare 1 DMA request */
1243 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1244 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1245 break;
1246 }
1247
1248 case TIM_CHANNEL_2:
1249 {
1250 /* Disable the TIM Capture/Compare 2 DMA request */
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1253 break;
1254 }
1255
1256 case TIM_CHANNEL_3:
1257 {
1258 /* Disable the TIM Capture/Compare 3 DMA request */
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1261 break;
1262 }
1263
1264 case TIM_CHANNEL_4:
1265 {
1266 /* Disable the TIM Capture/Compare 4 interrupt */
1267 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1268 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1269 break;
1270 }
1271
1272 default:
1273 status = HAL_ERROR;
1274 break;
1275 }
1276
1277 if (status == HAL_OK)
1278 {
1279 /* Disable the Output compare channel */
1280 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1281
1282 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1283 {
1284 /* Disable the Main Output */
1285 __HAL_TIM_MOE_DISABLE(htim);
1286 }
1287
1288 /* Disable the Peripheral */
1289 __HAL_TIM_DISABLE(htim);
1290
1291 /* Set the TIM channel state */
1292 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1293 }
1294
1295 /* Return function status */
1296 return status;
1297 }
1298
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1304 * @brief TIM PWM functions
1305 *
1306 @verbatim
1307 ==============================================================================
1308 ##### TIM PWM functions #####
1309 ==============================================================================
1310 [..]
1311 This section provides functions allowing to:
1312 (+) Initialize and configure the TIM PWM.
1313 (+) De-initialize the TIM PWM.
1314 (+) Start the TIM PWM.
1315 (+) Stop the TIM PWM.
1316 (+) Start the TIM PWM and enable interrupt.
1317 (+) Stop the TIM PWM and disable interrupt.
1318 (+) Start the TIM PWM and enable DMA transfer.
1319 (+) Stop the TIM PWM and disable DMA transfer.
1320
1321 @endverbatim
1322 * @{
1323 */
1324 /**
1325 * @brief Initializes the TIM PWM Time Base according to the specified
1326 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1327 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1328 * requires a timer reset to avoid unexpected direction
1329 * due to DIR bit readonly in center aligned mode.
1330 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1331 * @param htim TIM PWM handle
1332 * @retval HAL status
1333 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1334 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1335 {
1336 /* Check the TIM handle allocation */
1337 if (htim == NULL)
1338 {
1339 return HAL_ERROR;
1340 }
1341
1342 /* Check the parameters */
1343 assert_param(IS_TIM_INSTANCE(htim->Instance));
1344 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1345 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1346 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1347 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1348
1349 if (htim->State == HAL_TIM_STATE_RESET)
1350 {
1351 /* Allocate lock resource and initialize it */
1352 htim->Lock = HAL_UNLOCKED;
1353
1354 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1355 /* Reset interrupt callbacks to legacy weak callbacks */
1356 TIM_ResetCallback(htim);
1357
1358 if (htim->PWM_MspInitCallback == NULL)
1359 {
1360 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1361 }
1362 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1363 htim->PWM_MspInitCallback(htim);
1364 #else
1365 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1366 HAL_TIM_PWM_MspInit(htim);
1367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1368 }
1369
1370 /* Set the TIM state */
1371 htim->State = HAL_TIM_STATE_BUSY;
1372
1373 /* Init the base time for the PWM */
1374 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1375
1376 /* Initialize the DMA burst operation state */
1377 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1378
1379 /* Initialize the TIM channels state */
1380 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1381 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1382
1383 /* Initialize the TIM state*/
1384 htim->State = HAL_TIM_STATE_READY;
1385
1386 return HAL_OK;
1387 }
1388
1389 /**
1390 * @brief DeInitializes the TIM peripheral
1391 * @param htim TIM PWM handle
1392 * @retval HAL status
1393 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1394 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1395 {
1396 /* Check the parameters */
1397 assert_param(IS_TIM_INSTANCE(htim->Instance));
1398
1399 htim->State = HAL_TIM_STATE_BUSY;
1400
1401 /* Disable the TIM Peripheral Clock */
1402 __HAL_TIM_DISABLE(htim);
1403
1404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1405 if (htim->PWM_MspDeInitCallback == NULL)
1406 {
1407 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1408 }
1409 /* DeInit the low level hardware */
1410 htim->PWM_MspDeInitCallback(htim);
1411 #else
1412 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1413 HAL_TIM_PWM_MspDeInit(htim);
1414 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1415
1416 /* Change the DMA burst operation state */
1417 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1418
1419 /* Change the TIM channels state */
1420 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1421 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1422
1423 /* Change TIM state */
1424 htim->State = HAL_TIM_STATE_RESET;
1425
1426 /* Release Lock */
1427 __HAL_UNLOCK(htim);
1428
1429 return HAL_OK;
1430 }
1431
1432 /**
1433 * @brief Initializes the TIM PWM MSP.
1434 * @param htim TIM PWM handle
1435 * @retval None
1436 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1437 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1438 {
1439 /* Prevent unused argument(s) compilation warning */
1440 UNUSED(htim);
1441
1442 /* NOTE : This function should not be modified, when the callback is needed,
1443 the HAL_TIM_PWM_MspInit could be implemented in the user file
1444 */
1445 }
1446
1447 /**
1448 * @brief DeInitializes TIM PWM MSP.
1449 * @param htim TIM PWM handle
1450 * @retval None
1451 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1452 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1453 {
1454 /* Prevent unused argument(s) compilation warning */
1455 UNUSED(htim);
1456
1457 /* NOTE : This function should not be modified, when the callback is needed,
1458 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1459 */
1460 }
1461
1462 /**
1463 * @brief Starts the PWM signal generation.
1464 * @param htim TIM handle
1465 * @param Channel TIM Channels to be enabled
1466 * This parameter can be one of the following values:
1467 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1468 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1469 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1470 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1471 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1472 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1473 * @retval HAL status
1474 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1475 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1476 {
1477 uint32_t tmpsmcr;
1478
1479 /* Check the parameters */
1480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1481
1482 /* Check the TIM channel state */
1483 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1484 {
1485 return HAL_ERROR;
1486 }
1487
1488 /* Set the TIM channel state */
1489 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1490
1491 /* Enable the Capture compare channel */
1492 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1493
1494 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1495 {
1496 /* Enable the main output */
1497 __HAL_TIM_MOE_ENABLE(htim);
1498 }
1499
1500 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1501 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1502 {
1503 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1504 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1505 {
1506 __HAL_TIM_ENABLE(htim);
1507 }
1508 }
1509 else
1510 {
1511 __HAL_TIM_ENABLE(htim);
1512 }
1513
1514 /* Return function status */
1515 return HAL_OK;
1516 }
1517
1518 /**
1519 * @brief Stops the PWM signal generation.
1520 * @param htim TIM PWM handle
1521 * @param Channel TIM Channels to be disabled
1522 * This parameter can be one of the following values:
1523 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1524 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1525 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1526 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1527 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1528 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1529 * @retval HAL status
1530 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1531 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1532 {
1533 /* Check the parameters */
1534 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1535
1536 /* Disable the Capture compare channel */
1537 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1538
1539 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1540 {
1541 /* Disable the Main Output */
1542 __HAL_TIM_MOE_DISABLE(htim);
1543 }
1544
1545 /* Disable the Peripheral */
1546 __HAL_TIM_DISABLE(htim);
1547
1548 /* Set the TIM channel state */
1549 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1550
1551 /* Return function status */
1552 return HAL_OK;
1553 }
1554
1555 /**
1556 * @brief Starts the PWM signal generation in interrupt mode.
1557 * @param htim TIM PWM handle
1558 * @param Channel TIM Channel to be enabled
1559 * This parameter can be one of the following values:
1560 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1561 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1562 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1563 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1564 * @retval HAL status
1565 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1566 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1567 {
1568 HAL_StatusTypeDef status = HAL_OK;
1569 uint32_t tmpsmcr;
1570
1571 /* Check the parameters */
1572 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1573
1574 /* Check the TIM channel state */
1575 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1576 {
1577 return HAL_ERROR;
1578 }
1579
1580 /* Set the TIM channel state */
1581 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1582
1583 switch (Channel)
1584 {
1585 case TIM_CHANNEL_1:
1586 {
1587 /* Enable the TIM Capture/Compare 1 interrupt */
1588 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1589 break;
1590 }
1591
1592 case TIM_CHANNEL_2:
1593 {
1594 /* Enable the TIM Capture/Compare 2 interrupt */
1595 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1596 break;
1597 }
1598
1599 case TIM_CHANNEL_3:
1600 {
1601 /* Enable the TIM Capture/Compare 3 interrupt */
1602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1603 break;
1604 }
1605
1606 case TIM_CHANNEL_4:
1607 {
1608 /* Enable the TIM Capture/Compare 4 interrupt */
1609 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1610 break;
1611 }
1612
1613 default:
1614 status = HAL_ERROR;
1615 break;
1616 }
1617
1618 if (status == HAL_OK)
1619 {
1620 /* Enable the Capture compare channel */
1621 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1622
1623 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1624 {
1625 /* Enable the main output */
1626 __HAL_TIM_MOE_ENABLE(htim);
1627 }
1628
1629 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1630 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1631 {
1632 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1633 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1634 {
1635 __HAL_TIM_ENABLE(htim);
1636 }
1637 }
1638 else
1639 {
1640 __HAL_TIM_ENABLE(htim);
1641 }
1642 }
1643
1644 /* Return function status */
1645 return status;
1646 }
1647
1648 /**
1649 * @brief Stops the PWM signal generation in interrupt mode.
1650 * @param htim TIM PWM handle
1651 * @param Channel TIM Channels to be disabled
1652 * This parameter can be one of the following values:
1653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1655 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1656 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1657 * @retval HAL status
1658 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1659 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1660 {
1661 HAL_StatusTypeDef status = HAL_OK;
1662
1663 /* Check the parameters */
1664 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1665
1666 switch (Channel)
1667 {
1668 case TIM_CHANNEL_1:
1669 {
1670 /* Disable the TIM Capture/Compare 1 interrupt */
1671 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1672 break;
1673 }
1674
1675 case TIM_CHANNEL_2:
1676 {
1677 /* Disable the TIM Capture/Compare 2 interrupt */
1678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1679 break;
1680 }
1681
1682 case TIM_CHANNEL_3:
1683 {
1684 /* Disable the TIM Capture/Compare 3 interrupt */
1685 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1686 break;
1687 }
1688
1689 case TIM_CHANNEL_4:
1690 {
1691 /* Disable the TIM Capture/Compare 4 interrupt */
1692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1693 break;
1694 }
1695
1696 default:
1697 status = HAL_ERROR;
1698 break;
1699 }
1700
1701 if (status == HAL_OK)
1702 {
1703 /* Disable the Capture compare channel */
1704 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1705
1706 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1707 {
1708 /* Disable the Main Output */
1709 __HAL_TIM_MOE_DISABLE(htim);
1710 }
1711
1712 /* Disable the Peripheral */
1713 __HAL_TIM_DISABLE(htim);
1714
1715 /* Set the TIM channel state */
1716 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1717 }
1718
1719 /* Return function status */
1720 return status;
1721 }
1722
1723 /**
1724 * @brief Starts the TIM PWM signal generation in DMA mode.
1725 * @param htim TIM PWM handle
1726 * @param Channel TIM Channels to be enabled
1727 * This parameter can be one of the following values:
1728 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1729 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1730 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1731 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1732 * @param pData The source Buffer address.
1733 * @param Length The length of data to be transferred from memory to TIM peripheral
1734 * @retval HAL status
1735 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1736 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1737 uint16_t Length)
1738 {
1739 HAL_StatusTypeDef status = HAL_OK;
1740 uint32_t tmpsmcr;
1741
1742 /* Check the parameters */
1743 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1744
1745 /* Set the TIM channel state */
1746 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1747 {
1748 return HAL_BUSY;
1749 }
1750 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1751 {
1752 if ((pData == NULL) || (Length == 0U))
1753 {
1754 return HAL_ERROR;
1755 }
1756 else
1757 {
1758 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1759 }
1760 }
1761 else
1762 {
1763 return HAL_ERROR;
1764 }
1765
1766 switch (Channel)
1767 {
1768 case TIM_CHANNEL_1:
1769 {
1770 /* Set the DMA compare callbacks */
1771 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1772 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1773
1774 /* Set the DMA error callback */
1775 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1776
1777 /* Enable the DMA channel */
1778 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1779 Length) != HAL_OK)
1780 {
1781 /* Return error status */
1782 return HAL_ERROR;
1783 }
1784
1785 /* Enable the TIM Capture/Compare 1 DMA request */
1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1787 break;
1788 }
1789
1790 case TIM_CHANNEL_2:
1791 {
1792 /* Set the DMA compare callbacks */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1794 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1795
1796 /* Set the DMA error callback */
1797 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1798
1799 /* Enable the DMA channel */
1800 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1801 Length) != HAL_OK)
1802 {
1803 /* Return error status */
1804 return HAL_ERROR;
1805 }
1806 /* Enable the TIM Capture/Compare 2 DMA request */
1807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1808 break;
1809 }
1810
1811 case TIM_CHANNEL_3:
1812 {
1813 /* Set the DMA compare callbacks */
1814 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1815 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1816
1817 /* Set the DMA error callback */
1818 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1819
1820 /* Enable the DMA channel */
1821 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1822 Length) != HAL_OK)
1823 {
1824 /* Return error status */
1825 return HAL_ERROR;
1826 }
1827 /* Enable the TIM Output Capture/Compare 3 request */
1828 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1829 break;
1830 }
1831
1832 case TIM_CHANNEL_4:
1833 {
1834 /* Set the DMA compare callbacks */
1835 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1836 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1837
1838 /* Set the DMA error callback */
1839 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1840
1841 /* Enable the DMA channel */
1842 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1843 Length) != HAL_OK)
1844 {
1845 /* Return error status */
1846 return HAL_ERROR;
1847 }
1848 /* Enable the TIM Capture/Compare 4 DMA request */
1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1850 break;
1851 }
1852
1853 default:
1854 status = HAL_ERROR;
1855 break;
1856 }
1857
1858 if (status == HAL_OK)
1859 {
1860 /* Enable the Capture compare channel */
1861 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1862
1863 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1864 {
1865 /* Enable the main output */
1866 __HAL_TIM_MOE_ENABLE(htim);
1867 }
1868
1869 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1870 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1871 {
1872 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1873 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1874 {
1875 __HAL_TIM_ENABLE(htim);
1876 }
1877 }
1878 else
1879 {
1880 __HAL_TIM_ENABLE(htim);
1881 }
1882 }
1883
1884 /* Return function status */
1885 return status;
1886 }
1887
1888 /**
1889 * @brief Stops the TIM PWM signal generation in DMA mode.
1890 * @param htim TIM PWM handle
1891 * @param Channel TIM Channels to be disabled
1892 * This parameter can be one of the following values:
1893 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1894 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1895 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1896 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1897 * @retval HAL status
1898 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1899 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1900 {
1901 HAL_StatusTypeDef status = HAL_OK;
1902
1903 /* Check the parameters */
1904 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1905
1906 switch (Channel)
1907 {
1908 case TIM_CHANNEL_1:
1909 {
1910 /* Disable the TIM Capture/Compare 1 DMA request */
1911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1912 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1913 break;
1914 }
1915
1916 case TIM_CHANNEL_2:
1917 {
1918 /* Disable the TIM Capture/Compare 2 DMA request */
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1920 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1921 break;
1922 }
1923
1924 case TIM_CHANNEL_3:
1925 {
1926 /* Disable the TIM Capture/Compare 3 DMA request */
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1929 break;
1930 }
1931
1932 case TIM_CHANNEL_4:
1933 {
1934 /* Disable the TIM Capture/Compare 4 interrupt */
1935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1937 break;
1938 }
1939
1940 default:
1941 status = HAL_ERROR;
1942 break;
1943 }
1944
1945 if (status == HAL_OK)
1946 {
1947 /* Disable the Capture compare channel */
1948 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1949
1950 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1951 {
1952 /* Disable the Main Output */
1953 __HAL_TIM_MOE_DISABLE(htim);
1954 }
1955
1956 /* Disable the Peripheral */
1957 __HAL_TIM_DISABLE(htim);
1958
1959 /* Set the TIM channel state */
1960 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1961 }
1962
1963 /* Return function status */
1964 return status;
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1972 * @brief TIM Input Capture functions
1973 *
1974 @verbatim
1975 ==============================================================================
1976 ##### TIM Input Capture functions #####
1977 ==============================================================================
1978 [..]
1979 This section provides functions allowing to:
1980 (+) Initialize and configure the TIM Input Capture.
1981 (+) De-initialize the TIM Input Capture.
1982 (+) Start the TIM Input Capture.
1983 (+) Stop the TIM Input Capture.
1984 (+) Start the TIM Input Capture and enable interrupt.
1985 (+) Stop the TIM Input Capture and disable interrupt.
1986 (+) Start the TIM Input Capture and enable DMA transfer.
1987 (+) Stop the TIM Input Capture and disable DMA transfer.
1988
1989 @endverbatim
1990 * @{
1991 */
1992 /**
1993 * @brief Initializes the TIM Input Capture Time base according to the specified
1994 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1995 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1996 * requires a timer reset to avoid unexpected direction
1997 * due to DIR bit readonly in center aligned mode.
1998 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1999 * @param htim TIM Input Capture handle
2000 * @retval HAL status
2001 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)2002 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
2003 {
2004 /* Check the TIM handle allocation */
2005 if (htim == NULL)
2006 {
2007 return HAL_ERROR;
2008 }
2009
2010 /* Check the parameters */
2011 assert_param(IS_TIM_INSTANCE(htim->Instance));
2012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2014 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2015 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2016
2017 if (htim->State == HAL_TIM_STATE_RESET)
2018 {
2019 /* Allocate lock resource and initialize it */
2020 htim->Lock = HAL_UNLOCKED;
2021
2022 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2023 /* Reset interrupt callbacks to legacy weak callbacks */
2024 TIM_ResetCallback(htim);
2025
2026 if (htim->IC_MspInitCallback == NULL)
2027 {
2028 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2029 }
2030 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2031 htim->IC_MspInitCallback(htim);
2032 #else
2033 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2034 HAL_TIM_IC_MspInit(htim);
2035 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2036 }
2037
2038 /* Set the TIM state */
2039 htim->State = HAL_TIM_STATE_BUSY;
2040
2041 /* Init the base time for the input capture */
2042 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2043
2044 /* Initialize the DMA burst operation state */
2045 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2046
2047 /* Initialize the TIM channels state */
2048 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2049 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2050
2051 /* Initialize the TIM state*/
2052 htim->State = HAL_TIM_STATE_READY;
2053
2054 return HAL_OK;
2055 }
2056
2057 /**
2058 * @brief DeInitializes the TIM peripheral
2059 * @param htim TIM Input Capture handle
2060 * @retval HAL status
2061 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2062 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2063 {
2064 /* Check the parameters */
2065 assert_param(IS_TIM_INSTANCE(htim->Instance));
2066
2067 htim->State = HAL_TIM_STATE_BUSY;
2068
2069 /* Disable the TIM Peripheral Clock */
2070 __HAL_TIM_DISABLE(htim);
2071
2072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2073 if (htim->IC_MspDeInitCallback == NULL)
2074 {
2075 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2076 }
2077 /* DeInit the low level hardware */
2078 htim->IC_MspDeInitCallback(htim);
2079 #else
2080 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2081 HAL_TIM_IC_MspDeInit(htim);
2082 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2083
2084 /* Change the DMA burst operation state */
2085 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2086
2087 /* Change the TIM channels state */
2088 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2089 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2090
2091 /* Change TIM state */
2092 htim->State = HAL_TIM_STATE_RESET;
2093
2094 /* Release Lock */
2095 __HAL_UNLOCK(htim);
2096
2097 return HAL_OK;
2098 }
2099
2100 /**
2101 * @brief Initializes the TIM Input Capture MSP.
2102 * @param htim TIM Input Capture handle
2103 * @retval None
2104 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2105 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2106 {
2107 /* Prevent unused argument(s) compilation warning */
2108 UNUSED(htim);
2109
2110 /* NOTE : This function should not be modified, when the callback is needed,
2111 the HAL_TIM_IC_MspInit could be implemented in the user file
2112 */
2113 }
2114
2115 /**
2116 * @brief DeInitializes TIM Input Capture MSP.
2117 * @param htim TIM handle
2118 * @retval None
2119 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2120 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2121 {
2122 /* Prevent unused argument(s) compilation warning */
2123 UNUSED(htim);
2124
2125 /* NOTE : This function should not be modified, when the callback is needed,
2126 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2127 */
2128 }
2129
2130 /**
2131 * @brief Starts the TIM Input Capture measurement.
2132 * @param htim TIM Input Capture handle
2133 * @param Channel TIM Channels to be enabled
2134 * This parameter can be one of the following values:
2135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2139 * @retval HAL status
2140 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2141 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2142 {
2143 uint32_t tmpsmcr;
2144 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2145 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2146
2147 /* Check the parameters */
2148 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2149
2150 /* Check the TIM channel state */
2151 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2152 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2153 {
2154 return HAL_ERROR;
2155 }
2156
2157 /* Set the TIM channel state */
2158 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2159 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2160
2161 /* Enable the Input Capture channel */
2162 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2163
2164 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2165 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2166 {
2167 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2168 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2169 {
2170 __HAL_TIM_ENABLE(htim);
2171 }
2172 }
2173 else
2174 {
2175 __HAL_TIM_ENABLE(htim);
2176 }
2177
2178 /* Return function status */
2179 return HAL_OK;
2180 }
2181
2182 /**
2183 * @brief Stops the TIM Input Capture measurement.
2184 * @param htim TIM Input Capture handle
2185 * @param Channel TIM Channels to be disabled
2186 * This parameter can be one of the following values:
2187 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2188 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2189 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2190 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2191 * @retval HAL status
2192 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2193 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2194 {
2195 /* Check the parameters */
2196 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2197
2198 /* Disable the Input Capture channel */
2199 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2200
2201 /* Disable the Peripheral */
2202 __HAL_TIM_DISABLE(htim);
2203
2204 /* Set the TIM channel state */
2205 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2206 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2207
2208 /* Return function status */
2209 return HAL_OK;
2210 }
2211
2212 /**
2213 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2214 * @param htim TIM Input Capture handle
2215 * @param Channel TIM Channels to be enabled
2216 * This parameter can be one of the following values:
2217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2221 * @retval HAL status
2222 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2223 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2224 {
2225 HAL_StatusTypeDef status = HAL_OK;
2226 uint32_t tmpsmcr;
2227
2228 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2229 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2230
2231 /* Check the parameters */
2232 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2233
2234 /* Check the TIM channel state */
2235 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2236 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2237 {
2238 return HAL_ERROR;
2239 }
2240
2241 /* Set the TIM channel state */
2242 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2243 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2244
2245 switch (Channel)
2246 {
2247 case TIM_CHANNEL_1:
2248 {
2249 /* Enable the TIM Capture/Compare 1 interrupt */
2250 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2251 break;
2252 }
2253
2254 case TIM_CHANNEL_2:
2255 {
2256 /* Enable the TIM Capture/Compare 2 interrupt */
2257 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2258 break;
2259 }
2260
2261 case TIM_CHANNEL_3:
2262 {
2263 /* Enable the TIM Capture/Compare 3 interrupt */
2264 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2265 break;
2266 }
2267
2268 case TIM_CHANNEL_4:
2269 {
2270 /* Enable the TIM Capture/Compare 4 interrupt */
2271 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2272 break;
2273 }
2274
2275 default:
2276 status = HAL_ERROR;
2277 break;
2278 }
2279
2280 if (status == HAL_OK)
2281 {
2282 /* Enable the Input Capture channel */
2283 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2284
2285 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2286 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2287 {
2288 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2289 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2290 {
2291 __HAL_TIM_ENABLE(htim);
2292 }
2293 }
2294 else
2295 {
2296 __HAL_TIM_ENABLE(htim);
2297 }
2298 }
2299
2300 /* Return function status */
2301 return status;
2302 }
2303
2304 /**
2305 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2306 * @param htim TIM Input Capture handle
2307 * @param Channel TIM Channels to be disabled
2308 * This parameter can be one of the following values:
2309 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2310 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2311 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2312 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2313 * @retval HAL status
2314 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2315 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2316 {
2317 HAL_StatusTypeDef status = HAL_OK;
2318
2319 /* Check the parameters */
2320 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2321
2322 switch (Channel)
2323 {
2324 case TIM_CHANNEL_1:
2325 {
2326 /* Disable the TIM Capture/Compare 1 interrupt */
2327 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2328 break;
2329 }
2330
2331 case TIM_CHANNEL_2:
2332 {
2333 /* Disable the TIM Capture/Compare 2 interrupt */
2334 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2335 break;
2336 }
2337
2338 case TIM_CHANNEL_3:
2339 {
2340 /* Disable the TIM Capture/Compare 3 interrupt */
2341 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2342 break;
2343 }
2344
2345 case TIM_CHANNEL_4:
2346 {
2347 /* Disable the TIM Capture/Compare 4 interrupt */
2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2349 break;
2350 }
2351
2352 default:
2353 status = HAL_ERROR;
2354 break;
2355 }
2356
2357 if (status == HAL_OK)
2358 {
2359 /* Disable the Input Capture channel */
2360 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2361
2362 /* Disable the Peripheral */
2363 __HAL_TIM_DISABLE(htim);
2364
2365 /* Set the TIM channel state */
2366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2368 }
2369
2370 /* Return function status */
2371 return status;
2372 }
2373
2374 /**
2375 * @brief Starts the TIM Input Capture measurement in DMA mode.
2376 * @param htim TIM Input Capture handle
2377 * @param Channel TIM Channels to be enabled
2378 * This parameter can be one of the following values:
2379 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2380 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2381 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2382 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2383 * @param pData The destination Buffer address.
2384 * @param Length The length of data to be transferred from TIM peripheral to memory.
2385 * @retval HAL status
2386 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2387 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2388 {
2389 HAL_StatusTypeDef status = HAL_OK;
2390 uint32_t tmpsmcr;
2391
2392 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2393 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2394
2395 /* Check the parameters */
2396 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2397 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2398
2399 /* Set the TIM channel state */
2400 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2401 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2402 {
2403 return HAL_BUSY;
2404 }
2405 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2406 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2407 {
2408 if ((pData == NULL) || (Length == 0U))
2409 {
2410 return HAL_ERROR;
2411 }
2412 else
2413 {
2414 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2415 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2416 }
2417 }
2418 else
2419 {
2420 return HAL_ERROR;
2421 }
2422
2423 /* Enable the Input Capture channel */
2424 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2425
2426 switch (Channel)
2427 {
2428 case TIM_CHANNEL_1:
2429 {
2430 /* Set the DMA capture callbacks */
2431 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2432 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2433
2434 /* Set the DMA error callback */
2435 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2436
2437 /* Enable the DMA channel */
2438 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2439 Length) != HAL_OK)
2440 {
2441 /* Return error status */
2442 return HAL_ERROR;
2443 }
2444 /* Enable the TIM Capture/Compare 1 DMA request */
2445 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2446 break;
2447 }
2448
2449 case TIM_CHANNEL_2:
2450 {
2451 /* Set the DMA capture callbacks */
2452 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2453 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2454
2455 /* Set the DMA error callback */
2456 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2457
2458 /* Enable the DMA channel */
2459 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2460 Length) != HAL_OK)
2461 {
2462 /* Return error status */
2463 return HAL_ERROR;
2464 }
2465 /* Enable the TIM Capture/Compare 2 DMA request */
2466 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2467 break;
2468 }
2469
2470 case TIM_CHANNEL_3:
2471 {
2472 /* Set the DMA capture callbacks */
2473 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2474 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2475
2476 /* Set the DMA error callback */
2477 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2478
2479 /* Enable the DMA channel */
2480 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2481 Length) != HAL_OK)
2482 {
2483 /* Return error status */
2484 return HAL_ERROR;
2485 }
2486 /* Enable the TIM Capture/Compare 3 DMA request */
2487 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2488 break;
2489 }
2490
2491 case TIM_CHANNEL_4:
2492 {
2493 /* Set the DMA capture callbacks */
2494 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2495 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2496
2497 /* Set the DMA error callback */
2498 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2499
2500 /* Enable the DMA channel */
2501 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2502 Length) != HAL_OK)
2503 {
2504 /* Return error status */
2505 return HAL_ERROR;
2506 }
2507 /* Enable the TIM Capture/Compare 4 DMA request */
2508 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2509 break;
2510 }
2511
2512 default:
2513 status = HAL_ERROR;
2514 break;
2515 }
2516
2517 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2518 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2519 {
2520 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2521 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2522 {
2523 __HAL_TIM_ENABLE(htim);
2524 }
2525 }
2526 else
2527 {
2528 __HAL_TIM_ENABLE(htim);
2529 }
2530
2531 /* Return function status */
2532 return status;
2533 }
2534
2535 /**
2536 * @brief Stops the TIM Input Capture measurement in DMA mode.
2537 * @param htim TIM Input Capture handle
2538 * @param Channel TIM Channels to be disabled
2539 * This parameter can be one of the following values:
2540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2542 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2543 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2544 * @retval HAL status
2545 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2546 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2547 {
2548 HAL_StatusTypeDef status = HAL_OK;
2549
2550 /* Check the parameters */
2551 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2552 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2553
2554 /* Disable the Input Capture channel */
2555 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2556
2557 switch (Channel)
2558 {
2559 case TIM_CHANNEL_1:
2560 {
2561 /* Disable the TIM Capture/Compare 1 DMA request */
2562 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2563 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2564 break;
2565 }
2566
2567 case TIM_CHANNEL_2:
2568 {
2569 /* Disable the TIM Capture/Compare 2 DMA request */
2570 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2571 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2572 break;
2573 }
2574
2575 case TIM_CHANNEL_3:
2576 {
2577 /* Disable the TIM Capture/Compare 3 DMA request */
2578 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2579 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2580 break;
2581 }
2582
2583 case TIM_CHANNEL_4:
2584 {
2585 /* Disable the TIM Capture/Compare 4 DMA request */
2586 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2587 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2588 break;
2589 }
2590
2591 default:
2592 status = HAL_ERROR;
2593 break;
2594 }
2595
2596 if (status == HAL_OK)
2597 {
2598 /* Disable the Peripheral */
2599 __HAL_TIM_DISABLE(htim);
2600
2601 /* Set the TIM channel state */
2602 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2603 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2604 }
2605
2606 /* Return function status */
2607 return status;
2608 }
2609 /**
2610 * @}
2611 */
2612
2613 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2614 * @brief TIM One Pulse functions
2615 *
2616 @verbatim
2617 ==============================================================================
2618 ##### TIM One Pulse functions #####
2619 ==============================================================================
2620 [..]
2621 This section provides functions allowing to:
2622 (+) Initialize and configure the TIM One Pulse.
2623 (+) De-initialize the TIM One Pulse.
2624 (+) Start the TIM One Pulse.
2625 (+) Stop the TIM One Pulse.
2626 (+) Start the TIM One Pulse and enable interrupt.
2627 (+) Stop the TIM One Pulse and disable interrupt.
2628 (+) Start the TIM One Pulse and enable DMA transfer.
2629 (+) Stop the TIM One Pulse and disable DMA transfer.
2630
2631 @endverbatim
2632 * @{
2633 */
2634 /**
2635 * @brief Initializes the TIM One Pulse Time Base according to the specified
2636 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2637 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2638 * requires a timer reset to avoid unexpected direction
2639 * due to DIR bit readonly in center aligned mode.
2640 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2641 * @note When the timer instance is initialized in One Pulse mode, timer
2642 * channels 1 and channel 2 are reserved and cannot be used for other
2643 * purpose.
2644 * @param htim TIM One Pulse handle
2645 * @param OnePulseMode Select the One pulse mode.
2646 * This parameter can be one of the following values:
2647 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2648 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2649 * @retval HAL status
2650 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2651 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2652 {
2653 /* Check the TIM handle allocation */
2654 if (htim == NULL)
2655 {
2656 return HAL_ERROR;
2657 }
2658
2659 /* Check the parameters */
2660 assert_param(IS_TIM_INSTANCE(htim->Instance));
2661 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2662 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2663 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2664 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2665 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2666
2667 if (htim->State == HAL_TIM_STATE_RESET)
2668 {
2669 /* Allocate lock resource and initialize it */
2670 htim->Lock = HAL_UNLOCKED;
2671
2672 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2673 /* Reset interrupt callbacks to legacy weak callbacks */
2674 TIM_ResetCallback(htim);
2675
2676 if (htim->OnePulse_MspInitCallback == NULL)
2677 {
2678 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2679 }
2680 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2681 htim->OnePulse_MspInitCallback(htim);
2682 #else
2683 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2684 HAL_TIM_OnePulse_MspInit(htim);
2685 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2686 }
2687
2688 /* Set the TIM state */
2689 htim->State = HAL_TIM_STATE_BUSY;
2690
2691 /* Configure the Time base in the One Pulse Mode */
2692 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2693
2694 /* Reset the OPM Bit */
2695 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2696
2697 /* Configure the OPM Mode */
2698 htim->Instance->CR1 |= OnePulseMode;
2699
2700 /* Initialize the DMA burst operation state */
2701 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2702
2703 /* Initialize the TIM channels state */
2704 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2705 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2706 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2707 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2708
2709 /* Initialize the TIM state*/
2710 htim->State = HAL_TIM_STATE_READY;
2711
2712 return HAL_OK;
2713 }
2714
2715 /**
2716 * @brief DeInitializes the TIM One Pulse
2717 * @param htim TIM One Pulse handle
2718 * @retval HAL status
2719 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2720 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2721 {
2722 /* Check the parameters */
2723 assert_param(IS_TIM_INSTANCE(htim->Instance));
2724
2725 htim->State = HAL_TIM_STATE_BUSY;
2726
2727 /* Disable the TIM Peripheral Clock */
2728 __HAL_TIM_DISABLE(htim);
2729
2730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2731 if (htim->OnePulse_MspDeInitCallback == NULL)
2732 {
2733 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2734 }
2735 /* DeInit the low level hardware */
2736 htim->OnePulse_MspDeInitCallback(htim);
2737 #else
2738 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2739 HAL_TIM_OnePulse_MspDeInit(htim);
2740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2741
2742 /* Change the DMA burst operation state */
2743 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2744
2745 /* Set the TIM channel state */
2746 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2747 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2748 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2749 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2750
2751 /* Change TIM state */
2752 htim->State = HAL_TIM_STATE_RESET;
2753
2754 /* Release Lock */
2755 __HAL_UNLOCK(htim);
2756
2757 return HAL_OK;
2758 }
2759
2760 /**
2761 * @brief Initializes the TIM One Pulse MSP.
2762 * @param htim TIM One Pulse handle
2763 * @retval None
2764 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2765 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2766 {
2767 /* Prevent unused argument(s) compilation warning */
2768 UNUSED(htim);
2769
2770 /* NOTE : This function should not be modified, when the callback is needed,
2771 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2772 */
2773 }
2774
2775 /**
2776 * @brief DeInitializes TIM One Pulse MSP.
2777 * @param htim TIM One Pulse handle
2778 * @retval None
2779 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2780 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2781 {
2782 /* Prevent unused argument(s) compilation warning */
2783 UNUSED(htim);
2784
2785 /* NOTE : This function should not be modified, when the callback is needed,
2786 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2787 */
2788 }
2789
2790 /**
2791 * @brief Starts the TIM One Pulse signal generation.
2792 * @note Though OutputChannel parameter is deprecated and ignored by the function
2793 * it has been kept to avoid HAL_TIM API compatibility break.
2794 * @note The pulse output channel is determined when calling
2795 * @ref HAL_TIM_OnePulse_ConfigChannel().
2796 * @param htim TIM One Pulse handle
2797 * @param OutputChannel See note above
2798 * @retval HAL status
2799 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2800 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2801 {
2802 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2803 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2804 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2805 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2806
2807 /* Prevent unused argument(s) compilation warning */
2808 UNUSED(OutputChannel);
2809
2810 /* Check the TIM channels state */
2811 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2812 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2813 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2814 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2815 {
2816 return HAL_ERROR;
2817 }
2818
2819 /* Set the TIM channels state */
2820 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2821 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2822 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2823 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2824
2825 /* Enable the Capture compare and the Input Capture channels
2826 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2827 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2828 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2829 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2830
2831 No need to enable the counter, it's enabled automatically by hardware
2832 (the counter starts in response to a stimulus and generate a pulse */
2833
2834 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2835 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2836
2837 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2838 {
2839 /* Enable the main output */
2840 __HAL_TIM_MOE_ENABLE(htim);
2841 }
2842
2843 /* Return function status */
2844 return HAL_OK;
2845 }
2846
2847 /**
2848 * @brief Stops the TIM One Pulse signal generation.
2849 * @note Though OutputChannel parameter is deprecated and ignored by the function
2850 * it has been kept to avoid HAL_TIM API compatibility break.
2851 * @note The pulse output channel is determined when calling
2852 * @ref HAL_TIM_OnePulse_ConfigChannel().
2853 * @param htim TIM One Pulse handle
2854 * @param OutputChannel See note above
2855 * @retval HAL status
2856 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2857 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2858 {
2859 /* Prevent unused argument(s) compilation warning */
2860 UNUSED(OutputChannel);
2861
2862 /* Disable the Capture compare and the Input Capture channels
2863 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2864 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2865 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2866 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2867
2868 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2869 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2870
2871 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2872 {
2873 /* Disable the Main Output */
2874 __HAL_TIM_MOE_DISABLE(htim);
2875 }
2876
2877 /* Disable the Peripheral */
2878 __HAL_TIM_DISABLE(htim);
2879
2880 /* Set the TIM channels state */
2881 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2882 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2883 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2884 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2885
2886 /* Return function status */
2887 return HAL_OK;
2888 }
2889
2890 /**
2891 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2892 * @note Though OutputChannel parameter is deprecated and ignored by the function
2893 * it has been kept to avoid HAL_TIM API compatibility break.
2894 * @note The pulse output channel is determined when calling
2895 * @ref HAL_TIM_OnePulse_ConfigChannel().
2896 * @param htim TIM One Pulse handle
2897 * @param OutputChannel See note above
2898 * @retval HAL status
2899 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2900 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2901 {
2902 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2903 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2904 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2905 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2906
2907 /* Prevent unused argument(s) compilation warning */
2908 UNUSED(OutputChannel);
2909
2910 /* Check the TIM channels state */
2911 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2912 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2913 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2914 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2915 {
2916 return HAL_ERROR;
2917 }
2918
2919 /* Set the TIM channels state */
2920 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2921 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2922 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2923 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2924
2925 /* Enable the Capture compare and the Input Capture channels
2926 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2927 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2928 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2929 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2930
2931 No need to enable the counter, it's enabled automatically by hardware
2932 (the counter starts in response to a stimulus and generate a pulse */
2933
2934 /* Enable the TIM Capture/Compare 1 interrupt */
2935 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2936
2937 /* Enable the TIM Capture/Compare 2 interrupt */
2938 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2939
2940 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2941 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2942
2943 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2944 {
2945 /* Enable the main output */
2946 __HAL_TIM_MOE_ENABLE(htim);
2947 }
2948
2949 /* Return function status */
2950 return HAL_OK;
2951 }
2952
2953 /**
2954 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2955 * @note Though OutputChannel parameter is deprecated and ignored by the function
2956 * it has been kept to avoid HAL_TIM API compatibility break.
2957 * @note The pulse output channel is determined when calling
2958 * @ref HAL_TIM_OnePulse_ConfigChannel().
2959 * @param htim TIM One Pulse handle
2960 * @param OutputChannel See note above
2961 * @retval HAL status
2962 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2964 {
2965 /* Prevent unused argument(s) compilation warning */
2966 UNUSED(OutputChannel);
2967
2968 /* Disable the TIM Capture/Compare 1 interrupt */
2969 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2970
2971 /* Disable the TIM Capture/Compare 2 interrupt */
2972 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2973
2974 /* Disable the Capture compare and the Input Capture channels
2975 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2976 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2977 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2978 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2979 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2980 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2981
2982 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2983 {
2984 /* Disable the Main Output */
2985 __HAL_TIM_MOE_DISABLE(htim);
2986 }
2987
2988 /* Disable the Peripheral */
2989 __HAL_TIM_DISABLE(htim);
2990
2991 /* Set the TIM channels state */
2992 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2993 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2994 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2995 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2996
2997 /* Return function status */
2998 return HAL_OK;
2999 }
3000
3001 /**
3002 * @}
3003 */
3004
3005 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
3006 * @brief TIM Encoder functions
3007 *
3008 @verbatim
3009 ==============================================================================
3010 ##### TIM Encoder functions #####
3011 ==============================================================================
3012 [..]
3013 This section provides functions allowing to:
3014 (+) Initialize and configure the TIM Encoder.
3015 (+) De-initialize the TIM Encoder.
3016 (+) Start the TIM Encoder.
3017 (+) Stop the TIM Encoder.
3018 (+) Start the TIM Encoder and enable interrupt.
3019 (+) Stop the TIM Encoder and disable interrupt.
3020 (+) Start the TIM Encoder and enable DMA transfer.
3021 (+) Stop the TIM Encoder and disable DMA transfer.
3022
3023 @endverbatim
3024 * @{
3025 */
3026 /**
3027 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3028 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3029 * requires a timer reset to avoid unexpected direction
3030 * due to DIR bit readonly in center aligned mode.
3031 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3032 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3033 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3034 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3035 * @note When the timer instance is initialized in Encoder mode, timer
3036 * channels 1 and channel 2 are reserved and cannot be used for other
3037 * purpose.
3038 * @param htim TIM Encoder Interface handle
3039 * @param sConfig TIM Encoder Interface configuration structure
3040 * @retval HAL status
3041 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3042 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3043 {
3044 uint32_t tmpsmcr;
3045 uint32_t tmpccmr1;
3046 uint32_t tmpccer;
3047
3048 /* Check the TIM handle allocation */
3049 if (htim == NULL)
3050 {
3051 return HAL_ERROR;
3052 }
3053
3054 /* Check the parameters */
3055 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3056 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3057 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3058 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3059 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3060 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3061 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3062 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3063 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3064 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3065 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3066 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3067 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3068 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3069
3070 if (htim->State == HAL_TIM_STATE_RESET)
3071 {
3072 /* Allocate lock resource and initialize it */
3073 htim->Lock = HAL_UNLOCKED;
3074
3075 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3076 /* Reset interrupt callbacks to legacy weak callbacks */
3077 TIM_ResetCallback(htim);
3078
3079 if (htim->Encoder_MspInitCallback == NULL)
3080 {
3081 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3082 }
3083 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3084 htim->Encoder_MspInitCallback(htim);
3085 #else
3086 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3087 HAL_TIM_Encoder_MspInit(htim);
3088 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3089 }
3090
3091 /* Set the TIM state */
3092 htim->State = HAL_TIM_STATE_BUSY;
3093
3094 /* Reset the SMS and ECE bits */
3095 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3096
3097 /* Configure the Time base in the Encoder Mode */
3098 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3099
3100 /* Get the TIMx SMCR register value */
3101 tmpsmcr = htim->Instance->SMCR;
3102
3103 /* Get the TIMx CCMR1 register value */
3104 tmpccmr1 = htim->Instance->CCMR1;
3105
3106 /* Get the TIMx CCER register value */
3107 tmpccer = htim->Instance->CCER;
3108
3109 /* Set the encoder Mode */
3110 tmpsmcr |= sConfig->EncoderMode;
3111
3112 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3113 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3114 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3115
3116 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3117 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3118 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3119 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3120 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3121
3122 /* Set the TI1 and the TI2 Polarities */
3123 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3124 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3125 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3126
3127 /* Write to TIMx SMCR */
3128 htim->Instance->SMCR = tmpsmcr;
3129
3130 /* Write to TIMx CCMR1 */
3131 htim->Instance->CCMR1 = tmpccmr1;
3132
3133 /* Write to TIMx CCER */
3134 htim->Instance->CCER = tmpccer;
3135
3136 /* Initialize the DMA burst operation state */
3137 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3138
3139 /* Set the TIM channels state */
3140 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3141 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3142 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3143 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3144
3145 /* Initialize the TIM state*/
3146 htim->State = HAL_TIM_STATE_READY;
3147
3148 return HAL_OK;
3149 }
3150
3151
3152 /**
3153 * @brief DeInitializes the TIM Encoder interface
3154 * @param htim TIM Encoder Interface handle
3155 * @retval HAL status
3156 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3157 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3158 {
3159 /* Check the parameters */
3160 assert_param(IS_TIM_INSTANCE(htim->Instance));
3161
3162 htim->State = HAL_TIM_STATE_BUSY;
3163
3164 /* Disable the TIM Peripheral Clock */
3165 __HAL_TIM_DISABLE(htim);
3166
3167 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3168 if (htim->Encoder_MspDeInitCallback == NULL)
3169 {
3170 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3171 }
3172 /* DeInit the low level hardware */
3173 htim->Encoder_MspDeInitCallback(htim);
3174 #else
3175 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3176 HAL_TIM_Encoder_MspDeInit(htim);
3177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3178
3179 /* Change the DMA burst operation state */
3180 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3181
3182 /* Set the TIM channels state */
3183 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3184 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3185 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3186 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3187
3188 /* Change TIM state */
3189 htim->State = HAL_TIM_STATE_RESET;
3190
3191 /* Release Lock */
3192 __HAL_UNLOCK(htim);
3193
3194 return HAL_OK;
3195 }
3196
3197 /**
3198 * @brief Initializes the TIM Encoder Interface MSP.
3199 * @param htim TIM Encoder Interface handle
3200 * @retval None
3201 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3202 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3203 {
3204 /* Prevent unused argument(s) compilation warning */
3205 UNUSED(htim);
3206
3207 /* NOTE : This function should not be modified, when the callback is needed,
3208 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3209 */
3210 }
3211
3212 /**
3213 * @brief DeInitializes TIM Encoder Interface MSP.
3214 * @param htim TIM Encoder Interface handle
3215 * @retval None
3216 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3217 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3218 {
3219 /* Prevent unused argument(s) compilation warning */
3220 UNUSED(htim);
3221
3222 /* NOTE : This function should not be modified, when the callback is needed,
3223 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3224 */
3225 }
3226
3227 /**
3228 * @brief Starts the TIM Encoder Interface.
3229 * @param htim TIM Encoder Interface handle
3230 * @param Channel TIM Channels to be enabled
3231 * This parameter can be one of the following values:
3232 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3233 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3234 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3235 * @retval HAL status
3236 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3237 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3238 {
3239 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3240 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3241 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3242 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3243
3244 /* Check the parameters */
3245 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3246
3247 /* Set the TIM channel(s) state */
3248 if (Channel == TIM_CHANNEL_1)
3249 {
3250 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3251 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3252 {
3253 return HAL_ERROR;
3254 }
3255 else
3256 {
3257 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3258 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3259 }
3260 }
3261 else if (Channel == TIM_CHANNEL_2)
3262 {
3263 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3264 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3265 {
3266 return HAL_ERROR;
3267 }
3268 else
3269 {
3270 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3271 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3272 }
3273 }
3274 else
3275 {
3276 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3277 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3278 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3279 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3280 {
3281 return HAL_ERROR;
3282 }
3283 else
3284 {
3285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3289 }
3290 }
3291
3292 /* Enable the encoder interface channels */
3293 switch (Channel)
3294 {
3295 case TIM_CHANNEL_1:
3296 {
3297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3298 break;
3299 }
3300
3301 case TIM_CHANNEL_2:
3302 {
3303 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3304 break;
3305 }
3306
3307 default :
3308 {
3309 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3310 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3311 break;
3312 }
3313 }
3314 /* Enable the Peripheral */
3315 __HAL_TIM_ENABLE(htim);
3316
3317 /* Return function status */
3318 return HAL_OK;
3319 }
3320
3321 /**
3322 * @brief Stops the TIM Encoder Interface.
3323 * @param htim TIM Encoder Interface handle
3324 * @param Channel TIM Channels to be disabled
3325 * This parameter can be one of the following values:
3326 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3327 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3328 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3329 * @retval HAL status
3330 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3331 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3332 {
3333 /* Check the parameters */
3334 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3335
3336 /* Disable the Input Capture channels 1 and 2
3337 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3338 switch (Channel)
3339 {
3340 case TIM_CHANNEL_1:
3341 {
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3343 break;
3344 }
3345
3346 case TIM_CHANNEL_2:
3347 {
3348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3349 break;
3350 }
3351
3352 default :
3353 {
3354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3355 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3356 break;
3357 }
3358 }
3359
3360 /* Disable the Peripheral */
3361 __HAL_TIM_DISABLE(htim);
3362
3363 /* Set the TIM channel(s) state */
3364 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3365 {
3366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3368 }
3369 else
3370 {
3371 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3372 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3373 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3374 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3375 }
3376
3377 /* Return function status */
3378 return HAL_OK;
3379 }
3380
3381 /**
3382 * @brief Starts the TIM Encoder Interface in interrupt mode.
3383 * @param htim TIM Encoder Interface handle
3384 * @param Channel TIM Channels to be enabled
3385 * This parameter can be one of the following values:
3386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3389 * @retval HAL status
3390 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3391 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3392 {
3393 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3394 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3395 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3396 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3397
3398 /* Check the parameters */
3399 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3400
3401 /* Set the TIM channel(s) state */
3402 if (Channel == TIM_CHANNEL_1)
3403 {
3404 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3405 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3406 {
3407 return HAL_ERROR;
3408 }
3409 else
3410 {
3411 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3412 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3413 }
3414 }
3415 else if (Channel == TIM_CHANNEL_2)
3416 {
3417 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3418 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3419 {
3420 return HAL_ERROR;
3421 }
3422 else
3423 {
3424 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3425 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3426 }
3427 }
3428 else
3429 {
3430 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3431 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3432 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3433 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3434 {
3435 return HAL_ERROR;
3436 }
3437 else
3438 {
3439 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3440 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3441 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3442 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3443 }
3444 }
3445
3446 /* Enable the encoder interface channels */
3447 /* Enable the capture compare Interrupts 1 and/or 2 */
3448 switch (Channel)
3449 {
3450 case TIM_CHANNEL_1:
3451 {
3452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3453 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3454 break;
3455 }
3456
3457 case TIM_CHANNEL_2:
3458 {
3459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3461 break;
3462 }
3463
3464 default :
3465 {
3466 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3468 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3469 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3470 break;
3471 }
3472 }
3473
3474 /* Enable the Peripheral */
3475 __HAL_TIM_ENABLE(htim);
3476
3477 /* Return function status */
3478 return HAL_OK;
3479 }
3480
3481 /**
3482 * @brief Stops the TIM Encoder Interface in interrupt mode.
3483 * @param htim TIM Encoder Interface handle
3484 * @param Channel TIM Channels to be disabled
3485 * This parameter can be one of the following values:
3486 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3487 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3488 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3489 * @retval HAL status
3490 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3492 {
3493 /* Check the parameters */
3494 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3495
3496 /* Disable the Input Capture channels 1 and 2
3497 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3498 if (Channel == TIM_CHANNEL_1)
3499 {
3500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3501
3502 /* Disable the capture compare Interrupts 1 */
3503 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3504 }
3505 else if (Channel == TIM_CHANNEL_2)
3506 {
3507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3508
3509 /* Disable the capture compare Interrupts 2 */
3510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3511 }
3512 else
3513 {
3514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3516
3517 /* Disable the capture compare Interrupts 1 and 2 */
3518 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3519 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3520 }
3521
3522 /* Disable the Peripheral */
3523 __HAL_TIM_DISABLE(htim);
3524
3525 /* Set the TIM channel(s) state */
3526 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3527 {
3528 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3529 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3530 }
3531 else
3532 {
3533 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3534 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3535 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3536 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3537 }
3538
3539 /* Return function status */
3540 return HAL_OK;
3541 }
3542
3543 /**
3544 * @brief Starts the TIM Encoder Interface in DMA mode.
3545 * @param htim TIM Encoder Interface handle
3546 * @param Channel TIM Channels to be enabled
3547 * This parameter can be one of the following values:
3548 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3549 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3550 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3551 * @param pData1 The destination Buffer address for IC1.
3552 * @param pData2 The destination Buffer address for IC2.
3553 * @param Length The length of data to be transferred from TIM peripheral to memory.
3554 * @retval HAL status
3555 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3556 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3557 uint32_t *pData2, uint16_t Length)
3558 {
3559 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3560 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3561 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3562 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3563
3564 /* Check the parameters */
3565 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3566
3567 /* Set the TIM channel(s) state */
3568 if (Channel == TIM_CHANNEL_1)
3569 {
3570 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3571 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3572 {
3573 return HAL_BUSY;
3574 }
3575 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3576 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3577 {
3578 if ((pData1 == NULL) || (Length == 0U))
3579 {
3580 return HAL_ERROR;
3581 }
3582 else
3583 {
3584 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3585 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3586 }
3587 }
3588 else
3589 {
3590 return HAL_ERROR;
3591 }
3592 }
3593 else if (Channel == TIM_CHANNEL_2)
3594 {
3595 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3596 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3597 {
3598 return HAL_BUSY;
3599 }
3600 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3601 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3602 {
3603 if ((pData2 == NULL) || (Length == 0U))
3604 {
3605 return HAL_ERROR;
3606 }
3607 else
3608 {
3609 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3611 }
3612 }
3613 else
3614 {
3615 return HAL_ERROR;
3616 }
3617 }
3618 else
3619 {
3620 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3621 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3622 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3623 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3624 {
3625 return HAL_BUSY;
3626 }
3627 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3628 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3629 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3630 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3631 {
3632 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3633 {
3634 return HAL_ERROR;
3635 }
3636 else
3637 {
3638 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3640 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3641 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3642 }
3643 }
3644 else
3645 {
3646 return HAL_ERROR;
3647 }
3648 }
3649
3650 switch (Channel)
3651 {
3652 case TIM_CHANNEL_1:
3653 {
3654 /* Set the DMA capture callbacks */
3655 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3656 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3657
3658 /* Set the DMA error callback */
3659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3660
3661 /* Enable the DMA channel */
3662 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3663 Length) != HAL_OK)
3664 {
3665 /* Return error status */
3666 return HAL_ERROR;
3667 }
3668 /* Enable the TIM Input Capture DMA request */
3669 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3670
3671 /* Enable the Capture compare channel */
3672 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3673
3674 /* Enable the Peripheral */
3675 __HAL_TIM_ENABLE(htim);
3676
3677 break;
3678 }
3679
3680 case TIM_CHANNEL_2:
3681 {
3682 /* Set the DMA capture callbacks */
3683 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3684 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3685
3686 /* Set the DMA error callback */
3687 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3688 /* Enable the DMA channel */
3689 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3690 Length) != HAL_OK)
3691 {
3692 /* Return error status */
3693 return HAL_ERROR;
3694 }
3695 /* Enable the TIM Input Capture DMA request */
3696 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3697
3698 /* Enable the Capture compare channel */
3699 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3700
3701 /* Enable the Peripheral */
3702 __HAL_TIM_ENABLE(htim);
3703
3704 break;
3705 }
3706
3707 default:
3708 {
3709 /* Set the DMA capture callbacks */
3710 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3711 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3712
3713 /* Set the DMA error callback */
3714 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3715
3716 /* Enable the DMA channel */
3717 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3718 Length) != HAL_OK)
3719 {
3720 /* Return error status */
3721 return HAL_ERROR;
3722 }
3723
3724 /* Set the DMA capture callbacks */
3725 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3726 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3727
3728 /* Set the DMA error callback */
3729 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3730
3731 /* Enable the DMA channel */
3732 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3733 Length) != HAL_OK)
3734 {
3735 /* Return error status */
3736 return HAL_ERROR;
3737 }
3738
3739 /* Enable the TIM Input Capture DMA request */
3740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3741 /* Enable the TIM Input Capture DMA request */
3742 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3743
3744 /* Enable the Capture compare channel */
3745 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3746 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3747
3748 /* Enable the Peripheral */
3749 __HAL_TIM_ENABLE(htim);
3750
3751 break;
3752 }
3753 }
3754
3755 /* Return function status */
3756 return HAL_OK;
3757 }
3758
3759 /**
3760 * @brief Stops the TIM Encoder Interface in DMA mode.
3761 * @param htim TIM Encoder Interface handle
3762 * @param Channel TIM Channels to be enabled
3763 * This parameter can be one of the following values:
3764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3766 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3767 * @retval HAL status
3768 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3769 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3770 {
3771 /* Check the parameters */
3772 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3773
3774 /* Disable the Input Capture channels 1 and 2
3775 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3776 if (Channel == TIM_CHANNEL_1)
3777 {
3778 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3779
3780 /* Disable the capture compare DMA Request 1 */
3781 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3782 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3783 }
3784 else if (Channel == TIM_CHANNEL_2)
3785 {
3786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3787
3788 /* Disable the capture compare DMA Request 2 */
3789 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3790 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3791 }
3792 else
3793 {
3794 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3795 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3796
3797 /* Disable the capture compare DMA Request 1 and 2 */
3798 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3799 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3800 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3801 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3802 }
3803
3804 /* Disable the Peripheral */
3805 __HAL_TIM_DISABLE(htim);
3806
3807 /* Set the TIM channel(s) state */
3808 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3809 {
3810 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3811 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3812 }
3813 else
3814 {
3815 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3817 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3819 }
3820
3821 /* Return function status */
3822 return HAL_OK;
3823 }
3824
3825 /**
3826 * @}
3827 */
3828 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3829 * @brief TIM IRQ handler management
3830 *
3831 @verbatim
3832 ==============================================================================
3833 ##### IRQ handler management #####
3834 ==============================================================================
3835 [..]
3836 This section provides Timer IRQ handler function.
3837
3838 @endverbatim
3839 * @{
3840 */
3841 /**
3842 * @brief This function handles TIM interrupts requests.
3843 * @param htim TIM handle
3844 * @retval None
3845 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3846 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3847 {
3848 uint32_t itsource = htim->Instance->DIER;
3849 uint32_t itflag = htim->Instance->SR;
3850
3851 /* Capture compare 1 event */
3852 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3853 {
3854 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3855 {
3856 {
3857 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3858 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3859
3860 /* Input capture event */
3861 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3862 {
3863 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3864 htim->IC_CaptureCallback(htim);
3865 #else
3866 HAL_TIM_IC_CaptureCallback(htim);
3867 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3868 }
3869 /* Output compare event */
3870 else
3871 {
3872 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3873 htim->OC_DelayElapsedCallback(htim);
3874 htim->PWM_PulseFinishedCallback(htim);
3875 #else
3876 HAL_TIM_OC_DelayElapsedCallback(htim);
3877 HAL_TIM_PWM_PulseFinishedCallback(htim);
3878 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3879 }
3880 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3881 }
3882 }
3883 }
3884 /* Capture compare 2 event */
3885 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3886 {
3887 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3888 {
3889 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3890 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3891 /* Input capture event */
3892 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3893 {
3894 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3895 htim->IC_CaptureCallback(htim);
3896 #else
3897 HAL_TIM_IC_CaptureCallback(htim);
3898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3899 }
3900 /* Output compare event */
3901 else
3902 {
3903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3904 htim->OC_DelayElapsedCallback(htim);
3905 htim->PWM_PulseFinishedCallback(htim);
3906 #else
3907 HAL_TIM_OC_DelayElapsedCallback(htim);
3908 HAL_TIM_PWM_PulseFinishedCallback(htim);
3909 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3910 }
3911 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3912 }
3913 }
3914 /* Capture compare 3 event */
3915 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3916 {
3917 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3918 {
3919 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3920 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3921 /* Input capture event */
3922 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3923 {
3924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3925 htim->IC_CaptureCallback(htim);
3926 #else
3927 HAL_TIM_IC_CaptureCallback(htim);
3928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3929 }
3930 /* Output compare event */
3931 else
3932 {
3933 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3934 htim->OC_DelayElapsedCallback(htim);
3935 htim->PWM_PulseFinishedCallback(htim);
3936 #else
3937 HAL_TIM_OC_DelayElapsedCallback(htim);
3938 HAL_TIM_PWM_PulseFinishedCallback(htim);
3939 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3940 }
3941 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3942 }
3943 }
3944 /* Capture compare 4 event */
3945 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3946 {
3947 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3948 {
3949 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3950 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3951 /* Input capture event */
3952 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3953 {
3954 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3955 htim->IC_CaptureCallback(htim);
3956 #else
3957 HAL_TIM_IC_CaptureCallback(htim);
3958 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3959 }
3960 /* Output compare event */
3961 else
3962 {
3963 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3964 htim->OC_DelayElapsedCallback(htim);
3965 htim->PWM_PulseFinishedCallback(htim);
3966 #else
3967 HAL_TIM_OC_DelayElapsedCallback(htim);
3968 HAL_TIM_PWM_PulseFinishedCallback(htim);
3969 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3970 }
3971 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3972 }
3973 }
3974 /* TIM Update event */
3975 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3976 {
3977 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3978 {
3979 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3980 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3981 htim->PeriodElapsedCallback(htim);
3982 #else
3983 HAL_TIM_PeriodElapsedCallback(htim);
3984 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3985 }
3986 }
3987 /* TIM Break input event */
3988 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
3989 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
3990 {
3991 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3992 {
3993 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
3994 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3995 htim->BreakCallback(htim);
3996 #else
3997 HAL_TIMEx_BreakCallback(htim);
3998 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3999 }
4000 }
4001 /* TIM Break2 input event */
4002 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
4003 {
4004 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
4005 {
4006 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
4007 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4008 htim->Break2Callback(htim);
4009 #else
4010 HAL_TIMEx_Break2Callback(htim);
4011 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4012 }
4013 }
4014 /* TIM Trigger detection event */
4015 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4016 {
4017 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4018 {
4019 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
4020 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4021 htim->TriggerCallback(htim);
4022 #else
4023 HAL_TIM_TriggerCallback(htim);
4024 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4025 }
4026 }
4027 /* TIM commutation event */
4028 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4029 {
4030 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4031 {
4032 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
4033 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4034 htim->CommutationCallback(htim);
4035 #else
4036 HAL_TIMEx_CommutCallback(htim);
4037 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4038 }
4039 }
4040 /* TIM Encoder index event */
4041 if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
4042 {
4043 if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
4044 {
4045 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
4046 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4047 htim->EncoderIndexCallback(htim);
4048 #else
4049 HAL_TIMEx_EncoderIndexCallback(htim);
4050 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4051 }
4052 }
4053 /* TIM Direction change event */
4054 if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
4055 {
4056 if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
4057 {
4058 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
4059 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4060 htim->DirectionChangeCallback(htim);
4061 #else
4062 HAL_TIMEx_DirectionChangeCallback(htim);
4063 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4064 }
4065 }
4066 /* TIM Index error event */
4067 if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
4068 {
4069 if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
4070 {
4071 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
4072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4073 htim->IndexErrorCallback(htim);
4074 #else
4075 HAL_TIMEx_IndexErrorCallback(htim);
4076 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4077 }
4078 }
4079 /* TIM Transition error event */
4080 if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
4081 {
4082 if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
4083 {
4084 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
4085 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4086 htim->TransitionErrorCallback(htim);
4087 #else
4088 HAL_TIMEx_TransitionErrorCallback(htim);
4089 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4090 }
4091 }
4092 }
4093
4094 /**
4095 * @}
4096 */
4097
4098 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4099 * @brief TIM Peripheral Control functions
4100 *
4101 @verbatim
4102 ==============================================================================
4103 ##### Peripheral Control functions #####
4104 ==============================================================================
4105 [..]
4106 This section provides functions allowing to:
4107 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4108 (+) Configure External Clock source.
4109 (+) Configure Complementary channels, break features and dead time.
4110 (+) Configure Master and the Slave synchronization.
4111 (+) Configure the DMA Burst Mode.
4112
4113 @endverbatim
4114 * @{
4115 */
4116
4117 /**
4118 * @brief Initializes the TIM Output Compare Channels according to the specified
4119 * parameters in the TIM_OC_InitTypeDef.
4120 * @param htim TIM Output Compare handle
4121 * @param sConfig TIM Output Compare configuration structure
4122 * @param Channel TIM Channels to configure
4123 * This parameter can be one of the following values:
4124 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4125 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4126 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4127 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4128 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4129 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4130 * @retval HAL status
4131 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4132 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4133 const TIM_OC_InitTypeDef *sConfig,
4134 uint32_t Channel)
4135 {
4136 HAL_StatusTypeDef status = HAL_OK;
4137
4138 /* Check the parameters */
4139 assert_param(IS_TIM_CHANNELS(Channel));
4140 assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
4141 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4142
4143 /* Process Locked */
4144 __HAL_LOCK(htim);
4145
4146 switch (Channel)
4147 {
4148 case TIM_CHANNEL_1:
4149 {
4150 /* Check the parameters */
4151 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4152
4153 /* Configure the TIM Channel 1 in Output Compare */
4154 TIM_OC1_SetConfig(htim->Instance, sConfig);
4155 break;
4156 }
4157
4158 case TIM_CHANNEL_2:
4159 {
4160 /* Check the parameters */
4161 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4162
4163 /* Configure the TIM Channel 2 in Output Compare */
4164 TIM_OC2_SetConfig(htim->Instance, sConfig);
4165 break;
4166 }
4167
4168 case TIM_CHANNEL_3:
4169 {
4170 /* Check the parameters */
4171 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4172
4173 /* Configure the TIM Channel 3 in Output Compare */
4174 TIM_OC3_SetConfig(htim->Instance, sConfig);
4175 break;
4176 }
4177
4178 case TIM_CHANNEL_4:
4179 {
4180 /* Check the parameters */
4181 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4182
4183 /* Configure the TIM Channel 4 in Output Compare */
4184 TIM_OC4_SetConfig(htim->Instance, sConfig);
4185 break;
4186 }
4187
4188 case TIM_CHANNEL_5:
4189 {
4190 /* Check the parameters */
4191 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4192
4193 /* Configure the TIM Channel 5 in Output Compare */
4194 TIM_OC5_SetConfig(htim->Instance, sConfig);
4195 break;
4196 }
4197
4198 case TIM_CHANNEL_6:
4199 {
4200 /* Check the parameters */
4201 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4202
4203 /* Configure the TIM Channel 6 in Output Compare */
4204 TIM_OC6_SetConfig(htim->Instance, sConfig);
4205 break;
4206 }
4207
4208 default:
4209 status = HAL_ERROR;
4210 break;
4211 }
4212
4213 __HAL_UNLOCK(htim);
4214
4215 return status;
4216 }
4217
4218 /**
4219 * @brief Initializes the TIM Input Capture Channels according to the specified
4220 * parameters in the TIM_IC_InitTypeDef.
4221 * @param htim TIM IC handle
4222 * @param sConfig TIM Input Capture configuration structure
4223 * @param Channel TIM Channel to configure
4224 * This parameter can be one of the following values:
4225 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4226 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4227 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4228 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4229 * @retval HAL status
4230 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4231 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4232 {
4233 HAL_StatusTypeDef status = HAL_OK;
4234
4235 /* Check the parameters */
4236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4237 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4238 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4239 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4240 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4241
4242 /* Process Locked */
4243 __HAL_LOCK(htim);
4244
4245 if (Channel == TIM_CHANNEL_1)
4246 {
4247 /* TI1 Configuration */
4248 TIM_TI1_SetConfig(htim->Instance,
4249 sConfig->ICPolarity,
4250 sConfig->ICSelection,
4251 sConfig->ICFilter);
4252
4253 /* Reset the IC1PSC Bits */
4254 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4255
4256 /* Set the IC1PSC value */
4257 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4258 }
4259 else if (Channel == TIM_CHANNEL_2)
4260 {
4261 /* TI2 Configuration */
4262 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4263
4264 TIM_TI2_SetConfig(htim->Instance,
4265 sConfig->ICPolarity,
4266 sConfig->ICSelection,
4267 sConfig->ICFilter);
4268
4269 /* Reset the IC2PSC Bits */
4270 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4271
4272 /* Set the IC2PSC value */
4273 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4274 }
4275 else if (Channel == TIM_CHANNEL_3)
4276 {
4277 /* TI3 Configuration */
4278 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4279
4280 TIM_TI3_SetConfig(htim->Instance,
4281 sConfig->ICPolarity,
4282 sConfig->ICSelection,
4283 sConfig->ICFilter);
4284
4285 /* Reset the IC3PSC Bits */
4286 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4287
4288 /* Set the IC3PSC value */
4289 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4290 }
4291 else if (Channel == TIM_CHANNEL_4)
4292 {
4293 /* TI4 Configuration */
4294 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4295
4296 TIM_TI4_SetConfig(htim->Instance,
4297 sConfig->ICPolarity,
4298 sConfig->ICSelection,
4299 sConfig->ICFilter);
4300
4301 /* Reset the IC4PSC Bits */
4302 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4303
4304 /* Set the IC4PSC value */
4305 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4306 }
4307 else
4308 {
4309 status = HAL_ERROR;
4310 }
4311
4312 __HAL_UNLOCK(htim);
4313
4314 return status;
4315 }
4316
4317 /**
4318 * @brief Initializes the TIM PWM channels according to the specified
4319 * parameters in the TIM_OC_InitTypeDef.
4320 * @param htim TIM PWM handle
4321 * @param sConfig TIM PWM configuration structure
4322 * @param Channel TIM Channels to be configured
4323 * This parameter can be one of the following values:
4324 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4325 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4326 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4327 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4328 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4329 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4330 * @retval HAL status
4331 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4332 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4333 const TIM_OC_InitTypeDef *sConfig,
4334 uint32_t Channel)
4335 {
4336 HAL_StatusTypeDef status = HAL_OK;
4337
4338 /* Check the parameters */
4339 assert_param(IS_TIM_CHANNELS(Channel));
4340 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4341 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4342 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4343
4344 /* Process Locked */
4345 __HAL_LOCK(htim);
4346
4347 switch (Channel)
4348 {
4349 case TIM_CHANNEL_1:
4350 {
4351 /* Check the parameters */
4352 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4353
4354 /* Configure the Channel 1 in PWM mode */
4355 TIM_OC1_SetConfig(htim->Instance, sConfig);
4356
4357 /* Set the Preload enable bit for channel1 */
4358 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4359
4360 /* Configure the Output Fast mode */
4361 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4362 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4363 break;
4364 }
4365
4366 case TIM_CHANNEL_2:
4367 {
4368 /* Check the parameters */
4369 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4370
4371 /* Configure the Channel 2 in PWM mode */
4372 TIM_OC2_SetConfig(htim->Instance, sConfig);
4373
4374 /* Set the Preload enable bit for channel2 */
4375 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4376
4377 /* Configure the Output Fast mode */
4378 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4379 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4380 break;
4381 }
4382
4383 case TIM_CHANNEL_3:
4384 {
4385 /* Check the parameters */
4386 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4387
4388 /* Configure the Channel 3 in PWM mode */
4389 TIM_OC3_SetConfig(htim->Instance, sConfig);
4390
4391 /* Set the Preload enable bit for channel3 */
4392 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4393
4394 /* Configure the Output Fast mode */
4395 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4396 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4397 break;
4398 }
4399
4400 case TIM_CHANNEL_4:
4401 {
4402 /* Check the parameters */
4403 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4404
4405 /* Configure the Channel 4 in PWM mode */
4406 TIM_OC4_SetConfig(htim->Instance, sConfig);
4407
4408 /* Set the Preload enable bit for channel4 */
4409 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4410
4411 /* Configure the Output Fast mode */
4412 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4413 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4414 break;
4415 }
4416
4417 case TIM_CHANNEL_5:
4418 {
4419 /* Check the parameters */
4420 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4421
4422 /* Configure the Channel 5 in PWM mode */
4423 TIM_OC5_SetConfig(htim->Instance, sConfig);
4424
4425 /* Set the Preload enable bit for channel5*/
4426 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4427
4428 /* Configure the Output Fast mode */
4429 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4430 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4431 break;
4432 }
4433
4434 case TIM_CHANNEL_6:
4435 {
4436 /* Check the parameters */
4437 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4438
4439 /* Configure the Channel 6 in PWM mode */
4440 TIM_OC6_SetConfig(htim->Instance, sConfig);
4441
4442 /* Set the Preload enable bit for channel6 */
4443 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4444
4445 /* Configure the Output Fast mode */
4446 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4447 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4448 break;
4449 }
4450
4451 default:
4452 status = HAL_ERROR;
4453 break;
4454 }
4455
4456 __HAL_UNLOCK(htim);
4457
4458 return status;
4459 }
4460
4461 /**
4462 * @brief Initializes the TIM One Pulse Channels according to the specified
4463 * parameters in the TIM_OnePulse_InitTypeDef.
4464 * @param htim TIM One Pulse handle
4465 * @param sConfig TIM One Pulse configuration structure
4466 * @param OutputChannel TIM output channel to configure
4467 * This parameter can be one of the following values:
4468 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4469 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4470 * @param InputChannel TIM input Channel to configure
4471 * This parameter can be one of the following values:
4472 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4473 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4474 * @note To output a waveform with a minimum delay user can enable the fast
4475 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4476 * output is forced in response to the edge detection on TIx input,
4477 * without taking in account the comparison.
4478 * @retval HAL status
4479 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4480 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4481 uint32_t OutputChannel, uint32_t InputChannel)
4482 {
4483 HAL_StatusTypeDef status = HAL_OK;
4484 TIM_OC_InitTypeDef temp1;
4485
4486 /* Check the parameters */
4487 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4488 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4489
4490 if (OutputChannel != InputChannel)
4491 {
4492 /* Process Locked */
4493 __HAL_LOCK(htim);
4494
4495 htim->State = HAL_TIM_STATE_BUSY;
4496
4497 /* Extract the Output compare configuration from sConfig structure */
4498 temp1.OCMode = sConfig->OCMode;
4499 temp1.Pulse = sConfig->Pulse;
4500 temp1.OCPolarity = sConfig->OCPolarity;
4501 temp1.OCNPolarity = sConfig->OCNPolarity;
4502 temp1.OCIdleState = sConfig->OCIdleState;
4503 temp1.OCNIdleState = sConfig->OCNIdleState;
4504
4505 switch (OutputChannel)
4506 {
4507 case TIM_CHANNEL_1:
4508 {
4509 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4510
4511 TIM_OC1_SetConfig(htim->Instance, &temp1);
4512 break;
4513 }
4514
4515 case TIM_CHANNEL_2:
4516 {
4517 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4518
4519 TIM_OC2_SetConfig(htim->Instance, &temp1);
4520 break;
4521 }
4522
4523 default:
4524 status = HAL_ERROR;
4525 break;
4526 }
4527
4528 if (status == HAL_OK)
4529 {
4530 switch (InputChannel)
4531 {
4532 case TIM_CHANNEL_1:
4533 {
4534 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4535
4536 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4537 sConfig->ICSelection, sConfig->ICFilter);
4538
4539 /* Reset the IC1PSC Bits */
4540 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4541
4542 /* Select the Trigger source */
4543 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4544 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4545
4546 /* Select the Slave Mode */
4547 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4548 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4549 break;
4550 }
4551
4552 case TIM_CHANNEL_2:
4553 {
4554 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4555
4556 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4557 sConfig->ICSelection, sConfig->ICFilter);
4558
4559 /* Reset the IC2PSC Bits */
4560 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4561
4562 /* Select the Trigger source */
4563 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4564 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4565
4566 /* Select the Slave Mode */
4567 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4568 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4569 break;
4570 }
4571
4572 default:
4573 status = HAL_ERROR;
4574 break;
4575 }
4576 }
4577
4578 htim->State = HAL_TIM_STATE_READY;
4579
4580 __HAL_UNLOCK(htim);
4581
4582 return status;
4583 }
4584 else
4585 {
4586 return HAL_ERROR;
4587 }
4588 }
4589
4590 /**
4591 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4592 * @param htim TIM handle
4593 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4594 * This parameter can be one of the following values:
4595 * @arg TIM_DMABASE_CR1
4596 * @arg TIM_DMABASE_CR2
4597 * @arg TIM_DMABASE_SMCR
4598 * @arg TIM_DMABASE_DIER
4599 * @arg TIM_DMABASE_SR
4600 * @arg TIM_DMABASE_EGR
4601 * @arg TIM_DMABASE_CCMR1
4602 * @arg TIM_DMABASE_CCMR2
4603 * @arg TIM_DMABASE_CCER
4604 * @arg TIM_DMABASE_CNT
4605 * @arg TIM_DMABASE_PSC
4606 * @arg TIM_DMABASE_ARR
4607 * @arg TIM_DMABASE_RCR
4608 * @arg TIM_DMABASE_CCR1
4609 * @arg TIM_DMABASE_CCR2
4610 * @arg TIM_DMABASE_CCR3
4611 * @arg TIM_DMABASE_CCR4
4612 * @arg TIM_DMABASE_BDTR
4613 * @arg TIM_DMABASE_CCMR3
4614 * @arg TIM_DMABASE_CCR5
4615 * @arg TIM_DMABASE_CCR6
4616 * @arg TIM_DMABASE_DTR2
4617 * @arg TIM_DMABASE_ECR
4618 * @arg TIM_DMABASE_TISEL
4619 * @arg TIM_DMABASE_AF1
4620 * @arg TIM_DMABASE_AF2
4621 * @arg TIM_DMABASE_OR1
4622 * @param BurstRequestSrc TIM DMA Request sources
4623 * This parameter can be one of the following values:
4624 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4625 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4626 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4627 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4628 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4629 * @arg TIM_DMA_COM: TIM Commutation DMA source
4630 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4631 * @param BurstBuffer The Buffer address.
4632 * @param BurstLength DMA Burst length. This parameter can be one value
4633 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4634 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4635 * @retval HAL status
4636 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4637 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4638 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4639 uint32_t BurstLength)
4640 {
4641 HAL_StatusTypeDef status = HAL_OK;
4642 uint32_t BlockDataLength = 0;
4643 uint32_t data_width;
4644 const DMA_HandleTypeDef *hdma = NULL;
4645
4646 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4647
4648 switch (BurstRequestSrc)
4649 {
4650 case TIM_DMA_UPDATE:
4651 {
4652 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
4653 break;
4654 }
4655 case TIM_DMA_CC1:
4656 {
4657 hdma = htim->hdma[TIM_DMA_ID_CC1];
4658 break;
4659 }
4660 case TIM_DMA_CC2:
4661 {
4662 hdma = htim->hdma[TIM_DMA_ID_CC2];
4663 break;
4664 }
4665 case TIM_DMA_CC3:
4666 {
4667 hdma = htim->hdma[TIM_DMA_ID_CC3];
4668 break;
4669 }
4670 case TIM_DMA_CC4:
4671 {
4672 hdma = htim->hdma[TIM_DMA_ID_CC4];
4673 break;
4674 }
4675 case TIM_DMA_COM:
4676 {
4677 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
4678 break;
4679 }
4680 case TIM_DMA_TRIGGER:
4681 {
4682 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
4683 break;
4684 }
4685 default:
4686 status = HAL_ERROR;
4687 break;
4688 }
4689
4690 if (hdma != NULL)
4691 {
4692
4693 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
4694 && (hdma->LinkedListQueue->Head != 0U))
4695 {
4696 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
4697 }
4698 else
4699 {
4700 data_width = hdma->Init.SrcDataWidth;
4701 }
4702
4703 switch (data_width)
4704 {
4705 case DMA_SRC_DATAWIDTH_BYTE:
4706 {
4707 BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
4708 break;
4709 }
4710 case DMA_SRC_DATAWIDTH_HALFWORD:
4711 {
4712 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
4713 break;
4714 }
4715 case DMA_SRC_DATAWIDTH_WORD:
4716 {
4717 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
4718 break;
4719 }
4720 default:
4721 status = HAL_ERROR;
4722 break;
4723 }
4724
4725 if (status == HAL_OK)
4726 {
4727 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4728 BlockDataLength);
4729 }
4730 }
4731
4732
4733 return status;
4734 }
4735
4736 /**
4737 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4738 * @param htim TIM handle
4739 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4740 * This parameter can be one of the following values:
4741 * @arg TIM_DMABASE_CR1
4742 * @arg TIM_DMABASE_CR2
4743 * @arg TIM_DMABASE_SMCR
4744 * @arg TIM_DMABASE_DIER
4745 * @arg TIM_DMABASE_SR
4746 * @arg TIM_DMABASE_EGR
4747 * @arg TIM_DMABASE_CCMR1
4748 * @arg TIM_DMABASE_CCMR2
4749 * @arg TIM_DMABASE_CCER
4750 * @arg TIM_DMABASE_CNT
4751 * @arg TIM_DMABASE_PSC
4752 * @arg TIM_DMABASE_ARR
4753 * @arg TIM_DMABASE_RCR
4754 * @arg TIM_DMABASE_CCR1
4755 * @arg TIM_DMABASE_CCR2
4756 * @arg TIM_DMABASE_CCR3
4757 * @arg TIM_DMABASE_CCR4
4758 * @arg TIM_DMABASE_BDTR
4759 * @arg TIM_DMABASE_CCMR3
4760 * @arg TIM_DMABASE_CCR5
4761 * @arg TIM_DMABASE_CCR6
4762 * @arg TIM_DMABASE_DTR2
4763 * @arg TIM_DMABASE_ECR
4764 * @arg TIM_DMABASE_TISEL
4765 * @arg TIM_DMABASE_AF1
4766 * @arg TIM_DMABASE_AF2
4767 * @arg TIM_DMABASE_OR1
4768 * @param BurstRequestSrc TIM DMA Request sources
4769 * This parameter can be one of the following values:
4770 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4771 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4772 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4773 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4774 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4775 * @arg TIM_DMA_COM: TIM Commutation DMA source
4776 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4777 * @param BurstBuffer The Buffer address.
4778 * @param BurstLength DMA Burst length. This parameter can be one value
4779 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4780 * @param DataLength Data length. This parameter can be one value
4781 * between 1 and 0xFFFF.
4782 * @retval HAL status
4783 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4784 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4785 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4786 uint32_t BurstLength, uint32_t DataLength)
4787 {
4788 HAL_StatusTypeDef status = HAL_OK;
4789 uint32_t tmpDBSS = 0;
4790
4791 /* Check the parameters */
4792 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4793 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4794 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4795 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4796 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4797
4798 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4799 {
4800 return HAL_BUSY;
4801 }
4802 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4803 {
4804 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4805 {
4806 return HAL_ERROR;
4807 }
4808 else
4809 {
4810 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4811 }
4812 }
4813 else
4814 {
4815 /* nothing to do */
4816 }
4817
4818 switch (BurstRequestSrc)
4819 {
4820 case TIM_DMA_UPDATE:
4821 {
4822 /* Set the DMA Period elapsed callbacks */
4823 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4824 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4825
4826 /* Set the DMA error callback */
4827 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4828
4829 /* Enable the DMA channel */
4830 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4831 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4832 {
4833 /* Return error status */
4834 return HAL_ERROR;
4835 }
4836 /* Configure the DMA Burst Source Selection */
4837 tmpDBSS = TIM_DCR_DBSS_0;
4838 break;
4839 }
4840 case TIM_DMA_CC1:
4841 {
4842 /* Set the DMA compare callbacks */
4843 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4844 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4845
4846 /* Set the DMA error callback */
4847 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4848
4849 /* Enable the DMA channel */
4850 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4851 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4852 {
4853 /* Return error status */
4854 return HAL_ERROR;
4855 }
4856 /* Configure the DMA Burst Source Selection */
4857 tmpDBSS = TIM_DCR_DBSS_1;
4858 break;
4859 }
4860 case TIM_DMA_CC2:
4861 {
4862 /* Set the DMA compare callbacks */
4863 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4864 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4865
4866 /* Set the DMA error callback */
4867 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4868
4869 /* Enable the DMA channel */
4870 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4871 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4872 {
4873 /* Return error status */
4874 return HAL_ERROR;
4875 }
4876 /* Configure the DMA Burst Source Selection */
4877 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4878 break;
4879 }
4880 case TIM_DMA_CC3:
4881 {
4882 /* Set the DMA compare callbacks */
4883 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4884 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4885
4886 /* Set the DMA error callback */
4887 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4888
4889 /* Enable the DMA channel */
4890 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4891 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4892 {
4893 /* Return error status */
4894 return HAL_ERROR;
4895 }
4896 /* Configure the DMA Burst Source Selection */
4897 tmpDBSS = TIM_DCR_DBSS_2;
4898 break;
4899 }
4900 case TIM_DMA_CC4:
4901 {
4902 /* Set the DMA compare callbacks */
4903 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4904 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4905
4906 /* Set the DMA error callback */
4907 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4908
4909 /* Enable the DMA channel */
4910 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4911 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4912 {
4913 /* Return error status */
4914 return HAL_ERROR;
4915 }
4916 /* Configure the DMA Burst Source Selection */
4917 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
4918 break;
4919 }
4920 case TIM_DMA_COM:
4921 {
4922 /* Set the DMA commutation callbacks */
4923 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4924 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4925
4926 /* Set the DMA error callback */
4927 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4928
4929 /* Enable the DMA channel */
4930 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4931 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4932 {
4933 /* Return error status */
4934 return HAL_ERROR;
4935 }
4936 /* Configure the DMA Burst Source Selection */
4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
4938 break;
4939 }
4940 case TIM_DMA_TRIGGER:
4941 {
4942 /* Set the DMA trigger callbacks */
4943 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4944 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4945
4946 /* Set the DMA error callback */
4947 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4948
4949 /* Enable the DMA channel */
4950 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4951 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4952 {
4953 /* Return error status */
4954 return HAL_ERROR;
4955 }
4956 /* Configure the DMA Burst Source Selection */
4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4958 break;
4959 }
4960 default:
4961 status = HAL_ERROR;
4962 break;
4963 }
4964
4965 if (status == HAL_OK)
4966 {
4967 /* Configure the DMA Burst Mode */
4968 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
4969 /* Enable the TIM DMA Request */
4970 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4971 }
4972
4973 /* Return function status */
4974 return status;
4975 }
4976
4977 /**
4978 * @brief Stops the TIM DMA Burst mode
4979 * @param htim TIM handle
4980 * @param BurstRequestSrc TIM DMA Request sources to disable
4981 * @retval HAL status
4982 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4983 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4984 {
4985 HAL_StatusTypeDef status = HAL_OK;
4986
4987 /* Check the parameters */
4988 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4989
4990 /* Abort the DMA transfer (at least disable the DMA channel) */
4991 switch (BurstRequestSrc)
4992 {
4993 case TIM_DMA_UPDATE:
4994 {
4995 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4996 break;
4997 }
4998 case TIM_DMA_CC1:
4999 {
5000 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5001 break;
5002 }
5003 case TIM_DMA_CC2:
5004 {
5005 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5006 break;
5007 }
5008 case TIM_DMA_CC3:
5009 {
5010 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5011 break;
5012 }
5013 case TIM_DMA_CC4:
5014 {
5015 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5016 break;
5017 }
5018 case TIM_DMA_COM:
5019 {
5020 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5021 break;
5022 }
5023 case TIM_DMA_TRIGGER:
5024 {
5025 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5026 break;
5027 }
5028 default:
5029 status = HAL_ERROR;
5030 break;
5031 }
5032
5033 if (status == HAL_OK)
5034 {
5035 /* Disable the TIM Update DMA request */
5036 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5037
5038 /* Change the DMA burst operation state */
5039 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5040 }
5041
5042 /* Return function status */
5043 return status;
5044 }
5045
5046 /**
5047 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5048 * @param htim TIM handle
5049 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5050 * This parameter can be one of the following values:
5051 * @arg TIM_DMABASE_CR1
5052 * @arg TIM_DMABASE_CR2
5053 * @arg TIM_DMABASE_SMCR
5054 * @arg TIM_DMABASE_DIER
5055 * @arg TIM_DMABASE_SR
5056 * @arg TIM_DMABASE_EGR
5057 * @arg TIM_DMABASE_CCMR1
5058 * @arg TIM_DMABASE_CCMR2
5059 * @arg TIM_DMABASE_CCER
5060 * @arg TIM_DMABASE_CNT
5061 * @arg TIM_DMABASE_PSC
5062 * @arg TIM_DMABASE_ARR
5063 * @arg TIM_DMABASE_RCR
5064 * @arg TIM_DMABASE_CCR1
5065 * @arg TIM_DMABASE_CCR2
5066 * @arg TIM_DMABASE_CCR3
5067 * @arg TIM_DMABASE_CCR4
5068 * @arg TIM_DMABASE_BDTR
5069 * @arg TIM_DMABASE_CCMR3
5070 * @arg TIM_DMABASE_CCR5
5071 * @arg TIM_DMABASE_CCR6
5072 * @arg TIM_DMABASE_DTR2
5073 * @arg TIM_DMABASE_ECR
5074 * @arg TIM_DMABASE_TISEL
5075 * @arg TIM_DMABASE_AF1
5076 * @arg TIM_DMABASE_AF2
5077 * @arg TIM_DMABASE_OR1
5078 * @param BurstRequestSrc TIM DMA Request sources
5079 * This parameter can be one of the following values:
5080 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5081 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5082 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5083 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5084 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5085 * @arg TIM_DMA_COM: TIM Commutation DMA source
5086 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5087 * @param BurstBuffer The Buffer address.
5088 * @param BurstLength DMA Burst length. This parameter can be one value
5089 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5090 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
5091 * @retval HAL status
5092 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)5093 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5094 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
5095 {
5096 HAL_StatusTypeDef status = HAL_OK;
5097 uint32_t BlockDataLength = 0;
5098 uint32_t data_width;
5099 const DMA_HandleTypeDef *hdma = NULL;
5100
5101 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5102
5103 switch (BurstRequestSrc)
5104 {
5105 case TIM_DMA_UPDATE:
5106 {
5107 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
5108 break;
5109 }
5110 case TIM_DMA_CC1:
5111 {
5112 hdma = htim->hdma[TIM_DMA_ID_CC1];
5113 break;
5114 }
5115 case TIM_DMA_CC2:
5116 {
5117 hdma = htim->hdma[TIM_DMA_ID_CC2];
5118 break;
5119 }
5120 case TIM_DMA_CC3:
5121 {
5122 hdma = htim->hdma[TIM_DMA_ID_CC3];
5123 break;
5124 }
5125 case TIM_DMA_CC4:
5126 {
5127 hdma = htim->hdma[TIM_DMA_ID_CC4];
5128 break;
5129 }
5130 case TIM_DMA_COM:
5131 {
5132 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
5133 break;
5134 }
5135 case TIM_DMA_TRIGGER:
5136 {
5137 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
5138 break;
5139 }
5140 default:
5141 status = HAL_ERROR;
5142 break;
5143 }
5144
5145 if (hdma != NULL)
5146 {
5147
5148 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
5149 && (hdma->LinkedListQueue->Head != 0U))
5150 {
5151 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
5152 }
5153 else
5154 {
5155 data_width = hdma->Init.SrcDataWidth;
5156 }
5157
5158 switch (data_width)
5159
5160 {
5161 case DMA_SRC_DATAWIDTH_BYTE:
5162 {
5163 BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
5164 break;
5165 }
5166 case DMA_SRC_DATAWIDTH_HALFWORD:
5167 {
5168 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
5169 break;
5170 }
5171 case DMA_SRC_DATAWIDTH_WORD:
5172 {
5173 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
5174 break;
5175 }
5176 default:
5177 status = HAL_ERROR;
5178 break;
5179 }
5180
5181 if (status == HAL_OK)
5182 {
5183 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
5184 BlockDataLength);
5185 }
5186 }
5187
5188 return status;
5189 }
5190
5191 /**
5192 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5193 * @param htim TIM handle
5194 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5195 * This parameter can be one of the following values:
5196 * @arg TIM_DMABASE_CR1
5197 * @arg TIM_DMABASE_CR2
5198 * @arg TIM_DMABASE_SMCR
5199 * @arg TIM_DMABASE_DIER
5200 * @arg TIM_DMABASE_SR
5201 * @arg TIM_DMABASE_EGR
5202 * @arg TIM_DMABASE_CCMR1
5203 * @arg TIM_DMABASE_CCMR2
5204 * @arg TIM_DMABASE_CCER
5205 * @arg TIM_DMABASE_CNT
5206 * @arg TIM_DMABASE_PSC
5207 * @arg TIM_DMABASE_ARR
5208 * @arg TIM_DMABASE_RCR
5209 * @arg TIM_DMABASE_CCR1
5210 * @arg TIM_DMABASE_CCR2
5211 * @arg TIM_DMABASE_CCR3
5212 * @arg TIM_DMABASE_CCR4
5213 * @arg TIM_DMABASE_BDTR
5214 * @arg TIM_DMABASE_CCMR3
5215 * @arg TIM_DMABASE_CCR5
5216 * @arg TIM_DMABASE_CCR6
5217 * @arg TIM_DMABASE_DTR2
5218 * @arg TIM_DMABASE_ECR
5219 * @arg TIM_DMABASE_TISEL
5220 * @arg TIM_DMABASE_AF1
5221 * @arg TIM_DMABASE_AF2
5222 * @arg TIM_DMABASE_OR1
5223 * @param BurstRequestSrc TIM DMA Request sources
5224 * This parameter can be one of the following values:
5225 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5226 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5227 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5228 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5229 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5230 * @arg TIM_DMA_COM: TIM Commutation DMA source
5231 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5232 * @param BurstBuffer The Buffer address.
5233 * @param BurstLength DMA Burst length. This parameter can be one value
5234 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5235 * @param DataLength Data length. This parameter can be one value
5236 * between 1 and 0xFFFF.
5237 * @retval HAL status
5238 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)5239 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5240 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
5241 uint32_t BurstLength, uint32_t DataLength)
5242 {
5243 HAL_StatusTypeDef status = HAL_OK;
5244 uint32_t tmpDBSS = 0;
5245
5246 /* Check the parameters */
5247 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5248 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5249 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5250 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5251 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5252
5253 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5254 {
5255 return HAL_BUSY;
5256 }
5257 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5258 {
5259 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5260 {
5261 return HAL_ERROR;
5262 }
5263 else
5264 {
5265 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5266 }
5267 }
5268 else
5269 {
5270 /* nothing to do */
5271 }
5272 switch (BurstRequestSrc)
5273 {
5274 case TIM_DMA_UPDATE:
5275 {
5276 /* Set the DMA Period elapsed callbacks */
5277 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5278 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5279
5280 /* Set the DMA error callback */
5281 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5282
5283 /* Enable the DMA channel */
5284 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5285 DataLength) != HAL_OK)
5286 {
5287 /* Return error status */
5288 return HAL_ERROR;
5289 }
5290 /* Configure the DMA Burst Source Selection */
5291 tmpDBSS = TIM_DCR_DBSS_0;
5292 break;
5293 }
5294 case TIM_DMA_CC1:
5295 {
5296 /* Set the DMA capture callbacks */
5297 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5298 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5299
5300 /* Set the DMA error callback */
5301 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5302
5303 /* Enable the DMA channel */
5304 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5305 DataLength) != HAL_OK)
5306 {
5307 /* Return error status */
5308 return HAL_ERROR;
5309 }
5310 /* Configure the DMA Burst Source Selection */
5311 tmpDBSS = TIM_DCR_DBSS_1;
5312 break;
5313 }
5314 case TIM_DMA_CC2:
5315 {
5316 /* Set the DMA capture callbacks */
5317 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5318 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5319
5320 /* Set the DMA error callback */
5321 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5322
5323 /* Enable the DMA channel */
5324 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5325 DataLength) != HAL_OK)
5326 {
5327 /* Return error status */
5328 return HAL_ERROR;
5329 }
5330 /* Configure the DMA Burst Source Selection */
5331 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5332 break;
5333 }
5334 case TIM_DMA_CC3:
5335 {
5336 /* Set the DMA capture callbacks */
5337 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5338 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5339
5340 /* Set the DMA error callback */
5341 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5342
5343 /* Enable the DMA channel */
5344 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5345 DataLength) != HAL_OK)
5346 {
5347 /* Return error status */
5348 return HAL_ERROR;
5349 }
5350 /* Configure the DMA Burst Source Selection */
5351 tmpDBSS = TIM_DCR_DBSS_2;
5352 break;
5353 }
5354 case TIM_DMA_CC4:
5355 {
5356 /* Set the DMA capture callbacks */
5357 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5358 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5359
5360 /* Set the DMA error callback */
5361 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5362
5363 /* Enable the DMA channel */
5364 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5365 DataLength) != HAL_OK)
5366 {
5367 /* Return error status */
5368 return HAL_ERROR;
5369 }
5370 /* Configure the DMA Burst Source Selection */
5371 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
5372 break;
5373 }
5374 case TIM_DMA_COM:
5375 {
5376 /* Set the DMA commutation callbacks */
5377 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5378 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5379
5380 /* Set the DMA error callback */
5381 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5382
5383 /* Enable the DMA channel */
5384 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5385 DataLength) != HAL_OK)
5386 {
5387 /* Return error status */
5388 return HAL_ERROR;
5389 }
5390 /* Configure the DMA Burst Source Selection */
5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
5392 break;
5393 }
5394 case TIM_DMA_TRIGGER:
5395 {
5396 /* Set the DMA trigger callbacks */
5397 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5398 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5399
5400 /* Set the DMA error callback */
5401 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5402
5403 /* Enable the DMA channel */
5404 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5405 DataLength) != HAL_OK)
5406 {
5407 /* Return error status */
5408 return HAL_ERROR;
5409 }
5410 /* Configure the DMA Burst Source Selection */
5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5412 break;
5413 }
5414 default:
5415 status = HAL_ERROR;
5416 break;
5417 }
5418
5419 if (status == HAL_OK)
5420 {
5421 /* Configure the DMA Burst Mode */
5422 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
5423
5424 /* Enable the TIM DMA Request */
5425 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5426 }
5427
5428 /* Return function status */
5429 return status;
5430 }
5431
5432 /**
5433 * @brief Stop the DMA burst reading
5434 * @param htim TIM handle
5435 * @param BurstRequestSrc TIM DMA Request sources to disable.
5436 * @retval HAL status
5437 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5438 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5439 {
5440 HAL_StatusTypeDef status = HAL_OK;
5441
5442 /* Check the parameters */
5443 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5444
5445 /* Abort the DMA transfer (at least disable the DMA channel) */
5446 switch (BurstRequestSrc)
5447 {
5448 case TIM_DMA_UPDATE:
5449 {
5450 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5451 break;
5452 }
5453 case TIM_DMA_CC1:
5454 {
5455 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5456 break;
5457 }
5458 case TIM_DMA_CC2:
5459 {
5460 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5461 break;
5462 }
5463 case TIM_DMA_CC3:
5464 {
5465 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5466 break;
5467 }
5468 case TIM_DMA_CC4:
5469 {
5470 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5471 break;
5472 }
5473 case TIM_DMA_COM:
5474 {
5475 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5476 break;
5477 }
5478 case TIM_DMA_TRIGGER:
5479 {
5480 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5481 break;
5482 }
5483 default:
5484 status = HAL_ERROR;
5485 break;
5486 }
5487
5488 if (status == HAL_OK)
5489 {
5490 /* Disable the TIM Update DMA request */
5491 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5492
5493 /* Change the DMA burst operation state */
5494 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5495 }
5496
5497 /* Return function status */
5498 return status;
5499 }
5500
5501 /**
5502 * @brief Generate a software event
5503 * @param htim TIM handle
5504 * @param EventSource specifies the event source.
5505 * This parameter can be one of the following values:
5506 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5507 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5508 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5509 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5510 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5511 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5512 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5513 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5514 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5515 * @note Basic timers can only generate an update event.
5516 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5517 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5518 * only for timer instances supporting break input(s).
5519 * @retval HAL status
5520 */
5521
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5522 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5523 {
5524 /* Check the parameters */
5525 assert_param(IS_TIM_INSTANCE(htim->Instance));
5526 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5527
5528 /* Process Locked */
5529 __HAL_LOCK(htim);
5530
5531 /* Change the TIM state */
5532 htim->State = HAL_TIM_STATE_BUSY;
5533
5534 /* Set the event sources */
5535 htim->Instance->EGR = EventSource;
5536
5537 /* Change the TIM state */
5538 htim->State = HAL_TIM_STATE_READY;
5539
5540 __HAL_UNLOCK(htim);
5541
5542 /* Return function status */
5543 return HAL_OK;
5544 }
5545
5546 /**
5547 * @brief Configures the OCRef clear feature
5548 * @param htim TIM handle
5549 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5550 * contains the OCREF clear feature and parameters for the TIM peripheral.
5551 * @param Channel specifies the TIM Channel
5552 * This parameter can be one of the following values:
5553 * @arg TIM_CHANNEL_1: TIM Channel 1
5554 * @arg TIM_CHANNEL_2: TIM Channel 2
5555 * @arg TIM_CHANNEL_3: TIM Channel 3
5556 * @arg TIM_CHANNEL_4: TIM Channel 4
5557 * @arg TIM_CHANNEL_5: TIM Channel 5
5558 * @arg TIM_CHANNEL_6: TIM Channel 6
5559 * @retval HAL status
5560 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5561 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5562 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5563 uint32_t Channel)
5564 {
5565 HAL_StatusTypeDef status = HAL_OK;
5566
5567 /* Check the parameters */
5568 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5569 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5570
5571 /* Process Locked */
5572 __HAL_LOCK(htim);
5573
5574 htim->State = HAL_TIM_STATE_BUSY;
5575
5576 switch (sClearInputConfig->ClearInputSource)
5577 {
5578 case TIM_CLEARINPUTSOURCE_NONE:
5579 {
5580 /* Clear the OCREF clear selection bit and the the ETR Bits */
5581 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5582 break;
5583 }
5584
5585 case TIM_CLEARINPUTSOURCE_COMP1:
5586 case TIM_CLEARINPUTSOURCE_COMP2:
5587 {
5588 /* Clear the OCREF clear selection bit */
5589 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5590
5591 /* Set the clear input source */
5592 MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
5593 break;
5594 }
5595
5596 case TIM_CLEARINPUTSOURCE_ETR:
5597 {
5598 /* Check the parameters */
5599 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5600 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5601 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5602
5603 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5604 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5605 {
5606 htim->State = HAL_TIM_STATE_READY;
5607 __HAL_UNLOCK(htim);
5608 return HAL_ERROR;
5609 }
5610
5611 TIM_ETR_SetConfig(htim->Instance,
5612 sClearInputConfig->ClearInputPrescaler,
5613 sClearInputConfig->ClearInputPolarity,
5614 sClearInputConfig->ClearInputFilter);
5615
5616 /* Set the OCREF clear selection bit */
5617 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5618
5619 /* Clear TIMx_AF2_OCRSEL (reset value) */
5620 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5621 break;
5622 }
5623
5624 default:
5625 status = HAL_ERROR;
5626 break;
5627 }
5628
5629 if (status == HAL_OK)
5630 {
5631 switch (Channel)
5632 {
5633 case TIM_CHANNEL_1:
5634 {
5635 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5636 {
5637 /* Enable the OCREF clear feature for Channel 1 */
5638 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5639 }
5640 else
5641 {
5642 /* Disable the OCREF clear feature for Channel 1 */
5643 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5644 }
5645 break;
5646 }
5647 case TIM_CHANNEL_2:
5648 {
5649 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5650 {
5651 /* Enable the OCREF clear feature for Channel 2 */
5652 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5653 }
5654 else
5655 {
5656 /* Disable the OCREF clear feature for Channel 2 */
5657 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5658 }
5659 break;
5660 }
5661 case TIM_CHANNEL_3:
5662 {
5663 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5664 {
5665 /* Enable the OCREF clear feature for Channel 3 */
5666 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5667 }
5668 else
5669 {
5670 /* Disable the OCREF clear feature for Channel 3 */
5671 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5672 }
5673 break;
5674 }
5675 case TIM_CHANNEL_4:
5676 {
5677 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5678 {
5679 /* Enable the OCREF clear feature for Channel 4 */
5680 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5681 }
5682 else
5683 {
5684 /* Disable the OCREF clear feature for Channel 4 */
5685 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5686 }
5687 break;
5688 }
5689 case TIM_CHANNEL_5:
5690 {
5691 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5692 {
5693 /* Enable the OCREF clear feature for Channel 5 */
5694 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5695 }
5696 else
5697 {
5698 /* Disable the OCREF clear feature for Channel 5 */
5699 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5700 }
5701 break;
5702 }
5703 case TIM_CHANNEL_6:
5704 {
5705 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5706 {
5707 /* Enable the OCREF clear feature for Channel 6 */
5708 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5709 }
5710 else
5711 {
5712 /* Disable the OCREF clear feature for Channel 6 */
5713 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5714 }
5715 break;
5716 }
5717 default:
5718 break;
5719 }
5720 }
5721
5722 htim->State = HAL_TIM_STATE_READY;
5723
5724 __HAL_UNLOCK(htim);
5725
5726 return status;
5727 }
5728
5729 /**
5730 * @brief Configures the clock source to be used
5731 * @param htim TIM handle
5732 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5733 * contains the clock source information for the TIM peripheral.
5734 * @retval HAL status
5735 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5736 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5737 {
5738 HAL_StatusTypeDef status = HAL_OK;
5739 uint32_t tmpsmcr;
5740
5741 /* Process Locked */
5742 __HAL_LOCK(htim);
5743
5744 htim->State = HAL_TIM_STATE_BUSY;
5745
5746 /* Check the parameters */
5747 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5748
5749 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5750 tmpsmcr = htim->Instance->SMCR;
5751 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5752 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5753 htim->Instance->SMCR = tmpsmcr;
5754
5755 switch (sClockSourceConfig->ClockSource)
5756 {
5757 case TIM_CLOCKSOURCE_INTERNAL:
5758 {
5759 assert_param(IS_TIM_INSTANCE(htim->Instance));
5760 break;
5761 }
5762
5763 case TIM_CLOCKSOURCE_ETRMODE1:
5764 {
5765 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5766 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5767
5768 /* Check ETR input conditioning related parameters */
5769 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5770 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5771 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5772
5773 /* Configure the ETR Clock source */
5774 TIM_ETR_SetConfig(htim->Instance,
5775 sClockSourceConfig->ClockPrescaler,
5776 sClockSourceConfig->ClockPolarity,
5777 sClockSourceConfig->ClockFilter);
5778
5779 /* Select the External clock mode1 and the ETRF trigger */
5780 tmpsmcr = htim->Instance->SMCR;
5781 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5782 /* Write to TIMx SMCR */
5783 htim->Instance->SMCR = tmpsmcr;
5784 break;
5785 }
5786
5787 case TIM_CLOCKSOURCE_ETRMODE2:
5788 {
5789 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5790 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5791
5792 /* Check ETR input conditioning related parameters */
5793 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5794 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5795 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5796
5797 /* Configure the ETR Clock source */
5798 TIM_ETR_SetConfig(htim->Instance,
5799 sClockSourceConfig->ClockPrescaler,
5800 sClockSourceConfig->ClockPolarity,
5801 sClockSourceConfig->ClockFilter);
5802 /* Enable the External clock mode2 */
5803 htim->Instance->SMCR |= TIM_SMCR_ECE;
5804 break;
5805 }
5806
5807 case TIM_CLOCKSOURCE_TI1:
5808 {
5809 /* Check whether or not the timer instance supports external clock mode 1 */
5810 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5811
5812 /* Check TI1 input conditioning related parameters */
5813 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5814 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5815
5816 TIM_TI1_ConfigInputStage(htim->Instance,
5817 sClockSourceConfig->ClockPolarity,
5818 sClockSourceConfig->ClockFilter);
5819 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5820 break;
5821 }
5822
5823 case TIM_CLOCKSOURCE_TI2:
5824 {
5825 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5826 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5827
5828 /* Check TI2 input conditioning related parameters */
5829 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5830 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5831
5832 TIM_TI2_ConfigInputStage(htim->Instance,
5833 sClockSourceConfig->ClockPolarity,
5834 sClockSourceConfig->ClockFilter);
5835 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5836 break;
5837 }
5838
5839 case TIM_CLOCKSOURCE_TI1ED:
5840 {
5841 /* Check whether or not the timer instance supports external clock mode 1 */
5842 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5843
5844 /* Check TI1 input conditioning related parameters */
5845 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5846 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5847
5848 TIM_TI1_ConfigInputStage(htim->Instance,
5849 sClockSourceConfig->ClockPolarity,
5850 sClockSourceConfig->ClockFilter);
5851 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5852 break;
5853 }
5854
5855 case TIM_CLOCKSOURCE_ITR0:
5856 case TIM_CLOCKSOURCE_ITR1:
5857 case TIM_CLOCKSOURCE_ITR2:
5858 case TIM_CLOCKSOURCE_ITR3:
5859 case TIM_CLOCKSOURCE_ITR4:
5860 case TIM_CLOCKSOURCE_ITR5:
5861 case TIM_CLOCKSOURCE_ITR6:
5862 case TIM_CLOCKSOURCE_ITR7:
5863 case TIM_CLOCKSOURCE_ITR8:
5864 case TIM_CLOCKSOURCE_ITR11:
5865 {
5866 /* Check whether or not the timer instance supports internal trigger input */
5867 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5868
5869 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5870 break;
5871 }
5872
5873 default:
5874 status = HAL_ERROR;
5875 break;
5876 }
5877 htim->State = HAL_TIM_STATE_READY;
5878
5879 __HAL_UNLOCK(htim);
5880
5881 return status;
5882 }
5883
5884 /**
5885 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5886 * or a XOR combination between CH1_input, CH2_input & CH3_input
5887 * @param htim TIM handle.
5888 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5889 * output of a XOR gate.
5890 * This parameter can be one of the following values:
5891 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5892 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5893 * pins are connected to the TI1 input (XOR combination)
5894 * @retval HAL status
5895 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5896 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5897 {
5898 uint32_t tmpcr2;
5899
5900 /* Check the parameters */
5901 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5902 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5903
5904 /* Get the TIMx CR2 register value */
5905 tmpcr2 = htim->Instance->CR2;
5906
5907 /* Reset the TI1 selection */
5908 tmpcr2 &= ~TIM_CR2_TI1S;
5909
5910 /* Set the TI1 selection */
5911 tmpcr2 |= TI1_Selection;
5912
5913 /* Write to TIMxCR2 */
5914 htim->Instance->CR2 = tmpcr2;
5915
5916 return HAL_OK;
5917 }
5918
5919 /**
5920 * @brief Configures the TIM in Slave mode
5921 * @param htim TIM handle.
5922 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5923 * contains the selected trigger (internal trigger input, filtered
5924 * timer input or external trigger input) and the Slave mode
5925 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5926 * @retval HAL status
5927 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5928 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5929 {
5930 /* Check the parameters */
5931 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5932 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5933 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5934
5935 __HAL_LOCK(htim);
5936
5937 htim->State = HAL_TIM_STATE_BUSY;
5938
5939 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5940 {
5941 htim->State = HAL_TIM_STATE_READY;
5942 __HAL_UNLOCK(htim);
5943 return HAL_ERROR;
5944 }
5945
5946 /* Disable Trigger Interrupt */
5947 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5948
5949 /* Disable Trigger DMA request */
5950 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5951
5952 htim->State = HAL_TIM_STATE_READY;
5953
5954 __HAL_UNLOCK(htim);
5955
5956 return HAL_OK;
5957 }
5958
5959 /**
5960 * @brief Configures the TIM in Slave mode in interrupt mode
5961 * @param htim TIM handle.
5962 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5963 * contains the selected trigger (internal trigger input, filtered
5964 * timer input or external trigger input) and the Slave mode
5965 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5966 * @retval HAL status
5967 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5968 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5969 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5970 {
5971 /* Check the parameters */
5972 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5973 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5974 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5975
5976 __HAL_LOCK(htim);
5977
5978 htim->State = HAL_TIM_STATE_BUSY;
5979
5980 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5981 {
5982 htim->State = HAL_TIM_STATE_READY;
5983 __HAL_UNLOCK(htim);
5984 return HAL_ERROR;
5985 }
5986
5987 /* Enable Trigger Interrupt */
5988 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5989
5990 /* Disable Trigger DMA request */
5991 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5992
5993 htim->State = HAL_TIM_STATE_READY;
5994
5995 __HAL_UNLOCK(htim);
5996
5997 return HAL_OK;
5998 }
5999
6000 /**
6001 * @brief Read the captured value from Capture Compare unit
6002 * @param htim TIM handle.
6003 * @param Channel TIM Channels to be enabled
6004 * This parameter can be one of the following values:
6005 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
6006 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
6007 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
6008 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
6009 * @retval Captured value
6010 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)6011 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
6012 {
6013 uint32_t tmpreg = 0U;
6014
6015 switch (Channel)
6016 {
6017 case TIM_CHANNEL_1:
6018 {
6019 /* Check the parameters */
6020 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6021
6022 /* Return the capture 1 value */
6023 tmpreg = htim->Instance->CCR1;
6024
6025 break;
6026 }
6027 case TIM_CHANNEL_2:
6028 {
6029 /* Check the parameters */
6030 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6031
6032 /* Return the capture 2 value */
6033 tmpreg = htim->Instance->CCR2;
6034
6035 break;
6036 }
6037
6038 case TIM_CHANNEL_3:
6039 {
6040 /* Check the parameters */
6041 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
6042
6043 /* Return the capture 3 value */
6044 tmpreg = htim->Instance->CCR3;
6045
6046 break;
6047 }
6048
6049 case TIM_CHANNEL_4:
6050 {
6051 /* Check the parameters */
6052 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
6053
6054 /* Return the capture 4 value */
6055 tmpreg = htim->Instance->CCR4;
6056
6057 break;
6058 }
6059
6060 default:
6061 break;
6062 }
6063
6064 return tmpreg;
6065 }
6066
6067 /**
6068 * @brief Start the DMA data transfer.
6069 * @param hdma DMA handle
6070 * @param src : The source memory Buffer address.
6071 * @param dst : The destination memory Buffer address.
6072 * @param length : The size of a source block transfer in byte.
6073 * @retval HAL status
6074 */
TIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)6075 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
6076 uint32_t length)
6077 {
6078 HAL_StatusTypeDef status ;
6079
6080 /* Enable the DMA channel */
6081 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6082 {
6083 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
6084 {
6085 /* Enable the DMA channel */
6086 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
6087 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
6088 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
6089
6090 status = HAL_DMAEx_List_Start_IT(hdma);
6091 }
6092 else
6093 {
6094 status = HAL_ERROR;
6095 }
6096 }
6097 else
6098 {
6099 status = HAL_DMA_Start_IT(hdma, src, dst, length);
6100 }
6101
6102 return status;
6103 }
6104
6105 /**
6106 * @}
6107 */
6108
6109 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
6110 * @brief TIM Callbacks functions
6111 *
6112 @verbatim
6113 ==============================================================================
6114 ##### TIM Callbacks functions #####
6115 ==============================================================================
6116 [..]
6117 This section provides TIM callback functions:
6118 (+) TIM Period elapsed callback
6119 (+) TIM Output Compare callback
6120 (+) TIM Input capture callback
6121 (+) TIM Trigger callback
6122 (+) TIM Error callback
6123 (+) TIM Index callback
6124 (+) TIM Direction change callback
6125 (+) TIM Index error callback
6126 (+) TIM Transition error callback
6127
6128 @endverbatim
6129 * @{
6130 */
6131
6132 /**
6133 * @brief Period elapsed callback in non-blocking mode
6134 * @param htim TIM handle
6135 * @retval None
6136 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)6137 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
6138 {
6139 /* Prevent unused argument(s) compilation warning */
6140 UNUSED(htim);
6141
6142 /* NOTE : This function should not be modified, when the callback is needed,
6143 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
6144 */
6145 }
6146
6147 /**
6148 * @brief Period elapsed half complete callback in non-blocking mode
6149 * @param htim TIM handle
6150 * @retval None
6151 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)6152 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
6153 {
6154 /* Prevent unused argument(s) compilation warning */
6155 UNUSED(htim);
6156
6157 /* NOTE : This function should not be modified, when the callback is needed,
6158 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
6159 */
6160 }
6161
6162 /**
6163 * @brief Output Compare callback in non-blocking mode
6164 * @param htim TIM OC handle
6165 * @retval None
6166 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)6167 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
6168 {
6169 /* Prevent unused argument(s) compilation warning */
6170 UNUSED(htim);
6171
6172 /* NOTE : This function should not be modified, when the callback is needed,
6173 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
6174 */
6175 }
6176
6177 /**
6178 * @brief Input Capture callback in non-blocking mode
6179 * @param htim TIM IC handle
6180 * @retval None
6181 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)6182 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
6183 {
6184 /* Prevent unused argument(s) compilation warning */
6185 UNUSED(htim);
6186
6187 /* NOTE : This function should not be modified, when the callback is needed,
6188 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
6189 */
6190 }
6191
6192 /**
6193 * @brief Input Capture half complete callback in non-blocking mode
6194 * @param htim TIM IC handle
6195 * @retval None
6196 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)6197 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
6198 {
6199 /* Prevent unused argument(s) compilation warning */
6200 UNUSED(htim);
6201
6202 /* NOTE : This function should not be modified, when the callback is needed,
6203 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
6204 */
6205 }
6206
6207 /**
6208 * @brief PWM Pulse finished callback in non-blocking mode
6209 * @param htim TIM handle
6210 * @retval None
6211 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)6212 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
6213 {
6214 /* Prevent unused argument(s) compilation warning */
6215 UNUSED(htim);
6216
6217 /* NOTE : This function should not be modified, when the callback is needed,
6218 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
6219 */
6220 }
6221
6222 /**
6223 * @brief PWM Pulse finished half complete callback in non-blocking mode
6224 * @param htim TIM handle
6225 * @retval None
6226 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)6227 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
6228 {
6229 /* Prevent unused argument(s) compilation warning */
6230 UNUSED(htim);
6231
6232 /* NOTE : This function should not be modified, when the callback is needed,
6233 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
6234 */
6235 }
6236
6237 /**
6238 * @brief Hall Trigger detection callback in non-blocking mode
6239 * @param htim TIM handle
6240 * @retval None
6241 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)6242 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
6243 {
6244 /* Prevent unused argument(s) compilation warning */
6245 UNUSED(htim);
6246
6247 /* NOTE : This function should not be modified, when the callback is needed,
6248 the HAL_TIM_TriggerCallback could be implemented in the user file
6249 */
6250 }
6251
6252 /**
6253 * @brief Hall Trigger detection half complete callback in non-blocking mode
6254 * @param htim TIM handle
6255 * @retval None
6256 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)6257 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
6258 {
6259 /* Prevent unused argument(s) compilation warning */
6260 UNUSED(htim);
6261
6262 /* NOTE : This function should not be modified, when the callback is needed,
6263 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
6264 */
6265 }
6266
6267 /**
6268 * @brief Timer error callback in non-blocking mode
6269 * @param htim TIM handle
6270 * @retval None
6271 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)6272 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
6273 {
6274 /* Prevent unused argument(s) compilation warning */
6275 UNUSED(htim);
6276
6277 /* NOTE : This function should not be modified, when the callback is needed,
6278 the HAL_TIM_ErrorCallback could be implemented in the user file
6279 */
6280 }
6281
6282 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6283 /**
6284 * @brief Register a User TIM callback to be used instead of the weak predefined callback
6285 * @param htim tim handle
6286 * @param CallbackID ID of the callback to be registered
6287 * This parameter can be one of the following values:
6288 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6289 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6290 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6291 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6292 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6293 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6294 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6295 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6296 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6297 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6298 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6299 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6300 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6301 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6302 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6303 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6304 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6305 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6306 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6307 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6308 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6309 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6310 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6311 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6312 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6313 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6314 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6315 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6316 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6317 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6318 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6319 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6320 * @param pCallback pointer to the callback function
6321 * @retval status
6322 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6323 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6324 pTIM_CallbackTypeDef pCallback)
6325 {
6326 HAL_StatusTypeDef status = HAL_OK;
6327
6328 if (pCallback == NULL)
6329 {
6330 return HAL_ERROR;
6331 }
6332
6333 if (htim->State == HAL_TIM_STATE_READY)
6334 {
6335 switch (CallbackID)
6336 {
6337 case HAL_TIM_BASE_MSPINIT_CB_ID :
6338 htim->Base_MspInitCallback = pCallback;
6339 break;
6340
6341 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6342 htim->Base_MspDeInitCallback = pCallback;
6343 break;
6344
6345 case HAL_TIM_IC_MSPINIT_CB_ID :
6346 htim->IC_MspInitCallback = pCallback;
6347 break;
6348
6349 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6350 htim->IC_MspDeInitCallback = pCallback;
6351 break;
6352
6353 case HAL_TIM_OC_MSPINIT_CB_ID :
6354 htim->OC_MspInitCallback = pCallback;
6355 break;
6356
6357 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6358 htim->OC_MspDeInitCallback = pCallback;
6359 break;
6360
6361 case HAL_TIM_PWM_MSPINIT_CB_ID :
6362 htim->PWM_MspInitCallback = pCallback;
6363 break;
6364
6365 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6366 htim->PWM_MspDeInitCallback = pCallback;
6367 break;
6368
6369 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6370 htim->OnePulse_MspInitCallback = pCallback;
6371 break;
6372
6373 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6374 htim->OnePulse_MspDeInitCallback = pCallback;
6375 break;
6376
6377 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6378 htim->Encoder_MspInitCallback = pCallback;
6379 break;
6380
6381 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6382 htim->Encoder_MspDeInitCallback = pCallback;
6383 break;
6384
6385 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6386 htim->HallSensor_MspInitCallback = pCallback;
6387 break;
6388
6389 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6390 htim->HallSensor_MspDeInitCallback = pCallback;
6391 break;
6392
6393 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6394 htim->PeriodElapsedCallback = pCallback;
6395 break;
6396
6397 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6398 htim->PeriodElapsedHalfCpltCallback = pCallback;
6399 break;
6400
6401 case HAL_TIM_TRIGGER_CB_ID :
6402 htim->TriggerCallback = pCallback;
6403 break;
6404
6405 case HAL_TIM_TRIGGER_HALF_CB_ID :
6406 htim->TriggerHalfCpltCallback = pCallback;
6407 break;
6408
6409 case HAL_TIM_IC_CAPTURE_CB_ID :
6410 htim->IC_CaptureCallback = pCallback;
6411 break;
6412
6413 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6414 htim->IC_CaptureHalfCpltCallback = pCallback;
6415 break;
6416
6417 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6418 htim->OC_DelayElapsedCallback = pCallback;
6419 break;
6420
6421 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6422 htim->PWM_PulseFinishedCallback = pCallback;
6423 break;
6424
6425 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6426 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6427 break;
6428
6429 case HAL_TIM_ERROR_CB_ID :
6430 htim->ErrorCallback = pCallback;
6431 break;
6432
6433 case HAL_TIM_COMMUTATION_CB_ID :
6434 htim->CommutationCallback = pCallback;
6435 break;
6436
6437 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6438 htim->CommutationHalfCpltCallback = pCallback;
6439 break;
6440
6441 case HAL_TIM_BREAK_CB_ID :
6442 htim->BreakCallback = pCallback;
6443 break;
6444
6445 case HAL_TIM_BREAK2_CB_ID :
6446 htim->Break2Callback = pCallback;
6447 break;
6448
6449 case HAL_TIM_ENCODER_INDEX_CB_ID :
6450 htim->EncoderIndexCallback = pCallback;
6451 break;
6452
6453 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6454 htim->DirectionChangeCallback = pCallback;
6455 break;
6456
6457 case HAL_TIM_INDEX_ERROR_CB_ID :
6458 htim->IndexErrorCallback = pCallback;
6459 break;
6460
6461 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6462 htim->TransitionErrorCallback = pCallback;
6463 break;
6464
6465 default :
6466 /* Return error status */
6467 status = HAL_ERROR;
6468 break;
6469 }
6470 }
6471 else if (htim->State == HAL_TIM_STATE_RESET)
6472 {
6473 switch (CallbackID)
6474 {
6475 case HAL_TIM_BASE_MSPINIT_CB_ID :
6476 htim->Base_MspInitCallback = pCallback;
6477 break;
6478
6479 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6480 htim->Base_MspDeInitCallback = pCallback;
6481 break;
6482
6483 case HAL_TIM_IC_MSPINIT_CB_ID :
6484 htim->IC_MspInitCallback = pCallback;
6485 break;
6486
6487 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6488 htim->IC_MspDeInitCallback = pCallback;
6489 break;
6490
6491 case HAL_TIM_OC_MSPINIT_CB_ID :
6492 htim->OC_MspInitCallback = pCallback;
6493 break;
6494
6495 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6496 htim->OC_MspDeInitCallback = pCallback;
6497 break;
6498
6499 case HAL_TIM_PWM_MSPINIT_CB_ID :
6500 htim->PWM_MspInitCallback = pCallback;
6501 break;
6502
6503 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6504 htim->PWM_MspDeInitCallback = pCallback;
6505 break;
6506
6507 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6508 htim->OnePulse_MspInitCallback = pCallback;
6509 break;
6510
6511 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6512 htim->OnePulse_MspDeInitCallback = pCallback;
6513 break;
6514
6515 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6516 htim->Encoder_MspInitCallback = pCallback;
6517 break;
6518
6519 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6520 htim->Encoder_MspDeInitCallback = pCallback;
6521 break;
6522
6523 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6524 htim->HallSensor_MspInitCallback = pCallback;
6525 break;
6526
6527 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6528 htim->HallSensor_MspDeInitCallback = pCallback;
6529 break;
6530
6531 default :
6532 /* Return error status */
6533 status = HAL_ERROR;
6534 break;
6535 }
6536 }
6537 else
6538 {
6539 /* Return error status */
6540 status = HAL_ERROR;
6541 }
6542
6543 return status;
6544 }
6545
6546 /**
6547 * @brief Unregister a TIM callback
6548 * TIM callback is redirected to the weak predefined callback
6549 * @param htim tim handle
6550 * @param CallbackID ID of the callback to be unregistered
6551 * This parameter can be one of the following values:
6552 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6553 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6554 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6555 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6556 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6557 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6558 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6559 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6560 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6561 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6562 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6563 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6564 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6565 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6566 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6567 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6568 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6569 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6570 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6571 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6572 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6573 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6574 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6575 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6576 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6577 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6578 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6579 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6580 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6581 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6582 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6583 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6584 * @retval status
6585 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6586 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6587 {
6588 HAL_StatusTypeDef status = HAL_OK;
6589
6590 if (htim->State == HAL_TIM_STATE_READY)
6591 {
6592 switch (CallbackID)
6593 {
6594 case HAL_TIM_BASE_MSPINIT_CB_ID :
6595 /* Legacy weak Base MspInit Callback */
6596 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6597 break;
6598
6599 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6600 /* Legacy weak Base Msp DeInit Callback */
6601 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6602 break;
6603
6604 case HAL_TIM_IC_MSPINIT_CB_ID :
6605 /* Legacy weak IC Msp Init Callback */
6606 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6607 break;
6608
6609 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6610 /* Legacy weak IC Msp DeInit Callback */
6611 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6612 break;
6613
6614 case HAL_TIM_OC_MSPINIT_CB_ID :
6615 /* Legacy weak OC Msp Init Callback */
6616 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6617 break;
6618
6619 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6620 /* Legacy weak OC Msp DeInit Callback */
6621 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6622 break;
6623
6624 case HAL_TIM_PWM_MSPINIT_CB_ID :
6625 /* Legacy weak PWM Msp Init Callback */
6626 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6627 break;
6628
6629 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6630 /* Legacy weak PWM Msp DeInit Callback */
6631 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6632 break;
6633
6634 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6635 /* Legacy weak One Pulse Msp Init Callback */
6636 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6637 break;
6638
6639 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6640 /* Legacy weak One Pulse Msp DeInit Callback */
6641 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6642 break;
6643
6644 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6645 /* Legacy weak Encoder Msp Init Callback */
6646 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6647 break;
6648
6649 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6650 /* Legacy weak Encoder Msp DeInit Callback */
6651 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6652 break;
6653
6654 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6655 /* Legacy weak Hall Sensor Msp Init Callback */
6656 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6657 break;
6658
6659 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6660 /* Legacy weak Hall Sensor Msp DeInit Callback */
6661 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6662 break;
6663
6664 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6665 /* Legacy weak Period Elapsed Callback */
6666 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6667 break;
6668
6669 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6670 /* Legacy weak Period Elapsed half complete Callback */
6671 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6672 break;
6673
6674 case HAL_TIM_TRIGGER_CB_ID :
6675 /* Legacy weak Trigger Callback */
6676 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6677 break;
6678
6679 case HAL_TIM_TRIGGER_HALF_CB_ID :
6680 /* Legacy weak Trigger half complete Callback */
6681 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6682 break;
6683
6684 case HAL_TIM_IC_CAPTURE_CB_ID :
6685 /* Legacy weak IC Capture Callback */
6686 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6687 break;
6688
6689 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6690 /* Legacy weak IC Capture half complete Callback */
6691 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6692 break;
6693
6694 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6695 /* Legacy weak OC Delay Elapsed Callback */
6696 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6697 break;
6698
6699 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6700 /* Legacy weak PWM Pulse Finished Callback */
6701 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6702 break;
6703
6704 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6705 /* Legacy weak PWM Pulse Finished half complete Callback */
6706 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6707 break;
6708
6709 case HAL_TIM_ERROR_CB_ID :
6710 /* Legacy weak Error Callback */
6711 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6712 break;
6713
6714 case HAL_TIM_COMMUTATION_CB_ID :
6715 /* Legacy weak Commutation Callback */
6716 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6717 break;
6718
6719 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6720 /* Legacy weak Commutation half complete Callback */
6721 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6722 break;
6723
6724 case HAL_TIM_BREAK_CB_ID :
6725 /* Legacy weak Break Callback */
6726 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6727 break;
6728
6729 case HAL_TIM_BREAK2_CB_ID :
6730 /* Legacy weak Break2 Callback */
6731 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6732 break;
6733
6734 case HAL_TIM_ENCODER_INDEX_CB_ID :
6735 /* Legacy weak Encoder Index Callback */
6736 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
6737 break;
6738
6739 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6740 /* Legacy weak Direction Change Callback */
6741 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
6742 break;
6743
6744 case HAL_TIM_INDEX_ERROR_CB_ID :
6745 /* Legacy weak Index Error Callback */
6746 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
6747 break;
6748
6749 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6750 /* Legacy weak Transition Error Callback */
6751 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
6752 break;
6753
6754 default :
6755 /* Return error status */
6756 status = HAL_ERROR;
6757 break;
6758 }
6759 }
6760 else if (htim->State == HAL_TIM_STATE_RESET)
6761 {
6762 switch (CallbackID)
6763 {
6764 case HAL_TIM_BASE_MSPINIT_CB_ID :
6765 /* Legacy weak Base MspInit Callback */
6766 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6767 break;
6768
6769 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6770 /* Legacy weak Base Msp DeInit Callback */
6771 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6772 break;
6773
6774 case HAL_TIM_IC_MSPINIT_CB_ID :
6775 /* Legacy weak IC Msp Init Callback */
6776 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6777 break;
6778
6779 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6780 /* Legacy weak IC Msp DeInit Callback */
6781 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6782 break;
6783
6784 case HAL_TIM_OC_MSPINIT_CB_ID :
6785 /* Legacy weak OC Msp Init Callback */
6786 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6787 break;
6788
6789 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6790 /* Legacy weak OC Msp DeInit Callback */
6791 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6792 break;
6793
6794 case HAL_TIM_PWM_MSPINIT_CB_ID :
6795 /* Legacy weak PWM Msp Init Callback */
6796 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6797 break;
6798
6799 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6800 /* Legacy weak PWM Msp DeInit Callback */
6801 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6802 break;
6803
6804 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6805 /* Legacy weak One Pulse Msp Init Callback */
6806 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6807 break;
6808
6809 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6810 /* Legacy weak One Pulse Msp DeInit Callback */
6811 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6812 break;
6813
6814 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6815 /* Legacy weak Encoder Msp Init Callback */
6816 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6817 break;
6818
6819 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6820 /* Legacy weak Encoder Msp DeInit Callback */
6821 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6822 break;
6823
6824 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6825 /* Legacy weak Hall Sensor Msp Init Callback */
6826 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6827 break;
6828
6829 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6830 /* Legacy weak Hall Sensor Msp DeInit Callback */
6831 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6832 break;
6833
6834 default :
6835 /* Return error status */
6836 status = HAL_ERROR;
6837 break;
6838 }
6839 }
6840 else
6841 {
6842 /* Return error status */
6843 status = HAL_ERROR;
6844 }
6845
6846 return status;
6847 }
6848 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6849
6850 /**
6851 * @}
6852 */
6853
6854 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6855 * @brief TIM Peripheral State functions
6856 *
6857 @verbatim
6858 ==============================================================================
6859 ##### Peripheral State functions #####
6860 ==============================================================================
6861 [..]
6862 This subsection permits to get in run-time the status of the peripheral
6863 and the data flow.
6864
6865 @endverbatim
6866 * @{
6867 */
6868
6869 /**
6870 * @brief Return the TIM Base handle state.
6871 * @param htim TIM Base handle
6872 * @retval HAL state
6873 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6874 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6875 {
6876 return htim->State;
6877 }
6878
6879 /**
6880 * @brief Return the TIM OC handle state.
6881 * @param htim TIM Output Compare handle
6882 * @retval HAL state
6883 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6884 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6885 {
6886 return htim->State;
6887 }
6888
6889 /**
6890 * @brief Return the TIM PWM handle state.
6891 * @param htim TIM handle
6892 * @retval HAL state
6893 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6894 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6895 {
6896 return htim->State;
6897 }
6898
6899 /**
6900 * @brief Return the TIM Input Capture handle state.
6901 * @param htim TIM IC handle
6902 * @retval HAL state
6903 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6904 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6905 {
6906 return htim->State;
6907 }
6908
6909 /**
6910 * @brief Return the TIM One Pulse Mode handle state.
6911 * @param htim TIM OPM handle
6912 * @retval HAL state
6913 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6914 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6915 {
6916 return htim->State;
6917 }
6918
6919 /**
6920 * @brief Return the TIM Encoder Mode handle state.
6921 * @param htim TIM Encoder Interface handle
6922 * @retval HAL state
6923 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6924 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6925 {
6926 return htim->State;
6927 }
6928
6929 /**
6930 * @brief Return the TIM Encoder Mode handle state.
6931 * @param htim TIM handle
6932 * @retval Active channel
6933 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6934 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6935 {
6936 return htim->Channel;
6937 }
6938
6939 /**
6940 * @brief Return actual state of the TIM channel.
6941 * @param htim TIM handle
6942 * @param Channel TIM Channel
6943 * This parameter can be one of the following values:
6944 * @arg TIM_CHANNEL_1: TIM Channel 1
6945 * @arg TIM_CHANNEL_2: TIM Channel 2
6946 * @arg TIM_CHANNEL_3: TIM Channel 3
6947 * @arg TIM_CHANNEL_4: TIM Channel 4
6948 * @arg TIM_CHANNEL_5: TIM Channel 5
6949 * @arg TIM_CHANNEL_6: TIM Channel 6
6950 * @retval TIM Channel state
6951 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6952 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6953 {
6954 HAL_TIM_ChannelStateTypeDef channel_state;
6955
6956 /* Check the parameters */
6957 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6958
6959 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6960
6961 return channel_state;
6962 }
6963
6964 /**
6965 * @brief Return actual state of a DMA burst operation.
6966 * @param htim TIM handle
6967 * @retval DMA burst state
6968 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6969 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6970 {
6971 /* Check the parameters */
6972 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6973
6974 return htim->DMABurstState;
6975 }
6976
6977 /**
6978 * @}
6979 */
6980
6981 /**
6982 * @}
6983 */
6984
6985 /** @defgroup TIM_Private_Functions TIM Private Functions
6986 * @{
6987 */
6988
6989 /**
6990 * @brief TIM DMA error callback
6991 * @param hdma pointer to DMA handle.
6992 * @retval None
6993 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6994 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6995 {
6996 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6997
6998 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6999 {
7000 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7001 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
7002 }
7003 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7004 {
7005 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7006 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
7007 }
7008 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7009 {
7010 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7011 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
7012 }
7013 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7014 {
7015 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7016 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
7017 }
7018 else
7019 {
7020 htim->State = HAL_TIM_STATE_READY;
7021 }
7022
7023 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7024 htim->ErrorCallback(htim);
7025 #else
7026 HAL_TIM_ErrorCallback(htim);
7027 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7028
7029 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7030 }
7031
7032 /**
7033 * @brief TIM DMA Delay Pulse complete callback.
7034 * @param hdma pointer to DMA handle.
7035 * @retval None
7036 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)7037 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
7038 {
7039 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7040
7041 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7042 {
7043 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7044 }
7045 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7046 {
7047 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7048 }
7049 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7050 {
7051 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7052 }
7053 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7054 {
7055 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7056 }
7057 else
7058 {
7059 /* nothing to do */
7060 }
7061
7062 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7063 htim->PWM_PulseFinishedCallback(htim);
7064 #else
7065 HAL_TIM_PWM_PulseFinishedCallback(htim);
7066 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7067
7068 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7069 }
7070
7071 /**
7072 * @brief TIM DMA Delay Pulse half complete callback.
7073 * @param hdma pointer to DMA handle.
7074 * @retval None
7075 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)7076 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
7077 {
7078 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7079
7080 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7081 {
7082 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7083 }
7084 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7085 {
7086 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7087 }
7088 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7089 {
7090 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7091 }
7092 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7093 {
7094 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7095 }
7096 else
7097 {
7098 /* nothing to do */
7099 }
7100
7101 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7102 htim->PWM_PulseFinishedHalfCpltCallback(htim);
7103 #else
7104 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
7105 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7106
7107 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7108 }
7109
7110 /**
7111 * @brief TIM DMA Capture complete callback.
7112 * @param hdma pointer to DMA handle.
7113 * @retval None
7114 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)7115 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
7116 {
7117 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7118
7119 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7120 {
7121 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7122 }
7123 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7124 {
7125 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7126 }
7127 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7128 {
7129 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7130 }
7131 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7132 {
7133 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7134 }
7135 else
7136 {
7137 /* nothing to do */
7138 }
7139
7140 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7141 htim->IC_CaptureCallback(htim);
7142 #else
7143 HAL_TIM_IC_CaptureCallback(htim);
7144 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7145
7146 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7147 }
7148
7149 /**
7150 * @brief TIM DMA Capture half complete callback.
7151 * @param hdma pointer to DMA handle.
7152 * @retval None
7153 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)7154 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
7155 {
7156 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7157
7158 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7159 {
7160 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7161 }
7162 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7163 {
7164 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7165 }
7166 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7167 {
7168 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7169 }
7170 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7171 {
7172 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7173 }
7174 else
7175 {
7176 /* nothing to do */
7177 }
7178
7179 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7180 htim->IC_CaptureHalfCpltCallback(htim);
7181 #else
7182 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
7183 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7184
7185 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7186 }
7187
7188 /**
7189 * @brief TIM DMA Period Elapse complete callback.
7190 * @param hdma pointer to DMA handle.
7191 * @retval None
7192 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)7193 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
7194 {
7195 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7196
7197 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7198 htim->PeriodElapsedCallback(htim);
7199 #else
7200 HAL_TIM_PeriodElapsedCallback(htim);
7201 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7202 }
7203
7204 /**
7205 * @brief TIM DMA Period Elapse half complete callback.
7206 * @param hdma pointer to DMA handle.
7207 * @retval None
7208 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)7209 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
7210 {
7211 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7212
7213 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7214 htim->PeriodElapsedHalfCpltCallback(htim);
7215 #else
7216 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
7217 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7218 }
7219
7220 /**
7221 * @brief TIM DMA Trigger callback.
7222 * @param hdma pointer to DMA handle.
7223 * @retval None
7224 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)7225 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
7226 {
7227 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7228
7229 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7230 htim->TriggerCallback(htim);
7231 #else
7232 HAL_TIM_TriggerCallback(htim);
7233 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7234 }
7235
7236 /**
7237 * @brief TIM DMA Trigger half complete callback.
7238 * @param hdma pointer to DMA handle.
7239 * @retval None
7240 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)7241 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
7242 {
7243 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7244
7245 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7246 htim->TriggerHalfCpltCallback(htim);
7247 #else
7248 HAL_TIM_TriggerHalfCpltCallback(htim);
7249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7250 }
7251
7252 /**
7253 * @brief Time Base configuration
7254 * @param TIMx TIM peripheral
7255 * @param Structure TIM Base configuration structure
7256 * @retval None
7257 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)7258 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
7259 {
7260 uint32_t tmpcr1;
7261 tmpcr1 = TIMx->CR1;
7262
7263 /* Set TIM Time Base Unit parameters ---------------------------------------*/
7264 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
7265 {
7266 /* Select the Counter Mode */
7267 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
7268 tmpcr1 |= Structure->CounterMode;
7269 }
7270
7271 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
7272 {
7273 /* Set the clock division */
7274 tmpcr1 &= ~TIM_CR1_CKD;
7275 tmpcr1 |= (uint32_t)Structure->ClockDivision;
7276 }
7277
7278 /* Set the auto-reload preload */
7279 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
7280
7281 TIMx->CR1 = tmpcr1;
7282
7283 /* Set the Autoreload value */
7284 TIMx->ARR = (uint32_t)Structure->Period ;
7285
7286 /* Set the Prescaler value */
7287 TIMx->PSC = Structure->Prescaler;
7288
7289 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7290 {
7291 /* Set the Repetition Counter value */
7292 TIMx->RCR = Structure->RepetitionCounter;
7293 }
7294
7295 /* Generate an update event to reload the Prescaler
7296 and the repetition counter (only for advanced timer) value immediately */
7297 TIMx->EGR = TIM_EGR_UG;
7298 }
7299
7300 /**
7301 * @brief Timer Output Compare 1 configuration
7302 * @param TIMx to select the TIM peripheral
7303 * @param OC_Config The output configuration structure
7304 * @retval None
7305 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7306 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7307 {
7308 uint32_t tmpccmrx;
7309 uint32_t tmpccer;
7310 uint32_t tmpcr2;
7311
7312 /* Get the TIMx CCER register value */
7313 tmpccer = TIMx->CCER;
7314
7315 /* Disable the Channel 1: Reset the CC1E Bit */
7316 TIMx->CCER &= ~TIM_CCER_CC1E;
7317
7318 /* Get the TIMx CR2 register value */
7319 tmpcr2 = TIMx->CR2;
7320
7321 /* Get the TIMx CCMR1 register value */
7322 tmpccmrx = TIMx->CCMR1;
7323
7324 /* Reset the Output Compare Mode Bits */
7325 tmpccmrx &= ~TIM_CCMR1_OC1M;
7326 tmpccmrx &= ~TIM_CCMR1_CC1S;
7327 /* Select the Output Compare Mode */
7328 tmpccmrx |= OC_Config->OCMode;
7329
7330 /* Reset the Output Polarity level */
7331 tmpccer &= ~TIM_CCER_CC1P;
7332 /* Set the Output Compare Polarity */
7333 tmpccer |= OC_Config->OCPolarity;
7334
7335 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7336 {
7337 /* Check parameters */
7338 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7339
7340 /* Reset the Output N Polarity level */
7341 tmpccer &= ~TIM_CCER_CC1NP;
7342 /* Set the Output N Polarity */
7343 tmpccer |= OC_Config->OCNPolarity;
7344 /* Reset the Output N State */
7345 tmpccer &= ~TIM_CCER_CC1NE;
7346 }
7347
7348 if (IS_TIM_BREAK_INSTANCE(TIMx))
7349 {
7350 /* Check parameters */
7351 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7352 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7353
7354 /* Reset the Output Compare and Output Compare N IDLE State */
7355 tmpcr2 &= ~TIM_CR2_OIS1;
7356 tmpcr2 &= ~TIM_CR2_OIS1N;
7357 /* Set the Output Idle state */
7358 tmpcr2 |= OC_Config->OCIdleState;
7359 /* Set the Output N Idle state */
7360 tmpcr2 |= OC_Config->OCNIdleState;
7361 }
7362
7363 /* Write to TIMx CR2 */
7364 TIMx->CR2 = tmpcr2;
7365
7366 /* Write to TIMx CCMR1 */
7367 TIMx->CCMR1 = tmpccmrx;
7368
7369 /* Set the Capture Compare Register value */
7370 TIMx->CCR1 = OC_Config->Pulse;
7371
7372 /* Write to TIMx CCER */
7373 TIMx->CCER = tmpccer;
7374 }
7375
7376 /**
7377 * @brief Timer Output Compare 2 configuration
7378 * @param TIMx to select the TIM peripheral
7379 * @param OC_Config The output configuration structure
7380 * @retval None
7381 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7382 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7383 {
7384 uint32_t tmpccmrx;
7385 uint32_t tmpccer;
7386 uint32_t tmpcr2;
7387
7388 /* Get the TIMx CCER register value */
7389 tmpccer = TIMx->CCER;
7390
7391 /* Disable the Channel 2: Reset the CC2E Bit */
7392 TIMx->CCER &= ~TIM_CCER_CC2E;
7393
7394 /* Get the TIMx CR2 register value */
7395 tmpcr2 = TIMx->CR2;
7396
7397 /* Get the TIMx CCMR1 register value */
7398 tmpccmrx = TIMx->CCMR1;
7399
7400 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7401 tmpccmrx &= ~TIM_CCMR1_OC2M;
7402 tmpccmrx &= ~TIM_CCMR1_CC2S;
7403
7404 /* Select the Output Compare Mode */
7405 tmpccmrx |= (OC_Config->OCMode << 8U);
7406
7407 /* Reset the Output Polarity level */
7408 tmpccer &= ~TIM_CCER_CC2P;
7409 /* Set the Output Compare Polarity */
7410 tmpccer |= (OC_Config->OCPolarity << 4U);
7411
7412 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7413 {
7414 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7415
7416 /* Reset the Output N Polarity level */
7417 tmpccer &= ~TIM_CCER_CC2NP;
7418 /* Set the Output N Polarity */
7419 tmpccer |= (OC_Config->OCNPolarity << 4U);
7420 /* Reset the Output N State */
7421 tmpccer &= ~TIM_CCER_CC2NE;
7422
7423 }
7424
7425 if (IS_TIM_BREAK_INSTANCE(TIMx))
7426 {
7427 /* Check parameters */
7428 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7429 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7430
7431 /* Reset the Output Compare and Output Compare N IDLE State */
7432 tmpcr2 &= ~TIM_CR2_OIS2;
7433 tmpcr2 &= ~TIM_CR2_OIS2N;
7434 /* Set the Output Idle state */
7435 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7436 /* Set the Output N Idle state */
7437 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7438 }
7439
7440 /* Write to TIMx CR2 */
7441 TIMx->CR2 = tmpcr2;
7442
7443 /* Write to TIMx CCMR1 */
7444 TIMx->CCMR1 = tmpccmrx;
7445
7446 /* Set the Capture Compare Register value */
7447 TIMx->CCR2 = OC_Config->Pulse;
7448
7449 /* Write to TIMx CCER */
7450 TIMx->CCER = tmpccer;
7451 }
7452
7453 /**
7454 * @brief Timer Output Compare 3 configuration
7455 * @param TIMx to select the TIM peripheral
7456 * @param OC_Config The output configuration structure
7457 * @retval None
7458 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7459 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7460 {
7461 uint32_t tmpccmrx;
7462 uint32_t tmpccer;
7463 uint32_t tmpcr2;
7464
7465 /* Get the TIMx CCER register value */
7466 tmpccer = TIMx->CCER;
7467
7468 /* Disable the Channel 3: Reset the CC2E Bit */
7469 TIMx->CCER &= ~TIM_CCER_CC3E;
7470
7471 /* Get the TIMx CR2 register value */
7472 tmpcr2 = TIMx->CR2;
7473
7474 /* Get the TIMx CCMR2 register value */
7475 tmpccmrx = TIMx->CCMR2;
7476
7477 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7478 tmpccmrx &= ~TIM_CCMR2_OC3M;
7479 tmpccmrx &= ~TIM_CCMR2_CC3S;
7480 /* Select the Output Compare Mode */
7481 tmpccmrx |= OC_Config->OCMode;
7482
7483 /* Reset the Output Polarity level */
7484 tmpccer &= ~TIM_CCER_CC3P;
7485 /* Set the Output Compare Polarity */
7486 tmpccer |= (OC_Config->OCPolarity << 8U);
7487
7488 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7489 {
7490 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7491
7492 /* Reset the Output N Polarity level */
7493 tmpccer &= ~TIM_CCER_CC3NP;
7494 /* Set the Output N Polarity */
7495 tmpccer |= (OC_Config->OCNPolarity << 8U);
7496 /* Reset the Output N State */
7497 tmpccer &= ~TIM_CCER_CC3NE;
7498 }
7499
7500 if (IS_TIM_BREAK_INSTANCE(TIMx))
7501 {
7502 /* Check parameters */
7503 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7504 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7505
7506 /* Reset the Output Compare and Output Compare N IDLE State */
7507 tmpcr2 &= ~TIM_CR2_OIS3;
7508 tmpcr2 &= ~TIM_CR2_OIS3N;
7509 /* Set the Output Idle state */
7510 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7511 /* Set the Output N Idle state */
7512 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7513 }
7514
7515 /* Write to TIMx CR2 */
7516 TIMx->CR2 = tmpcr2;
7517
7518 /* Write to TIMx CCMR2 */
7519 TIMx->CCMR2 = tmpccmrx;
7520
7521 /* Set the Capture Compare Register value */
7522 TIMx->CCR3 = OC_Config->Pulse;
7523
7524 /* Write to TIMx CCER */
7525 TIMx->CCER = tmpccer;
7526 }
7527
7528 /**
7529 * @brief Timer Output Compare 4 configuration
7530 * @param TIMx to select the TIM peripheral
7531 * @param OC_Config The output configuration structure
7532 * @retval None
7533 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7534 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7535 {
7536 uint32_t tmpccmrx;
7537 uint32_t tmpccer;
7538 uint32_t tmpcr2;
7539
7540 /* Get the TIMx CCER register value */
7541 tmpccer = TIMx->CCER;
7542
7543 /* Disable the Channel 4: Reset the CC4E Bit */
7544 TIMx->CCER &= ~TIM_CCER_CC4E;
7545
7546 /* Get the TIMx CR2 register value */
7547 tmpcr2 = TIMx->CR2;
7548
7549 /* Get the TIMx CCMR2 register value */
7550 tmpccmrx = TIMx->CCMR2;
7551
7552 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7553 tmpccmrx &= ~TIM_CCMR2_OC4M;
7554 tmpccmrx &= ~TIM_CCMR2_CC4S;
7555
7556 /* Select the Output Compare Mode */
7557 tmpccmrx |= (OC_Config->OCMode << 8U);
7558
7559 /* Reset the Output Polarity level */
7560 tmpccer &= ~TIM_CCER_CC4P;
7561 /* Set the Output Compare Polarity */
7562 tmpccer |= (OC_Config->OCPolarity << 12U);
7563
7564 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7565 {
7566 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7567
7568 /* Reset the Output N Polarity level */
7569 tmpccer &= ~TIM_CCER_CC4NP;
7570 /* Set the Output N Polarity */
7571 tmpccer |= (OC_Config->OCNPolarity << 12U);
7572 /* Reset the Output N State */
7573 tmpccer &= ~TIM_CCER_CC4NE;
7574 }
7575
7576 if (IS_TIM_BREAK_INSTANCE(TIMx))
7577 {
7578 /* Check parameters */
7579 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7580 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7581
7582 /* Reset the Output Compare IDLE State */
7583 tmpcr2 &= ~TIM_CR2_OIS4;
7584 /* Reset the Output Compare N IDLE State */
7585 tmpcr2 &= ~TIM_CR2_OIS4N;
7586
7587 /* Set the Output Idle state */
7588 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7589 /* Set the Output N Idle state */
7590 tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7591 }
7592
7593 /* Write to TIMx CR2 */
7594 TIMx->CR2 = tmpcr2;
7595
7596 /* Write to TIMx CCMR2 */
7597 TIMx->CCMR2 = tmpccmrx;
7598
7599 /* Set the Capture Compare Register value */
7600 TIMx->CCR4 = OC_Config->Pulse;
7601
7602 /* Write to TIMx CCER */
7603 TIMx->CCER = tmpccer;
7604 }
7605
7606 /**
7607 * @brief Timer Output Compare 5 configuration
7608 * @param TIMx to select the TIM peripheral
7609 * @param OC_Config The output configuration structure
7610 * @retval None
7611 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7612 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7613 const TIM_OC_InitTypeDef *OC_Config)
7614 {
7615 uint32_t tmpccmrx;
7616 uint32_t tmpccer;
7617 uint32_t tmpcr2;
7618
7619 /* Get the TIMx CCER register value */
7620 tmpccer = TIMx->CCER;
7621
7622 /* Disable the output: Reset the CCxE Bit */
7623 TIMx->CCER &= ~TIM_CCER_CC5E;
7624
7625 /* Get the TIMx CR2 register value */
7626 tmpcr2 = TIMx->CR2;
7627 /* Get the TIMx CCMR1 register value */
7628 tmpccmrx = TIMx->CCMR3;
7629
7630 /* Reset the Output Compare Mode Bits */
7631 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7632 /* Select the Output Compare Mode */
7633 tmpccmrx |= OC_Config->OCMode;
7634
7635 /* Reset the Output Polarity level */
7636 tmpccer &= ~TIM_CCER_CC5P;
7637 /* Set the Output Compare Polarity */
7638 tmpccer |= (OC_Config->OCPolarity << 16U);
7639
7640 if (IS_TIM_BREAK_INSTANCE(TIMx))
7641 {
7642 /* Reset the Output Compare IDLE State */
7643 tmpcr2 &= ~TIM_CR2_OIS5;
7644 /* Set the Output Idle state */
7645 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7646 }
7647 /* Write to TIMx CR2 */
7648 TIMx->CR2 = tmpcr2;
7649
7650 /* Write to TIMx CCMR3 */
7651 TIMx->CCMR3 = tmpccmrx;
7652
7653 /* Set the Capture Compare Register value */
7654 TIMx->CCR5 = OC_Config->Pulse;
7655
7656 /* Write to TIMx CCER */
7657 TIMx->CCER = tmpccer;
7658 }
7659
7660 /**
7661 * @brief Timer Output Compare 6 configuration
7662 * @param TIMx to select the TIM peripheral
7663 * @param OC_Config The output configuration structure
7664 * @retval None
7665 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7666 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7667 const TIM_OC_InitTypeDef *OC_Config)
7668 {
7669 uint32_t tmpccmrx;
7670 uint32_t tmpccer;
7671 uint32_t tmpcr2;
7672
7673 /* Get the TIMx CCER register value */
7674 tmpccer = TIMx->CCER;
7675
7676 /* Disable the output: Reset the CCxE Bit */
7677 TIMx->CCER &= ~TIM_CCER_CC6E;
7678
7679 /* Get the TIMx CR2 register value */
7680 tmpcr2 = TIMx->CR2;
7681 /* Get the TIMx CCMR1 register value */
7682 tmpccmrx = TIMx->CCMR3;
7683
7684 /* Reset the Output Compare Mode Bits */
7685 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7686 /* Select the Output Compare Mode */
7687 tmpccmrx |= (OC_Config->OCMode << 8U);
7688
7689 /* Reset the Output Polarity level */
7690 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7691 /* Set the Output Compare Polarity */
7692 tmpccer |= (OC_Config->OCPolarity << 20U);
7693
7694 if (IS_TIM_BREAK_INSTANCE(TIMx))
7695 {
7696 /* Reset the Output Compare IDLE State */
7697 tmpcr2 &= ~TIM_CR2_OIS6;
7698 /* Set the Output Idle state */
7699 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7700 }
7701
7702 /* Write to TIMx CR2 */
7703 TIMx->CR2 = tmpcr2;
7704
7705 /* Write to TIMx CCMR3 */
7706 TIMx->CCMR3 = tmpccmrx;
7707
7708 /* Set the Capture Compare Register value */
7709 TIMx->CCR6 = OC_Config->Pulse;
7710
7711 /* Write to TIMx CCER */
7712 TIMx->CCER = tmpccer;
7713 }
7714
7715 /**
7716 * @brief Slave Timer configuration function
7717 * @param htim TIM handle
7718 * @param sSlaveConfig Slave timer configuration
7719 * @retval None
7720 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7721 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7722 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7723 {
7724 HAL_StatusTypeDef status = HAL_OK;
7725 uint32_t tmpsmcr;
7726 uint32_t tmpccmr1;
7727 uint32_t tmpccer;
7728
7729 /* Get the TIMx SMCR register value */
7730 tmpsmcr = htim->Instance->SMCR;
7731
7732 /* Reset the Trigger Selection Bits */
7733 tmpsmcr &= ~TIM_SMCR_TS;
7734 /* Set the Input Trigger source */
7735 tmpsmcr |= sSlaveConfig->InputTrigger;
7736
7737 /* Reset the slave mode Bits */
7738 tmpsmcr &= ~TIM_SMCR_SMS;
7739 /* Set the slave mode */
7740 tmpsmcr |= sSlaveConfig->SlaveMode;
7741
7742 /* Write to TIMx SMCR */
7743 htim->Instance->SMCR = tmpsmcr;
7744
7745 /* Configure the trigger prescaler, filter, and polarity */
7746 switch (sSlaveConfig->InputTrigger)
7747 {
7748 case TIM_TS_ETRF:
7749 {
7750 /* Check the parameters */
7751 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7752 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7753 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7754 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7755 /* Configure the ETR Trigger source */
7756 TIM_ETR_SetConfig(htim->Instance,
7757 sSlaveConfig->TriggerPrescaler,
7758 sSlaveConfig->TriggerPolarity,
7759 sSlaveConfig->TriggerFilter);
7760 break;
7761 }
7762
7763 case TIM_TS_TI1F_ED:
7764 {
7765 /* Check the parameters */
7766 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7767 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7768
7769 if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
7770 (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7771 {
7772 return HAL_ERROR;
7773 }
7774
7775 /* Disable the Channel 1: Reset the CC1E Bit */
7776 tmpccer = htim->Instance->CCER;
7777 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7778 tmpccmr1 = htim->Instance->CCMR1;
7779
7780 /* Set the filter */
7781 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7782 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7783
7784 /* Write to TIMx CCMR1 and CCER registers */
7785 htim->Instance->CCMR1 = tmpccmr1;
7786 htim->Instance->CCER = tmpccer;
7787 break;
7788 }
7789
7790 case TIM_TS_TI1FP1:
7791 {
7792 /* Check the parameters */
7793 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7794 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7795 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7796
7797 /* Configure TI1 Filter and Polarity */
7798 TIM_TI1_ConfigInputStage(htim->Instance,
7799 sSlaveConfig->TriggerPolarity,
7800 sSlaveConfig->TriggerFilter);
7801 break;
7802 }
7803
7804 case TIM_TS_TI2FP2:
7805 {
7806 /* Check the parameters */
7807 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7808 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7809 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7810
7811 /* Configure TI2 Filter and Polarity */
7812 TIM_TI2_ConfigInputStage(htim->Instance,
7813 sSlaveConfig->TriggerPolarity,
7814 sSlaveConfig->TriggerFilter);
7815 break;
7816 }
7817
7818 case TIM_TS_ITR0:
7819 case TIM_TS_ITR1:
7820 case TIM_TS_ITR2:
7821 case TIM_TS_ITR3:
7822 case TIM_TS_ITR4:
7823 case TIM_TS_ITR5:
7824 case TIM_TS_ITR6:
7825 case TIM_TS_ITR7:
7826 case TIM_TS_ITR8:
7827 case TIM_TS_ITR11:
7828 {
7829 /* Check the parameter */
7830 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7831 break;
7832 }
7833
7834 default:
7835 status = HAL_ERROR;
7836 break;
7837 }
7838
7839 return status;
7840 }
7841
7842 /**
7843 * @brief Configure the TI1 as Input.
7844 * @param TIMx to select the TIM peripheral.
7845 * @param TIM_ICPolarity The Input Polarity.
7846 * This parameter can be one of the following values:
7847 * @arg TIM_ICPOLARITY_RISING
7848 * @arg TIM_ICPOLARITY_FALLING
7849 * @arg TIM_ICPOLARITY_BOTHEDGE
7850 * @param TIM_ICSelection specifies the input to be used.
7851 * This parameter can be one of the following values:
7852 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7853 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7854 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7855 * @param TIM_ICFilter Specifies the Input Capture Filter.
7856 * This parameter must be a value between 0x00 and 0x0F.
7857 * @retval None
7858 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7859 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7860 * protected against un-initialized filter and polarity values.
7861 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7862 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7863 uint32_t TIM_ICFilter)
7864 {
7865 uint32_t tmpccmr1;
7866 uint32_t tmpccer;
7867
7868 /* Disable the Channel 1: Reset the CC1E Bit */
7869 tmpccer = TIMx->CCER;
7870 TIMx->CCER &= ~TIM_CCER_CC1E;
7871 tmpccmr1 = TIMx->CCMR1;
7872
7873 /* Select the Input */
7874 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7875 {
7876 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7877 tmpccmr1 |= TIM_ICSelection;
7878 }
7879 else
7880 {
7881 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7882 }
7883
7884 /* Set the filter */
7885 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7886 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7887
7888 /* Select the Polarity and set the CC1E Bit */
7889 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7890 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7891
7892 /* Write to TIMx CCMR1 and CCER registers */
7893 TIMx->CCMR1 = tmpccmr1;
7894 TIMx->CCER = tmpccer;
7895 }
7896
7897 /**
7898 * @brief Configure the Polarity and Filter for TI1.
7899 * @param TIMx to select the TIM peripheral.
7900 * @param TIM_ICPolarity The Input Polarity.
7901 * This parameter can be one of the following values:
7902 * @arg TIM_ICPOLARITY_RISING
7903 * @arg TIM_ICPOLARITY_FALLING
7904 * @arg TIM_ICPOLARITY_BOTHEDGE
7905 * @param TIM_ICFilter Specifies the Input Capture Filter.
7906 * This parameter must be a value between 0x00 and 0x0F.
7907 * @retval None
7908 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7909 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7910 {
7911 uint32_t tmpccmr1;
7912 uint32_t tmpccer;
7913
7914 /* Disable the Channel 1: Reset the CC1E Bit */
7915 tmpccer = TIMx->CCER;
7916 TIMx->CCER &= ~TIM_CCER_CC1E;
7917 tmpccmr1 = TIMx->CCMR1;
7918
7919 /* Set the filter */
7920 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7921 tmpccmr1 |= (TIM_ICFilter << 4U);
7922
7923 /* Select the Polarity and set the CC1E Bit */
7924 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7925 tmpccer |= TIM_ICPolarity;
7926
7927 /* Write to TIMx CCMR1 and CCER registers */
7928 TIMx->CCMR1 = tmpccmr1;
7929 TIMx->CCER = tmpccer;
7930 }
7931
7932 /**
7933 * @brief Configure the TI2 as Input.
7934 * @param TIMx to select the TIM peripheral
7935 * @param TIM_ICPolarity The Input Polarity.
7936 * This parameter can be one of the following values:
7937 * @arg TIM_ICPOLARITY_RISING
7938 * @arg TIM_ICPOLARITY_FALLING
7939 * @arg TIM_ICPOLARITY_BOTHEDGE
7940 * @param TIM_ICSelection specifies the input to be used.
7941 * This parameter can be one of the following values:
7942 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7943 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7944 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7945 * @param TIM_ICFilter Specifies the Input Capture Filter.
7946 * This parameter must be a value between 0x00 and 0x0F.
7947 * @retval None
7948 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7949 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7950 * protected against un-initialized filter and polarity values.
7951 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7952 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7953 uint32_t TIM_ICFilter)
7954 {
7955 uint32_t tmpccmr1;
7956 uint32_t tmpccer;
7957
7958 /* Disable the Channel 2: Reset the CC2E Bit */
7959 tmpccer = TIMx->CCER;
7960 TIMx->CCER &= ~TIM_CCER_CC2E;
7961 tmpccmr1 = TIMx->CCMR1;
7962
7963 /* Select the Input */
7964 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7965 tmpccmr1 |= (TIM_ICSelection << 8U);
7966
7967 /* Set the filter */
7968 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7969 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7970
7971 /* Select the Polarity and set the CC2E Bit */
7972 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7973 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7974
7975 /* Write to TIMx CCMR1 and CCER registers */
7976 TIMx->CCMR1 = tmpccmr1 ;
7977 TIMx->CCER = tmpccer;
7978 }
7979
7980 /**
7981 * @brief Configure the Polarity and Filter for TI2.
7982 * @param TIMx to select the TIM peripheral.
7983 * @param TIM_ICPolarity The Input Polarity.
7984 * This parameter can be one of the following values:
7985 * @arg TIM_ICPOLARITY_RISING
7986 * @arg TIM_ICPOLARITY_FALLING
7987 * @arg TIM_ICPOLARITY_BOTHEDGE
7988 * @param TIM_ICFilter Specifies the Input Capture Filter.
7989 * This parameter must be a value between 0x00 and 0x0F.
7990 * @retval None
7991 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7992 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7993 {
7994 uint32_t tmpccmr1;
7995 uint32_t tmpccer;
7996
7997 /* Disable the Channel 2: Reset the CC2E Bit */
7998 tmpccer = TIMx->CCER;
7999 TIMx->CCER &= ~TIM_CCER_CC2E;
8000 tmpccmr1 = TIMx->CCMR1;
8001
8002 /* Set the filter */
8003 tmpccmr1 &= ~TIM_CCMR1_IC2F;
8004 tmpccmr1 |= (TIM_ICFilter << 12U);
8005
8006 /* Select the Polarity and set the CC2E Bit */
8007 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8008 tmpccer |= (TIM_ICPolarity << 4U);
8009
8010 /* Write to TIMx CCMR1 and CCER registers */
8011 TIMx->CCMR1 = tmpccmr1 ;
8012 TIMx->CCER = tmpccer;
8013 }
8014
8015 /**
8016 * @brief Configure the TI3 as Input.
8017 * @param TIMx to select the TIM peripheral
8018 * @param TIM_ICPolarity The Input Polarity.
8019 * This parameter can be one of the following values:
8020 * @arg TIM_ICPOLARITY_RISING
8021 * @arg TIM_ICPOLARITY_FALLING
8022 * @arg TIM_ICPOLARITY_BOTHEDGE
8023 * @param TIM_ICSelection specifies the input to be used.
8024 * This parameter can be one of the following values:
8025 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
8026 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
8027 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
8028 * @param TIM_ICFilter Specifies the Input Capture Filter.
8029 * This parameter must be a value between 0x00 and 0x0F.
8030 * @retval None
8031 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
8032 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8033 * protected against un-initialized filter and polarity values.
8034 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8035 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8036 uint32_t TIM_ICFilter)
8037 {
8038 uint32_t tmpccmr2;
8039 uint32_t tmpccer;
8040
8041 /* Disable the Channel 3: Reset the CC3E Bit */
8042 tmpccer = TIMx->CCER;
8043 TIMx->CCER &= ~TIM_CCER_CC3E;
8044 tmpccmr2 = TIMx->CCMR2;
8045
8046 /* Select the Input */
8047 tmpccmr2 &= ~TIM_CCMR2_CC3S;
8048 tmpccmr2 |= TIM_ICSelection;
8049
8050 /* Set the filter */
8051 tmpccmr2 &= ~TIM_CCMR2_IC3F;
8052 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
8053
8054 /* Select the Polarity and set the CC3E Bit */
8055 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
8056 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
8057
8058 /* Write to TIMx CCMR2 and CCER registers */
8059 TIMx->CCMR2 = tmpccmr2;
8060 TIMx->CCER = tmpccer;
8061 }
8062
8063 /**
8064 * @brief Configure the TI4 as Input.
8065 * @param TIMx to select the TIM peripheral
8066 * @param TIM_ICPolarity The Input Polarity.
8067 * This parameter can be one of the following values:
8068 * @arg TIM_ICPOLARITY_RISING
8069 * @arg TIM_ICPOLARITY_FALLING
8070 * @arg TIM_ICPOLARITY_BOTHEDGE
8071 * @param TIM_ICSelection specifies the input to be used.
8072 * This parameter can be one of the following values:
8073 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
8074 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
8075 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
8076 * @param TIM_ICFilter Specifies the Input Capture Filter.
8077 * This parameter must be a value between 0x00 and 0x0F.
8078 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
8079 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8080 * protected against un-initialized filter and polarity values.
8081 * @retval None
8082 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8083 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8084 uint32_t TIM_ICFilter)
8085 {
8086 uint32_t tmpccmr2;
8087 uint32_t tmpccer;
8088
8089 /* Disable the Channel 4: Reset the CC4E Bit */
8090 tmpccer = TIMx->CCER;
8091 TIMx->CCER &= ~TIM_CCER_CC4E;
8092 tmpccmr2 = TIMx->CCMR2;
8093
8094 /* Select the Input */
8095 tmpccmr2 &= ~TIM_CCMR2_CC4S;
8096 tmpccmr2 |= (TIM_ICSelection << 8U);
8097
8098 /* Set the filter */
8099 tmpccmr2 &= ~TIM_CCMR2_IC4F;
8100 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
8101
8102 /* Select the Polarity and set the CC4E Bit */
8103 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
8104 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
8105
8106 /* Write to TIMx CCMR2 and CCER registers */
8107 TIMx->CCMR2 = tmpccmr2;
8108 TIMx->CCER = tmpccer ;
8109 }
8110
8111 /**
8112 * @brief Selects the Input Trigger source
8113 * @param TIMx to select the TIM peripheral
8114 * @param InputTriggerSource The Input Trigger source.
8115 * This parameter can be one of the following values:
8116 * @arg TIM_TS_ITR0: Internal Trigger 0
8117 * @arg TIM_TS_ITR1: Internal Trigger 1
8118 * @arg TIM_TS_ITR2: Internal Trigger 2
8119 * @arg TIM_TS_ITR3: Internal Trigger 3
8120 * @arg TIM_TS_ITR4: Internal Trigger 4
8121 * @arg TIM_TS_ITR5: Internal Trigger 5
8122 * @arg TIM_TS_ITR6: Internal Trigger 6
8123 * @arg TIM_TS_ITR7: Internal Trigger 7
8124 * @arg TIM_TS_ITR8: Internal Trigger 8
8125 * @arg TIM_TS_ITR11: Internal Trigger 11
8126 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
8127 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
8128 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
8129 * @arg TIM_TS_ETRF: External Trigger input
8130 * @retval None
8131 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)8132 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
8133 {
8134 uint32_t tmpsmcr;
8135
8136 /* Get the TIMx SMCR register value */
8137 tmpsmcr = TIMx->SMCR;
8138 /* Reset the TS Bits */
8139 tmpsmcr &= ~TIM_SMCR_TS;
8140 /* Set the Input Trigger source and the slave mode*/
8141 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8142 /* Write to TIMx SMCR */
8143 TIMx->SMCR = tmpsmcr;
8144 }
8145 /**
8146 * @brief Configures the TIMx External Trigger (ETR).
8147 * @param TIMx to select the TIM peripheral
8148 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
8149 * This parameter can be one of the following values:
8150 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
8151 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
8152 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
8153 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
8154 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
8155 * This parameter can be one of the following values:
8156 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
8157 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
8158 * @param ExtTRGFilter External Trigger Filter.
8159 * This parameter must be a value between 0x00 and 0x0F
8160 * @retval None
8161 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)8162 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
8163 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
8164 {
8165 uint32_t tmpsmcr;
8166
8167 tmpsmcr = TIMx->SMCR;
8168
8169 /* Reset the ETR Bits */
8170 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8171
8172 /* Set the Prescaler, the Filter value and the Polarity */
8173 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8174
8175 /* Write to TIMx SMCR */
8176 TIMx->SMCR = tmpsmcr;
8177 }
8178
8179 /**
8180 * @brief Enables or disables the TIM Capture Compare Channel x.
8181 * @param TIMx to select the TIM peripheral
8182 * @param Channel specifies the TIM Channel
8183 * This parameter can be one of the following values:
8184 * @arg TIM_CHANNEL_1: TIM Channel 1
8185 * @arg TIM_CHANNEL_2: TIM Channel 2
8186 * @arg TIM_CHANNEL_3: TIM Channel 3
8187 * @arg TIM_CHANNEL_4: TIM Channel 4
8188 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
8189 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
8190 * @param ChannelState specifies the TIM Channel CCxE bit new state.
8191 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
8192 * @retval None
8193 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)8194 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
8195 {
8196 uint32_t tmp;
8197
8198 /* Check the parameters */
8199 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
8200 assert_param(IS_TIM_CHANNELS(Channel));
8201
8202 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8203
8204 /* Reset the CCxE Bit */
8205 TIMx->CCER &= ~tmp;
8206
8207 /* Set or reset the CCxE Bit */
8208 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8209 }
8210
8211 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
8212 /**
8213 * @brief Reset interrupt callbacks to the legacy weak callbacks.
8214 * @param htim pointer to a TIM_HandleTypeDef structure that contains
8215 * the configuration information for TIM module.
8216 * @retval None
8217 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)8218 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
8219 {
8220 /* Reset the TIM callback to the legacy weak callbacks */
8221 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
8222 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
8223 htim->TriggerCallback = HAL_TIM_TriggerCallback;
8224 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
8225 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
8226 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
8227 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
8228 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
8229 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
8230 htim->ErrorCallback = HAL_TIM_ErrorCallback;
8231 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
8232 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
8233 htim->BreakCallback = HAL_TIMEx_BreakCallback;
8234 htim->Break2Callback = HAL_TIMEx_Break2Callback;
8235 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
8236 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
8237 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
8238 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
8239 }
8240 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
8241
8242 /**
8243 * @}
8244 */
8245
8246 #endif /* HAL_TIM_MODULE_ENABLED */
8247 /**
8248 * @}
8249 */
8250
8251 /**
8252 * @}
8253 */
8254
