Home
last modified time | relevance | path

Searched refs:u (Results 1 – 25 of 516) sorted by relevance

12345678910>>...21

/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_NVIC.h130 #define S32_NVIC_ICTR_ICTR_SHIFT 0u
135 #define S32_NVIC_ISER_SETENA_SHIFT 0u
140 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
145 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
150 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
155 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
160 #define S32_NVIC_IP_PRI0_SHIFT 0u
164 #define S32_NVIC_IP_PRI1_SHIFT 0u
168 #define S32_NVIC_IP_PRI2_SHIFT 0u
172 #define S32_NVIC_IP_PRI3_SHIFT 0u
[all …]
DS32Z2_SCB.h172 #define S32_SCB_ACTLR_ACTLR_SHIFT 0u
177 #define S32_SCB_CPUID_REVISION_SHIFT 0u
194 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
240 #define S32_SCB_AIRCR_AIRCR_SHIFT 0u
258 #define S32_SCB_CCR_CCR_SHIFT 0u
263 #define S32_SCB_SHPR1_SHPR1_SHIFT 0u
268 #define S32_SCB_SHPR2_SHPR2_SHIFT 0u
273 #define S32_SCB_SHPR3_SHPR3_SHIFT 0u
278 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
335 #define S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT 0u
[all …]
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_NVIC.h123 #define S32_NVIC_ICTR_ICTR_SHIFT 0u
128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
[all …]
DS32K344_SCB.h170 #define S32_SCB_ACTLR_ACTLR_SHIFT 0u
175 #define S32_SCB_CPUID_REVISION_SHIFT 0u
192 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
238 #define S32_SCB_AIRCR_AIRCR_SHIFT 0u
256 #define S32_SCB_CCR_CCR_SHIFT 0u
261 #define S32_SCB_SHPR1_SHPR1_SHIFT 0u
266 #define S32_SCB_SHPR2_SHPR2_SHIFT 0u
271 #define S32_SCB_SHPR3_SHPR3_SHIFT 0u
276 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
333 #define S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT 0u
[all …]
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142W_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
DS32K148_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
DS32K146_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
DS32K142_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
DS32K144W_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
DS32K144_NVIC.h128 #define S32_NVIC_ISER_SETENA_SHIFT 0u
133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
153 #define S32_NVIC_IP_PRI0_SHIFT 0u
157 #define S32_NVIC_IP_PRI1_SHIFT 0u
161 #define S32_NVIC_IP_PRI2_SHIFT 0u
165 #define S32_NVIC_IP_PRI3_SHIFT 0u
169 #define S32_NVIC_IP_PRI4_SHIFT 0u
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c261 uint16 NumberOfCmdWrites = 0u; in Spi_Ip_WriteCmdFifo()
311 if ( (0u != (SrStatusRegister & (SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK))) ) in Spi_Ip_TransferProcess()
320 if(NumberOfReads != 0u) in Spi_Ip_TransferProcess()
330 if (State->ExpectedCmdFifoWrites != 0u) in Spi_Ip_TransferProcess()
346 if(State->CurrentTxFifoSlot != 0u) in Spi_Ip_TransferProcess()
350 State->CurrentTxFifoSlot = 0u; in Spi_Ip_TransferProcess()
385 if (0u != (FrameSize % 32u)) in Spi_Ip_CalculateFifoWords()
434 DevAssert(State->NbCmds > 0u); in Spi_Ip_UpdateCtarAndPushr()
453 for (i = 0u; i < State->NbCmds; i++) { in Spi_Ip_UpdateCtarAndPushr()
456 SPI_CTAR_LSBFE(Dev->DeviceParams->Lsb ? 1u : 0u); in Spi_Ip_UpdateCtarAndPushr()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c94 context->xSize = 0u; in smartcard_emvsim_CompleteSendData()
116 while (((base->RX_STATUS & EMVSIM_RX_STATUS_RX_CNT_MASK) != 0u) && ((context->xSize) > 0u)) in smartcard_emvsim_CompleteReceiveData()
143 uint32_t delay = 0u; in smartcard_emvsim_StartSendData()
144 uint32_t control = 0u; in smartcard_emvsim_StartSendData()
151 base->CTRL = 0u; in smartcard_emvsim_StartSendData()
165 while ((base->TX_STATUS & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) == 0u) in smartcard_emvsim_StartSendData()
248 uint16_t temp16 = 0u; in smartcard_emvsim_SetTransferType()
249 uint32_t bwiVal = 0u; in smartcard_emvsim_SetTransferType()
250 uint8_t tdt = 0u; in smartcard_emvsim_SetTransferType()
418 if ((NULL == context) || (srcClock_Hz == 0u)) in SMARTCARD_EMVSIM_Init()
[all …]
Dfsl_smartcard_usim.c124 while ((base->FSR & USIM_FSR_TX_LENGTH_MASK) != 0u) in SMARTCARD_USIM_CompleteSendData()
131 context->xSize = 0u; in SMARTCARD_USIM_CompleteSendData()
153 while (((base->FSR & USIM_FSR_RX_LENGTH_MASK) != 0u) && ((context->xSize) > 0u)) in SMARTCARD_USIM_CompleteReceiveData()
250 uint16_t temp16 = 0u; in SMARTCARD_USIM_SetTransferType()
251 uint32_t bwiVal = 0u; in SMARTCARD_USIM_SetTransferType()
509 uint32_t instance = 0u; in SMARTCARD_USIM_Deinit()
511 while ((base->FSR & USIM_FSR_TX_LENGTH_MASK) != 0u) in SMARTCARD_USIM_Deinit()
514 while ((base->LSR & USIM_LSR_TX_WORKING_MASK) != 0u) in SMARTCARD_USIM_Deinit()
553 if ((0u == xfer->size)) in SMARTCARD_USIM_TransferNonBlocking()
690 if (((base->IIR & USIM_IIR_CWT_MASK) != 0u) && ((base->IER & USIM_IER_CWT_MASK) != 0u)) in SMARTCARD_USIM_IRQHandler()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/puf_v3/
Dfsl_puf_v3.c49 while (0u == base->SR) in puf_waitForInit()
54 while ((base->SR & PUF_SR_BUSY_MASK) != 0u) in puf_waitForInit()
74 while (0u == (PUF_SRAM_STATUS_READY_MASK & base->SRAM_STATUS)) in puf_powerOn()
110 if ((result == kPUF_ResultOK) && (0u == (base->SR & PUF_SR_ERROR_MASK))) in puf_makeStatus()
256 while (0u != (base->CR & PUF_CR_ENROLL_MASK)) in PUF_Enroll()
261 while (0u != (base->SR & PUF_SR_BUSY_MASK)) in PUF_Enroll()
263 if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) in PUF_Enroll()
276 if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) in PUF_Enroll()
334 while (0u != (base->CR & PUF_CR_START_MASK)) in PUF_Start()
339 while (0u != (base->SR & PUF_SR_BUSY_MASK)) in PUF_Start()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/conn_fwloader/include/
Dfusemap.h15 #define OTP_LOCK_CFG0_FUSE_IDX (0u)
18 #define OTP_BOOT_CFG_LOCK_FUSE_IDX (0u)
19 #define OTP_BOOT_CFG_LOCK_FUSE_SHIFT (0u)
25 #define OTP_SEC_BOOT_CFG_LOCK_FUSE_IDX (0u)
33 #define OTP_DCFG_CC_SOCU_LOCK_FUSE_IDX (0u)
41 #define OTP_DCFG_CC_SOCU_NS_LOCK_FUSE_IDX (0u)
49 #define OTP_LOCK_CFG_LOCK_FUSE_IDX (0u)
61 #define OTP_CUST_KEY_LOCK_FUSE_SHIFT (0u)
101 #define OTP_OTP_SHARE_LOCK_FUSE_SHIFT (0u)
139 #define OTP_TSENS_CAU_MIN_FUSE_SHIFT (0u)
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/rtt/RTT/
DSEGGER_RTT_printf.c134 p->Cnt = 0u; in _StoreChar()
175 if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) in _PrintUnsigned()
177 if (FieldWidth != 0u) in _PrintUnsigned()
179 if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) in _PrintUnsigned()
187 while ((FieldWidth != 0u) && (Width < FieldWidth)) in _PrintUnsigned()
241 if (FieldWidth != 0u) in _PrintUnsigned()
243 while ((FieldWidth != 0u) && (Width < FieldWidth)) in _PrintUnsigned()
286 …if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_… in _PrintInt()
294 if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && in _PrintInt()
295 ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) in _PrintInt()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c387 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
411 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
438 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
462 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
489 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
513 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
540 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
564 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
591 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
615 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++) in ISR()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/elemu/
Dfsl_elemu.c52 while ((mu->TSR & mask) == 0u) in ELEMU_mu_hal_send_data()
62 while ((mu->RSR & mask) == 0u) in ELEMU_mu_hal_receive_data()
66 while (((mu->RSR & mask) != 0u) && (read_retries != 0u)) in ELEMU_mu_hal_receive_data()
78 while ((mu->RSR & mask) == 0u) in ELEMU_mu_hal_receive_data_wait()
80 if (--wait == 0u) in ELEMU_mu_hal_receive_data_wait()
89 while (((mu->RSR & mask) != 0u) && (read_retries != 0u)) in ELEMU_mu_hal_receive_data_wait()
101 uint8_t tx_reg_idx = 0u; in ELEMU_mu_send_message()
102 uint8_t counter = 0u; in ELEMU_mu_send_message()
114 while (wordCount > 0u) in ELEMU_mu_send_message()
136 if (wait == 0u) in ELEMU_mu_wait_for_ready()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_ele_base_api.c46 uint32_t rmsg[MSG_RESPONSE_MAX] = {0u}; in ele_mu_get_response_baseapi()
94 uint32_t tmsg[PING_SIZE] = {0u}; in ELE_BaseAPI_Ping()
95 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_Ping()
138 uint32_t tmsg[GET_FW_VERSION_SIZE] = {0u}; in ELE_BaseAPI_GetFwVersion()
139 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_GetFwVersion()
183 uint32_t tmsg[ENABLE_APC_SIZE] = {0u}; in ELE_BaseAPI_EnableAPC()
184 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_EnableAPC()
231 uint32_t tmsg[FORWARD_LIFECYCLE_SIZE] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
232 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
273 uint32_t tmsg[CLOCK_CHANGE_START_SIZE] = {0u}; in ELE_BaseAPI_ClockChangeStart()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_ele_base_api.c46 uint32_t rmsg[MSG_RESPONSE_MAX] = {0u}; in ele_mu_get_response_baseapi()
94 uint32_t tmsg[PING_SIZE] = {0u}; in ELE_BaseAPI_Ping()
95 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_Ping()
138 uint32_t tmsg[GET_FW_VERSION_SIZE] = {0u}; in ELE_BaseAPI_GetFwVersion()
139 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_GetFwVersion()
183 uint32_t tmsg[ENABLE_APC_SIZE] = {0u}; in ELE_BaseAPI_EnableAPC()
184 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_EnableAPC()
231 uint32_t tmsg[FORWARD_LIFECYCLE_SIZE] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
232 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
273 uint32_t tmsg[CLOCK_CHANGE_START_SIZE] = {0u}; in ELE_BaseAPI_ClockChangeStart()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_ele_base_api.c46 uint32_t rmsg[MSG_RESPONSE_MAX] = {0u}; in ele_mu_get_response_baseapi()
94 uint32_t tmsg[PING_SIZE] = {0u}; in ELE_BaseAPI_Ping()
95 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_Ping()
138 uint32_t tmsg[GET_FW_VERSION_SIZE] = {0u}; in ELE_BaseAPI_GetFwVersion()
139 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_GetFwVersion()
183 uint32_t tmsg[ENABLE_APC_SIZE] = {0u}; in ELE_BaseAPI_EnableAPC()
184 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_EnableAPC()
231 uint32_t tmsg[FORWARD_LIFECYCLE_SIZE] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
232 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
273 uint32_t tmsg[CLOCK_CHANGE_START_SIZE] = {0u}; in ELE_BaseAPI_ClockChangeStart()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_ele_base_api.c46 uint32_t rmsg[MSG_RESPONSE_MAX] = {0u}; in ele_mu_get_response_baseapi()
94 uint32_t tmsg[PING_SIZE] = {0u}; in ELE_BaseAPI_Ping()
95 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_Ping()
138 uint32_t tmsg[GET_FW_VERSION_SIZE] = {0u}; in ELE_BaseAPI_GetFwVersion()
139 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_GetFwVersion()
183 uint32_t tmsg[ENABLE_APC_SIZE] = {0u}; in ELE_BaseAPI_EnableAPC()
184 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_EnableAPC()
231 uint32_t tmsg[FORWARD_LIFECYCLE_SIZE] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
232 uint32_t rmsg[S3MU_RR_COUNT] = {0u}; in ELE_BaseAPI_ForwardLifecycle()
273 uint32_t tmsg[CLOCK_CHANGE_START_SIZE] = {0u}; in ELE_BaseAPI_ClockChangeStart()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/iee_apc/
Dfsl_iee_apc.c34 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_GlobalEnable()
56 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_GlobalDisable()
81 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
98 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
111 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
123 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
135 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
147 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
159 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
171 #if defined(FSL_FEATURE_IEE_APC_USE_GPR) && (FSL_FEATURE_IEE_APC_USE_GPR > 0u) in IEE_APC_SetRegionConfig()
[all …]
/hal_nxp-latest/mcux/middleware/mcux-secure-subsystem/src/sscp/
Dfsl_sss_sscp.c27 uint32_t ret = 0u; in sss_sscp_open_session()
56 uint32_t ret = 0u; in sss_sscp_close_session()
66 op.resultCount = 0u; in sss_sscp_close_session()
87 uint32_t ret = 0u; in sss_sscp_symmetric_context_init()
128 uint32_t ret = 0u; in sss_sscp_cipher_one_go()
145 op.resultCount = 0u; in sss_sscp_cipher_one_go()
161 uint32_t ret = 0u; in sss_sscp_cipher_init()
187 uint32_t ret = 0u; in sss_sscp_cipher_update()
208 *destLen = 0u; in sss_sscp_cipher_update()
227 uint32_t ret = 0u; in sss_sscp_cipher_finish()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/s3mu/
Dfsl_s3mu.c57 uint8_t tx_reg_idx = 0u; in S3MU_SendMessage()
58 uint8_t counter = 0u; in S3MU_SendMessage()
66 while (wordCount != 0u) in S3MU_SendMessage()
83 while ((mu->TSR & mask) == 0u) in s3mu_hal_send_data()
130 uint32_t msg_size = 0u; in S3MU_ReadMessage()
131 uint32_t rx_reg_idx = 0u; in S3MU_ReadMessage()
154 while (msg_size != 0u) in S3MU_ReadMessage()
172 while ((mu->RSR & mask) == 0u) in s3mu_hal_receive_data()
216 uint8_t counter = 0u; in s3mu_read_data_wait()
217 uint8_t rx_reg_idx = 0u; in s3mu_read_data_wait()
[all …]

12345678910>>...21