Lines Matching refs:u
170 #define S32_SCB_ACTLR_ACTLR_SHIFT 0u
175 #define S32_SCB_CPUID_REVISION_SHIFT 0u
192 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
238 #define S32_SCB_AIRCR_AIRCR_SHIFT 0u
256 #define S32_SCB_CCR_CCR_SHIFT 0u
261 #define S32_SCB_SHPR1_SHPR1_SHIFT 0u
266 #define S32_SCB_SHPR2_SHPR2_SHIFT 0u
271 #define S32_SCB_SHPR3_SHPR3_SHIFT 0u
276 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
333 #define S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT 0u
410 #define S32_SCB_HFSR_HFSR_SHIFT 0u
415 #define S32_SCB_DFSR_DFSR_SHIFT 0u
420 #define S32_SCB_MMFAR_MMFAR_SHIFT 0u
425 #define S32_SCB_BFAR_BFAR_SHIFT 0u
430 #define S32_SCB_AFSR_AFSR_SHIFT 0u
435 #define S32_SCB_ID_PFR0_ID_PFR0_SHIFT 0u
440 #define S32_SCB_ID_PFR1_ID_PFR1_SHIFT 0u
445 #define S32_SCB_ID_DFR0_ID_DFR0_SHIFT 0u
450 #define S32_SCB_ID_AFR0_ID_AFR0_SHIFT 0u
455 #define S32_SCB_ID_MMFR_ID_MMFR0_SHIFT 0u
459 #define S32_SCB_ID_MMFR_ID_MMFR1_SHIFT 0u
463 #define S32_SCB_ID_MMFR_ID_MMFR2_SHIFT 0u
467 #define S32_SCB_ID_MMFR_ID_MMFR3_SHIFT 0u
472 #define S32_SCB_ID_ISAR_ID_ISAR0_SHIFT 0u
476 #define S32_SCB_ID_ISAR_ID_ISAR1_SHIFT 0u
480 #define S32_SCB_ID_ISAR_ID_ISAR2_SHIFT 0u
484 #define S32_SCB_ID_ISAR_ID_ISAR3_SHIFT 0u
488 #define S32_SCB_ID_ISAR_ID_ISAR4_SHIFT 0u
493 #define S32_SCB_CLIDR_CLIDR_SHIFT 0u
498 #define S32_SCB_CTR_CTR_SHIFT 0u
503 #define S32_SCB_CCSIDR_CCSIDR_SHIFT 0u
508 #define S32_SCB_CSSELR_CSSELR_SHIFT 0u
513 #define S32_SCB_STIR_STIR_SHIFT 0u
518 #define S32_SCB_FPCCR_FPCCR_SHIFT 0u
523 #define S32_SCB_FPCAR_FPCAR_SHIFT 0u
528 #define S32_SCB_FPDSCR_FPDSCR_SHIFT 0u
533 #define S32_SCB_ICIALLU_ICIALLU_SHIFT 0u
538 #define S32_SCB_ICIMVAU_ICIMVAU_SHIFT 0u
543 #define S32_SCB_DCIMVAC_DCIMVAC_SHIFT 0u
548 #define S32_SCB_DCISW_DCISW_SHIFT 0u
553 #define S32_SCB_DCCMVAU_DCCMVAU_SHIFT 0u
558 #define S32_SCB_DCCMVAC_DCCMVAC_SHIFT 0u
563 #define S32_SCB_DCCSW_DCCSW_SHIFT 0u
568 #define S32_SCB_DCCIMVAC_DCCIMVAC_SHIFT 0u
573 #define S32_SCB_DCCISW_DCCISW_SHIFT 0u
578 #define S32_SCB_BPIALL_BPIALL_SHIFT 0u
583 #define S32_SCB_ITCMCR_ITCMCR_SHIFT 0u
588 #define S32_SCB_DTCMCR_DTCMCR_SHIFT 0u
593 #define S32_SCB_AHBPCR_AHBPCR_SHIFT 0u
598 #define S32_SCB_CACR_CACR_SHIFT 0u
603 #define S32_SCB_AHBSCR_AHBSCR_SHIFT 0u
608 #define S32_SCB_ABFSR_ABFSR_SHIFT 0u
613 #define S32_SCB_IEBR0_IEBR0_SHIFT 0u
618 #define S32_SCB_IEBR1h_IEBR1h_SHIFT 0u
623 #define S32_SCB_DEBR0h_DEBR0h_SHIFT 0u
628 #define S32_SCB_DEBR1h_DEBR1h_SHIFT 0u
633 #define S32_SCB_PID_PID0_SHIFT 0u
637 #define S32_SCB_PID_PID1_SHIFT 0u
641 #define S32_SCB_PID_PID2_SHIFT 0u
645 #define S32_SCB_PID_PID3_SHIFT 0u
649 #define S32_SCB_PID_PID4_SHIFT 0u
653 #define S32_SCB_PID_PID5_SHIFT 0u
657 #define S32_SCB_PID_PID6_SHIFT 0u
661 #define S32_SCB_PID_PID7_SHIFT 0u
666 #define S32_SCB_CID_CID0_SHIFT 0u
670 #define S32_SCB_CID_CID1_SHIFT 0u
674 #define S32_SCB_CID_CID2_SHIFT 0u
678 #define S32_SCB_CID_CID3_SHIFT 0u