Lines Matching refs:u
261 uint16 NumberOfCmdWrites = 0u; in Spi_Ip_WriteCmdFifo()
311 if ( (0u != (SrStatusRegister & (SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK))) ) in Spi_Ip_TransferProcess()
320 if(NumberOfReads != 0u) in Spi_Ip_TransferProcess()
330 if (State->ExpectedCmdFifoWrites != 0u) in Spi_Ip_TransferProcess()
346 if(State->CurrentTxFifoSlot != 0u) in Spi_Ip_TransferProcess()
350 State->CurrentTxFifoSlot = 0u; in Spi_Ip_TransferProcess()
385 if (0u != (FrameSize % 32u)) in Spi_Ip_CalculateFifoWords()
434 DevAssert(State->NbCmds > 0u); in Spi_Ip_UpdateCtarAndPushr()
453 for (i = 0u; i < State->NbCmds; i++) { in Spi_Ip_UpdateCtarAndPushr()
456 SPI_CTAR_LSBFE(Dev->DeviceParams->Lsb ? 1u : 0u); in Spi_Ip_UpdateCtarAndPushr()
464 if ((State->PushrCmds[i - 1u] & SPI_IP_PUSHR_CONT_MASK_U16) != 0u) in Spi_Ip_UpdateCtarAndPushr()
512 State->RxIndex = 0u; in Spi_Ip_PrepareTransfer()
513 State->TxIndex = 0u; in Spi_Ip_PrepareTransfer()
531 … if (((State->ExternalDevice->PushrCmd & SPI_IP_PUSHR_CONT_MASK_U16) != 0u) && (Frames > 1u)) in Spi_Ip_PrepareTransfer()
545 State->DTCPValue[1] = 0u; in Spi_Ip_PrepareTransfer()
596 uint8 TCDSGIndex = 0u; in Spi_Ip_CmdDmaTcdSGInit()
599 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_CmdDmaTcdSGInit()
609 DmaTcdList[0u].Value = 0u; /* dummy src address read, it will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
611 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_CmdDmaTcdSGInit()
615 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_CmdDmaTcdSGInit()
616 DmaTcdList[7u].Value = 0u; /* dummy iteration count will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
619 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->NumTxCmdDmaSGId; TCDSGIndex++) in Spi_Ip_CmdDmaTcdSGInit()
626 …ScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyUnitConfig->TxCmdDmaSGId[0u]); in Spi_Ip_CmdDmaTcdSGInit()
635 uint8 TCDSGIndex = 0u; in Spi_Ip_TxDmaTcdSGInit()
638 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_TxDmaTcdSGInit()
654 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_TxDmaTcdSGInit()
655 …DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter according to number of… in Spi_Ip_TxDmaTcdSGInit()
657 …DmaTcdList[9u].Value = 0u; /* dummy no src address modulo, will be updated latter Base on transfe… in Spi_Ip_TxDmaTcdSGInit()
658 DmaTcdList[0u].Value = 0u; /* dummy src address read, will be updated latter Base on TxBuffer */ in Spi_Ip_TxDmaTcdSGInit()
660 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TCDSGIndex++) in Spi_Ip_TxDmaTcdSGInit()
677 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_TxDmaTcdSGConfig()
702 DmaTcdList[7u].Value = 0u; /* no src address modulo */ in Spi_Ip_TxDmaTcdSGConfig()
706 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[TCDSGIndex].DefaultDa… in Spi_Ip_TxDmaTcdSGConfig()
709 DmaTcdList[1u].Value = 0u; /* src offset is 0 byte */ in Spi_Ip_TxDmaTcdSGConfig()
718 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_TxDmaTcdSGConfig()
729 uint8 TCDSGIndex = 0u; in Spi_Ip_RxDmaTcdSGInit()
732 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_RxDmaTcdSGInit()
742 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_RxDmaTcdSGInit()
743 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_RxDmaTcdSGInit()
748 …DmaTcdList[1u].Value = 0u; /* dummy dest address write, will be updated latter Base on RxBuffer… in Spi_Ip_RxDmaTcdSGInit()
749 …DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter Base on number of fram… in Spi_Ip_RxDmaTcdSGInit()
752 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TCDSGIndex++) in Spi_Ip_RxDmaTcdSGInit()
769 DmaTcdList[0u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS; in Spi_Ip_RxDmaTcdSGConfig()
802 … DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Spi_Ip_u32DiscardData; /* dest address write*/ in Spi_Ip_RxDmaTcdSGConfig()
803 DmaTcdList[4u].Value = 0u; /* dest offset is 0 bytes */ in Spi_Ip_RxDmaTcdSGConfig()
807 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->RxBuffer; /* dest address write*/ in Spi_Ip_RxDmaTcdSGConfig()
830 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_CmdDmaTcdSGConfig()
835 DmaTcdList[0u].Value = CmdAdd; /* src address read */ in Spi_Ip_CmdDmaTcdSGConfig()
857 [3] = { DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ , 0u} in Spi_Ip_DmaCmdConfigAndStart()
869 Tcds[2].Value = 0u; /* Enable HW Request */ in Spi_Ip_DmaCmdConfigAndStart()
876 …ScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyUnitConfig->TxCmdDmaSGId[0u]); in Spi_Ip_DmaCmdConfigAndStart()
912 DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; in Spi_Ip_DmaConfig()
937 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_DmaConfig()
939 DmaTcdList[8u].Value = 0u; /* no src address modulo */ in Spi_Ip_DmaConfig()
943 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->ExternalDevice->DeviceParams->DefaultData; /* s… in Spi_Ip_DmaConfig()
946 DmaTcdList[2u].Value = 0u; /* src offset is 0 byte */ in Spi_Ip_DmaConfig()
955 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_DmaConfig()
959 DmaTcdList[9u].Value = 0u; /* No adjust DADD when major loop completed */ in Spi_Ip_DmaConfig()
964 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_DmaConfig()
965 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_DmaConfig()
991 DmaTcdList[6u].Value = 0u; /* dest offset is 0 bytes */ in Spi_Ip_DmaConfig()
1000 DmaTcdList[8u].Value = 0u; /* No adjust DADD when major loop completed */ in Spi_Ip_DmaConfig()
1031 if (0u != (NumberDmaIterWrite%2u)) in Spi_Ip_DmaTxRxUpdateLoop()
1105 uint16 Data = 0u; in Spi_Ip_WriteTxFifo()
1280 uint16 NumberOfWrites = 0u; in Spi_Ip_AsyncStart()
1298 if (State->CurrentTxFifoSlot != 0u) in Spi_Ip_AsyncStart()
1302 State->CurrentTxFifoSlot = 0u; in Spi_Ip_AsyncStart()
1316 NumberOfWrites = 0u; in Spi_Ip_AsyncStart()
1351 DevAssert(0u != Length); in Spi_Ip_CheckValidParameters()
1352 DevAssert(0u != TimeOut); in Spi_Ip_CheckValidParameters()
1355 DevAssert((Length % 4u) == 0u); in Spi_Ip_CheckValidParameters()
1359 DevAssert((Length % 2u) == 0u); in Spi_Ip_CheckValidParameters()
1396 uint32 SrStatusRegister = 0u; in Spi_Ip_IrqDmaHandler()
1406 if ( (0u != (SrStatusRegister & (SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK))) ) in Spi_Ip_IrqDmaHandler()
1490 uint8 Instance = 0u; in Spi_Ip_Init()
1561 Base->RSER = 0u; in Spi_Ip_DeInit()
1594 if (State->ExpectedCmdFifoWrites != 0u) in Spi_Ip_SyncReadWriteStep()
1596 if (Spi_Ip_WriteCmdFifo(State, Base) != 0u) in Spi_Ip_SyncReadWriteStep()
1616 if (State->CurrentTxFifoSlot != 0u) in Spi_Ip_SyncReadWriteStep()
1620 State->CurrentTxFifoSlot = 0u; in Spi_Ip_SyncReadWriteStep()
1631 if(NumberOfReads != 0u) in Spi_Ip_SyncReadWriteStep()
1654 uint32 CurrentTicks = 0u; /* initialize current counter */ in Spi_Ip_SyncTransmit()
1655 uint32 ElapsedTicks = 0u; /* elapsed will give timeout */ in Spi_Ip_SyncTransmit()
1656 uint8 Instance = 0u; in Spi_Ip_SyncTransmit()
1695 ElapsedTicks = 0u; in Spi_Ip_SyncTransmit()
1768 Spi_Ip_DmaAsyncStart(State, Base, (State->TransferMode == SPI_IP_POLLING) ? 0u : 1u); in Spi_Ip_AsyncTransmit()
1789 uint8 Instance = 0u; in Spi_Ip_AsyncTransmitFast()
1790 uint32 LsbValue = 0u; in Spi_Ip_AsyncTransmitFast()
1792 uint8 Count = 0u; in Spi_Ip_AsyncTransmitFast()
1795 DevAssert(NULL_PTR != FastTransferCfg[0u].ExternalDevice); in Spi_Ip_AsyncTransmitFast()
1797 State = Spi_Ip_apxStateStructureArray[FastTransferCfg[0u].ExternalDevice->Instance]; in Spi_Ip_AsyncTransmitFast()
1803 for(Count = 0u; Count < NumberOfTransfer; Count++) in Spi_Ip_AsyncTransmitFast()
1806 DevAssert(0u != FastTransferCfg[Count].Length); in Spi_Ip_AsyncTransmitFast()
1807 if (FastTransferCfg[0u].ExternalDevice->DeviceParams->FrameSize > 16u) in Spi_Ip_AsyncTransmitFast()
1809 DevAssert((FastTransferCfg[Count].Length % 4u) == 0u); in Spi_Ip_AsyncTransmitFast()
1811 else if (FastTransferCfg[0u].ExternalDevice->DeviceParams->FrameSize > 8u) in Spi_Ip_AsyncTransmitFast()
1813 DevAssert((FastTransferCfg[Count].Length % 2u) == 0u); in Spi_Ip_AsyncTransmitFast()
1821 Instance = FastTransferCfg[0u].ExternalDevice->Instance; in Spi_Ip_AsyncTransmitFast()
1847 State->ExternalDevice = FastTransferCfg[0u].ExternalDevice; in Spi_Ip_AsyncTransmitFast()
1856 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ((… in Spi_Ip_AsyncTransmitFast()
1858 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1860 …Base->CTARE[0u] = FastTransferCfg[0u].ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1879 uint8 DisHwRequest = 0u; in Spi_Ip_DmaFastConfig()
1880 uint8 Count = 0u; in Spi_Ip_DmaFastConfig()
1881 uint8 CmdTCDSGIndex = 0u; in Spi_Ip_DmaFastConfig()
1884 DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT; in Spi_Ip_DmaFastConfig()
1885 DmaTcdList[0u].Value = 1u; in Spi_Ip_DmaFastConfig()
1887 for(Count = 0u; Count < NumberOfTransfer; Count++) in Spi_Ip_DmaFastConfig()
1890 State->RxIndex = 0u; in Spi_Ip_DmaFastConfig()
1891 State->TxIndex = 0u; in Spi_Ip_DmaFastConfig()
1929 DisHwRequest = 0u; in Spi_Ip_DmaFastConfig()
1941 …0u /* not disable dma hw request, the transfer will be continued after next software TCD Scatter … in Spi_Ip_DmaFastConfig()
1963 State->ExpectedCmdFifoWrites = 0u; in Spi_Ip_DmaFastConfig()
1982 …ScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyUnitConfig->TxCmdDmaSGId[0u]); in Spi_Ip_DmaFastConfig()
1984 …elScatterGatherConfig(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[0u]); in Spi_Ip_DmaFastConfig()
1986 …elScatterGatherConfig(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitConfig->RxDmaFastSGId[0u]); in Spi_Ip_DmaFastConfig()
2223 uint32 IrqFlags = 0u; in Spi_Ip_IrqHandler()
2230 if(0u != IrqFlags) in Spi_Ip_IrqHandler()