1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142_NVIC.h 10 * @version 1.0 11 * @date 2021-02-18 12 * @brief Peripheral Access Layer for S32K142_NVIC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142_NVIC_H_) /* Check if memory map has not been already included */ 58 #define S32K142_NVIC_H_ 59 60 #include "S32K142_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_NVIC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_NVIC_Peripheral_Access_Layer S32_NVIC Peripheral Access Layer 68 * @{ 69 */ 70 71 72 /** S32_NVIC - Size of Registers Arrays */ 73 #define S32_NVIC_ISER_COUNT 8u 74 #define S32_NVIC_ICER_COUNT 8u 75 #define S32_NVIC_ISPR_COUNT 8u 76 #define S32_NVIC_ICPR_COUNT 8u 77 #define S32_NVIC_IABR_COUNT 8u 78 #define S32_NVIC_IP_COUNT 240u 79 80 /** S32_NVIC - Register Layout Typedef */ 81 typedef struct { 82 __IO uint32_t ISER[S32_NVIC_ISER_COUNT]; /**< Interrupt Set Enable Register n, array offset: 0x0, array step: 0x4 */ 83 uint8_t RESERVED_0[96]; 84 __IO uint32_t ICER[S32_NVIC_ICER_COUNT]; /**< Interrupt Clear Enable Register n, array offset: 0x80, array step: 0x4 */ 85 uint8_t RESERVED_1[96]; 86 __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT]; /**< Interrupt Set Pending Register n, array offset: 0x100, array step: 0x4 */ 87 uint8_t RESERVED_2[96]; 88 __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT]; /**< Interrupt Clear Pending Register n, array offset: 0x180, array step: 0x4 */ 89 uint8_t RESERVED_3[96]; 90 __IO uint32_t IABR[S32_NVIC_IABR_COUNT]; /**< Interrupt Active bit Register n, array offset: 0x200, array step: 0x4 */ 91 uint8_t RESERVED_4[224]; 92 __IO uint8_t IP[S32_NVIC_IP_COUNT]; /**< Interrupt Priority Register n, array offset: 0x300, array step: 0x1 */ 93 uint8_t RESERVED_5[2576]; 94 __O uint32_t STIR; /**< Software Trigger Interrupt Register, offset: 0xE00 */ 95 } S32_NVIC_Type, *S32_NVIC_MemMapPtr; 96 97 /** Number of instances of the S32_NVIC module. */ 98 #define S32_NVIC_INSTANCE_COUNT (1u) 99 100 101 /* S32_NVIC - Peripheral instance base addresses */ 102 /** Peripheral S32_NVIC base address */ 103 #define S32_NVIC_BASE (0xE000E100u) 104 /** Peripheral S32_NVIC base pointer */ 105 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE) 106 /** Array initializer of S32_NVIC peripheral base addresses */ 107 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE } 108 /** Array initializer of S32_NVIC peripheral base pointers */ 109 #define S32_NVIC_BASE_PTRS { S32_NVIC } 110 /** Number of interrupt vector arrays for the S32_NVIC module. */ 111 #define S32_NVIC_IRQS_ARR_COUNT (1u) 112 /** Number of interrupt channels for the S32_NVIC module. */ 113 #define S32_NVIC_IRQS_CH_COUNT (1u) 114 /** Interrupt vectors for the S32_NVIC peripheral type */ 115 #define S32_NVIC_IRQS { SWI_IRQn } 116 117 /* ---------------------------------------------------------------------------- 118 -- S32_NVIC Register Masks 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup S32_NVIC_Register_Masks S32_NVIC Register Masks 123 * @{ 124 */ 125 126 /* ISER Bit Fields */ 127 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu 128 #define S32_NVIC_ISER_SETENA_SHIFT 0u 129 #define S32_NVIC_ISER_SETENA_WIDTH 32u 130 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK) 131 /* ICER Bit Fields */ 132 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu 133 #define S32_NVIC_ICER_CLRENA_SHIFT 0u 134 #define S32_NVIC_ICER_CLRENA_WIDTH 32u 135 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK) 136 /* ISPR Bit Fields */ 137 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu 138 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u 139 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u 140 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK) 141 /* ICPR Bit Fields */ 142 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu 143 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u 144 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u 145 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK) 146 /* IABR Bit Fields */ 147 #define S32_NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu 148 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u 149 #define S32_NVIC_IABR_ACTIVE_WIDTH 32u 150 #define S32_NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IABR_ACTIVE_SHIFT))&S32_NVIC_IABR_ACTIVE_MASK) 151 /* IP Bit Fields */ 152 #define S32_NVIC_IP_PRI0_MASK 0xFFu 153 #define S32_NVIC_IP_PRI0_SHIFT 0u 154 #define S32_NVIC_IP_PRI0_WIDTH 8u 155 #define S32_NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI0_SHIFT))&S32_NVIC_IP_PRI0_MASK) 156 #define S32_NVIC_IP_PRI1_MASK 0xFFu 157 #define S32_NVIC_IP_PRI1_SHIFT 0u 158 #define S32_NVIC_IP_PRI1_WIDTH 8u 159 #define S32_NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI1_SHIFT))&S32_NVIC_IP_PRI1_MASK) 160 #define S32_NVIC_IP_PRI2_MASK 0xFFu 161 #define S32_NVIC_IP_PRI2_SHIFT 0u 162 #define S32_NVIC_IP_PRI2_WIDTH 8u 163 #define S32_NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI2_SHIFT))&S32_NVIC_IP_PRI2_MASK) 164 #define S32_NVIC_IP_PRI3_MASK 0xFFu 165 #define S32_NVIC_IP_PRI3_SHIFT 0u 166 #define S32_NVIC_IP_PRI3_WIDTH 8u 167 #define S32_NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI3_SHIFT))&S32_NVIC_IP_PRI3_MASK) 168 #define S32_NVIC_IP_PRI4_MASK 0xFFu 169 #define S32_NVIC_IP_PRI4_SHIFT 0u 170 #define S32_NVIC_IP_PRI4_WIDTH 8u 171 #define S32_NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI4_SHIFT))&S32_NVIC_IP_PRI4_MASK) 172 #define S32_NVIC_IP_PRI5_MASK 0xFFu 173 #define S32_NVIC_IP_PRI5_SHIFT 0u 174 #define S32_NVIC_IP_PRI5_WIDTH 8u 175 #define S32_NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI5_SHIFT))&S32_NVIC_IP_PRI5_MASK) 176 #define S32_NVIC_IP_PRI6_MASK 0xFFu 177 #define S32_NVIC_IP_PRI6_SHIFT 0u 178 #define S32_NVIC_IP_PRI6_WIDTH 8u 179 #define S32_NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI6_SHIFT))&S32_NVIC_IP_PRI6_MASK) 180 #define S32_NVIC_IP_PRI7_MASK 0xFFu 181 #define S32_NVIC_IP_PRI7_SHIFT 0u 182 #define S32_NVIC_IP_PRI7_WIDTH 8u 183 #define S32_NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI7_SHIFT))&S32_NVIC_IP_PRI7_MASK) 184 #define S32_NVIC_IP_PRI8_MASK 0xFFu 185 #define S32_NVIC_IP_PRI8_SHIFT 0u 186 #define S32_NVIC_IP_PRI8_WIDTH 8u 187 #define S32_NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI8_SHIFT))&S32_NVIC_IP_PRI8_MASK) 188 #define S32_NVIC_IP_PRI9_MASK 0xFFu 189 #define S32_NVIC_IP_PRI9_SHIFT 0u 190 #define S32_NVIC_IP_PRI9_WIDTH 8u 191 #define S32_NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI9_SHIFT))&S32_NVIC_IP_PRI9_MASK) 192 #define S32_NVIC_IP_PRI10_MASK 0xFFu 193 #define S32_NVIC_IP_PRI10_SHIFT 0u 194 #define S32_NVIC_IP_PRI10_WIDTH 8u 195 #define S32_NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI10_SHIFT))&S32_NVIC_IP_PRI10_MASK) 196 #define S32_NVIC_IP_PRI11_MASK 0xFFu 197 #define S32_NVIC_IP_PRI11_SHIFT 0u 198 #define S32_NVIC_IP_PRI11_WIDTH 8u 199 #define S32_NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI11_SHIFT))&S32_NVIC_IP_PRI11_MASK) 200 #define S32_NVIC_IP_PRI12_MASK 0xFFu 201 #define S32_NVIC_IP_PRI12_SHIFT 0u 202 #define S32_NVIC_IP_PRI12_WIDTH 8u 203 #define S32_NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI12_SHIFT))&S32_NVIC_IP_PRI12_MASK) 204 #define S32_NVIC_IP_PRI13_MASK 0xFFu 205 #define S32_NVIC_IP_PRI13_SHIFT 0u 206 #define S32_NVIC_IP_PRI13_WIDTH 8u 207 #define S32_NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI13_SHIFT))&S32_NVIC_IP_PRI13_MASK) 208 #define S32_NVIC_IP_PRI14_MASK 0xFFu 209 #define S32_NVIC_IP_PRI14_SHIFT 0u 210 #define S32_NVIC_IP_PRI14_WIDTH 8u 211 #define S32_NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI14_SHIFT))&S32_NVIC_IP_PRI14_MASK) 212 #define S32_NVIC_IP_PRI15_MASK 0xFFu 213 #define S32_NVIC_IP_PRI15_SHIFT 0u 214 #define S32_NVIC_IP_PRI15_WIDTH 8u 215 #define S32_NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI15_SHIFT))&S32_NVIC_IP_PRI15_MASK) 216 #define S32_NVIC_IP_PRI16_MASK 0xFFu 217 #define S32_NVIC_IP_PRI16_SHIFT 0u 218 #define S32_NVIC_IP_PRI16_WIDTH 8u 219 #define S32_NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI16_SHIFT))&S32_NVIC_IP_PRI16_MASK) 220 #define S32_NVIC_IP_PRI17_MASK 0xFFu 221 #define S32_NVIC_IP_PRI17_SHIFT 0u 222 #define S32_NVIC_IP_PRI17_WIDTH 8u 223 #define S32_NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI17_SHIFT))&S32_NVIC_IP_PRI17_MASK) 224 #define S32_NVIC_IP_PRI18_MASK 0xFFu 225 #define S32_NVIC_IP_PRI18_SHIFT 0u 226 #define S32_NVIC_IP_PRI18_WIDTH 8u 227 #define S32_NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI18_SHIFT))&S32_NVIC_IP_PRI18_MASK) 228 #define S32_NVIC_IP_PRI19_MASK 0xFFu 229 #define S32_NVIC_IP_PRI19_SHIFT 0u 230 #define S32_NVIC_IP_PRI19_WIDTH 8u 231 #define S32_NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI19_SHIFT))&S32_NVIC_IP_PRI19_MASK) 232 #define S32_NVIC_IP_PRI20_MASK 0xFFu 233 #define S32_NVIC_IP_PRI20_SHIFT 0u 234 #define S32_NVIC_IP_PRI20_WIDTH 8u 235 #define S32_NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI20_SHIFT))&S32_NVIC_IP_PRI20_MASK) 236 #define S32_NVIC_IP_PRI21_MASK 0xFFu 237 #define S32_NVIC_IP_PRI21_SHIFT 0u 238 #define S32_NVIC_IP_PRI21_WIDTH 8u 239 #define S32_NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI21_SHIFT))&S32_NVIC_IP_PRI21_MASK) 240 #define S32_NVIC_IP_PRI22_MASK 0xFFu 241 #define S32_NVIC_IP_PRI22_SHIFT 0u 242 #define S32_NVIC_IP_PRI22_WIDTH 8u 243 #define S32_NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI22_SHIFT))&S32_NVIC_IP_PRI22_MASK) 244 #define S32_NVIC_IP_PRI23_MASK 0xFFu 245 #define S32_NVIC_IP_PRI23_SHIFT 0u 246 #define S32_NVIC_IP_PRI23_WIDTH 8u 247 #define S32_NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI23_SHIFT))&S32_NVIC_IP_PRI23_MASK) 248 #define S32_NVIC_IP_PRI24_MASK 0xFFu 249 #define S32_NVIC_IP_PRI24_SHIFT 0u 250 #define S32_NVIC_IP_PRI24_WIDTH 8u 251 #define S32_NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI24_SHIFT))&S32_NVIC_IP_PRI24_MASK) 252 #define S32_NVIC_IP_PRI25_MASK 0xFFu 253 #define S32_NVIC_IP_PRI25_SHIFT 0u 254 #define S32_NVIC_IP_PRI25_WIDTH 8u 255 #define S32_NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI25_SHIFT))&S32_NVIC_IP_PRI25_MASK) 256 #define S32_NVIC_IP_PRI26_MASK 0xFFu 257 #define S32_NVIC_IP_PRI26_SHIFT 0u 258 #define S32_NVIC_IP_PRI26_WIDTH 8u 259 #define S32_NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI26_SHIFT))&S32_NVIC_IP_PRI26_MASK) 260 #define S32_NVIC_IP_PRI27_MASK 0xFFu 261 #define S32_NVIC_IP_PRI27_SHIFT 0u 262 #define S32_NVIC_IP_PRI27_WIDTH 8u 263 #define S32_NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI27_SHIFT))&S32_NVIC_IP_PRI27_MASK) 264 #define S32_NVIC_IP_PRI28_MASK 0xFFu 265 #define S32_NVIC_IP_PRI28_SHIFT 0u 266 #define S32_NVIC_IP_PRI28_WIDTH 8u 267 #define S32_NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI28_SHIFT))&S32_NVIC_IP_PRI28_MASK) 268 #define S32_NVIC_IP_PRI29_MASK 0xFFu 269 #define S32_NVIC_IP_PRI29_SHIFT 0u 270 #define S32_NVIC_IP_PRI29_WIDTH 8u 271 #define S32_NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI29_SHIFT))&S32_NVIC_IP_PRI29_MASK) 272 #define S32_NVIC_IP_PRI30_MASK 0xFFu 273 #define S32_NVIC_IP_PRI30_SHIFT 0u 274 #define S32_NVIC_IP_PRI30_WIDTH 8u 275 #define S32_NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI30_SHIFT))&S32_NVIC_IP_PRI30_MASK) 276 #define S32_NVIC_IP_PRI31_MASK 0xFFu 277 #define S32_NVIC_IP_PRI31_SHIFT 0u 278 #define S32_NVIC_IP_PRI31_WIDTH 8u 279 #define S32_NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI31_SHIFT))&S32_NVIC_IP_PRI31_MASK) 280 #define S32_NVIC_IP_PRI32_MASK 0xFFu 281 #define S32_NVIC_IP_PRI32_SHIFT 0u 282 #define S32_NVIC_IP_PRI32_WIDTH 8u 283 #define S32_NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI32_SHIFT))&S32_NVIC_IP_PRI32_MASK) 284 #define S32_NVIC_IP_PRI33_MASK 0xFFu 285 #define S32_NVIC_IP_PRI33_SHIFT 0u 286 #define S32_NVIC_IP_PRI33_WIDTH 8u 287 #define S32_NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI33_SHIFT))&S32_NVIC_IP_PRI33_MASK) 288 #define S32_NVIC_IP_PRI34_MASK 0xFFu 289 #define S32_NVIC_IP_PRI34_SHIFT 0u 290 #define S32_NVIC_IP_PRI34_WIDTH 8u 291 #define S32_NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI34_SHIFT))&S32_NVIC_IP_PRI34_MASK) 292 #define S32_NVIC_IP_PRI35_MASK 0xFFu 293 #define S32_NVIC_IP_PRI35_SHIFT 0u 294 #define S32_NVIC_IP_PRI35_WIDTH 8u 295 #define S32_NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI35_SHIFT))&S32_NVIC_IP_PRI35_MASK) 296 #define S32_NVIC_IP_PRI36_MASK 0xFFu 297 #define S32_NVIC_IP_PRI36_SHIFT 0u 298 #define S32_NVIC_IP_PRI36_WIDTH 8u 299 #define S32_NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI36_SHIFT))&S32_NVIC_IP_PRI36_MASK) 300 #define S32_NVIC_IP_PRI37_MASK 0xFFu 301 #define S32_NVIC_IP_PRI37_SHIFT 0u 302 #define S32_NVIC_IP_PRI37_WIDTH 8u 303 #define S32_NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI37_SHIFT))&S32_NVIC_IP_PRI37_MASK) 304 #define S32_NVIC_IP_PRI38_MASK 0xFFu 305 #define S32_NVIC_IP_PRI38_SHIFT 0u 306 #define S32_NVIC_IP_PRI38_WIDTH 8u 307 #define S32_NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI38_SHIFT))&S32_NVIC_IP_PRI38_MASK) 308 #define S32_NVIC_IP_PRI39_MASK 0xFFu 309 #define S32_NVIC_IP_PRI39_SHIFT 0u 310 #define S32_NVIC_IP_PRI39_WIDTH 8u 311 #define S32_NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI39_SHIFT))&S32_NVIC_IP_PRI39_MASK) 312 #define S32_NVIC_IP_PRI40_MASK 0xFFu 313 #define S32_NVIC_IP_PRI40_SHIFT 0u 314 #define S32_NVIC_IP_PRI40_WIDTH 8u 315 #define S32_NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI40_SHIFT))&S32_NVIC_IP_PRI40_MASK) 316 #define S32_NVIC_IP_PRI41_MASK 0xFFu 317 #define S32_NVIC_IP_PRI41_SHIFT 0u 318 #define S32_NVIC_IP_PRI41_WIDTH 8u 319 #define S32_NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI41_SHIFT))&S32_NVIC_IP_PRI41_MASK) 320 #define S32_NVIC_IP_PRI42_MASK 0xFFu 321 #define S32_NVIC_IP_PRI42_SHIFT 0u 322 #define S32_NVIC_IP_PRI42_WIDTH 8u 323 #define S32_NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI42_SHIFT))&S32_NVIC_IP_PRI42_MASK) 324 #define S32_NVIC_IP_PRI43_MASK 0xFFu 325 #define S32_NVIC_IP_PRI43_SHIFT 0u 326 #define S32_NVIC_IP_PRI43_WIDTH 8u 327 #define S32_NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI43_SHIFT))&S32_NVIC_IP_PRI43_MASK) 328 #define S32_NVIC_IP_PRI44_MASK 0xFFu 329 #define S32_NVIC_IP_PRI44_SHIFT 0u 330 #define S32_NVIC_IP_PRI44_WIDTH 8u 331 #define S32_NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI44_SHIFT))&S32_NVIC_IP_PRI44_MASK) 332 #define S32_NVIC_IP_PRI45_MASK 0xFFu 333 #define S32_NVIC_IP_PRI45_SHIFT 0u 334 #define S32_NVIC_IP_PRI45_WIDTH 8u 335 #define S32_NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI45_SHIFT))&S32_NVIC_IP_PRI45_MASK) 336 #define S32_NVIC_IP_PRI46_MASK 0xFFu 337 #define S32_NVIC_IP_PRI46_SHIFT 0u 338 #define S32_NVIC_IP_PRI46_WIDTH 8u 339 #define S32_NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI46_SHIFT))&S32_NVIC_IP_PRI46_MASK) 340 #define S32_NVIC_IP_PRI47_MASK 0xFFu 341 #define S32_NVIC_IP_PRI47_SHIFT 0u 342 #define S32_NVIC_IP_PRI47_WIDTH 8u 343 #define S32_NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI47_SHIFT))&S32_NVIC_IP_PRI47_MASK) 344 #define S32_NVIC_IP_PRI48_MASK 0xFFu 345 #define S32_NVIC_IP_PRI48_SHIFT 0u 346 #define S32_NVIC_IP_PRI48_WIDTH 8u 347 #define S32_NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI48_SHIFT))&S32_NVIC_IP_PRI48_MASK) 348 #define S32_NVIC_IP_PRI49_MASK 0xFFu 349 #define S32_NVIC_IP_PRI49_SHIFT 0u 350 #define S32_NVIC_IP_PRI49_WIDTH 8u 351 #define S32_NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI49_SHIFT))&S32_NVIC_IP_PRI49_MASK) 352 #define S32_NVIC_IP_PRI50_MASK 0xFFu 353 #define S32_NVIC_IP_PRI50_SHIFT 0u 354 #define S32_NVIC_IP_PRI50_WIDTH 8u 355 #define S32_NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI50_SHIFT))&S32_NVIC_IP_PRI50_MASK) 356 #define S32_NVIC_IP_PRI51_MASK 0xFFu 357 #define S32_NVIC_IP_PRI51_SHIFT 0u 358 #define S32_NVIC_IP_PRI51_WIDTH 8u 359 #define S32_NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI51_SHIFT))&S32_NVIC_IP_PRI51_MASK) 360 #define S32_NVIC_IP_PRI52_MASK 0xFFu 361 #define S32_NVIC_IP_PRI52_SHIFT 0u 362 #define S32_NVIC_IP_PRI52_WIDTH 8u 363 #define S32_NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI52_SHIFT))&S32_NVIC_IP_PRI52_MASK) 364 #define S32_NVIC_IP_PRI53_MASK 0xFFu 365 #define S32_NVIC_IP_PRI53_SHIFT 0u 366 #define S32_NVIC_IP_PRI53_WIDTH 8u 367 #define S32_NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI53_SHIFT))&S32_NVIC_IP_PRI53_MASK) 368 #define S32_NVIC_IP_PRI54_MASK 0xFFu 369 #define S32_NVIC_IP_PRI54_SHIFT 0u 370 #define S32_NVIC_IP_PRI54_WIDTH 8u 371 #define S32_NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI54_SHIFT))&S32_NVIC_IP_PRI54_MASK) 372 #define S32_NVIC_IP_PRI55_MASK 0xFFu 373 #define S32_NVIC_IP_PRI55_SHIFT 0u 374 #define S32_NVIC_IP_PRI55_WIDTH 8u 375 #define S32_NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI55_SHIFT))&S32_NVIC_IP_PRI55_MASK) 376 #define S32_NVIC_IP_PRI56_MASK 0xFFu 377 #define S32_NVIC_IP_PRI56_SHIFT 0u 378 #define S32_NVIC_IP_PRI56_WIDTH 8u 379 #define S32_NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI56_SHIFT))&S32_NVIC_IP_PRI56_MASK) 380 #define S32_NVIC_IP_PRI57_MASK 0xFFu 381 #define S32_NVIC_IP_PRI57_SHIFT 0u 382 #define S32_NVIC_IP_PRI57_WIDTH 8u 383 #define S32_NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI57_SHIFT))&S32_NVIC_IP_PRI57_MASK) 384 #define S32_NVIC_IP_PRI58_MASK 0xFFu 385 #define S32_NVIC_IP_PRI58_SHIFT 0u 386 #define S32_NVIC_IP_PRI58_WIDTH 8u 387 #define S32_NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI58_SHIFT))&S32_NVIC_IP_PRI58_MASK) 388 #define S32_NVIC_IP_PRI59_MASK 0xFFu 389 #define S32_NVIC_IP_PRI59_SHIFT 0u 390 #define S32_NVIC_IP_PRI59_WIDTH 8u 391 #define S32_NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI59_SHIFT))&S32_NVIC_IP_PRI59_MASK) 392 #define S32_NVIC_IP_PRI60_MASK 0xFFu 393 #define S32_NVIC_IP_PRI60_SHIFT 0u 394 #define S32_NVIC_IP_PRI60_WIDTH 8u 395 #define S32_NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI60_SHIFT))&S32_NVIC_IP_PRI60_MASK) 396 #define S32_NVIC_IP_PRI61_MASK 0xFFu 397 #define S32_NVIC_IP_PRI61_SHIFT 0u 398 #define S32_NVIC_IP_PRI61_WIDTH 8u 399 #define S32_NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI61_SHIFT))&S32_NVIC_IP_PRI61_MASK) 400 #define S32_NVIC_IP_PRI62_MASK 0xFFu 401 #define S32_NVIC_IP_PRI62_SHIFT 0u 402 #define S32_NVIC_IP_PRI62_WIDTH 8u 403 #define S32_NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI62_SHIFT))&S32_NVIC_IP_PRI62_MASK) 404 #define S32_NVIC_IP_PRI63_MASK 0xFFu 405 #define S32_NVIC_IP_PRI63_SHIFT 0u 406 #define S32_NVIC_IP_PRI63_WIDTH 8u 407 #define S32_NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI63_SHIFT))&S32_NVIC_IP_PRI63_MASK) 408 #define S32_NVIC_IP_PRI64_MASK 0xFFu 409 #define S32_NVIC_IP_PRI64_SHIFT 0u 410 #define S32_NVIC_IP_PRI64_WIDTH 8u 411 #define S32_NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI64_SHIFT))&S32_NVIC_IP_PRI64_MASK) 412 #define S32_NVIC_IP_PRI65_MASK 0xFFu 413 #define S32_NVIC_IP_PRI65_SHIFT 0u 414 #define S32_NVIC_IP_PRI65_WIDTH 8u 415 #define S32_NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI65_SHIFT))&S32_NVIC_IP_PRI65_MASK) 416 #define S32_NVIC_IP_PRI66_MASK 0xFFu 417 #define S32_NVIC_IP_PRI66_SHIFT 0u 418 #define S32_NVIC_IP_PRI66_WIDTH 8u 419 #define S32_NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI66_SHIFT))&S32_NVIC_IP_PRI66_MASK) 420 #define S32_NVIC_IP_PRI67_MASK 0xFFu 421 #define S32_NVIC_IP_PRI67_SHIFT 0u 422 #define S32_NVIC_IP_PRI67_WIDTH 8u 423 #define S32_NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI67_SHIFT))&S32_NVIC_IP_PRI67_MASK) 424 #define S32_NVIC_IP_PRI68_MASK 0xFFu 425 #define S32_NVIC_IP_PRI68_SHIFT 0u 426 #define S32_NVIC_IP_PRI68_WIDTH 8u 427 #define S32_NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI68_SHIFT))&S32_NVIC_IP_PRI68_MASK) 428 #define S32_NVIC_IP_PRI69_MASK 0xFFu 429 #define S32_NVIC_IP_PRI69_SHIFT 0u 430 #define S32_NVIC_IP_PRI69_WIDTH 8u 431 #define S32_NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI69_SHIFT))&S32_NVIC_IP_PRI69_MASK) 432 #define S32_NVIC_IP_PRI70_MASK 0xFFu 433 #define S32_NVIC_IP_PRI70_SHIFT 0u 434 #define S32_NVIC_IP_PRI70_WIDTH 8u 435 #define S32_NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI70_SHIFT))&S32_NVIC_IP_PRI70_MASK) 436 #define S32_NVIC_IP_PRI71_MASK 0xFFu 437 #define S32_NVIC_IP_PRI71_SHIFT 0u 438 #define S32_NVIC_IP_PRI71_WIDTH 8u 439 #define S32_NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI71_SHIFT))&S32_NVIC_IP_PRI71_MASK) 440 #define S32_NVIC_IP_PRI72_MASK 0xFFu 441 #define S32_NVIC_IP_PRI72_SHIFT 0u 442 #define S32_NVIC_IP_PRI72_WIDTH 8u 443 #define S32_NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI72_SHIFT))&S32_NVIC_IP_PRI72_MASK) 444 #define S32_NVIC_IP_PRI73_MASK 0xFFu 445 #define S32_NVIC_IP_PRI73_SHIFT 0u 446 #define S32_NVIC_IP_PRI73_WIDTH 8u 447 #define S32_NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI73_SHIFT))&S32_NVIC_IP_PRI73_MASK) 448 #define S32_NVIC_IP_PRI74_MASK 0xFFu 449 #define S32_NVIC_IP_PRI74_SHIFT 0u 450 #define S32_NVIC_IP_PRI74_WIDTH 8u 451 #define S32_NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI74_SHIFT))&S32_NVIC_IP_PRI74_MASK) 452 #define S32_NVIC_IP_PRI75_MASK 0xFFu 453 #define S32_NVIC_IP_PRI75_SHIFT 0u 454 #define S32_NVIC_IP_PRI75_WIDTH 8u 455 #define S32_NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI75_SHIFT))&S32_NVIC_IP_PRI75_MASK) 456 #define S32_NVIC_IP_PRI76_MASK 0xFFu 457 #define S32_NVIC_IP_PRI76_SHIFT 0u 458 #define S32_NVIC_IP_PRI76_WIDTH 8u 459 #define S32_NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI76_SHIFT))&S32_NVIC_IP_PRI76_MASK) 460 #define S32_NVIC_IP_PRI77_MASK 0xFFu 461 #define S32_NVIC_IP_PRI77_SHIFT 0u 462 #define S32_NVIC_IP_PRI77_WIDTH 8u 463 #define S32_NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI77_SHIFT))&S32_NVIC_IP_PRI77_MASK) 464 #define S32_NVIC_IP_PRI78_MASK 0xFFu 465 #define S32_NVIC_IP_PRI78_SHIFT 0u 466 #define S32_NVIC_IP_PRI78_WIDTH 8u 467 #define S32_NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI78_SHIFT))&S32_NVIC_IP_PRI78_MASK) 468 #define S32_NVIC_IP_PRI79_MASK 0xFFu 469 #define S32_NVIC_IP_PRI79_SHIFT 0u 470 #define S32_NVIC_IP_PRI79_WIDTH 8u 471 #define S32_NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI79_SHIFT))&S32_NVIC_IP_PRI79_MASK) 472 #define S32_NVIC_IP_PRI80_MASK 0xFFu 473 #define S32_NVIC_IP_PRI80_SHIFT 0u 474 #define S32_NVIC_IP_PRI80_WIDTH 8u 475 #define S32_NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI80_SHIFT))&S32_NVIC_IP_PRI80_MASK) 476 #define S32_NVIC_IP_PRI81_MASK 0xFFu 477 #define S32_NVIC_IP_PRI81_SHIFT 0u 478 #define S32_NVIC_IP_PRI81_WIDTH 8u 479 #define S32_NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI81_SHIFT))&S32_NVIC_IP_PRI81_MASK) 480 #define S32_NVIC_IP_PRI82_MASK 0xFFu 481 #define S32_NVIC_IP_PRI82_SHIFT 0u 482 #define S32_NVIC_IP_PRI82_WIDTH 8u 483 #define S32_NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI82_SHIFT))&S32_NVIC_IP_PRI82_MASK) 484 #define S32_NVIC_IP_PRI83_MASK 0xFFu 485 #define S32_NVIC_IP_PRI83_SHIFT 0u 486 #define S32_NVIC_IP_PRI83_WIDTH 8u 487 #define S32_NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI83_SHIFT))&S32_NVIC_IP_PRI83_MASK) 488 #define S32_NVIC_IP_PRI84_MASK 0xFFu 489 #define S32_NVIC_IP_PRI84_SHIFT 0u 490 #define S32_NVIC_IP_PRI84_WIDTH 8u 491 #define S32_NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI84_SHIFT))&S32_NVIC_IP_PRI84_MASK) 492 #define S32_NVIC_IP_PRI85_MASK 0xFFu 493 #define S32_NVIC_IP_PRI85_SHIFT 0u 494 #define S32_NVIC_IP_PRI85_WIDTH 8u 495 #define S32_NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI85_SHIFT))&S32_NVIC_IP_PRI85_MASK) 496 #define S32_NVIC_IP_PRI86_MASK 0xFFu 497 #define S32_NVIC_IP_PRI86_SHIFT 0u 498 #define S32_NVIC_IP_PRI86_WIDTH 8u 499 #define S32_NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI86_SHIFT))&S32_NVIC_IP_PRI86_MASK) 500 #define S32_NVIC_IP_PRI87_MASK 0xFFu 501 #define S32_NVIC_IP_PRI87_SHIFT 0u 502 #define S32_NVIC_IP_PRI87_WIDTH 8u 503 #define S32_NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI87_SHIFT))&S32_NVIC_IP_PRI87_MASK) 504 #define S32_NVIC_IP_PRI88_MASK 0xFFu 505 #define S32_NVIC_IP_PRI88_SHIFT 0u 506 #define S32_NVIC_IP_PRI88_WIDTH 8u 507 #define S32_NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI88_SHIFT))&S32_NVIC_IP_PRI88_MASK) 508 #define S32_NVIC_IP_PRI89_MASK 0xFFu 509 #define S32_NVIC_IP_PRI89_SHIFT 0u 510 #define S32_NVIC_IP_PRI89_WIDTH 8u 511 #define S32_NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI89_SHIFT))&S32_NVIC_IP_PRI89_MASK) 512 #define S32_NVIC_IP_PRI90_MASK 0xFFu 513 #define S32_NVIC_IP_PRI90_SHIFT 0u 514 #define S32_NVIC_IP_PRI90_WIDTH 8u 515 #define S32_NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI90_SHIFT))&S32_NVIC_IP_PRI90_MASK) 516 #define S32_NVIC_IP_PRI91_MASK 0xFFu 517 #define S32_NVIC_IP_PRI91_SHIFT 0u 518 #define S32_NVIC_IP_PRI91_WIDTH 8u 519 #define S32_NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI91_SHIFT))&S32_NVIC_IP_PRI91_MASK) 520 #define S32_NVIC_IP_PRI92_MASK 0xFFu 521 #define S32_NVIC_IP_PRI92_SHIFT 0u 522 #define S32_NVIC_IP_PRI92_WIDTH 8u 523 #define S32_NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI92_SHIFT))&S32_NVIC_IP_PRI92_MASK) 524 #define S32_NVIC_IP_PRI93_MASK 0xFFu 525 #define S32_NVIC_IP_PRI93_SHIFT 0u 526 #define S32_NVIC_IP_PRI93_WIDTH 8u 527 #define S32_NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI93_SHIFT))&S32_NVIC_IP_PRI93_MASK) 528 #define S32_NVIC_IP_PRI94_MASK 0xFFu 529 #define S32_NVIC_IP_PRI94_SHIFT 0u 530 #define S32_NVIC_IP_PRI94_WIDTH 8u 531 #define S32_NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI94_SHIFT))&S32_NVIC_IP_PRI94_MASK) 532 #define S32_NVIC_IP_PRI95_MASK 0xFFu 533 #define S32_NVIC_IP_PRI95_SHIFT 0u 534 #define S32_NVIC_IP_PRI95_WIDTH 8u 535 #define S32_NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI95_SHIFT))&S32_NVIC_IP_PRI95_MASK) 536 #define S32_NVIC_IP_PRI96_MASK 0xFFu 537 #define S32_NVIC_IP_PRI96_SHIFT 0u 538 #define S32_NVIC_IP_PRI96_WIDTH 8u 539 #define S32_NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI96_SHIFT))&S32_NVIC_IP_PRI96_MASK) 540 #define S32_NVIC_IP_PRI97_MASK 0xFFu 541 #define S32_NVIC_IP_PRI97_SHIFT 0u 542 #define S32_NVIC_IP_PRI97_WIDTH 8u 543 #define S32_NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI97_SHIFT))&S32_NVIC_IP_PRI97_MASK) 544 #define S32_NVIC_IP_PRI98_MASK 0xFFu 545 #define S32_NVIC_IP_PRI98_SHIFT 0u 546 #define S32_NVIC_IP_PRI98_WIDTH 8u 547 #define S32_NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI98_SHIFT))&S32_NVIC_IP_PRI98_MASK) 548 #define S32_NVIC_IP_PRI99_MASK 0xFFu 549 #define S32_NVIC_IP_PRI99_SHIFT 0u 550 #define S32_NVIC_IP_PRI99_WIDTH 8u 551 #define S32_NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI99_SHIFT))&S32_NVIC_IP_PRI99_MASK) 552 #define S32_NVIC_IP_PRI100_MASK 0xFFu 553 #define S32_NVIC_IP_PRI100_SHIFT 0u 554 #define S32_NVIC_IP_PRI100_WIDTH 8u 555 #define S32_NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI100_SHIFT))&S32_NVIC_IP_PRI100_MASK) 556 #define S32_NVIC_IP_PRI101_MASK 0xFFu 557 #define S32_NVIC_IP_PRI101_SHIFT 0u 558 #define S32_NVIC_IP_PRI101_WIDTH 8u 559 #define S32_NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI101_SHIFT))&S32_NVIC_IP_PRI101_MASK) 560 #define S32_NVIC_IP_PRI102_MASK 0xFFu 561 #define S32_NVIC_IP_PRI102_SHIFT 0u 562 #define S32_NVIC_IP_PRI102_WIDTH 8u 563 #define S32_NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI102_SHIFT))&S32_NVIC_IP_PRI102_MASK) 564 #define S32_NVIC_IP_PRI103_MASK 0xFFu 565 #define S32_NVIC_IP_PRI103_SHIFT 0u 566 #define S32_NVIC_IP_PRI103_WIDTH 8u 567 #define S32_NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI103_SHIFT))&S32_NVIC_IP_PRI103_MASK) 568 #define S32_NVIC_IP_PRI104_MASK 0xFFu 569 #define S32_NVIC_IP_PRI104_SHIFT 0u 570 #define S32_NVIC_IP_PRI104_WIDTH 8u 571 #define S32_NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI104_SHIFT))&S32_NVIC_IP_PRI104_MASK) 572 #define S32_NVIC_IP_PRI105_MASK 0xFFu 573 #define S32_NVIC_IP_PRI105_SHIFT 0u 574 #define S32_NVIC_IP_PRI105_WIDTH 8u 575 #define S32_NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI105_SHIFT))&S32_NVIC_IP_PRI105_MASK) 576 #define S32_NVIC_IP_PRI106_MASK 0xFFu 577 #define S32_NVIC_IP_PRI106_SHIFT 0u 578 #define S32_NVIC_IP_PRI106_WIDTH 8u 579 #define S32_NVIC_IP_PRI106(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI106_SHIFT))&S32_NVIC_IP_PRI106_MASK) 580 #define S32_NVIC_IP_PRI107_MASK 0xFFu 581 #define S32_NVIC_IP_PRI107_SHIFT 0u 582 #define S32_NVIC_IP_PRI107_WIDTH 8u 583 #define S32_NVIC_IP_PRI107(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI107_SHIFT))&S32_NVIC_IP_PRI107_MASK) 584 #define S32_NVIC_IP_PRI108_MASK 0xFFu 585 #define S32_NVIC_IP_PRI108_SHIFT 0u 586 #define S32_NVIC_IP_PRI108_WIDTH 8u 587 #define S32_NVIC_IP_PRI108(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI108_SHIFT))&S32_NVIC_IP_PRI108_MASK) 588 #define S32_NVIC_IP_PRI109_MASK 0xFFu 589 #define S32_NVIC_IP_PRI109_SHIFT 0u 590 #define S32_NVIC_IP_PRI109_WIDTH 8u 591 #define S32_NVIC_IP_PRI109(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI109_SHIFT))&S32_NVIC_IP_PRI109_MASK) 592 #define S32_NVIC_IP_PRI110_MASK 0xFFu 593 #define S32_NVIC_IP_PRI110_SHIFT 0u 594 #define S32_NVIC_IP_PRI110_WIDTH 8u 595 #define S32_NVIC_IP_PRI110(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI110_SHIFT))&S32_NVIC_IP_PRI110_MASK) 596 #define S32_NVIC_IP_PRI111_MASK 0xFFu 597 #define S32_NVIC_IP_PRI111_SHIFT 0u 598 #define S32_NVIC_IP_PRI111_WIDTH 8u 599 #define S32_NVIC_IP_PRI111(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI111_SHIFT))&S32_NVIC_IP_PRI111_MASK) 600 #define S32_NVIC_IP_PRI112_MASK 0xFFu 601 #define S32_NVIC_IP_PRI112_SHIFT 0u 602 #define S32_NVIC_IP_PRI112_WIDTH 8u 603 #define S32_NVIC_IP_PRI112(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI112_SHIFT))&S32_NVIC_IP_PRI112_MASK) 604 #define S32_NVIC_IP_PRI113_MASK 0xFFu 605 #define S32_NVIC_IP_PRI113_SHIFT 0u 606 #define S32_NVIC_IP_PRI113_WIDTH 8u 607 #define S32_NVIC_IP_PRI113(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI113_SHIFT))&S32_NVIC_IP_PRI113_MASK) 608 #define S32_NVIC_IP_PRI114_MASK 0xFFu 609 #define S32_NVIC_IP_PRI114_SHIFT 0u 610 #define S32_NVIC_IP_PRI114_WIDTH 8u 611 #define S32_NVIC_IP_PRI114(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI114_SHIFT))&S32_NVIC_IP_PRI114_MASK) 612 #define S32_NVIC_IP_PRI115_MASK 0xFFu 613 #define S32_NVIC_IP_PRI115_SHIFT 0u 614 #define S32_NVIC_IP_PRI115_WIDTH 8u 615 #define S32_NVIC_IP_PRI115(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI115_SHIFT))&S32_NVIC_IP_PRI115_MASK) 616 #define S32_NVIC_IP_PRI116_MASK 0xFFu 617 #define S32_NVIC_IP_PRI116_SHIFT 0u 618 #define S32_NVIC_IP_PRI116_WIDTH 8u 619 #define S32_NVIC_IP_PRI116(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI116_SHIFT))&S32_NVIC_IP_PRI116_MASK) 620 #define S32_NVIC_IP_PRI117_MASK 0xFFu 621 #define S32_NVIC_IP_PRI117_SHIFT 0u 622 #define S32_NVIC_IP_PRI117_WIDTH 8u 623 #define S32_NVIC_IP_PRI117(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI117_SHIFT))&S32_NVIC_IP_PRI117_MASK) 624 #define S32_NVIC_IP_PRI118_MASK 0xFFu 625 #define S32_NVIC_IP_PRI118_SHIFT 0u 626 #define S32_NVIC_IP_PRI118_WIDTH 8u 627 #define S32_NVIC_IP_PRI118(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI118_SHIFT))&S32_NVIC_IP_PRI118_MASK) 628 #define S32_NVIC_IP_PRI119_MASK 0xFFu 629 #define S32_NVIC_IP_PRI119_SHIFT 0u 630 #define S32_NVIC_IP_PRI119_WIDTH 8u 631 #define S32_NVIC_IP_PRI119(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI119_SHIFT))&S32_NVIC_IP_PRI119_MASK) 632 #define S32_NVIC_IP_PRI120_MASK 0xFFu 633 #define S32_NVIC_IP_PRI120_SHIFT 0u 634 #define S32_NVIC_IP_PRI120_WIDTH 8u 635 #define S32_NVIC_IP_PRI120(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI120_SHIFT))&S32_NVIC_IP_PRI120_MASK) 636 #define S32_NVIC_IP_PRI121_MASK 0xFFu 637 #define S32_NVIC_IP_PRI121_SHIFT 0u 638 #define S32_NVIC_IP_PRI121_WIDTH 8u 639 #define S32_NVIC_IP_PRI121(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI121_SHIFT))&S32_NVIC_IP_PRI121_MASK) 640 #define S32_NVIC_IP_PRI122_MASK 0xFFu 641 #define S32_NVIC_IP_PRI122_SHIFT 0u 642 #define S32_NVIC_IP_PRI122_WIDTH 8u 643 #define S32_NVIC_IP_PRI122(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI122_SHIFT))&S32_NVIC_IP_PRI122_MASK) 644 #define S32_NVIC_IP_PRI123_MASK 0xFFu 645 #define S32_NVIC_IP_PRI123_SHIFT 0u 646 #define S32_NVIC_IP_PRI123_WIDTH 8u 647 #define S32_NVIC_IP_PRI123(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI123_SHIFT))&S32_NVIC_IP_PRI123_MASK) 648 #define S32_NVIC_IP_PRI124_MASK 0xFFu 649 #define S32_NVIC_IP_PRI124_SHIFT 0u 650 #define S32_NVIC_IP_PRI124_WIDTH 8u 651 #define S32_NVIC_IP_PRI124(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI124_SHIFT))&S32_NVIC_IP_PRI124_MASK) 652 #define S32_NVIC_IP_PRI125_MASK 0xFFu 653 #define S32_NVIC_IP_PRI125_SHIFT 0u 654 #define S32_NVIC_IP_PRI125_WIDTH 8u 655 #define S32_NVIC_IP_PRI125(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI125_SHIFT))&S32_NVIC_IP_PRI125_MASK) 656 #define S32_NVIC_IP_PRI126_MASK 0xFFu 657 #define S32_NVIC_IP_PRI126_SHIFT 0u 658 #define S32_NVIC_IP_PRI126_WIDTH 8u 659 #define S32_NVIC_IP_PRI126(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI126_SHIFT))&S32_NVIC_IP_PRI126_MASK) 660 #define S32_NVIC_IP_PRI127_MASK 0xFFu 661 #define S32_NVIC_IP_PRI127_SHIFT 0u 662 #define S32_NVIC_IP_PRI127_WIDTH 8u 663 #define S32_NVIC_IP_PRI127(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI127_SHIFT))&S32_NVIC_IP_PRI127_MASK) 664 #define S32_NVIC_IP_PRI128_MASK 0xFFu 665 #define S32_NVIC_IP_PRI128_SHIFT 0u 666 #define S32_NVIC_IP_PRI128_WIDTH 8u 667 #define S32_NVIC_IP_PRI128(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI128_SHIFT))&S32_NVIC_IP_PRI128_MASK) 668 #define S32_NVIC_IP_PRI129_MASK 0xFFu 669 #define S32_NVIC_IP_PRI129_SHIFT 0u 670 #define S32_NVIC_IP_PRI129_WIDTH 8u 671 #define S32_NVIC_IP_PRI129(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI129_SHIFT))&S32_NVIC_IP_PRI129_MASK) 672 #define S32_NVIC_IP_PRI130_MASK 0xFFu 673 #define S32_NVIC_IP_PRI130_SHIFT 0u 674 #define S32_NVIC_IP_PRI130_WIDTH 8u 675 #define S32_NVIC_IP_PRI130(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI130_SHIFT))&S32_NVIC_IP_PRI130_MASK) 676 #define S32_NVIC_IP_PRI131_MASK 0xFFu 677 #define S32_NVIC_IP_PRI131_SHIFT 0u 678 #define S32_NVIC_IP_PRI131_WIDTH 8u 679 #define S32_NVIC_IP_PRI131(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI131_SHIFT))&S32_NVIC_IP_PRI131_MASK) 680 #define S32_NVIC_IP_PRI132_MASK 0xFFu 681 #define S32_NVIC_IP_PRI132_SHIFT 0u 682 #define S32_NVIC_IP_PRI132_WIDTH 8u 683 #define S32_NVIC_IP_PRI132(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI132_SHIFT))&S32_NVIC_IP_PRI132_MASK) 684 #define S32_NVIC_IP_PRI133_MASK 0xFFu 685 #define S32_NVIC_IP_PRI133_SHIFT 0u 686 #define S32_NVIC_IP_PRI133_WIDTH 8u 687 #define S32_NVIC_IP_PRI133(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI133_SHIFT))&S32_NVIC_IP_PRI133_MASK) 688 #define S32_NVIC_IP_PRI134_MASK 0xFFu 689 #define S32_NVIC_IP_PRI134_SHIFT 0u 690 #define S32_NVIC_IP_PRI134_WIDTH 8u 691 #define S32_NVIC_IP_PRI134(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI134_SHIFT))&S32_NVIC_IP_PRI134_MASK) 692 #define S32_NVIC_IP_PRI135_MASK 0xFFu 693 #define S32_NVIC_IP_PRI135_SHIFT 0u 694 #define S32_NVIC_IP_PRI135_WIDTH 8u 695 #define S32_NVIC_IP_PRI135(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI135_SHIFT))&S32_NVIC_IP_PRI135_MASK) 696 #define S32_NVIC_IP_PRI136_MASK 0xFFu 697 #define S32_NVIC_IP_PRI136_SHIFT 0u 698 #define S32_NVIC_IP_PRI136_WIDTH 8u 699 #define S32_NVIC_IP_PRI136(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI136_SHIFT))&S32_NVIC_IP_PRI136_MASK) 700 #define S32_NVIC_IP_PRI137_MASK 0xFFu 701 #define S32_NVIC_IP_PRI137_SHIFT 0u 702 #define S32_NVIC_IP_PRI137_WIDTH 8u 703 #define S32_NVIC_IP_PRI137(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI137_SHIFT))&S32_NVIC_IP_PRI137_MASK) 704 #define S32_NVIC_IP_PRI138_MASK 0xFFu 705 #define S32_NVIC_IP_PRI138_SHIFT 0u 706 #define S32_NVIC_IP_PRI138_WIDTH 8u 707 #define S32_NVIC_IP_PRI138(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI138_SHIFT))&S32_NVIC_IP_PRI138_MASK) 708 #define S32_NVIC_IP_PRI139_MASK 0xFFu 709 #define S32_NVIC_IP_PRI139_SHIFT 0u 710 #define S32_NVIC_IP_PRI139_WIDTH 8u 711 #define S32_NVIC_IP_PRI139(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI139_SHIFT))&S32_NVIC_IP_PRI139_MASK) 712 #define S32_NVIC_IP_PRI140_MASK 0xFFu 713 #define S32_NVIC_IP_PRI140_SHIFT 0u 714 #define S32_NVIC_IP_PRI140_WIDTH 8u 715 #define S32_NVIC_IP_PRI140(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI140_SHIFT))&S32_NVIC_IP_PRI140_MASK) 716 #define S32_NVIC_IP_PRI141_MASK 0xFFu 717 #define S32_NVIC_IP_PRI141_SHIFT 0u 718 #define S32_NVIC_IP_PRI141_WIDTH 8u 719 #define S32_NVIC_IP_PRI141(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI141_SHIFT))&S32_NVIC_IP_PRI141_MASK) 720 #define S32_NVIC_IP_PRI142_MASK 0xFFu 721 #define S32_NVIC_IP_PRI142_SHIFT 0u 722 #define S32_NVIC_IP_PRI142_WIDTH 8u 723 #define S32_NVIC_IP_PRI142(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI142_SHIFT))&S32_NVIC_IP_PRI142_MASK) 724 #define S32_NVIC_IP_PRI143_MASK 0xFFu 725 #define S32_NVIC_IP_PRI143_SHIFT 0u 726 #define S32_NVIC_IP_PRI143_WIDTH 8u 727 #define S32_NVIC_IP_PRI143(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI143_SHIFT))&S32_NVIC_IP_PRI143_MASK) 728 #define S32_NVIC_IP_PRI144_MASK 0xFFu 729 #define S32_NVIC_IP_PRI144_SHIFT 0u 730 #define S32_NVIC_IP_PRI144_WIDTH 8u 731 #define S32_NVIC_IP_PRI144(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI144_SHIFT))&S32_NVIC_IP_PRI144_MASK) 732 #define S32_NVIC_IP_PRI145_MASK 0xFFu 733 #define S32_NVIC_IP_PRI145_SHIFT 0u 734 #define S32_NVIC_IP_PRI145_WIDTH 8u 735 #define S32_NVIC_IP_PRI145(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI145_SHIFT))&S32_NVIC_IP_PRI145_MASK) 736 #define S32_NVIC_IP_PRI146_MASK 0xFFu 737 #define S32_NVIC_IP_PRI146_SHIFT 0u 738 #define S32_NVIC_IP_PRI146_WIDTH 8u 739 #define S32_NVIC_IP_PRI146(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI146_SHIFT))&S32_NVIC_IP_PRI146_MASK) 740 #define S32_NVIC_IP_PRI147_MASK 0xFFu 741 #define S32_NVIC_IP_PRI147_SHIFT 0u 742 #define S32_NVIC_IP_PRI147_WIDTH 8u 743 #define S32_NVIC_IP_PRI147(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI147_SHIFT))&S32_NVIC_IP_PRI147_MASK) 744 #define S32_NVIC_IP_PRI148_MASK 0xFFu 745 #define S32_NVIC_IP_PRI148_SHIFT 0u 746 #define S32_NVIC_IP_PRI148_WIDTH 8u 747 #define S32_NVIC_IP_PRI148(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI148_SHIFT))&S32_NVIC_IP_PRI148_MASK) 748 #define S32_NVIC_IP_PRI149_MASK 0xFFu 749 #define S32_NVIC_IP_PRI149_SHIFT 0u 750 #define S32_NVIC_IP_PRI149_WIDTH 8u 751 #define S32_NVIC_IP_PRI149(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI149_SHIFT))&S32_NVIC_IP_PRI149_MASK) 752 #define S32_NVIC_IP_PRI150_MASK 0xFFu 753 #define S32_NVIC_IP_PRI150_SHIFT 0u 754 #define S32_NVIC_IP_PRI150_WIDTH 8u 755 #define S32_NVIC_IP_PRI150(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI150_SHIFT))&S32_NVIC_IP_PRI150_MASK) 756 #define S32_NVIC_IP_PRI151_MASK 0xFFu 757 #define S32_NVIC_IP_PRI151_SHIFT 0u 758 #define S32_NVIC_IP_PRI151_WIDTH 8u 759 #define S32_NVIC_IP_PRI151(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI151_SHIFT))&S32_NVIC_IP_PRI151_MASK) 760 #define S32_NVIC_IP_PRI152_MASK 0xFFu 761 #define S32_NVIC_IP_PRI152_SHIFT 0u 762 #define S32_NVIC_IP_PRI152_WIDTH 8u 763 #define S32_NVIC_IP_PRI152(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI152_SHIFT))&S32_NVIC_IP_PRI152_MASK) 764 #define S32_NVIC_IP_PRI153_MASK 0xFFu 765 #define S32_NVIC_IP_PRI153_SHIFT 0u 766 #define S32_NVIC_IP_PRI153_WIDTH 8u 767 #define S32_NVIC_IP_PRI153(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI153_SHIFT))&S32_NVIC_IP_PRI153_MASK) 768 #define S32_NVIC_IP_PRI154_MASK 0xFFu 769 #define S32_NVIC_IP_PRI154_SHIFT 0u 770 #define S32_NVIC_IP_PRI154_WIDTH 8u 771 #define S32_NVIC_IP_PRI154(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI154_SHIFT))&S32_NVIC_IP_PRI154_MASK) 772 #define S32_NVIC_IP_PRI155_MASK 0xFFu 773 #define S32_NVIC_IP_PRI155_SHIFT 0u 774 #define S32_NVIC_IP_PRI155_WIDTH 8u 775 #define S32_NVIC_IP_PRI155(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI155_SHIFT))&S32_NVIC_IP_PRI155_MASK) 776 #define S32_NVIC_IP_PRI156_MASK 0xFFu 777 #define S32_NVIC_IP_PRI156_SHIFT 0u 778 #define S32_NVIC_IP_PRI156_WIDTH 8u 779 #define S32_NVIC_IP_PRI156(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI156_SHIFT))&S32_NVIC_IP_PRI156_MASK) 780 #define S32_NVIC_IP_PRI157_MASK 0xFFu 781 #define S32_NVIC_IP_PRI157_SHIFT 0u 782 #define S32_NVIC_IP_PRI157_WIDTH 8u 783 #define S32_NVIC_IP_PRI157(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI157_SHIFT))&S32_NVIC_IP_PRI157_MASK) 784 #define S32_NVIC_IP_PRI158_MASK 0xFFu 785 #define S32_NVIC_IP_PRI158_SHIFT 0u 786 #define S32_NVIC_IP_PRI158_WIDTH 8u 787 #define S32_NVIC_IP_PRI158(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI158_SHIFT))&S32_NVIC_IP_PRI158_MASK) 788 #define S32_NVIC_IP_PRI159_MASK 0xFFu 789 #define S32_NVIC_IP_PRI159_SHIFT 0u 790 #define S32_NVIC_IP_PRI159_WIDTH 8u 791 #define S32_NVIC_IP_PRI159(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI159_SHIFT))&S32_NVIC_IP_PRI159_MASK) 792 #define S32_NVIC_IP_PRI160_MASK 0xFFu 793 #define S32_NVIC_IP_PRI160_SHIFT 0u 794 #define S32_NVIC_IP_PRI160_WIDTH 8u 795 #define S32_NVIC_IP_PRI160(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI160_SHIFT))&S32_NVIC_IP_PRI160_MASK) 796 #define S32_NVIC_IP_PRI161_MASK 0xFFu 797 #define S32_NVIC_IP_PRI161_SHIFT 0u 798 #define S32_NVIC_IP_PRI161_WIDTH 8u 799 #define S32_NVIC_IP_PRI161(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI161_SHIFT))&S32_NVIC_IP_PRI161_MASK) 800 #define S32_NVIC_IP_PRI162_MASK 0xFFu 801 #define S32_NVIC_IP_PRI162_SHIFT 0u 802 #define S32_NVIC_IP_PRI162_WIDTH 8u 803 #define S32_NVIC_IP_PRI162(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI162_SHIFT))&S32_NVIC_IP_PRI162_MASK) 804 #define S32_NVIC_IP_PRI163_MASK 0xFFu 805 #define S32_NVIC_IP_PRI163_SHIFT 0u 806 #define S32_NVIC_IP_PRI163_WIDTH 8u 807 #define S32_NVIC_IP_PRI163(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI163_SHIFT))&S32_NVIC_IP_PRI163_MASK) 808 #define S32_NVIC_IP_PRI164_MASK 0xFFu 809 #define S32_NVIC_IP_PRI164_SHIFT 0u 810 #define S32_NVIC_IP_PRI164_WIDTH 8u 811 #define S32_NVIC_IP_PRI164(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI164_SHIFT))&S32_NVIC_IP_PRI164_MASK) 812 #define S32_NVIC_IP_PRI165_MASK 0xFFu 813 #define S32_NVIC_IP_PRI165_SHIFT 0u 814 #define S32_NVIC_IP_PRI165_WIDTH 8u 815 #define S32_NVIC_IP_PRI165(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI165_SHIFT))&S32_NVIC_IP_PRI165_MASK) 816 #define S32_NVIC_IP_PRI166_MASK 0xFFu 817 #define S32_NVIC_IP_PRI166_SHIFT 0u 818 #define S32_NVIC_IP_PRI166_WIDTH 8u 819 #define S32_NVIC_IP_PRI166(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI166_SHIFT))&S32_NVIC_IP_PRI166_MASK) 820 #define S32_NVIC_IP_PRI167_MASK 0xFFu 821 #define S32_NVIC_IP_PRI167_SHIFT 0u 822 #define S32_NVIC_IP_PRI167_WIDTH 8u 823 #define S32_NVIC_IP_PRI167(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI167_SHIFT))&S32_NVIC_IP_PRI167_MASK) 824 #define S32_NVIC_IP_PRI168_MASK 0xFFu 825 #define S32_NVIC_IP_PRI168_SHIFT 0u 826 #define S32_NVIC_IP_PRI168_WIDTH 8u 827 #define S32_NVIC_IP_PRI168(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI168_SHIFT))&S32_NVIC_IP_PRI168_MASK) 828 #define S32_NVIC_IP_PRI169_MASK 0xFFu 829 #define S32_NVIC_IP_PRI169_SHIFT 0u 830 #define S32_NVIC_IP_PRI169_WIDTH 8u 831 #define S32_NVIC_IP_PRI169(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI169_SHIFT))&S32_NVIC_IP_PRI169_MASK) 832 #define S32_NVIC_IP_PRI170_MASK 0xFFu 833 #define S32_NVIC_IP_PRI170_SHIFT 0u 834 #define S32_NVIC_IP_PRI170_WIDTH 8u 835 #define S32_NVIC_IP_PRI170(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI170_SHIFT))&S32_NVIC_IP_PRI170_MASK) 836 #define S32_NVIC_IP_PRI171_MASK 0xFFu 837 #define S32_NVIC_IP_PRI171_SHIFT 0u 838 #define S32_NVIC_IP_PRI171_WIDTH 8u 839 #define S32_NVIC_IP_PRI171(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI171_SHIFT))&S32_NVIC_IP_PRI171_MASK) 840 #define S32_NVIC_IP_PRI172_MASK 0xFFu 841 #define S32_NVIC_IP_PRI172_SHIFT 0u 842 #define S32_NVIC_IP_PRI172_WIDTH 8u 843 #define S32_NVIC_IP_PRI172(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI172_SHIFT))&S32_NVIC_IP_PRI172_MASK) 844 #define S32_NVIC_IP_PRI173_MASK 0xFFu 845 #define S32_NVIC_IP_PRI173_SHIFT 0u 846 #define S32_NVIC_IP_PRI173_WIDTH 8u 847 #define S32_NVIC_IP_PRI173(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI173_SHIFT))&S32_NVIC_IP_PRI173_MASK) 848 #define S32_NVIC_IP_PRI174_MASK 0xFFu 849 #define S32_NVIC_IP_PRI174_SHIFT 0u 850 #define S32_NVIC_IP_PRI174_WIDTH 8u 851 #define S32_NVIC_IP_PRI174(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI174_SHIFT))&S32_NVIC_IP_PRI174_MASK) 852 #define S32_NVIC_IP_PRI175_MASK 0xFFu 853 #define S32_NVIC_IP_PRI175_SHIFT 0u 854 #define S32_NVIC_IP_PRI175_WIDTH 8u 855 #define S32_NVIC_IP_PRI175(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI175_SHIFT))&S32_NVIC_IP_PRI175_MASK) 856 #define S32_NVIC_IP_PRI176_MASK 0xFFu 857 #define S32_NVIC_IP_PRI176_SHIFT 0u 858 #define S32_NVIC_IP_PRI176_WIDTH 8u 859 #define S32_NVIC_IP_PRI176(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI176_SHIFT))&S32_NVIC_IP_PRI176_MASK) 860 #define S32_NVIC_IP_PRI177_MASK 0xFFu 861 #define S32_NVIC_IP_PRI177_SHIFT 0u 862 #define S32_NVIC_IP_PRI177_WIDTH 8u 863 #define S32_NVIC_IP_PRI177(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI177_SHIFT))&S32_NVIC_IP_PRI177_MASK) 864 #define S32_NVIC_IP_PRI178_MASK 0xFFu 865 #define S32_NVIC_IP_PRI178_SHIFT 0u 866 #define S32_NVIC_IP_PRI178_WIDTH 8u 867 #define S32_NVIC_IP_PRI178(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI178_SHIFT))&S32_NVIC_IP_PRI178_MASK) 868 #define S32_NVIC_IP_PRI179_MASK 0xFFu 869 #define S32_NVIC_IP_PRI179_SHIFT 0u 870 #define S32_NVIC_IP_PRI179_WIDTH 8u 871 #define S32_NVIC_IP_PRI179(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI179_SHIFT))&S32_NVIC_IP_PRI179_MASK) 872 #define S32_NVIC_IP_PRI180_MASK 0xFFu 873 #define S32_NVIC_IP_PRI180_SHIFT 0u 874 #define S32_NVIC_IP_PRI180_WIDTH 8u 875 #define S32_NVIC_IP_PRI180(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI180_SHIFT))&S32_NVIC_IP_PRI180_MASK) 876 #define S32_NVIC_IP_PRI181_MASK 0xFFu 877 #define S32_NVIC_IP_PRI181_SHIFT 0u 878 #define S32_NVIC_IP_PRI181_WIDTH 8u 879 #define S32_NVIC_IP_PRI181(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI181_SHIFT))&S32_NVIC_IP_PRI181_MASK) 880 #define S32_NVIC_IP_PRI182_MASK 0xFFu 881 #define S32_NVIC_IP_PRI182_SHIFT 0u 882 #define S32_NVIC_IP_PRI182_WIDTH 8u 883 #define S32_NVIC_IP_PRI182(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI182_SHIFT))&S32_NVIC_IP_PRI182_MASK) 884 #define S32_NVIC_IP_PRI183_MASK 0xFFu 885 #define S32_NVIC_IP_PRI183_SHIFT 0u 886 #define S32_NVIC_IP_PRI183_WIDTH 8u 887 #define S32_NVIC_IP_PRI183(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI183_SHIFT))&S32_NVIC_IP_PRI183_MASK) 888 #define S32_NVIC_IP_PRI184_MASK 0xFFu 889 #define S32_NVIC_IP_PRI184_SHIFT 0u 890 #define S32_NVIC_IP_PRI184_WIDTH 8u 891 #define S32_NVIC_IP_PRI184(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI184_SHIFT))&S32_NVIC_IP_PRI184_MASK) 892 #define S32_NVIC_IP_PRI185_MASK 0xFFu 893 #define S32_NVIC_IP_PRI185_SHIFT 0u 894 #define S32_NVIC_IP_PRI185_WIDTH 8u 895 #define S32_NVIC_IP_PRI185(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI185_SHIFT))&S32_NVIC_IP_PRI185_MASK) 896 #define S32_NVIC_IP_PRI186_MASK 0xFFu 897 #define S32_NVIC_IP_PRI186_SHIFT 0u 898 #define S32_NVIC_IP_PRI186_WIDTH 8u 899 #define S32_NVIC_IP_PRI186(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI186_SHIFT))&S32_NVIC_IP_PRI186_MASK) 900 #define S32_NVIC_IP_PRI187_MASK 0xFFu 901 #define S32_NVIC_IP_PRI187_SHIFT 0u 902 #define S32_NVIC_IP_PRI187_WIDTH 8u 903 #define S32_NVIC_IP_PRI187(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI187_SHIFT))&S32_NVIC_IP_PRI187_MASK) 904 #define S32_NVIC_IP_PRI188_MASK 0xFFu 905 #define S32_NVIC_IP_PRI188_SHIFT 0u 906 #define S32_NVIC_IP_PRI188_WIDTH 8u 907 #define S32_NVIC_IP_PRI188(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI188_SHIFT))&S32_NVIC_IP_PRI188_MASK) 908 #define S32_NVIC_IP_PRI189_MASK 0xFFu 909 #define S32_NVIC_IP_PRI189_SHIFT 0u 910 #define S32_NVIC_IP_PRI189_WIDTH 8u 911 #define S32_NVIC_IP_PRI189(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI189_SHIFT))&S32_NVIC_IP_PRI189_MASK) 912 #define S32_NVIC_IP_PRI190_MASK 0xFFu 913 #define S32_NVIC_IP_PRI190_SHIFT 0u 914 #define S32_NVIC_IP_PRI190_WIDTH 8u 915 #define S32_NVIC_IP_PRI190(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI190_SHIFT))&S32_NVIC_IP_PRI190_MASK) 916 #define S32_NVIC_IP_PRI191_MASK 0xFFu 917 #define S32_NVIC_IP_PRI191_SHIFT 0u 918 #define S32_NVIC_IP_PRI191_WIDTH 8u 919 #define S32_NVIC_IP_PRI191(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI191_SHIFT))&S32_NVIC_IP_PRI191_MASK) 920 #define S32_NVIC_IP_PRI192_MASK 0xFFu 921 #define S32_NVIC_IP_PRI192_SHIFT 0u 922 #define S32_NVIC_IP_PRI192_WIDTH 8u 923 #define S32_NVIC_IP_PRI192(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI192_SHIFT))&S32_NVIC_IP_PRI192_MASK) 924 #define S32_NVIC_IP_PRI193_MASK 0xFFu 925 #define S32_NVIC_IP_PRI193_SHIFT 0u 926 #define S32_NVIC_IP_PRI193_WIDTH 8u 927 #define S32_NVIC_IP_PRI193(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI193_SHIFT))&S32_NVIC_IP_PRI193_MASK) 928 #define S32_NVIC_IP_PRI194_MASK 0xFFu 929 #define S32_NVIC_IP_PRI194_SHIFT 0u 930 #define S32_NVIC_IP_PRI194_WIDTH 8u 931 #define S32_NVIC_IP_PRI194(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI194_SHIFT))&S32_NVIC_IP_PRI194_MASK) 932 #define S32_NVIC_IP_PRI195_MASK 0xFFu 933 #define S32_NVIC_IP_PRI195_SHIFT 0u 934 #define S32_NVIC_IP_PRI195_WIDTH 8u 935 #define S32_NVIC_IP_PRI195(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI195_SHIFT))&S32_NVIC_IP_PRI195_MASK) 936 #define S32_NVIC_IP_PRI196_MASK 0xFFu 937 #define S32_NVIC_IP_PRI196_SHIFT 0u 938 #define S32_NVIC_IP_PRI196_WIDTH 8u 939 #define S32_NVIC_IP_PRI196(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI196_SHIFT))&S32_NVIC_IP_PRI196_MASK) 940 #define S32_NVIC_IP_PRI197_MASK 0xFFu 941 #define S32_NVIC_IP_PRI197_SHIFT 0u 942 #define S32_NVIC_IP_PRI197_WIDTH 8u 943 #define S32_NVIC_IP_PRI197(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI197_SHIFT))&S32_NVIC_IP_PRI197_MASK) 944 #define S32_NVIC_IP_PRI198_MASK 0xFFu 945 #define S32_NVIC_IP_PRI198_SHIFT 0u 946 #define S32_NVIC_IP_PRI198_WIDTH 8u 947 #define S32_NVIC_IP_PRI198(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI198_SHIFT))&S32_NVIC_IP_PRI198_MASK) 948 #define S32_NVIC_IP_PRI199_MASK 0xFFu 949 #define S32_NVIC_IP_PRI199_SHIFT 0u 950 #define S32_NVIC_IP_PRI199_WIDTH 8u 951 #define S32_NVIC_IP_PRI199(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI199_SHIFT))&S32_NVIC_IP_PRI199_MASK) 952 #define S32_NVIC_IP_PRI200_MASK 0xFFu 953 #define S32_NVIC_IP_PRI200_SHIFT 0u 954 #define S32_NVIC_IP_PRI200_WIDTH 8u 955 #define S32_NVIC_IP_PRI200(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI200_SHIFT))&S32_NVIC_IP_PRI200_MASK) 956 #define S32_NVIC_IP_PRI201_MASK 0xFFu 957 #define S32_NVIC_IP_PRI201_SHIFT 0u 958 #define S32_NVIC_IP_PRI201_WIDTH 8u 959 #define S32_NVIC_IP_PRI201(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI201_SHIFT))&S32_NVIC_IP_PRI201_MASK) 960 #define S32_NVIC_IP_PRI202_MASK 0xFFu 961 #define S32_NVIC_IP_PRI202_SHIFT 0u 962 #define S32_NVIC_IP_PRI202_WIDTH 8u 963 #define S32_NVIC_IP_PRI202(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI202_SHIFT))&S32_NVIC_IP_PRI202_MASK) 964 #define S32_NVIC_IP_PRI203_MASK 0xFFu 965 #define S32_NVIC_IP_PRI203_SHIFT 0u 966 #define S32_NVIC_IP_PRI203_WIDTH 8u 967 #define S32_NVIC_IP_PRI203(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI203_SHIFT))&S32_NVIC_IP_PRI203_MASK) 968 #define S32_NVIC_IP_PRI204_MASK 0xFFu 969 #define S32_NVIC_IP_PRI204_SHIFT 0u 970 #define S32_NVIC_IP_PRI204_WIDTH 8u 971 #define S32_NVIC_IP_PRI204(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI204_SHIFT))&S32_NVIC_IP_PRI204_MASK) 972 #define S32_NVIC_IP_PRI205_MASK 0xFFu 973 #define S32_NVIC_IP_PRI205_SHIFT 0u 974 #define S32_NVIC_IP_PRI205_WIDTH 8u 975 #define S32_NVIC_IP_PRI205(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI205_SHIFT))&S32_NVIC_IP_PRI205_MASK) 976 #define S32_NVIC_IP_PRI206_MASK 0xFFu 977 #define S32_NVIC_IP_PRI206_SHIFT 0u 978 #define S32_NVIC_IP_PRI206_WIDTH 8u 979 #define S32_NVIC_IP_PRI206(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI206_SHIFT))&S32_NVIC_IP_PRI206_MASK) 980 #define S32_NVIC_IP_PRI207_MASK 0xFFu 981 #define S32_NVIC_IP_PRI207_SHIFT 0u 982 #define S32_NVIC_IP_PRI207_WIDTH 8u 983 #define S32_NVIC_IP_PRI207(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI207_SHIFT))&S32_NVIC_IP_PRI207_MASK) 984 #define S32_NVIC_IP_PRI208_MASK 0xFFu 985 #define S32_NVIC_IP_PRI208_SHIFT 0u 986 #define S32_NVIC_IP_PRI208_WIDTH 8u 987 #define S32_NVIC_IP_PRI208(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI208_SHIFT))&S32_NVIC_IP_PRI208_MASK) 988 #define S32_NVIC_IP_PRI209_MASK 0xFFu 989 #define S32_NVIC_IP_PRI209_SHIFT 0u 990 #define S32_NVIC_IP_PRI209_WIDTH 8u 991 #define S32_NVIC_IP_PRI209(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI209_SHIFT))&S32_NVIC_IP_PRI209_MASK) 992 #define S32_NVIC_IP_PRI210_MASK 0xFFu 993 #define S32_NVIC_IP_PRI210_SHIFT 0u 994 #define S32_NVIC_IP_PRI210_WIDTH 8u 995 #define S32_NVIC_IP_PRI210(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI210_SHIFT))&S32_NVIC_IP_PRI210_MASK) 996 #define S32_NVIC_IP_PRI211_MASK 0xFFu 997 #define S32_NVIC_IP_PRI211_SHIFT 0u 998 #define S32_NVIC_IP_PRI211_WIDTH 8u 999 #define S32_NVIC_IP_PRI211(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI211_SHIFT))&S32_NVIC_IP_PRI211_MASK) 1000 #define S32_NVIC_IP_PRI212_MASK 0xFFu 1001 #define S32_NVIC_IP_PRI212_SHIFT 0u 1002 #define S32_NVIC_IP_PRI212_WIDTH 8u 1003 #define S32_NVIC_IP_PRI212(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI212_SHIFT))&S32_NVIC_IP_PRI212_MASK) 1004 #define S32_NVIC_IP_PRI213_MASK 0xFFu 1005 #define S32_NVIC_IP_PRI213_SHIFT 0u 1006 #define S32_NVIC_IP_PRI213_WIDTH 8u 1007 #define S32_NVIC_IP_PRI213(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI213_SHIFT))&S32_NVIC_IP_PRI213_MASK) 1008 #define S32_NVIC_IP_PRI214_MASK 0xFFu 1009 #define S32_NVIC_IP_PRI214_SHIFT 0u 1010 #define S32_NVIC_IP_PRI214_WIDTH 8u 1011 #define S32_NVIC_IP_PRI214(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI214_SHIFT))&S32_NVIC_IP_PRI214_MASK) 1012 #define S32_NVIC_IP_PRI215_MASK 0xFFu 1013 #define S32_NVIC_IP_PRI215_SHIFT 0u 1014 #define S32_NVIC_IP_PRI215_WIDTH 8u 1015 #define S32_NVIC_IP_PRI215(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI215_SHIFT))&S32_NVIC_IP_PRI215_MASK) 1016 #define S32_NVIC_IP_PRI216_MASK 0xFFu 1017 #define S32_NVIC_IP_PRI216_SHIFT 0u 1018 #define S32_NVIC_IP_PRI216_WIDTH 8u 1019 #define S32_NVIC_IP_PRI216(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI216_SHIFT))&S32_NVIC_IP_PRI216_MASK) 1020 #define S32_NVIC_IP_PRI217_MASK 0xFFu 1021 #define S32_NVIC_IP_PRI217_SHIFT 0u 1022 #define S32_NVIC_IP_PRI217_WIDTH 8u 1023 #define S32_NVIC_IP_PRI217(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI217_SHIFT))&S32_NVIC_IP_PRI217_MASK) 1024 #define S32_NVIC_IP_PRI218_MASK 0xFFu 1025 #define S32_NVIC_IP_PRI218_SHIFT 0u 1026 #define S32_NVIC_IP_PRI218_WIDTH 8u 1027 #define S32_NVIC_IP_PRI218(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI218_SHIFT))&S32_NVIC_IP_PRI218_MASK) 1028 #define S32_NVIC_IP_PRI219_MASK 0xFFu 1029 #define S32_NVIC_IP_PRI219_SHIFT 0u 1030 #define S32_NVIC_IP_PRI219_WIDTH 8u 1031 #define S32_NVIC_IP_PRI219(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI219_SHIFT))&S32_NVIC_IP_PRI219_MASK) 1032 #define S32_NVIC_IP_PRI220_MASK 0xFFu 1033 #define S32_NVIC_IP_PRI220_SHIFT 0u 1034 #define S32_NVIC_IP_PRI220_WIDTH 8u 1035 #define S32_NVIC_IP_PRI220(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI220_SHIFT))&S32_NVIC_IP_PRI220_MASK) 1036 #define S32_NVIC_IP_PRI221_MASK 0xFFu 1037 #define S32_NVIC_IP_PRI221_SHIFT 0u 1038 #define S32_NVIC_IP_PRI221_WIDTH 8u 1039 #define S32_NVIC_IP_PRI221(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI221_SHIFT))&S32_NVIC_IP_PRI221_MASK) 1040 #define S32_NVIC_IP_PRI222_MASK 0xFFu 1041 #define S32_NVIC_IP_PRI222_SHIFT 0u 1042 #define S32_NVIC_IP_PRI222_WIDTH 8u 1043 #define S32_NVIC_IP_PRI222(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI222_SHIFT))&S32_NVIC_IP_PRI222_MASK) 1044 #define S32_NVIC_IP_PRI223_MASK 0xFFu 1045 #define S32_NVIC_IP_PRI223_SHIFT 0u 1046 #define S32_NVIC_IP_PRI223_WIDTH 8u 1047 #define S32_NVIC_IP_PRI223(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI223_SHIFT))&S32_NVIC_IP_PRI223_MASK) 1048 #define S32_NVIC_IP_PRI224_MASK 0xFFu 1049 #define S32_NVIC_IP_PRI224_SHIFT 0u 1050 #define S32_NVIC_IP_PRI224_WIDTH 8u 1051 #define S32_NVIC_IP_PRI224(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI224_SHIFT))&S32_NVIC_IP_PRI224_MASK) 1052 #define S32_NVIC_IP_PRI225_MASK 0xFFu 1053 #define S32_NVIC_IP_PRI225_SHIFT 0u 1054 #define S32_NVIC_IP_PRI225_WIDTH 8u 1055 #define S32_NVIC_IP_PRI225(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI225_SHIFT))&S32_NVIC_IP_PRI225_MASK) 1056 #define S32_NVIC_IP_PRI226_MASK 0xFFu 1057 #define S32_NVIC_IP_PRI226_SHIFT 0u 1058 #define S32_NVIC_IP_PRI226_WIDTH 8u 1059 #define S32_NVIC_IP_PRI226(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI226_SHIFT))&S32_NVIC_IP_PRI226_MASK) 1060 #define S32_NVIC_IP_PRI227_MASK 0xFFu 1061 #define S32_NVIC_IP_PRI227_SHIFT 0u 1062 #define S32_NVIC_IP_PRI227_WIDTH 8u 1063 #define S32_NVIC_IP_PRI227(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI227_SHIFT))&S32_NVIC_IP_PRI227_MASK) 1064 #define S32_NVIC_IP_PRI228_MASK 0xFFu 1065 #define S32_NVIC_IP_PRI228_SHIFT 0u 1066 #define S32_NVIC_IP_PRI228_WIDTH 8u 1067 #define S32_NVIC_IP_PRI228(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI228_SHIFT))&S32_NVIC_IP_PRI228_MASK) 1068 #define S32_NVIC_IP_PRI229_MASK 0xFFu 1069 #define S32_NVIC_IP_PRI229_SHIFT 0u 1070 #define S32_NVIC_IP_PRI229_WIDTH 8u 1071 #define S32_NVIC_IP_PRI229(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI229_SHIFT))&S32_NVIC_IP_PRI229_MASK) 1072 #define S32_NVIC_IP_PRI230_MASK 0xFFu 1073 #define S32_NVIC_IP_PRI230_SHIFT 0u 1074 #define S32_NVIC_IP_PRI230_WIDTH 8u 1075 #define S32_NVIC_IP_PRI230(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI230_SHIFT))&S32_NVIC_IP_PRI230_MASK) 1076 #define S32_NVIC_IP_PRI231_MASK 0xFFu 1077 #define S32_NVIC_IP_PRI231_SHIFT 0u 1078 #define S32_NVIC_IP_PRI231_WIDTH 8u 1079 #define S32_NVIC_IP_PRI231(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI231_SHIFT))&S32_NVIC_IP_PRI231_MASK) 1080 #define S32_NVIC_IP_PRI232_MASK 0xFFu 1081 #define S32_NVIC_IP_PRI232_SHIFT 0u 1082 #define S32_NVIC_IP_PRI232_WIDTH 8u 1083 #define S32_NVIC_IP_PRI232(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI232_SHIFT))&S32_NVIC_IP_PRI232_MASK) 1084 #define S32_NVIC_IP_PRI233_MASK 0xFFu 1085 #define S32_NVIC_IP_PRI233_SHIFT 0u 1086 #define S32_NVIC_IP_PRI233_WIDTH 8u 1087 #define S32_NVIC_IP_PRI233(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI233_SHIFT))&S32_NVIC_IP_PRI233_MASK) 1088 #define S32_NVIC_IP_PRI234_MASK 0xFFu 1089 #define S32_NVIC_IP_PRI234_SHIFT 0u 1090 #define S32_NVIC_IP_PRI234_WIDTH 8u 1091 #define S32_NVIC_IP_PRI234(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI234_SHIFT))&S32_NVIC_IP_PRI234_MASK) 1092 #define S32_NVIC_IP_PRI235_MASK 0xFFu 1093 #define S32_NVIC_IP_PRI235_SHIFT 0u 1094 #define S32_NVIC_IP_PRI235_WIDTH 8u 1095 #define S32_NVIC_IP_PRI235(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI235_SHIFT))&S32_NVIC_IP_PRI235_MASK) 1096 #define S32_NVIC_IP_PRI236_MASK 0xFFu 1097 #define S32_NVIC_IP_PRI236_SHIFT 0u 1098 #define S32_NVIC_IP_PRI236_WIDTH 8u 1099 #define S32_NVIC_IP_PRI236(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI236_SHIFT))&S32_NVIC_IP_PRI236_MASK) 1100 #define S32_NVIC_IP_PRI237_MASK 0xFFu 1101 #define S32_NVIC_IP_PRI237_SHIFT 0u 1102 #define S32_NVIC_IP_PRI237_WIDTH 8u 1103 #define S32_NVIC_IP_PRI237(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI237_SHIFT))&S32_NVIC_IP_PRI237_MASK) 1104 #define S32_NVIC_IP_PRI238_MASK 0xFFu 1105 #define S32_NVIC_IP_PRI238_SHIFT 0u 1106 #define S32_NVIC_IP_PRI238_WIDTH 8u 1107 #define S32_NVIC_IP_PRI238(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI238_SHIFT))&S32_NVIC_IP_PRI238_MASK) 1108 #define S32_NVIC_IP_PRI239_MASK 0xFFu 1109 #define S32_NVIC_IP_PRI239_SHIFT 0u 1110 #define S32_NVIC_IP_PRI239_WIDTH 8u 1111 #define S32_NVIC_IP_PRI239(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI239_SHIFT))&S32_NVIC_IP_PRI239_MASK) 1112 /* STIR Bit Fields */ 1113 #define S32_NVIC_STIR_INTID_MASK 0x1FFu 1114 #define S32_NVIC_STIR_INTID_SHIFT 0u 1115 #define S32_NVIC_STIR_INTID_WIDTH 9u 1116 #define S32_NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_STIR_INTID_SHIFT))&S32_NVIC_STIR_INTID_MASK) 1117 1118 /*! 1119 * @} 1120 */ /* end of group S32_NVIC_Register_Masks */ 1121 1122 1123 /*! 1124 * @} 1125 */ /* end of group S32_NVIC_Peripheral_Access_Layer */ 1126 1127 #endif /* #if !defined(S32K142_NVIC_H_) */ 1128
