Lines Matching refs:u
172 #define S32_SCB_ACTLR_ACTLR_SHIFT 0u
177 #define S32_SCB_CPUID_REVISION_SHIFT 0u
194 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
240 #define S32_SCB_AIRCR_AIRCR_SHIFT 0u
258 #define S32_SCB_CCR_CCR_SHIFT 0u
263 #define S32_SCB_SHPR1_SHPR1_SHIFT 0u
268 #define S32_SCB_SHPR2_SHPR2_SHIFT 0u
273 #define S32_SCB_SHPR3_SHPR3_SHIFT 0u
278 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
335 #define S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT 0u
412 #define S32_SCB_HFSR_HFSR_SHIFT 0u
417 #define S32_SCB_DFSR_DFSR_SHIFT 0u
422 #define S32_SCB_MMFAR_MMFAR_SHIFT 0u
427 #define S32_SCB_BFAR_BFAR_SHIFT 0u
432 #define S32_SCB_AFSR_AFSR_SHIFT 0u
437 #define S32_SCB_ID_PFR0_ID_PFR0_SHIFT 0u
442 #define S32_SCB_ID_PFR1_ID_PFR1_SHIFT 0u
447 #define S32_SCB_ID_DFR0_ID_DFR0_SHIFT 0u
452 #define S32_SCB_ID_AFR0_ID_AFR0_SHIFT 0u
457 #define S32_SCB_ID_MMFR_ID_MMFR0_SHIFT 0u
461 #define S32_SCB_ID_MMFR_ID_MMFR1_SHIFT 0u
465 #define S32_SCB_ID_MMFR_ID_MMFR2_SHIFT 0u
469 #define S32_SCB_ID_MMFR_ID_MMFR3_SHIFT 0u
474 #define S32_SCB_ID_ISAR_ID_ISAR0_SHIFT 0u
478 #define S32_SCB_ID_ISAR_ID_ISAR1_SHIFT 0u
482 #define S32_SCB_ID_ISAR_ID_ISAR2_SHIFT 0u
486 #define S32_SCB_ID_ISAR_ID_ISAR3_SHIFT 0u
490 #define S32_SCB_ID_ISAR_ID_ISAR4_SHIFT 0u
495 #define S32_SCB_CLIDR_CLIDR_SHIFT 0u
500 #define S32_SCB_CTR_CTR_SHIFT 0u
505 #define S32_SCB_CCSIDR_CCSIDR_SHIFT 0u
510 #define S32_SCB_CSSELR_CSSELR_SHIFT 0u
515 #define S32_SCB_STIR_STIR_SHIFT 0u
520 #define S32_SCB_FPCCR_FPCCR_SHIFT 0u
525 #define S32_SCB_FPCAR_FPCAR_SHIFT 0u
530 #define S32_SCB_FPDSCR_FPDSCR_SHIFT 0u
535 #define S32_SCB_ICIALLU_ICIALLU_SHIFT 0u
540 #define S32_SCB_ICIMVAU_ICIMVAU_SHIFT 0u
545 #define S32_SCB_DCIMVAC_DCIMVAC_SHIFT 0u
550 #define S32_SCB_DCISW_DCISW_SHIFT 0u
555 #define S32_SCB_DCCMVAU_DCCMVAU_SHIFT 0u
560 #define S32_SCB_DCCMVAC_DCCMVAC_SHIFT 0u
565 #define S32_SCB_DCCSW_DCCSW_SHIFT 0u
570 #define S32_SCB_DCCIMVAC_DCCIMVAC_SHIFT 0u
575 #define S32_SCB_DCCISW_DCCISW_SHIFT 0u
580 #define S32_SCB_BPIALL_BPIALL_SHIFT 0u
585 #define S32_SCB_ITCMCR_ITCMCR_SHIFT 0u
590 #define S32_SCB_DTCMCR_DTCMCR_SHIFT 0u
595 #define S32_SCB_AHBPCR_AHBPCR_SHIFT 0u
600 #define S32_SCB_CACR_CACR_SHIFT 0u
605 #define S32_SCB_AHBSCR_AHBSCR_SHIFT 0u
610 #define S32_SCB_ABFSR_ABFSR_SHIFT 0u
615 #define S32_SCB_IEBR0_IEBR0_SHIFT 0u
620 #define S32_SCB_IEBR1h_IEBR1h_SHIFT 0u
625 #define S32_SCB_DEBR0h_DEBR0h_SHIFT 0u
630 #define S32_SCB_DEBR1h_DEBR1h_SHIFT 0u
635 #define S32_SCB_PID_PID0_SHIFT 0u
639 #define S32_SCB_PID_PID1_SHIFT 0u
643 #define S32_SCB_PID_PID2_SHIFT 0u
647 #define S32_SCB_PID_PID3_SHIFT 0u
651 #define S32_SCB_PID_PID4_SHIFT 0u
655 #define S32_SCB_PID_PID5_SHIFT 0u
659 #define S32_SCB_PID_PID6_SHIFT 0u
663 #define S32_SCB_PID_PID7_SHIFT 0u
668 #define S32_SCB_CID_CID0_SHIFT 0u
672 #define S32_SCB_CID_CID1_SHIFT 0u
676 #define S32_SCB_CID_CID2_SHIFT 0u
680 #define S32_SCB_CID_CID3_SHIFT 0u