| /hal_nxp-latest/mcux/mcux-sdk/drivers/lptmr/ |
| D | fsl_lptmr.h | 195 uint32_t reg = base->CSR; in LPTMR_EnableInterrupts()
200 base->CSR = reg; in LPTMR_EnableInterrupts()
212 uint32_t reg = base->CSR; in LPTMR_DisableInterrupts()
217 base->CSR = reg; in LPTMR_DisableInterrupts()
230 return (base->CSR & LPTMR_CSR_TIE_MASK); in LPTMR_GetEnabledInterrupts()
246 base->CSR |= LPTMR_CSR_TDRE_MASK; in LPTMR_EnableTimerDMA()
250 base->CSR &= ~(LPTMR_CSR_TDRE_MASK); in LPTMR_EnableTimerDMA()
270 return (base->CSR & LPTMR_CSR_TCF_MASK); in LPTMR_GetStatusFlags()
282 base->CSR |= mask; in LPTMR_ClearStatusFlags()
351 uint32_t reg = base->CSR; in LPTMR_StartTimer()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma/ |
| D | fsl_edma.c | 105 base->TCD[channel].CSR = 0; in EDMA_InstallTCD()
106 base->TCD[channel].CSR = tcd->CSR; in EDMA_InstallTCD()
350 …base->TCD[channel].CSR = (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(b… in EDMA_SetBandWidth()
396 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; in EDMA_EnableChannelInterrupts()
402 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; in EDMA_EnableChannelInterrupts()
427 base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; in EDMA_DisableChannelInterrupts()
433 base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_DisableChannelInterrupts()
461 tcd->CSR = DMA_CSR_DREQ(1U); in EDMA_TcdReset()
540 tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
627 tcd->CSR |= DMA_CSR_MAJORELINK_MASK; in EDMA_TcdSetChannelLink()
[all …]
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| D | fsl_edma.h | 215 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
510 base->TCD[channel].CSR = in EDMA_EnableAutoStopRequest()
511 …(uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0… in EDMA_EnableAutoStopRequest()
636 tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); in EDMA_TcdSetBandWidth()
665 …tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))… in EDMA_TcdEnableAutoStopRequest()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/vref_1/ |
| D | fsl_vref.c | 99 base->CSR |= VREF_CSR_LPBGEN_MASK; in VREF_Init()
106 base->CSR |= VREF_CSR_LPBG_BUF_EN_MASK; in VREF_Init()
140 base->CSR |= tmp32; in VREF_Init()
217 if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) in VREF_SetVrefTrimVal()
230 while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) in VREF_SetVrefTrimVal()
257 if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) in VREF_SetTrim21Val()
270 while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) in VREF_SetTrim21Val()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mmdvsq/ |
| D | fsl_mmdvsq.c | 35 temp = base->CSR; in MMDVSQ_GetDivideRemainder()
40 base->CSR = temp; in MMDVSQ_GetDivideRemainder()
46 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideRemainder()
67 temp = base->CSR; in MMDVSQ_GetDivideQuotient()
72 base->CSR = temp; in MMDVSQ_GetDivideQuotient()
78 base->CSR |= MMDVSQ_CSR_SRT_MASK; in MMDVSQ_GetDivideQuotient()
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| D | fsl_mmdvsq.h | 115 uint32_t tmp = base->CSR >> MMDVSQ_CSR_SQRT_SHIFT; in MMDVSQ_GetExecutionStatus()
138 base->CSR |= MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
142 base->CSR &= ~MMDVSQ_CSR_DFS_MASK; in MMDVSQ_SetFastStartConfig()
163 base->CSR |= MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
167 base->CSR &= ~MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/ |
| D | fsl_ad_edma.c | 109 base->CH[channel].TCD_CSR = tcd->CSR; in EDMA_AD_InstallTCD()
460 tcd->CSR = DMA_TCD_CSR_DREQ(1U); in EDMA_AD_TcdReset()
542 tcd->CSR = (tcd->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_AD_TcdSetTransferConfig()
616 tcd->CSR |= DMA_TCD_CSR_MAJORELINK_MASK; in EDMA_AD_TcdSetChannelLink()
618 tmpreg = tcd->CSR & (~(uint16_t)DMA_TCD_CSR_MAJORLINKCH_MASK); in EDMA_AD_TcdSetChannelLink()
619 tcd->CSR = tmpreg | DMA_TCD_CSR_MAJORLINKCH(linkedChannel); in EDMA_AD_TcdSetChannelLink()
625 tcd->CSR &= ~(uint16_t)DMA_TCD_CSR_MAJORELINK_MASK; in EDMA_AD_TcdSetChannelLink()
667 tcd->CSR |= DMA_TCD_CSR_INTMAJOR_MASK; in EDMA_AD_TcdEnableInterrupts()
673 tcd->CSR |= DMA_TCD_CSR_INTHALF_MASK; in EDMA_AD_TcdEnableInterrupts()
691 tcd->CSR &= ~(uint16_t)DMA_TCD_CSR_INTMAJOR_MASK; in EDMA_AD_TcdDisableInterrupts()
[all …]
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| D | fsl_edma.c | 140 base->CH[channel].TCD_CSR = tcd->CSR; in EDMA_InstallTCD()
488 tcd->CSR = DMA_TCD_CSR_DREQ(1U); in EDMA_TcdReset()
570 tcd->CSR = (tcd->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
644 tcd->CSR |= DMA_TCD_CSR_MAJORELINK_MASK; in EDMA_TcdSetChannelLink()
646 tmpreg = tcd->CSR & (~(uint16_t)DMA_TCD_CSR_MAJORLINKCH_MASK); in EDMA_TcdSetChannelLink()
647 tcd->CSR = tmpreg | DMA_TCD_CSR_MAJORLINKCH(linkedChannel); in EDMA_TcdSetChannelLink()
653 tcd->CSR &= ~(uint16_t)DMA_TCD_CSR_MAJORELINK_MASK; in EDMA_TcdSetChannelLink()
695 tcd->CSR |= DMA_TCD_CSR_INTMAJOR_MASK; in EDMA_TcdEnableInterrupts()
701 tcd->CSR |= DMA_TCD_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
719 tcd->CSR &= ~(uint16_t)DMA_TCD_CSR_INTMAJOR_MASK; in EDMA_TcdDisableInterrupts()
[all …]
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| D | fsl_ad_edma.h | 228 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
669 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_BWC_MASK)) | DMA_TCD_CSR_BWC(bandWidth); in EDMA_AD_TcdSetBandWidth()
698 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_AD_TcdEnableAutoStopRequest()
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| D | fsl_edma.h | 229 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
670 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_BWC_MASK)) | DMA_TCD_CSR_BWC(bandWidth); in EDMA_TcdSetBandWidth()
699 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | system_K32L3A60_cm0plus.c | 83 if (LPTMR0->CSR != 0U) in SystemInit()
85 LPTMR0->CSR = 0; in SystemInit()
104 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
106 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| D | system_K32L3A60_cm4.c | 86 if (LPTMR0->CSR != 0U) in SystemInit()
88 LPTMR0->CSR = 0; in SystemInit()
111 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
113 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mmau/ |
| D | fsl_mmau.h | 178 base->CSR |= MMAU_CSR_DRE_MASK; in MMAU_EnableDMA()
182 base->CSR &= ~(MMAU_CSR_DRE_MASK); in MMAU_EnableDMA()
197 base->CSR |= MMAU_CSR_SO_MASK; in MMAU_EnableSupervisorOnly()
201 base->CSR &= ~(MMAU_CSR_SO_MASK); in MMAU_EnableSupervisorOnly()
237 …base->CSR |= (mask & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInter… in MMAU_EnableInterrupts()
256 …base->CSR &= ~(mask & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInte… in MMAU_DisableInterrupts()
281 …return base->CSR & ((uint32_t)kMMAU_AccumOverflowInterruptEnable | (uint32_t)kMMAU_OverflowInterru… in MMAU_GetEnabledInterrupts()
296 …return base->CSR & ((uint32_t)kMMAU_AccumOverflowInterruptFlag | (uint32_t)kMMAU_OverflowInterrupt… in MMAU_GetInterruptFlags()
344 …return base->CSR & ((uint32_t)kMMAU_AccumOverflowInstructionFlag | (uint32_t)kMMAU_OverflowInstruc… in MMAU_GetInstructionFlags()
394 return ((base->CSR & MMAU_CSR_HDR_MASK) >> MMAU_CSR_HDR_SHIFT); in MMAU_GetHwRevCmd()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/ |
| D | fsl_edma_core.h | 89 ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
233 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
311 …ype_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \
312 … (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR))))
337 #define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/ |
| D | fsl_edma_core.h | 89 ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
233 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
311 …ype_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \
312 … (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR))))
337 #define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/spdif/ |
| D | fsl_spdif_edma.c | 260 handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; in SPDIF_SubmitTransfer()
272 …csr = (handle->tcdPool[previousTcd].CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MA… in SPDIF_SubmitTransfer()
273 handle->tcdPool[previousTcd].CSR = csr; in SPDIF_SubmitTransfer()
288 csr = (tcdRegs->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; in SPDIF_SubmitTransfer()
290 tcdRegs->CSR = csr; in SPDIF_SubmitTransfer()
301 if ((tcdRegs->CSR & DMA_CSR_ESG_MASK) != 0x00U) in SPDIF_SubmitTransfer()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sinc/ |
| D | fsl_sinc.h | 1229 return (uint8_t)(base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_FIFOAVIL_MASK); in SINC_GetChannelFifoCount()
1243 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_RDRS_MASK) != SINC_CSR_RDRS_MASK); in SINC_CheckChannelResultDataReady()
1446 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PSRDY_MASK) == SINC_CSR_PSRDY_MASK); in SINC_CheckChannelParallelSerialDataReady()
1460 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PFSAT_MASK) == SINC_CSR_PFSAT_MASK); in SINC_CheckChannelPrimaryCICSaturation()
1474 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_HPFSAT_MASK) == SINC_CSR_HPFSAT_MASK); in SINC_CheckChannelHPFSaturation()
1488 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_SFTSAT_MASK) == SINC_CSR_SFTSAT_MASK); in SINC_CheckChannelShiftSaturation()
1502 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_BIASSAT_MASK) == SINC_CSR_BIASSAT_MASK); in SINC_CheckChannelBiasSaturation()
1868 base->CHANNEL[(uint8_t)chId].CSR |= SINC_CSR_SRDS_MASK; in SINC_LatchChannelDebugProceduce()
1882 return ((base->CHANNEL[(uint8_t)chId].CSR & (SINC_CSR_SRDS_MASK | SINC_CSR_DBGRS_MASK)) == 0UL); in SINC_CheckChannelDebugDataValid()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/ |
| D | system_MKE13Z7.c | 98 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
100 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/ |
| D | system_MKE15Z7.c | 105 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
107 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/ |
| D | system_MKE17Z9.c | 90 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
92 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/ |
| D | system_MKE17Z7.c | 98 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
100 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/ |
| D | system_MKE12Z9.c | 90 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
92 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/ |
| D | system_MKE15Z4.c | 98 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
100 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/ |
| D | system_MKE12Z7.c | 98 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
100 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/ |
| D | system_MKE16Z4.c | 96 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); in SystemCoreClockUpdate()
98 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { in SystemCoreClockUpdate()
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