1 /*
2 ** ###################################################################
3 **     Processor:           K32L3A60VPJ1A_cm4
4 **     Compilers:           GNU C Compiler
5 **                          IAR ANSI C/C++ Compiler for ARM
6 **                          Keil ARM C/C++ Compiler
7 **                          MCUXpresso Compiler
8 **
9 **     Reference manual:    K32L3ARM, Rev. 0 , 05/2019
10 **     Version:             rev. 1.0, 2019-04-22
11 **     Build:               b201013
12 **
13 **     Abstract:
14 **         Provides a system configuration function and a global variable that
15 **         contains the system frequency. It configures the device and initializes
16 **         the oscillator (PLL) that is part of the microcontroller device.
17 **
18 **     Copyright 2016 Freescale Semiconductor, Inc.
19 **     Copyright 2016-2020 NXP
20 **     All rights reserved.
21 **
22 **     SPDX-License-Identifier: BSD-3-Clause
23 **
24 **     http:                 www.nxp.com
25 **     mail:                 support@nxp.com
26 **
27 **     Revisions:
28 **     - rev. 1.0 (2019-04-22)
29 **         Initial version.
30 **
31 ** ###################################################################
32 */
33 
34 /*!
35  * @file K32L3A60_cm4
36  * @version 1.0
37  * @date 2019-04-22
38  * @brief Device specific configuration file for K32L3A60_cm4 (implementation
39  *        file)
40  *
41  * Provides a system configuration function and a global variable that contains
42  * the system frequency. It configures the device and initializes the oscillator
43  * (PLL) that is part of the microcontroller device.
44  */
45 
46 #include <stdint.h>
47 #include "fsl_device_registers.h"
48 
49 
50 
51 /* ----------------------------------------------------------------------------
52    -- Core clock
53    ---------------------------------------------------------------------------- */
54 
55 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
56 
57 /* ----------------------------------------------------------------------------
58    -- SystemInit()
59    ---------------------------------------------------------------------------- */
60 
SystemInit(void)61 void SystemInit (void) {
62 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
63   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
64 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
65 
66 #if (DISABLE_WDOG)
67   if ((WDOG0->CS & WDOG_CS_CMD32EN_MASK) != 0U)
68   {
69       WDOG0->CNT = 0xD928C520U;
70   }
71   else
72   {
73       WDOG0->CNT = 0xC520U;
74       WDOG0->CNT = 0xD928U;
75   }
76   WDOG0->TOVAL = 0xFFFFU;
77   WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
78 #endif /* (DISABLE_WDOG) */
79 
80 /* Boot ROM on K32_L3 does not properly restore the registers (LPTMR0->CSR, LPTMR0->PSR, SCB->AIRCR) upon exiting. This can cause
81  * an unrecoverable hard fault when SVC calls are executed. SVC calls are needed by operating systems when starting tasks.
82  * Add following codes to the end of the SystemInit function which is called before any application is started. This operation
83  * will be done only when current core is boot core. */
84   if (((FTFE->FOPT3 & 0x40U) >> 6U) != 0U)
85   {
86     if (LPTMR0->CSR != 0U)
87     {
88         LPTMR0->CSR = 0;
89     }
90     if (LPTMR0->PSR != 0U)
91     {
92         LPTMR0->PSR = 0;
93     }
94     if ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) != 0x0U)
95     {
96         SCB->AIRCR = 0x05FA0000;
97     }
98   }
99 
100   SystemInitHook();
101 }
102 
103 /* ----------------------------------------------------------------------------
104    -- SystemCoreClockUpdate()
105    ---------------------------------------------------------------------------- */
106 
SystemCoreClockUpdate(void)107 void SystemCoreClockUpdate (void) {
108 
109   uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
110   uint16_t Divider;
111   Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
112 
113   switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
114     case 0x1:
115       /* System OSC */
116       SCGOUTClock = CPU_XTAL_CLK_HZ;
117       break;
118     case 0x2:
119       /* Slow IRC */
120       SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
121       break;
122     case 0x3:
123       /* Fast IRC */
124       SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
125       break;
126     case 0x5:
127       /* Low Power FLL */
128       SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U;
129       break;
130     default:
131       SCGOUTClock = 0U;
132       break;
133   }
134   SystemCoreClock = (SCGOUTClock / Divider);
135 }
136 
137 /* ----------------------------------------------------------------------------
138    -- SystemInitHook()
139    ---------------------------------------------------------------------------- */
140 
SystemInitHook(void)141 __attribute__ ((weak)) void SystemInitHook (void) {
142   /* Void implementation of the weak function. */
143 }
144