1 /* 2 ** ################################################################### 3 ** Processors: MKE12Z512VLH9 4 ** MKE12Z512VLL9 5 ** 6 ** Compilers: Freescale C/C++ for Embedded ARM 7 ** GNU C Compiler 8 ** IAR ANSI C/C++ Compiler for ARM 9 ** Keil ARM C/C++ Compiler 10 ** MCUXpresso Compiler 11 ** 12 ** Reference manual: KE1xZP100M96SF0RM, Rev. 1, Sep. 2023 13 ** Version: rev. 2.0, 2023-10-08 14 ** Build: b231008 15 ** 16 ** Abstract: 17 ** Provides a system configuration function and a global variable that 18 ** contains the system frequency. It configures the device and initializes 19 ** the oscillator (PLL) that is part of the microcontroller device. 20 ** 21 ** Copyright 2016 Freescale Semiconductor, Inc. 22 ** Copyright 2016-2023 NXP 23 ** SPDX-License-Identifier: BSD-3-Clause 24 ** 25 ** http: www.nxp.com 26 ** mail: support@nxp.com 27 ** 28 ** Revisions: 29 ** - rev. 1.0 (2023-03-01) 30 ** Initial version. 31 ** - rev. 2.0 (2023-10-08) 32 ** Based on Rev.1 RM. 33 ** 34 ** ################################################################### 35 */ 36 37 /*! 38 * @file MKE12Z9 39 * @version 2.0 40 * @date 2023-10-08 41 * @brief Device specific configuration file for MKE12Z9 (implementation file) 42 * 43 * Provides a system configuration function and a global variable that contains 44 * the system frequency. It configures the device and initializes the oscillator 45 * (PLL) that is part of the microcontroller device. 46 */ 47 48 #include <stdint.h> 49 #include "fsl_device_registers.h" 50 51 52 53 /* ---------------------------------------------------------------------------- 54 -- Core clock 55 ---------------------------------------------------------------------------- */ 56 57 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 58 59 /* ---------------------------------------------------------------------------- 60 -- SystemInit() 61 ---------------------------------------------------------------------------- */ 62 SystemInit(void)63void SystemInit (void) { 64 65 #if (DISABLE_WDOG) 66 if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) 67 { 68 WDOG->CNT = WDOG_UPDATE_KEY; 69 } 70 else 71 { 72 WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; 73 WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; 74 } 75 WDOG->TOVAL = 0xFFFFU; 76 WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; 77 #endif /* (DISABLE_WDOG) */ 78 79 SystemInitHook(); 80 } 81 82 /* ---------------------------------------------------------------------------- 83 -- SystemCoreClockUpdate() 84 ---------------------------------------------------------------------------- */ 85 SystemCoreClockUpdate(void)86void SystemCoreClockUpdate (void) { 87 88 uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */ 89 uint16_t Divider; 90 Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U); 91 92 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { 93 case 0x1: 94 /* System OSC */ 95 SCGOUTClock = CPU_XTAL_CLK_HZ; 96 break; 97 case 0x2: 98 /* Slow IRC */ 99 SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U); 100 break; 101 case 0x3: 102 /* Fast IRC */ 103 SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U; 104 break; 105 case 0x5: 106 /* Low Power FLL */ 107 SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U; 108 break; 109 default: 110 SCGOUTClock = 0U; 111 break; 112 } 113 SystemCoreClock = (SCGOUTClock / Divider); 114 } 115 116 /* ---------------------------------------------------------------------------- 117 -- SystemInitHook() 118 ---------------------------------------------------------------------------- */ 119 SystemInitHook(void)120__attribute__ ((weak)) void SystemInitHook (void) { 121 /* Void implementation of the weak function. */ 122 } 123