1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef FSL_EDMA_CORE_H_ 8 #define FSL_EDMA_CORE_H_ 9 10 #include "fsl_edma_soc.h" 11 12 /*! 13 * @addtogroup edma_core 14 * @{ 15 */ 16 17 /******************************************************************************* 18 * Definitions 19 ******************************************************************************/ 20 #define DMA_CSR_INTMAJOR_MASK (0x2U) 21 #define DMA_CSR_INTHALF_MASK (0x4U) 22 #define DMA_CSR_DREQ_MASK (0x8U) 23 #define DMA_CSR_ESG_MASK (0x10U) 24 #define DMA_CSR_BWC_MASK (0xC000U) 25 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U)) 26 #define DMA_CSR_START_MASK (0x1U) 27 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) 28 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) 29 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) 30 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) 31 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) 32 #define DMA_ATTR_SMOD_MASK (0xF800U) 33 #define DMA_ATTR_DMOD_MASK (0xF8U) 34 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) 35 #define DMA_CSR_MAJORELINK_MASK (0x20U) 36 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) 37 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) 38 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) 39 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 40 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 41 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 42 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 43 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 44 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 45 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U)) 46 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U)) 47 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) 48 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) 49 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U)) 50 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U)) 51 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U)) 52 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU)) 53 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU)) 54 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U)) 55 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U)) 56 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U)) 57 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U)) 58 #define DMA_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U)) 59 #define DMA_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU)) 60 #define DMA_CH_CSR_SIGNEXT_MASK (0x3F0000U) 61 #define DMA_CH_CSR_SIGNEXT_SHIFT (16U) 62 #define DMA_CH_CSR_SWAP_MASK (0xF000U) 63 #define DMA_CH_CSR_SWAP_SHIFT (12U) 64 #define DMA_CH_SBR_INSTR_MASK (0x2000U) 65 #define DMA_CH_SBR_INSTR_SHIFT (13U) 66 #define DMA_CH_MUX_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU)) 67 68 /*! @brief DMA error flag */ 69 #if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA 70 #define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK 71 #define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK 72 #define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK 73 #define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK 74 #define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK 75 #define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK 76 #define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK 77 #define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK 78 #define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK 79 #define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK 80 #define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK 81 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) 82 #define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK 83 #endif 84 #define DMA_ERR_FLAG DMA_ES_VLD_MASK 85 86 /*! @brief get/clear DONE status*/ 87 #define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel) 88 #define DMA_GET_DONE_STATUS(base, channel) \ 89 ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT) 90 /*! @brief enable/disable error interrupt*/ 91 #define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel)) 92 #define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel))) 93 /*! @brief get/clear error status*/ 94 #define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) 95 #define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel) 96 /*! @brief get/clear int status*/ 97 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U)) 98 #define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel) 99 100 #else 101 102 #define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK 103 #define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK 104 #define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK 105 #define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK 106 #define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK 107 #define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK 108 #define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK 109 #define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK 110 #define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK 111 #define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK 112 #define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK 113 114 /*! @brief get/clear DONE bit*/ 115 #define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK) 116 #define DMA_GET_DONE_STATUS(base, channel) \ 117 ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT) 118 /*! @brief enable/disable error interupt*/ 119 #define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK) 120 #define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK) 121 /*! @brief get/clear error status*/ 122 #define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK) 123 #define DMA_GET_ERROR_STATUS(base, channel) \ 124 (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) 125 /*! @brief get/clear INT status*/ 126 #define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK) 127 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U)) 128 #endif /*FSL_EDMA_SOC_IP_EDMA*/ 129 130 /*! @brief enable/dsiable MAJOR/HALF INT*/ 131 #define DMA_ENABLE_MAJOR_INT(base, channel) \ 132 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK) 133 #define DMA_ENABLE_HALF_INT(base, channel) \ 134 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK) 135 #define DMA_DISABLE_MAJOR_INT(base, channel) \ 136 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK) 137 #define DMA_DISABLE_HALF_INT(base, channel) \ 138 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK) 139 140 /*!@brief EDMA tcd align size */ 141 #define EDMA_TCD_ALIGN_SIZE (32U) 142 143 /*!@brief edma core channel struture definition */ 144 typedef struct _edma_core_mp 145 { 146 __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ 147 __IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ 148 union 149 { 150 struct 151 { 152 __IO uint32_t MP_INT_LOW; /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */ 153 __I uint32_t MP_INT_HIGH; /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */ 154 __I uint32_t MP_HRS_LOW; /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */ 155 __I uint32_t MP_HRS_HIGH; /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */ 156 uint8_t RESERVED_0[8]; 157 __IO uint32_t MP_STOPCH; /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */ 158 uint8_t RESERVED_1[12]; 159 __I uint32_t MP_SSR_LOW; /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */ 160 __I uint32_t MP_SSR_HIGH; /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */ 161 uint8_t RESERVED_2[200]; 162 __IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */ 163 __IO uint32_t CH_MUX[64]; /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */ 164 uint8_t RESERVED_3[256]; 165 __IO uint32_t CH_PROT[64]; /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */ 166 } EDMA5_REG; 167 } MP_REGS; 168 } edma_core_mp_t; 169 170 /*!@brief edma core channel struture definition */ 171 typedef struct _edma_core_channel 172 { 173 __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ 174 __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ 175 __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ 176 __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ 177 __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ 178 union 179 { 180 struct 181 { 182 __IO uint8_t RESERVED_1[4]; 183 __IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ 184 } EDMA5_REG; 185 struct 186 { 187 __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ 188 __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ 189 } EDMA4_REG; 190 } CH_REGS; 191 } edma_core_channel_t; 192 193 /*! @brief eDMA tcd flag type */ 194 typedef enum _edma_tcd_type 195 { 196 kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */ 197 kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */ 198 } edma_tcd_type_t; 199 200 /*!@brief edma5 core TCD struture definition */ 201 typedef struct _edma5_core_tcd 202 { 203 __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ 204 __IO uint32_t SADDR_HIGH; /*!< SADDR HIGH register, used to save source address */ 205 __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ 206 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ 207 __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ 208 __IO uint32_t SLAST; /*!< SLAST register */ 209 __IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */ 210 __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ 211 __IO uint32_t DADDR_HIGH; /*!< DADDR HIGH register, used for destination address */ 212 __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ 213 __IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */ 214 __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ 215 __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ 216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ 217 __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ 218 uint8_t RESERVED[16]; /*!< Aligned 64 bytes */ 219 } edma5_core_tcd_t; 220 221 /*!@brief edma4 core TCD struture definition */ 222 typedef struct _edma4_core_tcd 223 { 224 __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ 225 __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ 226 __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ 227 __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ 228 __IO uint32_t SLAST; /*!< SLAST register */ 229 __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ 230 __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ 231 __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ 232 __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ 233 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ 234 __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ 235 } edma4_core_tcd_t; 236 237 /*!@brief edma core TCD struture definition */ 238 typedef struct _edma_core_tcd 239 { 240 union 241 { 242 edma4_core_tcd_t edma4_tcd; 243 #if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 244 edma5_core_tcd_t edma5_tcd; 245 #endif /* FSL_EDMA_SOC_IP_DMA5 */ 246 } TCD_REGS; 247 } edma_core_tcd_t; 248 249 /*!@brief EDMA typedef */ 250 typedef edma_core_channel_t EDMA_ChannelType; 251 typedef edma_core_tcd_t EDMA_TCDType; 252 typedef void EDMA_Type; 253 254 /*!@brief EDMA base address convert macro */ 255 #define EDMA_BASE(base) 256 #define EDMA_CHANNEL_BASE(base, channel) \ 257 ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ 258 (channel)*EDMA_CHANNEL_ARRAY_STEP(base))) 259 #define EDMA_TCD_BASE(base, channel) \ 260 ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ 261 (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) 262 #define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base))) 263 264 /*!@brief EDMA TCD type macro */ 265 #if defined FSL_FEATURE_EDMA_TCD_TYPEn 266 #define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x) 267 #else 268 #define EDMA_TCD_TYPE(x) (0) 269 #endif 270 271 #if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 272 /*!@brief EDMA TCD address convert macro */ 273 #define EDMA_TCD_SADDR(tcd, flag) \ 274 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \ 275 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR)))) 276 277 #define EDMA_TCD_SOFF(tcd, flag) \ 278 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \ 279 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF)))) 280 281 #define EDMA_TCD_ATTR(tcd, flag) \ 282 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \ 283 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR)))) 284 285 #define EDMA_TCD_NBYTES(tcd, flag) \ 286 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \ 287 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES)))) 288 289 #define EDMA_TCD_SLAST(tcd, flag) \ 290 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \ 291 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST)))) 292 293 #define EDMA_TCD_DADDR(tcd, flag) \ 294 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \ 295 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR)))) 296 297 #define EDMA_TCD_DOFF(tcd, flag) \ 298 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \ 299 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF)))) 300 301 #define EDMA_TCD_CITER(tcd, flag) \ 302 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \ 303 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER)))) 304 305 #define EDMA_TCD_DLAST_SGA(tcd, flag) \ 306 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? \ 307 (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \ 308 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA)))) 309 310 #define EDMA_TCD_CSR(tcd, flag) \ 311 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \ 312 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR)))) 313 314 #define EDMA_TCD_BITER(tcd, flag) \ 315 (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \ 316 (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER)))) 317 #else 318 /*!@brief EDMA TCD address convert macro */ 319 #define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR) 320 321 #define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF) 322 323 #define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR) 324 325 #define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES) 326 327 #define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST) 328 329 #define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR) 330 331 #define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF) 332 333 #define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER) 334 335 #define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA) 336 337 #define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR) 338 339 #define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER) 340 #endif /* FSL_EDMA_SOC_IP_DMA5 */ 341 /******************************************************************************* 342 * API 343 ******************************************************************************/ 344 345 #ifdef __cplusplus 346 extern "C" { 347 #endif 348 349 #ifdef __cplusplus 350 } 351 #endif 352 353 /*! 354 * @} 355 */ 356 357 #endif /* FSL_EDMA_CORE_H_ */ 358
