1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_MMDVSQ_H_
10 #define FSL_MMDVSQ_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup mmdvsq
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*! @{ */
25 #define FSL_MMSVSQ_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
26 /*! @} */
27
28 /*! @brief MMDVSQ execution status */
29 typedef enum _mmdvsq_execution_status
30 {
31 kMMDVSQ_IdleSquareRoot = 0x01U, /*!< MMDVSQ is idle; the last calculation was a square root */
32 kMMDVSQ_IdleDivide = 0x02U, /*!< MMDVSQ is idle; the last calculation was division */
33 kMMDVSQ_BusySquareRoot = 0x05U, /*!< MMDVSQ is busy processing a square root calculation */
34 kMMDVSQ_BusyDivide = 0x06U /*!< MMDVSQ is busy processing a division calculation */
35 } mmdvsq_execution_status_t;
36
37 /*! @brief MMDVSQ divide fast start select */
38 typedef enum _mmdvsq_fast_start_select
39 {
40 kMMDVSQ_EnableFastStart = 0U, /*!< Division operation is initiated by a write to the DSOR register */
41 kMMDVSQ_DisableFastStart =
42 1U /*!< Division operation is initiated by a write to CSR[SRT] = 1; normal start instead fast start */
43 } mmdvsq_fast_start_select_t;
44
45 /*******************************************************************************
46 * API
47 ******************************************************************************/
48
49 #if defined(__cplusplus)
50 extern "C" {
51 #endif /* __cplusplus */
52
53 /*!
54 * @name MMDVSQ functional Operation
55 * @{
56 */
57
58 /*!
59 * @brief Performs the MMDVSQ division operation and returns the remainder.
60 *
61 * @param base MMDVSQ peripheral address
62 * @param dividend Dividend value
63 * @param divisor Divisor value
64 * @param isUnsigned Mode of unsigned divide
65 * - true unsigned divide
66 * - false signed divide
67 *
68 */
69 int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned);
70
71 /*!
72 * @brief Performs the MMDVSQ division operation and returns the quotient.
73 *
74 * @param base MMDVSQ peripheral address
75 * @param dividend Dividend value
76 * @param divisor Divisor value
77 * @param isUnsigned Mode of unsigned divide
78 * - true unsigned divide
79 * - false signed divide
80 *
81 */
82 int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned);
83
84 /*!
85 * @brief Performs the MMDVSQ square root operation.
86 *
87 * This function performs the MMDVSQ square root operation and returns the square root
88 * result of a given radicand value.
89 *
90 * @param base MMDVSQ peripheral address
91 * @param radicand Radicand value
92 *
93 */
94 uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand);
95
96 /*! @} */
97
98 /*!
99 * @name MMDVSQ status Operation
100 * @{
101 */
102
103 /*!
104 * @brief Gets the MMDVSQ execution status.
105 *
106 * This function checks the current MMDVSQ execution status of the combined
107 * CSR[BUSY, DIV, SQRT] indicators.
108 *
109 * @param base MMDVSQ peripheral address
110 *
111 * @return Current MMDVSQ execution status
112 */
MMDVSQ_GetExecutionStatus(MMDVSQ_Type * base)113 static inline mmdvsq_execution_status_t MMDVSQ_GetExecutionStatus(MMDVSQ_Type *base)
114 {
115 uint32_t tmp = base->CSR >> MMDVSQ_CSR_SQRT_SHIFT;
116
117 return (mmdvsq_execution_status_t)tmp;
118 }
119
120 /*!
121 * @brief Configures MMDVSQ fast start mode.
122 *
123 * This function sets the MMDVSQ division fast start. The MMDVSQ supports two
124 * mechanisms for initiating a division operation. The default mechanism is
125 * a “fast start” where a write to the DSOR register begins the division.
126 * Alternatively, the start mechanism can begin after a write to the CSR
127 * register with CSR[SRT] set.
128 *
129 * @param base MMDVSQ peripheral address
130 * @param mode Mode of Divide-Fast-Start
131 * - kMmdvsqDivideFastStart = 0
132 * - kMmdvsqDivideNormalStart = 1
133 */
MMDVSQ_SetFastStartConfig(MMDVSQ_Type * base,mmdvsq_fast_start_select_t mode)134 static inline void MMDVSQ_SetFastStartConfig(MMDVSQ_Type *base, mmdvsq_fast_start_select_t mode)
135 {
136 if (mode == kMMDVSQ_DisableFastStart)
137 {
138 base->CSR |= MMDVSQ_CSR_DFS_MASK;
139 }
140 else
141 {
142 base->CSR &= ~MMDVSQ_CSR_DFS_MASK;
143 }
144 }
145
146 /*!
147 * @brief Configures the MMDVSQ divide-by-zero mode.
148 *
149 * This function configures the MMDVSQ response to divide-by-zero
150 * calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read
151 * of the RES register is error-terminated to signal the processor of the
152 * attempted divide-by-zero. Otherwise, the register contents are returned.
153 *
154 * @param base MMDVSQ peripheral address
155 * @param isDivByZero Mode of Divide-By-Zero
156 * - kMmdvsqDivideByZeroDis = 0
157 * - kMmdvsqDivideByZeroEn = 1
158 */
MMDVSQ_SetDivideByZeroConfig(MMDVSQ_Type * base,bool isDivByZero)159 static inline void MMDVSQ_SetDivideByZeroConfig(MMDVSQ_Type *base, bool isDivByZero)
160 {
161 if (isDivByZero)
162 {
163 base->CSR |= MMDVSQ_CSR_DZE_MASK;
164 }
165 else
166 {
167 base->CSR &= ~MMDVSQ_CSR_DZE_MASK;
168 }
169 }
170
171 /*! @} */
172
173 #if defined(__cplusplus)
174 }
175 #endif /* __cplusplus */
176
177 /*! @}*/
178
179 #endif /* FSL_MMDVSQ_H_ */
180
