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Searched refs:refSrc (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm35z75m/project_template/
Dclock_config.c178 … .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
268 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm34z50mv3/
Dclock_config.c161 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
255 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm34z50mv3/project_template/
Dclock_config.c162 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
256 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm34z75m/
Dclock_config.c175 … .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
271 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm35z75m/
Dclock_config.c181 … .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
277 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/twrkm34z75m/project_template/
Dclock_config.c209 … .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
307 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34ZA5/project_template/
Dclock_config.c108 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM33ZA5/project_template/
Dclock_config.c109 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM14ZA5/project_template/
Dclock_config.c108 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM35Z7/project_template/
Dclock_config.c108 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34Z7/project_template/
Dclock_config.c109 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM33ZA5/drivers/
Dfsl_clock.c1204 mcg_c5 |= MCG_C5_PLLREFSEL0(config->refSrc); in CLOCK_EnablePll0()
1212 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_EnablePll0()
1249 MCG->C11 = mcg_c11 | MCG_C11_PLLREFSEL1(config->refSrc) | MCG_C11_PRDIV1(config->prdiv) | in CLOCK_EnablePll1()
2449 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_SetPbeMode()
Dfsl_clock.h644 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM14ZA5/drivers/
Dfsl_clock.c1204 mcg_c5 |= MCG_C5_PLLREFSEL0(config->refSrc); in CLOCK_EnablePll0()
1212 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_EnablePll0()
1249 MCG->C11 = mcg_c11 | MCG_C11_PLLREFSEL1(config->refSrc) | MCG_C11_PRDIV1(config->prdiv) | in CLOCK_EnablePll1()
2449 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_SetPbeMode()
Dfsl_clock.h644 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34ZA5/drivers/
Dfsl_clock.h573 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */ member
Dfsl_clock.c863 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_EnablePll0()
1793 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_SetPbeMode()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM35Z7/drivers/
Dfsl_clock.h584 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */ member
Dfsl_clock.c901 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_EnablePll0()
1831 … MCG->C7 = (uint8_t)((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_SetPbeMode()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.h581 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */ member
Dfsl_clock.c873 MCG->C7 = (MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc); in CLOCK_EnablePll0()
1800 MCG->C7 = ((MCG->C7 & ~MCG_C7_PLL32KREFSEL_MASK) | MCG_C7_PLL32KREFSEL(config->refSrc)); in CLOCK_SetPbeMode()