1 /*
2 * Copyright 2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
12 * and flash clock are in allowed range during clock mode switch.
13 *
14 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
15 *
16 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
17 * internal reference clock(MCGIRCLK). Follow the steps to setup:
18 *
19 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
20 *
21 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
22 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
23 * explicitly to setup MCGIRCLK.
24 *
25 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
26 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
27 * if the target mode is not FLL mode, the FLL is disabled.
28 *
29 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
30 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
31 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
32 *
33 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
34 */
35
36 /* clang-format off */
37 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
38 !!GlobalInfo
39 product: Clocks v7.0
40 processor: MKM34Z256xxx7
41 package_id: MKM34Z256VLQ7
42 mcu_data: ksdk2_0
43 processor_version: 9.0.1
44 board: TWR-KM34Z75M
45 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
46 /* clang-format on */
47
48 #include "fsl_smc.h"
49 #include "fsl_irtc.h"
50 #include "clock_config.h"
51
52 /*******************************************************************************
53 * Definitions
54 ******************************************************************************/
55 #define IRTC_OSC_CAP0P 0U /*!< RTC oscillator 0pF capacitor load */
56 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
57 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
58 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
59 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
60 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
61
62 /*******************************************************************************
63 * Variables
64 ******************************************************************************/
65 /* System clock frequency. */
66 extern uint32_t SystemCoreClock;
67
68 /*******************************************************************************
69 * Code
70 ******************************************************************************/
71 /*FUNCTION**********************************************************************
72 *
73 * Function Name : CLOCK_CONFIG_FllStableDelay
74 * Description : This function is used to delay for FLL stable.
75 *
76 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)77 static void CLOCK_CONFIG_FllStableDelay(void)
78 {
79 uint32_t i = 30000U;
80 while (i--)
81 {
82 __NOP();
83 }
84 }
85
86 /*FUNCTION**********************************************************************
87 *
88 * Function Name : CLOCK_CONFIG_EnableRtcOsc
89 * Description : This function is used to configuring RTC oscillator
90 * Param capLoad : RTC oscillator capacity load
91 *
92 *END**************************************************************************/
CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)93 static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)
94 {
95 if ((RTC->GP_DATA_REG & 0x01U) != 0U) { /* Only if the Rtc oscillator is not already enabled */
96 /* Set the specified capacitor configuration for the RTC oscillator */
97 IRTC_SetOscCapLoad(RTC, capLoad);
98 /* Enable the RTC 32KHz oscillator */
99 RTC->GP_DATA_REG &= ~0x01U;
100 }
101 }
102
103 /*******************************************************************************
104 ************************ BOARD_InitBootClocks function ************************
105 ******************************************************************************/
BOARD_InitBootClocks(void)106 void BOARD_InitBootClocks(void)
107 {
108 BOARD_BootClockRUN();
109 }
110
111 /*******************************************************************************
112 ********************** Configuration BOARD_BootClockRUN ***********************
113 ******************************************************************************/
114 /* clang-format off */
115 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
116 !!Configuration
117 name: BOARD_BootClockRUN
118 called_from_default_init: true
119 outputs:
120 - {id: Bus_clock.outFreq, value: 71.991296/3 MHz}
121 - {id: Core_clock.outFreq, value: 71.991296 MHz}
122 - {id: Flash_clock.outFreq, value: 71.991296/3 MHz}
123 - {id: LPO_clock.outFreq, value: 1 kHz}
124 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
125 - {id: OSC32KSELCLK.outFreq, value: 32.768 kHz}
126 - {id: OSCERCLK.outFreq, value: 8 MHz}
127 - {id: PLLFLLCLK.outFreq, value: 71.991296 MHz}
128 - {id: System_clock.outFreq, value: 71.991296 MHz}
129 settings:
130 - {id: MCGMode, value: FEE}
131 - {id: MCG.CLKS.sel, value: MCG.PLLS}
132 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
133 - {id: MCG.FLL_mul.scale, value: '2197', locked: true}
134 - {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK}
135 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
136 - {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK}
137 - {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV}
138 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
139 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
140 - {id: MCG_C2_RANGE0_CFG, value: High}
141 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
142 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
143 - {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk}
144 - {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK}
145 - {id: SIM.CLKDIVBUS.scale, value: '3', locked: true}
146 - {id: SIM.CLKDIVSYS.scale, value: '1', locked: true}
147 - {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK}
148 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
149 - {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK}
150 - {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK}
151 - {id: XBARCLKOUTConfig, value: 'no'}
152 sources:
153 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
154 - {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true}
155 - {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz}
156 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
157 /* clang-format on */
158
159 /*******************************************************************************
160 * Variables for BOARD_BootClockRUN configuration
161 ******************************************************************************/
162 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
163 {
164 .mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
165 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
166 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
167 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
168 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
169 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
170 .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
171 .oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */
172 .pll0Config =
173 {
174 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
175 .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
176 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
177 },
178 };
179 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
180 {
181 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
182 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
183 .clkdiv1 = 0x2000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */
184 };
185 const osc_config_t oscConfig_BOARD_BootClockRUN =
186 {
187 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
188 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
189 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
190 .oscerConfig =
191 {
192 .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
193 }
194 };
195
196 /*******************************************************************************
197 * Code for BOARD_BootClockRUN configuration
198 ******************************************************************************/
BOARD_BootClockRUN(void)199 void BOARD_BootClockRUN(void)
200 {
201 /* Use RTC_CLKIN input clock directly. */
202 CLOCK_SetXtal32Freq(32768U);
203 /* Set the system clock dividers in SIM to safe value. */
204 CLOCK_SetSimSafeDivs();
205 /* Enable RTC oscillator. */
206 CLOCK_CONFIG_EnableRtcOsc((IRTC_OSC_CAP0P));
207 /* Initializes OSC0 according to board configuration. */
208 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
209 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
210 /* Set MCG to FEE mode. */
211 CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
212 mcgConfig_BOARD_BootClockRUN.frdiv,
213 mcgConfig_BOARD_BootClockRUN.dmx32,
214 mcgConfig_BOARD_BootClockRUN.drs,
215 CLOCK_CONFIG_FllStableDelay);
216 /* Configure the Internal Reference clock (MCGIRCLK). */
217 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
218 mcgConfig_BOARD_BootClockRUN.ircs,
219 mcgConfig_BOARD_BootClockRUN.fcrdiv);
220 /* Set the clock configuration in SIM module. */
221 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
222 /* Set SystemCoreClock variable. */
223 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
224 }
225
226 /*******************************************************************************
227 ********************* Configuration BOARD_BootClockVLPR ***********************
228 ******************************************************************************/
229 /* clang-format off */
230 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
231 !!Configuration
232 name: BOARD_BootClockVLPR
233 outputs:
234 - {id: Bus_clock.outFreq, value: 1 MHz}
235 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
236 - {id: Flash_clock.outFreq, value: 1 MHz}
237 - {id: LPO_clock.outFreq, value: 1 kHz}
238 - {id: MCGIRCLK.outFreq, value: 4 MHz}
239 - {id: System_clock.outFreq, value: 4 MHz}
240 settings:
241 - {id: powerMode, value: VLPR}
242 - {id: MCG.FCRDIV.scale, value: '1'}
243 - {id: MCG.FRDIV.scale, value: '32'}
244 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
245 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
246 - {id: MCG_C2_RANGE0_CFG, value: High}
247 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
248 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
249 - {id: SIM.CLKDIVBUS.scale, value: '4'}
250 sources:
251 - {id: OSC.OSC.outFreq, value: 8 MHz}
252 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
253 /* clang-format on */
254
255 /*******************************************************************************
256 * Variables for BOARD_BootClockVLPR configuration
257 ******************************************************************************/
258 const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
259 {
260 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
261 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
262 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
263 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
264 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
265 .drs = kMCG_DrsLow, /* Low frequency range */
266 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
267 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
268 .pll0Config =
269 {
270 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
271 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
272 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
273 },
274 };
275 const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
276 {
277 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
278 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
279 .clkdiv1 = 0x3000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /4, FLASHCLKMODE: /1 */
280 };
281 const osc_config_t oscConfig_BOARD_BootClockVLPR =
282 {
283 .freq = 0U, /* Oscillator frequency: 0Hz */
284 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
285 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
286 .oscerConfig =
287 {
288 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
289 }
290 };
291
292 /*******************************************************************************
293 * Code for BOARD_BootClockVLPR configuration
294 ******************************************************************************/
BOARD_BootClockVLPR(void)295 void BOARD_BootClockVLPR(void)
296 {
297 /* Set the system clock dividers in SIM to safe value. */
298 CLOCK_SetSimSafeDivs();
299 /* Set MCG to BLPI mode. */
300 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
301 mcgConfig_BOARD_BootClockVLPR.ircs,
302 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
303 /* Set the clock configuration in SIM module. */
304 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
305 /* Set VLPR power mode. */
306 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
307 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
308 SMC_SetPowerModeVlpr(SMC, false);
309 #else
310 SMC_SetPowerModeVlpr(SMC);
311 #endif
312 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
313 {
314 }
315 /* Set SystemCoreClock variable. */
316 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
317 }
318
319
