1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2021, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.0. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
63 /*@}*/
64
65 /* Definition for delay API in clock driver, users can redefine it to the real application. */
66 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
67 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (75000000UL)
68 #endif
69
70 /*! @brief External XTAL0 (OSC0) clock frequency.
71 *
72 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
73 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
74 * if XTAL0 is 8 MHz:
75 * @code
76 * Set up the OSC0
77 * CLOCK_InitOsc0(...);
78 * Set the XTAL0 value to the clock driver.
79 * CLOCK_SetXtal0Freq(80000000);
80 * @endcode
81 *
82 * This is important for the multicore platforms where only one core needs to set up the
83 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
84 * to get a valid clock frequency.
85 */
86 extern volatile uint32_t g_xtal0Freq;
87
88 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
89 *
90 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
91 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
92 *
93 * This is important for the multicore platforms where only one core needs to set up
94 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
95 * to get a valid clock frequency.
96 */
97 extern volatile uint32_t g_xtal32Freq;
98
99 #if (defined(OSC) && !(defined(OSC0)))
100 #define OSC0 OSC
101 #endif
102
103 /*! @brief Clock ip name array for DMAMUX. */
104 #define DMAMUX_CLOCKS \
105 { \
106 kCLOCK_Dmamux0 \
107 }
108
109 /*! @brief Clock ip name array for RTC. */
110 #define RTC_CLOCKS \
111 { \
112 kCLOCK_Rtc0 \
113 }
114
115 /*! @brief Clock ip name array for SPI. */
116 #define SPI_CLOCKS \
117 { \
118 kCLOCK_Spi0, kCLOCK_Spi1 \
119 }
120
121 /*! @brief Clock ip name array for SLCD. */
122 #define SLCD_CLOCKS \
123 { \
124 kCLOCK_Slcd0 \
125 }
126
127 /*! @brief Clock ip name array for EWM. */
128 #define EWM_CLOCKS \
129 { \
130 kCLOCK_Ewm0 \
131 }
132
133 /*! @brief Clock ip name array for AFE. */
134 #define AFE_CLOCKS \
135 { \
136 kCLOCK_Afe0 \
137 }
138
139 /*! @brief Clock ip name array for LPUART. */
140 #define LPUART_CLOCKS \
141 { \
142 kCLOCK_Lpuart0 \
143 }
144
145 /*! @brief Clock ip name array for ADC16. */
146 #define ADC16_CLOCKS \
147 { \
148 kCLOCK_Adc0 \
149 }
150
151 /*! @brief Clock ip name array for XBAR. */
152 #define XBAR_CLOCKS \
153 { \
154 kCLOCK_Xbar \
155 }
156
157 /*! @brief Clock ip name array for MPU. */
158 #define SYSMPU_CLOCKS \
159 { \
160 kCLOCK_Sysmpu0 \
161 }
162
163 /*! @brief Clock ip name array for VREF. */
164 #define VREF_CLOCKS \
165 { \
166 kCLOCK_Vref0 \
167 }
168
169 /*! @brief Clock ip name array for DMA. */
170 #define DMA_CLOCKS \
171 { \
172 kCLOCK_Dma0 \
173 }
174
175 /*! @brief Clock ip name array for PORT. */
176 #define PORT_CLOCKS \
177 { \
178 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE, kCLOCK_PortF, kCLOCK_PortG, \
179 kCLOCK_PortH, kCLOCK_PortI, kCLOCK_PortJ, kCLOCK_PortK, kCLOCK_PortL, kCLOCK_PortM \
180 }
181
182 /*! @brief Clock ip name array for UART. */
183 #define UART_CLOCKS \
184 { \
185 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3 \
186 }
187
188 /*! @brief Clock ip name array for PIT. */
189 #define PIT_CLOCKS \
190 { \
191 kCLOCK_Pit0, kCLOCK_Pit1 \
192 }
193
194 /*! @brief Clock ip name array for RNGA. */
195 #define RNGA_CLOCKS \
196 { \
197 kCLOCK_Rnga0 \
198 }
199
200 /*! @brief Clock ip name array for CRC. */
201 #define CRC_CLOCKS \
202 { \
203 kCLOCK_Crc0 \
204 }
205
206 /*! @brief Clock ip name array for I2C. */
207 #define I2C_CLOCKS \
208 { \
209 kCLOCK_I2c0, kCLOCK_I2c1 \
210 }
211
212 /*! @brief Clock ip name array for LPTMR. */
213 #define LPTMR_CLOCKS \
214 { \
215 kCLOCK_Lptmr0 \
216 }
217
218 /*! @brief Clock ip name array for TMR. */
219 #define TMR_CLOCKS \
220 { \
221 kCLOCK_Tmr0, kCLOCK_Tmr1, kCLOCK_Tmr2, kCLOCK_Tmr3 \
222 }
223
224 /*! @brief Clock ip name array for PDB. */
225 #define PDB_CLOCKS \
226 { \
227 kCLOCK_Pdb0 \
228 }
229
230 /*! @brief Clock ip name array for FTF. */
231 #define FTF_CLOCKS \
232 { \
233 kCLOCK_Ftf0 \
234 }
235
236 /*! @brief Clock ip name array for CMP. */
237 #define CMP_CLOCKS \
238 { \
239 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
240 }
241
242 /*!
243 * @brief LPO clock frequency.
244 */
245 #define LPO_CLK_FREQ 1000U
246
247 /*! @brief Peripherals clock source definition. */
248 #define SYS_CLK kCLOCK_CoreSysClk
249 #define BUS_CLK kCLOCK_BusClk
250
251 #define I2C0_CLK_SRC BUS_CLK
252 #define I2C1_CLK_SRC BUS_CLK
253 #define SPI0_CLK_SRC SYS_CLK
254 #define SPI1_CLK_SRC SYS_CLK
255 #define UART0_CLK_SRC BUS_CLK
256 #define UART1_CLK_SRC SYS_CLK
257 #define UART2_CLK_SRC BUS_CLK
258 #define UART3_CLK_SRC SYS_CLK
259
260 /*! @brief Clock name used to get clock frequency. */
261 typedef enum _clock_name
262 {
263
264 /* ----------------------------- System layer clock -------------------------------*/
265 kCLOCK_CoreSysClk, /*!< Core/system clock */
266 kCLOCK_PlatClk, /*!< Platform clock */
267 kCLOCK_BusClk, /*!< Bus clock */
268 kCLOCK_FlashClk, /*!< Flash clock */
269 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
270
271 /* ---------------------------------- OSC clock -----------------------------------*/
272 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
273 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
274
275 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
276 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
277 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
278 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
279 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
280 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
281 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
282
283 /* --------------------------------- Other clock ----------------------------------*/
284 kCLOCK_LpoClk, /*!< LPO clock */
285
286 } clock_name_t;
287
288 /*------------------------------------------------------------------------------
289
290 clock_gate_t definition:
291
292 31 16 0
293 -----------------------------------------------------------------
294 | SIM_SCGC register offset | control bit offset in SCGC |
295 -----------------------------------------------------------------
296
297 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
298 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
299
300 kClockGateSdhc0 = (0x1030 << 16) | 17;
301
302 ------------------------------------------------------------------------------*/
303
304 #define CLK_GATE_REG_OFFSET_SHIFT 16U
305 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
306 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
307 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
308
309 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
310 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
311 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
312
313 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
314 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
315
316 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
317 typedef enum _clock_ip_name
318 {
319 kCLOCK_IpInvalid = 0U,
320 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
321 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 7U),
322 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 8U),
323 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
324 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
325 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
326 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
327 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 15U),
328 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 18U),
329 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 18U),
330 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 18U),
331 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x1034U, 21U),
332 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x1034U, 22U),
333
334 kCLOCK_Slcd0 = CLK_GATE_DEFINE(0x1038U, 3U),
335 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 6U),
336 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 7U),
337 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 8U),
338 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 9U),
339 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 10U),
340 kCLOCK_PortF = CLK_GATE_DEFINE(0x1038U, 11U),
341 kCLOCK_PortG = CLK_GATE_DEFINE(0x1038U, 12U),
342 kCLOCK_PortH = CLK_GATE_DEFINE(0x1038U, 13U),
343 kCLOCK_PortI = CLK_GATE_DEFINE(0x1038U, 14U),
344 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x1038U, 16U),
345 kCLOCK_Rtcreg = CLK_GATE_DEFINE(0x1038U, 17U),
346 kCLOCK_Xbar = CLK_GATE_DEFINE(0x1038U, 21U),
347 kCLOCK_Tmr0 = CLK_GATE_DEFINE(0x1038U, 23U),
348 kCLOCK_Tmr1 = CLK_GATE_DEFINE(0x1038U, 24U),
349 kCLOCK_Tmr2 = CLK_GATE_DEFINE(0x1038U, 25U),
350 kCLOCK_Tmr3 = CLK_GATE_DEFINE(0x1038U, 26U),
351
352 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
353 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
354 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
355 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U),
356 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 11U),
357 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 13U),
358 kCLOCK_Pit1 = CLK_GATE_DEFINE(0x103CU, 14U),
359 kCLOCK_Afe0 = CLK_GATE_DEFINE(0x103CU, 16U),
360 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 20U),
361 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
362 kCLOCK_PortJ = CLK_GATE_DEFINE(0x103CU, 23U),
363 kCLOCK_PortK = CLK_GATE_DEFINE(0x103CU, 24U),
364 kCLOCK_PortL = CLK_GATE_DEFINE(0x103CU, 25U),
365 kCLOCK_PortM = CLK_GATE_DEFINE(0x103CU, 26U),
366 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x103CU, 28U),
367
368 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 0U),
369 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
370 kCLOCK_Cau0 = CLK_GATE_DEFINE(0x1040U, 2U),
371 } clock_ip_name_t;
372
373 /*!@brief SIM configuration structure for clock setting. */
374 typedef struct _sim_clock_config
375 {
376 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
377 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
378 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
379 } sim_clock_config_t;
380
381 /*! @brief OSC work mode. */
382 typedef enum _osc_mode
383 {
384 kOSC_ModeExt = 0U, /*!< Use an external clock. */
385 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
386 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
387 #else
388 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
389 #endif
390 kOSC_ModeOscHighGain = 0U
391 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
392 | MCG_C2_EREFS_MASK
393 #else
394 | MCG_C2_EREFS0_MASK
395 #endif
396 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
397 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
398 #else
399 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
400 #endif
401 } osc_mode_t;
402
403 /*! @brief Oscillator capacitor load setting.*/
404 enum _osc_cap_load
405 {
406 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
407 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
408 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
409 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
410 };
411
412 /*! @brief OSCERCLK enable mode. */
413 enum _oscer_enable_mode
414 {
415 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
416 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
417 };
418
419 /*! @brief OSC configuration for OSCERCLK. */
420 typedef struct _oscer_config
421 {
422 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
423
424 } oscer_config_t;
425
426 /*!
427 * @brief OSC Initialization Configuration Structure
428 *
429 * Defines the configuration data structure to initialize the OSC.
430 * When porting to a new board, set the following members
431 * according to the board setting:
432 * 1. freq: The external frequency.
433 * 2. workMode: The OSC module mode.
434 */
435 typedef struct _osc_config
436 {
437 uint32_t freq; /*!< External clock frequency. */
438 uint8_t capLoad; /*!< Capacitor load setting. */
439 osc_mode_t workMode; /*!< OSC work mode setting. */
440 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
441 } osc_config_t;
442
443 /*! @brief MCG FLL reference clock source select. */
444 typedef enum _mcg_fll_src
445 {
446 kMCG_FllSrcExternal, /*!< External reference clock is selected */
447 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
448 } mcg_fll_src_t;
449
450 /*! @brief MCG internal reference clock select */
451 typedef enum _mcg_irc_mode
452 {
453 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
454 kMCG_IrcFast /*!< Fast internal reference clock selected */
455 } mcg_irc_mode_t;
456
457 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
458 typedef enum _mcg_dmx32
459 {
460 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
461 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
462 } mcg_dmx32_t;
463
464 /*! @brief MCG DCO range select */
465 typedef enum _mcg_drs
466 {
467 kMCG_DrsLow, /*!< Low frequency range */
468 kMCG_DrsMid, /*!< Mid frequency range */
469 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
470 kMCG_DrsHigh /*!< High frequency range */
471 } mcg_drs_t;
472
473 /*! @brief MCG PLL reference clock select */
474 typedef enum _mcg_pll_ref_src
475 {
476 kMCG_PllRefRtc, /*!< Selects 32k RTC oscillator. */
477 kMCG_PllRefIrc, /*!< Selects 32k IRC. */
478 kMCG_PllRefFllRef /*!< Selects FLL reference clock, the clock after FRDIV. */
479 } mcg_pll_ref_src_t;
480
481 /*! @brief MCGOUT clock source. */
482 typedef enum _mcg_clkout_src
483 {
484 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
485 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
486 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
487 } mcg_clkout_src_t;
488
489 /*! @brief MCG Automatic Trim Machine Select */
490 typedef enum _mcg_atm_select
491 {
492 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
493 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
494 } mcg_atm_select_t;
495
496 /*! @brief MCG OSC Clock Select */
497 typedef enum _mcg_oscsel
498 {
499 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
500 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
501 } mcg_oscsel_t;
502
503 /*! @brief MCG PLLCS select */
504 typedef enum _mcg_pll_clk_select
505 {
506 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
507 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
508 } mcg_pll_clk_select_t;
509
510 /*! @brief MCG clock monitor mode. */
511 typedef enum _mcg_monitor_mode
512 {
513 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
514 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
515 kMCG_MonitorReset /*!< System reset when clock lost. */
516 } mcg_monitor_mode_t;
517
518 /*! @brief MCG status. */
519 enum _mcg_status
520 {
521 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
522 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
523 function. */
524 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
525 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
526 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
527 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
528 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
529 it is in use. */
530 };
531
532 /*! @brief MCG status flags. */
533 enum _mcg_status_flags_t
534 {
535 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
536 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
537 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
538 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
539 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
540 };
541
542 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
543 enum _mcg_irclk_enable_mode
544 {
545 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
546 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
547 };
548
549 /*! @brief MCG PLL clock enable mode definition. */
550 enum _mcg_pll_enable_mode
551 {
552 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
553 MCG clock mode. Generally, the PLL
554 is disabled in FLL modes
555 (FEI/FBI/FEE/FBE). Setting the PLL clock
556 enable independent, enables the
557 PLL in the FLL modes. */
558 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
559 };
560
561 /*! @brief MCG mode definitions */
562 typedef enum _mcg_mode
563 {
564 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
565 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
566 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
567 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
568 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
569 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
570 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
571 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
572 kMCG_ModePEI, /*!< PEI - PLL Engaged Internal */
573 kMCG_ModePBI, /*!< PBI - PLL Bypassed Internal */
574 kMCG_ModeError /*!< Unknown mode */
575 } mcg_mode_t;
576
577 /*! @brief MCG PLL configuration. */
578 typedef struct _mcg_pll_config
579 {
580 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
581 mcg_pll_ref_src_t refSrc; /*!< PLL reference clock source. */
582 uint8_t frdiv; /*!< FLL reference clock divider. */
583 } mcg_pll_config_t;
584
585 /*! @brief MCG mode change configuration structure
586 *
587 * When porting to a new board, set the following members
588 * according to the board setting:
589 * 1. frdiv: If the FLL uses the external reference clock, set this
590 * value to ensure that the external reference clock divided by frdiv is
591 * in the 31.25 kHz to 39.0625 kHz range.
592 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
593 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
594 * FSL_FEATURE_MCG_PLL_REF_MAX range.
595 */
596 typedef struct _mcg_config
597 {
598 mcg_mode_t mcgMode; /*!< MCG mode. */
599
600 /* ----------------------- MCGIRCCLK settings ------------------------ */
601 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
602 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
603 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
604
605 /* ------------------------ MCG FLL settings ------------------------- */
606 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
607 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
608 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
609 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
610
611 /* ------------------------ MCG PLL settings ------------------------- */
612 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
613
614 } mcg_config_t;
615
616 /*******************************************************************************
617 * API
618 ******************************************************************************/
619
620 #if defined(__cplusplus)
621 extern "C" {
622 #endif /* __cplusplus */
623
624 /*!
625 * @brief Enable the clock for specific IP.
626 *
627 * @param name Which clock to enable, see \ref clock_ip_name_t.
628 */
CLOCK_EnableClock(clock_ip_name_t name)629 static inline void CLOCK_EnableClock(clock_ip_name_t name)
630 {
631 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
632 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
633 }
634
635 /*!
636 * @brief Disable the clock for specific IP.
637 *
638 * @param name Which clock to disable, see \ref clock_ip_name_t.
639 */
CLOCK_DisableClock(clock_ip_name_t name)640 static inline void CLOCK_DisableClock(clock_ip_name_t name)
641 {
642 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
643 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
644 }
645
646 /*!
647 * @brief Set ERCLK32K source.
648 *
649 * @param src The value to set ERCLK32K clock source.
650 */
CLOCK_SetEr32kClock(uint32_t src)651 static inline void CLOCK_SetEr32kClock(uint32_t src)
652 {
653 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
654 }
655
656 /*!
657 * @brief Set LPUART clock source.
658 *
659 * @param src The value to set LPUART clock source.
660 */
CLOCK_SetLpuartClock(uint32_t src)661 static inline void CLOCK_SetLpuartClock(uint32_t src)
662 {
663 SIM->CTRL_REG = ((SIM->CTRL_REG & ~SIM_CTRL_REG_LPUARTSRC_MASK) | SIM_CTRL_REG_LPUARTSRC(src));
664 }
665
666 /*!
667 * @brief Set XBAR clock source.
668 *
669 * @param src The value to set XBAR clock source.
670 */
CLOCK_SetXbarClock(uint32_t src)671 static inline void CLOCK_SetXbarClock(uint32_t src)
672 {
673 SIM->CTRL_REG = ((SIM->CTRL_REG & ~SIM_CTRL_REG_XBARCLKOUT_MASK) | SIM_CTRL_REG_XBARCLKOUT(src));
674 }
675
676 /*!
677 * @brief Set the clock selection of AFECLKSEL.
678 *
679 * @param src The value to set AFECLKSEL clock source.
680 */
CLOCK_SetAfeClkSrc(uint32_t src)681 static inline void CLOCK_SetAfeClkSrc(uint32_t src)
682 {
683 SIM->MISC_CTL = ((SIM->MISC_CTL & ~SIM_MISC_CTL_AFECLKSEL_MASK) | SIM_MISC_CTL_AFECLKSEL(src));
684 }
685
686 /*!
687 * @brief Set PLLFLLSEL clock source.
688 *
689 * @param src The value to set PLLFLLSEL clock source.
690 */
CLOCK_SetPllFllSelClock(uint32_t src)691 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
692 {
693 SIM->CTRL_REG = ((SIM->CTRL_REG & ~SIM_CTRL_REG_PLLFLLSEL_MASK) | SIM_CTRL_REG_PLLFLLSEL(src));
694 }
695
696 /*!
697 * @brief Set CLKOUT source.
698 *
699 * @param src The value to set CLKOUT source.
700 */
CLOCK_SetClkOutClock(uint32_t src)701 static inline void CLOCK_SetClkOutClock(uint32_t src)
702 {
703 SIM->CTRL_REG = ((SIM->CTRL_REG & ~SIM_CTRL_REG_CLKOUT_MASK) | SIM_CTRL_REG_CLKOUT(src));
704 }
705
706 /*!
707 * @brief Set ADC trigger clock source.
708 *
709 * @param src The value to set ADC trigger clock source.
710 */
CLOCK_SetAdcTriggerClock(uint32_t src)711 static inline void CLOCK_SetAdcTriggerClock(uint32_t src)
712 {
713 SIM->CTRL_REG = ((SIM->CTRL_REG & ~SIM_CTRL_REG_ADCTRGSEL_MASK) | SIM_CTRL_REG_ADCTRGSEL(src));
714 }
715
716 /*!
717 * @brief System clock divider
718 *
719 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
720 *
721 * @param sysClk System clock divider value.
722 *
723 * @param busClk Bus clock divider value.
724 *
725 * @param flashClk Flash clock mode value.
726 */
CLOCK_SetOutDiv(uint32_t sysClk,uint32_t busClk,uint32_t flashClk)727 static inline void CLOCK_SetOutDiv(uint32_t sysClk, uint32_t busClk, uint32_t flashClk)
728 {
729 SIM->CLKDIV1 = SIM_CLKDIV1_CLKDIVSYS(sysClk) | SIM_CLKDIV1_CLKDIVBUS(busClk) | SIM_CLKDIV1_FLASHCLKMODE(flashClk);
730 }
731
732 /*!
733 * @brief Gets the clock frequency for AFE module.
734 *
735 * This function checks the current mode configurations in MISC_CTL register.
736 *
737 * @return Clock frequency value in Hertz
738 */
739 uint32_t CLOCK_GetAfeFreq(void);
740
741 /*!
742 * @brief Gets the clock frequency for a specific clock name.
743 *
744 * This function checks the current clock configurations and then calculates
745 * the clock frequency for a specific clock name defined in clock_name_t.
746 * The MCG must be properly configured before using this function.
747 *
748 * @param clockName Clock names defined in clock_name_t
749 * @return Clock frequency value in Hertz
750 */
751 uint32_t CLOCK_GetFreq(clock_name_t clockName);
752
753 /*!
754 * @brief Get the core clock or system clock frequency.
755 *
756 * @return Clock frequency in Hz.
757 */
758 uint32_t CLOCK_GetCoreSysClkFreq(void);
759
760 /*!
761 * @brief Get the platform clock frequency.
762 *
763 * @return Clock frequency in Hz.
764 */
765 uint32_t CLOCK_GetPlatClkFreq(void);
766
767 /*!
768 * @brief Get the bus clock frequency.
769 *
770 * @return Clock frequency in Hz.
771 */
772 uint32_t CLOCK_GetBusClkFreq(void);
773
774 /*!
775 * @brief Get the flash clock frequency.
776 *
777 * @return Clock frequency in Hz.
778 */
779 uint32_t CLOCK_GetFlashClkFreq(void);
780
781 /*!
782 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
783 *
784 * @return Clock frequency in Hz.
785 */
786 uint32_t CLOCK_GetPllFllSelClkFreq(void);
787
788 /*!
789 * @brief Get the external reference 32K clock frequency (ERCLK32K).
790 *
791 * @return Clock frequency in Hz.
792 */
793 uint32_t CLOCK_GetEr32kClkFreq(void);
794
795 /*!
796 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
797 *
798 * @return Clock frequency in Hz.
799 */
800 uint32_t CLOCK_GetOsc0ErClkFreq(void);
801
802 /*!
803 * @brief Set the clock configure in SIM module.
804 *
805 * This function sets system layer clock settings in SIM module.
806 *
807 * @param config Pointer to the configure structure.
808 */
809 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
810
811 /*!
812 * @brief Set the system clock dividers in SIM to safe value.
813 *
814 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
815 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
816 * changes then the system level clocks may be out of range. This function could
817 * be used before MCG mode change, to make sure system level clocks are in allowed
818 * range.
819 */
CLOCK_SetSimSafeDivs(void)820 static inline void CLOCK_SetSimSafeDivs(void)
821 {
822 SIM->CLKDIV1 = 0x03000000U;
823 }
824
825 /*! @name MCG frequency functions. */
826 /*@{*/
827
828 /*!
829 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
830 *
831 * This function gets the MCG output clock frequency in Hz based on the current MCG
832 * register value.
833 *
834 * @return The frequency of MCGOUTCLK.
835 */
836 uint32_t CLOCK_GetOutClkFreq(void);
837
838 /*!
839 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
840 *
841 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
842 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
843 * disabled in low power state in other modes.
844 *
845 * @return The frequency of MCGFLLCLK.
846 */
847 uint32_t CLOCK_GetFllFreq(void);
848
849 /*!
850 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
851 *
852 * This function gets the MCG internal reference clock frequency in Hz based
853 * on the current MCG register value.
854 *
855 * @return The frequency of MCGIRCLK.
856 */
857 uint32_t CLOCK_GetInternalRefClkFreq(void);
858
859 /*!
860 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
861 *
862 * This function gets the MCG fixed frequency clock frequency in Hz based
863 * on the current MCG register value.
864 *
865 * @return The frequency of MCGFFCLK.
866 */
867 uint32_t CLOCK_GetFixedFreqClkFreq(void);
868
869 /*!
870 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
871 *
872 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
873 * register value.
874 *
875 * @return The frequency of MCGPLL0CLK.
876 */
877 uint32_t CLOCK_GetPll0Freq(void);
878
879 /*@}*/
880
881 /*! @name MCG clock configuration. */
882 /*@{*/
883
884 /*!
885 * @brief Enables or disables the MCG low power.
886 *
887 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
888 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
889 * PBI modes, enabling low power sets the MCG to BLPI mode.
890 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
891 *
892 * @param enable True to enable MCG low power, false to disable MCG low power.
893 */
CLOCK_SetLowPowerEnable(bool enable)894 static inline void CLOCK_SetLowPowerEnable(bool enable)
895 {
896 if (enable)
897 {
898 MCG->C2 |= MCG_C2_LP_MASK;
899 }
900 else
901 {
902 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
903 }
904 }
905
906 /*!
907 * @brief Configures the Internal Reference clock (MCGIRCLK).
908 *
909 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
910 * source. If the fast IRC is used, this function sets the fast IRC divider.
911 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
912 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
913 * using the function in these modes it is not allowed.
914 *
915 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
916 * @param ircs MCGIRCLK clock source, choose fast or slow.
917 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
918 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
919 * the configuration should not be changed. Otherwise, a glitch occurs.
920 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
921 */
922 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
923
924 /*!
925 * @brief Selects the MCG external reference clock.
926 *
927 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
928 * and waits for the clock source to be stable. Because the external reference
929 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
930 *
931 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
932 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
933 * the configuration should not be changed. Otherwise, a glitch occurs.
934 * @retval kStatus_Success External reference clock set successfully.
935 */
936 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
937
938 /*!
939 * @brief Set the FLL external reference clock divider value.
940 *
941 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
942 *
943 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
944 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)945 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
946 {
947 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
948 }
949
950 /*!
951 * @brief Enables the PLL0 in FLL mode.
952 *
953 * This function sets us the PLL0 in FLL mode and reconfigures
954 * the PLL0. Ensure that the PLL reference
955 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
956 * The function CLOCK_CalcPllDiv gets the correct PLL
957 * divider values.
958 *
959 * @param config Pointer to the configuration structure.
960 */
961 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
962
963 /*!
964 * @brief Disables the PLL0 in FLL mode.
965 *
966 * This function disables the PLL0 in FLL mode. It should be used together with the
967 * @ref CLOCK_EnablePll0.
968 */
CLOCK_DisablePll0(void)969 static inline void CLOCK_DisablePll0(void)
970 {
971 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
972 }
973
974 /*@}*/
975
976 /*! @name MCG clock lock monitor functions. */
977 /*@{*/
978
979 /*!
980 * @brief Sets the OSC0 clock monitor mode.
981 *
982 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
983 *
984 * @param mode Monitor mode to set.
985 */
986 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
987
988 /*!
989 * @brief Sets the RTC OSC clock monitor mode.
990 *
991 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
992 *
993 * @param mode Monitor mode to set.
994 */
995 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
996
997 /*!
998 * @brief Sets the PLL0 clock monitor mode.
999 *
1000 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1001 *
1002 * @param mode Monitor mode to set.
1003 */
1004 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1005
1006 /*!
1007 * @brief Gets the MCG status flags.
1008 *
1009 * This function gets the MCG clock status flags. All status flags are
1010 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
1011 * check a specific flag, compare the return value with the flag.
1012 *
1013 * Example:
1014 * @code
1015 * To check the clock lost lock status of OSC0 and PLL0.
1016 * uint32_t mcgFlags;
1017 *
1018 * mcgFlags = CLOCK_GetStatusFlags();
1019 *
1020 * if (mcgFlags & kMCG_Osc0LostFlag)
1021 * {
1022 * OSC0 clock lock lost. Do something.
1023 * }
1024 * if (mcgFlags & kMCG_Pll0LostFlag)
1025 * {
1026 * PLL0 clock lock lost. Do something.
1027 * }
1028 * @endcode
1029 *
1030 * @return Logical OR value of the @ref _mcg_status_flags_t.
1031 */
1032 uint32_t CLOCK_GetStatusFlags(void);
1033
1034 /*!
1035 * @brief Clears the MCG status flags.
1036 *
1037 * This function clears the MCG clock lock lost status. The parameter is a logical
1038 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
1039 *
1040 * Example:
1041 * @code
1042 * To clear the clock lost lock status flags of OSC0 and PLL0.
1043 *
1044 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1045 * @endcode
1046 *
1047 * @param mask The status flags to clear. This is a logical OR of members of the
1048 * enumeration @ref _mcg_status_flags_t.
1049 */
1050 void CLOCK_ClearStatusFlags(uint32_t mask);
1051
1052 /*@}*/
1053
1054 /*!
1055 * @name OSC configuration
1056 * @{
1057 */
1058
1059 /*!
1060 * @brief Configures the OSC external reference clock (OSCERCLK).
1061 *
1062 * This function configures the OSC external reference clock (OSCERCLK).
1063 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1064 * the output divider to 1:
1065 *
1066 @code
1067 oscer_config_t config =
1068 {
1069 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1070 .erclkDiv = 1U,
1071 };
1072
1073 OSC_SetExtRefClkConfig(OSC, &config);
1074 @endcode
1075 *
1076 * @param base OSC peripheral address.
1077 * @param config Pointer to the configuration structure.
1078 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1079 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1080 {
1081 uint8_t reg = base->CR;
1082
1083 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
1084 reg |= config->enableMode;
1085
1086 base->CR = reg;
1087 }
1088
1089 /*!
1090 * @brief Sets the capacitor load configuration for the oscillator.
1091 *
1092 * This function sets the specified capacitors configuration for the oscillator.
1093 * This should be done in the early system level initialization function call
1094 * based on the system configuration.
1095 *
1096 * @param base OSC peripheral address.
1097 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1098 *
1099 * Example:
1100 @code
1101 To enable only 2 pF and 8 pF capacitor load, please use like this.
1102 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1103 @endcode
1104 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1105 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1106 {
1107 uint8_t reg = base->CR;
1108
1109 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
1110 reg |= capLoad;
1111
1112 base->CR = reg;
1113 }
1114
1115 /*!
1116 * @brief Initializes the OSC0.
1117 *
1118 * This function initializes the OSC0 according to the board configuration.
1119 *
1120 * @param config Pointer to the OSC0 configuration structure.
1121 */
1122 void CLOCK_InitOsc0(osc_config_t const *config);
1123
1124 /*!
1125 * @brief Deinitializes the OSC0.
1126 *
1127 * This function deinitializes the OSC0.
1128 */
1129 void CLOCK_DeinitOsc0(void);
1130
1131 /* @} */
1132
1133 /*!
1134 * @name External clock frequency
1135 * @{
1136 */
1137
1138 /*!
1139 * @brief Sets the XTAL0 frequency based on board settings.
1140 *
1141 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1142 */
CLOCK_SetXtal0Freq(uint32_t freq)1143 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1144 {
1145 g_xtal0Freq = freq;
1146 }
1147
1148 /*!
1149 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1150 *
1151 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1152 */
CLOCK_SetXtal32Freq(uint32_t freq)1153 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1154 {
1155 g_xtal32Freq = freq;
1156 }
1157 /* @} */
1158
1159 /*!
1160 * @name IRCs frequency
1161 * @{
1162 */
1163
1164 /*!
1165 * @brief Set the Slow IRC frequency based on the trimmed value
1166 *
1167 * @param freq The Slow IRC frequency input clock frequency in Hz.
1168 */
1169 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1170
1171 /*!
1172 * @brief Set the Fast IRC frequency based on the trimmed value
1173 *
1174 * @param freq The Fast IRC frequency input clock frequency in Hz.
1175 */
1176 void CLOCK_SetFastIrcFreq(uint32_t freq);
1177 /* @} */
1178
1179 /*!
1180 * @name MCG auto-trim machine.
1181 * @{
1182 */
1183
1184 /*!
1185 * @brief Auto trims the internal reference clock.
1186 *
1187 * This function trims the internal reference clock by using the external clock. If
1188 * successful, it returns the kStatus_Success and the frequency after
1189 * trimming is received in the parameter @p actualFreq. If an error occurs,
1190 * the error code is returned.
1191 *
1192 * @param extFreq External clock frequency, which should be a bus clock.
1193 * @param desireFreq Frequency to trim to.
1194 * @param actualFreq Actual frequency after trimming.
1195 * @param atms Trim fast or slow internal reference clock.
1196 * @retval kStatus_Success ATM success.
1197 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1198 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1199 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1200 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1201 */
1202 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1203 /* @} */
1204
1205 /*! @name MCG mode functions. */
1206 /*@{*/
1207
1208 /*!
1209 * @brief Gets the current MCG mode.
1210 *
1211 * This function checks the MCG registers and determines the current MCG mode.
1212 *
1213 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1214 */
1215 mcg_mode_t CLOCK_GetMode(void);
1216
1217 /*!
1218 * @brief Sets the MCG to FEI mode.
1219 *
1220 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1221 * from the current mode, this function returns an error.
1222 *
1223 * @param dmx32 DMX32 in FEI mode.
1224 * @param drs The DCO range selection.
1225 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1226 * NULL does not cause a delay.
1227 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1228 * @retval kStatus_Success Switched to the target mode successfully.
1229 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1230 * to a frequency above 32768 Hz.
1231 */
1232 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1233
1234 /*!
1235 * @brief Sets the MCG to FEE mode.
1236 *
1237 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1238 * from the current mode, this function returns an error.
1239 *
1240 * @param frdiv FLL reference clock divider setting, FRDIV.
1241 * @param dmx32 DMX32 in FEE mode.
1242 * @param drs The DCO range selection.
1243 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1244 * NULL does not cause a delay.
1245 *
1246 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1247 * @retval kStatus_Success Switched to the target mode successfully.
1248 */
1249 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1250
1251 /*!
1252 * @brief Sets the MCG to FBI mode.
1253 *
1254 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1255 * from the current mode, this function returns an error.
1256 *
1257 * @param dmx32 DMX32 in FBI mode.
1258 * @param drs The DCO range selection.
1259 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1260 * is not used in FBI mode, this parameter can be NULL. Passing
1261 * NULL does not cause a delay.
1262 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1263 * @retval kStatus_Success Switched to the target mode successfully.
1264 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1265 * to frequency above 32768 Hz.
1266 */
1267 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1268
1269 /*!
1270 * @brief Sets the MCG to FBE mode.
1271 *
1272 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1273 * from the current mode, this function returns an error.
1274 *
1275 * @param frdiv FLL reference clock divider setting, FRDIV.
1276 * @param dmx32 DMX32 in FBE mode.
1277 * @param drs The DCO range selection.
1278 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1279 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1280 * does not cause a delay.
1281 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1282 * @retval kStatus_Success Switched to the target mode successfully.
1283 */
1284 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1285
1286 /*!
1287 * @brief Sets the MCG to BLPI mode.
1288 *
1289 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1290 * from the current mode, this function returns an error.
1291 *
1292 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1293 * @retval kStatus_Success Switched to the target mode successfully.
1294 */
1295 status_t CLOCK_SetBlpiMode(void);
1296
1297 /*!
1298 * @brief Sets the MCG to BLPE mode.
1299 *
1300 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1301 * from the current mode, this function returns an error.
1302 *
1303 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1304 * @retval kStatus_Success Switched to the target mode successfully.
1305 */
1306 status_t CLOCK_SetBlpeMode(void);
1307
1308 /*!
1309 * @brief Sets the MCG to PBE mode.
1310 *
1311 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1312 * from the current mode, this function returns an error.
1313 *
1314 * @param pllcs The PLL selection, PLLCS.
1315 * @param config Pointer to the PLL configuration.
1316 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1317 * @retval kStatus_Success Switched to the target mode successfully.
1318 *
1319 * @note
1320 * 1. The parameter \c pllcs selects the PLL. For platforms with
1321 * only one PLL, the parameter pllcs is kept for interface compatibility.
1322 * 2. The parameter \c config is the PLL configuration structure. On some
1323 * platforms, it is possible to choose the external PLL directly, which renders the
1324 * configuration structure not necessary. In this case, pass in NULL.
1325 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1326 */
1327 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1328
1329 /*!
1330 * @brief Sets the MCG to PEE mode.
1331 *
1332 * This function sets the MCG to PEE mode.
1333 *
1334 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1335 * @retval kStatus_Success Switched to the target mode successfully.
1336 *
1337 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1338 * PRDIV/VDIV are different than in the PBE mode, set them up
1339 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1340 */
1341 status_t CLOCK_SetPeeMode(void);
1342
1343 /*!
1344 * @brief Sets the MCG to PBI mode.
1345 *
1346 * This function sets the MCG to PBI mode.
1347 *
1348 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1349 * @retval kStatus_Success Switched to the target mode successfully.
1350 */
1351 status_t CLOCK_SetPbiMode(void);
1352
1353 /*!
1354 * @brief Sets the MCG to PEI mode.
1355 *
1356 * This function sets the MCG to PEI mode.
1357 *
1358 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1359 * @retval kStatus_Success Switched to the target mode successfully.
1360 */
1361 status_t CLOCK_SetPeiMode(void);
1362
1363 /*!
1364 * @brief Switches the MCG to FBE mode from the external mode.
1365 *
1366 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1367 * The external clock is used as the system clock source and PLL is disabled. However,
1368 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1369 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1370 *
1371 * @code
1372 * CLOCK_ExternalModeToFbeModeQuick();
1373 * CLOCK_SetFeiMode(...);
1374 * @endcode
1375 *
1376 * @retval kStatus_Success Switched successfully.
1377 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1378 */
1379 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1380
1381 /*!
1382 * @brief Switches the MCG to FBI mode from internal modes.
1383 *
1384 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1385 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1386 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1387 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1388 *
1389 * @code
1390 * CLOCK_InternalModeToFbiModeQuick();
1391 * CLOCK_SetFeeMode(...);
1392 * @endcode
1393 *
1394 * @retval kStatus_Success Switched successfully.
1395 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1396 */
1397 status_t CLOCK_InternalModeToFbiModeQuick(void);
1398
1399 /*!
1400 * @brief Sets the MCG to FEI mode during system boot up.
1401 *
1402 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1403 * set up MCG during system boot up.
1404 *
1405 * @param dmx32 DMX32 in FEI mode.
1406 * @param drs The DCO range selection.
1407 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1408 *
1409 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1410 * @retval kStatus_Success Switched to the target mode successfully.
1411 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1412 * to frequency above 32768 Hz.
1413 */
1414 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1415
1416 /*!
1417 * @brief Sets the MCG to FEE mode during system bootup.
1418 *
1419 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1420 * set up the MCG during system boot up.
1421 *
1422 * @param oscsel OSC clock select, OSCSEL.
1423 * @param frdiv FLL reference clock divider setting, FRDIV.
1424 * @param dmx32 DMX32 in FEE mode.
1425 * @param drs The DCO range selection.
1426 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1427 *
1428 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1429 * @retval kStatus_Success Switched to the target mode successfully.
1430 */
1431 status_t CLOCK_BootToFeeMode(
1432 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1433
1434 /*!
1435 * @brief Sets the MCG to BLPI mode during system boot up.
1436 *
1437 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1438 * set up the MCG during system boot up.
1439 *
1440 * @param fcrdiv Fast IRC divider, FCRDIV.
1441 * @param ircs The internal reference clock to select, IRCS.
1442 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1443 *
1444 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1445 * @retval kStatus_Success Switched to the target mode successfully.
1446 */
1447 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1448
1449 /*!
1450 * @brief Sets the MCG to BLPE mode during system boot up.
1451 *
1452 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1453 * set up the MCG during system boot up.
1454 *
1455 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1456 *
1457 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1458 * @retval kStatus_Success Switched to the target mode successfully.
1459 */
1460 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1461
1462 /*!
1463 * @brief Sets the MCG to PEE mode during system boot up.
1464 *
1465 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1466 * set up the MCG during system boot up.
1467 *
1468 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1469 * @param pllcs The PLL selection, PLLCS.
1470 * @param config Pointer to the PLL configuration.
1471 *
1472 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1473 * @retval kStatus_Success Switched to the target mode successfully.
1474 */
1475 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1476
1477 /*!
1478 * @brief Sets the MCG to PEI mode during system boot up.
1479 *
1480 * This function sets the MCG to PEI mode from the reset mode. It can be used to
1481 * set up the MCG during system boot up.
1482 *
1483 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1484 * @retval kStatus_Success Switched to the target mode successfully.
1485 */
1486 status_t CLOCK_BootToPeiMode(void);
1487
1488 /*!
1489 * @brief Sets the MCG to a target mode.
1490 *
1491 * This function sets MCG to a target mode defined by the configuration
1492 * structure. If switching to the target mode fails, this function
1493 * chooses the correct path.
1494 *
1495 * @param config Pointer to the target MCG mode configuration structure.
1496 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1497 *
1498 * @note If the external clock is used in the target mode, ensure that it is
1499 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1500 * function.
1501 */
1502 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1503
1504 /*@}*/
1505
1506 #if defined(__cplusplus)
1507 }
1508 #endif /* __cplusplus */
1509
1510 /*! @} */
1511
1512 #endif /* _FSL_CLOCK_H_ */
1513
