1 /*
2 * Copyright 2019 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11 /*
12 * How to setup clock using clock driver functions:
13 *
14 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
15 * and flash clock are in allowed range during clock mode switch.
16 *
17 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
18 *
19 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
20 * internal reference clock(MCGIRCLK). Follow the steps to setup:
21 *
22 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
23 *
24 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
25 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
26 * explicitly to setup MCGIRCLK.
27 *
28 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
29 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
30 * if the target mode is not FLL mode, the FLL is disabled.
31 *
32 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
33 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
34 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
35 *
36 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
37 */
38
39 /* clang-format off */
40 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
41 !!GlobalInfo
42 product: Clocks v7.0
43 processor: MKM35Z512xxx7
44 package_id: MKM35Z512VLQ7
45 mcu_data: ksdk2_0
46 processor_version: 0.0.1
47 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
48 /* clang-format on */
49
50 #include "fsl_smc.h"
51 #include "fsl_irtc.h"
52 #include "clock_config.h"
53
54 /*******************************************************************************
55 * Definitions
56 ******************************************************************************/
57 #define IRTC_OSC_CAP0P 0U /*!< RTC oscillator 0pF capacitor load */
58 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
59 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
60 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
61 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
62 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
63
64 /*******************************************************************************
65 * Variables
66 ******************************************************************************/
67 /* System clock frequency. */
68 extern uint32_t SystemCoreClock;
69
70 /*******************************************************************************
71 * Code
72 ******************************************************************************/
73 /*FUNCTION**********************************************************************
74 *
75 * Function Name : CLOCK_CONFIG_FllStableDelay
76 * Description : This function is used to delay for FLL stable.
77 *
78 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)79 static void CLOCK_CONFIG_FllStableDelay(void)
80 {
81 uint32_t i = 30000U;
82 while (i--)
83 {
84 __NOP();
85 }
86 }
87
88 /*FUNCTION**********************************************************************
89 *
90 * Function Name : CLOCK_CONFIG_EnableRtcOsc
91 * Description : This function is used to configuring RTC oscillator
92 * Param capLoad : RTC oscillator capacity load
93 *
94 *END**************************************************************************/
CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)95 static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)
96 {
97 if ((RTC->GP_DATA_REG & 0x01U) != 0U)
98 { /* Only if the Rtc oscillator is not already enabled */
99 /* Set the specified capacitor configuration for the RTC oscillator */
100 IRTC_SetOscCapLoad(RTC, capLoad);
101 /* Enable the RTC 32KHz oscillator */
102 RTC->GP_DATA_REG &= ~0x01U;
103 }
104 }
105
106 /*******************************************************************************
107 ************************ BOARD_InitBootClocks function ************************
108 ******************************************************************************/
BOARD_InitBootClocks(void)109 void BOARD_InitBootClocks(void)
110 {
111 BOARD_BootClockRUN();
112 }
113
114 /*******************************************************************************
115 ********************** Configuration BOARD_BootClockRUN ***********************
116 ******************************************************************************/
117 /* clang-format off */
118 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
119 !!Configuration
120 name: BOARD_BootClockRUN
121 called_from_default_init: true
122 outputs:
123 - {id: Bus_clock.outFreq, value: 71.991296/3 MHz}
124 - {id: Core_clock.outFreq, value: 71.991296 MHz}
125 - {id: Flash_clock.outFreq, value: 71.991296/3 MHz}
126 - {id: LPO_clock.outFreq, value: 1 kHz}
127 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
128 - {id: OSC32KSELCLK.outFreq, value: 32.768 kHz}
129 - {id: OSCERCLK.outFreq, value: 8 MHz}
130 - {id: PLLFLLCLK.outFreq, value: 71.991296 MHz}
131 - {id: System_clock.outFreq, value: 71.991296 MHz}
132 settings:
133 - {id: MCGMode, value: FEE}
134 - {id: MCG.CLKS.sel, value: MCG.PLLS}
135 - {id: MCG.FCRDIV.scale, value: '1', locked: true}
136 - {id: MCG.FLL_mul.scale, value: '2197', locked: true}
137 - {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK}
138 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
139 - {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK}
140 - {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV}
141 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
142 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
143 - {id: MCG_C2_RANGE0_CFG, value: High}
144 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
145 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
146 - {id: RTC_CR_OSCE_CFG, value: Enabled}
147 - {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk}
148 - {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK}
149 - {id: SIM.CLKDIVBUS.scale, value: '3', locked: true}
150 - {id: SIM.CLKDIVSYS.scale, value: '1', locked: true}
151 - {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK}
152 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
153 - {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK}
154 - {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK}
155 - {id: XBARCLKOUTConfig, value: 'no'}
156 sources:
157 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
158 - {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true}
159 - {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz}
160 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
161 /* clang-format on */
162
163 /*******************************************************************************
164 * Variables for BOARD_BootClockRUN configuration
165 ******************************************************************************/
166 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
167 .mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
168 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
169 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
170 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
171 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
172 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
173 .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
174 .oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */
175 .pll0Config =
176 {
177 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
178 .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
179 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
180 },
181 };
182 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
183 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
184 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
185 .clkdiv1 = 0x2000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */
186 };
187 const osc_config_t oscConfig_BOARD_BootClockRUN = {
188 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
189 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
190 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
191 .oscerConfig = {
192 .enableMode =
193 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
194 }};
195
196 /*******************************************************************************
197 * Code for BOARD_BootClockRUN configuration
198 ******************************************************************************/
BOARD_BootClockRUN(void)199 void BOARD_BootClockRUN(void)
200 {
201 /* Use RTC_CLKIN input clock directly. */
202 CLOCK_SetXtal32Freq(32768U);
203 /* Set the system clock dividers in SIM to safe value. */
204 CLOCK_SetSimSafeDivs();
205 /* Enable RTC oscillator. */
206 CLOCK_CONFIG_EnableRtcOsc((IRTC_OSC_CAP0P));
207 /* Initializes OSC0 according to board configuration. */
208 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
209 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
210 /* Set MCG to FEE mode. */
211 CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, mcgConfig_BOARD_BootClockRUN.frdiv,
212 mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
213 CLOCK_CONFIG_FllStableDelay);
214 /* Configure the Internal Reference clock (MCGIRCLK). */
215 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
216 mcgConfig_BOARD_BootClockRUN.fcrdiv);
217 /* Set the clock configuration in SIM module. */
218 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
219 /* Set SystemCoreClock variable. */
220 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
221 }
222
223 /*******************************************************************************
224 ********************* Configuration BOARD_BootClockVLPR ***********************
225 ******************************************************************************/
226 /* clang-format off */
227 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
228 !!Configuration
229 name: BOARD_BootClockVLPR
230 outputs:
231 - {id: Bus_clock.outFreq, value: 1 MHz}
232 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
233 - {id: Flash_clock.outFreq, value: 1 MHz}
234 - {id: LPO_clock.outFreq, value: 1 kHz}
235 - {id: MCGIRCLK.outFreq, value: 4 MHz}
236 - {id: System_clock.outFreq, value: 4 MHz}
237 settings:
238 - {id: powerMode, value: VLPR}
239 - {id: MCG.FCRDIV.scale, value: '1'}
240 - {id: MCG.FRDIV.scale, value: '32'}
241 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
242 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
243 - {id: MCG_C2_RANGE0_CFG, value: High}
244 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
245 - {id: RTC_CR_OSCE_CFG, value: Enabled}
246 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
247 - {id: SIM.CLKDIVBUS.scale, value: '4'}
248 sources:
249 - {id: OSC.OSC.outFreq, value: 8 MHz}
250 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
251 /* clang-format on */
252
253 /*******************************************************************************
254 * Variables for BOARD_BootClockVLPR configuration
255 ******************************************************************************/
256 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
257 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
258 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
259 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
260 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
261 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
262 .drs = kMCG_DrsLow, /* Low frequency range */
263 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
264 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
265 .pll0Config =
266 {
267 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
268 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
269 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
270 },
271 };
272 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
273 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
274 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
275 .clkdiv1 = 0x3000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /4, FLASHCLKMODE: /1 */
276 };
277 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
278 .freq = 0U, /* Oscillator frequency: 0Hz */
279 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
280 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
281 .oscerConfig = {
282 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
283 }};
284
285 /*******************************************************************************
286 * Code for BOARD_BootClockVLPR configuration
287 ******************************************************************************/
BOARD_BootClockVLPR(void)288 void BOARD_BootClockVLPR(void)
289 {
290 /* Set the system clock dividers in SIM to safe value. */
291 CLOCK_SetSimSafeDivs();
292 /* Set MCG to BLPI mode. */
293 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
294 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
295 /* Set the clock configuration in SIM module. */
296 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
297 /* Set VLPR power mode. */
298 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
299 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
300 SMC_SetPowerModeVlpr(SMC, false);
301 #else
302 SMC_SetPowerModeVlpr(SMC);
303 #endif
304 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
305 {
306 }
307 /* Set SystemCoreClock variable. */
308 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
309 }
310
