1 /*
2 * Copyright 2018 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
16 * and flash clock are in allowed range during clock mode switch.
17 *
18 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
19 *
20 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
21 * internal reference clock(MCGIRCLK). Follow the steps to setup:
22 *
23 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
24 *
25 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
26 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
27 * explicitly to setup MCGIRCLK.
28 *
29 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
30 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
31 * if the target mode is not FLL mode, the FLL is disabled.
32 *
33 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
34 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
35 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
36 *
37 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
38 */
39
40 /* clang-format off */
41 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
42 !!GlobalInfo
43 product: Clocks v4.1
44 processor: MKM34Z256xxx7
45 package_id: MKM34Z256VLQ7
46 mcu_data: ksdk2_0
47 processor_version: 4.0.0
48 board: TWR-KM34Z75M
49 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
50 /* clang-format on */
51
52 #include "fsl_irtc.h"
53 #include "clock_config.h"
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58 #define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
59 #define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
60 #define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
61 #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
62 #define SIM_ADC_TRG_CLK_SEL_ADC_ASYNC_CLK 1U /*!< ADC trigger clock select: ADC asynchronous clock */
63 #define SIM_AFE_CLK_SEL_MCGFLLCLK_CLK 1U /*!< AFE clock select: MCGFLLCLK clock */
64 #define SIM_CLKOUT_SEL_LPO_CLK 3U /*!< CLKOUT pin clock select: LPO clock */
65 #define SIM_LPUART_CLK_SEL_OSCERCLK_CLK 2U /*!< LPUART clock select: OSCERCLK clock */
66 #define SIM_OSC32KSEL_MCGIRCLK_CLK 2U /*!< OSC32KSEL select: MCGIRCLK clock */
67 #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
68 #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
69 #define SIM_RTC_CLK_SEL_MCGIRCLK_CLK 1U /*!< RTC clock select: MCGIRCLK clock */
70 #define SIM_XBAR_CLKOUT_SEL_LPO_CLK 3U /*!< XBAR clock out select: LPO clock */
71
72 /*******************************************************************************
73 * Variables
74 ******************************************************************************/
75 /* System clock frequency. */
76 extern uint32_t SystemCoreClock;
77
78 /*******************************************************************************
79 * Code
80 ******************************************************************************/
81 /*FUNCTION**********************************************************************
82 *
83 * Function Name : CLOCK_CONFIG_FllStableDelay
84 * Description : This function is used to delay for FLL stable.
85 *
86 *END**************************************************************************/
CLOCK_CONFIG_FllStableDelay(void)87 static void CLOCK_CONFIG_FllStableDelay(void)
88 {
89 uint32_t i = 30000U;
90 while (i--)
91 {
92 __NOP();
93 }
94 }
95
96 /*FUNCTION**********************************************************************
97 *
98 * Function Name : CLOCK_CONFIG_EnableRtcOsc
99 * Description : This function is used to configuring RTC oscillator
100 * Param capLoad : RTC oscillator capacity load
101 *
102 *END**************************************************************************/
CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)103 static void CLOCK_CONFIG_EnableRtcOsc(uint32_t capLoad)
104 {
105 if ((RTC->GP_DATA_REG & 0x01U) != 0U)
106 { /* Only if the Rtc oscillator is not already enabled */
107 /* Set the specified capacitor configuration for the RTC oscillator */
108 IRTC_SetOscCapLoad(RTC, capLoad);
109 /* Enable the RTC 32KHz oscillator */
110 RTC->GP_DATA_REG &= ~0x01U;
111 }
112 }
113
114 /*FUNCTION**********************************************************************
115 *
116 * Function Name : CLOCK_CONFIG_SetRtcClockSrc
117 * Description : Set RTC clock source.
118 * Param src : The value to set RTC clock source.
119 *
120 *END**************************************************************************/
CLOCK_CONFIG_SetRtcClockSrc(uint8_t src)121 static void CLOCK_CONFIG_SetRtcClockSrc(uint8_t src)
122 {
123 SIM->MISC_CTL = ((SIM->MISC_CTL & ~SIM_MISC_CTL_RTCCLKSEL_MASK) | SIM_MISC_CTL_RTCCLKSEL(src));
124 }
125
126 /*******************************************************************************
127 ************************ BOARD_InitBootClocks function ************************
128 ******************************************************************************/
BOARD_InitBootClocks(void)129 void BOARD_InitBootClocks(void)
130 {
131 BOARD_BootClockRUN();
132 }
133
134 /*******************************************************************************
135 ********************** Configuration BOARD_BootClockRUN ***********************
136 ******************************************************************************/
137 /* clang-format off */
138 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
139 !!Configuration
140 name: BOARD_BootClockRUN
141 called_from_default_init: true
142 outputs:
143 - {id: AFECLK.outFreq, value: 71.991296 MHz}
144 - {id: Bus_clock.outFreq, value: 71.991296/3 MHz}
145 - {id: CLKOUT.outFreq, value: 1 kHz}
146 - {id: Core_clock.outFreq, value: 71.991296 MHz}
147 - {id: Flash_clock.outFreq, value: 71.991296/3 MHz}
148 - {id: LPO_clock.outFreq, value: 1 kHz}
149 - {id: LPUARTCLK.outFreq, value: 8 MHz}
150 - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
151 - {id: OSC32KSELCLK.outFreq, value: 32.768 kHz}
152 - {id: OSCERCLK.outFreq, value: 8 MHz}
153 - {id: PLLFLLCLK.outFreq, value: 71.991296 MHz}
154 - {id: RTCCLK.outFreq, value: 32.768 kHz}
155 - {id: System_clock.outFreq, value: 71.991296 MHz}
156 - {id: XBARCLKOUT.outFreq, value: 1 kHz}
157 settings:
158 - {id: MCGMode, value: FEE}
159 - {id: ADCTRGClkConfig, value: 'yes'}
160 - {id: AFEClkConfig, value: 'yes'}
161 - {id: CLKOUTConfig, value: 'yes'}
162 - {id: LPUARTClkConfig, value: 'yes'}
163 - {id: MCG.CLKS.sel, value: MCG.PLLS}
164 - {id: MCG.FLL_mul.scale, value: '2197', locked: true}
165 - {id: MCG.IRCS.sel, value: MCG.SLOW_IRCLK}
166 - {id: MCG.IREFS.sel, value: MCG.FRDIV}
167 - {id: MCG.OSCSEL.sel, value: SIM.RTC32KCLK}
168 - {id: MCG.PLL32KREFSEL.sel, value: MCG.FRDIV}
169 - {id: 'MCG::C2[LP].bitField', value: BitFieldValue}
170 - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
171 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
172 - {id: MCG_C2_RANGE0_CFG, value: High}
173 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
174 - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
175 - {id: RTCClkConfig, value: 'yes'}
176 - {id: RTC_CR_OSCE_CFG, value: Enabled}
177 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
178 - {id: SIM.ADCTRGSEL.sel, value: SIM.ADC_asynchronous_clk}
179 - {id: SIM.AFECLKSEL.sel, value: MCG.MCGFLLCLK}
180 - {id: SIM.CLKDIVBUS.scale, value: '3', locked: true}
181 - {id: SIM.CLKDIVSYS.scale, value: '1', locked: true}
182 - {id: SIM.CLKOUTSEL.sel, value: PMC.LPOCLK}
183 - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
184 - {id: SIM.OSC32KSEL.sel, value: MCG.MCGIRCLK}
185 - {id: SIM.RTCCLKSEL.sel, value: MCG.MCGIRCLK}
186 - {id: SIM.XBARCLKOUTSEL.sel, value: PMC.LPOCLK}
187 sources:
188 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
189 - {id: RTC.OSC32kHz.outFreq, value: 32.768 kHz, enabled: true}
190 - {id: SIM.ADC_asynchronous_clk.outFreq, value: 1.255 MHz}
191 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
192 /* clang-format on */
193
194 /*******************************************************************************
195 * Variables for BOARD_BootClockRUN configuration
196 ******************************************************************************/
197 const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
198 .mcgMode = kMCG_ModeFEE, /* FEE - FLL Engaged External */
199 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
200 .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
201 .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
202 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
203 .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */
204 .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
205 .oscsel = kMCG_OscselRtc, /* Selects 32 kHz RTC Oscillator */
206 .pll0Config =
207 {
208 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
209 .refSrc = kMCG_PllRefFllRef, /* Selects FLL reference clock, the clock after FRDIV */
210 .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
211 },
212 };
213 const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
214 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
215 .er32kSrc = SIM_OSC32KSEL_MCGIRCLK_CLK, /* OSC32KSEL select: MCGIRCLK clock */
216 .clkdiv1 = 0x2000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /3, FLASHCLKMODE: /1 */
217 };
218 const osc_config_t oscConfig_BOARD_BootClockRUN = {
219 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
220 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
221 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
222 .oscerConfig = {
223 .enableMode =
224 kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
225 }};
226
227 /*******************************************************************************
228 * Code for BOARD_BootClockRUN configuration
229 ******************************************************************************/
BOARD_BootClockRUN(void)230 void BOARD_BootClockRUN(void)
231 {
232 /* Use RTC_CLKIN input clock directly. */
233 CLOCK_SetXtal32Freq(32768U);
234 /* Set the system clock dividers in SIM to safe value. */
235 CLOCK_SetSimSafeDivs();
236 /* Enable RTC oscillator. */
237 CLOCK_CONFIG_EnableRtcOsc((kIRTC_Capacitor2p | kIRTC_Capacitor16p));
238 /* Initializes OSC0 according to board configuration. */
239 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
240 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
241 /* Set MCG to FEE mode. */
242 CLOCK_BootToFeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, mcgConfig_BOARD_BootClockRUN.frdiv,
243 mcgConfig_BOARD_BootClockRUN.dmx32, mcgConfig_BOARD_BootClockRUN.drs,
244 CLOCK_CONFIG_FllStableDelay);
245 /* Configure the Internal Reference clock (MCGIRCLK). */
246 CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
247 mcgConfig_BOARD_BootClockRUN.fcrdiv);
248 /* Set the clock configuration in SIM module. */
249 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
250 /* Set SystemCoreClock variable. */
251 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
252 /* Set AFE clock source. */
253 CLOCK_SetAfeClkSrc(SIM_AFE_CLK_SEL_MCGFLLCLK_CLK);
254 /* Set RTC clock source. */
255 CLOCK_CONFIG_SetRtcClockSrc(SIM_RTC_CLK_SEL_MCGIRCLK_CLK);
256 /* Set XBAR clock out source. */
257 CLOCK_SetXbarClock(SIM_XBAR_CLKOUT_SEL_LPO_CLK);
258 /* Set ADC trigger clock source. */
259 CLOCK_SetAdcTriggerClock(SIM_ADC_TRG_CLK_SEL_ADC_ASYNC_CLK);
260 /* Set LPUART clock source. */
261 CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_OSCERCLK_CLK);
262 /* Set CLKOUT source. */
263 CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_LPO_CLK);
264 }
265
266 /*******************************************************************************
267 ********************* Configuration BOARD_BootClockVLPR ***********************
268 ******************************************************************************/
269 /* clang-format off */
270 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
271 !!Configuration
272 name: BOARD_BootClockVLPR
273 outputs:
274 - {id: Bus_clock.outFreq, value: 2 MHz}
275 - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
276 - {id: Flash_clock.outFreq, value: 2 MHz}
277 - {id: LPO_clock.outFreq, value: 1 kHz}
278 - {id: System_clock.outFreq, value: 4 MHz}
279 settings:
280 - {id: MCG.FCRDIV.scale, value: '1'}
281 - {id: MCG.FRDIV.scale, value: '32'}
282 - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
283 - {id: MCG_C2_RANGE0_CFG, value: High}
284 - {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
285 - {id: RTC_CR_OSCE_CFG, value: Enabled}
286 - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC18PF}
287 sources:
288 - {id: OSC.OSC.outFreq, value: 8 MHz}
289 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
290 /* clang-format on */
291
292 /*******************************************************************************
293 * Variables for BOARD_BootClockVLPR configuration
294 ******************************************************************************/
295 const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
296 .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
297 .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
298 .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
299 .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
300 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
301 .drs = kMCG_DrsLow, /* Low frequency range */
302 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
303 .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
304 .pll0Config =
305 {
306 .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
307 .refSrc = kMCG_PllRefRtc, /* Selects 32k RTC oscillator */
308 .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
309 },
310 };
311 const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
312 .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
313 .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
314 .clkdiv1 = 0x1000000U, /* SIM_CLKDIV1 - CLKDIVSYS: /1, CLKDIVBUS: /2, FLASHCLKMODE: /1 */
315 };
316 const osc_config_t oscConfig_BOARD_BootClockVLPR = {
317 .freq = 0U, /* Oscillator frequency: 0Hz */
318 .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
319 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
320 .oscerConfig = {
321 .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
322 }};
323
324 /*******************************************************************************
325 * Code for BOARD_BootClockVLPR configuration
326 ******************************************************************************/
BOARD_BootClockVLPR(void)327 void BOARD_BootClockVLPR(void)
328 {
329 /* Set the system clock dividers in SIM to safe value. */
330 CLOCK_SetSimSafeDivs();
331 /* Set MCG to BLPI mode. */
332 CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
333 mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
334 /* Set the clock configuration in SIM module. */
335 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
336 /* Set SystemCoreClock variable. */
337 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
338 }
339
