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Searched refs:u32Mask (Results 1 – 25 of 80) sorted by relevance

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/hal_nuvoton-latest/m46x/StdDriver/src/
Dusci_spi.c222 void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) in USPI_EnableInt() argument
225 if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) in USPI_EnableInt()
232 if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) in USPI_EnableInt()
239 if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) in USPI_EnableInt()
246 if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) in USPI_EnableInt()
253 if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) in USPI_EnableInt()
260 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) in USPI_EnableInt()
267 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) in USPI_EnableInt()
274 if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) in USPI_EnableInt()
281 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) in USPI_EnableInt()
[all …]
Dbmc.c121 void BMC_EnableInt(uint32_t u32Mask) in BMC_EnableInt() argument
124 if((u32Mask & BMC_FTXD_INT_MASK) == BMC_FTXD_INT_MASK) in BMC_EnableInt()
130 if((u32Mask & BMC_TXUND_INT_MASK) == BMC_TXUND_INT_MASK) in BMC_EnableInt()
147 void BMC_DisableInt(uint32_t u32Mask) in BMC_DisableInt() argument
150 if((u32Mask & BMC_FTXD_INT_MASK) == BMC_FTXD_INT_MASK) in BMC_DisableInt()
156 if((u32Mask & BMC_TXUND_INT_MASK) == BMC_TXUND_INT_MASK) in BMC_DisableInt()
173 uint32_t BMC_GetIntFlag(uint32_t u32Mask) in BMC_GetIntFlag() argument
181 if((u32Mask & BMC_FTXD_INT_MASK) && (u32IntStatus & BMC_INTSTS_FTXDIF_Msk)) in BMC_GetIntFlag()
187 if((u32Mask & BMC_TXUND_INT_MASK) && (u32IntStatus & BMC_INTSTS_TXUNDIF_Msk)) in BMC_GetIntFlag()
204 void BMC_ClearIntFlag(uint32_t u32Mask) in BMC_ClearIntFlag() argument
[all …]
Dqspi.c458 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) in QSPI_EnableInt() argument
461 if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) in QSPI_EnableInt()
467 if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) in QSPI_EnableInt()
473 if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) in QSPI_EnableInt()
479 if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) in QSPI_EnableInt()
485 if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) in QSPI_EnableInt()
491 if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) in QSPI_EnableInt()
497 if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) in QSPI_EnableInt()
503 if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) in QSPI_EnableInt()
509 if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) in QSPI_EnableInt()
[all …]
Dusci_uart.c45 void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_ClearIntFlag() argument
48 if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ in UUART_ClearIntFlag()
53 if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ in UUART_ClearIntFlag()
58 if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ in UUART_ClearIntFlag()
63 if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ in UUART_ClearIntFlag()
68 if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ in UUART_ClearIntFlag()
73 if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ in UUART_ClearIntFlag()
78 if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ in UUART_ClearIntFlag()
105 uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_GetIntFlag() argument
111 u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); in UUART_GetIntFlag()
[all …]
Dspi.c1237 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) in SPI_EnableInt() argument
1240 if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) in SPI_EnableInt()
1246 if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) in SPI_EnableInt()
1252 if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) in SPI_EnableInt()
1258 if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) in SPI_EnableInt()
1264 if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) in SPI_EnableInt()
1270 if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) in SPI_EnableInt()
1276 if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) in SPI_EnableInt()
1282 if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) in SPI_EnableInt()
1288 if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) in SPI_EnableInt()
[all …]
/hal_nuvoton-latest/m2l31x/StdDriver/src/
Dusci_spi.c234 void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) in USPI_EnableInt() argument
237 if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) in USPI_EnableInt()
244 if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) in USPI_EnableInt()
251 if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) in USPI_EnableInt()
258 if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) in USPI_EnableInt()
265 if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) in USPI_EnableInt()
272 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) in USPI_EnableInt()
279 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) in USPI_EnableInt()
286 if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) in USPI_EnableInt()
293 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) in USPI_EnableInt()
[all …]
Dqspi.c369 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) in QSPI_EnableInt() argument
372 if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) in QSPI_EnableInt()
378 if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) in QSPI_EnableInt()
384 if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) in QSPI_EnableInt()
390 if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) in QSPI_EnableInt()
396 if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) in QSPI_EnableInt()
402 if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) in QSPI_EnableInt()
408 if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) in QSPI_EnableInt()
414 if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) in QSPI_EnableInt()
420 if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) in QSPI_EnableInt()
[all …]
Dlpspi.c334 void LPSPI_EnableInt(LPSPI_T *lpspi, uint32_t u32Mask) in LPSPI_EnableInt() argument
337 if((u32Mask & LPSPI_UNIT_INT_MASK) == LPSPI_UNIT_INT_MASK) in LPSPI_EnableInt()
343 if((u32Mask & LPSPI_SSACT_INT_MASK) == LPSPI_SSACT_INT_MASK) in LPSPI_EnableInt()
349 if((u32Mask & LPSPI_SSINACT_INT_MASK) == LPSPI_SSINACT_INT_MASK) in LPSPI_EnableInt()
355 if((u32Mask & LPSPI_SLVUR_INT_MASK) == LPSPI_SLVUR_INT_MASK) in LPSPI_EnableInt()
361 if((u32Mask & LPSPI_SLVBE_INT_MASK) == LPSPI_SLVBE_INT_MASK) in LPSPI_EnableInt()
367 if((u32Mask & LPSPI_TXUF_INT_MASK) == LPSPI_TXUF_INT_MASK) in LPSPI_EnableInt()
373 if((u32Mask & LPSPI_FIFO_TXTH_INT_MASK) == LPSPI_FIFO_TXTH_INT_MASK) in LPSPI_EnableInt()
379 if((u32Mask & LPSPI_FIFO_RXTH_INT_MASK) == LPSPI_FIFO_RXTH_INT_MASK) in LPSPI_EnableInt()
385 if((u32Mask & LPSPI_FIFO_RXOV_INT_MASK) == LPSPI_FIFO_RXOV_INT_MASK) in LPSPI_EnableInt()
[all …]
Dspi.c626 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) in SPI_EnableInt() argument
629 if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) in SPI_EnableInt()
635 if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) in SPI_EnableInt()
641 if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) in SPI_EnableInt()
647 if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) in SPI_EnableInt()
653 if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) in SPI_EnableInt()
659 if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) in SPI_EnableInt()
665 if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) in SPI_EnableInt()
671 if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) in SPI_EnableInt()
677 if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) in SPI_EnableInt()
[all …]
Dusci_uart.c45 void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_ClearIntFlag() argument
48 if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ in UUART_ClearIntFlag()
53 if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ in UUART_ClearIntFlag()
58 if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ in UUART_ClearIntFlag()
63 if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ in UUART_ClearIntFlag()
68 if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ in UUART_ClearIntFlag()
73 if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ in UUART_ClearIntFlag()
78 if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ in UUART_ClearIntFlag()
106 uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_GetIntFlag() argument
112 u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); in UUART_GetIntFlag()
[all …]
/hal_nuvoton-latest/m48x/StdDriver/src/
Dusci_spi.c234 void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) in USPI_EnableInt() argument
237 if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) in USPI_EnableInt()
243 if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) in USPI_EnableInt()
249 if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) in USPI_EnableInt()
256 if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) in USPI_EnableInt()
262 if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) in USPI_EnableInt()
268 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) in USPI_EnableInt()
274 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) in USPI_EnableInt()
280 if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) in USPI_EnableInt()
286 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) in USPI_EnableInt()
[all …]
Dqspi.c463 void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) in QSPI_EnableInt() argument
466 if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) in QSPI_EnableInt()
472 if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) in QSPI_EnableInt()
478 if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) in QSPI_EnableInt()
484 if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) in QSPI_EnableInt()
490 if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) in QSPI_EnableInt()
496 if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) in QSPI_EnableInt()
502 if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) in QSPI_EnableInt()
508 if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) in QSPI_EnableInt()
514 if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) in QSPI_EnableInt()
[all …]
Dspi.c627 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) in SPI_EnableInt() argument
630 if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) in SPI_EnableInt()
636 if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) in SPI_EnableInt()
642 if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) in SPI_EnableInt()
648 if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) in SPI_EnableInt()
654 if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) in SPI_EnableInt()
660 if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) in SPI_EnableInt()
666 if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) in SPI_EnableInt()
672 if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) in SPI_EnableInt()
678 if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) in SPI_EnableInt()
[all …]
Dusci_uart.c45 void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_ClearIntFlag() argument
48 if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ in UUART_ClearIntFlag()
53 if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ in UUART_ClearIntFlag()
58 if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ in UUART_ClearIntFlag()
63 if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ in UUART_ClearIntFlag()
68 if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ in UUART_ClearIntFlag()
73 if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ in UUART_ClearIntFlag()
78 if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ in UUART_ClearIntFlag()
105 uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) in UUART_GetIntFlag() argument
111 u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); in UUART_GetIntFlag()
[all …]
/hal_nuvoton-latest/m2l31x/StdDriver/inc/
Dtk.h149 #define TK_ENABLE_SCAN_KEY(u32Mask) (TK->SCANC |= (u32Mask&0x1FFFF)); \ argument
150 (TK->SCANC1 |= ((u32Mask)>>17))
159 #define TK_DISABLE_SCAN_KEY(u32Mask) (TK->SCANC &= ~(u32Mask&0x1FFFF)); \ argument
160 (TK->SCANC1 &= ~((u32Mask)>>17))
170 #define TK_ENABLE_REF_KEY(u32Mask) (TK->REFC |= (u32Mask&0x1FFFF)); \ argument
171 (TK->REFC1 |= (u32Mask>>17))
182 #define TK_DISABLE_REF_KEY(u32Mask) (TK->REFC &= ~(u32Mask&0x1FFFF)); \ argument
183 (TK->REFC1 &= ~(u32Mask>>17))
307 #define TK_GET_INT_STATUS(u32Mask) ((TK->STA & (u32Mask)) ? 1: 0) argument
326 #define TK_GET_INT_STATUS1(u32Mask) ((TK->STA1 & (u32Mask)) ? 1: 0) argument
[all …]
Dotg.h169 #define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask)) argument
191 #define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) argument
213 #define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) argument
235 #define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) argument
250 #define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) argument
Decap.h130 #define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
143 #define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
173 #define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
186 #define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
388 #define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) argument
403 #define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) argument
449 void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
450 void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
Dlppdma.h142 #define LPPDMA_CLR_TD_FLAG(lppdma,u32Mask) ((uint32_t)(lppdma->TDSTS = (u32Mask))) argument
168 #define LPPDMA_CLR_ABORT_FLAG(lppdma,u32Mask) ((uint32_t)(lppdma->ABTSTS = (u32Mask))) argument
193 #define LPPDMA_CLR_ALIGN_FLAG(lppdma,u32Mask) ((uint32_t)(lppdma->ALIGN = (u32Mask))) argument
296 void LPPDMA_Open(LPPDMA_T * lppdma,uint32_t u32Mask);
303 void LPPDMA_EnableInt(LPPDMA_T * lppdma,uint32_t u32Ch, uint32_t u32Mask);
304 void LPPDMA_DisableInt(LPPDMA_T * lppdma,uint32_t u32Ch, uint32_t u32Mask);
/hal_nuvoton-latest/m46x/StdDriver/inc/
Dotg.h169 #define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask)) argument
191 #define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) argument
213 #define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) argument
235 #define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) argument
252 #define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) argument
Dhsotg.h177 #define HSOTG_ENABLE_INT(u32Mask) (HSOTG->INTEN |= (u32Mask)) argument
199 #define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) argument
221 #define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) argument
243 #define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) argument
260 #define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) argument
Decap.h129 #define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
142 #define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
171 #define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
184 #define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
383 #define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) argument
398 #define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) argument
444 void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
445 void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
/hal_nuvoton-latest/m48x/StdDriver/inc/
Dotg.h169 #define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask)) argument
191 #define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) argument
213 #define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) argument
235 #define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) argument
250 #define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) argument
Dhsotg.h169 #define HSOTG_ENABLE_INT(u32Mask) (HSOTG->INTEN |= (u32Mask)) argument
191 #define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) argument
213 #define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) argument
235 #define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) argument
250 #define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) argument
Decap.h129 #define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
142 #define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
171 #define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) argument
184 #define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) argument
383 #define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) argument
398 #define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) argument
444 void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
445 void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
Dpdma.h196 #define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) argument
222 #define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) argument
247 #define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) argument
363 void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask);
369 void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask);
370 void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask);
373 void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask);
374 void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask);

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