Searched refs:_UINT32_ (Results 1 – 25 of 133) sorted by relevance
123456
92 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */93 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */94 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */95 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */96 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */97 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */98 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */99 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */100 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */101 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */[all …]
126 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */127 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */128 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */129 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */130 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */131 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */132 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */133 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */134 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */135 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */[all …]
78 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */79 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */80 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */81 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */82 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */83 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */84 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */85 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */86 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */87 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */[all …]
108 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */109 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */110 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */111 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */112 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */113 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */114 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */115 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */116 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */117 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */[all …]
113 #define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */114 #define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */115 #define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */116 #define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */117 #define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */118 #define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */119 #define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */120 #define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */121 #define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */122 #define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */[all …]
126 #define PORT_PA00 (_UINT32_(1) << 0) /**< PORT mask for PA00 */127 #define PORT_PA01 (_UINT32_(1) << 1) /**< PORT mask for PA01 */128 #define PORT_PA02 (_UINT32_(1) << 2) /**< PORT mask for PA02 */129 #define PORT_PA03 (_UINT32_(1) << 3) /**< PORT mask for PA03 */130 #define PORT_PA04 (_UINT32_(1) << 4) /**< PORT mask for PA04 */131 #define PORT_PA05 (_UINT32_(1) << 5) /**< PORT mask for PA05 */132 #define PORT_PA06 (_UINT32_(1) << 6) /**< PORT mask for PA06 */133 #define PORT_PA07 (_UINT32_(1) << 7) /**< PORT mask for PA07 */134 #define PORT_PA08 (_UINT32_(1) << 8) /**< PORT mask for PA08 */135 #define PORT_PA09 (_UINT32_(1) << 9) /**< PORT mask for PA09 */[all …]
29 #define GMAC_SAB_RESETVALUE _UINT32_(0x00) …31 #define GMAC_SAB_ADDR_Pos _UINT32_(0) …32 #define GMAC_SAB_ADDR_Msk (_UINT32_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) …33 #define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & (_UINT32_(value) << GMAC_SAB_ADD…34 #define GMAC_SAB_Msk _UINT32_(0xFFFFFFFF) …38 #define GMAC_SAT_RESETVALUE _UINT32_(0x00) …40 #define GMAC_SAT_ADDR_Pos _UINT32_(0) …41 #define GMAC_SAT_ADDR_Msk (_UINT32_(0xFFFF) << GMAC_SAT_ADDR_Pos) …42 #define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & (_UINT32_(value) << GMAC_SAT_ADD…43 #define GMAC_SAT_Msk _UINT32_(0x0000FFFF) …[all …]
29 #define CAN_RXBE_0_ID_Pos _UINT32_(0) …30 #define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) …31 #define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_I…32 #define CAN_RXBE_0_RTR_Pos _UINT32_(29) …33 #define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) …34 #define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_…35 #define CAN_RXBE_0_XTD_Pos _UINT32_(30) …36 #define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) …37 #define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_…38 #define CAN_RXBE_0_ESI_Pos _UINT32_(31) …[all …]
29 #define PAC_WRCTRL_RESETVALUE _UINT32_(0x00) …31 #define PAC_WRCTRL_PERID_Pos _UINT32_(0) …32 #define PAC_WRCTRL_PERID_Msk (_UINT32_(0xFFFF) << PAC_WRCTRL_PERID_Pos) …33 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & (_UINT32_(value) << PAC_WRCTR…34 #define PAC_WRCTRL_KEY_Pos _UINT32_(16) …35 #define PAC_WRCTRL_KEY_Msk (_UINT32_(0xFF) << PAC_WRCTRL_KEY_Pos) …36 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & (_UINT32_(value) << PAC_WRCTRL_…37 #define PAC_WRCTRL_KEY_OFF_Val _UINT32_(0x0) …38 #define PAC_WRCTRL_KEY_CLR_Val _UINT32_(0x1) …39 #define PAC_WRCTRL_KEY_SET_Val _UINT32_(0x2) …[all …]
29 #define ICM_RADDR_Msk _UINT32_(0x00000000) …33 #define ICM_RCFG_RESETVALUE _UINT32_(0x00) …35 #define ICM_RCFG_CDWBN_Pos _UINT32_(0) …36 #define ICM_RCFG_CDWBN_Msk (_UINT32_(0x1) << ICM_RCFG_CDWBN_Pos) …37 #define ICM_RCFG_CDWBN(value) (ICM_RCFG_CDWBN_Msk & (_UINT32_(value) << ICM_RCFG_CD…38 #define ICM_RCFG_CDWBN_WRBA_Val _UINT32_(0x0) …39 #define ICM_RCFG_CDWBN_COMP_Val _UINT32_(0x1) …42 #define ICM_RCFG_WRAP_Pos _UINT32_(1) …43 #define ICM_RCFG_WRAP_Msk (_UINT32_(0x1) << ICM_RCFG_WRAP_Pos) …44 #define ICM_RCFG_WRAP(value) (ICM_RCFG_WRAP_Msk & (_UINT32_(value) << ICM_RCFG_WRA…[all …]
92 #define MCLK_AHBMASK_RESETVALUE _UINT32_(0xFFFFFF) …94 #define MCLK_AHBMASK_HPB0_Pos _UINT32_(0) …95 #define MCLK_AHBMASK_HPB0_Msk (_UINT32_(0x1) << MCLK_AHBMASK_HPB0_Pos) …96 #define MCLK_AHBMASK_HPB0(value) (MCLK_AHBMASK_HPB0_Msk & (_UINT32_(value) << MCLK_AHB…97 #define MCLK_AHBMASK_HPB1_Pos _UINT32_(1) …98 #define MCLK_AHBMASK_HPB1_Msk (_UINT32_(0x1) << MCLK_AHBMASK_HPB1_Pos) …99 #define MCLK_AHBMASK_HPB1(value) (MCLK_AHBMASK_HPB1_Msk & (_UINT32_(value) << MCLK_AHB…100 #define MCLK_AHBMASK_HPB2_Pos _UINT32_(2) …101 #define MCLK_AHBMASK_HPB2_Msk (_UINT32_(0x1) << MCLK_AHBMASK_HPB2_Pos) …102 #define MCLK_AHBMASK_HPB2(value) (MCLK_AHBMASK_HPB2_Msk & (_UINT32_(value) << MCLK_AHB…[all …]
29 #define QSPI_CTRLA_RESETVALUE _UINT32_(0x00) …31 #define QSPI_CTRLA_SWRST_Pos _UINT32_(0) …32 #define QSPI_CTRLA_SWRST_Msk (_UINT32_(0x1) << QSPI_CTRLA_SWRST_Pos) …33 #define QSPI_CTRLA_SWRST(value) (QSPI_CTRLA_SWRST_Msk & (_UINT32_(value) << QSPI_CTRL…34 #define QSPI_CTRLA_ENABLE_Pos _UINT32_(1) …35 #define QSPI_CTRLA_ENABLE_Msk (_UINT32_(0x1) << QSPI_CTRLA_ENABLE_Pos) …36 #define QSPI_CTRLA_ENABLE(value) (QSPI_CTRLA_ENABLE_Msk & (_UINT32_(value) << QSPI_CTR…37 #define QSPI_CTRLA_LASTXFER_Pos _UINT32_(24) …38 #define QSPI_CTRLA_LASTXFER_Msk (_UINT32_(0x1) << QSPI_CTRLA_LASTXFER_Pos) …39 #define QSPI_CTRLA_LASTXFER(value) (QSPI_CTRLA_LASTXFER_Msk & (_UINT32_(value) << QSPI_C…[all …]
